1144411Sscottl/* 2247443Sdelphij******************************************************************************** 3247443Sdelphij** OS : FreeBSD 4144411Sscottl** FILE NAME : arcmsr.h 5210358Sdelphij** BY : Erich Chen, Ching Huang 6144411Sscottl** Description: SCSI RAID Device Driver for 7247443Sdelphij** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8247443Sdelphij** SATA/SAS RAID HOST Adapter 9247443Sdelphij******************************************************************************** 10247443Sdelphij******************************************************************************** 11247443Sdelphij** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 12165155Sscottl** 13144411Sscottl** Redistribution and use in source and binary forms,with or without 14144411Sscottl** modification,are permitted provided that the following conditions 15144411Sscottl** are met: 16144411Sscottl** 1. Redistributions of source code must retain the above copyright 17144411Sscottl** notice,this list of conditions and the following disclaimer. 18144411Sscottl** 2. Redistributions in binary form must reproduce the above copyright 19144411Sscottl** notice,this list of conditions and the following disclaimer in the 20144411Sscottl** documentation and/or other materials provided with the distribution. 21144411Sscottl** 3. The name of the author may not be used to endorse or promote products 22144411Sscottl** derived from this software without specific prior written permission. 23144411Sscottl** 24144411Sscottl** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25144411Sscottl** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES 26144411Sscottl** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27144411Sscottl** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, 28144411Sscottl** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 29144411Sscottl** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30144411Sscottl** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 31144411Sscottl** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT 32144411Sscottl**(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 33144411Sscottl** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34144411Sscottl************************************************************************** 35165155Sscottl* $FreeBSD$ 36144411Sscottl*/ 37215234Sdelphij#define ARCMSR_SCSI_INITIATOR_ID 255 38215234Sdelphij#define ARCMSR_DEV_SECTOR_SIZE 512 39215234Sdelphij#define ARCMSR_MAX_XFER_SECTORS 4096 40215234Sdelphij#define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/ 41215234Sdelphij#define ARCMSR_MAX_TARGETLUN 8 /*8*/ 42215234Sdelphij#define ARCMSR_MAX_CHIPTYPE_NUM 4 43215234Sdelphij#define ARCMSR_MAX_OUTSTANDING_CMD 256 44244406Sdelphij#define ARCMSR_MAX_START_JOB 256 45215234Sdelphij#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 46220403Sdelphij#define ARCMSR_MAX_FREESRB_NUM 384 47215234Sdelphij#define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 48215234Sdelphij#define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 49215234Sdelphij#define ARCMSR_MAX_ADAPTER 4 50215234Sdelphij#define ARCMSR_RELEASE_SIMQ_LEVEL 230 51215234Sdelphij#define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */ 52244406Sdelphij#define ARCMSR_MAX_HBD_POSTQUEUE 256 53240079Sdelphij#define ARCMSR_TIMEOUT_DELAY 60 /* in sec */ 54144411Sscottl/* 55144411Sscottl********************************************************************* 56144411Sscottl*/ 57144411Sscottl#ifndef TRUE 58174451Sscottl #define TRUE 1 59144411Sscottl#endif 60144411Sscottl#ifndef FALSE 61174451Sscottl #define FALSE 0 62144411Sscottl#endif 63165155Sscottl#ifndef INTR_ENTROPY 64174451Sscottl # define INTR_ENTROPY 0 65165155Sscottl#endif 66165155Sscottl 67165155Sscottl#ifndef offsetof 68165155Sscottl #define offsetof(type, member) ((size_t)(&((type *)0)->member)) 69165155Sscottl#endif 70244406Sdelphij 71244406Sdelphij#if __FreeBSD_version >= 500005 72244406Sdelphij #define ARCMSR_LOCK_INIT(l, s) mtx_init(l, s, NULL, MTX_DEF) 73244406Sdelphij #define ARCMSR_LOCK_DESTROY(l) mtx_destroy(l) 74244406Sdelphij #define ARCMSR_LOCK_ACQUIRE(l) mtx_lock(l) 75244406Sdelphij #define ARCMSR_LOCK_RELEASE(l) mtx_unlock(l) 76244406Sdelphij #define ARCMSR_LOCK_TRY(l) mtx_trylock(l) 77244406Sdelphij #define arcmsr_htole32(x) htole32(x) 78244406Sdelphij typedef struct mtx arcmsr_lock_t; 79244406Sdelphij#else 80244406Sdelphij #define ARCMSR_LOCK_INIT(l, s) simple_lock_init(l) 81244406Sdelphij #define ARCMSR_LOCK_DESTROY(l) 82244406Sdelphij #define ARCMSR_LOCK_ACQUIRE(l) simple_lock(l) 83244406Sdelphij #define ARCMSR_LOCK_RELEASE(l) simple_unlock(l) 84244406Sdelphij #define ARCMSR_LOCK_TRY(l) simple_lock_try(l) 85244406Sdelphij #define arcmsr_htole32(x) (x) 86244406Sdelphij typedef struct simplelock arcmsr_lock_t; 87244406Sdelphij#endif 88244406Sdelphij 89144411Sscottl/* 90144411Sscottl********************************************************************************** 91144411Sscottl** 92144411Sscottl********************************************************************************** 93144411Sscottl*/ 94215234Sdelphij#define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 95215234Sdelphij#define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 96215234Sdelphij#define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 97215234Sdelphij#define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 98215234Sdelphij#define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 99215234Sdelphij#define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 100215234Sdelphij#define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */ 101215234Sdelphij#define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ 102215234Sdelphij#define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 103210358Sdelphij#define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */ 104244406Sdelphij#define PCI_DEVICE_ID_ARECA_1214 0x1214 /* Device ID */ 105215234Sdelphij#define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 106210358Sdelphij#define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */ 107215234Sdelphij#define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 108215234Sdelphij#define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */ 109215234Sdelphij#define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 110215234Sdelphij#define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */ 111215234Sdelphij#define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 112215234Sdelphij#define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 113215234Sdelphij#define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 114215234Sdelphij#define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 115215234Sdelphij#define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 116215234Sdelphij#define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 117210358Sdelphij#define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */ 118144411Sscottl 119240079Sdelphij#define ARECA_SUB_DEV_ID_1880 0x1880 /* Subsystem Device ID */ 120240079Sdelphij#define ARECA_SUB_DEV_ID_1882 0x1882 /* Subsystem Device ID */ 121240079Sdelphij#define ARECA_SUB_DEV_ID_1212 0x1212 /* Subsystem Device ID */ 122240079Sdelphij#define ARECA_SUB_DEV_ID_1213 0x1213 /* Subsystem Device ID */ 123240079Sdelphij#define ARECA_SUB_DEV_ID_1222 0x1222 /* Subsystem Device ID */ 124240079Sdelphij#define ARECA_SUB_DEV_ID_1223 0x1223 /* Subsystem Device ID */ 125240079Sdelphij 126215234Sdelphij#define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */ 127215234Sdelphij#define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */ 128215234Sdelphij#define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 129215234Sdelphij#define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 130215234Sdelphij#define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 131215234Sdelphij#define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */ 132215234Sdelphij#define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */ 133215234Sdelphij#define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 134210358Sdelphij#define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */ 135240079Sdelphij#define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */ 136244406Sdelphij#define PCIDevVenIDARC1214 0x121417D3 /* Vendor Device ID */ 137215234Sdelphij#define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 138210358Sdelphij#define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */ 139240079Sdelphij#define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */ 140215234Sdelphij#define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 141215234Sdelphij#define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */ 142215234Sdelphij#define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 143215234Sdelphij#define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */ 144215234Sdelphij#define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ 145215234Sdelphij#define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */ 146215234Sdelphij#define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */ 147215234Sdelphij#define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */ 148215234Sdelphij#define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */ 149215234Sdelphij#define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */ 150210358Sdelphij#define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */ 151240079Sdelphij#define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */ 152144411Sscottl 153165155Sscottl#ifndef PCIR_BARS 154165155Sscottl #define PCIR_BARS 0x10 155165155Sscottl #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 156165155Sscottl#endif 157165155Sscottl 158215234Sdelphij#define PCI_BASE_ADDR0 0x10 159215234Sdelphij#define PCI_BASE_ADDR1 0x14 160215234Sdelphij#define PCI_BASE_ADDR2 0x18 161215234Sdelphij#define PCI_BASE_ADDR3 0x1C 162215234Sdelphij#define PCI_BASE_ADDR4 0x20 163215234Sdelphij#define PCI_BASE_ADDR5 0x24 164144411Sscottl/* 165144411Sscottl********************************************************************************** 166144411Sscottl** 167144411Sscottl********************************************************************************** 168144411Sscottl*/ 169215234Sdelphij#define ARCMSR_SCSICMD_IOCTL 0x77 170215234Sdelphij#define ARCMSR_CDEVSW_IOCTL 0x88 171215234Sdelphij#define ARCMSR_MESSAGE_FAIL 0x0001 172215234Sdelphij#define ARCMSR_MESSAGE_SUCCESS 0x0000 173144411Sscottl/* 174144411Sscottl********************************************************************************** 175144411Sscottl** 176144411Sscottl********************************************************************************** 177144411Sscottl*/ 178215234Sdelphij#define arcmsr_ccbsrb_ptr spriv_ptr0 179215234Sdelphij#define arcmsr_ccbacb_ptr spriv_ptr1 180215234Sdelphij#define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16) 181215234Sdelphij#define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff) 182165155Sscottl#define get_min(x,y) ((x) < (y) ? (x) : (y)) 183165155Sscottl#define get_max(x,y) ((x) < (y) ? (y) : (x)) 184144411Sscottl/* 185244406Sdelphij************************************************************************** 186244406Sdelphij************************************************************************** 187244406Sdelphij*/ 188244406Sdelphij#define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r)) 189244406Sdelphij#define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d) 190244406Sdelphij/* 191165155Sscottl********************************************************************************** 192244406Sdelphij** IOCTL CONTROL Mail Box 193165155Sscottl********************************************************************************** 194144411Sscottl*/ 195210358Sdelphijstruct CMD_MESSAGE { 196210358Sdelphij u_int32_t HeaderLength; 197210358Sdelphij u_int8_t Signature[8]; 198210358Sdelphij u_int32_t Timeout; 199210358Sdelphij u_int32_t ControlCode; 200210358Sdelphij u_int32_t ReturnCode; 201210358Sdelphij u_int32_t Length; 202210358Sdelphij}; 203210358Sdelphij 204210358Sdelphijstruct CMD_MESSAGE_FIELD { 205210358Sdelphij struct CMD_MESSAGE cmdmessage; /* ioctl header */ 206210358Sdelphij u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */ 207210358Sdelphij}; 208210358Sdelphij 209210358Sdelphij/************************************************************************/ 210210358Sdelphij/************************************************************************/ 211210358Sdelphij 212144411Sscottl#define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 213144411Sscottl#define ARCMSR_IOP_ERROR_VENDORID 0x0002 214144411Sscottl#define ARCMSR_IOP_ERROR_DEVICEID 0x0002 215144411Sscottl#define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 216144411Sscottl#define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 217144411Sscottl#define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 218144411Sscottl#define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 219144411Sscottl#define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 220144411Sscottl#define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 221144411Sscottl#define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 222144411Sscottl#define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 223210358Sdelphij 224144411Sscottl/*DeviceType*/ 225144411Sscottl#define ARECA_SATA_RAID 0x90000000 226210358Sdelphij 227144411Sscottl/*FunctionCode*/ 228144411Sscottl#define FUNCTION_READ_RQBUFFER 0x0801 229144411Sscottl#define FUNCTION_WRITE_WQBUFFER 0x0802 230144411Sscottl#define FUNCTION_CLEAR_RQBUFFER 0x0803 231144411Sscottl#define FUNCTION_CLEAR_WQBUFFER 0x0804 232144411Sscottl#define FUNCTION_CLEAR_ALLQBUFFER 0x0805 233165155Sscottl#define FUNCTION_REQUEST_RETURNCODE_3F 0x0806 234144411Sscottl#define FUNCTION_SAY_HELLO 0x0807 235165155Sscottl#define FUNCTION_SAY_GOODBYE 0x0808 236165155Sscottl#define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 237165155Sscottl/* 238165155Sscottl************************************************************************ 239244406Sdelphij** IOCTL CONTROL CODE 240165155Sscottl************************************************************************ 241165155Sscottl*/ 242144411Sscottl/* ARECA IO CONTROL CODE*/ 243165155Sscottl#define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD) 244165155Sscottl#define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD) 245165155Sscottl#define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD) 246165155Sscottl#define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD) 247165155Sscottl#define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD) 248165155Sscottl#define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD) 249165155Sscottl#define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD) 250165155Sscottl#define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD) 251165155Sscottl#define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD) 252210358Sdelphij 253144411Sscottl/* ARECA IOCTL ReturnCode */ 254215234Sdelphij#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 255215234Sdelphij#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 256215234Sdelphij#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 257210358Sdelphij#define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088 258144411Sscottl/* 259174451Sscottl************************************************************************ 260244406Sdelphij** SPEC. for Areca HBA adapter 261244406Sdelphij************************************************************************ 262244406Sdelphij*/ 263244406Sdelphij/* signature of set and get firmware config */ 264244406Sdelphij#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 265244406Sdelphij#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 266244406Sdelphij/* message code of inbound message register */ 267244406Sdelphij#define ARCMSR_INBOUND_MESG0_NOP 0x00000000 268244406Sdelphij#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 269244406Sdelphij#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 270244406Sdelphij#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 271244406Sdelphij#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 272244406Sdelphij#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 273244406Sdelphij#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 274244406Sdelphij#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 275244406Sdelphij#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 276244406Sdelphij/* doorbell interrupt generator */ 277244406Sdelphij#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 278244406Sdelphij#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 279244406Sdelphij#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 280244406Sdelphij#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 281244406Sdelphij/* srb areca cdb flag */ 282244406Sdelphij#define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 283244406Sdelphij#define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 284244406Sdelphij#define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 285244406Sdelphij#define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 286244406Sdelphij#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000 287244406Sdelphij#define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001 288244406Sdelphij/* outbound firmware ok */ 289244406Sdelphij#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 290244406Sdelphij 291244406Sdelphij#define ARCMSR_ARC1680_BUS_RESET 0x00000003 292244406Sdelphij/* 293244406Sdelphij************************************************************************ 294174451Sscottl** SPEC. for Areca HBB adapter 295174451Sscottl************************************************************************ 296174451Sscottl*/ 297174451Sscottl/* ARECA HBB COMMAND for its FIRMWARE */ 298174451Sscottl#define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */ 299174451Sscottl#define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 300174451Sscottl#define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */ 301174451Sscottl#define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 302210358Sdelphij 303174451Sscottl/* ARECA FLAG LANGUAGE */ 304174451Sscottl#define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 305174451Sscottl#define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */ 306174451Sscottl#define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 307174451Sscottl#define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 308174451Sscottl 309174451Sscottl#define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 310174451Sscottl#define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 311174451Sscottl#define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 312174451Sscottl 313174451Sscottl#define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 314174451Sscottl#define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 315174451Sscottl#define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 316174451Sscottl#define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 317174451Sscottl#define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 318174451Sscottl#define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 319174451Sscottl#define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 320174451Sscottl#define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 321174451Sscottl#define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 322174451Sscottl#define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 323174451Sscottl 324174451Sscottl#define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 325174451Sscottl#define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */ 326174451Sscottl#define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 327174451Sscottl#define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 328174451Sscottl#define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */ 329174451Sscottl 330174451Sscottl/* data tunnel buffer between user space program and its firmware */ 331174451Sscottl#define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */ 332174451Sscottl#define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */ 333174451Sscottl#define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */ 334174451Sscottl#define ARCMSR_HBB_BASE0_OFFSET 0x00000010 335174451Sscottl#define ARCMSR_HBB_BASE1_OFFSET 0x00000018 336174451Sscottl#define ARCMSR_HBB_BASE0_LEN 0x00021000 337174451Sscottl#define ARCMSR_HBB_BASE1_LEN 0x00010000 338174451Sscottl/* 339210358Sdelphij************************************************************************ 340210358Sdelphij** SPEC. for Areca HBC adapter 341210358Sdelphij************************************************************************ 342210358Sdelphij*/ 343210358Sdelphij#define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 344210358Sdelphij#define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 345210358Sdelphij/* Host Interrupt Mask */ 346210358Sdelphij#define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/ 347210358Sdelphij#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/ 348210358Sdelphij#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/ 349210358Sdelphij#define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */ 350210358Sdelphij/* Host Interrupt Status */ 351210358Sdelphij#define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 352210358Sdelphij /* 353210358Sdelphij ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 354210358Sdelphij ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). 355210358Sdelphij */ 356210358Sdelphij#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 357210358Sdelphij /* 358210358Sdelphij ** Set if Outbound Doorbell register bits 30:1 have a non-zero 359210358Sdelphij ** value. This bit clears only when Outbound Doorbell bits 360210358Sdelphij ** 30:1 are ALL clear. Only a write to the Outbound Doorbell 361210358Sdelphij ** Clear register clears bits in the Outbound Doorbell register. 362210358Sdelphij */ 363210358Sdelphij#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 364210358Sdelphij /* 365210358Sdelphij ** Set whenever the Outbound Post List Producer/Consumer 366210358Sdelphij ** Register (FIFO) is not empty. It clears when the Outbound 367210358Sdelphij ** Post List FIFO is empty. 368210358Sdelphij */ 369210358Sdelphij#define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 370210358Sdelphij /* 371210358Sdelphij ** This bit indicates a SAS interrupt from a source external to 372210358Sdelphij ** the PCIe core. This bit is not maskable. 373210358Sdelphij */ 374210358Sdelphij/* DoorBell*/ 375210358Sdelphij#define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002/**/ 376210358Sdelphij#define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004/**/ 377210358Sdelphij#define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008/*inbound message 0 ready*/ 378210358Sdelphij#define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request completed in a time*/ 379210358Sdelphij#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/ 380210358Sdelphij#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr door bell clear*/ 381210358Sdelphij#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/ 382210358Sdelphij#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/ 383210358Sdelphij#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/ 384210358Sdelphij#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/ 385210358Sdelphij#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/ 386244406Sdelphij#define ARCMSR_HBCMU_RESET_ADAPTER 0x00000024 387244406Sdelphij#define ARCMSR_HBCMU_DiagWrite_ENABLE 0x00000080 388210358Sdelphij 389210358Sdelphij/* 390244406Sdelphij************************************************************************ 391244406Sdelphij** SPEC. for Areca HBD adapter 392244406Sdelphij************************************************************************ 393244406Sdelphij*/ 394244406Sdelphij#define ARCMSR_HBDMU_CHIP_ID 0x00004 395244406Sdelphij#define ARCMSR_HBDMU_CPU_MEMORY_CONFIGURATION 0x00008 396244406Sdelphij#define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK 0x00034 397244406Sdelphij#define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS 0x00200 398244406Sdelphij#define ARCMSR_HBDMU_PCIE_F0_INTERRUPT_ENABLE 0x0020C 399244406Sdelphij#define ARCMSR_HBDMU_INBOUND_MESSAGE0 0x00400 400244406Sdelphij#define ARCMSR_HBDMU_INBOUND_MESSAGE1 0x00404 401244406Sdelphij#define ARCMSR_HBDMU_OUTBOUND_MESSAGE0 0x00420 402244406Sdelphij#define ARCMSR_HBDMU_OUTBOUND_MESSAGE1 0x00424 403244406Sdelphij#define ARCMSR_HBDMU_INBOUND_DOORBELL 0x00460 404244406Sdelphij#define ARCMSR_HBDMU_OUTBOUND_DOORBELL 0x00480 405244406Sdelphij#define ARCMSR_HBDMU_OUTBOUND_DOORBELL_ENABLE 0x00484 406244406Sdelphij#define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW 0x01000 407244406Sdelphij#define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH 0x01004 408244406Sdelphij#define ARCMSR_HBDMU_INBOUND_LIST_WRITE_POINTER 0x01018 409244406Sdelphij#define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW 0x01060 410244406Sdelphij#define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_HIGH 0x01064 411244406Sdelphij#define ARCMSR_HBDMU_OUTBOUND_LIST_COPY_POINTER 0x0106C 412244406Sdelphij#define ARCMSR_HBDMU_OUTBOUND_LIST_READ_POINTER 0x01070 413244406Sdelphij#define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_CAUSE 0x01088 414244406Sdelphij#define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_ENABLE 0x0108C 415244406Sdelphij 416244406Sdelphij#define ARCMSR_HBDMU_MESSAGE_WBUFFER 0x02000 417244406Sdelphij#define ARCMSR_HBDMU_MESSAGE_RBUFFER 0x02100 418244406Sdelphij#define ARCMSR_HBDMU_MESSAGE_RWBUFFER 0x02200 419244406Sdelphij 420244406Sdelphij#define ARCMSR_HBDMU_ISR_THROTTLING_LEVEL 16 421244406Sdelphij#define ARCMSR_HBDMU_ISR_MAX_DONE_QUEUE 20 422244406Sdelphij 423244406Sdelphij/* Host Interrupt Mask */ 424244406Sdelphij#define ARCMSR_HBDMU_ALL_INT_ENABLE 0x00001010 /* enable all ISR */ 425244406Sdelphij#define ARCMSR_HBDMU_ALL_INT_DISABLE 0x00000000 /* disable all ISR */ 426244406Sdelphij 427244406Sdelphij/* Host Interrupt Status */ 428244406Sdelphij#define ARCMSR_HBDMU_OUTBOUND_INT 0x00001010 429244406Sdelphij#define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT 0x00001000 430244406Sdelphij#define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT 0x00000010 431244406Sdelphij 432244406Sdelphij/* DoorBell*/ 433244406Sdelphij#define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY 0x00000001 434244406Sdelphij#define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ 0x00000002 435244406Sdelphij 436244406Sdelphij#define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK 0x00000001 437244406Sdelphij#define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK 0x00000002 438244406Sdelphij 439244406Sdelphij/*outbound message 0 ready*/ 440244406Sdelphij#define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE 0x02000000 441244406Sdelphij 442244406Sdelphij#define ARCMSR_HBDMU_F0_DOORBELL_CAUSE 0x02000003 443244406Sdelphij 444244406Sdelphij/*outbound message cmd isr door bell clear*/ 445244406Sdelphij#define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000 446244406Sdelphij 447244406Sdelphij/*outbound list */ 448244406Sdelphij#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001 449244406Sdelphij#define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001 450244406Sdelphij 451244406Sdelphij/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 452244406Sdelphij#define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000 453244406Sdelphij/* 454244406Sdelphij********************************************************************* 455244406Sdelphij** Message Unit structure 456244406Sdelphij********************************************************************* 457244406Sdelphij*/ 458244406Sdelphijstruct HBA_MessageUnit 459244406Sdelphij{ 460244406Sdelphij u_int32_t resrved0[4]; /*0000 000F*/ 461244406Sdelphij u_int32_t inbound_msgaddr0; /*0010 0013*/ 462244406Sdelphij u_int32_t inbound_msgaddr1; /*0014 0017*/ 463244406Sdelphij u_int32_t outbound_msgaddr0; /*0018 001B*/ 464244406Sdelphij u_int32_t outbound_msgaddr1; /*001C 001F*/ 465244406Sdelphij u_int32_t inbound_doorbell; /*0020 0023*/ 466244406Sdelphij u_int32_t inbound_intstatus; /*0024 0027*/ 467244406Sdelphij u_int32_t inbound_intmask; /*0028 002B*/ 468244406Sdelphij u_int32_t outbound_doorbell; /*002C 002F*/ 469244406Sdelphij u_int32_t outbound_intstatus; /*0030 0033*/ 470244406Sdelphij u_int32_t outbound_intmask; /*0034 0037*/ 471244406Sdelphij u_int32_t reserved1[2]; /*0038 003F*/ 472244406Sdelphij u_int32_t inbound_queueport; /*0040 0043*/ 473244406Sdelphij u_int32_t outbound_queueport; /*0044 0047*/ 474244406Sdelphij u_int32_t reserved2[2]; /*0048 004F*/ 475244406Sdelphij u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ 476244406Sdelphij u_int32_t reserved4[128]; /*0800 09FF 128*/ 477244406Sdelphij u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/ 478244406Sdelphij u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 479244406Sdelphij u_int32_t reserved5[32]; /*0E80 0EFF 32*/ 480244406Sdelphij u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 481244406Sdelphij u_int32_t reserved6[32]; /*0F80 0FFF 32*/ 482244406Sdelphij}; 483244406Sdelphij/* 484244406Sdelphij********************************************************************* 485244406Sdelphij** 486244406Sdelphij********************************************************************* 487244406Sdelphij*/ 488244406Sdelphijstruct HBB_DOORBELL 489244406Sdelphij{ 490244406Sdelphij u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */ 491244406Sdelphij u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */ 492244406Sdelphij u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */ 493244406Sdelphij u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */ 494244406Sdelphij u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */ 495244406Sdelphij}; 496244406Sdelphij/* 497244406Sdelphij********************************************************************* 498244406Sdelphij** 499244406Sdelphij********************************************************************* 500244406Sdelphij*/ 501244406Sdelphijstruct HBB_RWBUFFER 502244406Sdelphij{ 503244406Sdelphij u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */ 504244406Sdelphij u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */ 505244406Sdelphij u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */ 506244406Sdelphij u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/ 507244406Sdelphij u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ 508244406Sdelphij}; 509244406Sdelphij/* 510244406Sdelphij********************************************************************* 511244406Sdelphij** 512244406Sdelphij********************************************************************* 513244406Sdelphij*/ 514244406Sdelphijstruct HBB_MessageUnit 515244406Sdelphij{ 516244406Sdelphij u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */ 517244406Sdelphij u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */ 518244406Sdelphij int32_t postq_index; /* post queue index */ 519244406Sdelphij int32_t doneq_index; /* done queue index */ 520244406Sdelphij struct HBB_DOORBELL *hbb_doorbell; 521244406Sdelphij struct HBB_RWBUFFER *hbb_rwbuffer; 522244406Sdelphij}; 523244406Sdelphij 524244406Sdelphij/* 525244406Sdelphij********************************************************************* 526244406Sdelphij** 527244406Sdelphij********************************************************************* 528244406Sdelphij*/ 529244406Sdelphijstruct HBC_MessageUnit { 530244406Sdelphij u_int32_t message_unit_status; /*0000 0003*/ 531244406Sdelphij u_int32_t slave_error_attribute; /*0004 0007*/ 532244406Sdelphij u_int32_t slave_error_address; /*0008 000B*/ 533244406Sdelphij u_int32_t posted_outbound_doorbell; /*000C 000F*/ 534244406Sdelphij u_int32_t master_error_attribute; /*0010 0013*/ 535244406Sdelphij u_int32_t master_error_address_low; /*0014 0017*/ 536244406Sdelphij u_int32_t master_error_address_high; /*0018 001B*/ 537244406Sdelphij u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/ 538244406Sdelphij u_int32_t inbound_doorbell; /*0020 0023*/ 539244406Sdelphij u_int32_t diagnostic_rw_data; /*0024 0027*/ 540244406Sdelphij u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 541244406Sdelphij u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 542244406Sdelphij u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 543244406Sdelphij u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 544244406Sdelphij u_int32_t dcr_data; /*0038 003B*/ 545244406Sdelphij u_int32_t dcr_address; /*003C 003F*/ 546244406Sdelphij u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 547244406Sdelphij u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 548244406Sdelphij u_int32_t hcb_pci_address_low; /*0048 004B*/ 549244406Sdelphij u_int32_t hcb_pci_address_high; /*004C 004F*/ 550244406Sdelphij u_int32_t iop_int_status; /*0050 0053*/ 551244406Sdelphij u_int32_t iop_int_mask; /*0054 0057*/ 552244406Sdelphij u_int32_t iop_inbound_queue_port; /*0058 005B*/ 553244406Sdelphij u_int32_t iop_outbound_queue_port; /*005C 005F*/ 554244406Sdelphij u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/ 555244406Sdelphij u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/ 556244406Sdelphij u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/ 557244406Sdelphij u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/ 558244406Sdelphij u_int32_t inbound_doorbell_clear; /*0070 0073*/ 559244406Sdelphij u_int32_t i2o_message_unit_control; /*0074 0077*/ 560244406Sdelphij u_int32_t last_used_message_source_address_low; /*0078 007B*/ 561244406Sdelphij u_int32_t last_used_message_source_address_high; /*007C 007F*/ 562244406Sdelphij u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/ 563244406Sdelphij u_int32_t message_dest_address_index; /*0090 0093*/ 564244406Sdelphij u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 565244406Sdelphij u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 566244406Sdelphij u_int32_t outbound_doorbell; /*009C 009F*/ 567244406Sdelphij u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 568244406Sdelphij u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/ 569244406Sdelphij u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/ 570244406Sdelphij u_int32_t reserved0; /*00AC 00AF*/ 571244406Sdelphij u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 572244406Sdelphij u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 573244406Sdelphij u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 574244406Sdelphij u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 575244406Sdelphij u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 576244406Sdelphij u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 577244406Sdelphij u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 578244406Sdelphij u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 579244406Sdelphij u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 580244406Sdelphij u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 581244406Sdelphij u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 582244406Sdelphij u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 583244406Sdelphij u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/ 584244406Sdelphij u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/ 585244406Sdelphij u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/ 586244406Sdelphij u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/ 587244406Sdelphij u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/ 588244406Sdelphij u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/ 589244406Sdelphij u_int32_t host_diagnostic; /*00F8 00FB*/ 590244406Sdelphij u_int32_t write_sequence; /*00FC 00FF*/ 591244406Sdelphij u_int32_t reserved1[34]; /*0100 0187*/ 592244406Sdelphij u_int32_t reserved2[1950]; /*0188 1FFF*/ 593244406Sdelphij u_int32_t message_wbuffer[32]; /*2000 207F*/ 594244406Sdelphij u_int32_t reserved3[32]; /*2080 20FF*/ 595244406Sdelphij u_int32_t message_rbuffer[32]; /*2100 217F*/ 596244406Sdelphij u_int32_t reserved4[32]; /*2180 21FF*/ 597244406Sdelphij u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 598244406Sdelphij}; 599244406Sdelphij/* 600244406Sdelphij********************************************************************* 601244406Sdelphij** 602244406Sdelphij********************************************************************* 603244406Sdelphij*/ 604244406Sdelphijstruct InBound_SRB { 605244406Sdelphij uint32_t addressLow; //pointer to SRB block 606244406Sdelphij uint32_t addressHigh; 607244406Sdelphij uint32_t length; // in DWORDs 608244406Sdelphij uint32_t reserved0; 609244406Sdelphij}; 610244406Sdelphij 611244406Sdelphijstruct OutBound_SRB { 612244406Sdelphij uint32_t addressLow; //pointer to SRB block 613244406Sdelphij uint32_t addressHigh; 614244406Sdelphij}; 615244406Sdelphij 616244406Sdelphijstruct HBD_MessageUnit { 617244406Sdelphij uint32_t reserved0; 618244406Sdelphij uint32_t chip_id; //0x0004 619244406Sdelphij uint32_t cpu_mem_config; //0x0008 620244406Sdelphij uint32_t reserved1[10]; //0x000C 621244406Sdelphij uint32_t i2o_host_interrupt_mask; //0x0034 622244406Sdelphij uint32_t reserved2[114]; //0x0038 623244406Sdelphij uint32_t host_int_status; //0x0200 624244406Sdelphij uint32_t host_int_enable; //0x0204 625244406Sdelphij uint32_t reserved3[1]; //0x0208 626244406Sdelphij uint32_t pcief0_int_enable; //0x020C 627244406Sdelphij uint32_t reserved4[124]; //0x0210 628244406Sdelphij uint32_t inbound_msgaddr0; //0x0400 629244406Sdelphij uint32_t inbound_msgaddr1; //0x0404 630244406Sdelphij uint32_t reserved5[6]; //0x0408 631244406Sdelphij uint32_t outbound_msgaddr0; //0x0420 632244406Sdelphij uint32_t outbound_msgaddr1; //0x0424 633244406Sdelphij uint32_t reserved6[14]; //0x0428 634244406Sdelphij uint32_t inbound_doorbell; //0x0460 635244406Sdelphij uint32_t reserved7[7]; //0x0464 636244406Sdelphij uint32_t outbound_doorbell; //0x0480 637244406Sdelphij uint32_t outbound_doorbell_enable; //0x0484 638244406Sdelphij uint32_t reserved8[734]; //0x0488 639244406Sdelphij uint32_t inboundlist_base_low; //0x1000 640244406Sdelphij uint32_t inboundlist_base_high; //0x1004 641244406Sdelphij uint32_t reserved9[4]; //0x1008 642244406Sdelphij uint32_t inboundlist_write_pointer; //0x1018 643244406Sdelphij uint32_t inboundlist_read_pointer; //0x101C 644244406Sdelphij uint32_t reserved10[16]; //0x1020 645244406Sdelphij uint32_t outboundlist_base_low; //0x1060 646244406Sdelphij uint32_t outboundlist_base_high; //0x1064 647244406Sdelphij uint32_t reserved11; //0x1068 648244406Sdelphij uint32_t outboundlist_copy_pointer; //0x106C 649244406Sdelphij uint32_t outboundlist_read_pointer; //0x1070 0x1072 650244406Sdelphij uint32_t reserved12[5]; //0x1074 651244406Sdelphij uint32_t outboundlist_interrupt_cause; //0x1088 652244406Sdelphij uint32_t outboundlist_interrupt_enable; //0x108C 653244406Sdelphij uint32_t reserved13[988]; //0x1090 654244406Sdelphij uint32_t message_wbuffer[32]; //0x2000 655244406Sdelphij uint32_t reserved14[32]; //0x2080 656244406Sdelphij uint32_t message_rbuffer[32]; //0x2100 657244406Sdelphij uint32_t reserved15[32]; //0x2180 658244406Sdelphij uint32_t msgcode_rwbuffer[256]; //0x2200 659244406Sdelphij}; 660244406Sdelphij 661244406Sdelphijstruct HBD_MessageUnit0 { 662244406Sdelphij struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE]; 663244406Sdelphij struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1]; 664244406Sdelphij uint16_t postq_index; 665244406Sdelphij uint16_t doneq_index; 666244406Sdelphij struct HBD_MessageUnit *phbdmu; 667244406Sdelphij}; 668244406Sdelphij 669244406Sdelphij/* 670244406Sdelphij********************************************************************* 671244406Sdelphij** 672244406Sdelphij********************************************************************* 673244406Sdelphij*/ 674244406Sdelphijstruct MessageUnit_UNION 675244406Sdelphij{ 676244406Sdelphij union { 677244406Sdelphij struct HBA_MessageUnit hbamu; 678244406Sdelphij struct HBB_MessageUnit hbbmu; 679244406Sdelphij struct HBC_MessageUnit hbcmu; 680244406Sdelphij struct HBD_MessageUnit0 hbdmu; 681244406Sdelphij } muu; 682244406Sdelphij}; 683244406Sdelphij/* 684144411Sscottl************************************************************* 685144411Sscottl** structure for holding DMA address data 686144411Sscottl************************************************************* 687144411Sscottl*/ 688144411Sscottl#define IS_SG64_ADDR 0x01000000 /* bit24 */ 689144411Sscottl/* 690144411Sscottl************************************************************************************************ 691144411Sscottl** ARECA FIRMWARE SPEC 692144411Sscottl************************************************************************************************ 693144411Sscottl** Usage of IOP331 adapter 694144411Sscottl** (All In/Out is in IOP331's view) 695144411Sscottl** 1. Message 0 --> InitThread message and retrun code 696144411Sscottl** 2. Doorbell is used for RS-232 emulation 697144411Sscottl** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK) 698144411Sscottl** bit1 -- data out has been read (DRIVER DATA READ OK) 699144411Sscottl** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK) 700144411Sscottl** bit1 -- data in has been read (IOP331 DATA READ OK) 701144411Sscottl** 3. Index Memory Usage 702144411Sscottl** offset 0xf00 : for RS232 out (request buffer) 703144411Sscottl** offset 0xe00 : for RS232 in (scratch buffer) 704174451Sscottl** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 705174451Sscottl** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver) 706144411Sscottl** 4. RS-232 emulation 707144411Sscottl** Currently 128 byte buffer is used 708165155Sscottl** 1st u_int32_t : Data length (1--124) 709144411Sscottl** Byte 4--127 : Max 124 bytes of data 710144411Sscottl** 5. PostQ 711144411Sscottl** All SCSI Command must be sent through postQ: 712144411Sscottl** (inbound queue port) Request frame must be 32 bytes aligned 713165155Sscottl** # bit27--bit31 => flag for post ccb 714144411Sscottl** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb 715144411Sscottl** bit31 : 0 : 256 bytes frame 716144411Sscottl** 1 : 512 bytes frame 717144411Sscottl** bit30 : 0 : normal request 718144411Sscottl** 1 : BIOS request 719144411Sscottl** bit29 : reserved 720144411Sscottl** bit28 : reserved 721144411Sscottl** bit27 : reserved 722144411Sscottl** ------------------------------------------------------------------------------- 723144411Sscottl** (outbount queue port) Request reply 724144411Sscottl** # bit27--bit31 => flag for reply 725144411Sscottl** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 726144411Sscottl** bit31 : must be 0 (for this type of reply) 727144411Sscottl** bit30 : reserved for BIOS handshake 728144411Sscottl** bit29 : reserved 729144411Sscottl** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 730144411Sscottl** 1 : Error, error code in AdapStatus/DevStatus/SenseData 731144411Sscottl** bit27 : reserved 732144411Sscottl** 6. BIOS request 733144411Sscottl** All BIOS request is the same with request from PostQ 734144411Sscottl** Except : 735144411Sscottl** Request frame is sent from configuration space 736144411Sscottl** offset: 0x78 : Request Frame (bit30 == 1) 737144411Sscottl** offset: 0x18 : writeonly to generate IRQ to IOP331 738144411Sscottl** Completion of request: 739144411Sscottl** (bit30 == 0, bit28==err flag) 740144411Sscottl** 7. Definition of SGL entry (structure) 741144411Sscottl** 8. Message1 Out - Diag Status Code (????) 742144411Sscottl** 9. Message0 message code : 743144411Sscottl** 0x00 : NOP 744174451Sscottl** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver) 745165155Sscottl** Signature 0x87974060(4) 746165155Sscottl** Request len 0x00000200(4) 747165155Sscottl** numbers of queue 0x00000100(4) 748165155Sscottl** SDRAM Size 0x00000100(4)-->256 MB 749165155Sscottl** IDE Channels 0x00000008(4) 750165155Sscottl** vendor 40 bytes char 751165155Sscottl** model 8 bytes char 752165155Sscottl** FirmVer 16 bytes char 753174451Sscottl** Device Map 16 bytes char 754174451Sscottl** 755174451Sscottl** FirmwareVersion DWORD <== Added for checking of new firmware capability 756174451Sscottl** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 757165155Sscottl** Signature 0x87974063(4) 758144411Sscottl** UPPER32 of Request Frame (4)-->Driver Only 759144411Sscottl** 0x03 : Reset (Abort all queued Command) 760144411Sscottl** 0x04 : Stop Background Activity 761144411Sscottl** 0x05 : Flush Cache 762144411Sscottl** 0x06 : Start Background Activity (re-start if background is halted) 763144411Sscottl** 0x07 : Check If Host Command Pending (Novell May Need This Function) 764174451Sscottl** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331) 765174451Sscottl** byte 0 : 0xaa <-- signature 766174451Sscottl** byte 1 : 0x55 <-- signature 767174451Sscottl** byte 2 : year (04) 768174451Sscottl** byte 3 : month (1..12) 769174451Sscottl** byte 4 : date (1..31) 770174451Sscottl** byte 5 : hour (0..23) 771174451Sscottl** byte 6 : minute (0..59) 772174451Sscottl** byte 7 : second (0..59) 773210358Sdelphij** ********************************************************************************* 774210358Sdelphij** Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter 775210358Sdelphij** ==> Difference from IOP348 776210358Sdelphij** <1> Message Register 0,1 (the same usage) Init Thread message and retrun code 777210358Sdelphij** Inbound Message 0 (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound message code msgcode_rwbuffer (driver send to IOP) 778210358Sdelphij** Inbound Message 1 (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code 779210358Sdelphij** Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code 780210358Sdelphij** Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound message code msgcode_rwbuffer (IOP send to driver) 781210358Sdelphij** <A> use doorbell to generate interrupt 782210358Sdelphij** 783210358Sdelphij** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop) 784210358Sdelphij** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver) 785210358Sdelphij** 786210358Sdelphij** a. Message1: Out - Diag Status Code (????) 787210358Sdelphij** 788210358Sdelphij** b. Message0: message code 789210358Sdelphij** 0x00 : NOP 790210358Sdelphij** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver) 791210358Sdelphij** Signature 0x87974060(4) 792210358Sdelphij** Request len 0x00000200(4) 793210358Sdelphij** numbers of queue 0x00000100(4) 794210358Sdelphij** SDRAM Size 0x00000100(4)-->256 MB 795210358Sdelphij** IDE Channels 0x00000008(4) 796210358Sdelphij** vendor 40 bytes char 797210358Sdelphij** model 8 bytes char 798210358Sdelphij** FirmVer 16 bytes char 799210358Sdelphij** Device Map 16 bytes char 800210358Sdelphij** cfgVersion ULONG <== Added for checking of new firmware capability 801210358Sdelphij** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP) 802210358Sdelphij** Signature 0x87974063(4) 803210358Sdelphij** UPPER32 of Request Frame (4)-->Driver Only 804210358Sdelphij** 0x03 : Reset (Abort all queued Command) 805210358Sdelphij** 0x04 : Stop Background Activity 806210358Sdelphij** 0x05 : Flush Cache 807210358Sdelphij** 0x06 : Start Background Activity (re-start if background is halted) 808210358Sdelphij** 0x07 : Check If Host Command Pending (Novell May Need This Function) 809210358Sdelphij** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP) 810210358Sdelphij** byte 0 : 0xaa <-- signature 811210358Sdelphij** byte 1 : 0x55 <-- signature 812210358Sdelphij** byte 2 : year (04) 813210358Sdelphij** byte 3 : month (1..12) 814210358Sdelphij** byte 4 : date (1..31) 815210358Sdelphij** byte 5 : hour (0..23) 816210358Sdelphij** byte 6 : minute (0..59) 817210358Sdelphij** byte 7 : second (0..59) 818210358Sdelphij** 819210358Sdelphij** <2> Doorbell Register is used for RS-232 emulation 820210358Sdelphij** <A> different clear register 821210358Sdelphij** <B> different bit0 definition (bit0 is reserved) 822210358Sdelphij** 823210358Sdelphij** inbound doorbell : at offset 0x20 824210358Sdelphij** inbound doorbell clear : at offset 0x70 825210358Sdelphij** 826210358Sdelphij** inbound doorbell : bit0 -- reserved 827210358Sdelphij** bit1 -- data in ready (DRIVER DATA WRITE OK) 828210358Sdelphij** bit2 -- data out has been read (DRIVER DATA READ OK) 829210358Sdelphij** bit3 -- inbound message 0 ready 830210358Sdelphij** bit4 -- more than 12 request completed in a time 831210358Sdelphij** 832210358Sdelphij** outbound doorbell : at offset 0x9C 833210358Sdelphij** outbound doorbell clear : at offset 0xA0 834210358Sdelphij** 835210358Sdelphij** outbound doorbell : bit0 -- reserved 836210358Sdelphij** bit1 -- data out ready (IOP DATA WRITE OK) 837210358Sdelphij** bit2 -- data in has been read (IOP DATA READ OK) 838210358Sdelphij** bit3 -- outbound message 0 ready 839210358Sdelphij** 840210358Sdelphij** <3> Index Memory Usage (Buffer Area) 841210358Sdelphij** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS232 in (scratch buffer) 842210358Sdelphij** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS232 out (request buffer) 843210358Sdelphij** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code msgcode_rwbuffer (IOP send to driver) 844210358Sdelphij** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code msgcode_rwbuffer (driver send to IOP) 845210358Sdelphij** 846210358Sdelphij** <4> PostQ (Command Post Address) 847210358Sdelphij** All SCSI Command must be sent through postQ: 848210358Sdelphij** inbound queue port32 at offset 0x40 , 0x41, 0x42, 0x43 849210358Sdelphij** inbound queue port64 at offset 0xC0 (lower)/0xC4 (upper) 850210358Sdelphij** outbound queue port32 at offset 0x44 851210358Sdelphij** outbound queue port64 at offset 0xC8 (lower)/0xCC (upper) 852210358Sdelphij** <A> For 32bit queue, access low part is enough to send/receive request 853210358Sdelphij** i.e. write 0x40/0xC0, ROC will get the request with high part == 0, the 854210358Sdelphij** same for outbound queue port 855210358Sdelphij** <B> For 64bit queue, if 64bit instruction is supported, use 64bit instruction 856210358Sdelphij** to post inbound request in a single instruction, and use 64bit instruction 857210358Sdelphij** to retrieve outbound request in a single instruction. 858210358Sdelphij** If in 32bit environment, when sending inbound queue, write high part first 859210358Sdelphij** then write low part. For receiving outbound request, read high part first 860210358Sdelphij** then low part, to check queue empty, ONLY check high part to be 0xFFFFFFFF. 861210358Sdelphij** If high part is 0xFFFFFFFF, DO NOT read low part, this may corrupt the 862210358Sdelphij** consistency of the FIFO. Another way to check empty is to check status flag 863210358Sdelphij** at 0x30 bit3. 864210358Sdelphij** <C> Post Address IS NOT shifted (must be 16 bytes aligned) 865210358Sdelphij** For BIOS, 16bytes aligned is OK 866210358Sdelphij** For Driver, 32bytes alignment is recommended. 867210358Sdelphij** POST Command bit0 to bit3 is defined differently 868210358Sdelphij** ---------------------------- 869210358Sdelphij** bit0:1 for PULL mode (must be 1) 870210358Sdelphij** ---------------------------- 871210358Sdelphij** bit3/2/1: for arcmsr cdb size (arccdbsize) 872210358Sdelphij** 000: <= 0x0080 (128) 873210358Sdelphij** 001: <= 0x0100 (256) 874210358Sdelphij** 010: <= 0x0180 (384) 875210358Sdelphij** 011: <= 0x0200 (512) 876210358Sdelphij** 100: <= 0x0280 (640) 877210358Sdelphij** 101: <= 0x0300 (768) 878210358Sdelphij** 110: <= 0x0300 (reserved) 879210358Sdelphij** 111: <= 0x0300 (reserved) 880210358Sdelphij** ----------------------------- 881210358Sdelphij** if len > 0x300 the len always set as 0x300 882210358Sdelphij** ----------------------------- 883210358Sdelphij** post addr = addr | ((len-1) >> 6) | 1 884210358Sdelphij** ----------------------------- 885210358Sdelphij** page length in command buffer still required, 886210358Sdelphij** 887210358Sdelphij** if page length > 3, 888210358Sdelphij** firmware will assume more request data need to be retrieved 889210358Sdelphij** 890210358Sdelphij** <D> Outbound Posting 891210358Sdelphij** bit0:0 , no error, 1 with error, refer to status buffer 892210358Sdelphij** bit1:0 , reserved (will be 0) 893210358Sdelphij** bit2:0 , reserved (will be 0) 894210358Sdelphij** bit3:0 , reserved (will be 0) 895210358Sdelphij** bit63-4: Completed command address 896210358Sdelphij** 897210358Sdelphij** <E> BIOS support, no special support is required. 898210358Sdelphij** LSI2108 support I/O register 899210358Sdelphij** All driver functionality is supported through I/O address 900210358Sdelphij** 901144411Sscottl************************************************************************************************ 902144411Sscottl*/ 903144411Sscottl/* 904165155Sscottl********************************** 905165155Sscottl** 906165155Sscottl********************************** 907165155Sscottl*/ 908165155Sscottl/* size 8 bytes */ 909210358Sdelphij/* 32bit Scatter-Gather list */ 910165155Sscottlstruct SG32ENTRY { /* length bit 24 == 0 */ 911165155Sscottl u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 912165155Sscottl u_int32_t address; 913165155Sscottl}; 914165155Sscottl/* size 12 bytes */ 915210358Sdelphij/* 64bit Scatter-Gather list */ 916165155Sscottlstruct SG64ENTRY { /* length bit 24 == 1 */ 917165155Sscottl u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 918165155Sscottl u_int32_t address; 919165155Sscottl u_int32_t addresshigh; 920165155Sscottl}; 921165155Sscottlstruct SGENTRY_UNION { 922165155Sscottl union { 923165155Sscottl struct SG32ENTRY sg32entry; /* 30h Scatter gather address */ 924165155Sscottl struct SG64ENTRY sg64entry; /* 30h */ 925165155Sscottl }u; 926165155Sscottl}; 927165155Sscottl/* 928165155Sscottl********************************** 929165155Sscottl** 930165155Sscottl********************************** 931165155Sscottl*/ 932165155Sscottlstruct QBUFFER { 933165155Sscottl u_int32_t data_len; 934165155Sscottl u_int8_t data[124]; 935165155Sscottl}; 936165155Sscottl/* 937244406Sdelphij********************************** 938244406Sdelphij*/ 939244406Sdelphijtypedef struct PHYS_ADDR64 { 940244406Sdelphij u_int32_t phyadd_low; 941244406Sdelphij u_int32_t phyadd_high; 942244406Sdelphij}PHYSADDR64; 943244406Sdelphij/* 944144411Sscottl************************************************************************************************ 945165155Sscottl** FIRMWARE INFO 946165155Sscottl************************************************************************************************ 947165155Sscottl*/ 948210358Sdelphij#define ARCMSR_FW_MODEL_OFFSET 15 949210358Sdelphij#define ARCMSR_FW_VERS_OFFSET 17 950210358Sdelphij#define ARCMSR_FW_DEVMAP_OFFSET 21 951210358Sdelphij#define ARCMSR_FW_CFGVER_OFFSET 25 952210358Sdelphij 953165155Sscottlstruct FIRMWARE_INFO { 954215234Sdelphij u_int32_t signature; /*0,00-03*/ 955215234Sdelphij u_int32_t request_len; /*1,04-07*/ 956215234Sdelphij u_int32_t numbers_queue; /*2,08-11*/ 957215234Sdelphij u_int32_t sdram_size; /*3,12-15*/ 958215234Sdelphij u_int32_t ide_channels; /*4,16-19*/ 959215234Sdelphij char vendor[40]; /*5,20-59*/ 960215234Sdelphij char model[8]; /*15,60-67*/ 961215234Sdelphij char firmware_ver[16]; /*17,68-83*/ 962215234Sdelphij char device_map[16]; /*21,84-99*/ 963210358Sdelphij u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 964210358Sdelphij char cfgSerial[16]; /*26,104-119*/ 965210358Sdelphij u_int32_t cfgPicStatus; /*30,120-123*/ 966165155Sscottl}; 967210358Sdelphij/* (A) For cfgVersion in FIRMWARE_INFO 968210358Sdelphij** if low BYTE (byte#0) >= 3 (version 3) 969210358Sdelphij** then byte#1 report the capability of the firmware can xfer in a single request 970210358Sdelphij** 971210358Sdelphij** byte#1 972210358Sdelphij** 0 256K 973210358Sdelphij** 1 512K 974210358Sdelphij** 2 1M 975210358Sdelphij** 3 2M 976210358Sdelphij** 4 4M 977210358Sdelphij** 5 8M 978210358Sdelphij** 6 16M 979210358Sdelphij** (B) Byte offset 7 (Reserved1) of CDB is changed to msgPages 980210358Sdelphij** Driver support new xfer method need to set this field to indicate 981210358Sdelphij** large CDB block in 0x100 unit (we use 0x100 byte as one page) 982210358Sdelphij** e.g. If the length of CDB including MSG header and SGL is 0x1508 983210358Sdelphij** driver need to set the msgPages to 0x16 984210358Sdelphij** (C) REQ_LEN_512BYTE must be used also to indicate SRB length 985210358Sdelphij** e.g. CDB len msgPages REQ_LEN_512BYTE flag 986210358Sdelphij** <= 0x100 1 0 987210358Sdelphij** <= 0x200 2 1 988210358Sdelphij** <= 0x300 3 1 989210358Sdelphij** <= 0x400 4 1 990210358Sdelphij** . 991210358Sdelphij** . 992210358Sdelphij*/ 993210358Sdelphij 994165155Sscottl/* 995165155Sscottl************************************************************************************************ 996144411Sscottl** size 0x1F8 (504) 997144411Sscottl************************************************************************************************ 998144411Sscottl*/ 999165155Sscottlstruct ARCMSR_CDB { 1000215234Sdelphij u_int8_t Bus; /* 00h should be 0 */ 1001215234Sdelphij u_int8_t TargetID; /* 01h should be 0--15 */ 1002215234Sdelphij u_int8_t LUN; /* 02h should be 0--7 */ 1003215234Sdelphij u_int8_t Function; /* 03h should be 1 */ 1004174451Sscottl 1005215234Sdelphij u_int8_t CdbLength; /* 04h not used now */ 1006215234Sdelphij u_int8_t sgcount; /* 05h */ 1007215234Sdelphij u_int8_t Flags; /* 06h */ 1008210358Sdelphij u_int8_t msgPages; /* 07h */ 1009174451Sscottl 1010215234Sdelphij u_int32_t Context; /* 08h Address of this request */ 1011215234Sdelphij u_int32_t DataLength; /* 0ch not used now */ 1012174451Sscottl 1013215234Sdelphij u_int8_t Cdb[16]; /* 10h SCSI CDB */ 1014144411Sscottl /* 1015144411Sscottl ******************************************************** 1016244406Sdelphij ** Device Status : the same from SCSI bus if error occur 1017144411Sscottl ** SCSI bus status codes. 1018144411Sscottl ******************************************************** 1019144411Sscottl */ 1020215234Sdelphij u_int8_t DeviceStatus; /* 20h if error */ 1021244406Sdelphij 1022244406Sdelphij u_int8_t SenseData[15]; /* 21h output */ 1023244406Sdelphij 1024244406Sdelphij union { 1025244406Sdelphij struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ 1026244406Sdelphij struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ 1027244406Sdelphij } u; 1028244406Sdelphij}; 1029244406Sdelphij/* CDB flag */ 1030244406Sdelphij#define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ 1031244406Sdelphij#define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ 1032244406Sdelphij#define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ 1033244406Sdelphij#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 1034244406Sdelphij#define ARCMSR_CDB_FLAG_HEADQ 0x08 1035244406Sdelphij#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 1036244406Sdelphij/* scsi status */ 1037144411Sscottl#define SCSISTAT_GOOD 0x00 1038144411Sscottl#define SCSISTAT_CHECK_CONDITION 0x02 1039144411Sscottl#define SCSISTAT_CONDITION_MET 0x04 1040144411Sscottl#define SCSISTAT_BUSY 0x08 1041144411Sscottl#define SCSISTAT_INTERMEDIATE 0x10 1042144411Sscottl#define SCSISTAT_INTERMEDIATE_COND_MET 0x14 1043144411Sscottl#define SCSISTAT_RESERVATION_CONFLICT 0x18 1044144411Sscottl#define SCSISTAT_COMMAND_TERMINATED 0x22 1045144411Sscottl#define SCSISTAT_QUEUE_FULL 0x28 1046244406Sdelphij/* DeviceStatus */ 1047215234Sdelphij#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 1048215234Sdelphij#define ARCMSR_DEV_ABORTED 0xF1 1049215234Sdelphij#define ARCMSR_DEV_INIT_FAIL 0xF2 1050144411Sscottl/* 1051144411Sscottl********************************************************************* 1052144411Sscottl** Command Control Block (SrbExtension) 1053144411Sscottl** SRB must be not cross page boundary,and the order from offset 0 1054144411Sscottl** structure describing an ATA disk request 1055144411Sscottl** this SRB length must be 32 bytes boundary 1056144411Sscottl********************************************************************* 1057144411Sscottl*/ 1058165155Sscottlstruct CommandControlBlock { 1059210358Sdelphij struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ 1060244406Sdelphij u_int32_t cdb_phyaddr_low; /* 504-507 */ 1061210358Sdelphij u_int32_t arc_cdb_size; /* 508-511 */ 1062165155Sscottl /* ======================512+32 bytes============================ */ 1063210358Sdelphij union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */ 1064210358Sdelphij struct AdapterControlBlock *acb; /* 520-523 524-527 */ 1065215234Sdelphij bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */ 1066215234Sdelphij u_int16_t srb_flags; /* 536-537 */ 1067244406Sdelphij u_int16_t srb_state; /* 538-539 */ 1068244406Sdelphij u_int32_t cdb_phyaddr_high; /* 540-543 */ 1069220403Sdelphij struct callout ccb_callout; 1070144411Sscottl /* ========================================================== */ 1071144411Sscottl}; 1072210358Sdelphij/* srb_flags */ 1073210358Sdelphij#define SRB_FLAG_READ 0x0000 1074210358Sdelphij#define SRB_FLAG_WRITE 0x0001 1075210358Sdelphij#define SRB_FLAG_ERROR 0x0002 1076210358Sdelphij#define SRB_FLAG_FLUSHCACHE 0x0004 1077210358Sdelphij#define SRB_FLAG_MASTER_ABORTED 0x0008 1078210358Sdelphij#define SRB_FLAG_DMAVALID 0x0010 1079210358Sdelphij#define SRB_FLAG_DMACONSISTENT 0x0020 1080210358Sdelphij#define SRB_FLAG_DMAWRITE 0x0040 1081210358Sdelphij#define SRB_FLAG_PKTBIND 0x0080 1082220403Sdelphij#define SRB_FLAG_TIMER_START 0x0080 1083220403Sdelphij/* srb_state */ 1084210358Sdelphij#define ARCMSR_SRB_DONE 0x0000 1085210358Sdelphij#define ARCMSR_SRB_UNBUILD 0x0000 1086210358Sdelphij#define ARCMSR_SRB_TIMEOUT 0x1111 1087210358Sdelphij#define ARCMSR_SRB_RETRY 0x2222 1088210358Sdelphij#define ARCMSR_SRB_START 0x55AA 1089210358Sdelphij#define ARCMSR_SRB_PENDING 0xAA55 1090210358Sdelphij#define ARCMSR_SRB_RESET 0xA5A5 1091210358Sdelphij#define ARCMSR_SRB_ABORTED 0x5A5A 1092210358Sdelphij#define ARCMSR_SRB_ILLEGAL 0xFFFF 1093244406Sdelphij 1094244406Sdelphij#define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0) 1095244406Sdelphij#define ARCMSR_SRBS_POOL_SIZE (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM) 1096244406Sdelphij 1097144411Sscottl/* 1098144411Sscottl********************************************************************* 1099144411Sscottl** Adapter Control Block 1100144411Sscottl********************************************************************* 1101144411Sscottl*/ 1102215234Sdelphij#define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */ 1103215234Sdelphij#define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */ 1104210358Sdelphij#define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc L IOP */ 1105244406Sdelphij#define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd M IOP */ 1106215234Sdelphij 1107210358Sdelphijstruct AdapterControlBlock { 1108210358Sdelphij u_int32_t adapter_type; /* adapter A,B..... */ 1109210358Sdelphij 1110215234Sdelphij bus_space_tag_t btag[2]; 1111215234Sdelphij bus_space_handle_t bhandle[2]; 1112215234Sdelphij bus_dma_tag_t parent_dmat; 1113215234Sdelphij bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */ 1114215234Sdelphij bus_dma_tag_t srb_dmat; /* dmat for freesrb */ 1115215234Sdelphij bus_dmamap_t srb_dmamap; 1116165155Sscottl device_t pci_dev; 1117144411Sscottl#if __FreeBSD_version < 503000 1118165155Sscottl dev_t ioctl_dev; 1119144411Sscottl#else 1120220403Sdelphij struct cdev *ioctl_dev; 1121144411Sscottl#endif 1122215234Sdelphij int pci_unit; 1123174451Sscottl 1124220403Sdelphij struct resource *sys_res_arcmsr[2]; 1125220403Sdelphij struct resource *irqres; 1126220403Sdelphij void *ih; /* interrupt handle */ 1127174451Sscottl 1128144411Sscottl /* Hooks into the CAM XPT */ 1129165155Sscottl struct cam_sim *psim; 1130165155Sscottl struct cam_path *ppath; 1131220403Sdelphij u_int8_t *uncacheptr; 1132215234Sdelphij unsigned long vir2phy_offset; 1133210358Sdelphij union { 1134210358Sdelphij unsigned long phyaddr; 1135210358Sdelphij struct { 1136210358Sdelphij u_int32_t phyadd_low; 1137210358Sdelphij u_int32_t phyadd_high; 1138210358Sdelphij }B; 1139210358Sdelphij } srb_phyaddr; 1140210358Sdelphij// unsigned long srb_phyaddr; 1141165155Sscottl /* Offset is used in making arc cdb physical to virtual calculations */ 1142165155Sscottl u_int32_t outbound_int_enable; 1143174451Sscottl 1144220403Sdelphij struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */ 1145174451Sscottl 1146215234Sdelphij u_int8_t adapter_index; /* */ 1147165155Sscottl u_int8_t irq; 1148215234Sdelphij u_int16_t acb_flags; /* */ 1149174451Sscottl 1150220403Sdelphij struct CommandControlBlock *psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */ 1151220403Sdelphij struct CommandControlBlock *srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */ 1152165155Sscottl int32_t workingsrb_doneindex; /* done srb array index */ 1153165155Sscottl int32_t workingsrb_startindex; /* start srb array index */ 1154165155Sscottl int32_t srboutstandingcount; 1155174451Sscottl 1156165155Sscottl u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ 1157165155Sscottl u_int32_t rqbuf_firstindex; /* first of read buffer */ 1158165155Sscottl u_int32_t rqbuf_lastindex; /* last of read buffer */ 1159174451Sscottl 1160165155Sscottl u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ 1161165155Sscottl u_int32_t wqbuf_firstindex; /* first of write buffer */ 1162165155Sscottl u_int32_t wqbuf_lastindex; /* last of write buffer */ 1163174451Sscottl 1164244406Sdelphij arcmsr_lock_t isr_lock; 1165244406Sdelphij arcmsr_lock_t srb_lock; 1166244406Sdelphij arcmsr_lock_t postDone_lock; 1167215234Sdelphij arcmsr_lock_t qbuffer_lock; 1168174451Sscottl 1169165155Sscottl u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ 1170165155Sscottl u_int32_t num_resets; 1171165155Sscottl u_int32_t num_aborts; 1172215234Sdelphij u_int32_t firm_request_len; /*1,04-07*/ 1173215234Sdelphij u_int32_t firm_numbers_queue; /*2,08-11*/ 1174215234Sdelphij u_int32_t firm_sdram_size; /*3,12-15*/ 1175215234Sdelphij u_int32_t firm_ide_channels; /*4,16-19*/ 1176210358Sdelphij u_int32_t firm_cfg_version; 1177215234Sdelphij char firm_model[12]; /*15,60-67*/ 1178215234Sdelphij char firm_version[20]; /*17,68-83*/ 1179210358Sdelphij char device_map[20]; /*21,84-99 */ 1180210358Sdelphij struct callout devmap_callout; 1181220403Sdelphij u_int32_t pktRequestCount; 1182220403Sdelphij u_int32_t pktReturnCount; 1183240079Sdelphij u_int32_t vendor_device_id; 1184240079Sdelphij u_int32_t adapter_bus_speed; 1185252857Sdelphij u_int32_t maxOutstanding; 1186144411Sscottl};/* HW_DEVICE_EXTENSION */ 1187210358Sdelphij/* acb_flags */ 1188210358Sdelphij#define ACB_F_SCSISTOPADAPTER 0x0001 1189210358Sdelphij#define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 1190210358Sdelphij#define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 1191210358Sdelphij#define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ 1192210358Sdelphij#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */ 1193210358Sdelphij#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */ 1194210358Sdelphij#define ACB_F_MESSAGE_WQBUFFER_READ 0x0040 1195210358Sdelphij#define ACB_F_BUS_RESET 0x0080 1196210358Sdelphij#define ACB_F_IOP_INITED 0x0100 /* iop init */ 1197210358Sdelphij#define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */ 1198210358Sdelphij#define ACB_F_CAM_DEV_QFRZN 0x0400 1199210358Sdelphij#define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */ 1200210358Sdelphij#define ACB_F_SRB_FUNCTION_POWER 0x1000 1201210358Sdelphij/* devstate */ 1202210358Sdelphij#define ARECA_RAID_GONE 0x55 1203210358Sdelphij#define ARECA_RAID_GOOD 0xaa 1204240079Sdelphij/* adapter_bus_speed */ 1205240079Sdelphij#define ACB_BUS_SPEED_3G 0 1206240079Sdelphij#define ACB_BUS_SPEED_6G 1 1207240079Sdelphij#define ACB_BUS_SPEED_12G 2 1208144411Sscottl/* 1209144411Sscottl************************************************************* 1210144411Sscottl************************************************************* 1211144411Sscottl*/ 1212165155Sscottlstruct SENSE_DATA { 1213215234Sdelphij u_int8_t ErrorCode:7; 1214215234Sdelphij u_int8_t Valid:1; 1215215234Sdelphij u_int8_t SegmentNumber; 1216215234Sdelphij u_int8_t SenseKey:4; 1217215234Sdelphij u_int8_t Reserved:1; 1218215234Sdelphij u_int8_t IncorrectLength:1; 1219215234Sdelphij u_int8_t EndOfMedia:1; 1220215234Sdelphij u_int8_t FileMark:1; 1221215234Sdelphij u_int8_t Information[4]; 1222215234Sdelphij u_int8_t AdditionalSenseLength; 1223215234Sdelphij u_int8_t CommandSpecificInformation[4]; 1224215234Sdelphij u_int8_t AdditionalSenseCode; 1225215234Sdelphij u_int8_t AdditionalSenseCodeQualifier; 1226215234Sdelphij u_int8_t FieldReplaceableUnitCode; 1227215234Sdelphij u_int8_t SenseKeySpecific[3]; 1228144411Sscottl}; 1229144411Sscottl/* 1230144411Sscottl********************************** 1231144411Sscottl** Peripheral Device Type definitions 1232144411Sscottl********************************** 1233144411Sscottl*/ 1234215234Sdelphij#define SCSI_DASD 0x00 /* Direct-access Device */ 1235215234Sdelphij#define SCSI_SEQACESS 0x01 /* Sequential-access device */ 1236215234Sdelphij#define SCSI_PRINTER 0x02 /* Printer device */ 1237215234Sdelphij#define SCSI_PROCESSOR 0x03 /* Processor device */ 1238215234Sdelphij#define SCSI_WRITEONCE 0x04 /* Write-once device */ 1239215234Sdelphij#define SCSI_CDROM 0x05 /* CD-ROM device */ 1240215234Sdelphij#define SCSI_SCANNER 0x06 /* Scanner device */ 1241215234Sdelphij#define SCSI_OPTICAL 0x07 /* Optical memory device */ 1242215234Sdelphij#define SCSI_MEDCHGR 0x08 /* Medium changer device */ 1243215234Sdelphij#define SCSI_COMM 0x09 /* Communications device */ 1244215234Sdelphij#define SCSI_NODEV 0x1F /* Unknown or no device type */ 1245144411Sscottl/* 1246144411Sscottl************************************************************************************************************ 1247144411Sscottl** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1248144411Sscottl** 80331 PCI-to-PCI Bridge 1249144411Sscottl** PCI Configuration Space 1250144411Sscottl** 1251144411Sscottl** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1252144411Sscottl** Programming Interface 1253144411Sscottl** ======================== 1254144411Sscottl** Configuration Register Address Space Groupings and Ranges 1255144411Sscottl** ============================================================= 1256144411Sscottl** Register Group Configuration Offset 1257144411Sscottl** ------------------------------------------------------------- 1258144411Sscottl** Standard PCI Configuration 00-3Fh 1259144411Sscottl** ------------------------------------------------------------- 1260144411Sscottl** Device Specific Registers 40-A7h 1261144411Sscottl** ------------------------------------------------------------- 1262144411Sscottl** Reserved A8-CBh 1263144411Sscottl** ------------------------------------------------------------- 1264144411Sscottl** Enhanced Capability List CC-FFh 1265144411Sscottl** ========================================================================================================== 1266144411Sscottl** Standard PCI [Type 1] Configuration Space Address Map 1267144411Sscottl** ********************************************************************************************************** 1268144411Sscottl** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1269144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1270144411Sscottl** | Device ID | Vendor ID | 00h 1271144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1272144411Sscottl** | Primary Status | Primary Command | 04h 1273144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1274144411Sscottl** | Class Code | RevID | 08h 1275144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1276144411Sscottl** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch 1277144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1278144411Sscottl** | Reserved | 10h 1279144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1280144411Sscottl** | Reserved | 14h 1281144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1282144411Sscottl** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h 1283144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1284144411Sscottl** | Secondary Status | I/O Limit | I/O Base | 1Ch 1285144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1286144411Sscottl** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h 1287144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1288144411Sscottl** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h 1289144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1290144411Sscottl** | Prefetchable Memory Base Address Upper 32 Bits | 28h 1291144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1292144411Sscottl** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch 1293144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1294144411Sscottl** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h 1295144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1296144411Sscottl** | Reserved | Capabilities Pointer | 34h 1297144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1298144411Sscottl** | Reserved | 38h 1299144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1300144411Sscottl** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch 1301144411Sscottl**============================================================================================================= 1302144411Sscottl*/ 1303144411Sscottl/* 1304144411Sscottl**============================================================================================================= 1305144411Sscottl** 0x03-0x00 : 1306144411Sscottl** Bit Default Description 1307144411Sscottl**31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG. 1308144411Sscottl** ID is unique per product speed as indicated. 1309144411Sscottl**15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor. 1310144411Sscottl**============================================================================================================= 1311144411Sscottl*/ 1312144411Sscottl#define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/ 1313144411Sscottl#define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/ 1314144411Sscottl/* 1315144411Sscottl**============================================================================== 1316144411Sscottl** 0x05-0x04 : command register 1317144411Sscottl** Bit Default Description 1318144411Sscottl**15:11 00h Reserved 1319144411Sscottl** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 1320144411Sscottl** The bridge does not support interrupts. 1321165155Sscottl** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back 1322165155Sscottl** transactions on the primary bus. 1323165155Sscottl** The bridge does not generate fast back to back 1324165155Sscottl** transactions on the primary bus. 1325144411Sscottl** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions. 1326144411Sscottl** 0=The bridge does not assert P_SERR#. 1327144411Sscottl** 1=The bridge may assert P_SERR#, subject to other programmable criteria. 1328165155Sscottl** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating 1329165155Sscottl** that bridge does not perform address or data stepping, 1330144411Sscottl** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error. 1331144411Sscottl** 0=When a data parity error is detected bridge does not assert S_PERR#. 1332165155Sscottl** Also bridge does not assert P_SERR# in response to 1333165155Sscottl** a detected address or attribute parity error. 1334144411Sscottl** 1=When a data parity error is detected bridge asserts S_PERR#. 1335165155Sscottl** The bridge also asserts P_SERR# 1336165155Sscottl** (when enabled globally via bit(8) of this register) 1337165155Sscottl** in response to a detected address or attribute parity error. 1338144411Sscottl** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 1339165155Sscottl** VGA palette write transactions are I/O transactions 1340165155Sscottl** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h 1341165155Sscottl** P_AD[15:10] are not decoded (i.e. aliases are claimed), 1342165155Sscottl** or are fully decoding 1343165155Sscottl** (i.e., must be all 0's depending upon the VGA 1344165155Sscottl** aliasing bit in the Bridge Control Register, offset 3Eh. 1345144411Sscottl** P_AD[31:16] equal to 0000h 1346165155Sscottl** 0=The bridge ignores VGA palette write transactions, 1347165155Sscottl** unless decoded by the standard I/O address range window. 1348165155Sscottl** 1=The bridge responds to VGA palette write transactions 1349165155Sscottl** with medium DEVSEL# timing and forwards them to the secondary bus. 1350144411Sscottl** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 1351165155Sscottl** MWI transactions targeting resources on the opposite side of the bridge, 1352165155Sscottl** however, are forwarded as MWI transactions. 1353144411Sscottl** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 1354144411Sscottl** This bit is read only and always returns 0 when read 1355144411Sscottl** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface. 1356144411Sscottl** Initiation of configuration transactions is not affected by the state of this bit. 1357144411Sscottl** 0=The bridge does not initiate memory or I/O transactions on the primary interface. 1358144411Sscottl** 1=The bridge is enabled to function as an initiator on the primary interface. 1359144411Sscottl** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface. 1360144411Sscottl** 0=The bridge target response to memory transactions on the primary interface is disabled. 1361144411Sscottl** 1=The bridge target response to memory transactions on the primary interface is enabled. 1362144411Sscottl** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface. 1363144411Sscottl** 0=The bridge target response to I/O transactions on the primary interface is disabled. 1364144411Sscottl** 1=The bridge target response to I/O transactions on the primary interface is enabled. 1365144411Sscottl**============================================================================== 1366144411Sscottl*/ 1367215234Sdelphij#define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/ 1368215234Sdelphij#define PCI_DISABLE_INTERRUPT 0x0400 1369144411Sscottl/* 1370144411Sscottl**============================================================================== 1371144411Sscottl** 0x07-0x06 : status register 1372144411Sscottl** Bit Default Description 1373165155Sscottl** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1374165155Sscottl** attribute or data parity error. 1375144411Sscottl** This bit is set regardless of the state of the PER bit in the command register. 1376144411Sscottl** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus. 1377165155Sscottl** 13 0 Received Master Abort: The bridge sets this bit to a 1b when, 1378165155Sscottl** acting as the initiator on the primary bus, 1379165155Sscottl** its transaction (with the exception of special cycles) 1380165155Sscottl** has been terminated with a Master Abort. 1381165155Sscottl** 12 0 Received Target Abort: The bridge sets this bit to a 1b when, 1382165155Sscottl** acting as the initiator on the primary bus, 1383165155Sscottl** its transaction has been terminated with a Target Abort. 1384165155Sscottl** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it, 1385165155Sscottl** as the target of a transaction, terminates it with a Target Abort. 1386144411Sscottl** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1387144411Sscottl** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 1388144411Sscottl** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1389165155Sscottl** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1390165155Sscottl** The bridge is the current master on the primary bus 1391144411Sscottl** S_PERR# is detected asserted or is asserted by bridge 1392144411Sscottl** The Parity Error Response bit is set in the Command register 1393165155Sscottl** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge 1394165155Sscottl** is able to respond to fast back to back transactions on its primary interface. 1395144411Sscottl** 06 0 Reserved 1396144411Sscottl** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable. 1397144411Sscottl** 1 = 1398144411Sscottl** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 1399165155Sscottl** Offset 34h (Capability Pointer register) 1400165155Sscottl** provides the offset for the first entry 1401165155Sscottl** in the linked list of enhanced capabilities. 1402144411Sscottl** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function. 1403144411Sscottl** The bridge does not support interrupts. 1404144411Sscottl** 02:00 000 Reserved 1405144411Sscottl**============================================================================== 1406144411Sscottl*/ 1407144411Sscottl#define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */ 1408165155Sscottl#define ARCMSR_ADAP_66MHZ 0x20 1409144411Sscottl/* 1410144411Sscottl**============================================================================== 1411144411Sscottl** 0x08 : revision ID 1412144411Sscottl** Bit Default Description 1413144411Sscottl** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping. 1414144411Sscottl**============================================================================== 1415144411Sscottl*/ 1416144411Sscottl#define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/ 1417144411Sscottl/* 1418144411Sscottl**============================================================================== 1419144411Sscottl** 0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 1420144411Sscottl** Bit Default Description 1421144411Sscottl** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device. 1422144411Sscottl** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge. 1423144411Sscottl** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge. 1424144411Sscottl**============================================================================== 1425144411Sscottl*/ 1426144411Sscottl#define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/ 1427144411Sscottl/* 1428144411Sscottl**============================================================================== 1429144411Sscottl** 0x0c : cache line size 1430144411Sscottl** Bit Default Description 1431144411Sscottl** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units. 1432165155Sscottl** The contents of this register are factored into 1433165155Sscottl** internal policy decisions associated with memory read prefetching, 1434165155Sscottl** and the promotion of Memory Write transactions to MWI transactions. 1435144411Sscottl** Valid cache line sizes are 8 and 16 dwords. 1436165155Sscottl** When the cache line size is set to an invalid value, 1437165155Sscottl** bridge behaves as though the cache line size was set to 00h. 1438144411Sscottl**============================================================================== 1439144411Sscottl*/ 1440144411Sscottl#define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/ 1441144411Sscottl/* 1442144411Sscottl**============================================================================== 1443144411Sscottl** 0x0d : latency timer (number of pci clock 00-ff ) 1444144411Sscottl** Bit Default Description 1445144411Sscottl** Primary Latency Timer (PTV): 1446144411Sscottl** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles, 1447144411Sscottl** referenced from the assertion of FRAME# to the expiration of the timer, 1448144411Sscottl** when bridge may continue as master of the current transaction. All bits are writable, 1449144411Sscottl** resulting in a granularity of 1 PCI clock cycle. 1450165155Sscottl** When the timer expires (i.e., equals 00h) 1451165155Sscottl** bridge relinquishes the bus after the first data transfer 1452165155Sscottl** when its PCI bus grant has been deasserted. 1453144411Sscottl** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer. 1454144411Sscottl** Indicates the number of PCI clock cycles, 1455144411Sscottl** referenced from the assertion of FRAME# to the expiration of the timer, 1456144411Sscottl** when bridge may continue as master of the current transaction. 1457144411Sscottl** All bits are writable, resulting in a granularity of 1 PCI clock cycle. 1458144411Sscottl** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1459165155Sscottl** (Except in the case where MLT expires within 3 data phases 1460165155Sscottl** of an ADB.In this case bridge continues on 1461165155Sscottl** until it reaches the next ADB before relinquishing the bus.) 1462144411Sscottl**============================================================================== 1463144411Sscottl*/ 1464144411Sscottl#define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/ 1465144411Sscottl/* 1466144411Sscottl**============================================================================== 1467144411Sscottl** 0x0e : (header type,single function ) 1468144411Sscottl** Bit Default Description 1469144411Sscottl** 07 0 Multi-function device (MVD): 80331 is a single-function device. 1470144411Sscottl** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 1471165155Sscottl** Returns ��01h�� when read indicating 1472165155Sscottl** that the register layout conforms to the standard PCI-to-PCI bridge layout. 1473144411Sscottl**============================================================================== 1474144411Sscottl*/ 1475144411Sscottl#define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/ 1476144411Sscottl/* 1477144411Sscottl**============================================================================== 1478144411Sscottl** 0x0f : 1479144411Sscottl**============================================================================== 1480144411Sscottl*/ 1481144411Sscottl/* 1482144411Sscottl**============================================================================== 1483144411Sscottl** 0x13-0x10 : 1484144411Sscottl** PCI CFG Base Address #0 (0x10) 1485144411Sscottl**============================================================================== 1486144411Sscottl*/ 1487144411Sscottl/* 1488144411Sscottl**============================================================================== 1489144411Sscottl** 0x17-0x14 : 1490144411Sscottl** PCI CFG Base Address #1 (0x14) 1491144411Sscottl**============================================================================== 1492144411Sscottl*/ 1493144411Sscottl/* 1494144411Sscottl**============================================================================== 1495144411Sscottl** 0x1b-0x18 : 1496144411Sscottl** PCI CFG Base Address #2 (0x18) 1497144411Sscottl**-----------------0x1A,0x19,0x18--Bus Number Register - BNR 1498144411Sscottl** Bit Default Description 1499144411Sscottl** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 1500165155Sscottl** Any Type 1 configuration cycle 1501165155Sscottl** on the primary bus whose bus number is greater than the secondary bus number, 1502165155Sscottl** and less than or equal to the subordinate bus number 1503165155Sscottl** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus. 1504144411Sscottl** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 1505165155Sscottl** Any Type 1 configuration cycle matching this bus number 1506165155Sscottl** is translated to a Type 0 configuration cycle (or a Special Cycle) 1507165155Sscottl** before being executed on bridge's secondary PCI bus. 1508144411Sscottl** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number. 1509165155Sscottl** Any Type 1 configuration cycle on the primary interface 1510165155Sscottl** with a bus number that is less than the contents 1511165155Sscottl** of this register field does not be claimed by bridge. 1512144411Sscottl**-----------------0x1B--Secondary Latency Timer Register - SLTR 1513144411Sscottl** Bit Default Description 1514144411Sscottl** Secondary Latency Timer (STV): 1515144411Sscottl** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer. 1516165155Sscottl** Indicates the number of PCI clock cycles, 1517165155Sscottl** referenced from the assertion of FRAME# to the expiration of the timer, 1518144411Sscottl** when bridge may continue as master of the current transaction. All bits are writable, 1519144411Sscottl** resulting in a granularity of 1 PCI clock cycle. 1520165155Sscottl** When the timer expires (i.e., equals 00h) 1521165155Sscottl** bridge relinquishes the bus after the first data transfer 1522165155Sscottl** when its PCI bus grant has been deasserted. 1523144411Sscottl** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer. 1524165155Sscottl** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# 1525165155Sscottl** to the expiration of the timer, 1526144411Sscottl** when bridge may continue as master of the current transaction. All bits are writable, 1527144411Sscottl** resulting in a granularity of 1 PCI clock cycle. 1528144411Sscottl** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1529165155Sscottl** (Except in the case where MLT expires within 3 data phases of an ADB. 1530165155Sscottl** In this case bridge continues on until it reaches the next ADB 1531165155Sscottl** before relinquishing the bus) 1532144411Sscottl**============================================================================== 1533144411Sscottl*/ 1534144411Sscottl#define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/ 1535144411Sscottl#define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/ 1536165155Sscottl#define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/ 1537165155Sscottl#define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/ 1538144411Sscottl/* 1539144411Sscottl**============================================================================== 1540144411Sscottl** 0x1f-0x1c : 1541144411Sscottl** PCI CFG Base Address #3 (0x1C) 1542144411Sscottl**-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL 1543144411Sscottl** Bit Default Description 1544165155Sscottl** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to 1545165155Sscottl** determine when to forward I/O transactions from one interface to the other. 1546144411Sscottl** These bits correspond to address lines 15:12 for 4KB alignment. 1547144411Sscottl** Bits 11:0 are assumed to be FFFh. 1548144411Sscottl** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing. 1549165155Sscottl** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of 1550165155Sscottl** an address range to determine when to forward I/O transactions 1551165155Sscottl** from one interface to the other. 1552165155Sscottl** These bits correspond to address lines 15:12 for 4KB alignment. 1553165155Sscottl** Bits 11:0 are assumed to be 000h. 1554144411Sscottl** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing. 1555144411Sscottl**-----------------0x1F,0x1E--Secondary Status Register - SSR 1556144411Sscottl** Bit Default Description 1557165155Sscottl** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1558165155Sscottl** attribute or data parity error on its secondary interface. 1559144411Sscottl** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface. 1560165155Sscottl** 13 0b Received Master Abort: The bridge sets this bit to a 1b when, 1561165155Sscottl** acting as the initiator on the secondary bus, 1562165155Sscottl** it's transaction (with the exception of special cycles) 1563165155Sscottl** has been terminated with a Master Abort. 1564165155Sscottl** 12 0b Received Target Abort: The bridge sets this bit to a 1b when, 1565165155Sscottl** acting as the initiator on the secondary bus, 1566165155Sscottl** it's transaction has been terminated with a Target Abort. 1567165155Sscottl** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it, 1568165155Sscottl** as the target of a transaction, terminates it with a Target Abort. 1569144411Sscottl** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1570144411Sscottl** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 1571144411Sscottl** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1572144411Sscottl** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1573144411Sscottl** The bridge is the current master on the secondary bus 1574144411Sscottl** S_PERR# is detected asserted or is asserted by bridge 1575144411Sscottl** The Parity Error Response bit is set in the Command register 1576144411Sscottl** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles. 1577144411Sscottl** 06 0b Reserved 1578144411Sscottl** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable. 1579144411Sscottl** 1 = 1580144411Sscottl** 04:00 00h Reserved 1581144411Sscottl**============================================================================== 1582144411Sscottl*/ 1583144411Sscottl#define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/ 1584144411Sscottl#define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/ 1585144411Sscottl#define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */ 1586144411Sscottl/* 1587144411Sscottl**============================================================================== 1588144411Sscottl** 0x23-0x20 : 1589144411Sscottl** PCI CFG Base Address #4 (0x20) 1590144411Sscottl**-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL 1591144411Sscottl** Bit Default Description 1592144411Sscottl** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1593144411Sscottl** the upper 1MB aligned value (exclusive) of the range. 1594144411Sscottl** The incoming address must be less than or equal to this value. 1595165155Sscottl** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1596165155Sscottl** are assumed to be F FFFFh. 1597144411Sscottl** 19:16 0h Reserved. 1598165155Sscottl** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20] 1599165155Sscottl** of the incoming address to determine the lower 1MB 1600165155Sscottl** aligned value (inclusive) of the range. 1601144411Sscottl** The incoming address must be greater than or equal to this value. 1602165155Sscottl** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1603165155Sscottl** are assumed to be 0 0000h. 1604144411Sscottl** 03:00 0h Reserved. 1605144411Sscottl**============================================================================== 1606144411Sscottl*/ 1607144411Sscottl#define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */ 1608144411Sscottl#define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */ 1609144411Sscottl/* 1610144411Sscottl**============================================================================== 1611144411Sscottl** 0x27-0x24 : 1612144411Sscottl** PCI CFG Base Address #5 (0x24) 1613144411Sscottl**-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL 1614144411Sscottl** Bit Default Description 1615144411Sscottl** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1616144411Sscottl** the upper 1MB aligned value (exclusive) of the range. 1617144411Sscottl** The incoming address must be less than or equal to this value. 1618165155Sscottl** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1619165155Sscottl** are assumed to be F FFFFh. 1620144411Sscottl** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1621165155Sscottl** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] 1622165155Sscottl** of the incoming address to determine the lower 1MB aligned value (inclusive) 1623165155Sscottl** of the range. 1624144411Sscottl** The incoming address must be greater than or equal to this value. 1625165155Sscottl** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1626165155Sscottl** are assumed to be 0 0000h. 1627144411Sscottl** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1628144411Sscottl**============================================================================== 1629144411Sscottl*/ 1630144411Sscottl#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */ 1631144411Sscottl#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */ 1632144411Sscottl/* 1633144411Sscottl**============================================================================== 1634144411Sscottl** 0x2b-0x28 : 1635144411Sscottl** Bit Default Description 1636144411Sscottl** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable 1637144411Sscottl** bridge supports full 64-bit addressing. 1638144411Sscottl**============================================================================== 1639144411Sscottl*/ 1640144411Sscottl#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */ 1641144411Sscottl/* 1642144411Sscottl**============================================================================== 1643144411Sscottl** 0x2f-0x2c : 1644144411Sscottl** Bit Default Description 1645144411Sscottl** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 1646144411Sscottl** bridge supports full 64-bit addressing. 1647144411Sscottl**============================================================================== 1648144411Sscottl*/ 1649144411Sscottl#define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */ 1650144411Sscottl/* 1651144411Sscottl**============================================================================== 1652144411Sscottl** 0x33-0x30 : 1653144411Sscottl** Bit Default Description 1654144411Sscottl** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration 1655144411Sscottl** space. (Power Management Capability Registers) 1656144411Sscottl**============================================================================== 1657144411Sscottl*/ 1658144411Sscottl#define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/ 1659144411Sscottl/* 1660144411Sscottl**============================================================================== 1661144411Sscottl** 0x3b-0x35 : reserved 1662144411Sscottl**============================================================================== 1663144411Sscottl*/ 1664165155Sscottl/* 1665144411Sscottl**============================================================================== 1666144411Sscottl** 0x3d-0x3c : 1667144411Sscottl** 1668144411Sscottl** Bit Default Description 1669144411Sscottl** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts. 1670144411Sscottl** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'. 1671144411Sscottl**============================================================================== 1672144411Sscottl*/ 1673144411Sscottl#define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/ 1674144411Sscottl#define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/ 1675144411Sscottl/* 1676144411Sscottl**============================================================================== 1677144411Sscottl** 0x3f-0x3e : 1678144411Sscottl** Bit Default Description 1679144411Sscottl** 15:12 0h Reserved 1680144411Sscottl** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response 1681144411Sscottl** to a timer discard on either the primary or secondary interface. 1682144411Sscottl** 0b=SERR# is not asserted. 1683144411Sscottl** 1b=SERR# is asserted. 1684144411Sscottl** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires. 1685144411Sscottl** The delayed completion is then discarded. 1686165155Sscottl** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles 1687165155Sscottl** that bridge waits for an initiator on the secondary bus 1688165155Sscottl** to repeat a delayed transaction request. 1689165155Sscottl** The counter starts when the delayed transaction completion is ready 1690165155Sscottl** to be returned to the initiator. 1691165155Sscottl** When the initiator has not repeated the transaction 1692165155Sscottl** at least once before the counter expires,bridge 1693165155Sscottl** discards the delayed transaction from its queues. 1694144411Sscottl** 0b=The secondary master time-out counter is 2 15 PCI clock cycles. 1695144411Sscottl** 1b=The secondary master time-out counter is 2 10 PCI clock cycles. 1696165155Sscottl** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles 1697165155Sscottl** that bridge waits for an initiator on the primary bus 1698165155Sscottl** to repeat a delayed transaction request. 1699165155Sscottl** The counter starts when the delayed transaction completion 1700165155Sscottl** is ready to be returned to the initiator. 1701165155Sscottl** When the initiator has not repeated the transaction 1702165155Sscottl** at least once before the counter expires, 1703165155Sscottl** bridge discards the delayed transaction from its queues. 1704144411Sscottl** 0b=The primary master time-out counter is 2 15 PCI clock cycles. 1705144411Sscottl** 1b=The primary master time-out counter is 2 10 PCI clock cycles. 1706144411Sscottl** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions. 1707144411Sscottl** 06 0b Secondary Bus Reset (SBR): 1708165155Sscottl** When cleared to 0b: The bridge deasserts S_RST#, 1709165155Sscottl** when it had been asserted by writing this bit to a 1b. 1710144411Sscottl** When set to 1b: The bridge asserts S_RST#. 1711165155Sscottl** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus 1712165155Sscottl** when a master abort termination occurs in response to 1713165155Sscottl** a delayed transaction initiated by bridge on the target bus. 1714165155Sscottl** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction, 1715165155Sscottl** and returns FFFF FFFFh when a read. 1716165155Sscottl** 1b=When the transaction had not yet been completed on the initiator bus 1717165155Sscottl** (e.g.,delayed reads, or non-posted writes), 1718144411Sscottl** then bridge returns a Target Abort in response to the original requester 1719144411Sscottl** when it returns looking for its delayed completion on the initiator bus. 1720165155Sscottl** When the transaction had completed on the initiator bus (e.g., a PMW), 1721165155Sscottl** then bridge asserts P_SERR# (when enabled). 1722165155Sscottl** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort 1723165155Sscottl** while attempting to deliver a posted memory write on the destination bus. 1724165155Sscottl** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit 1725165155Sscottl** (also of this register), 1726144411Sscottl** and the VGA Palette Snoop Enable bit (Command Register). 1727165155Sscottl** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) 1728165155Sscottl** the VGA Aliasing bit for the corresponding enabled functionality,: 1729144411Sscottl** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses. 1730144411Sscottl** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses. 1731165155Sscottl** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), 1732165155Sscottl** then this bit has no impact on bridge behavior. 1733165155Sscottl** 03 0b VGA Enable: Setting this bit enables address decoding 1734165155Sscottl** and transaction forwarding of the following VGA transactions from the primary bus 1735165155Sscottl** to the secondary bus: 1736165155Sscottl** frame buffer memory addresses 000A0000h:000BFFFFh, 1737174451Sscottl** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=��0000h?** ?and AD[15:10] are either not decoded (i.e., don't cares), 1738165155Sscottl** or must be ��000000b�� 1739144411Sscottl** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register) 1740165155Sscottl** I/O and Memory Enable bits must be set in the Command register 1741165155Sscottl** to enable forwarding of VGA cycles. 1742165155Sscottl** 02 0b ISA Enable: Setting this bit enables special handling 1743165155Sscottl** for the forwarding of ISA I/O transactions that fall within the address range 1744165155Sscottl** specified by the I/O Base and Limit registers, 1745165155Sscottl** and are within the lowest 64Kbyte of the I/O address map 1746165155Sscottl** (i.e., 0000 0000h - 0000 FFFFh). 1747165155Sscottl** 0b=All I/O transactions that fall within the I/O Base 1748165155Sscottl** and Limit registers' specified range are forwarded 1749165155Sscottl** from primary to secondary unfiltered. 1750165155Sscottl** 1b=Blocks the forwarding from primary to secondary 1751165155Sscottl** of the top 768 bytes of each 1Kbyte alias. 1752165155Sscottl** On the secondary the top 768 bytes of each 1K alias 1753165155Sscottl** are inversely decoded and forwarded 1754165155Sscottl** from secondary to primary. 1755144411Sscottl** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion. 1756165155Sscottl** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected 1757165155Sscottl** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b). 1758165155Sscottl** 00 0b Parity Error Response: This bit controls bridge response to a parity error 1759165155Sscottl** that is detected on its secondary interface. 1760144411Sscottl** 0b=When a data parity error is detected bridge does not assert S_PERR#. 1761165155Sscottl** Also bridge does not assert P_SERR# in response to a detected address 1762165155Sscottl** or attribute parity error. 1763165155Sscottl** 1b=When a data parity error is detected bridge asserts S_PERR#. 1764165155Sscottl** The bridge also asserts P_SERR# (when enabled globally via bit(8) 1765165155Sscottl** of the Command register) 1766144411Sscottl** in response to a detected address or attribute parity error. 1767144411Sscottl**============================================================================== 1768144411Sscottl*/ 1769144411Sscottl#define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/ 1770144411Sscottl/* 1771144411Sscottl************************************************************************** 1772144411Sscottl** Device Specific Registers 40-A7h 1773144411Sscottl************************************************************************** 1774144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1775144411Sscottl** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1776144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1777144411Sscottl** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h 1778144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1779144411Sscottl** | Bridge Control 2 | Bridge Control 1 | 44h 1780144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1781144411Sscottl** | Reserved | Bridge Status | 48h 1782144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1783144411Sscottl** | Reserved | 4Ch 1784144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1785144411Sscottl** | Prefetch Policy | Multi-Transaction Timer | 50h 1786144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1787144411Sscottl** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h 1788144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1789144411Sscottl** | Reserved | Reserved | Secondary Decode Enable | 58h 1790144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1791144411Sscottl** | Reserved | Secondary IDSEL | 5Ch 1792144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1793144411Sscottl** | Reserved | 5Ch 1794144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1795144411Sscottl** | Reserved | 68h:CBh 1796144411Sscottl** ---------------------------------------------------------------------------------------------------------- 1797144411Sscottl************************************************************************** 1798144411Sscottl**============================================================================== 1799144411Sscottl** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR 1800144411Sscottl** Bit Default Description 1801165155Sscottl** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule 1802165155Sscottl** (PCI=16 clocks,PCI-X=6 clocks). 1803144411Sscottl** Note that this field is only meaningful when: 1804165155Sscottl** # Bit[11] of this register is set to 1b, 1805165155Sscottl** indicating that a Grant Time-out violation had occurred. 1806144411Sscottl** # bridge internal arbiter is enabled. 1807144411Sscottl** Bits[15:12] Violating Agent (REQ#/GNT# pair number) 1808144411Sscottl** 0000b REQ#/GNT#[0] 1809144411Sscottl** 0001b REQ#/GNT#[1] 1810144411Sscottl** 0010b REQ#/GNT#[2] 1811144411Sscottl** 0011b REQ#/GNT#[3] 1812144411Sscottl** 1111b Default Value (no violation detected) 1813144411Sscottl** When bit[11] is cleared by software, this field reverts back to its default value. 1814144411Sscottl** All other values are Reserved 1815144411Sscottl** 11 0b Grant Time-out Occurred: When set to 1b, 1816144411Sscottl** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents. 1817144411Sscottl** Software clears this bit by writing a 1b to it. 1818144411Sscottl** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus. 1819165155Sscottl** 1=During bus idle, bridge parks the bus on itself. 1820165155Sscottl** The bus grant is removed from the last master and internally asserted to bridge. 1821144411Sscottl** 09:08 00b Reserved 1822144411Sscottl** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 1823165155Sscottl** Each bit of this field assigns its corresponding secondary 1824165155Sscottl** bus master to either the high priority arbiter ring (1b) 1825165155Sscottl** or to the low priority arbiter ring (0b). 1826144411Sscottl** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 1827165155Sscottl** Bit [6] corresponds to the bridge internal secondary bus request 1828165155Sscottl** while Bit [7] corresponds to the SATU secondary bus request. 1829144411Sscottl** Bits [5:4] are unused. 1830144411Sscottl** 0b=Indicates that the master belongs to the low priority group. 1831144411Sscottl** 1b=Indicates that the master belongs to the high priority group 1832144411Sscottl**================================================================================= 1833144411Sscottl** 0x43: Bridge Control Register 0 - BCR0 1834144411Sscottl** Bit Default Description 1835165155Sscottl** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight 1836165155Sscottl** and the Posted Write data is limited to 4KB. 1837165155Sscottl** 1=Operation in fully dynamic queue mode. The bridge enqueues up to 1838165155Sscottl** 14 Posted Memory Write transactions and 8KB of posted write data. 1839144411Sscottl** 06:03 0H Reserved. 1840165155Sscottl** 02 0b Upstream Prefetch Disable: This bit disables bridge ability 1841165155Sscottl** to perform upstream prefetch operations for Memory 1842165155Sscottl** Read requests received on its secondary interface. 1843165155Sscottl** This bit also controls the bridge's ability to generate advanced read commands 1844165155Sscottl** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus 1845165155Sscottl** to a Conventional PCI bus. 1846165155Sscottl** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory. 1847165155Sscottl** The use of Memory Read Line and Memory Read 1848165155Sscottl** Multiple is enabled when forwarding a PCI-X Memory Read Block request 1849165155Sscottl** to an upstream bus operating in Conventional PCI mode. 1850165155Sscottl** 1b=bridge treats upstream PCI Memory Read requests as though 1851165155Sscottl** they target non-prefetchable memory and forwards upstream PCI-X Memory 1852165155Sscottl** Read Block commands as Memory Read 1853165155Sscottl** when the primary bus is operating 1854165155Sscottl** in Conventional PCI mode. 1855165155Sscottl** NOTE: This bit does not affect bridge ability to perform read prefetching 1856165155Sscottl** when the received command is Memory Read Line or Memory Read Multiple. 1857144411Sscottl**================================================================================= 1858144411Sscottl** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2) 1859144411Sscottl** Bit Default Description 1860144411Sscottl** 15:08 0000000b Reserved 1861165155Sscottl** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ��Alias�� commands, 1862165155Sscottl** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 1863165155Sscottl** The three options for handling these alias commands are to either pass it as is, 1864165155Sscottl** re-map to the actual block memory read/write command encoding, or ignore 1865165155Sscottl** the transaction forcing a Master Abort to occur on the Origination Bus. 1866144411Sscottl** Bit (7:6) Handling of command 1867144411Sscottl** 0 0 Re-map to Memory Read/Write Block before forwarding 1868144411Sscottl** 0 1 Enqueue and forward the alias command code unaltered 1869144411Sscottl** 1 0 Ignore the transaction, forcing Master Abort 1870144411Sscottl** 1 1 Reserved 1871144411Sscottl** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 1872144411Sscottl** The watchdog timers are used to detect prohibitively long latencies in the system. 1873144411Sscottl** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 1874144411Sscottl** or Split Requests (PCI-X mode) is not completed within 2 24 events 1875165155Sscottl** (��events�� are defined as PCI Clocks when operating in PCI-X mode, 1876165155Sscottl** and as the number of times being retried when operating in Conventional PCI mode) 1877144411Sscottl** 0b=All 2 24 watchdog timers are enabled. 1878165155Sscottl** 1b=All 2 24 watchdog timers are disabled and there is no limits to 1879165155Sscottl** the number of attempts bridge makes when initiating a PMW, 1880165155Sscottl** transacting a Delayed Transaction, or how long it waits for 1881165155Sscottl** a split completion corresponding to one of its requests. 1882144411Sscottl** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 1883144411Sscottl** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X. 1884165155Sscottl** 0b=The Secondary bus arbiter times out an agent 1885165155Sscottl** that does not assert FRAME# within 16/6 clocks of receiving its grant, 1886165155Sscottl** once the bus has gone idle. 1887144411Sscottl** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 1888165155Sscottl** An infringing agent does not receive a subsequent GNT# 1889165155Sscottl** until it de-asserts its REQ# for at least one clock cycle. 1890144411Sscottl** 1b=GNT# time-out mechanism is disabled. 1891144411Sscottl** 03 00b Reserved. 1892144411Sscottl** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism. 1893165155Sscottl** The time out mechanism is used to ensure that initiators 1894165155Sscottl** of delayed transactions return for their delayed completion data/status 1895165155Sscottl** within a reasonable amount of time after it is available from bridge. 1896165155Sscottl** 0b=The secondary master time-out counter is enabled 1897165155Sscottl** and uses the value specified by the Secondary Discard Timer bit 1898165155Sscottl** (see Bridge Control Register). 1899165155Sscottl** 1b=The secondary master time-out counter is disabled. 1900165155Sscottl** The bridge waits indefinitely for a secondary bus master 1901165155Sscottl** to repeat a delayed transaction. 1902165155Sscottl** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. 1903165155Sscottl** The time out mechanism is used to ensure that initiators 1904165155Sscottl** of delayed transactions return for their delayed completion data/status 1905165155Sscottl** within a reasonable amount of time after it is available from bridge. 1906165155Sscottl** 0b=The primary master time-out counter is enabled and uses the value specified 1907165155Sscottl** by the Primary Discard Timer bit (see Bridge Control Register). 1908165155Sscottl** 1b=The secondary master time-out counter is disabled. 1909165155Sscottl** The bridge waits indefinitely for a secondary bus master 1910165155Sscottl** to repeat a delayed transaction. 1911144411Sscottl** 00 0b Reserved 1912144411Sscottl**================================================================================= 1913144411Sscottl** 0x47-0x46: Bridge Control Register 2 - BCR2 1914144411Sscottl** Bit Default Description 1915144411Sscottl** 15:07 0000b Reserved. 1916165155Sscottl** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): 1917165155Sscottl** This bit disables all of the secondary PCI clock outputs including 1918165155Sscottl** the feedback clock S_CLKOUT. 1919144411Sscottl** This means that the user is required to provide an S_CLKIN input source. 1920144411Sscottl** 05:04 11 (66 MHz) Preserved. 1921144411Sscottl** 01 (100 MHz) 1922144411Sscottl** 00 (133 MHz) 1923144411Sscottl** 03:00 Fh (100 MHz & 66 MHz) 1924144411Sscottl** 7h (133 MHz) 1925144411Sscottl** This 4 bit field provides individual enable/disable mask bits for each of bridge 1926144411Sscottl** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0]) 1927144411Sscottl** default to being enabled following the rising edge of P_RST#, depending on the 1928144411Sscottl** frequency of the secondary bus clock: 1929165155Sscottl** �E Designs with 100 MHz (or lower) Secondary PCI clock power up with 1930165155Sscottl** all four S_CLKOs enabled by default. (SCLKO[3:0])�P 1931165155Sscottl** �E Designs with 133 MHz Secondary PCI clock power up 1932165155Sscottl** with the lower order 3 S_CLKOs enabled by default. 1933165155Sscottl** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected 1934165155Sscottl** to downstream device clock inputs. 1935144411Sscottl**================================================================================= 1936144411Sscottl** 0x49-0x48: Bridge Status Register - BSR 1937144411Sscottl** Bit Default Description 1938165155Sscottl** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 1939165155Sscottl** is conditionally asserted when the secondary discard timer expires. 1940144411Sscottl** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: 1941165155Sscottl** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1942165155Sscottl** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry. 1943165155Sscottl** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1944165155Sscottl** when bridge discards an upstream split read request 1945165155Sscottl** after waiting in excess of 2 24 clocks for the corresponding 1946165155Sscottl** Split Completion to arrive. 1947144411Sscottl** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: 1948165155Sscottl** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1949165155Sscottl** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry. 1950165155Sscottl** PCI-X Mode: This bit is set to a 1b and P_SERR# 1951165155Sscottl** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding 1952165155Sscottl** Split Completion to arrive. 1953165155Sscottl** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 1954165155Sscottl** is conditionally asserted when a Master Abort occurs as a result of an attempt, 1955165155Sscottl** by bridge, to retire a PMW upstream. 1956165155Sscottl** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 1957165155Sscottl** is conditionally asserted when a Target Abort occurs as a result of an attempt, 1958165155Sscottl** by bridge, to retire a PMW upstream. 1959165155Sscottl** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 1960165155Sscottl** is conditionally asserted when bridge discards an upstream PMW transaction 1961165155Sscottl** after receiving 2 24 target retries from the primary bus target 1962165155Sscottl** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 1963165155Sscottl** is conditionally asserted when a data parity error is detected by bridge 1964165155Sscottl** while attempting to retire a PMW upstream 1965165155Sscottl** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# 1966165155Sscottl** is conditionally asserted when bridge detects an address parity error on 1967165155Sscottl** the secondary bus. 1968165155Sscottl** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 1969165155Sscottl** is conditionally asserted when the primary bus discard timer expires. 1970144411Sscottl** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: 1971165155Sscottl** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1972165155Sscottl** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries 1973165155Sscottl** from the secondary bus target. 1974165155Sscottl** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1975165155Sscottl** when bridge discards a downstream split read request 1976165155Sscottl** after waiting in excess of 2 24 clocks for the corresponding 1977165155Sscottl** Split Completion to arrive. 1978144411Sscottl** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired: 1979165155Sscottl** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1980165155Sscottl** when bridge discards a downstream delayed write transaction request 1981165155Sscottl** after receiving 2 24 target retries from the secondary bus target. 1982165155Sscottl** PCI-X Mode: This bit is set to a 1b and P_SERR# 1983165155Sscottl** is conditionally asserted when bridge discards a downstream 1984165155Sscottl** split write request after waiting in excess of 2 24 clocks 1985165155Sscottl** for the corresponding Split Completion to arrive. 1986165155Sscottl** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# 1987165155Sscottl** is conditionally asserted when a Master Abort occurs as a result of an attempt, 1988165155Sscottl** by bridge, to retire a PMW downstream. 1989165155Sscottl** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted 1990165155Sscottl** when a Target Abort occurs as a result of an attempt, by bridge, 1991165155Sscottl** to retire a PMW downstream. 1992165155Sscottl** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 1993165155Sscottl** is conditionally asserted when bridge discards a downstream PMW transaction 1994165155Sscottl** after receiving 2 24 target retries from the secondary bus target 1995165155Sscottl** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 1996165155Sscottl** is conditionally asserted when a data parity error is detected by bridge 1997165155Sscottl** while attempting to retire a PMW downstream. 1998165155Sscottl** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted 1999165155Sscottl** when bridge detects an address parity error on the primary bus. 2000144411Sscottl**================================================================================== 2001144411Sscottl** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR 2002144411Sscottl** Bit Default Description 2003144411Sscottl** 15:13 000b Reserved 2004165155Sscottl** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks) 2005165155Sscottl** that a secondary bus master has its grant maintained in order to enable 2006165155Sscottl** multiple transactions to execute within the same arbitration cycle. 2007144411Sscottl** Bit[02:00] GNT# Extended Duration 2008144411Sscottl** 000 MTT Disabled (Default=no GNT# extension) 2009144411Sscottl** 001 16 clocks 2010144411Sscottl** 010 32 clocks 2011144411Sscottl** 011 64 clocks 2012144411Sscottl** 100 128 clocks 2013144411Sscottl** 101 256 clocks 2014144411Sscottl** 110 Invalid (treated as 000) 2015144411Sscottl** 111 Invalid (treated as 000) 2016144411Sscottl** 09:08 00b Reserved 2017165155Sscottl** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# 2018165155Sscottl** pair supported by bridge secondary arbiter. 2019144411Sscottl** Bit(7) corresponds to SATU internal REQ#/GNT# pair, 2020144411Sscottl** bit(6) corresponds to bridge internal REQ#/GNT# pair, 2021144411Sscottl** bit(5) corresponds to REQ#/GNT#(5) pair, etc. 2022165155Sscottl** When a given bit is set to 1b, its corresponding REQ#/GNT# 2023165155Sscottl** pair is enabled for MTT functionality as determined by bits(12:10) of this register. 2024144411Sscottl** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT. 2025144411Sscottl**================================================================================== 2026144411Sscottl** 0x53-0x52: Read Prefetch Policy Register - RPPR 2027144411Sscottl** Bit Default Description 2028165155Sscottl** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor 2029165155Sscottl** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied 2030165155Sscottl** using the FirstRead parameter. 2031165155Sscottl** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 2032165155Sscottl** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines 2033165155Sscottl** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating 2034165155Sscottl** the number of bytes to prefetch from the secondary bus interface 2035165155Sscottl** on the initial PreFetch operation. 2036165155Sscottl** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 2037165155Sscottl** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 2038165155Sscottl** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 2039165155Sscottl** in calculating the number of bytes to prefetch from the primary 2040165155Sscottl** bus interface on subsequent PreFetch operations given 2041165155Sscottl** that the read demands were not satisfied using 2042165155Sscottl** the FirstRead parameter. 2043165155Sscottl** The default value of 010b correlates to: Command Type Hardwired pre-fetch a 2044165155Sscottl** mount Memory Read 3 cache lines Memory Read Line 3 cache lines 2045165155Sscottl** Memory Read Multiple 6 cache lines 2046165155Sscottl** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 2047165155Sscottl** in calculating the number of bytes to prefetch from 2048165155Sscottl** the primary bus interface on the initial PreFetch operation. 2049165155Sscottl** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount 2050165155Sscottl** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 2051165155Sscottl** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch 2052165155Sscottl** algorithm for the secondary and the primary bus interfaces. 2053144411Sscottl** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual 2054165155Sscottl** enable bits for REQ#/GNT#[2:0]. 2055165155Sscottl** (bit(2) is the enable bit for REQ#/GNT#[2], etc...) 2056144411Sscottl** 1b: enables the staged pre-fetch feature 2057144411Sscottl** 0b: disables staged pre-fetch, 2058144411Sscottl** and hardwires read pre-fetch policy to the following for 2059144411Sscottl** Memory Read, 2060144411Sscottl** Memory Read Line, 2061144411Sscottl** and Memory Read Multiple commands: 2062144411Sscottl** Command Type Hardwired Pre-Fetch Amount... 2063144411Sscottl** Memory Read 4 DWORDs 2064144411Sscottl** Memory Read Line 1 cache line 2065144411Sscottl** Memory Read Multiple 2 cache lines 2066165155Sscottl** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands 2067165155Sscottl** only to the next higher cache line boundary.For non-cache line aligned Memory Read 2068165155Sscottl** Multiple commands bridge pre-fetches only to the second cache line boundary encountered. 2069144411Sscottl**================================================================================== 2070144411Sscottl** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL 2071144411Sscottl** Bit Default Description 2072165155Sscottl** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior 2073165155Sscottl** in response to its discarding of a delayed transaction that was initiated from the primary bus. 2074144411Sscottl** 0b=bridge asserts P_SERR#. 2075144411Sscottl** 1b=bridge does not assert P_SERR# 2076144411Sscottl** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2077144411Sscottl** 0b=bridge asserts P_SERR#. 2078144411Sscottl** 1b=bridge does not assert P_SERR# 2079144411Sscottl** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2080144411Sscottl** 0b=bridge asserts P_SERR#. 2081144411Sscottl** 1b=bridge does not assert P_SERR# 2082165155Sscottl** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following 2083165155Sscottl** its having detected a Master Abort while attempting to retire one of its PMWs upstream. 2084144411Sscottl** 0b=bridge asserts P_SERR#. 2085144411Sscottl** 1b=bridge does not assert P_SERR# 2086165155Sscottl** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following 2087165155Sscottl** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream. 2088144411Sscottl** 0b=bridge asserts P_SERR#. 2089144411Sscottl** 1b=bridge does not assert P_SERR# 2090165155Sscottl** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that 2091165155Sscottl** it discards an upstream posted write transaction. 2092144411Sscottl** 0b=bridge asserts P_SERR#. 2093144411Sscottl** 1b=bridge does not assert P_SERR# 2094165155Sscottl** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior 2095165155Sscottl** when a data parity error is detected while attempting to retire on of its PMWs upstream. 2096144411Sscottl** 0b=bridge asserts P_SERR#. 2097144411Sscottl** 1b=bridge does not assert P_SERR# 2098165155Sscottl** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior 2099165155Sscottl** when it detects an address parity error on the secondary bus. 2100144411Sscottl** 0b=bridge asserts P_SERR#. 2101144411Sscottl** 1b=bridge does not assert P_SERR# 2102165155Sscottl** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to 2103165155Sscottl** its discarding of a delayed transaction that was initiated on the secondary bus. 2104144411Sscottl** 0b=bridge asserts P_SERR#. 2105144411Sscottl** 1b=bridge does not assert P_SERR# 2106144411Sscottl** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2107144411Sscottl** 0b=bridge asserts P_SERR#. 2108144411Sscottl** 1b=bridge does not assert P_SERR# 2109144411Sscottl** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2110144411Sscottl** 0b=bridge asserts P_SERR#. 2111144411Sscottl** 1b=bridge does not assert P_SERR# 2112165155Sscottl** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following 2113165155Sscottl** its having detected a Master Abort while attempting to retire one of its PMWs downstream. 2114144411Sscottl** 0b=bridge asserts P_SERR#. 2115144411Sscottl** 1b=bridge does not assert P_SERR# 2116165155Sscottl** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following 2117165155Sscottl** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream. 2118144411Sscottl** 0b=bridge asserts P_SERR#. 2119144411Sscottl** 1b=bridge does not assert P_SERR# 2120165155Sscottl** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event 2121165155Sscottl** that it discards a downstream posted write transaction. 2122144411Sscottl** 0b=bridge asserts P_SERR#. 2123144411Sscottl** 1b=bridge does not assert P_SERR# 2124165155Sscottl** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior 2125165155Sscottl** when a data parity error is detected while attempting to retire on of its PMWs downstream. 2126144411Sscottl** 0b=bridge asserts P_SERR#. 2127144411Sscottl** 1b=bridge does not assert P_SERR# 2128165155Sscottl** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior 2129165155Sscottl** when it detects an address parity error on the primary bus. 2130144411Sscottl** 0b=bridge asserts P_SERR#. 2131144411Sscottl** 1b=bridge does not assert P_SERR# 2132144411Sscottl**=============================================================================== 2133144411Sscottl** 0x56: Pre-Boot Status Register - PBSR 2134144411Sscottl** Bit Default Description 2135144411Sscottl** 07 1 Reserved 2136144411Sscottl** 06 - Reserved - value indeterminate 2137144411Sscottl** 05:02 0 Reserved 2138165155Sscottl** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting: 2139165155Sscottl** This bit reflect captured S_133EN strap, 2140165155Sscottl** indicating the maximum secondary bus clock frequency when in PCI-X mode. 2141144411Sscottl** Max Allowable Secondary Bus Frequency 2142165155Sscottl** ** S_133EN PCI-X Mode 2143165155Sscottl** ** 0 100 MHz 2144165155Sscottl** ** 1 133 MH 2145144411Sscottl** 00 0b Reserved 2146144411Sscottl**=============================================================================== 2147144411Sscottl** 0x59-0x58: Secondary Decode Enable Register - SDER 2148144411Sscottl** Bit Default Description 2149144411Sscottl** 15:03 FFF1h Preserved. 2150165155Sscottl** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set, 2151165155Sscottl** bridge overrides its secondary inverse decode logic and not 2152144411Sscottl** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b. 2153165155Sscottl** This creates a private memory space on the Secondary PCI bus 2154165155Sscottl** that allows peer-to-peer transactions. 2155144411Sscottl** 01:00 10 2 Preserved. 2156144411Sscottl**=============================================================================== 2157144411Sscottl** 0x5D-0x5C: Secondary IDSEL Select Register - SISR 2158144411Sscottl** Bit Default Description 2159144411Sscottl** 15:10 000000 2 Reserved. 2160165155Sscottl** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set, 2161165155Sscottl** AD25 is deasserted for any possible Type 1 to Type 0 conversion. 2162165155Sscottl** When this bit is clear, 2163165155Sscottl** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion. 2164165155Sscottl** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set, 2165165155Sscottl** AD24 is deasserted for any possible Type 1 to Type 0 conversion. 2166165155Sscottl** When this bit is clear, 2167165155Sscottl** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion. 2168165155Sscottl** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set, 2169165155Sscottl** AD23 is deasserted for any possible Type 1 to Type 0 conversion. 2170165155Sscottl** When this bit is clear, 2171165155Sscottl** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion. 2172165155Sscottl** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set, 2173165155Sscottl** AD22 is deasserted for any possible Type 1 to Type 0 conversion. 2174165155Sscottl** When this bit is clear, 2175165155Sscottl** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion. 2176165155Sscottl** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set, 2177165155Sscottl** AD21 is deasserted for any possible Type 1 to Type 0 conversion. 2178165155Sscottl** When this bit is clear, 2179165155Sscottl** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion. 2180165155Sscottl** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set, 2181165155Sscottl** AD20 is deasserted for any possible Type 1 to Type 0 conversion. 2182165155Sscottl** When this bit is clear, 2183165155Sscottl** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion. 2184165155Sscottl** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set, 2185165155Sscottl** AD19 is deasserted for any possible Type 1 to Type 0 conversion. 2186165155Sscottl** When this bit is clear, 2187165155Sscottl** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion. 2188165155Sscottl** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set, 2189165155Sscottl** AD18 is deasserted for any possible Type 1 to Type 0 conversion. 2190165155Sscottl** When this bit is clear, 2191165155Sscottl** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion. 2192165155Sscottl** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set, 2193165155Sscottl** AD17 is deasserted for any possible Type 1 to Type 0 conversion. 2194165155Sscottl** When this bit is clear, 2195165155Sscottl** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion. 2196165155Sscottl** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set, 2197165155Sscottl** AD16 is deasserted for any possible Type 1 to Type 0 conversion. 2198165155Sscottl** When this bit is clear, 2199165155Sscottl** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion. 2200144411Sscottl************************************************************************** 2201144411Sscottl*/ 2202144411Sscottl/* 2203144411Sscottl************************************************************************** 2204144411Sscottl** Reserved A8-CBh 2205144411Sscottl************************************************************************** 2206144411Sscottl*/ 2207144411Sscottl/* 2208144411Sscottl************************************************************************** 2209144411Sscottl** PCI Extended Enhanced Capabilities List CC-FFh 2210144411Sscottl************************************************************************** 2211144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2212144411Sscottl** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 2213144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2214144411Sscottl** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh 2215144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2216144411Sscottl** | PM Data | PPB Support | Extensions Power Management CSR | E0h 2217144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2218144411Sscottl** | Reserved | Reserved | Reserved | E4h 2219144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2220144411Sscottl** | Reserved | E8h 2221144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2222144411Sscottl** | Reserved | Reserved | Reserved | Reserved | ECh 2223144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2224144411Sscottl** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h 2225144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2226144411Sscottl** | PCI-X Bridge Status | F4h 2227144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2228144411Sscottl** | PCI-X Upstream Split Transaction Control | F8h 2229144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2230144411Sscottl** | PCI-X Downstream Split Transaction Control | FCh 2231144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2232144411Sscottl**=============================================================================== 2233144411Sscottl** 0xDC: Power Management Capabilities Identifier - PM_CAPID 2234144411Sscottl** Bit Default Description 2235144411Sscottl** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block 2236144411Sscottl**=============================================================================== 2237144411Sscottl** 0xDD: Next Item Pointer - PM_NXTP 2238144411Sscottl** Bit Default Description 2239144411Sscottl** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header. 2240144411Sscottl**=============================================================================== 2241144411Sscottl** 0xDF-0xDE: Power Management Capabilities Register - PMCR 2242144411Sscottl** Bit Default Description 2243144411Sscottl** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge. 2244144411Sscottl** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state. 2245144411Sscottl** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state. 2246144411Sscottl** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 2247144411Sscottl** This returns 000b as PME# wake-up for bridge is not implemented. 2248144411Sscottl** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge. 2249144411Sscottl** 04:03 00 Reserved 2250144411Sscottl** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1. 2251144411Sscottl**=============================================================================== 2252144411Sscottl** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR 2253144411Sscottl** Bit Default Description 2254144411Sscottl** 15:09 00h Reserved 2255165155Sscottl** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#. 2256165155Sscottl** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug. 2257144411Sscottl** 07:02 00h Reserved 2258165155Sscottl** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of 2259165155Sscottl** a function and to set the Function into a new power state. 2260144411Sscottl** 00 - D0 state 2261144411Sscottl** 01 - D1 state 2262144411Sscottl** 10 - D2 state 2263144411Sscottl** 11 - D3 hot state 2264144411Sscottl**=============================================================================== 2265144411Sscottl** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE 2266144411Sscottl** Bit Default Description 2267144411Sscottl** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled. 2268165155Sscottl** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that 2269165155Sscottl** is to occur as a direct result of programming the function to D3 hot. 2270144411Sscottl** This bit is only meaningful when bit 7 (BPCC_En) is a ��1��. 2271144411Sscottl** 05:00 00h Reserved 2272144411Sscottl**=============================================================================== 2273144411Sscottl** 0xE3: Power Management Data Register - PMDR 2274144411Sscottl** Bit Default Description 2275144411Sscottl** 07:00 00h Reserved 2276144411Sscottl**=============================================================================== 2277144411Sscottl** 0xF0: PCI-X Capabilities Identifier - PX_CAPID 2278144411Sscottl** Bit Default Description 2279144411Sscottl** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list. 2280144411Sscottl**=============================================================================== 2281144411Sscottl** 0xF1: Next Item Pointer - PX_NXTP 2282144411Sscottl** Bit Default Description 2283144411Sscottl** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this 2284144411Sscottl** register is 00h indicating that this is the last entry in the linked list of capabilities. 2285144411Sscottl**=============================================================================== 2286144411Sscottl** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS 2287144411Sscottl** Bit Default Description 2288144411Sscottl** 15:09 00h Reserved 2289144411Sscottl** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 2290144411Sscottl** The values are: 2291165155Sscottl** ** BitsMax FrequencyClock Period 2292165155Sscottl** ** 000PCI ModeN/A 2293165155Sscottl** ** 00166 15 2294165155Sscottl** ** 01010010 2295165155Sscottl** ** 0111337.5 2296165155Sscottl** ** 1xxreservedreserved 2297165155Sscottl** ** The default value for this register is the operating frequency of the secondary bus 2298144411Sscottl** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the 2299165155Sscottl** secondary bus to the primary bus because there is not enough room within the limit 2300165155Sscottl** specified in the Split Transaction Commitment Limit field in the Downstream Split 2301165155Sscottl** Transaction Control register. The bridge does not set this bit. 2302165155Sscottl** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full. 2303165155Sscottl** The bridge does not set this bit. 2304165155Sscottl** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID 2305165155Sscottl** equal to bridge secondary bus number, device number 00h, 2306165155Sscottl** and function number 0 is received on the secondary interface. 2307165155Sscottl** This bit is cleared by software writing a '1'. 2308165155Sscottl** 02 0b Split Completion Discarded (SCD): This bit is set 2309165155Sscottl** when bridge discards a split completion moving toward the secondary bus 2310165155Sscottl** because the requester would not accept it. This bit cleared by software writing a '1'. 2311144411Sscottl** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz 2312144411Sscottl** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits. 2313144411Sscottl**=============================================================================== 2314144411Sscottl** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS 2315144411Sscottl** Bit Default Description 2316144411Sscottl** 31:22 0 Reserved 2317165155Sscottl** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge. 2318165155Sscottl** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge 2319165155Sscottl** because bridge throttles traffic on the completion side. 2320165155Sscottl** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b 2321165155Sscottl** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears 2322165155Sscottl** this bit by writing a 1b to it. 2323165155Sscottl** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b 2324165155Sscottl** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it. 2325165155Sscottl** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode. 2326165155Sscottl** 0=The maximum operating frequency is 66 MHz. 2327165155Sscottl** 1=The maximum operating frequency is 133 MHz. 2328144411Sscottl** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface. 2329165155Sscottl** 0=Primary Interface is connected as a 32-bit PCI bus. 2330165155Sscottl** 1=Primary Interface is connected as a 64-bit PCI bus. 2331165155Sscottl** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field 2332165155Sscottl** of the BNUM register at offset 18h. 2333165155Sscottl** Apparently it was deemed necessary reflect it here for diagnostic purposes. 2334165155Sscottl** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes. 2335165155Sscottl** May be updated whenever a PCI-X 2336165155Sscottl** configuration write cycle that targets bridge scores a hit. 2337144411Sscottl** 02:00 0h Function Number (FNUM): The bridge Function # 2338144411Sscottl**=============================================================================== 2339144411Sscottl** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC 2340144411Sscottl** Bit Default Description 2341144411Sscottl** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2342144411Sscottl** Software is permitted to program this register to any value greater than or equal to 2343144411Sscottl** the contents of the Split Transaction Capacity register. A value less than the contents 2344144411Sscottl** of the Split Transaction Capacity register causes unspecified results. 2345144411Sscottl** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2346144411Sscottl** size regardless of the amount of buffer space available. 2347144411Sscottl** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2348165155Sscottl** split completions. This register controls behavior of the bridge buffers for forwarding 2349165155Sscottl** Split Transactions from a primary bus requester to a secondary bus completer. 2350165155Sscottl** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes). 2351144411Sscottl**=============================================================================== 2352144411Sscottl** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC 2353144411Sscottl** Bit Default Description 2354144411Sscottl** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2355165155Sscottl** Software is permitted to program this register to any value greater than or equal to 2356165155Sscottl** the contents of the Split Transaction Capacity register. A value less than the contents 2357165155Sscottl** of the Split Transaction Capacity register causes unspecified results. 2358165155Sscottl** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2359165155Sscottl** size regardless of the amount of buffer space available. 2360144411Sscottl** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2361144411Sscottl** split completions. This register controls behavior of the bridge buffers for forwarding 2362144411Sscottl** Split Transactions from a primary bus requester to a secondary bus completer. 2363165155Sscottl** The default value of 003Eh indicates there is available buffer space for 62 ADQs 2364165155Sscottl** (7936 bytes). 2365144411Sscottl************************************************************************** 2366144411Sscottl*/ 2367144411Sscottl 2368144411Sscottl 2369144411Sscottl 2370144411Sscottl 2371144411Sscottl/* 2372144411Sscottl************************************************************************************************************************************* 2373144411Sscottl** 80331 Address Translation Unit Register Definitions 2374144411Sscottl** ATU Interface Configuration Header Format 2375144411Sscottl** The ATU is programmed via a [Type 0] configuration command on the PCI interface. 2376144411Sscottl************************************************************************************************************************************* 2377144411Sscottl** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset 2378144411Sscottl**=================================================================================================================================== 2379144411Sscottl** | ATU Device ID | Vendor ID | 00h 2380144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2381144411Sscottl** | Status | Command | 04H 2382144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2383144411Sscottl** | ATU Class Code | Revision ID | 08H 2384144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2385144411Sscottl** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH 2386144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2387144411Sscottl** | Inbound ATU Base Address 0 | 10H 2388144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2389144411Sscottl** | Inbound ATU Upper Base Address 0 | 14H 2390144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2391144411Sscottl** | Inbound ATU Base Address 1 | 18H 2392144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2393144411Sscottl** | Inbound ATU Upper Base Address 1 | 1CH 2394144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2395144411Sscottl** | Inbound ATU Base Address 2 | 20H 2396144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2397144411Sscottl** | Inbound ATU Upper Base Address 2 | 24H 2398144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2399144411Sscottl** | Reserved | 28H 2400144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2401144411Sscottl** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH 2402144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2403144411Sscottl** | Expansion ROM Base Address | 30H 2404144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2405144411Sscottl** | Reserved Capabilities Pointer | 34H 2406144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2407144411Sscottl** | Reserved | 38H 2408144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2409144411Sscottl** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH 2410144411Sscottl** ---------------------------------------------------------------------------------------------------------- 2411144411Sscottl********************************************************************************************************************* 2412144411Sscottl*/ 2413144411Sscottl/* 2414144411Sscottl*********************************************************************************** 2415144411Sscottl** ATU Vendor ID Register - ATUVID 2416144411Sscottl** ----------------------------------------------------------------- 2417144411Sscottl** Bit Default Description 2418165155Sscottl** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel. 2419165155Sscottl** This register, combined with the DID, uniquely identify the PCI device. 2420165155Sscottl** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID 2421165155Sscottl** to simulate the interface of a standard mechanism currently used by existing application software. 2422144411Sscottl*********************************************************************************** 2423144411Sscottl*/ 2424144411Sscottl#define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/ 2425144411Sscottl/* 2426144411Sscottl*********************************************************************************** 2427144411Sscottl** ATU Device ID Register - ATUDID 2428144411Sscottl** ----------------------------------------------------------------- 2429144411Sscottl** Bit Default Description 2430165155Sscottl** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU. 2431165155Sscottl** This ID, combined with the VID, uniquely identify any PCI device. 2432144411Sscottl*********************************************************************************** 2433144411Sscottl*/ 2434144411Sscottl#define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/ 2435144411Sscottl/* 2436144411Sscottl*********************************************************************************** 2437144411Sscottl** ATU Command Register - ATUCMD 2438144411Sscottl** ----------------------------------------------------------------- 2439144411Sscottl** Bit Default Description 2440144411Sscottl** 15:11 000000 2 Reserved 2441144411Sscottl** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal. 2442144411Sscottl** 0=enables the assertion of interrupt signal. 2443144411Sscottl** 1=disables the assertion of its interrupt signal. 2444165155Sscottl** 09 0 2 Fast Back to Back Enable - When cleared, 2445165155Sscottl** the ATU interface is not allowed to generate fast back-to-back cycles on its bus. 2446165155Sscottl** Ignored when operating in the PCI-X mode. 2447144411Sscottl** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface. 2448144411Sscottl** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The 2449165155Sscottl** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles 2450165155Sscottl** of address stepping for PCI-X mode. 2451165155Sscottl** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error 2452165155Sscottl** is detected. When cleared, parity checking is disabled. 2453165155Sscottl** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, 2454165155Sscottl** does not perform VGA palette snooping. 2455165155Sscottl** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. 2456165155Sscottl** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode. 2457165155Sscottl** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. 2458165155Sscottl** Not implemented and a reserved bit field. 2459165155Sscottl** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus. 2460165155Sscottl** When cleared, disables the device from generating PCI accesses. 2461165155Sscottl** When set, allows the device to behave as a PCI bus master. 2462165155Sscottl** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless 2463165155Sscottl** of the state of this bit. 2464165155Sscottl** 01 0 2 Memory Enable - Controls the ATU interface��s response to PCI memory addresses. 2465165155Sscottl** When cleared, the ATU interface does not respond to any memory access on the PCI bus. 2466165155Sscottl** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions. 2467165155Sscottl** Not implemented and a reserved bit field. 2468144411Sscottl*********************************************************************************** 2469144411Sscottl*/ 2470144411Sscottl#define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/ 2471144411Sscottl/* 2472144411Sscottl*********************************************************************************** 2473144411Sscottl** ATU Status Register - ATUSR (Sheet 1 of 2) 2474144411Sscottl** ----------------------------------------------------------------- 2475144411Sscottl** Bit Default Description 2476144411Sscottl** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even 2477165155Sscottl** when the ATUCMD register��s Parity Error Response bit is cleared. Set under the following conditions: 2478144411Sscottl** �E Write Data Parity Error when the ATU is a target (inbound write). 2479144411Sscottl** �E Read Data Parity Error when the ATU is a requester (outbound read). 2480165155Sscottl** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU). 2481144411Sscottl** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU. 2482144411Sscottl** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort 2483144411Sscottl** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode. 2484144411Sscottl** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target 2485144411Sscottl** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode. 2486165155Sscottl** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target, 2487165155Sscottl** terminates the transaction on the PCI bus with a target abort. 2488165155Sscottl** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# 2489165155Sscottl** timing for a target device in Conventional PCI Mode regardless of the operating mode 2490165155Sscottl** (except configuration accesses). 2491144411Sscottl** 00 2=Fast 2492144411Sscottl** 01 2=Medium 2493144411Sscottl** 10 2=Slow 2494144411Sscottl** 11 2=Reserved 2495144411Sscottl** The ATU interface uses Medium timing. 2496144411Sscottl** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions: 2497144411Sscottl** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 2498165155Sscottl** �E And the ATU acted as the requester 2499165155Sscottl** for the operation in which the error occurred. 2500144411Sscottl** �E And the ATUCMD register��s Parity Error Response bit is set 2501144411Sscottl** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 2502144411Sscottl** �E And the ATUCMD register��s Parity Error Response bit is set 2503144411Sscottl** 07 1 2 (Conventional mode) 2504144411Sscottl** 0 2 (PCI-X mode) 2505165155Sscottl** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back 2506165155Sscottl** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast 2507165155Sscottl** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode. 2508144411Sscottl** 06 0 2 UDF Supported - User Definable Features are not supported 2509144411Sscottl** 05 1 2 66 MHz. Capable - 66 MHz operation is supported. 2510144411Sscottl** 04 1 2 Capabilities - When set, this function implements extended capabilities. 2511165155Sscottl** 03 0 Interrupt Status - reflects the state of the ATU interrupt 2512165155Sscottl** when the Interrupt Disable bit in the command register is a 0. 2513144411Sscottl** 0=ATU interrupt signal deasserted. 2514144411Sscottl** 1=ATU interrupt signal asserted. 2515165155Sscottl** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to 2516165155Sscottl** Section 3.10.23, ��ATU Interrupt Pin Register - ATUIPR�� on page 236 for details on the ATU 2517144411Sscottl** interrupt signal. 2518144411Sscottl** 02:00 00000 2 Reserved. 2519144411Sscottl*********************************************************************************** 2520144411Sscottl*/ 2521144411Sscottl#define ARCMSR_ATU_STATUS_REG 0x06 /*word*/ 2522144411Sscottl/* 2523144411Sscottl*********************************************************************************** 2524144411Sscottl** ATU Revision ID Register - ATURID 2525144411Sscottl** ----------------------------------------------------------------- 2526144411Sscottl** Bit Default Description 2527144411Sscottl** 07:00 00H ATU Revision - identifies the 80331 revision number. 2528144411Sscottl*********************************************************************************** 2529144411Sscottl*/ 2530144411Sscottl#define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/ 2531144411Sscottl/* 2532144411Sscottl*********************************************************************************** 2533144411Sscottl** ATU Class Code Register - ATUCCR 2534144411Sscottl** ----------------------------------------------------------------- 2535144411Sscottl** Bit Default Description 2536144411Sscottl** 23:16 05H Base Class - Memory Controller 2537144411Sscottl** 15:08 80H Sub Class - Other Memory Controller 2538144411Sscottl** 07:00 00H Programming Interface - None defined 2539144411Sscottl*********************************************************************************** 2540144411Sscottl*/ 2541144411Sscottl#define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/ 2542144411Sscottl/* 2543144411Sscottl*********************************************************************************** 2544144411Sscottl** ATU Cacheline Size Register - ATUCLSR 2545144411Sscottl** ----------------------------------------------------------------- 2546144411Sscottl** Bit Default Description 2547144411Sscottl** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs. 2548144411Sscottl*********************************************************************************** 2549144411Sscottl*/ 2550144411Sscottl#define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/ 2551144411Sscottl/* 2552144411Sscottl*********************************************************************************** 2553144411Sscottl** ATU Latency Timer Register - ATULT 2554144411Sscottl** ----------------------------------------------------------------- 2555144411Sscottl** Bit Default Description 2556165155Sscottl** 07:03 00000 2 (for Conventional mode) 2557165155Sscottl** 01000 2 (for PCI-X mode) 2558165155Sscottl** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks. 2559165155Sscottl** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode. 2560165155Sscottl** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer. 2561144411Sscottl*********************************************************************************** 2562144411Sscottl*/ 2563144411Sscottl#define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/ 2564144411Sscottl/* 2565144411Sscottl*********************************************************************************** 2566144411Sscottl** ATU Header Type Register - ATUHTR 2567144411Sscottl** ----------------------------------------------------------------- 2568144411Sscottl** Bit Default Description 2569144411Sscottl** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device. 2570144411Sscottl** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface 2571144411Sscottl** header conforms to PCI Local Bus Specification, Revision 2.3. 2572144411Sscottl*********************************************************************************** 2573144411Sscottl*/ 2574144411Sscottl#define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/ 2575144411Sscottl/* 2576144411Sscottl*********************************************************************************** 2577144411Sscottl** ATU BIST Register - ATUBISTR 2578144411Sscottl** 2579144411Sscottl** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is 2580144411Sscottl** initiated. This register is the interface between the host processor requesting BIST functions and 2581144411Sscottl** the 80331 replying with the results from the software implementation of the BIST functionality. 2582144411Sscottl** ----------------------------------------------------------------- 2583144411Sscottl** Bit Default Description 2584144411Sscottl** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 2585144411Sscottl** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set: 2586165155Sscottl** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function. 2587165155Sscottl** The Intel XScale core clears this bit when the BIST software has completed with the BIST results 2588165155Sscottl** found in ATUBISTR register bits [3:0]. 2589165155Sscottl** When the ATUCR BIST Interrupt Enable bit is clear: 2590165155Sscottl** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 2591144411Sscottl** The Intel XScale core does not clear this bit. 2592165155Sscottl** 05:04 00 2 Reserved 2593165155Sscottl** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6): 2594165155Sscottl** The Intel XScale core places the results of the software BIST in these bits. 2595165155Sscottl** A nonzero value indicates a device-specific error. 2596144411Sscottl*********************************************************************************** 2597144411Sscottl*/ 2598144411Sscottl#define ARCMSR_ATU_BIST_REG 0x0F /*byte*/ 2599144411Sscottl 2600144411Sscottl/* 2601144411Sscottl*************************************************************************************** 2602144411Sscottl** ATU Base Registers and Associated Limit Registers 2603144411Sscottl*************************************************************************************** 2604144411Sscottl** Base Address Register Limit Register Description 2605144411Sscottl** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus. 2606165155Sscottl** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs. 2607144411Sscottl** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus. 2608165155Sscottl** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs. 2609144411Sscottl** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus. 2610165155Sscottl** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs. 2611144411Sscottl** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus. 2612165155Sscottl** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs. 2613165155Sscottl** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH). 2614165155Sscottl** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading ** from an Expansion ROM. 2615144411Sscottl**-------------------------------------------------------------------------------------- 2616144411Sscottl** ATU Inbound Window 1 is not a translate window. 2617144411Sscottl** The ATU does not claim any PCI accesses that fall within this range. 2618144411Sscottl** This window is used to allocate host memory for use by Private Devices. 2619144411Sscottl** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 2620144411Sscottl*********************************************************************************** 2621144411Sscottl*/ 2622144411Sscottl 2623144411Sscottl/* 2624144411Sscottl*********************************************************************************** 2625144411Sscottl** Inbound ATU Base Address Register 0 - IABAR0 2626144411Sscottl** 2627165155Sscottl** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) 2628165155Sscottl** defines the block of memory addresses where the inbound translation window 0 begins. 2629144411Sscottl** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2630144411Sscottl** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size. 2631144411Sscottl** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 2632144411Sscottl** depending on the value located within the IALR0. 2633144411Sscottl** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification. 2634144411Sscottl** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit. 2635144411Sscottl** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2636144411Sscottl** Warning: 2637144411Sscottl** When IALR0 is cleared prior to host configuration: 2638144411Sscottl** the user should also clear the Prefetchable Indicator and the Type Indicator. 2639144411Sscottl** Assuming IALR0 is not cleared: 2640144411Sscottl** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2641144411Sscottl** when the Prefetchable Indicator is cleared prior to host configuration, 2642144411Sscottl** the user should also set the Type Indicator for 32 bit addressability. 2643144411Sscottl** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification, 2644144411Sscottl** when the Prefetchable Indicator is set prior to host configuration, the user 2645144411Sscottl** should also set the Type Indicator for 64 bit addressability. 2646144411Sscottl** This is the default for IABAR0. 2647144411Sscottl** ----------------------------------------------------------------- 2648144411Sscottl** Bit Default Description 2649165155Sscottl** 31:12 00000H Translation Base Address 0 - These bits define the actual location 2650165155Sscottl** the translation function is to respond to when addressed from the PCI bus. 2651144411Sscottl** 11:04 00H Reserved. 2652144411Sscottl** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2653144411Sscottl** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window: 2654165155Sscottl** 00 - Memory Window is locatable anywhere in 32 bit address space 2655165155Sscottl** 10 - Memory Window is locatable anywhere in 64 bit address space 2656144411Sscottl** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2657144411Sscottl** The ATU does not occupy I/O space, 2658144411Sscottl** thus this bit must be zero. 2659144411Sscottl*********************************************************************************** 2660144411Sscottl*/ 2661144411Sscottl#define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/ 2662144411Sscottl#define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 2663144411Sscottl#define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 2664144411Sscottl/* 2665144411Sscottl*********************************************************************************** 2666144411Sscottl** Inbound ATU Upper Base Address Register 0 - IAUBAR0 2667144411Sscottl** 2668144411Sscottl** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2669144411Sscottl** Together with the Translation Base Address this register defines the actual location the translation 2670144411Sscottl** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2671144411Sscottl** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2672144411Sscottl** Note: 2673144411Sscottl** When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 2674144411Sscottl** the IAUBAR0 register attributes are read-only. 2675144411Sscottl** ----------------------------------------------------------------- 2676144411Sscottl** Bit Default Description 2677144411Sscottl** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the 2678165155Sscottl** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2679144411Sscottl*********************************************************************************** 2680144411Sscottl*/ 2681144411Sscottl#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/ 2682144411Sscottl/* 2683144411Sscottl*********************************************************************************** 2684144411Sscottl** Inbound ATU Base Address Register 1 - IABAR1 2685144411Sscottl** 2686165155Sscottl** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) 2687165155Sscottl** defines the block of memory addresses where the inbound translation window 1 begins. 2688144411Sscottl** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2689144411Sscottl** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2690144411Sscottl** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 2691165155Sscottl** Warning: 2692144411Sscottl** When a non-zero value is not written to IALR1 prior to host configuration, 2693144411Sscottl** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 2694144411Sscottl** This is the default for IABAR1. 2695144411Sscottl** Assuming a non-zero value is written to IALR1, 2696144411Sscottl** the user may set the Prefetchable Indicator 2697144411Sscottl** or the Type Indicator: 2698144411Sscottl** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address 2699144411Sscottl** boundary, when the Prefetchable Indicator is not set prior to host configuration, 2700144411Sscottl** the user should also leave the Type Indicator set for 32 bit addressability. 2701144411Sscottl** This is the default for IABAR1. 2702144411Sscottl** b. when the Prefetchable Indicator is set prior to host configuration, 2703144411Sscottl** the user should also set the Type Indicator for 64 bit addressability. 2704144411Sscottl** ----------------------------------------------------------------- 2705144411Sscottl** Bit Default Description 2706144411Sscottl** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus. 2707144411Sscottl** 11:04 00H Reserved. 2708144411Sscottl** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2709144411Sscottl** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2710165155Sscottl** 00 - Memory Window is locatable anywhere in 32 bit address space 2711165155Sscottl** 10 - Memory Window is locatable anywhere in 64 bit address space 2712144411Sscottl** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2713144411Sscottl** The ATU does not occupy I/O space, 2714144411Sscottl** thus this bit must be zero. 2715144411Sscottl*********************************************************************************** 2716144411Sscottl*/ 2717144411Sscottl#define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 2718144411Sscottl/* 2719144411Sscottl*********************************************************************************** 2720144411Sscottl** Inbound ATU Upper Base Address Register 1 - IAUBAR1 2721144411Sscottl** 2722144411Sscottl** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 2723144411Sscottl** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 2724144411Sscottl** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2725144411Sscottl** The programmed value within the base address register must comply with the PCI programming 2726144411Sscottl** requirements for address alignment. 2727144411Sscottl** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written 2728144411Sscottl** from the PCI bus. 2729144411Sscottl** Note: 2730144411Sscottl** When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 2731144411Sscottl** the IAUBAR1 register attributes are read-only. 2732144411Sscottl** This is the default for IABAR1. 2733144411Sscottl** ----------------------------------------------------------------- 2734144411Sscottl** Bit Default Description 2735165155Sscottl** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1 2736165155Sscottl** these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes. 2737144411Sscottl*********************************************************************************** 2738144411Sscottl*/ 2739144411Sscottl#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 2740144411Sscottl/* 2741144411Sscottl*********************************************************************************** 2742144411Sscottl** Inbound ATU Base Address Register 2 - IABAR2 2743144411Sscottl** 2744165155Sscottl** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) 2745165155Sscottl** defines the block of memory addresses where the inbound translation window 2 begins. 2746144411Sscottl** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2747144411Sscottl** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size 2748144411Sscottl** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2. 2749144411Sscottl** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2750144411Sscottl** Warning: 2751144411Sscottl** When a non-zero value is not written to IALR2 prior to host configuration, 2752144411Sscottl** the user should not set either the Prefetchable Indicator 2753144411Sscottl** or the Type Indicator for 64 bit addressability. 2754144411Sscottl** This is the default for IABAR2. 2755144411Sscottl** Assuming a non-zero value is written to IALR2, 2756144411Sscottl** the user may set the Prefetchable Indicator 2757144411Sscottl** or the Type Indicator: 2758144411Sscottl** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2759144411Sscottl** when the Prefetchable Indicator is not set prior to host configuration, 2760144411Sscottl** the user should also leave the Type Indicator set for 32 bit addressability. 2761144411Sscottl** This is the default for IABAR2. 2762144411Sscottl** b. when the Prefetchable Indicator is set prior to host configuration, 2763144411Sscottl** the user should also set the Type Indicator for 64 bit addressability. 2764144411Sscottl** ----------------------------------------------------------------- 2765144411Sscottl** Bit Default Description 2766165155Sscottl** 31:12 00000H Translation Base Address 2 - These bits define the actual location 2767165155Sscottl** the translation function is to respond to when addressed from the PCI bus. 2768144411Sscottl** 11:04 00H Reserved. 2769144411Sscottl** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2770144411Sscottl** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2771165155Sscottl** 00 - Memory Window is locatable anywhere in 32 bit address space 2772165155Sscottl** 10 - Memory Window is locatable anywhere in 64 bit address space 2773144411Sscottl** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2774144411Sscottl** The ATU does not occupy I/O space, 2775144411Sscottl** thus this bit must be zero. 2776144411Sscottl*********************************************************************************** 2777144411Sscottl*/ 2778144411Sscottl#define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 2779144411Sscottl/* 2780144411Sscottl*********************************************************************************** 2781144411Sscottl** Inbound ATU Upper Base Address Register 2 - IAUBAR2 2782165155Sscottl** 2783144411Sscottl** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2784165155Sscottl** Together with the Translation Base Address this register defines the actual location 2785165155Sscottl** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2786144411Sscottl** The programmed value within the base address register must comply with the PCI programming 2787144411Sscottl** requirements for address alignment. 2788144411Sscottl** Note: 2789144411Sscottl** When the Type indicator of IABAR2 is set to indicate 32 bit addressability, 2790144411Sscottl** the IAUBAR2 register attributes are read-only. 2791144411Sscottl** This is the default for IABAR2. 2792144411Sscottl** ----------------------------------------------------------------- 2793144411Sscottl** Bit Default Description 2794165155Sscottl** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2 2795165155Sscottl** these bits define the actual location the translation function is to respond to 2796165155Sscottl** when addressed from the PCI bus for addresses > 4GBytes. 2797144411Sscottl*********************************************************************************** 2798144411Sscottl*/ 2799144411Sscottl#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 2800144411Sscottl/* 2801144411Sscottl*********************************************************************************** 2802144411Sscottl** ATU Subsystem Vendor ID Register - ASVIR 2803144411Sscottl** ----------------------------------------------------------------- 2804144411Sscottl** Bit Default Description 2805144411Sscottl** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor. 2806144411Sscottl*********************************************************************************** 2807144411Sscottl*/ 2808144411Sscottl#define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/ 2809144411Sscottl/* 2810144411Sscottl*********************************************************************************** 2811144411Sscottl** ATU Subsystem ID Register - ASIR 2812144411Sscottl** ----------------------------------------------------------------- 2813144411Sscottl** Bit Default Description 2814144411Sscottl** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem. 2815144411Sscottl*********************************************************************************** 2816144411Sscottl*/ 2817144411Sscottl#define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/ 2818144411Sscottl/* 2819144411Sscottl*********************************************************************************** 2820144411Sscottl** Expansion ROM Base Address Register -ERBAR 2821144411Sscottl** ----------------------------------------------------------------- 2822144411Sscottl** Bit Default Description 2823165155Sscottl** 31:12 00000H Expansion ROM Base Address - These bits define the actual location 2824165155Sscottl** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary. 2825144411Sscottl** 11:01 000H Reserved 2826165155Sscottl** 00 0 2 Address Decode Enable - This bit field shows the ROM address 2827165155Sscottl** decoder is enabled or disabled. When cleared, indicates the address decoder is disabled. 2828144411Sscottl*********************************************************************************** 2829144411Sscottl*/ 2830144411Sscottl#define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/ 2831144411Sscottl#define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 2832144411Sscottl/* 2833144411Sscottl*********************************************************************************** 2834144411Sscottl** ATU Capabilities Pointer Register - ATU_CAP_PTR 2835144411Sscottl** ----------------------------------------------------------------- 2836144411Sscottl** Bit Default Description 2837165155Sscottl** 07:00 C0H Capability List Pointer - This provides an offset in this function��s configuration space 2838165155Sscottl** that points to the 80331 PCl Bus Power Management extended capability. 2839144411Sscottl*********************************************************************************** 2840144411Sscottl*/ 2841144411Sscottl#define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/ 2842144411Sscottl/* 2843144411Sscottl*********************************************************************************** 2844144411Sscottl** Determining Block Sizes for Base Address Registers 2845144411Sscottl** The required address size and type can be determined by writing ones to a base address register and 2846144411Sscottl** reading from the registers. By scanning the returned value from the least-significant bit of the base 2847144411Sscottl** address registers upwards, the programmer can determine the required address space size. The 2848144411Sscottl** binary-weighted value of the first non-zero bit found indicates the required amount of space. 2849144411Sscottl** Table 105 describes the relationship between the values read back and the byte sizes the base 2850144411Sscottl** address register requires. 2851144411Sscottl** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0 2852144411Sscottl** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires 2853144411Sscottl** memory address space. Bit three is one, so the memory does supports prefetching. Scanning 2854144411Sscottl** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this 2855144411Sscottl** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space. 2856144411Sscottl** The ATU Base Address Registers and the Expansion ROM Base Address Register use their 2857144411Sscottl** associated limit registers to enable which bits within the base address register are read/write and 2858144411Sscottl** which bits are read only (0). This allows the programming of these registers in a manner similar to 2859144411Sscottl** other PCI devices even though the limit is variable. 2860144411Sscottl** Table 105. Memory Block Size Read Response 2861144411Sscottl** Response After Writing all 1s 2862144411Sscottl** to the Base Address Register 2863144411Sscottl** Size 2864144411Sscottl** (Bytes) 2865144411Sscottl** Response After Writing all 1s 2866144411Sscottl** to the Base Address Register 2867144411Sscottl** Size 2868144411Sscottl** (Bytes) 2869144411Sscottl** FFFFFFF0H 16 FFF00000H 1 M 2870144411Sscottl** FFFFFFE0H 32 FFE00000H 2 M 2871144411Sscottl** FFFFFFC0H 64 FFC00000H 4 M 2872144411Sscottl** FFFFFF80H 128 FF800000H 8 M 2873144411Sscottl** FFFFFF00H 256 FF000000H 16 M 2874144411Sscottl** FFFFFE00H 512 FE000000H 32 M 2875144411Sscottl** FFFFFC00H 1K FC000000H 64 M 2876144411Sscottl** FFFFF800H 2K F8000000H 128 M 2877144411Sscottl** FFFFF000H 4K F0000000H 256 M 2878144411Sscottl** FFFFE000H 8K E0000000H 512 M 2879144411Sscottl** FFFFC000H 16K C0000000H 1 G 2880144411Sscottl** FFFF8000H 32K 80000000H 2 G 2881144411Sscottl** FFFF0000H 64K 2882144411Sscottl** 00000000H 2883144411Sscottl** Register not 2884144411Sscottl** imple-mented, 2885144411Sscottl** no 2886144411Sscottl** address 2887144411Sscottl** space 2888144411Sscottl** required. 2889144411Sscottl** FFFE0000H 128K 2890144411Sscottl** FFFC0000H 256K 2891144411Sscottl** FFF80000H 512K 2892165155Sscottl** 2893144411Sscottl*************************************************************************************** 2894144411Sscottl*/ 2895144411Sscottl 2896144411Sscottl 2897144411Sscottl 2898144411Sscottl/* 2899144411Sscottl*********************************************************************************** 2900144411Sscottl** ATU Interrupt Line Register - ATUILR 2901144411Sscottl** ----------------------------------------------------------------- 2902144411Sscottl** Bit Default Description 2903144411Sscottl** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller��s interrupt 2904165155Sscottl** request line connects to the device's PCI interrupt request lines 2905165155Sscottl** (as specified in the interrupt pin register). 2906144411Sscottl** A value of FFH signifies ��no connection�� or ��unknown��. 2907144411Sscottl*********************************************************************************** 2908144411Sscottl*/ 2909144411Sscottl#define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/ 2910144411Sscottl/* 2911144411Sscottl*********************************************************************************** 2912144411Sscottl** ATU Interrupt Pin Register - ATUIPR 2913144411Sscottl** ----------------------------------------------------------------- 2914144411Sscottl** Bit Default Description 2915144411Sscottl** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin. 2916144411Sscottl*********************************************************************************** 2917144411Sscottl*/ 2918144411Sscottl#define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/ 2919144411Sscottl/* 2920144411Sscottl*********************************************************************************** 2921144411Sscottl** ATU Minimum Grant Register - ATUMGNT 2922144411Sscottl** ----------------------------------------------------------------- 2923144411Sscottl** Bit Default Description 2924144411Sscottl** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks. 2925144411Sscottl*********************************************************************************** 2926144411Sscottl*/ 2927144411Sscottl#define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/ 2928144411Sscottl/* 2929144411Sscottl*********************************************************************************** 2930144411Sscottl** ATU Maximum Latency Register - ATUMLAT 2931144411Sscottl** ----------------------------------------------------------------- 2932144411Sscottl** Bit Default Description 2933165155Sscottl** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus 2934165155Sscottl** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement. 2935144411Sscottl*********************************************************************************** 2936144411Sscottl*/ 2937144411Sscottl#define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/ 2938144411Sscottl/* 2939144411Sscottl*********************************************************************************** 2940144411Sscottl** Inbound Address Translation 2941144411Sscottl** 2942144411Sscottl** The ATU allows external PCI bus initiators to directly access the internal bus. 2943144411Sscottl** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 2944144411Sscottl** The process of inbound address translation involves two steps: 2945144411Sscottl** 1. Address Detection. 2946144411Sscottl** �E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is 2947144411Sscottl** within the address windows defined for the inbound ATU. 2948144411Sscottl** �E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI 2949144411Sscottl** mode and with Decode A DEVSEL# timing in the PCI-X mode. 2950144411Sscottl** 2. Address Translation. 2951144411Sscottl** �E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address. 2952144411Sscottl** The ATU uses the following registers in inbound address window 0 translation: 2953144411Sscottl** �E Inbound ATU Base Address Register 0 2954144411Sscottl** �E Inbound ATU Limit Register 0 2955144411Sscottl** �E Inbound ATU Translate Value Register 0 2956144411Sscottl** The ATU uses the following registers in inbound address window 2 translation: 2957144411Sscottl** �E Inbound ATU Base Address Register 2 2958144411Sscottl** �E Inbound ATU Limit Register 2 2959144411Sscottl** �E Inbound ATU Translate Value Register 2 2960144411Sscottl** The ATU uses the following registers in inbound address window 3 translation: 2961144411Sscottl** �E Inbound ATU Base Address Register 3 2962144411Sscottl** �E Inbound ATU Limit Register 3 2963144411Sscottl** �E Inbound ATU Translate Value Register 3 2964144411Sscottl** Note: Inbound Address window 1 is not a translate window. 2965144411Sscottl** Instead, window 1 may be used to allocate host memory for Private Devices. 2966144411Sscottl** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 2967144411Sscottl** thus the host BIOS does not configure window 3. 2968144411Sscottl** Window 3 is intended to be used as a special window into local memory for private PCI 2969144411Sscottl** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge. 2970144411Sscottl** PCI-to-PCI Bridge in 80331 or 2971144411Sscottl** Inbound address detection is determined from the 32-bit PCI address, 2972144411Sscottl** (64-bit PCI address during DACs) the base address register and the limit register. 2973144411Sscottl** In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 2974144411Sscottl** 2975144411Sscottl** The algorithm for detection is: 2976144411Sscottl** 2977144411Sscottl** Equation 1. Inbound Address Detection 2978144411Sscottl** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 2979144411Sscottl** the PCI Address is claimed by the Inbound ATU. 2980144411Sscottl** 2981144411Sscottl** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed 2982144411Sscottl** with the associated inbound limit register. 2983144411Sscottl** When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 2984144411Sscottl** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU. 2985144411Sscottl** 2986144411Sscottl** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 2987144411Sscottl** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit 2988144411Sscottl** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the 2989144411Sscottl** lower 32-bits are used during address translation. 2990144411Sscottl** The algorithm is: 2991144411Sscottl** 2992144411Sscottl** 2993144411Sscottl** Equation 2. Inbound Translation 2994144411Sscottl** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0]. 2995144411Sscottl** 2996144411Sscottl** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the 2997144411Sscottl** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and 2998144411Sscottl** the result is the internal bus address. This translation mechanism is used for all inbound memory 2999144411Sscottl** read and write commands excluding inbound configuration read and writes. 3000144411Sscottl** In the PCI mode for inbound memory transactions, the only burst order supported is Linear 3001144411Sscottl** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase. 3002144411Sscottl** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode. 3003144411Sscottl** example: 3004144411Sscottl** Register Values 3005144411Sscottl** Base_Register=3A00 0000H 3006144411Sscottl** Limit_Register=FF80 0000H (8 Mbyte limit value) 3007144411Sscottl** Value_Register=B100 0000H 3008144411Sscottl** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes) 3009144411Sscottl** 3010144411Sscottl** Address Detection (32-bit address) 3011144411Sscottl** 3012144411Sscottl** PCI_Address & Limit_Register == Base_Register 3013144411Sscottl** 3A45 012CH & FF80 0000H == 3A00 0000H 3014144411Sscottl** 3015144411Sscottl** ANS: PCI_Address is in the Inbound Translation Window 3016144411Sscottl** Address Translation (to get internal bus address) 3017144411Sscottl** 3018144411Sscottl** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg 3019144411Sscottl** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H 3020144411Sscottl** 3021144411Sscottl** ANS:IB_Address=B145 012CH 3022144411Sscottl*********************************************************************************** 3023144411Sscottl*/ 3024144411Sscottl 3025144411Sscottl 3026144411Sscottl 3027144411Sscottl/* 3028144411Sscottl*********************************************************************************** 3029144411Sscottl** Inbound ATU Limit Register 0 - IALR0 3030165155Sscottl** 3031144411Sscottl** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI 3032144411Sscottl** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3033144411Sscottl** PCI addresses to internal bus addresses. 3034144411Sscottl** The 80331 translate value register��s programmed value must be naturally aligned with the base 3035144411Sscottl** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3036144411Sscottl** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3037144411Sscottl** Specification, Revision 2.3 for additional information on programming base address registers. 3038144411Sscottl** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a 3039144411Sscottl** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit 3040144411Sscottl** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0 3041144411Sscottl** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of 3042144411Sscottl** this programming scheme is that unless a valid value exists within the IALR0, all writes to the 3043144411Sscottl** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register. 3044144411Sscottl** ----------------------------------------------------------------- 3045144411Sscottl** Bit Default Description 3046144411Sscottl** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for 3047165155Sscottl** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB. 3048144411Sscottl** 11:00 000H Reserved 3049144411Sscottl*********************************************************************************** 3050144411Sscottl*/ 3051144411Sscottl#define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 3052144411Sscottl/* 3053144411Sscottl*********************************************************************************** 3054144411Sscottl** Inbound ATU Translate Value Register 0 - IATVR0 3055165155Sscottl** 3056144411Sscottl** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to 3057144411Sscottl** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3058144411Sscottl** inbound ATU address translation. 3059144411Sscottl** ----------------------------------------------------------------- 3060144411Sscottl** Bit Default Description 3061144411Sscottl** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 3062165155Sscottl** This value must be 64-bit aligned on the internal bus. 3063165155Sscottl** The default address allows the ATU to access the internal 80331 memory-mapped registers. 3064144411Sscottl** 11:00 000H Reserved 3065144411Sscottl*********************************************************************************** 3066144411Sscottl*/ 3067144411Sscottl#define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 3068144411Sscottl/* 3069144411Sscottl*********************************************************************************** 3070144411Sscottl** Expansion ROM Limit Register - ERLR 3071165155Sscottl** 3072144411Sscottl** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines 3073144411Sscottl** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR. 3074144411Sscottl** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one 3075144411Sscottl** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within 3076144411Sscottl** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes 3077144411Sscottl** the corresponding bit within the ERBAR read/write from PCI. 3078144411Sscottl** ----------------------------------------------------------------- 3079144411Sscottl** Bit Default Description 3080144411Sscottl** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default 3081165155Sscottl** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0. 3082144411Sscottl** 11:00 000H Reserved. 3083144411Sscottl*********************************************************************************** 3084144411Sscottl*/ 3085144411Sscottl#define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/ 3086144411Sscottl/* 3087144411Sscottl*********************************************************************************** 3088144411Sscottl** Expansion ROM Translate Value Register - ERTVR 3089165155Sscottl** 3090144411Sscottl** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the 3091144411Sscottl** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the 3092144411Sscottl** Expansion ROM address translation. 3093144411Sscottl** ----------------------------------------------------------------- 3094144411Sscottl** Bit Default Description 3095144411Sscottl** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses 3096165155Sscottl** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus. 3097144411Sscottl** 11:00 000H Reserved 3098144411Sscottl*********************************************************************************** 3099144411Sscottl*/ 3100144411Sscottl#define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/ 3101144411Sscottl/* 3102144411Sscottl*********************************************************************************** 3103144411Sscottl** Inbound ATU Limit Register 1 - IALR1 3104165155Sscottl** 3105144411Sscottl** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a 3106144411Sscottl** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit 3107144411Sscottl** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1 3108144411Sscottl** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of 3109144411Sscottl** this programming scheme is that unless a valid value exists within the IALR1, all writes to the 3110144411Sscottl** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only 3111144411Sscottl** register. 3112144411Sscottl** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does 3113144411Sscottl** not process any PCI bus transactions to this memory range. 3114144411Sscottl** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1, 3115144411Sscottl** IAUBAR1, and IALR1. 3116144411Sscottl** ----------------------------------------------------------------- 3117144411Sscottl** Bit Default Description 3118165155Sscottl** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size 3119165155Sscottl** required for the ATUs memory window 1. 3120144411Sscottl** 11:00 000H Reserved 3121144411Sscottl*********************************************************************************** 3122144411Sscottl*/ 3123144411Sscottl#define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/ 3124144411Sscottl/* 3125144411Sscottl*********************************************************************************** 3126144411Sscottl** Inbound ATU Limit Register 2 - IALR2 3127144411Sscottl** 3128144411Sscottl** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI 3129144411Sscottl** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3130144411Sscottl** PCI addresses to internal bus addresses. 3131144411Sscottl** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When 3132144411Sscottl** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3133144411Sscottl** register provides the block size requirements for the base address register. The remaining registers 3134144411Sscottl** used for performing address translation are discussed in Section 3.2.1.1. 3135144411Sscottl** The 80331 translate value register��s programmed value must be naturally aligned with the base 3136144411Sscottl** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3137144411Sscottl** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3138144411Sscottl** Specification, Revision 2.3 for additional information on programming base address registers. 3139144411Sscottl** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a 3140144411Sscottl** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit 3141144411Sscottl** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2 3142144411Sscottl** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of 3143144411Sscottl** this programming scheme is that unless a valid value exists within the IALR2, all writes to the 3144144411Sscottl** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only 3145144411Sscottl** register. 3146144411Sscottl** ----------------------------------------------------------------- 3147144411Sscottl** Bit Default Description 3148165155Sscottl** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size 3149165155Sscottl** required for the ATUs memory window 2. 3150144411Sscottl** 11:00 000H Reserved 3151144411Sscottl*********************************************************************************** 3152144411Sscottl*/ 3153144411Sscottl#define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/ 3154144411Sscottl/* 3155144411Sscottl*********************************************************************************** 3156144411Sscottl** Inbound ATU Translate Value Register 2 - IATVR2 3157165155Sscottl** 3158144411Sscottl** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to 3159144411Sscottl** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3160144411Sscottl** inbound ATU address translation. 3161144411Sscottl** ----------------------------------------------------------------- 3162144411Sscottl** Bit Default Description 3163144411Sscottl** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 3164165155Sscottl** This value must be 64-bit aligned on the internal bus. 3165165155Sscottl** The default address allows the ATU to access the internal 80331 ** ** memory-mapped registers. 3166144411Sscottl** 11:00 000H Reserved 3167144411Sscottl*********************************************************************************** 3168144411Sscottl*/ 3169144411Sscottl#define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/ 3170144411Sscottl/* 3171144411Sscottl*********************************************************************************** 3172144411Sscottl** Outbound I/O Window Translate Value Register - OIOWTVR 3173165155Sscottl** 3174144411Sscottl** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address 3175144411Sscottl** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a 3176144411Sscottl** result of the outbound ATU address translation. 3177144411Sscottl** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed 3178144411Sscottl** length of 64 Kbytes. 3179144411Sscottl** ----------------------------------------------------------------- 3180144411Sscottl** Bit Default Description 3181144411Sscottl** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses. 3182144411Sscottl** 15:00 0000H Reserved 3183144411Sscottl*********************************************************************************** 3184144411Sscottl*/ 3185144411Sscottl#define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/ 3186144411Sscottl/* 3187144411Sscottl*********************************************************************************** 3188144411Sscottl** Outbound Memory Window Translate Value Register 0 -OMWTVR0 3189165155Sscottl** 3190144411Sscottl** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI 3191144411Sscottl** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3192144411Sscottl** driven on the PCI bus as a result of the outbound ATU address translation. 3193144411Sscottl** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length 3194144411Sscottl** of 64 Mbytes. 3195144411Sscottl** ----------------------------------------------------------------- 3196144411Sscottl** Bit Default Description 3197144411Sscottl** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3198144411Sscottl** 25:02 00 0000H Reserved 3199165155Sscottl** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3200165155Sscottl** Only linear incrementing mode is supported. 3201144411Sscottl*********************************************************************************** 3202144411Sscottl*/ 3203144411Sscottl#define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/ 3204144411Sscottl/* 3205144411Sscottl*********************************************************************************** 3206144411Sscottl** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 3207165155Sscottl** 3208144411Sscottl** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines 3209144411Sscottl** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3210144411Sscottl** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3211144411Sscottl** a SAC is generated on the PCI bus. 3212144411Sscottl** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed 3213144411Sscottl** length of 64 Mbytes. 3214144411Sscottl** ----------------------------------------------------------------- 3215144411Sscottl** Bit Default Description 3216144411Sscottl** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3217144411Sscottl*********************************************************************************** 3218144411Sscottl*/ 3219144411Sscottl#define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/ 3220144411Sscottl/* 3221144411Sscottl*********************************************************************************** 3222144411Sscottl** Outbound Memory Window Translate Value Register 1 -OMWTVR1 3223165155Sscottl** 3224144411Sscottl** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI 3225144411Sscottl** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3226144411Sscottl** driven on the PCI bus as a result of the outbound ATU address translation. 3227144411Sscottl** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3228144411Sscottl** of 64 Mbytes. 3229144411Sscottl** ----------------------------------------------------------------- 3230144411Sscottl** Bit Default Description 3231144411Sscottl** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3232144411Sscottl** 25:02 00 0000H Reserved 3233165155Sscottl** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3234165155Sscottl** Only linear incrementing mode is supported. 3235144411Sscottl*********************************************************************************** 3236144411Sscottl*/ 3237144411Sscottl#define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/ 3238144411Sscottl/* 3239144411Sscottl*********************************************************************************** 3240144411Sscottl** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 3241165155Sscottl** 3242144411Sscottl** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines 3243144411Sscottl** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3244144411Sscottl** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3245144411Sscottl** a SAC is generated on the PCI bus. 3246144411Sscottl** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3247144411Sscottl** of 64 Mbytes. 3248144411Sscottl** ----------------------------------------------------------------- 3249144411Sscottl** Bit Default Description 3250144411Sscottl** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3251144411Sscottl*********************************************************************************** 3252144411Sscottl*/ 3253144411Sscottl#define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/ 3254144411Sscottl/* 3255144411Sscottl*********************************************************************************** 3256144411Sscottl** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR 3257165155Sscottl** 3258144411Sscottl** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the 3259144411Sscottl** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing 3260144411Sscottl** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host 3261144411Sscottl** address space. When this register is all-zero, then a SAC is generated on the PCI bus. 3262144411Sscottl** ----------------------------------------------------------------- 3263144411Sscottl** Bit Default Description 3264144411Sscottl** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3265144411Sscottl*********************************************************************************** 3266144411Sscottl*/ 3267144411Sscottl#define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/ 3268144411Sscottl/* 3269144411Sscottl*********************************************************************************** 3270144411Sscottl** ATU Configuration Register - ATUCR 3271165155Sscottl** 3272144411Sscottl** The ATU Configuration Register controls the outbound address translation for address translation 3273144411Sscottl** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard 3274144411Sscottl** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST 3275144411Sscottl** interrupt enabling. 3276144411Sscottl** ----------------------------------------------------------------- 3277144411Sscottl** Bit Default Description 3278144411Sscottl** 31:20 00H Reserved 3279144411Sscottl** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a 3280165155Sscottl** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read 3281165155Sscottl** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not 3282165155Sscottl** applicable in the PCI-X mode. 3283165155Sscottl** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set, 3284165155Sscottl** with Direct Addressing enabled (bit 7 of the ATUCR set), 3285165155Sscottl** the ATU forwards internal bus cycles with an address between 0000.0040H and 3286165155Sscottl** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH). 3287165155Sscottl** When clear, no translation occurs. 3288144411Sscottl** 17 0 2 Reserved 3289144411Sscottl** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until 3290165155Sscottl** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified. 3291144411Sscottl** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and 3292165155Sscottl** discarded the delayed completion transaction within the queue. When clear, no timer has expired. 3293144411Sscottl** 14:10 00000 2 Reserved 3294144411Sscottl** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt 3295165155Sscottl** when the ATU detects that SERR# was asserted. When clear, 3296165155Sscottl** the Intel XScale core is not interrupted when SERR# is detected. 3297144411Sscottl** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU. 3298165155Sscottl** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to 3299165155Sscottl** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of 3300165155Sscottl** the ATUCR. 3301144411Sscottl** 07:04 0000 2 Reserved 3302144411Sscottl** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start 3303165155Sscottl** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 3304165155Sscottl** in the ATUBISTR register. 3305144411Sscottl** 02 0 2 Reserved 3306165155Sscottl** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit. 3307165155Sscottl** When cleared, disables the outbound ATU. 3308144411Sscottl** 00 0 2 Reserved 3309144411Sscottl*********************************************************************************** 3310144411Sscottl*/ 3311144411Sscottl#define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/ 3312144411Sscottl/* 3313144411Sscottl*********************************************************************************** 3314144411Sscottl** PCI Configuration and Status Register - PCSR 3315144411Sscottl** 3316144411Sscottl** The PCI Configuration and Status Register has additional bits for controlling and monitoring 3317144411Sscottl** various features of the PCI bus interface. 3318144411Sscottl** ----------------------------------------------------------------- 3319144411Sscottl** Bit Default Description 3320144411Sscottl** 31:19 0000H Reserved 3321144411Sscottl** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address 3322165155Sscottl** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error 3323165155Sscottl** Response bit is cleared. Set under the following conditions: 3324165155Sscottl** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU). 3325144411Sscottl** 17:16 Varies with 3326144411Sscottl** external state 3327144411Sscottl** of DEVSEL#, 3328144411Sscottl** STOP#, and 3329144411Sscottl** TRDY#, 3330144411Sscottl** during 3331144411Sscottl** P_RST# 3332165155Sscottl** PCI-X capability - These two bits define the mode of 3333165155Sscottl** the PCI bus (conventional or PCI-X) as well as the 3334144411Sscottl** operating frequency in the case of PCI-X mode. 3335144411Sscottl** 00 - Conventional PCI mode 3336144411Sscottl** 01 - PCI-X 66 3337144411Sscottl** 10 - PCI-X 100 3338144411Sscottl** 11 - PCI-X 133 3339165155Sscottl** As defined by the PCI-X Addendum to the PCI Local Bus Specification, 3340165155Sscottl** Revision 1.0a, the operating 3341165155Sscottl** mode is determined by an initialization pattern on the PCI bus during 3342165155Sscottl** P_RST# assertion: 3343144411Sscottl** DEVSEL# STOP# TRDY# Mode 3344144411Sscottl** Deasserted Deasserted Deasserted Conventional 3345144411Sscottl** Deasserted Deasserted Asserted PCI-X 66 3346144411Sscottl** Deasserted Asserted Deasserted PCI-X 100 3347144411Sscottl** Deasserted Asserted Asserted PCI-X 133 3348144411Sscottl** All other patterns are reserved. 3349144411Sscottl** 15 0 2 3350144411Sscottl** Outbound Transaction Queue Busy: 3351144411Sscottl** 0=Outbound Transaction Queue Empty 3352144411Sscottl** 1=Outbound Transaction Queue Busy 3353144411Sscottl** 14 0 2 3354144411Sscottl** Inbound Transaction Queue Busy: 3355144411Sscottl** 0=Inbound Transaction Queue Empty 3356144411Sscottl** 1=Inbound Transaction Queue Busy 3357144411Sscottl** 13 0 2 Reserved. 3358165155Sscottl** 12 0 2 Discard Timer Value - This bit controls the time-out value 3359165155Sscottl** for the four discard timers attached to the queues holding read data. 3360144411Sscottl** A value of 0 indicates the time-out value is 2 15 clocks. 3361144411Sscottl** A value of 1 indicates the time-out value is 2 10 clocks. 3362144411Sscottl** 11 0 2 Reserved. 3363144411Sscottl** 10 Varies with 3364144411Sscottl** external state 3365144411Sscottl** of M66EN 3366144411Sscottl** during 3367144411Sscottl** P_RST# 3368165155Sscottl** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in 3369165155Sscottl** Conventional PCI mode by the assertion of M66EN during bus initialization. 3370165155Sscottl** When clear, the interface 3371144411Sscottl** has been initialized as a 33 MHz bus. 3372165155Sscottl** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode. 3373144411Sscottl** 09 0 2 Reserved 3374144411Sscottl** 08 Varies with 3375144411Sscottl** external state 3376144411Sscottl** of REQ64# 3377144411Sscottl** during 3378144411Sscottl** P_RST# 3379165155Sscottl** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been 3380165155Sscottl** configured as 64-bit capable by 3381165155Sscottl** the assertion of REQ64# on the rising edge of P_RST#. When set, 3382165155Sscottl** the PCI interface is configured as 3383144411Sscottl** 32-bit only. 3384144411Sscottl** 07:06 00 2 Reserved. 3385165155Sscottl** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core 3386165155Sscottl** and all units on the internal 3387165155Sscottl** bus. In addition to the internal bus initialization, 3388165155Sscottl** this bit triggers the assertion of the M_RST# pin for 3389165155Sscottl** initialization of registered DIMMs. When set: 3390165155Sscottl** When operating in the conventional PCI mode: 3391165155Sscottl** �E All current PCI transactions being mastered by the ATU completes, 3392165155Sscottl** and the ATU master interfaces 3393165155Sscottl** proceeds to an idle state. No additional transactions is mastered by these units 3394165155Sscottl** until the internal bus reset is complete. 3395165155Sscottl** �E All current transactions being slaved by the ATU on either the PCI bus 3396165155Sscottl** or the internal bus 3397165155Sscottl** completes, and the ATU target interfaces proceeds to an idle state. 3398165155Sscottl** All future slave transactions master aborts, 3399165155Sscottl** with the exception of the completion cycle for the transaction that set the Reset 3400165155Sscottl** Internal Bus bit in the PCSR. 3401165155Sscottl** �E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) 3402165155Sscottl** is set, the Intel XScale core is held in reset when the internal bus reset is complete. 3403165155Sscottl** �E The ATU ignores configuration cycles, and they appears as master aborts for: 32 3404165155Sscottl** Internal Bus clocks. 3405165155Sscottl** �E The 80331 hardware clears this bit after the reset operation completes. 3406165155Sscottl** When operating in the PCI-X mode: 3407165155Sscottl** The ATU hardware responds the same as in Conventional PCI-X mode. 3408165155Sscottl** However, this may create a problem in PCI-X mode for split requests in 3409165155Sscottl** that there may still be an outstanding split completion that the 3410165155Sscottl** ATU is either waiting to receive (Outbound Request) or initiate 3411165155Sscottl** (Inbound Read Request). For a cleaner 3412165155Sscottl** internal bus reset, host software can take the following steps prior 3413165155Sscottl** to asserting Reset Internal bus: 3414165155Sscottl** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in 3415165155Sscottl** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued. 3416165155Sscottl** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction 3417165155Sscottl** queue busy bits to be clear. 3418165155Sscottl** 3. Set the Reset Internal Bus bit 3419165155Sscottl** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode, 3420165155Sscottl** however the user is now assured that the ATU no longer has any pending inbound or outbound split 3421165155Sscottl** completion transactions. 3422165155Sscottl** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is 3423165155Sscottl** guaranteed that any prior configuration cycles have properly completed since there is only a one 3424165155Sscottl** deep transaction queue for configuration transaction requests. The ATU sends the appropriate 3425165155Sscottl** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset. 3426165155Sscottl** 04 0 2 Bus Master Indicator Enable: Provides software control for the 3427165155Sscottl** Bus Master Indicator signal P_BMI used 3428165155Sscottl** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and 3429165155Sscottl** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low). 3430165155Sscottl** 03 Varies with external state of PRIVDEV during 3431165155Sscottl** P_RST# 3432165155Sscottl** Private Device Enable - This bit indicates the state of the reset strap which enables the private device 3433165155Sscottl** control mechanism within the PCI-to-PCI Bridge SISR configuration register. 3434165155Sscottl** 0=Private Device control Disabled - SISR register bits default to zero 3435165155Sscottl** 1=Private Device control Enabled - SISR register bits default to one 3436165155Sscottl** 02 Varies with external state of RETRY during P_RST# 3437165155Sscottl** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all 3438165155Sscottl** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate 3439165155Sscottl** configuration cycles. 3440165155Sscottl** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of 3441165155Sscottl** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is 3442165155Sscottl** low, the bit is cleared. 3443165155Sscottl** 01 Varies with external state of CORE_RST# during P_RST# 3444165155Sscottl** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is 3445165155Sscottl** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is 3446165155Sscottl** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 3447165155Sscottl** XScale core reset. 3448165155Sscottl** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge 3449165155Sscottl** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is 3450165155Sscottl** high, the bit is clear. 3451165155Sscottl** 00 Varies with external state of PRIVMEM during P_RST# 3452165155Sscottl** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device 3453165155Sscottl** control mechanism within the PCI-to-PCI Bridge SDER configuration register. 3454165155Sscottl** 0=Private Memory control Disabled - SDER register bit 2 default to zero 3455165155Sscottl** 1=Private Memory control Enabled - SDER register bits 2 default to one 3456144411Sscottl*********************************************************************************** 3457144411Sscottl*/ 3458144411Sscottl#define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/ 3459144411Sscottl/* 3460144411Sscottl*********************************************************************************** 3461144411Sscottl** ATU Interrupt Status Register - ATUISR 3462144411Sscottl** 3463144411Sscottl** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU 3464144411Sscottl** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit 3465144411Sscottl** of the 80331. All bits in this register are Read/Clear. 3466144411Sscottl** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register 3467144411Sscottl** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set 3468144411Sscottl** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The 3469144411Sscottl** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this 3470144411Sscottl** register. 3471144411Sscottl** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core. 3472144411Sscottl** ----------------------------------------------------------------- 3473144411Sscottl** Bit Default Description 3474144411Sscottl** 31:18 0000H Reserved 3475144411Sscottl** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR 3476144411Sscottl** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set, 3477144411Sscottl** this bit results in the assertion of the ATU Configure Register Write Interrupt. 3478144411Sscottl** 16 0 2 Reserved 3479144411Sscottl** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register. 3480144411Sscottl** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt. 3481144411Sscottl** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write 3482144411Sscottl** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these 3483144411Sscottl** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU 3484144411Sscottl** Configure Register Write Interrupt. 3485144411Sscottl** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion 3486144411Sscottl** Message on the PCI Bus with the Split Completion Error attribute bit set. 3487144411Sscottl** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3488144411Sscottl** Message from the PCI Bus with the Split Completion Error attribute bit set. 3489144411Sscottl** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status 3490144411Sscottl** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and 3491144411Sscottl** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set. 3492144411Sscottl** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU. 3493144411Sscottl** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD 3494144411Sscottl** register��s Parity Error Response bit is cleared. Set under the following conditions: 3495144411Sscottl** �E Write Data Parity Error when the ATU is a target (inbound write). 3496144411Sscottl** �E Read Data Parity Error when the ATU is an initiator (outbound read). 3497144411Sscottl** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus. 3498144411Sscottl** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor 3499144411Sscottl** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR 3500144411Sscottl** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR 3501144411Sscottl** register bits 3:0. 3502144411Sscottl** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion 3503144411Sscottl** of the ATU Configure Register Write Interrupt. 3504144411Sscottl** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort. 3505144411Sscottl** 06:05 00 2 Reserved. 3506144411Sscottl** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU. 3507144411Sscottl** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort. 3508144411Sscottl** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort. 3509144411Sscottl** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort. 3510144411Sscottl** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following 3511144411Sscottl** conditions: 3512144411Sscottl** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 3513144411Sscottl** �E And the ATU acted as the requester for the operation in which the error occurred. 3514144411Sscottl** �E And the ATUCMD register��s Parity Error Response bit is set 3515144411Sscottl** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 3516144411Sscottl** �E And the ATUCMD register��s Parity Error Response bit is set 3517144411Sscottl*********************************************************************************** 3518144411Sscottl*/ 3519144411Sscottl#define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/ 3520144411Sscottl/* 3521144411Sscottl*********************************************************************************** 3522144411Sscottl** ATU Interrupt Mask Register - ATUIMR 3523165155Sscottl** 3524144411Sscottl** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts 3525144411Sscottl** generated by the ATU. 3526144411Sscottl** ----------------------------------------------------------------- 3527144411Sscottl** Bit Default Description 3528144411Sscottl** 31:15 0 0000H Reserved 3529144411Sscottl** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the 3530165155Sscottl** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register. 3531165155Sscottl** 0=Not Masked 3532165155Sscottl** 1=Masked 3533144411Sscottl** 13 0 2 Reserved 3534144411Sscottl** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the 3535165155Sscottl** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register 3536165155Sscottl** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR. 3537144411Sscottl** 0=Not Masked 3538144411Sscottl** 1=Masked 3539144411Sscottl** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and 3540165155Sscottl** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the 3541144411Sscottl** IABAR1 register or the IAUBAR1 register. 3542144411Sscottl** 0=Not Masked 3543144411Sscottl** 1=Masked 3544144411Sscottl** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and 3545165155Sscottl** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message. 3546144411Sscottl** 0=Not Masked 3547144411Sscottl** 1=Masked 3548144411Sscottl** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR 3549165155Sscottl** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the 3550165155Sscottl** PCIXSR being set. 3551165155Sscottl** 0=Not Masked 3552165155Sscottl** 1=Masked 3553144411Sscottl** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the 3554165155Sscottl** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the 3555165155Sscottl** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0. 3556144411Sscottl** 0=Not Masked 3557144411Sscottl** 1=Masked 3558144411Sscottl** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of 3559165155Sscottl** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR. 3560144411Sscottl** 0=Not Masked 3561144411Sscottl** 1=Masked 3562144411Sscottl** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the 3563165155Sscottl** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set. 3564144411Sscottl** 0=Not Masked 3565144411Sscottl** 1=Masked 3566165155Sscottl** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master. 3567144411Sscottl** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the 3568165155Sscottl** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set. 3569144411Sscottl** 0=Not Masked 3570144411Sscottl** 1=Masked 3571144411Sscottl** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error 3572165155Sscottl** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set 3573144411Sscottl** 0=Not Masked 3574144411Sscottl** 1=Masked 3575144411Sscottl** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation 3576165155Sscottl** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set. 3577144411Sscottl** 0=Not Masked 3578144411Sscottl** 1=Masked 3579144411Sscottl** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation 3580165155Sscottl** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set. 3581144411Sscottl** 0=Not Masked 3582144411Sscottl** 1=Masked 3583144411Sscottl** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the 3584165155Sscottl** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an 3585144411Sscottl** inbound write transaction. 3586144411Sscottl** 0=SERR# Not Asserted due to error 3587144411Sscottl** 1=SERR# Asserted due to error 3588144411Sscottl** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC 3589165155Sscottl** error) from the memory controller on the internal bus. In conventional mode, this action only occurs 3590165155Sscottl** during an inbound read transaction where the data phase that was target aborted on the internal bus is 3591165155Sscottl** actually requested from the inbound read queue. 3592165155Sscottl** 0=Disconnect with data 3593165155Sscottl** (the data being up to 64 bits of 1��s) 3594144411Sscottl** 1=Target Abort 3595165155Sscottl** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h - 3596165155Sscottl** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus, 3597165155Sscottl** independent of the setting of this bit. 3598144411Sscottl*********************************************************************************** 3599144411Sscottl*/ 3600144411Sscottl#define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/ 3601144411Sscottl/* 3602144411Sscottl*********************************************************************************** 3603144411Sscottl** Inbound ATU Base Address Register 3 - IABAR3 3604165155Sscottl** 3605165155Sscottl** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block 3606165155Sscottl** of memory addresses where the inbound translation window 3 begins. 3607144411Sscottl** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 3608144411Sscottl** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size. 3609144411Sscottl** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 3610144411Sscottl** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 3611144411Sscottl** Note: 3612144411Sscottl** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 3613144411Sscottl** IABAR3 is not configured by the host during normal system initialization. 3614144411Sscottl** Warning: 3615144411Sscottl** When a non-zero value is not written to IALR3, 3616144411Sscottl** the user should not set either the Prefetchable Indicator 3617144411Sscottl** or the Type Indicator for 64 bit addressability. 3618144411Sscottl** This is the default for IABAR3. 3619144411Sscottl** Assuming a non-zero value is written to IALR3, 3620144411Sscottl** the user may set the Prefetchable Indicator 3621144411Sscottl** or the Type Indicator: 3622144411Sscottl** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 3623144411Sscottl** when the Prefetchable Indicator is not set, 3624144411Sscottl** the user should also leave the Type Indicator set for 32 bit addressability. 3625144411Sscottl** This is the default for IABAR3. 3626144411Sscottl** b. when the Prefetchable Indicator is set, 3627144411Sscottl** the user should also set the Type Indicator for 64 bit addressability. 3628144411Sscottl** ----------------------------------------------------------------- 3629144411Sscottl** Bit Default Description 3630165155Sscottl** 31:12 00000H Translation Base Address 3 - These bits define the actual location 3631165155Sscottl** the translation function is to respond to when addressed from the PCI bus. 3632144411Sscottl** 11:04 00H Reserved. 3633144411Sscottl** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 3634144411Sscottl** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 3635165155Sscottl** 00 - Memory Window is locatable anywhere in 32 bit address space 3636165155Sscottl** 10 - Memory Window is locatable anywhere in 64 bit address space 3637144411Sscottl** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 3638144411Sscottl** The ATU does not occupy I/O space, 3639144411Sscottl** thus this bit must be zero. 3640144411Sscottl*********************************************************************************** 3641144411Sscottl*/ 3642144411Sscottl#define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/ 3643144411Sscottl/* 3644144411Sscottl*********************************************************************************** 3645144411Sscottl** Inbound ATU Upper Base Address Register 3 - IAUBAR3 3646165155Sscottl** 3647144411Sscottl** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 3648165155Sscottl** Together with the Translation Base Address this register defines the actual location 3649165155Sscottl** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 3650144411Sscottl** The programmed value within the base address register must comply with the PCI programming 3651144411Sscottl** requirements for address alignment. 3652144411Sscottl** Note: 3653144411Sscottl** When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 3654144411Sscottl** the IAUBAR3 register attributes are read-only. 3655144411Sscottl** This is the default for IABAR3. 3656144411Sscottl** ----------------------------------------------------------------- 3657144411Sscottl** Bit Default Description 3658165155Sscottl** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define 3659165155Sscottl** the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 3660144411Sscottl*********************************************************************************** 3661144411Sscottl*/ 3662144411Sscottl#define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/ 3663144411Sscottl/* 3664144411Sscottl*********************************************************************************** 3665144411Sscottl** Inbound ATU Limit Register 3 - IALR3 3666165155Sscottl** 3667144411Sscottl** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI 3668144411Sscottl** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3669144411Sscottl** PCI addresses to internal bus addresses. 3670144411Sscottl** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When 3671144411Sscottl** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3672144411Sscottl** register provides the block size requirements for the base address register. The remaining registers 3673144411Sscottl** used for performing address translation are discussed in Section 3.2.1.1. 3674144411Sscottl** The 80331 translate value register��s programmed value must be naturally aligned with the base 3675144411Sscottl** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3676144411Sscottl** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3677144411Sscottl** Specification, Revision 2.3 for additional information on programming base address registers. 3678144411Sscottl** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a 3679144411Sscottl** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit 3680144411Sscottl** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3 3681144411Sscottl** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of 3682144411Sscottl** this programming scheme is that unless a valid value exists within the IALR3, all writes to the 3683144411Sscottl** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only 3684144411Sscottl** register. 3685144411Sscottl** ----------------------------------------------------------------- 3686144411Sscottl** Bit Default Description 3687165155Sscottl** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required 3688165155Sscottl** for the ATUs memory window 3. 3689144411Sscottl** 11:00 000H Reserved 3690144411Sscottl*********************************************************************************** 3691144411Sscottl*/ 3692144411Sscottl#define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/ 3693144411Sscottl/* 3694144411Sscottl*********************************************************************************** 3695144411Sscottl** Inbound ATU Translate Value Register 3 - IATVR3 3696165155Sscottl** 3697144411Sscottl** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to 3698144411Sscottl** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3699144411Sscottl** inbound ATU address translation. 3700144411Sscottl** ----------------------------------------------------------------- 3701144411Sscottl** Bit Default Description 3702144411Sscottl** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 3703144411Sscottl** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to 3704144411Sscottl** access the internal 80331 memory-mapped registers. 3705144411Sscottl** 11:00 000H Reserved 3706144411Sscottl*********************************************************************************** 3707144411Sscottl*/ 3708144411Sscottl#define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/ 3709144411Sscottl/* 3710144411Sscottl*********************************************************************************** 3711144411Sscottl** Outbound Configuration Cycle Address Register - OCCAR 3712144411Sscottl** 3713144411Sscottl** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration 3714144411Sscottl** cycle address. The Intel XScale core writes the PCI configuration cycles address which then 3715144411Sscottl** enables the outbound configuration read or write. The Intel XScale core then performs a read or 3716144411Sscottl** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the 3717144411Sscottl** PCI bus. 3718144411Sscottl** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently 3719144411Sscottl** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a 3720144411Sscottl** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for 3721144411Sscottl** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears 3722144411Sscottl** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X 3723144411Sscottl** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats. 3724144411Sscottl** ----------------------------------------------------------------- 3725144411Sscottl** Bit Default Description 3726165155Sscottl** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound 3727165155Sscottl** configuration read or write cycle. 3728144411Sscottl*********************************************************************************** 3729144411Sscottl*/ 3730144411Sscottl#define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/ 3731144411Sscottl/* 3732144411Sscottl*********************************************************************************** 3733144411Sscottl** Outbound Configuration Cycle Data Register - OCCDR 3734165155Sscottl** 3735144411Sscottl** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write 3736144411Sscottl** on the PCI bus. The register is logical rather than physical meaning that it is an address not a 3737144411Sscottl** register. The Intel XScale core reads or writes the data registers memory-mapped address to 3738144411Sscottl** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a 3739144411Sscottl** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ. 3740144411Sscottl** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never 3741144411Sscottl** actually entered into the data register (which does not physically exist). 3742144411Sscottl** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value 3743144411Sscottl** within the ATU configuration space. 3744144411Sscottl** ----------------------------------------------------------------- 3745144411Sscottl** Bit Default Description 3746165155Sscottl** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read 3747165155Sscottl** or write cycle. 3748144411Sscottl*********************************************************************************** 3749144411Sscottl*/ 3750144411Sscottl#define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/ 3751144411Sscottl/* 3752144411Sscottl*********************************************************************************** 3753144411Sscottl** VPD Capability Identifier Register - VPD_CAPID 3754144411Sscottl** 3755144411Sscottl** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3756144411Sscottl** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3757144411Sscottl** Capability contained in that header. In the case of the 80331, this is the VPD extended capability 3758144411Sscottl** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3. 3759144411Sscottl** ----------------------------------------------------------------- 3760144411Sscottl** Bit Default Description 3761165155Sscottl** 07:00 03H Cap_Id - This field with its�� 03H value identifies this item in the linked list of Extended Capability 3762165155Sscottl** Headers as being the VPD capability registers. 3763144411Sscottl*********************************************************************************** 3764144411Sscottl*/ 3765144411Sscottl#define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/ 3766144411Sscottl/* 3767144411Sscottl*********************************************************************************** 3768144411Sscottl** VPD Next Item Pointer Register - VPD_NXTP 3769144411Sscottl** 3770144411Sscottl** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3771144411Sscottl** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3772144411Sscottl** For the 80331, this the final capability list, and hence, this register is set to 00H. 3773144411Sscottl** ----------------------------------------------------------------- 3774144411Sscottl** Bit Default Description 3775165155Sscottl** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3776165155Sscottl** next item in the function��s capability list. Since the VPD capabilities are the last in the linked list of 3777165155Sscottl** extended capabilities in the 80331, the register is set to 00H. 3778144411Sscottl*********************************************************************************** 3779144411Sscottl*/ 3780144411Sscottl#define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/ 3781144411Sscottl/* 3782144411Sscottl*********************************************************************************** 3783144411Sscottl** VPD Address Register - VPD_AR 3784165155Sscottl** 3785144411Sscottl** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be 3786144411Sscottl** accessed. The register is read/write and the initial value at power-up is indeterminate. 3787144411Sscottl** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use 3788144411Sscottl** the Flag setting to determine whether the configuration write was intended to initiate a read or 3789144411Sscottl** write of the VPD through the VPD Data Register. 3790144411Sscottl** ----------------------------------------------------------------- 3791144411Sscottl** Bit Default Description 3792165155Sscottl** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage 3793165155Sscottl** component has completed. Please see Section 3.9, ��Vital Product Data�� on page 201 for more details on 3794165155Sscottl** how the 80331 handles the data transfer. 3795165155Sscottl** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write 3796165155Sscottl** Vital Product Data from the VPD storage component. 3797144411Sscottl*********************************************************************************** 3798144411Sscottl*/ 3799144411Sscottl#define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/ 3800144411Sscottl/* 3801144411Sscottl*********************************************************************************** 3802144411Sscottl** VPD Data Register - VPD_DR 3803165155Sscottl** 3804144411Sscottl** This register is used to transfer data between the 80331 and the VPD storage component. 3805144411Sscottl** ----------------------------------------------------------------- 3806144411Sscottl** Bit Default Description 3807144411Sscottl** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component. 3808144411Sscottl*********************************************************************************** 3809144411Sscottl*/ 3810144411Sscottl#define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/ 3811144411Sscottl/* 3812144411Sscottl*********************************************************************************** 3813144411Sscottl** Power Management Capability Identifier Register -PM_CAPID 3814165155Sscottl** 3815144411Sscottl** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3816144411Sscottl** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3817144411Sscottl** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power 3818144411Sscottl** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management 3819144411Sscottl** Interface Specification, Revision 1.1. 3820144411Sscottl** ----------------------------------------------------------------- 3821144411Sscottl** Bit Default Description 3822165155Sscottl** 07:00 01H Cap_Id - This field with its�� 01H value identifies this item in the linked list of Extended Capability 3823165155Sscottl** Headers as being the PCI Power Management Registers. 3824144411Sscottl*********************************************************************************** 3825144411Sscottl*/ 3826144411Sscottl#define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/ 3827144411Sscottl/* 3828144411Sscottl*********************************************************************************** 3829144411Sscottl** Power Management Next Item Pointer Register - PM_NXTP 3830165155Sscottl** 3831144411Sscottl** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3832144411Sscottl** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3833144411Sscottl** For the 80331, the next capability (MSI capability list) is located at off-set D0H. 3834144411Sscottl** ----------------------------------------------------------------- 3835144411Sscottl** Bit Default Description 3836144411Sscottl** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3837165155Sscottl** next item in the function��s capability list which in the 80331 is the MSI extended capabilities header. 3838144411Sscottl*********************************************************************************** 3839144411Sscottl*/ 3840144411Sscottl#define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/ 3841144411Sscottl/* 3842144411Sscottl*********************************************************************************** 3843144411Sscottl** Power Management Capabilities Register - PM_CAP 3844144411Sscottl** 3845144411Sscottl** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management 3846144411Sscottl** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides 3847144411Sscottl** information on the capabilities of the ATU function related to power management. 3848144411Sscottl** ----------------------------------------------------------------- 3849144411Sscottl** Bit Default Description 3850165155Sscottl** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# 3851165155Sscottl** is not supported by the 80331. 3852144411Sscottl** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State 3853144411Sscottl** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State 3854144411Sscottl** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the 3855144411Sscottl** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1 3856144411Sscottl** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence 3857144411Sscottl** following the transition to the D0 uninitialized state. 3858144411Sscottl** 4 0 2 Reserved. 3859144411Sscottl** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 . 3860165155Sscottl** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management 3861165155Sscottl** Interface Specification, Revision 1.1 3862144411Sscottl*********************************************************************************** 3863144411Sscottl*/ 3864144411Sscottl#define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/ 3865144411Sscottl/* 3866144411Sscottl*********************************************************************************** 3867144411Sscottl** Power Management Control/Status Register - PM_CSR 3868165155Sscottl** 3869144411Sscottl** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power 3870144411Sscottl** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status 3871144411Sscottl** interface for the power management extended capability. 3872144411Sscottl** ----------------------------------------------------------------- 3873144411Sscottl** Bit Default Description 3874165155Sscottl** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not 3875165155Sscottl** supported by the 80331. 3876144411Sscottl** 14:9 00H Reserved 3877165155Sscottl** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# 3878165155Sscottl** generation from any power state. 3879144411Sscottl** 7:2 000000 2 Reserved 3880165155Sscottl** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state 3881165155Sscottl** of a function and to set the function into a new power state. The definition of the values is: 3882165155Sscottl** 00 2 - D0 3883165155Sscottl** 01 2 - D1 3884165155Sscottl** 10 2 - D2 (Unsupported) 3885165155Sscottl** 11 2 - D3 hot 3886165155Sscottl** The 80331 supports only the D0 and D3 hot states. 3887165155Sscottl** 3888144411Sscottl*********************************************************************************** 3889144411Sscottl*/ 3890144411Sscottl#define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/ 3891144411Sscottl/* 3892144411Sscottl*********************************************************************************** 3893144411Sscottl** PCI-X Capability Identifier Register - PX_CAPID 3894144411Sscottl** 3895144411Sscottl** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3896144411Sscottl** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3897144411Sscottl** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with 3898144411Sscottl** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 3899144411Sscottl** ----------------------------------------------------------------- 3900144411Sscottl** Bit Default Description 3901165155Sscottl** 07:00 07H Cap_Id - This field with its�� 07H value identifies this item in the linked list of Extended Capability 3902165155Sscottl** Headers as being the PCI-X capability registers. 3903144411Sscottl*********************************************************************************** 3904144411Sscottl*/ 3905144411Sscottl#define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/ 3906144411Sscottl/* 3907144411Sscottl*********************************************************************************** 3908144411Sscottl** PCI-X Next Item Pointer Register - PX_NXTP 3909144411Sscottl** 3910144411Sscottl** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3911144411Sscottl** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3912144411Sscottl** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults 3913144411Sscottl** to 00H. 3914144411Sscottl** However, this register may be written to B8H prior to host configuration to include the VPD 3915144411Sscottl** capability located at off-set B8H. 3916144411Sscottl** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may 3917144411Sscottl** produce unpredictable system behavior. 3918144411Sscottl** In order to guarantee that this register is written prior to host configuration, the 80331 must be 3919144411Sscottl** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically, 3920144411Sscottl** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in 3921144411Sscottl** this case (bit 1 of PCSR), as well. Please see Table 125, ��PCI Configuration and Status Register - 3922144411Sscottl** PCSR�� on page 253 for more details on the 80331 initialization modes. 3923144411Sscottl** ----------------------------------------------------------------- 3924144411Sscottl** Bit Default Description 3925144411Sscottl** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3926165155Sscottl** next item in the function��s capability list. Since the PCI-X capabilities are the last in the linked list of 3927165155Sscottl** extended capabilities in the 80331, the register is set to 00H. 3928165155Sscottl** However, this field may be written prior to host configuration with B8H to extend the list to include the 3929165155Sscottl** VPD extended capabilities header. 3930144411Sscottl*********************************************************************************** 3931144411Sscottl*/ 3932144411Sscottl#define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/ 3933144411Sscottl/* 3934144411Sscottl*********************************************************************************** 3935144411Sscottl** PCI-X Command Register - PX_CMD 3936144411Sscottl** 3937144411Sscottl** This register controls various modes and features of ATU and Message Unit when operating in the 3938144411Sscottl** PCI-X mode. 3939144411Sscottl** ----------------------------------------------------------------- 3940144411Sscottl** Bit Default Description 3941144411Sscottl** 15:7 000000000 2 Reserved. 3942144411Sscottl** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions 3943165155Sscottl** the device is permitted to have outstanding at one time. 3944165155Sscottl** Register Maximum Outstanding 3945165155Sscottl** 0 1 3946165155Sscottl** 1 2 3947165155Sscottl** 2 3 3948165155Sscottl** 3 4 3949165155Sscottl** 4 8 3950165155Sscottl** 5 12 3951165155Sscottl** 6 16 3952165155Sscottl** 7 32 3953144411Sscottl** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when 3954165155Sscottl** initiating a Sequence with one of the burst memory read commands. 3955165155Sscottl** Register Maximum Byte Count 3956165155Sscottl** 0 512 3957165155Sscottl** 1 1024 3958165155Sscottl** 2 2048 3959165155Sscottl** 3 4096 3960165155Sscottl** 1 0 2 3961165155Sscottl** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes 3962165155Sscottl** of Transactions. 3963144411Sscottl** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to 3964165155Sscottl** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts 3965165155Sscottl** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set. 3966144411Sscottl*********************************************************************************** 3967144411Sscottl*/ 3968144411Sscottl#define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/ 3969144411Sscottl/* 3970144411Sscottl*********************************************************************************** 3971144411Sscottl** PCI-X Status Register - PX_SR 3972144411Sscottl** 3973144411Sscottl** This register identifies the capabilities and current operating mode of ATU, DMAs and Message 3974144411Sscottl** Unit when operating in the PCI-X mode. 3975144411Sscottl** ----------------------------------------------------------------- 3976144411Sscottl** Bit Default Description 3977144411Sscottl** 31:30 00 2 Reserved 3978144411Sscottl** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3979165155Sscottl** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software 3980165155Sscottl** writes a 1 to this location. 3981165155Sscottl** 0=no Split Completion error message received. 3982165155Sscottl** 1=a Split Completion error message has been received. 3983144411Sscottl** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting 3984165155Sscottl** of the Maximum Memory Read Byte Count field of the PCIXCMD register: 3985165155Sscottl** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting 3986165155Sscottl** 1 16 512 (Default) 3987165155Sscottl** 2 32 1024 3988165155Sscottl** 2 32 2048 3989165155Sscottl** 2 32 4096 3990144411Sscottl** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions. 3991165155Sscottl** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up 3992165155Sscottl** to 1024 bytes. 3993144411Sscottl** 20 1 2 80331 is a complex device. 3994144411Sscottl** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device��s 3995165155Sscottl** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location. 3996165155Sscottl** 0=no unexpected Split Completion has been received. 3997165155Sscottl** 1=an unexpected Split Completion has been received. 3998144411Sscottl** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the 3999165155Sscottl** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus 4000165155Sscottl** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this 4001165155Sscottl** location. 4002165155Sscottl** 0=no Split Completion has been discarded. 4003165155Sscottl** 1=a Split Completion has been discarded. 4004165155Sscottl** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read 4005165155Sscottl** Requests with Split Responses (Memory or Register) that has ��read side effects.�� 4006144411Sscottl** 17 1 2 80331 is a 133 MHz capable device. 4007165155Sscottl** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, 4008165155Sscottl** therefore this bit is always set. 4009165155Sscottl** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), 4010165155Sscottl** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 4011165155Sscottl** This strap, by default, identifies the add in card based on 80331 with bridge disabled 4012165155Sscottl** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap. 4013165155Sscottl** 0=The bus is 32 bits wide. 4014165155Sscottl** 1=The bus is 64 bits wide. 4015144411Sscottl** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus 4016165155Sscottl** segment for the device containing this function. The function uses this number as part of its Requester 4017165155Sscottl** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed 4018165155Sscottl** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0] 4019165155Sscottl** of the attribute phase of the Configuration Write, regardless of which register in the function is 4020165155Sscottl** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of 4021165155Sscottl** the following are true: 4022165155Sscottl** 1. The transaction uses a Configuration Write command. 4023165155Sscottl** 2. IDSEL is asserted during the address phase. 4024165155Sscottl** 3. AD[1::0] are 00b (Type 0 configuration transaction). 4025165155Sscottl** 4. AD[10::08] of the configuration address contain the appropriate function number. 4026144411Sscottl** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device 4027165155Sscottl** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a 4028165155Sscottl** Type 0 configuration transaction that is assigned to the device containing this function by the connection 4029165155Sscottl** of the system hardware. The system must assign a device number other than 00h (00h is reserved for 4030165155Sscottl** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each 4031165155Sscottl** time the function is addressed by a Configuration Write transaction, the device must update this register 4032165155Sscottl** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which 4033165155Sscottl** register in the function is addressed by the transaction. The function is addressed by a Configuration 4034165155Sscottl** Write transaction when all of the following are true: 4035165155Sscottl** 1. The transaction uses a Configuration Write command. 4036165155Sscottl** 2. IDSEL is asserted during the address phase. 4037165155Sscottl** 3. AD[1::0] are 00b (Type 0 configuration transaction). 4038165155Sscottl** 4. AD[10::08] of the configuration address contain the appropriate function number. 4039144411Sscottl** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this 4040165155Sscottl** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0 4041165155Sscottl** configuration transaction to which this function responds. The function uses this number as part of its 4042165155Sscottl** Requester ID and Completer ID. 4043165155Sscottl** 4044144411Sscottl************************************************************************** 4045144411Sscottl*/ 4046144411Sscottl#define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/ 4047144411Sscottl 4048144411Sscottl/* 4049144411Sscottl************************************************************************** 4050144411Sscottl** Inbound Read Transaction 4051144411Sscottl** ======================================================================== 4052144411Sscottl** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local 4053144411Sscottl** memory or a 80331 memory-mapped register space. The read transaction is propagated through 4054144411Sscottl** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue 4055144411Sscottl** (IRQ). 4056144411Sscottl** When operating in the conventional PCI mode, all inbound read transactions are processed as 4057144411Sscottl** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are 4058144411Sscottl** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards 4059144411Sscottl** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for 4060144411Sscottl** an inbound read transaction on the PCI bus is summarized in the following statements: 4061144411Sscottl** �E The ATU claims the PCI read transaction when the PCI address is within the inbound 4062144411Sscottl** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base 4063144411Sscottl** Address Register during DACs) and Inbound Limit Register. 4064144411Sscottl** �E When operating in the conventional PCI mode, when the ITQ is currently holding transaction 4065144411Sscottl** information from a previous delayed read, the current transaction information is compared to 4066144411Sscottl** the previous transaction information (based on the setting of the DRC Alias bit in 4067144411Sscottl** Section 3.10.39, ��ATU Configuration Register - ATUCR�� on page 252). When there is a 4068144411Sscottl** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a 4069144411Sscottl** match and the data is not available, a Retry is signaled with no other action taken. When there 4070144411Sscottl** is not a match and when the ITQ has less than eight entries, capture the transaction 4071144411Sscottl** information, signal a Retry and initiate a delayed transaction. When there is not a match and 4072144411Sscottl** when the ITQ is full, then signal a Retry with no other action taken. 4073144411Sscottl** �X When an address parity error is detected, the address parity response defined in 4074144411Sscottl** Section 3.7 is used. 4075144411Sscottl** �E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from 4076144411Sscottl** the IRQ, it continues until one of the following is true: 4077144411Sscottl** �X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the 4078144411Sscottl** data is flushed. 4079144411Sscottl** �X An internal bus Target Abort was detected. In this case, the QWORD associated with the 4080144411Sscottl** Target Abort is never entered into the IRQ, and therefore is never returned. 4081144411Sscottl** �X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error. 4082144411Sscottl** �X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to 4083144411Sscottl** the initiator on the last data word available. 4084144411Sscottl** �E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and 4085144411Sscottl** command are latched into the available ITQ and a Split Response Termination is signalled to 4086144411Sscottl** the initiator. 4087144411Sscottl** �E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned 4088144411Sscottl** boundary, then the ATU waits until it receives the full byte count from the internal bus target 4089144411Sscottl** before returning read data by generating the split completion transaction on the PCI-X bus. 4090144411Sscottl** When the read requested crosses at least one 1024 byte boundary, then ATU completes the 4091144411Sscottl** transfer by returning data in 1024 byte aligned chunks. 4092144411Sscottl** �E When operating in the PCI-X mode, once a split completion transaction has started, it 4093144411Sscottl** continues until one of the following is true: 4094144411Sscottl** �X The requester (now the target) generates a Retry Termination, or a Disconnection at Next 4095144411Sscottl** ADB (when the requester is a bridge) 4096144411Sscottl** �X The byte count is satisfied. 4097144411Sscottl** �X An internal bus Target Abort was detected. The ATU generates a Split Completion 4098144411Sscottl** Message (message class=2h - completer error, and message index=81h - target abort) to 4099144411Sscottl** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 4100144411Sscottl** Refer to Section 3.7.1. 4101144411Sscottl** �X An internal bus Master Abort was detected. The ATU generates a Split Completion 4102144411Sscottl** Message (message class=2h - completer error, and message index=80h - Master abort) to 4103144411Sscottl** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 4104144411Sscottl** Refer to Section 3.7.1 4105144411Sscottl** �E When operating in the conventional PCI mode, when the master inserts wait states on the PCI 4106144411Sscottl** bus, the ATU PCI slave interface waits with no premature disconnects. 4107144411Sscottl** �E When a data parity error occurs signified by PERR# asserted from the initiator, no action is 4108144411Sscottl** taken by the target interface. Refer to Section 3.7.2.5. 4109144411Sscottl** �E When operating in the conventional PCI mode, when the read on the internal bus is 4110144411Sscottl** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is 4111144411Sscottl** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a 4112144411Sscottl** target abort is used, when clear, a disconnect is used. 4113144411Sscottl** �E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h 4114144411Sscottl** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates 4115144411Sscottl** a Split Completion Message (message class=2h - completer error, and message index=81h - 4116144411Sscottl** internal bus target abort) to inform the requester about the abnormal condition. For the MU 4117144411Sscottl** queue ports, the ATU returns either a target abort or a single data phase disconnect depending 4118144411Sscottl** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this 4119144411Sscottl** transaction is flushed. Refer to Section 3.7.1. 4120144411Sscottl** �E When operating in the conventional PCI mode, when the transaction on the internal bus 4121144411Sscottl** resulted in a master abort, the ATU returns a target abort to inform the requester about the 4122144411Sscottl** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1 4123144411Sscottl** �E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a 4124144411Sscottl** master abort, the ATU generates a Split Completion Message (message class=2h - completer 4125144411Sscottl** error, and message index=80h - internal bus master abort) to inform the requester about the 4126144411Sscottl** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1. 4127144411Sscottl** �E When operating in the PCI-X mode, when the Split Completion transaction completes with 4128144411Sscottl** either Master-Abort or Target-Abort, the requester is indicating a failure condition that 4129144411Sscottl** prevents it from accepting the completion it requested. In this case, since the Split Request 4130144411Sscottl** addresses a location that has no read side effects, the completer must discard the Split 4131144411Sscottl** Completion and take no further action. 4132144411Sscottl** The data flow for an inbound read transaction on the internal bus is summarized in the following 4133144411Sscottl** statements: 4134144411Sscottl** �E The ATU internal bus master interface requests the internal bus when a PCI address appears in 4135144411Sscottl** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the 4136144411Sscottl** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU 4137144411Sscottl** always uses conventional PCI ordering rules. 4138144411Sscottl** �E Once the internal bus is granted, the internal bus master interface drives the translated address 4139144411Sscottl** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated. 4140144411Sscottl** When a master abort occurs, the transaction is considered complete and a target abort is loaded 4141144411Sscottl** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI 4142144411Sscottl** master has been delivered the target abort). 4143144411Sscottl** �E Once the translated address is on the bus and the transaction has been accepted, the internal 4144144411Sscottl** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously 4145144411Sscottl** received by the IRQ until one of the following is true: 4146144411Sscottl** �X The full byte count requested by the ATU read request is received. The ATU internal bus 4147144411Sscottl** initiator interface performs a initiator completion in this case. 4148144411Sscottl** �X When operating in the conventional PCI mode, a Target Abort is received on the internal 4149144411Sscottl** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is 4150144411Sscottl** informed. 4151144411Sscottl** �X When operating in the PCI-X mode, a Target Abort is received on the internal bus from 4152144411Sscottl** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split 4153144411Sscottl** Completion Message (message class=2h - completer error, and message index=81h - 4154144411Sscottl** target abort) on the PCI bus to inform the requester about the abnormal condition. The 4155144411Sscottl** ITQ for this transaction is flushed. 4156144411Sscottl** �X When operating in the conventional PCI mode, a single data phase disconnection is 4157144411Sscottl** received from the internal bus target. When the data has not been received up to the next 4158144411Sscottl** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus. 4159144411Sscottl** When not, the bus returns to idle. 4160144411Sscottl** �X When operating in the PCI-X mode, a single data phase disconnection is received from 4161144411Sscottl** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to 4162144411Sscottl** obtain remaining data. 4163144411Sscottl** �X When operating in the conventional PCI mode, a disconnection at Next ADB is received 4164144411Sscottl** from the internal bus target. The bus returns to idle. 4165144411Sscottl** �X When operating in the PCI-X mode, a disconnection at Next ADB is received from the 4166144411Sscottl** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain 4167144411Sscottl** remaining data. 4168144411Sscottl** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to 4169144411Sscottl** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read 4170144411Sscottl** Multiple) when trying to match the current inbound read transaction with data in a DRC queue 4171144411Sscottl** which was read previously (DRC on target bus). When the Read Command Alias Bit in the 4172144411Sscottl** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For 4173144411Sscottl** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read 4174144411Sscottl** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address 4175144411Sscottl** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return 4176144411Sscottl** the read data from the DRC queue and consider the Delayed Read transaction complete. When the 4177144411Sscottl** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read 4178144411Sscottl** commands did not match, only the address. 4179144411Sscottl************************************************************************** 4180144411Sscottl*/ 4181144411Sscottl/* 4182144411Sscottl************************************************************************** 4183144411Sscottl** Inbound Write Transaction 4184144411Sscottl**======================================================================== 4185144411Sscottl** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local 4186144411Sscottl** memory or a 80331 memory-mapped register. 4187144411Sscottl** Data flow for an inbound write transaction on the PCI bus is summarized as: 4188144411Sscottl** �E The ATU claims the PCI write transaction when the PCI address is within the inbound 4189144411Sscottl** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper 4190144411Sscottl** Base Address Register during DACs) and Inbound Limit Register. 4191144411Sscottl** �E When the IWADQ has at least one address entry available and the IWQ has at least one buffer 4192144411Sscottl** available, the address is captured and the first data phase is accepted. 4193144411Sscottl** �E The PCI interface continues to accept write data until one of the following is true: 4194144411Sscottl** �X The initiator performs a disconnect. 4195144411Sscottl** �X The transaction crosses a buffer boundary. 4196144411Sscottl** �E When an address parity error is detected during the address phase of the transaction, the 4197144411Sscottl** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address 4198144411Sscottl** parity error response. 4199144411Sscottl** �E When operating in the PCI-X mode when an attribute parity error is detected, the attribute 4200144411Sscottl** parity error mechanism described in Section 3.7.1 is used. 4201144411Sscottl** �E When a data parity error is detected while accepting data, the slave interface sets the 4202144411Sscottl** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6 4203144411Sscottl** for details of the inbound write data parity error response. 4204144411Sscottl** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient 4205144411Sscottl** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus 4206144411Sscottl** interface becomes aware of the inbound write. When there are additional write transactions ahead 4207144411Sscottl** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been 4208144411Sscottl** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU 4209144411Sscottl** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI 4210144411Sscottl** interface, when operating in the PCI mode. 4211144411Sscottl** In the PCI-X mode memory writes are always executed as immediate transactions, while 4212144411Sscottl** configuration write transactions are processed as split transactions. The ATU generates a Split 4213144411Sscottl** Completion Message, (with Message class=0h - Write Completion Class and Message index = 4214144411Sscottl** 00h - Write Completion Message) once a configuration write is successfully executed. 4215144411Sscottl** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions. 4216144411Sscottl** The ATU handles such transactions as independent transactions. 4217144411Sscottl** Data flow for the inbound write transaction on the internal bus is summarized as: 4218144411Sscottl** �E The ATU internal bus master requests the internal bus when IWADQ has at least one entry 4219144411Sscottl** with associated data in the IWQ. 4220144411Sscottl** �E When the internal bus is granted, the internal bus master interface initiates the write 4221144411Sscottl** transaction by driving the translated address onto the internal bus. For details on inbound 4222144411Sscottl** address translation. 4223144411Sscottl** �E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus. 4224144411Sscottl** The current transaction is flushed from the queue and SERR# may be asserted on the PCI 4225144411Sscottl** interface. 4226144411Sscottl** �E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When 4227144411Sscottl** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the 4228144411Sscottl** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred 4229144411Sscottl** from the IWQ to the internal bus when data is available and the internal bus interface retains 4230144411Sscottl** internal bus ownership. 4231144411Sscottl** �E The internal bus interface stops transferring data from the current transaction to the internal 4232144411Sscottl** bus when one of the following conditions becomes true: 4233144411Sscottl** �X The internal bus initiator interface loses bus ownership. The ATU internal initiator 4234144411Sscottl** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB 4235144411Sscottl** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to 4236144411Sscottl** complete the delivery of remaining data using the same sequence ID but with the 4237144411Sscottl** modified starting address and byte count. 4238144411Sscottl** �X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When 4239144411Sscottl** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the 4240144411Sscottl** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to 4241144411Sscottl** complete the delivery of remaining data using the same sequence ID but with the 4242144411Sscottl** modified starting address and byte count. 4243144411Sscottl** �X A Single Data Phase Disconnect is signaled on the internal bus from the internal target. 4244144411Sscottl** When the transaction in the IWQ needs only a single data phase, the master returns to idle. 4245144411Sscottl** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the 4246144411Sscottl** bus to complete the delivery of remaining data using the same sequence ID but with the 4247144411Sscottl** modified starting address and byte count. 4248144411Sscottl** �X The data from the current transaction has completed (satisfaction of byte count). An 4249144411Sscottl** initiator termination is performed and the bus returns to idle. 4250144411Sscottl** �X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus. 4251144411Sscottl** Data is flushed from the IWQ. 4252144411Sscottl***************************************************************** 4253144411Sscottl*/ 4254144411Sscottl 4255144411Sscottl 4256144411Sscottl 4257144411Sscottl/* 4258144411Sscottl************************************************************************** 4259144411Sscottl** Inbound Read Completions Data Parity Errors 4260144411Sscottl**======================================================================== 4261144411Sscottl** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4262144411Sscottl** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split 4263144411Sscottl** completion transaction, the ATU attempts to complete the transaction normally and no further 4264144411Sscottl** action is taken. 4265144411Sscottl************************************************************************** 4266144411Sscottl*/ 4267144411Sscottl 4268144411Sscottl/* 4269144411Sscottl************************************************************************** 4270144411Sscottl** Inbound Configuration Write Completion Message Data Parity Errors 4271144411Sscottl**======================================================================== 4272144411Sscottl** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4273144411Sscottl** When as the completer of a Configuration (Split) Write Request the ATU observes PERR# 4274144411Sscottl** assertion during the split completion transaction, the ATU attempts to complete the transaction 4275144411Sscottl** normally and no further action is taken. 4276144411Sscottl************************************************************************** 4277144411Sscottl*/ 4278144411Sscottl 4279144411Sscottl/* 4280144411Sscottl************************************************************************** 4281144411Sscottl** Inbound Read Request Data Parity Errors 4282144411Sscottl**===================== Immediate Data Transfer ========================== 4283144411Sscottl** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes. 4284144411Sscottl** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having 4285144411Sscottl** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally 4286144411Sscottl** report the error to the system by asserting PERR#. As a target device in this scenario, no action is 4287144411Sscottl** required and no error bits are set. 4288144411Sscottl**=====================Split Response Termination========================= 4289144411Sscottl** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4290144411Sscottl** Inbound read data parity errors occur during the Split Response Termination. The initiator may 4291144411Sscottl** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no 4292144411Sscottl** action is required and no error bits are set. 4293144411Sscottl************************************************************************** 4294144411Sscottl*/ 4295144411Sscottl 4296144411Sscottl/* 4297144411Sscottl************************************************************************** 4298144411Sscottl** Inbound Write Request Data Parity Errors 4299144411Sscottl**======================================================================== 4300144411Sscottl** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4301144411Sscottl** Data parity errors occurring during write operations received by the ATU may assert PERR# on 4302144411Sscottl** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write 4303144411Sscottl** transaction completes or a queue fill condition is reached. Specifically, the following actions with 4304144411Sscottl** the given constraints are taken by the ATU: 4305144411Sscottl** �E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode) 4306144411Sscottl** following the data phase in which the data parity error is detected on the bus. This is only 4307144411Sscottl** done when the Parity Error Response bit in the ATUCMD is set. 4308144411Sscottl** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4309144411Sscottl** actions is taken: 4310144411Sscottl** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4311144411Sscottl** Detected Parity Error bit in the ATUISR. When set, no action. 4312144411Sscottl*************************************************************************** 4313144411Sscottl*/ 4314144411Sscottl 4315144411Sscottl 4316144411Sscottl/* 4317144411Sscottl*************************************************************************** 4318144411Sscottl** Inbound Configuration Write Request 4319144411Sscottl** ===================================================================== 4320144411Sscottl** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4321144411Sscottl** =============================================== 4322144411Sscottl** Conventional PCI Mode 4323144411Sscottl** =============================================== 4324144411Sscottl** To allow for correct data parity calculations for delayed write transactions, the ATU delays the 4325144411Sscottl** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a 4326144411Sscottl** delayed write transaction (inbound configuration write cycle) can occur in any of the following 4327144411Sscottl** parts of the transactions: 4328144411Sscottl** �E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the 4329144411Sscottl** address/command and data for delayed delivery to the internal configuration register. 4330144411Sscottl** �E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status 4331144411Sscottl** of the operation back to the original master. 4332144411Sscottl** The 80331 ATU PCI interface has the following responses to a delayed write parity error for 4333144411Sscottl** inbound transactions during Delayed Write Request cycles with the given constraints: 4334144411Sscottl** �E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY# 4335144411Sscottl** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the 4336144411Sscottl** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus. 4337144411Sscottl** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the 4338144411Sscottl** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be 4339144411Sscottl** forwarded to the internal bus. PERR# is not asserted. 4340144411Sscottl** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4341144411Sscottl** actions is taken: 4342144411Sscottl** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4343144411Sscottl** Detected Parity Error bit in the ATUISR. When set, no action. 4344144411Sscottl** For the original write transaction to be completed, the initiator retries the transaction on the PCI 4345144411Sscottl** bus and the ATU returns the status from the internal bus, completing the transaction. 4346144411Sscottl** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and 4347144411Sscottl** therefore does not agree with the status being returned from the internal bus (i.e. status being 4348144411Sscottl** returned is normal completion) the ATU performs the following actions with the given constraints: 4349144411Sscottl** �E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY# 4350144411Sscottl** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in 4351144411Sscottl** the IDWQ remains since the data of retried command did not match the data within the queue. 4352144411Sscottl** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4353144411Sscottl** actions is taken: 4354144411Sscottl** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4355144411Sscottl** Detected Parity Error bit in the ATUISR. When set, no action. 4356144411Sscottl** =================================================== 4357144411Sscottl** PCI-X Mode 4358144411Sscottl** =================================================== 4359144411Sscottl** Data parity errors occurring during configuration write operations received by the ATU may cause 4360144411Sscottl** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error 4361144411Sscottl** occurs, the ATU accepts the write data and complete with a Split Response Termination. 4362144411Sscottl** Specifically, the following actions with the given constraints are then taken by the ATU: 4363144411Sscottl** �E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks 4364144411Sscottl** cycles following the Split Response Termination in which the data parity error is detected on 4365144411Sscottl** the bus. When the ATU asserts PERR#, additional actions is taken: 4366144411Sscottl** �X A Split Write Data Parity Error message (with message class=2h - completer error and 4367144411Sscottl** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus 4368144411Sscottl** that addresses the requester of the configuration write. 4369144411Sscottl** �X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is 4370144411Sscottl** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no 4371144411Sscottl** action. 4372144411Sscottl** �X The Split Write Request is not enqueued and forwarded to the internal bus. 4373144411Sscottl** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4374144411Sscottl** actions is taken: 4375144411Sscottl** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4376144411Sscottl** Detected Parity Error bit in the ATUISR. When set, no action. 4377144411Sscottl** 4378144411Sscottl*************************************************************************** 4379144411Sscottl*/ 4380144411Sscottl 4381144411Sscottl/* 4382144411Sscottl*************************************************************************** 4383144411Sscottl** Split Completion Messages 4384144411Sscottl** ======================================================================= 4385144411Sscottl** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4386144411Sscottl** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert 4387144411Sscottl** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the 4388144411Sscottl** ATU accepts the data and complete normally. Specifically, the following actions with the given 4389144411Sscottl** constraints are taken by the ATU: 4390144411Sscottl** �E PERR# is asserted three clocks cycles following the data phase in which the data parity error 4391144411Sscottl** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD 4392144411Sscottl** is set. When the ATU asserts PERR#, additional actions is taken: 4393144411Sscottl** �X The Master Parity Error bit in the ATUSR is set. 4394144411Sscottl** �X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the 4395144411Sscottl** PCI Master Parity Error bit in the ATUISR. When set, no action. 4396144411Sscottl** �X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover 4397144411Sscottl** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken. 4398144411Sscottl** When the ATU asserts SERR#, additional actions is taken: 4399144411Sscottl** Set the SERR# Asserted bit in the ATUSR. 4400144411Sscottl** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the 4401144411Sscottl** SERR# Asserted bit in the ATUISR. When set, no action. 4402144411Sscottl** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the 4403144411Sscottl** SERR# Detected bit in the ATUISR. When clear, no action. 4404144411Sscottl** �E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during 4405144411Sscottl** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set. 4406144411Sscottl** When the ATU sets this bit, additional actions is taken: 4407144411Sscottl** �X When the ATU Received Split Completion Error Message Interrupt Mask bit in the 4408144411Sscottl** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR. 4409144411Sscottl** When set, no action. 4410144411Sscottl** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4411144411Sscottl** actions is taken: 4412144411Sscottl** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4413144411Sscottl** Detected Parity Error bit in the ATUISR. When set, no action. 4414144411Sscottl** �E The transaction associated with the Split Completion Message is discarded. 4415144411Sscottl** �E When the discarded transaction was a read, a completion error message (with message 4416144411Sscottl** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on 4417144411Sscottl** the internal bus of the 80331. 4418144411Sscottl***************************************************************************** 4419144411Sscottl*/ 4420144411Sscottl 4421144411Sscottl 4422144411Sscottl/* 4423144411Sscottl****************************************************************************************************** 4424144411Sscottl** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) 4425144411Sscottl** ================================================================================================== 4426144411Sscottl** The Messaging Unit (MU) transfers data between the PCI system and the 80331 4427144411Sscottl** notifies the respective system when new data arrives. 4428144411Sscottl** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation. 4429144411Sscottl** window defined by: 4430144411Sscottl** 1.Inbound ATU Base Address Register 0 (IABAR0) 4431144411Sscottl** 2.Inbound ATU Limit Register 0 (IALR0) 4432144411Sscottl** All of the Messaging Unit errors are reported in the same manner as ATU errors. 4433144411Sscottl** Error conditions and status can be found in : 4434144411Sscottl** 1.ATUSR 4435144411Sscottl** 2.ATUISR 4436144411Sscottl**==================================================================================================== 4437144411Sscottl** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt 4438144411Sscottl**---------------------------------------------------------------------------------------------------- 4439144411Sscottl** Message Registers 2 Inbound Optional Optional 4440144411Sscottl** 2 Outbound 4441144411Sscottl**---------------------------------------------------------------------------------------------------- 4442144411Sscottl** Doorbell Registers 1 Inbound Optional Optional 4443144411Sscottl** 1 Outbound 4444144411Sscottl**---------------------------------------------------------------------------------------------------- 4445144411Sscottl** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions 4446144411Sscottl**---------------------------------------------------------------------------------------------------- 4447144411Sscottl** Index Registers 1004 32-bit Memory Locations No Optional 4448144411Sscottl**==================================================================================================== 4449144411Sscottl** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space 4450144411Sscottl**==================================================================================================== 4451144411Sscottl** 0000H Reserved 4452144411Sscottl** 0004H Reserved 4453144411Sscottl** 0008H Reserved 4454144411Sscottl** 000CH Reserved 4455144411Sscottl**------------------------------------------------------------------------ 4456144411Sscottl** 0010H Inbound Message Register 0 ] 4457144411Sscottl** 0014H Inbound Message Register 1 ] 4458144411Sscottl** 0018H Outbound Message Register 0 ] 4459144411Sscottl** 001CH Outbound Message Register 1 ] 4 Message Registers 4460144411Sscottl**------------------------------------------------------------------------ 4461144411Sscottl** 0020H Inbound Doorbell Register ] 4462144411Sscottl** 0024H Inbound Interrupt Status Register ] 4463144411Sscottl** 0028H Inbound Interrupt Mask Register ] 4464144411Sscottl** 002CH Outbound Doorbell Register ] 4465144411Sscottl** 0030H Outbound Interrupt Status Register ] 4466144411Sscottl** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers 4467144411Sscottl**------------------------------------------------------------------------ 4468144411Sscottl** 0038H Reserved 4469144411Sscottl** 003CH Reserved 4470144411Sscottl**------------------------------------------------------------------------ 4471144411Sscottl** 0040H Inbound Queue Port ] 4472144411Sscottl** 0044H Outbound Queue Port ] 2 Queue Ports 4473144411Sscottl**------------------------------------------------------------------------ 4474144411Sscottl** 0048H Reserved 4475144411Sscottl** 004CH Reserved 4476144411Sscottl**------------------------------------------------------------------------ 4477144411Sscottl** 0050H ] 4478144411Sscottl** : ] 4479144411Sscottl** : Intel Xscale Microarchitecture Local Memory ] 4480144411Sscottl** : ] 4481144411Sscottl** 0FFCH ] 1004 Index Registers 4482144411Sscottl******************************************************************************* 4483144411Sscottl*/ 4484144411Sscottl/* 4485144411Sscottl***************************************************************************** 4486144411Sscottl** Theory of MU Operation 4487144411Sscottl***************************************************************************** 4488144411Sscottl**-------------------- 4489144411Sscottl** inbound_msgaddr0: 4490144411Sscottl** inbound_msgaddr1: 4491144411Sscottl** outbound_msgaddr0: 4492144411Sscottl** outbound_msgaddr1: 4493144411Sscottl** . The MU has four independent messaging mechanisms. 4494144411Sscottl** There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 4495144411Sscottl** Each holds a 32-bit value and generates an interrupt when written. 4496144411Sscottl**-------------------- 4497144411Sscottl** inbound_doorbell: 4498144411Sscottl** outbound_doorbell: 4499144411Sscottl** . The two Doorbell Registers support software interrupts. 4500144411Sscottl** When a bit is set in a Doorbell Register, an interrupt is generated. 4501144411Sscottl**-------------------- 4502144411Sscottl** inbound_queueport: 4503144411Sscottl** outbound_queueport: 4504144411Sscottl** 4505144411Sscottl** 4506144411Sscottl** . The Circular Queues support a message passing scheme that uses 4 circular queues. 4507144411Sscottl** The 4 circular queues are implemented in 80331 local memory. 4508144411Sscottl** Two queues are used for inbound messages and two are used for outbound messages. 4509144411Sscottl** Interrupts may be generated when the queue is written. 4510144411Sscottl**-------------------- 4511144411Sscottl** local_buffer 0x0050 ....0x0FFF 4512144411Sscottl** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 4513144411Sscottl** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured. 4514144411Sscottl** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 4515144411Sscottl** Each interrupt generated by the Messaging Unit can be masked. 4516144411Sscottl**-------------------- 4517144411Sscottl** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 4518144411Sscottl** with the exception of Multi-DWORD reads to the index registers. 4519165155Sscottl** In Conventional mode: the MU terminates Multi-DWORD PCI transactions 4520165155Sscottl** (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 4521165155Sscottl** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response 4522165155Sscottl** and the data is returned through split completion transaction(s). 4523165155Sscottl** however, when the burst request crosses into or through the range of offsets 40h to 4Ch 4524165155Sscottl** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 4525165155Sscottl** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect 4526165155Sscottl** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written. 4527144411Sscottl**-------------------- 4528144411Sscottl** . All registers needed to configure and control the Messaging Unit are memory-mapped registers. 4529144411Sscottl** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU). 4530144411Sscottl** This PCI address window is used for PCI transactions that access the 80331 local memory. 4531144411Sscottl** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register. 4532144411Sscottl**-------------------- 4533144411Sscottl** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit. 4534144411Sscottl** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information. 4535144411Sscottl** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register. 4536144411Sscottl** The Messaging Unit reports all PCI errors in the ATU Status Register. 4537144411Sscottl**-------------------- 4538144411Sscottl** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 4539165155Sscottl** The register interface, message registers, doorbell registers, 4540165155Sscottl** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 4541144411Sscottl** Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 4542144411Sscottl** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H. 4543144411Sscottl************************************************************************** 4544144411Sscottl*/ 4545144411Sscottl/* 4546144411Sscottl************************************************************************** 4547144411Sscottl** Message Registers 4548144411Sscottl** ============================== 4549144411Sscottl** . Messages can be sent and received by the 80331 through the use of the Message Registers. 4550144411Sscottl** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor. 4551144411Sscottl** . Inbound messages are sent by the host processor and received by the 80331. 4552144411Sscottl** Outbound messages are sent by the 80331 and received by the host processor. 4553144411Sscottl** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register. 4554144411Sscottl** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register. 4555165155Sscottl** 4556144411Sscottl** Inbound Messages: 4557144411Sscottl** ----------------- 4558144411Sscottl** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 4559144411Sscottl** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register. 4560144411Sscottl** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 4561144411Sscottl** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 4562144411Sscottl** This is a Read/Clear bit that is set by the MU hardware and cleared by software. 4563165155Sscottl** The interrupt is cleared when the Intel XScale core writes a value of 4564165155Sscottl** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register. 4565144411Sscottl** ------------------------------------------------------------------------ 4566144411Sscottl** Inbound Message Register - IMRx 4567144411Sscottl** 4568144411Sscottl** . There are two Inbound Message Registers: IMR0 and IMR1. 4569144411Sscottl** . When the IMR register is written, an interrupt to the Intel XScale core may be generated. 4570165155Sscottl** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked 4571165155Sscottl** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register. 4572144411Sscottl** ----------------------------------------------------------------- 4573144411Sscottl** Bit Default Description 4574144411Sscottl** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent. 4575144411Sscottl** When written, an interrupt to the Intel XScale core may be generated. 4576144411Sscottl************************************************************************** 4577144411Sscottl*/ 4578144411Sscottl#define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/ 4579144411Sscottl#define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/ 4580144411Sscottl/* 4581144411Sscottl************************************************************************** 4582144411Sscottl** Outbound Message Register - OMRx 4583144411Sscottl** -------------------------------- 4584144411Sscottl** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is 4585144411Sscottl** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt 4586144411Sscottl** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound 4587144411Sscottl** Interrupt Mask Register. 4588165155Sscottl** 4589144411Sscottl** Bit Default Description 4590144411Sscottl** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an 4591144411Sscottl** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register. 4592144411Sscottl************************************************************************** 4593144411Sscottl*/ 4594144411Sscottl#define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 4595144411Sscottl#define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 4596144411Sscottl/* 4597144411Sscottl************************************************************************** 4598144411Sscottl** Doorbell Registers 4599144411Sscottl** ============================== 4600144411Sscottl** There are two Doorbell Registers: 4601144411Sscottl** Inbound Doorbell Register 4602144411Sscottl** Outbound Doorbell Register 4603144411Sscottl** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 4604144411Sscottl** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 4605144411Sscottl** Both Doorbell Registers may generate interrupts whenever a bit in the register is set. 4606165155Sscottl** 4607144411Sscottl** Inbound Doorbells: 4608144411Sscottl** ------------------ 4609144411Sscottl** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core. 4610144411Sscottl** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1. 4611144411Sscottl** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 4612144411Sscottl** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 4613144411Sscottl** The interrupt is recorded in the Inbound Interrupt Status Register. 4614144411Sscottl** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register. 4615144411Sscottl** When the mask bit is set for a particular bit, no interrupt is generated for that bit. 4616165155Sscottl** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt 4617165155Sscottl** and not the values written to the Inbound Doorbell Register. 4618144411Sscottl** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt. 4619144411Sscottl** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 4620144411Sscottl** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt. 4621144411Sscottl** ------------------------------------------------------------------------ 4622144411Sscottl** Inbound Doorbell Register - IDR 4623144411Sscottl** 4624144411Sscottl** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 4625144411Sscottl** . Bit 31 is reserved for generating an Error Doorbell interrupt. 4626144411Sscottl** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 4627144411Sscottl** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 4628144411Sscottl** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register. 4629144411Sscottl** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core. 4630144411Sscottl** ------------------------------------------------------------------------ 4631144411Sscottl** Bit Default Description 4632144411Sscottl** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core. 4633144411Sscottl** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 4634144411Sscottl** When all bits are clear, do not generate a Normal Interrupt. 4635144411Sscottl************************************************************************** 4636144411Sscottl*/ 4637144411Sscottl#define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 4638144411Sscottl/* 4639144411Sscottl************************************************************************** 4640144411Sscottl** Inbound Interrupt Status Register - IISR 4641144411Sscottl** 4642144411Sscottl** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 4643144411Sscottl** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 4644144411Sscottl** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 4645144411Sscottl** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 4646144411Sscottl** these two are routed to the Messaging Unit Error interrupt input. 4647165155Sscottl** The generation of interrupts recorded in the Inbound Interrupt Status Register 4648165155Sscottl** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 4649144411Sscottl** Some of the bits in this register are Read Only. 4650144411Sscottl** For those bits, the interrupt must be cleared through another register. 4651144411Sscottl** 4652144411Sscottl** Bit Default Description 4653144411Sscottl** 31:07 0000000H 0 2 Reserved 4654165155Sscottl** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware 4655165155Sscottl** when an Index Register has been written after a PCI transaction. 4656165155Sscottl** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set 4657165155Sscottl** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4658165155Sscottl** An Error interrupt is generated for this condition. 4659165155Sscottl** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 4660165155Sscottl** Once cleared, an interrupt does NOT be generated 4661165155Sscottl** when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4662165155Sscottl** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4663165155Sscottl** software must retain the information that the Inbound Post queue status is not empty. 4664165155Sscottl** NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller. 4665165155Sscottl** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set. 4666165155Sscottl** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear. 4667165155Sscottl** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one 4668165155Sscottl** Normal Interrupt bit in the Inbound Doorbell Register is set. 4669165155Sscottl** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear. 4670165155Sscottl** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written. 4671165155Sscottl** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written. 4672144411Sscottl************************************************************************** 4673144411Sscottl*/ 4674144411Sscottl#define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 4675144411Sscottl#define ARCMSR_MU_INBOUND_INDEX_INT 0x40 4676144411Sscottl#define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 4677144411Sscottl#define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 4678144411Sscottl#define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 4679144411Sscottl#define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 4680144411Sscottl#define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 4681144411Sscottl#define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 4682144411Sscottl/* 4683144411Sscottl************************************************************************** 4684144411Sscottl** Inbound Interrupt Mask Register - IIMR 4685144411Sscottl** 4686144411Sscottl** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 4687144411Sscottl** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register. 4688144411Sscottl** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 4689144411Sscottl** They only affect the generation of the Intel XScale core interrupt. 4690144411Sscottl** ------------------------------------------------------------------------ 4691144411Sscottl** Bit Default Description 4692144411Sscottl** 31:07 000000H 0 2 Reserved 4693165155Sscottl** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware 4694165155Sscottl** when an Index Register has been written after a PCI transaction. 4695165155Sscottl** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated 4696165155Sscottl** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4697165155Sscottl** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated 4698165155Sscottl** by the MU hardware when the Inbound Post Queue has been written. 4699165155Sscottl** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt 4700165155Sscottl** when the Error Interrupt bit of the Inbound Doorbell Register is set. 4701165155Sscottl** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated 4702165155Sscottl** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set. 4703165155Sscottl** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 4704165155Sscottl** Interrupt generated by a write to the Inbound Message 1 Register. 4705165155Sscottl** 00 0 2 Inbound Message 0 Interrupt Mask - When set, 4706165155Sscottl** this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register. 4707144411Sscottl************************************************************************** 4708144411Sscottl*/ 4709144411Sscottl#define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/ 4710144411Sscottl#define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 4711144411Sscottl#define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 4712144411Sscottl#define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 4713144411Sscottl#define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 4714144411Sscottl#define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 4715144411Sscottl#define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 4716144411Sscottl#define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 4717144411Sscottl/* 4718144411Sscottl************************************************************************** 4719144411Sscottl** Outbound Doorbell Register - ODR 4720144411Sscottl** 4721144411Sscottl** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 4722144411Sscottl** XScale core to generate PCI interrupts to the host processor by writing to this register. The 4723144411Sscottl** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the 4724144411Sscottl** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register. 4725144411Sscottl** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only 4726144411Sscottl** be cleared by an external PCI agent. 4727144411Sscottl** ---------------------------------------------------------------------- 4728144411Sscottl** Bit Default Description 4729144411Sscottl** 31 0 2 Reserved 4730144411Sscottl** 30 0 2 Reserved. 4731144411Sscottl** 29 0 2 Reserved 4732165155Sscottl** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output 4733165155Sscottl** (P_INTA# with BRG_EN and ARB_EN straps low) 4734144411Sscottl** signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 4735165155Sscottl** When this bit is cleared, the P_INTC# interrupt output 4736165155Sscottl** (P_INTA# with BRG_EN and ARB_EN straps low) 4737144411Sscottl** signal is deasserted. 4738165155Sscottl** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output 4739165155Sscottl** (P_INTA# with BRG_EN and ARB_EN straps low) 4740165155Sscottl** signal is asserted or a Message-signaled Interrupt is generated (when enabled). 4741165155Sscottl** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 4742165155Sscottl** signal is deasserted. 4743144411Sscottl************************************************************************** 4744144411Sscottl*/ 4745144411Sscottl#define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/ 4746144411Sscottl/* 4747144411Sscottl************************************************************************** 4748144411Sscottl** Outbound Interrupt Status Register - OISR 4749144411Sscottl** 4750144411Sscottl** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the 4751144411Sscottl** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular 4752144411Sscottl** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may 4753144411Sscottl** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the 4754144411Sscottl** bits in this register are Read Only. For those bits, the interrupt must be cleared through another 4755144411Sscottl** register. 4756144411Sscottl** ---------------------------------------------------------------------- 4757144411Sscottl** Bit Default Description 4758144411Sscottl** 31:05 000000H 000 2 Reserved 4759144411Sscottl** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register. 4760144411Sscottl** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared. 4761144411Sscottl** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is 4762144411Sscottl** cleared when any prefetch data has been read from the Outbound Queue Port. 4763144411Sscottl** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound 4764165155Sscottl** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound 4765165155Sscottl** Doorbell Register must all be clear. 4766144411Sscottl** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is 4767144411Sscottl** written. Clearing this bit clears the interrupt. 4768144411Sscottl** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is 4769144411Sscottl** written. Clearing this bit clears the interrupt. 4770144411Sscottl************************************************************************** 4771144411Sscottl*/ 4772144411Sscottl#define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/ 4773144411Sscottl#define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 4774144411Sscottl#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 4775144411Sscottl#define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 4776144411Sscottl#define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 4777144411Sscottl#define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 4778144411Sscottl/* 4779144411Sscottl************************************************************************** 4780144411Sscottl** Outbound Interrupt Mask Register - OIMR 4781144411Sscottl** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI 4782144411Sscottl** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a 4783144411Sscottl** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI 4784144411Sscottl** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated. 4785144411Sscottl** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They 4786144411Sscottl** only affect the generation of the PCI interrupt. 4787144411Sscottl** ---------------------------------------------------------------------- 4788144411Sscottl** Bit Default Description 4789144411Sscottl** 31:05 000000H Reserved 4790144411Sscottl** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28) 4791144411Sscottl** in the Outbound Doorbell Register is set. 4792144411Sscottl** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in 4793144411Sscottl** the prefetch buffer is valid. 4794144411Sscottl** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound 4795144411Sscottl** Doorbell Register. 4796144411Sscottl** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt 4797144411Sscottl** generated by a write to the Outbound Message 1 Register. 4798144411Sscottl** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt 4799144411Sscottl** generated by a write to the Outbound Message 0 Register. 4800144411Sscottl************************************************************************** 4801144411Sscottl*/ 4802144411Sscottl#define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/ 4803144411Sscottl#define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 4804144411Sscottl#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 4805144411Sscottl#define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 4806144411Sscottl#define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 4807144411Sscottl#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 4808144411Sscottl#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 4809144411Sscottl/* 4810144411Sscottl************************************************************************** 4811144411Sscottl** 4812144411Sscottl************************************************************************** 4813144411Sscottl*/ 4814144411Sscottl#define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 4815144411Sscottl#define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 4816144411Sscottl/* 4817144411Sscottl************************************************************************** 4818144411Sscottl** Circular Queues 4819144411Sscottl** ====================================================================== 4820144411Sscottl** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In 4821144411Sscottl** this case, inbound and outbound refer to the direction of the flow of posted messages. 4822144411Sscottl** Inbound messages are either: 4823144411Sscottl** �E posted messages by other processors for the Intel XScale core to process or 4824144411Sscottl** �E free (or empty) messages that can be reused by other processors. 4825144411Sscottl** Outbound messages are either: 4826144411Sscottl** �E posted messages by the Intel XScale core for other processors to process or 4827144411Sscottl** �E free (or empty) messages that can be reused by the Intel XScale core. 4828144411Sscottl** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331. 4829144411Sscottl** The four Circular Queues are used to pass messages in the following manner. 4830144411Sscottl** . The two inbound queues are used to handle inbound messages 4831144411Sscottl** and the two outbound queues are used to handle outbound messages. 4832144411Sscottl** . One of the inbound queues is designated the Free queue and it contains inbound free messages. 4833144411Sscottl** The other inbound queue is designated the Post queue and it contains inbound posted messages. 4834144411Sscottl** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 4835165155Sscottl** 4836144411Sscottl** ============================================================================================================= 4837144411Sscottl** Circular Queue Summary 4838144411Sscottl** _____________________________________________________________________________________________________________ 4839144411Sscottl** | Queue Name | Purpose | Action on PCI Interface| 4840144411Sscottl** |______________________|____________________________________________________________|_________________________| 4841144411Sscottl** |Inbound Post Queue | Queue for inbound messages from other processors | Written | 4842144411Sscottl** | | waiting to be processed by the 80331 | | 4843144411Sscottl** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read | 4844144411Sscottl** | | available for use by other processors | | 4845144411Sscottl** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read | 4846144411Sscottl** | | that are being posted to the other processors | | 4847144411Sscottl** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written | 4848144411Sscottl** | | available for use by the 80331 | | 4849144411Sscottl** |______________________|____________________________________________________________|_________________________| 4850144411Sscottl** 4851144411Sscottl** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one 4852144411Sscottl** queue and to receive free messages returning from the 80331. 4853144411Sscottl** The host processor posts inbound messages, 4854144411Sscottl** the Intel XScale core receives the posted message and when it is finished with the message, 4855144411Sscottl** places it back on the inbound free queue for reuse by the host processor. 4856165155Sscottl** 4857144411Sscottl** The circular queues are accessed by external PCI agents through two port locations in the PCI 4858144411Sscottl** address space: 4859144411Sscottl** Inbound Queue Port 4860144411Sscottl** and Outbound Queue Port. 4861144411Sscottl** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 4862144411Sscottl** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue. 4863144411Sscottl** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 4864144411Sscottl** does not cause the MU hardware to increment the queue pointers. 4865144411Sscottl** This is treated as when the PCI transaction did not occur. 4866144411Sscottl** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface. 4867144411Sscottl** ====================================================================================== 4868144411Sscottl** Overview of Circular Queue Operation 4869144411Sscottl** ====================================================================================== 4870144411Sscottl** . The data storage for the circular queues must be provided by the 80331 local memory. 4871144411Sscottl** . The base address of the circular queues is contained in the Queue Base Address Register. 4872144411Sscottl** Each entry in the queue is a 32-bit data value. 4873144411Sscottl** . Each read from or write to the queue may access only one queue entry. 4874144411Sscottl** . Multi-DWORD accesses to the circular queues are not allowed. 4875144411Sscottl** Sub-DWORD accesses are promoted to DWORD accesses. 4876144411Sscottl** . Each circular queue has a head pointer and a tail pointer. 4877144411Sscottl** The pointers are offsets from the Queue Base Address. 4878144411Sscottl** . Writes to a queue occur at the head of the queue and reads occur from the tail. 4879144411Sscottl** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware. 4880144411Sscottl** Which unit maintains the pointer is determined by the writer of the queue. 4881144411Sscottl** More details about the pointers are given in the queue descriptions below. 4882144411Sscottl** The pointers are incremented after the queue access. 4883144411Sscottl** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size. 4884165155Sscottl** 4885144411Sscottl** Messaging Unit... 4886144411Sscottl** 4887144411Sscottl** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions. 4888144411Sscottl** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted. 4889144411Sscottl** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes). 4890144411Sscottl** . All four queues must be the same size and may be contiguous. 4891144411Sscottl** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 4892144411Sscottl** The Queue size is determined by the Queue Size field in the MU Configuration Register. 4893144411Sscottl** . There is one base address for all four queues. 4894144411Sscottl** It is stored in the Queue Base Address Register (QBAR). 4895144411Sscottl** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 4896144411Sscottl** here shows an example of how the circular queues should be set up based on the 4897144411Sscottl** Intelligent I/O (I 2 O) Architecture Specification. 4898144411Sscottl** Other ordering of the circular queues is possible. 4899165155Sscottl** 4900144411Sscottl** Queue Starting Address 4901144411Sscottl** Inbound Free Queue QBAR 4902144411Sscottl** Inbound Post Queue QBAR + Queue Size 4903144411Sscottl** Outbound Post Queue QBAR + 2 * Queue Size 4904144411Sscottl** Outbound Free Queue QBAR + 3 * Queue Size 4905144411Sscottl** =================================================================================== 4906144411Sscottl** Inbound Post Queue 4907144411Sscottl** ------------------ 4908144411Sscottl** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process. 4909144411Sscottl** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 4910144411Sscottl** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware. 4911165155Sscottl** For a PCI write transaction that accesses the Inbound Queue Port, 4912165155Sscottl** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register. 4913144411Sscottl** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register. 4914144411Sscottl** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 4915144411Sscottl** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status. 4916144411Sscottl** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 4917144411Sscottl** The interrupt can be masked by the Inbound Interrupt Mask Register. 4918165155Sscottl** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee 4919165155Sscottl** that the full condition is recognized by the core processor. 4920165155Sscottl** In addition, to guarantee that the queue does not get overwritten, 4921165155Sscottl** software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt. 4922144411Sscottl** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4923144411Sscottl** Only a new message posting the in the inbound queue generates a new interrupt. 4924165155Sscottl** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4925165155Sscottl** software must retain the information that the Inbound Post queue status. 4926165155Sscottl** From the time that the PCI write transaction is received until the data is written 4927165155Sscottl** in local memory and the Inbound Post Head Pointer Register is incremented, 4928165155Sscottl** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry. 4929165155Sscottl** The Intel XScale core may read messages from the Inbound Post Queue 4930165155Sscottl** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 4931144411Sscottl** The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 4932165155Sscottl** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), 4933165155Sscottl** the hardware retries any PCI writes until a slot in the queue becomes available. 4934144411Sscottl** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer. 4935144411Sscottl** =================================================================================== 4936144411Sscottl** Inbound Free Queue 4937144411Sscottl** ------------------ 4938144411Sscottl** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use. 4939144411Sscottl** This queue is read from the queue tail by external PCI agents. 4940144411Sscottl** It is written to the queue head by the Intel XScale core. 4941144411Sscottl** The tail pointer is maintained by the MU hardware. 4942144411Sscottl** The head pointer is maintained by the Intel XScale core. 4943144411Sscottl** For a PCI read transaction that accesses the Inbound Queue Port, 4944144411Sscottl** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 4945165155Sscottl** When the queue is not empty (head and tail pointers are not equal) 4946165155Sscottl** or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned. 4947165155Sscottl** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), 4948165155Sscottl** the value of -1 (FFFF.FFFFH) is returned. 4949144411Sscottl** When the queue was not empty and the MU succeeded in returning the data at the tail, 4950144411Sscottl** the MU hardware must increment the value in the Inbound Free Tail Pointer Register. 4951144411Sscottl** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 4952144411Sscottl** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 4953144411Sscottl** When the PCI read access occurs, the data is read directly from the prefetch register. 4954144411Sscottl** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 4955144411Sscottl** when the head and tail pointers are equal and the queue is empty. 4956144411Sscottl** In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 4957165155Sscottl** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH 4958165155Sscottl** and the Inbound Free Head Pointer Register is written. 4959144411Sscottl** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue. 4960144411Sscottl** A prefetch must appear atomic from the perspective of the external PCI agent. 4961144411Sscottl** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed. 4962144411Sscottl** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the 4963144411Sscottl** local memory location pointed to by the Inbound Free Head Pointer Register. 4964144411Sscottl** The processor must then increment the Inbound Free Head Pointer Register. 4965144411Sscottl** ================================================================================== 4966144411Sscottl** Outbound Post Queue 4967144411Sscottl** ------------------- 4968144411Sscottl** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 4969144411Sscottl** core for other processors to process. This queue is read from the queue tail by external PCI agents. 4970144411Sscottl** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the 4971144411Sscottl** MU hardware. The head pointer is maintained by the Intel XScale core. 4972144411Sscottl** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the 4973144411Sscottl** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not 4974144411Sscottl** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head 4975144411Sscottl** pointer was last written by software), the data is returned. When the queue is empty (head and tail 4976144411Sscottl** pointers are equal and the head pointer was last updated by hardware), the value of -1 4977144411Sscottl** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the 4978144411Sscottl** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer 4979144411Sscottl** Register. 4980144411Sscottl** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate 4981144411Sscottl** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the 4982144411Sscottl** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access 4983144411Sscottl** occurs, the data is read directly from the prefetch register. 4984144411Sscottl** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head 4985144411Sscottl** and tail pointers are equal and the queue is empty. In order to update the prefetch register when 4986144411Sscottl** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically 4987144411Sscottl** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head 4988144411Sscottl** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head 4989144411Sscottl** Pointer Register when it adds messages to the queue. 4990144411Sscottl** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is 4991144411Sscottl** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry 4992144411Sscottl** until the prefetch is completed. 4993144411Sscottl** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch 4994144411Sscottl** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound 4995144411Sscottl** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the 4996144411Sscottl** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound 4997144411Sscottl** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register. 4998144411Sscottl** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to 4999144411Sscottl** the local memory address in the Outbound Post Head Pointer Register. The processor must then 5000144411Sscottl** increment the Outbound Post Head Pointer Register. 5001144411Sscottl** ================================================== 5002144411Sscottl** Outbound Free Queue 5003144411Sscottl** ----------------------- 5004144411Sscottl** The Outbound Free Queue holds free messages placed there by other processors for the Intel 5005144411Sscottl** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is 5006144411Sscottl** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel 5007144411Sscottl** XScale core. The head pointer is maintained by the MU hardware. 5008144411Sscottl** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the 5009144411Sscottl** local memory address in the Outbound Free Head Pointer Register. When the data written to the 5010144411Sscottl** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free 5011144411Sscottl** Head Pointer Register. 5012144411Sscottl** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal 5013144411Sscottl** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is 5014144411Sscottl** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free 5015144411Sscottl** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can 5016144411Sscottl** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the 5017144411Sscottl** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the 5018144411Sscottl** core processor. 5019144411Sscottl** From the time that a PCI write transaction is received until the data is written in local memory and 5020144411Sscottl** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to 5021144411Sscottl** access the Outbound Free Queue Port is signalled a retry. 5022144411Sscottl** The Intel XScale core may read messages from the Outbound Free Queue by reading the data 5023144411Sscottl** from the local memory address in the Outbound Free Tail Pointer Register. The processor must 5024144411Sscottl** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full, 5025144411Sscottl** the hardware must retry any PCI writes until a slot in the queue becomes available. 5026165155Sscottl** 5027144411Sscottl** ================================================================================== 5028144411Sscottl** Circular Queue Summary 5029144411Sscottl** ---------------------- 5030144411Sscottl** ________________________________________________________________________________________________________________________________________________ 5031144411Sscottl** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by| 5032144411Sscottl** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5033144411Sscottl** |Inbound Post | Inbound Queue | | | | | 5034144411Sscottl** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale | 5035144411Sscottl** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5036144411Sscottl** |Inbound Free | Inbound Queue | | | | | 5037144411Sscottl** | Queue | Port | NO | NO | Intel XScale | MU hardware | 5038144411Sscottl** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5039144411Sscottl** ================================================================================== 5040144411Sscottl** Circular Queue Status Summary 5041144411Sscottl** ---------------------- 5042144411Sscottl** ____________________________________________________________________________________________________ 5043144411Sscottl** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update | 5044144411Sscottl** |_____________________|________________|_____________________|_______________________________________| 5045144411Sscottl** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software | 5046144411Sscottl** |_____________________|________________|_____________________|_______________________________________| 5047144411Sscottl** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware | 5048144411Sscottl** |_____________________|________________|_____________________|_______________________________________| 5049144411Sscottl************************************************************************** 5050144411Sscottl*/ 5051144411Sscottl 5052144411Sscottl/* 5053144411Sscottl************************************************************************** 5054144411Sscottl** Index Registers 5055144411Sscottl** ======================== 5056144411Sscottl** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 5057144411Sscottl** These registers are for inbound messages only. 5058144411Sscottl** The interrupt is recorded in the Inbound Interrupt Status Register. 5059144411Sscottl** The storage for the Index Registers is allocated from the 80331 local memory. 5060144411Sscottl** PCI write accesses to the Index Registers write the data to local memory. 5061144411Sscottl** PCI read accesses to the Index Registers read the data from local memory. 5062144411Sscottl** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 5063144411Sscottl** to Inbound ATU Translate Value Register + FFFH. 5064144411Sscottl** . The address of the first write access is stored in the Index Address Register. 5065144411Sscottl** This register is written during the earliest write access and provides a means to determine which Index Register was written. 5066165155Sscottl** Once updated by the MU, the Index Address Register is not updated until the Index Register 5067165155Sscottl** Interrupt bit in the Inbound Interrupt Status Register is cleared. 5068144411Sscottl** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access. 5069165155Sscottl** Writes by the Intel XScale core to the local memory used by the Index Registers 5070165155Sscottl** does not cause an interrupt and does not update the Index Address Register. 5071144411Sscottl** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes. 5072144411Sscottl************************************************************************** 5073144411Sscottl*/ 5074144411Sscottl/* 5075144411Sscottl************************************************************************** 5076144411Sscottl** Messaging Unit Internal Bus Memory Map 5077144411Sscottl** ======================================= 5078144411Sscottl** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_ 5079144411Sscottl** FFFF E300H reserved | 5080144411Sscottl** .. .. | 5081165155Sscottl** FFFF E30CH reserved | 5082144411Sscottl** FFFF E310H Inbound Message Register 0 | Available through 5083144411Sscottl** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window 5084165155Sscottl** FFFF E318H Outbound Message Register 0 | 5085165155Sscottl** FFFF E31CH Outbound Message Register 1 | or 5086165155Sscottl** FFFF E320H Inbound Doorbell Register | 5087165155Sscottl** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to 5088144411Sscottl** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core 5089144411Sscottl** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address 5090144411Sscottl** FFFF E330H Outbound Interrupt Status Register | 5091144411Sscottl** FFFF E334H Outbound Interrupt Mask Register | 5092144411Sscottl** ______________________________________________________________________|________________________________________ 5093144411Sscottl** FFFF E338H reserved | 5094144411Sscottl** FFFF E33CH reserved | 5095144411Sscottl** FFFF E340H reserved | 5096144411Sscottl** FFFF E344H reserved | 5097144411Sscottl** FFFF E348H reserved | 5098144411Sscottl** FFFF E34CH reserved | 5099144411Sscottl** FFFF E350H MU Configuration Register | 5100144411Sscottl** FFFF E354H Queue Base Address Register | 5101144411Sscottl** FFFF E358H reserved | 5102165155Sscottl** FFFF E35CH reserved | must translate PCI address to 5103165155Sscottl** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core 5104144411Sscottl** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address 5105144411Sscottl** FFFF E368H Inbound Post Head pointer Register | 5106144411Sscottl** FFFF E36CH Inbound Post Tail Pointer Register | 5107165155Sscottl** FFFF E370H Outbound Free Head Pointer Register | 5108144411Sscottl** FFFF E374H Outbound Free Tail Pointer Register | 5109144411Sscottl** FFFF E378H Outbound Post Head pointer Register | 5110144411Sscottl** FFFF E37CH Outbound Post Tail Pointer Register | 5111144411Sscottl** FFFF E380H Index Address Register | 5112144411Sscottl** FFFF E384H reserved | 5113144411Sscottl** .. .. | 5114144411Sscottl** FFFF E3FCH reserved | 5115144411Sscottl** ______________________________________________________________________|_______________________________________ 5116144411Sscottl************************************************************************** 5117144411Sscottl*/ 5118144411Sscottl/* 5119144411Sscottl************************************************************************** 5120144411Sscottl** MU Configuration Register - MUCR FFFF.E350H 5121144411Sscottl** 5122144411Sscottl** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue. 5123144411Sscottl** . The Circular Queue Enable bit enables or disables the Circular Queues. 5124165155Sscottl** The Circular Queues are disabled at reset to allow the software to initialize the head 5125165155Sscottl** and tail pointer registers before any PCI accesses to the Queue Ports. 5126144411Sscottl** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues. 5127144411Sscottl** ------------------------------------------------------------------------ 5128144411Sscottl** Bit Default Description 5129144411Sscottl** 31:06 000000H 00 2 Reserved 5130144411Sscottl** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue. 5131165155Sscottl** All four queues are the same size. 5132165155Sscottl** �E 00001 2 - 4K Entries (16 Kbytes) 5133165155Sscottl** �E 00010 2 - 8K Entries (32 Kbytes) 5134165155Sscottl** �E 00100 2 - 16K Entries (64 Kbytes) 5135165155Sscottl** �E 01000 2 - 32K Entries (128 Kbytes) 5136165155Sscottl** �E 10000 2 - 64K Entries (256 Kbytes) 5137165155Sscottl** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular 5138165155Sscottl** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores 5139165155Sscottl** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when 5140165155Sscottl** disabled. When set, the Circular Queues are fully enabled. 5141144411Sscottl************************************************************************** 5142144411Sscottl*/ 5143144411Sscottl#define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 5144144411Sscottl#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 5145144411Sscottl#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 5146144411Sscottl#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 5147144411Sscottl#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 5148144411Sscottl#define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 5149144411Sscottl#define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/ 5150144411Sscottl/* 5151144411Sscottl************************************************************************** 5152144411Sscottl** Queue Base Address Register - QBAR 5153144411Sscottl** 5154144411Sscottl** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues. 5155144411Sscottl** The base address is required to be located on a 1 Mbyte address boundary. 5156144411Sscottl** . All Circular Queue head and tail pointers are based on the QBAR. 5157144411Sscottl** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 5158144411Sscottl** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register. 5159144411Sscottl** Warning: 5160144411Sscottl** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 5161144411Sscottl** ------------------------------------------------------------------------ 5162144411Sscottl** Bit Default Description 5163144411Sscottl** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5164144411Sscottl** 19:00 00000H Reserved 5165144411Sscottl************************************************************************** 5166144411Sscottl*/ 5167144411Sscottl#define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 5168144411Sscottl/* 5169144411Sscottl************************************************************************** 5170144411Sscottl** Inbound Free Head Pointer Register - IFHPR 5171144411Sscottl** 5172165155Sscottl** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from 5173165155Sscottl** the Queue Base Address of the head pointer for the Inbound Free Queue. 5174144411Sscottl** The Head Pointer must be aligned on a DWORD address boundary. 5175144411Sscottl** When read, the Queue Base Address is provided in the upper 12 bits of the register. 5176144411Sscottl** Writes to the upper 12 bits of the register are ignored. 5177144411Sscottl** This register is maintained by software. 5178144411Sscottl** ------------------------------------------------------------------------ 5179144411Sscottl** Bit Default Description 5180144411Sscottl** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5181144411Sscottl** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue. 5182144411Sscottl** 01:00 00 2 Reserved 5183144411Sscottl************************************************************************** 5184144411Sscottl*/ 5185144411Sscottl#define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 5186144411Sscottl/* 5187144411Sscottl************************************************************************** 5188144411Sscottl** Inbound Free Tail Pointer Register - IFTPR 5189144411Sscottl** 5190144411Sscottl** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue 5191144411Sscottl** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a 5192144411Sscottl** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5193144411Sscottl** of the register. Writes to the upper 12 bits of the register are ignored. 5194144411Sscottl** ------------------------------------------------------------------------ 5195144411Sscottl** Bit Default Description 5196144411Sscottl** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5197144411Sscottl** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue. 5198144411Sscottl** 01:00 00 2 Reserved 5199144411Sscottl************************************************************************** 5200144411Sscottl*/ 5201144411Sscottl#define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 5202144411Sscottl/* 5203144411Sscottl************************************************************************** 5204144411Sscottl** Inbound Post Head Pointer Register - IPHPR 5205144411Sscottl** 5206144411Sscottl** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue 5207144411Sscottl** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on 5208144411Sscottl** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5209144411Sscottl** of the register. Writes to the upper 12 bits of the register are ignored. 5210144411Sscottl** ------------------------------------------------------------------------ 5211144411Sscottl** Bit Default Description 5212144411Sscottl** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5213144411Sscottl** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue. 5214144411Sscottl** 01:00 00 2 Reserved 5215144411Sscottl************************************************************************** 5216144411Sscottl*/ 5217144411Sscottl#define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 5218144411Sscottl/* 5219144411Sscottl************************************************************************** 5220144411Sscottl** Inbound Post Tail Pointer Register - IPTPR 5221144411Sscottl** 5222144411Sscottl** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue 5223144411Sscottl** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a 5224144411Sscottl** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5225144411Sscottl** of the register. Writes to the upper 12 bits of the register are ignored. 5226144411Sscottl** ------------------------------------------------------------------------ 5227144411Sscottl** Bit Default Description 5228144411Sscottl** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5229144411Sscottl** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue. 5230144411Sscottl** 01:00 00 2 Reserved 5231144411Sscottl************************************************************************** 5232144411Sscottl*/ 5233144411Sscottl#define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 5234144411Sscottl/* 5235144411Sscottl************************************************************************** 5236144411Sscottl** Index Address Register - IAR 5237144411Sscottl** 5238144411Sscottl** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register. 5239144411Sscottl** It is written by the MU when the Index Registers are written by a PCI agent. 5240144411Sscottl** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared. 5241165155Sscottl** . The local memory address of the Index Register least recently accessed is computed 5242165155Sscottl** by adding the Index Address Register to the Inbound ATU Translate Value Register. 5243144411Sscottl** ------------------------------------------------------------------------ 5244144411Sscottl** Bit Default Description 5245144411Sscottl** 31:12 000000H Reserved 5246144411Sscottl** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH) 5247144411Sscottl** 01:00 00 2 Reserved 5248144411Sscottl************************************************************************** 5249144411Sscottl*/ 5250144411Sscottl#define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/ 5251144411Sscottl/* 5252144411Sscottl********************************************************************************************************** 5253144411Sscottl** RS-232 Interface for Areca Raid Controller 5254144411Sscottl** The low level command interface is exclusive with VT100 terminal 5255144411Sscottl** -------------------------------------------------------------------- 5256144411Sscottl** 1. Sequence of command execution 5257144411Sscottl** -------------------------------------------------------------------- 5258144411Sscottl** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5259144411Sscottl** (B) Command block : variable length of data including length, command code, data and checksum byte 5260144411Sscottl** (C) Return data : variable length of data 5261144411Sscottl** -------------------------------------------------------------------- 5262144411Sscottl** 2. Command block 5263144411Sscottl** -------------------------------------------------------------------- 5264144411Sscottl** (A) 1st byte : command block length (low byte) 5265144411Sscottl** (B) 2nd byte : command block length (high byte) 5266144411Sscottl** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes 5267144411Sscottl** (C) 3rd byte : command code 5268144411Sscottl** (D) 4th and following bytes : variable length data bytes depends on command code 5269144411Sscottl** (E) last byte : checksum byte (sum of 1st byte until last data byte) 5270144411Sscottl** -------------------------------------------------------------------- 5271144411Sscottl** 3. Command code and associated data 5272144411Sscottl** -------------------------------------------------------------------- 5273165155Sscottl** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management, 5274165155Sscottl** no password checking is needed and should be implemented in separate well controlled utility and not for end user access. 5275144411Sscottl** Command code 0x20--0x?? always check the password, password must be entered to enable these command. 5276144411Sscottl** enum 5277144411Sscottl** { 5278144411Sscottl** GUI_SET_SERIAL=0x10, 5279144411Sscottl** GUI_SET_VENDOR, 5280144411Sscottl** GUI_SET_MODEL, 5281144411Sscottl** GUI_IDENTIFY, 5282144411Sscottl** GUI_CHECK_PASSWORD, 5283144411Sscottl** GUI_LOGOUT, 5284144411Sscottl** GUI_HTTP, 5285144411Sscottl** GUI_SET_ETHERNET_ADDR, 5286144411Sscottl** GUI_SET_LOGO, 5287144411Sscottl** GUI_POLL_EVENT, 5288144411Sscottl** GUI_GET_EVENT, 5289144411Sscottl** GUI_GET_HW_MONITOR, 5290165155Sscottl** 5291144411Sscottl** // GUI_QUICK_CREATE=0x20, (function removed) 5292144411Sscottl** GUI_GET_INFO_R=0x20, 5293144411Sscottl** GUI_GET_INFO_V, 5294144411Sscottl** GUI_GET_INFO_P, 5295144411Sscottl** GUI_GET_INFO_S, 5296144411Sscottl** GUI_CLEAR_EVENT, 5297165155Sscottl** 5298144411Sscottl** GUI_MUTE_BEEPER=0x30, 5299144411Sscottl** GUI_BEEPER_SETTING, 5300144411Sscottl** GUI_SET_PASSWORD, 5301144411Sscottl** GUI_HOST_INTERFACE_MODE, 5302144411Sscottl** GUI_REBUILD_PRIORITY, 5303144411Sscottl** GUI_MAX_ATA_MODE, 5304144411Sscottl** GUI_RESET_CONTROLLER, 5305144411Sscottl** GUI_COM_PORT_SETTING, 5306144411Sscottl** GUI_NO_OPERATION, 5307144411Sscottl** GUI_DHCP_IP, 5308165155Sscottl** 5309144411Sscottl** GUI_CREATE_PASS_THROUGH=0x40, 5310144411Sscottl** GUI_MODIFY_PASS_THROUGH, 5311144411Sscottl** GUI_DELETE_PASS_THROUGH, 5312144411Sscottl** GUI_IDENTIFY_DEVICE, 5313165155Sscottl** 5314144411Sscottl** GUI_CREATE_RAIDSET=0x50, 5315144411Sscottl** GUI_DELETE_RAIDSET, 5316144411Sscottl** GUI_EXPAND_RAIDSET, 5317144411Sscottl** GUI_ACTIVATE_RAIDSET, 5318144411Sscottl** GUI_CREATE_HOT_SPARE, 5319144411Sscottl** GUI_DELETE_HOT_SPARE, 5320165155Sscottl** 5321144411Sscottl** GUI_CREATE_VOLUME=0x60, 5322144411Sscottl** GUI_MODIFY_VOLUME, 5323144411Sscottl** GUI_DELETE_VOLUME, 5324144411Sscottl** GUI_START_CHECK_VOLUME, 5325144411Sscottl** GUI_STOP_CHECK_VOLUME 5326144411Sscottl** }; 5327165155Sscottl** 5328144411Sscottl** Command description : 5329165155Sscottl** 5330144411Sscottl** GUI_SET_SERIAL : Set the controller serial# 5331144411Sscottl** byte 0,1 : length 5332144411Sscottl** byte 2 : command code 0x10 5333144411Sscottl** byte 3 : password length (should be 0x0f) 5334144411Sscottl** byte 4-0x13 : should be "ArEcATecHnoLogY" 5335144411Sscottl** byte 0x14--0x23 : Serial number string (must be 16 bytes) 5336144411Sscottl** GUI_SET_VENDOR : Set vendor string for the controller 5337144411Sscottl** byte 0,1 : length 5338144411Sscottl** byte 2 : command code 0x11 5339144411Sscottl** byte 3 : password length (should be 0x08) 5340144411Sscottl** byte 4-0x13 : should be "ArEcAvAr" 5341144411Sscottl** byte 0x14--0x3B : vendor string (must be 40 bytes) 5342144411Sscottl** GUI_SET_MODEL : Set the model name of the controller 5343144411Sscottl** byte 0,1 : length 5344144411Sscottl** byte 2 : command code 0x12 5345144411Sscottl** byte 3 : password length (should be 0x08) 5346144411Sscottl** byte 4-0x13 : should be "ArEcAvAr" 5347144411Sscottl** byte 0x14--0x1B : model string (must be 8 bytes) 5348144411Sscottl** GUI_IDENTIFY : Identify device 5349144411Sscottl** byte 0,1 : length 5350144411Sscottl** byte 2 : command code 0x13 5351144411Sscottl** return "Areca RAID Subsystem " 5352144411Sscottl** GUI_CHECK_PASSWORD : Verify password 5353144411Sscottl** byte 0,1 : length 5354144411Sscottl** byte 2 : command code 0x14 5355144411Sscottl** byte 3 : password length 5356144411Sscottl** byte 4-0x?? : user password to be checked 5357144411Sscottl** GUI_LOGOUT : Logout GUI (force password checking on next command) 5358144411Sscottl** byte 0,1 : length 5359144411Sscottl** byte 2 : command code 0x15 5360144411Sscottl** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16) 5361144411Sscottl** 5362144411Sscottl** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address 5363144411Sscottl** byte 0,1 : length 5364144411Sscottl** byte 2 : command code 0x17 5365144411Sscottl** byte 3 : password length (should be 0x08) 5366144411Sscottl** byte 4-0x13 : should be "ArEcAvAr" 5367144411Sscottl** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes) 5368144411Sscottl** GUI_SET_LOGO : Set logo in HTTP 5369144411Sscottl** byte 0,1 : length 5370144411Sscottl** byte 2 : command code 0x18 5371144411Sscottl** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo) 5372144411Sscottl** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a 5373144411Sscottl** byte 8 : TITLE.JPG data (each page must be 2000 bytes) 5374144411Sscottl** note .... page0 1st 2 byte must be actual length of the JPG file 5375144411Sscottl** GUI_POLL_EVENT : Poll If Event Log Changed 5376144411Sscottl** byte 0,1 : length 5377144411Sscottl** byte 2 : command code 0x19 5378144411Sscottl** GUI_GET_EVENT : Read Event 5379144411Sscottl** byte 0,1 : length 5380144411Sscottl** byte 2 : command code 0x1a 5381144411Sscottl** byte 3 : Event Page (0:1st page/1/2/3:last page) 5382144411Sscottl** GUI_GET_HW_MONITOR : Get HW monitor data 5383144411Sscottl** byte 0,1 : length 5384144411Sscottl** byte 2 : command code 0x1b 5385144411Sscottl** byte 3 : # of FANs(example 2) 5386144411Sscottl** byte 4 : # of Voltage sensor(example 3) 5387144411Sscottl** byte 5 : # of temperature sensor(example 2) 5388144411Sscottl** byte 6 : # of power 5389144411Sscottl** byte 7/8 : Fan#0 (RPM) 5390144411Sscottl** byte 9/10 : Fan#1 5391144411Sscottl** byte 11/12 : Voltage#0 original value in *1000 5392144411Sscottl** byte 13/14 : Voltage#0 value 5393144411Sscottl** byte 15/16 : Voltage#1 org 5394144411Sscottl** byte 17/18 : Voltage#1 5395144411Sscottl** byte 19/20 : Voltage#2 org 5396144411Sscottl** byte 21/22 : Voltage#2 5397144411Sscottl** byte 23 : Temp#0 5398144411Sscottl** byte 24 : Temp#1 5399144411Sscottl** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1) 5400144411Sscottl** byte 26 : UPS indicator 5401144411Sscottl** GUI_QUICK_CREATE : Quick create raid/volume set 5402144411Sscottl** byte 0,1 : length 5403144411Sscottl** byte 2 : command code 0x20 5404144411Sscottl** byte 3/4/5/6 : raw capacity 5405144411Sscottl** byte 7 : raid level 5406144411Sscottl** byte 8 : stripe size 5407144411Sscottl** byte 9 : spare 5408144411Sscottl** byte 10/11/12/13: device mask (the devices to create raid/volume) 5409144411Sscottl** This function is removed, application like to implement quick create function 5410144411Sscottl** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function. 5411144411Sscottl** GUI_GET_INFO_R : Get Raid Set Information 5412144411Sscottl** byte 0,1 : length 5413144411Sscottl** byte 2 : command code 0x20 5414144411Sscottl** byte 3 : raidset# 5415165155Sscottl** 5416144411Sscottl** typedef struct sGUI_RAIDSET 5417144411Sscottl** { 5418144411Sscottl** BYTE grsRaidSetName[16]; 5419144411Sscottl** DWORD grsCapacity; 5420144411Sscottl** DWORD grsCapacityX; 5421144411Sscottl** DWORD grsFailMask; 5422144411Sscottl** BYTE grsDevArray[32]; 5423144411Sscottl** BYTE grsMemberDevices; 5424144411Sscottl** BYTE grsNewMemberDevices; 5425144411Sscottl** BYTE grsRaidState; 5426144411Sscottl** BYTE grsVolumes; 5427144411Sscottl** BYTE grsVolumeList[16]; 5428144411Sscottl** BYTE grsRes1; 5429144411Sscottl** BYTE grsRes2; 5430144411Sscottl** BYTE grsRes3; 5431144411Sscottl** BYTE grsFreeSegments; 5432144411Sscottl** DWORD grsRawStripes[8]; 5433144411Sscottl** DWORD grsRes4; 5434144411Sscottl** DWORD grsRes5; // Total to 128 bytes 5435144411Sscottl** DWORD grsRes6; // Total to 128 bytes 5436144411Sscottl** } sGUI_RAIDSET, *pGUI_RAIDSET; 5437144411Sscottl** GUI_GET_INFO_V : Get Volume Set Information 5438144411Sscottl** byte 0,1 : length 5439144411Sscottl** byte 2 : command code 0x21 5440144411Sscottl** byte 3 : volumeset# 5441165155Sscottl** 5442144411Sscottl** typedef struct sGUI_VOLUMESET 5443144411Sscottl** { 5444144411Sscottl** BYTE gvsVolumeName[16]; // 16 5445144411Sscottl** DWORD gvsCapacity; 5446144411Sscottl** DWORD gvsCapacityX; 5447144411Sscottl** DWORD gvsFailMask; 5448144411Sscottl** DWORD gvsStripeSize; 5449144411Sscottl** DWORD gvsNewFailMask; 5450144411Sscottl** DWORD gvsNewStripeSize; 5451144411Sscottl** DWORD gvsVolumeStatus; 5452144411Sscottl** DWORD gvsProgress; // 32 5453144411Sscottl** sSCSI_ATTR gvsScsi; 5454144411Sscottl** BYTE gvsMemberDisks; 5455144411Sscottl** BYTE gvsRaidLevel; // 8 5456165155Sscottl** 5457144411Sscottl** BYTE gvsNewMemberDisks; 5458144411Sscottl** BYTE gvsNewRaidLevel; 5459144411Sscottl** BYTE gvsRaidSetNumber; 5460144411Sscottl** BYTE gvsRes0; // 4 5461144411Sscottl** BYTE gvsRes1[4]; // 64 bytes 5462144411Sscottl** } sGUI_VOLUMESET, *pGUI_VOLUMESET; 5463165155Sscottl** 5464144411Sscottl** GUI_GET_INFO_P : Get Physical Drive Information 5465144411Sscottl** byte 0,1 : length 5466144411Sscottl** byte 2 : command code 0x22 5467144411Sscottl** byte 3 : drive # (from 0 to max-channels - 1) 5468165155Sscottl** 5469144411Sscottl** typedef struct sGUI_PHY_DRV 5470144411Sscottl** { 5471144411Sscottl** BYTE gpdModelName[40]; 5472144411Sscottl** BYTE gpdSerialNumber[20]; 5473144411Sscottl** BYTE gpdFirmRev[8]; 5474144411Sscottl** DWORD gpdCapacity; 5475144411Sscottl** DWORD gpdCapacityX; // Reserved for expansion 5476144411Sscottl** BYTE gpdDeviceState; 5477144411Sscottl** BYTE gpdPioMode; 5478144411Sscottl** BYTE gpdCurrentUdmaMode; 5479144411Sscottl** BYTE gpdUdmaMode; 5480144411Sscottl** BYTE gpdDriveSelect; 5481144411Sscottl** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set 5482144411Sscottl** sSCSI_ATTR gpdScsi; 5483144411Sscottl** BYTE gpdReserved[40]; // Total to 128 bytes 5484144411Sscottl** } sGUI_PHY_DRV, *pGUI_PHY_DRV; 5485165155Sscottl** 5486144411Sscottl** GUI_GET_INFO_S : Get System Information 5487144411Sscottl** byte 0,1 : length 5488144411Sscottl** byte 2 : command code 0x23 5489165155Sscottl** 5490144411Sscottl** typedef struct sCOM_ATTR 5491144411Sscottl** { 5492144411Sscottl** BYTE comBaudRate; 5493144411Sscottl** BYTE comDataBits; 5494144411Sscottl** BYTE comStopBits; 5495144411Sscottl** BYTE comParity; 5496144411Sscottl** BYTE comFlowControl; 5497144411Sscottl** } sCOM_ATTR, *pCOM_ATTR; 5498165155Sscottl** 5499144411Sscottl** typedef struct sSYSTEM_INFO 5500144411Sscottl** { 5501144411Sscottl** BYTE gsiVendorName[40]; 5502144411Sscottl** BYTE gsiSerialNumber[16]; 5503144411Sscottl** BYTE gsiFirmVersion[16]; 5504144411Sscottl** BYTE gsiBootVersion[16]; 5505144411Sscottl** BYTE gsiMbVersion[16]; 5506144411Sscottl** BYTE gsiModelName[8]; 5507144411Sscottl** BYTE gsiLocalIp[4]; 5508144411Sscottl** BYTE gsiCurrentIp[4]; 5509144411Sscottl** DWORD gsiTimeTick; 5510144411Sscottl** DWORD gsiCpuSpeed; 5511144411Sscottl** DWORD gsiICache; 5512144411Sscottl** DWORD gsiDCache; 5513144411Sscottl** DWORD gsiScache; 5514144411Sscottl** DWORD gsiMemorySize; 5515144411Sscottl** DWORD gsiMemorySpeed; 5516144411Sscottl** DWORD gsiEvents; 5517144411Sscottl** BYTE gsiMacAddress[6]; 5518144411Sscottl** BYTE gsiDhcp; 5519144411Sscottl** BYTE gsiBeeper; 5520144411Sscottl** BYTE gsiChannelUsage; 5521144411Sscottl** BYTE gsiMaxAtaMode; 5522144411Sscottl** BYTE gsiSdramEcc; // 1:if ECC enabled 5523144411Sscottl** BYTE gsiRebuildPriority; 5524144411Sscottl** sCOM_ATTR gsiComA; // 5 bytes 5525144411Sscottl** sCOM_ATTR gsiComB; // 5 bytes 5526144411Sscottl** BYTE gsiIdeChannels; 5527144411Sscottl** BYTE gsiScsiHostChannels; 5528144411Sscottl** BYTE gsiIdeHostChannels; 5529144411Sscottl** BYTE gsiMaxVolumeSet; 5530144411Sscottl** BYTE gsiMaxRaidSet; 5531144411Sscottl** BYTE gsiEtherPort; // 1:if ether net port supported 5532144411Sscottl** BYTE gsiRaid6Engine; // 1:Raid6 engine supported 5533144411Sscottl** BYTE gsiRes[75]; 5534144411Sscottl** } sSYSTEM_INFO, *pSYSTEM_INFO; 5535165155Sscottl** 5536144411Sscottl** GUI_CLEAR_EVENT : Clear System Event 5537144411Sscottl** byte 0,1 : length 5538144411Sscottl** byte 2 : command code 0x24 5539165155Sscottl** 5540144411Sscottl** GUI_MUTE_BEEPER : Mute current beeper 5541144411Sscottl** byte 0,1 : length 5542144411Sscottl** byte 2 : command code 0x30 5543165155Sscottl** 5544144411Sscottl** GUI_BEEPER_SETTING : Disable beeper 5545144411Sscottl** byte 0,1 : length 5546144411Sscottl** byte 2 : command code 0x31 5547144411Sscottl** byte 3 : 0->disable, 1->enable 5548165155Sscottl** 5549144411Sscottl** GUI_SET_PASSWORD : Change password 5550144411Sscottl** byte 0,1 : length 5551144411Sscottl** byte 2 : command code 0x32 5552144411Sscottl** byte 3 : pass word length ( must <= 15 ) 5553144411Sscottl** byte 4 : password (must be alpha-numerical) 5554165155Sscottl** 5555144411Sscottl** GUI_HOST_INTERFACE_MODE : Set host interface mode 5556144411Sscottl** byte 0,1 : length 5557144411Sscottl** byte 2 : command code 0x33 5558144411Sscottl** byte 3 : 0->Independent, 1->cluster 5559165155Sscottl** 5560144411Sscottl** GUI_REBUILD_PRIORITY : Set rebuild priority 5561144411Sscottl** byte 0,1 : length 5562144411Sscottl** byte 2 : command code 0x34 5563144411Sscottl** byte 3 : 0/1/2/3 (low->high) 5564165155Sscottl** 5565144411Sscottl** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used 5566144411Sscottl** byte 0,1 : length 5567144411Sscottl** byte 2 : command code 0x35 5568144411Sscottl** byte 3 : 0/1/2/3 (133/100/66/33) 5569165155Sscottl** 5570144411Sscottl** GUI_RESET_CONTROLLER : Reset Controller 5571144411Sscottl** byte 0,1 : length 5572144411Sscottl** byte 2 : command code 0x36 5573144411Sscottl** *Response with VT100 screen (discard it) 5574165155Sscottl** 5575144411Sscottl** GUI_COM_PORT_SETTING : COM port setting 5576144411Sscottl** byte 0,1 : length 5577144411Sscottl** byte 2 : command code 0x37 5578144411Sscottl** byte 3 : 0->COMA (term port), 1->COMB (debug port) 5579144411Sscottl** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200) 5580144411Sscottl** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit) 5581144411Sscottl** byte 6 : stop bit (0:1, 1:2 stop bits) 5582144411Sscottl** byte 7 : parity (0:none, 1:off, 2:even) 5583144411Sscottl** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none) 5584165155Sscottl** 5585144411Sscottl** GUI_NO_OPERATION : No operation 5586144411Sscottl** byte 0,1 : length 5587144411Sscottl** byte 2 : command code 0x38 5588165155Sscottl** 5589144411Sscottl** GUI_DHCP_IP : Set DHCP option and local IP address 5590144411Sscottl** byte 0,1 : length 5591144411Sscottl** byte 2 : command code 0x39 5592144411Sscottl** byte 3 : 0:dhcp disabled, 1:dhcp enabled 5593144411Sscottl** byte 4/5/6/7 : IP address 5594165155Sscottl** 5595144411Sscottl** GUI_CREATE_PASS_THROUGH : Create pass through disk 5596144411Sscottl** byte 0,1 : length 5597144411Sscottl** byte 2 : command code 0x40 5598144411Sscottl** byte 3 : device # 5599144411Sscottl** byte 4 : scsi channel (0/1) 5600144411Sscottl** byte 5 : scsi id (0-->15) 5601144411Sscottl** byte 6 : scsi lun (0-->7) 5602144411Sscottl** byte 7 : tagged queue (1 : enabled) 5603144411Sscottl** byte 8 : cache mode (1 : enabled) 5604144411Sscottl** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5605144411Sscottl** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5606165155Sscottl** 5607144411Sscottl** GUI_MODIFY_PASS_THROUGH : Modify pass through disk 5608144411Sscottl** byte 0,1 : length 5609144411Sscottl** byte 2 : command code 0x41 5610144411Sscottl** byte 3 : device # 5611144411Sscottl** byte 4 : scsi channel (0/1) 5612144411Sscottl** byte 5 : scsi id (0-->15) 5613144411Sscottl** byte 6 : scsi lun (0-->7) 5614144411Sscottl** byte 7 : tagged queue (1 : enabled) 5615144411Sscottl** byte 8 : cache mode (1 : enabled) 5616144411Sscottl** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5617144411Sscottl** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5618165155Sscottl** 5619144411Sscottl** GUI_DELETE_PASS_THROUGH : Delete pass through disk 5620144411Sscottl** byte 0,1 : length 5621144411Sscottl** byte 2 : command code 0x42 5622144411Sscottl** byte 3 : device# to be deleted 5623165155Sscottl** 5624144411Sscottl** GUI_IDENTIFY_DEVICE : Identify Device 5625144411Sscottl** byte 0,1 : length 5626144411Sscottl** byte 2 : command code 0x43 5627144411Sscottl** byte 3 : Flash Method(0:flash selected, 1:flash not selected) 5628144411Sscottl** byte 4/5/6/7 : IDE device mask to be flashed 5629144411Sscottl** note .... no response data available 5630165155Sscottl** 5631144411Sscottl** GUI_CREATE_RAIDSET : Create Raid Set 5632144411Sscottl** byte 0,1 : length 5633144411Sscottl** byte 2 : command code 0x50 5634144411Sscottl** byte 3/4/5/6 : device mask 5635144411Sscottl** byte 7-22 : raidset name (if byte 7 == 0:use default) 5636165155Sscottl** 5637144411Sscottl** GUI_DELETE_RAIDSET : Delete Raid Set 5638144411Sscottl** byte 0,1 : length 5639144411Sscottl** byte 2 : command code 0x51 5640144411Sscottl** byte 3 : raidset# 5641165155Sscottl** 5642144411Sscottl** GUI_EXPAND_RAIDSET : Expand Raid Set 5643144411Sscottl** byte 0,1 : length 5644144411Sscottl** byte 2 : command code 0x52 5645144411Sscottl** byte 3 : raidset# 5646144411Sscottl** byte 4/5/6/7 : device mask for expansion 5647144411Sscottl** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K ) 5648144411Sscottl** byte 11/12/13 : repeat for each volume in the raidset .... 5649165155Sscottl** 5650144411Sscottl** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set 5651144411Sscottl** byte 0,1 : length 5652144411Sscottl** byte 2 : command code 0x53 5653144411Sscottl** byte 3 : raidset# 5654165155Sscottl** 5655144411Sscottl** GUI_CREATE_HOT_SPARE : Create hot spare disk 5656144411Sscottl** byte 0,1 : length 5657144411Sscottl** byte 2 : command code 0x54 5658144411Sscottl** byte 3/4/5/6 : device mask for hot spare creation 5659165155Sscottl** 5660144411Sscottl** GUI_DELETE_HOT_SPARE : Delete hot spare disk 5661144411Sscottl** byte 0,1 : length 5662144411Sscottl** byte 2 : command code 0x55 5663144411Sscottl** byte 3/4/5/6 : device mask for hot spare deletion 5664165155Sscottl** 5665144411Sscottl** GUI_CREATE_VOLUME : Create volume set 5666144411Sscottl** byte 0,1 : length 5667144411Sscottl** byte 2 : command code 0x60 5668144411Sscottl** byte 3 : raidset# 5669144411Sscottl** byte 4-19 : volume set name (if byte4 == 0, use default) 5670144411Sscottl** byte 20-27 : volume capacity (blocks) 5671144411Sscottl** byte 28 : raid level 5672144411Sscottl** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5673144411Sscottl** byte 30 : channel 5674144411Sscottl** byte 31 : ID 5675144411Sscottl** byte 32 : LUN 5676144411Sscottl** byte 33 : 1 enable tag 5677144411Sscottl** byte 34 : 1 enable cache 5678144411Sscottl** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5679144411Sscottl** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5680144411Sscottl** byte 36 : 1 to select quick init 5681165155Sscottl** 5682144411Sscottl** GUI_MODIFY_VOLUME : Modify volume Set 5683144411Sscottl** byte 0,1 : length 5684144411Sscottl** byte 2 : command code 0x61 5685144411Sscottl** byte 3 : volumeset# 5686144411Sscottl** byte 4-19 : new volume set name (if byte4 == 0, not change) 5687144411Sscottl** byte 20-27 : new volume capacity (reserved) 5688144411Sscottl** byte 28 : new raid level 5689144411Sscottl** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5690144411Sscottl** byte 30 : new channel 5691144411Sscottl** byte 31 : new ID 5692144411Sscottl** byte 32 : new LUN 5693144411Sscottl** byte 33 : 1 enable tag 5694144411Sscottl** byte 34 : 1 enable cache 5695144411Sscottl** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5696144411Sscottl** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5697165155Sscottl** 5698144411Sscottl** GUI_DELETE_VOLUME : Delete volume set 5699144411Sscottl** byte 0,1 : length 5700144411Sscottl** byte 2 : command code 0x62 5701144411Sscottl** byte 3 : volumeset# 5702165155Sscottl** 5703144411Sscottl** GUI_START_CHECK_VOLUME : Start volume consistency check 5704144411Sscottl** byte 0,1 : length 5705144411Sscottl** byte 2 : command code 0x63 5706144411Sscottl** byte 3 : volumeset# 5707165155Sscottl** 5708144411Sscottl** GUI_STOP_CHECK_VOLUME : Stop volume consistency check 5709144411Sscottl** byte 0,1 : length 5710144411Sscottl** byte 2 : command code 0x64 5711144411Sscottl** --------------------------------------------------------------------- 5712144411Sscottl** 4. Returned data 5713144411Sscottl** --------------------------------------------------------------------- 5714144411Sscottl** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5715144411Sscottl** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte) 5716144411Sscottl** (C) status or data : 5717144411Sscottl** <1> If length == 1 ==> 1 byte status code 5718144411Sscottl** #define GUI_OK 0x41 5719144411Sscottl** #define GUI_RAIDSET_NOT_NORMAL 0x42 5720144411Sscottl** #define GUI_VOLUMESET_NOT_NORMAL 0x43 5721144411Sscottl** #define GUI_NO_RAIDSET 0x44 5722144411Sscottl** #define GUI_NO_VOLUMESET 0x45 5723144411Sscottl** #define GUI_NO_PHYSICAL_DRIVE 0x46 5724144411Sscottl** #define GUI_PARAMETER_ERROR 0x47 5725144411Sscottl** #define GUI_UNSUPPORTED_COMMAND 0x48 5726144411Sscottl** #define GUI_DISK_CONFIG_CHANGED 0x49 5727144411Sscottl** #define GUI_INVALID_PASSWORD 0x4a 5728144411Sscottl** #define GUI_NO_DISK_SPACE 0x4b 5729144411Sscottl** #define GUI_CHECKSUM_ERROR 0x4c 5730144411Sscottl** #define GUI_PASSWORD_REQUIRED 0x4d 5731144411Sscottl** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code 5732144411Sscottl** (E) Checksum : checksum of length and status or data byte 5733144411Sscottl************************************************************************** 5734144411Sscottl*/ 5735