aic6360reg.h revision 74370
1184902Srwatson/* 2184902Srwatson * Copyright (c) 1994 Charles Hannum. 3186647Srwatson * Copyright (c) 1994 Jarle Greipsland. 4186647Srwatson * All rights reserved. 5186647Srwatson * 6186647Srwatson * Redistribution and use in source and binary forms, with or without 7186647Srwatson * modification, are permitted provided that the following conditions 8186647Srwatson * are met: 9186647Srwatson * 1. Redistributions of source code must retain the above copyright 10186647Srwatson * notice, this list of conditions and the following disclaimer. 11186647Srwatson * 2. Redistributions in binary form must reproduce the above copyright 12186647Srwatson * notice, this list of conditions and the following disclaimer in the 13186647Srwatson * documentation and/or other materials provided with the distribution. 14186647Srwatson * 3. All advertising materials mentioning features or use of this software 15186647Srwatson * must display the following acknowledgement: 16186647Srwatson * This product includes software developed by Jarle Greipsland 17186647Srwatson * 4. The name of the author may not be used to endorse or promote products 18186647Srwatson * derived from this software without specific prior written permission. 19186647Srwatson * 20186647Srwatson * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21186647Srwatson * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22186647Srwatson * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23186647Srwatson * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 24186647Srwatson * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 25186647Srwatson * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26186647Srwatson * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27186647Srwatson * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28186647Srwatson * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 29186647Srwatson * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30186647Srwatson * POSSIBILITY OF SUCH DAMAGE. 31186647Srwatson * 32186647Srwatson * $FreeBSD: head/sys/dev/aic/aic6360reg.h 74370 2001-03-16 22:20:19Z ken $ 33186647Srwatson */ 34186647Srwatson 35186647Srwatson#define SCSISEQ 0x00 /* SCSI sequence control */ 36186647Srwatson#define SXFRCTL0 0x01 /* SCSI transfer control 0 */ 37186647Srwatson#define SXFRCTL1 0x02 /* SCSI transfer control 1 */ 38186647Srwatson#define SCSISIGI 0x03 /* SCSI signal in */ 39186647Srwatson#define SCSISIGO 0x03 /* SCSI signal out */ 40186647Srwatson#define SCSIRATE 0x04 /* SCSI rate control */ 41186647Srwatson#define SCSIID 0x05 /* SCSI ID */ 42186647Srwatson#define SELID 0x05 /* Selection/Reselection ID */ 43186647Srwatson#define SCSIDAT 0x06 /* SCSI Latched Data */ 44186647Srwatson#define SCSIBUS 0x07 /* SCSI Data Bus*/ 45186647Srwatson#define STCNT0 0x08 /* SCSI transfer count */ 46186647Srwatson#define STCNT1 0x09 47186647Srwatson#define STCNT2 0x0a 48184902Srwatson#define CLRSINT0 0x0b /* Clear SCSI interrupts 0 */ 49184902Srwatson#define SSTAT0 0x0b /* SCSI interrupt status 0 */ 50184902Srwatson#define CLRSINT1 0x0c /* Clear SCSI interrupts 1 */ 51184902Srwatson#define SSTAT1 0x0c /* SCSI status 1 */ 52184902Srwatson#define SSTAT2 0x0d /* SCSI status 2 */ 53184902Srwatson#define SCSITEST 0x0e /* SCSI test control */ 54184902Srwatson#define SSTAT3 0x0e /* SCSI status 3 */ 55184902Srwatson#define CLRSERR 0x0f /* Clear SCSI errors */ 56184902Srwatson#define SSTAT4 0x0f /* SCSI status 4 */ 57184902Srwatson#define SIMODE0 0x10 /* SCSI interrupt mode 0 */ 58184902Srwatson#define SIMODE1 0x11 /* SCSI interrupt mode 1 */ 59184902Srwatson#define DMACNTRL0 0x12 /* DMA control 0 */ 60184902Srwatson#define DMACNTRL1 0x13 /* DMA control 1 */ 61184902Srwatson#define DMASTAT 0x14 /* DMA status */ 62184902Srwatson#define FIFOSTAT 0x15 /* FIFO status */ 63184902Srwatson#define DMADATA 0x16 /* DMA data */ 64184902Srwatson#define DMADATAL 0x16 /* DMA data low byte */ 65184902Srwatson#define DMADATAH 0x17 /* DMA data high byte */ 66184902Srwatson#define BRSTCNTRL 0x18 /* Burst Control */ 67184902Srwatson#define DMADATALONG 0x18 68184902Srwatson#define PORTA 0x1a /* Port A */ 69184902Srwatson#define PORTB 0x1b /* Port B */ 70184902Srwatson#define REV 0x1c /* Revision (001 for 6360) */ 71184902Srwatson#define STACK 0x1d /* Stack */ 72184902Srwatson#define TEST 0x1e /* Test register */ 73184902Srwatson#define ID 0x1f /* ID register */ 74184902Srwatson 75184902Srwatson#define IDSTRING "(C)1991ADAPTECAIC6360 " 76184902Srwatson 77184902Srwatson/* What all the bits do */ 78184902Srwatson 79184902Srwatson/* SCSISEQ */ 80184902Srwatson#define TEMODEO 0x80 81184902Srwatson#define ENSELO 0x40 82184902Srwatson#define ENSELI 0x20 83184902Srwatson#define ENRESELI 0x10 84184902Srwatson#define ENAUTOATNO 0x08 85184902Srwatson#define ENAUTOATNI 0x04 86184902Srwatson#define ENAUTOATNP 0x02 87184902Srwatson#define SCSIRSTO 0x01 88184902Srwatson 89184902Srwatson/* SXFRCTL0 */ 90184902Srwatson#define SCSIEN 0x80 91184902Srwatson#define DMAEN 0x40 92184902Srwatson#define CHEN 0x20 93184902Srwatson#define CLRSTCNT 0x10 94184902Srwatson#define SPIOEN 0x08 95184902Srwatson#define CLRCH 0x02 96184902Srwatson 97184902Srwatson/* SXFRCTL1 */ 98184902Srwatson#define BITBUCKET 0x80 99184902Srwatson#define SWRAPEN 0x40 100184902Srwatson#define ENSPCHK 0x20 101184902Srwatson#define STIMESEL1 0x10 102184902Srwatson#define STIMESEL0 0x08 103184902Srwatson#define STIMO_256ms 0x00 104184902Srwatson#define STIMO_128ms 0x08 105184902Srwatson#define STIMO_64ms 0x10 106184902Srwatson#define STIMO_32ms 0x18 107184902Srwatson#define ENSTIMER 0x04 108184902Srwatson#define BYTEALIGN 0x02 109184902Srwatson 110184902Srwatson/* SCSISIGI */ 111184902Srwatson#define CDI 0x80 112184902Srwatson#define IOI 0x40 113184902Srwatson#define MSGI 0x20 114184902Srwatson#define ATNI 0x10 115184902Srwatson#define SELI 0x08 116184902Srwatson#define BSYI 0x04 117184902Srwatson#define REQI 0x02 118184902Srwatson#define ACKI 0x01 119184902Srwatson 120184902Srwatson/* Important! The 3 most significant bits of this register, in initiator mode, 121184902Srwatson * represents the "expected" SCSI bus phase and can be used to trigger phase 122184902Srwatson * mismatch and phase change interrupts. But more important: If there is a 123184902Srwatson * phase mismatch the chip will not transfer any data! This is actually a nice 124184902Srwatson * feature as it gives us a bit more control over what is happening when we are 125184902Srwatson * bursting data (in) through the FIFOs and the phase suddenly changes from 126184902Srwatson * DATA IN to STATUS or MESSAGE IN. The transfer will stop and wait for the 127184902Srwatson * proper phase to be set in this register instead of dumping the bits into the 128184902Srwatson * FIFOs. 129184902Srwatson */ 130184902Srwatson/* SCSISIGO */ 131184902Srwatson#define CDO 0x80 132184902Srwatson#define IOO 0x40 133184902Srwatson#define MSGO 0x20 134184902Srwatson#define ATNO 0x10 135184902Srwatson#define SELO 0x08 136184902Srwatson#define BSYO 0x04 137184902Srwatson#define REQO 0x02 138184902Srwatson#define ACKO 0x01 139184902Srwatson 140184902Srwatson/* Information transfer phases */ 141184902Srwatson#define PH_DATAOUT (0) 142184902Srwatson#define PH_DATAIN (IOI) 143184902Srwatson#define PH_CMD (CDI) 144184902Srwatson#define PH_STAT (CDI|IOI) 145184902Srwatson#define PH_MSGOUT (MSGI|CDI) 146184902Srwatson#define PH_MSGIN (MSGI|CDI|IOI) 147184902Srwatson#define PH_MASK (MSGI|CDI|IOI) 148184902Srwatson 149184902Srwatson/* SCSIRATE */ 150184902Srwatson#define SXFR2 0x40 151184902Srwatson#define SXFR1 0x20 152184902Srwatson#define SXFR0 0x10 153184902Srwatson#define SOFS3 0x08 154184902Srwatson#define SOFS2 0x04 155184902Srwatson#define SOFS1 0x02 156184902Srwatson#define SOFS0 0x01 157184902Srwatson 158184902Srwatson/* SCSI ID */ 159184902Srwatson#define OID2 0x40 160184902Srwatson#define OID1 0x20 161184902Srwatson#define OID0 0x10 162184902Srwatson#define OID_S 4 /* shift value */ 163184902Srwatson#define TID2 0x04 164184902Srwatson#define TID1 0x02 165184902Srwatson#define TID0 0x01 166184902Srwatson#define SCSI_ID_MASK 0x7 167184902Srwatson 168184902Srwatson/* SCSI selection/reselection ID (both target *and* initiator) */ 169184902Srwatson#define SELID7 0x80 170184902Srwatson#define SELID6 0x40 171184902Srwatson#define SELID5 0x20 172184902Srwatson#define SELID4 0x10 173184902Srwatson#define SELID3 0x08 174184902Srwatson#define SELID2 0x04 175184902Srwatson#define SELID1 0x02 176184902Srwatson#define SELID0 0x01 177184902Srwatson 178184902Srwatson/* CLRSINT0 Clears what? (interrupt and/or status bit) */ 179184902Srwatson#define SETSDONE 0x80 180184902Srwatson#define CLRSELDO 0x40 /* I */ 181184902Srwatson#define CLRSELDI 0x20 /* I+ */ 182184902Srwatson#define CLRSELINGO 0x10 /* I */ 183184902Srwatson#define CLRSWRAP 0x08 /* I+S */ 184184902Srwatson#define CLRSDONE 0x04 /* I+S */ 185184902Srwatson#define CLRSPIORDY 0x02 /* I */ 186184902Srwatson#define CLRDMADONE 0x01 /* I */ 187184902Srwatson 188184902Srwatson/* SSTAT0 Howto clear */ 189184902Srwatson#define TARGET 0x80 190184902Srwatson#define SELDO 0x40 /* Selfclearing */ 191184902Srwatson#define SELDI 0x20 /* Selfclearing when CLRSELDI is set */ 192184902Srwatson#define SELINGO 0x10 /* Selfclearing */ 193184902Srwatson#define SWRAP 0x08 /* CLRSWAP */ 194184902Srwatson#define SDONE 0x04 /* Not used in initiator mode */ 195184902Srwatson#define SPIORDY 0x02 /* Selfclearing (op on SCSIDAT) */ 196184902Srwatson#define DMADONE 0x01 /* Selfclearing (all FIFOs empty & T/C */ 197184902Srwatson 198184902Srwatson/* CLRSINT1 Clears what? */ 199184902Srwatson#define CLRSELTIMO 0x80 /* I+S */ 200184902Srwatson#define CLRATNO 0x40 201184902Srwatson#define CLRSCSIRSTI 0x20 /* I+S */ 202184902Srwatson#define CLRBUSFREE 0x08 /* I+S */ 203184902Srwatson#define CLRSCSIPERR 0x04 /* I+S */ 204184902Srwatson#define CLRPHASECHG 0x02 /* I+S */ 205184902Srwatson#define CLRREQINIT 0x01 /* I+S */ 206184902Srwatson 207184902Srwatson/* SSTAT1 How to clear? When set?*/ 208184902Srwatson#define SELTO 0x80 /* C select out timeout */ 209184902Srwatson#define ATNTARG 0x40 /* Not used in initiator mode */ 210184902Srwatson#define SCSIRSTI 0x20 /* C RST asserted */ 211184902Srwatson#define PHASEMIS 0x10 /* Selfclearing */ 212184902Srwatson#define BUSFREE 0x08 /* C bus free condition */ 213184902Srwatson#define SCSIPERR 0x04 /* C parity error on inbound data */ 214184902Srwatson#define PHASECHG 0x02 /* C phase in SCSISIGI doesn't match */ 215184902Srwatson#define REQINIT 0x01 /* C or ACK asserting edge of REQ */ 216184902Srwatson 217184902Srwatson/* SSTAT2 */ 218184902Srwatson#define SOFFSET 0x20 219184902Srwatson#define SEMPTY 0x10 220184902Srwatson#define SFULL 0x08 221184902Srwatson#define SFCNT2 0x04 222184902Srwatson#define SFCNT1 0x02 223184902Srwatson#define SFCNT0 0x01 224184902Srwatson 225184902Srwatson/* SCSITEST */ 226184902Srwatson#define SCTESTU 0x08 227184902Srwatson#define SCTESTD 0x04 228184902Srwatson#define STCTEST 0x01 229184902Srwatson 230184902Srwatson/* SSTAT3 */ 231184902Srwatson#define SCSICNT3 0x80 232184902Srwatson#define SCSICNT2 0x40 233184902Srwatson#define SCSICNT1 0x20 234184902Srwatson#define SCSICNT0 0x10 235184902Srwatson#define OFFCNT3 0x08 236184902Srwatson#define OFFCNT2 0x04 237184902Srwatson#define OFFCNT1 0x02 238184902Srwatson#define OFFCNT0 0x01 239184902Srwatson 240184902Srwatson/* CLRSERR */ 241184902Srwatson#define CLRSYNCERR 0x04 242184902Srwatson#define CLRFWERR 0x02 243184902Srwatson#define CLRFRERR 0x01 244184902Srwatson 245184902Srwatson/* SSTAT4 */ 246184902Srwatson#define SYNCERR 0x04 247184902Srwatson#define FWERR 0x02 248184902Srwatson#define FRERR 0x01 249184902Srwatson 250184902Srwatson/* SIMODE0 */ 251184902Srwatson#define ENSELDO 0x40 252184902Srwatson#define ENSELDI 0x20 253184902Srwatson#define ENSELINGO 0x10 254184902Srwatson#define ENSWRAP 0x08 255184902Srwatson#define ENSDONE 0x04 256184902Srwatson#define ENSPIORDY 0x02 257184902Srwatson#define ENDMADONE 0x01 258184902Srwatson 259184902Srwatson/* SIMODE1 */ 260184902Srwatson#define ENSELTIMO 0x80 261184902Srwatson#define ENATNTARG 0x40 262184902Srwatson#define ENSCSIRST 0x20 263184902Srwatson#define ENPHASEMIS 0x10 264184902Srwatson#define ENBUSFREE 0x08 265184902Srwatson#define ENSCSIPERR 0x04 266184902Srwatson#define ENPHASECHG 0x02 267184902Srwatson#define ENREQINIT 0x01 268184902Srwatson 269184902Srwatson/* DMACNTRL0 */ 270184902Srwatson#define ENDMA 0x80 271184902Srwatson#define B8MODE 0x40 272184902Srwatson#define DMA 0x20 273184902Srwatson#define DWORDPIO 0x10 274184902Srwatson#define WRITE 0x08 275184902Srwatson#define INTEN 0x04 276184902Srwatson#define RSTFIFO 0x02 277184902Srwatson#define SWINT 0x01 278184902Srwatson 279184902Srwatson/* DMACNTRL1 */ 280184902Srwatson#define PWRDWN 0x80 281184902Srwatson#define ENSTK32 0x40 282184902Srwatson#define STK4 0x10 283184902Srwatson#define STK3 0x08 284184902Srwatson#define STK2 0x04 285184902Srwatson#define STK1 0x02 286184902Srwatson#define STK0 0x01 287184902Srwatson 288184902Srwatson/* DMASTAT */ 289184902Srwatson#define ATDONE 0x80 290184902Srwatson#define WORDRDY 0x40 291184902Srwatson#define INTSTAT 0x20 292184902Srwatson#define DFIFOFULL 0x10 293184902Srwatson#define DFIFOEMP 0x08 294184902Srwatson#define DFIFOHF 0x04 295184902Srwatson#define DWORDRDY 0x02 296184902Srwatson 297184902Srwatson/* BRSTCNTRL */ 298184902Srwatson#define BON3 0x80 299184902Srwatson#define BON2 0x40 300184902Srwatson#define BON1 0x20 301184902Srwatson#define BON0 0x10 302184902Srwatson#define BOFF3 0x08 303184902Srwatson#define BOFF2 0x04 304184902Srwatson#define BOFF1 0x02 305184902Srwatson#define BOFF0 0x01 306184902Srwatson 307184902Srwatson/* TEST */ 308184902Srwatson#define BOFFTMR 0x40 309184902Srwatson#define BONTMR 0x20 310184902Srwatson#define STCNTH 0x10 311184902Srwatson#define STCNTM 0x08 312184902Srwatson#define STCNTL 0x04 313184902Srwatson#define SCSIBLK 0x02 314184902Srwatson#define DMABLK 0x01 315184902Srwatson 316184902Srwatson/* PORTA */ 317184902Srwatson#define PORTA_ID(a) ((a) & 7) 318184902Srwatson#define PORTA_IRQ(a) ((((a) >> 3) & 3) + 9) 319184902Srwatson#define PORTA_DRQ(a) ((((a) >> 5) & 3) ? (((a) >> 5) & 3) + 4 : 0) 320184902Srwatson#define PORTA_PARITY(a) ((a) & 0x80) 321184902Srwatson 322184902Srwatson/* PORTB */ 323184902Srwatson#define PORTB_EXTTRAN(b)((b) & 1) 324184902Srwatson#define PORTB_DISC(b) ((b) & 4) 325184902Srwatson#define PORTB_SYNC(b) ((b) & 8) 326184902Srwatson#define PORTB_FSYNC(b) ((b) & 0x10) 327184902Srwatson#define PORTB_BOOT(b) ((b) & 0x40) 328184902Srwatson#define PORTB_DMA(b) ((b) & 0x80) 329184902Srwatson 330184902Srwatson/* How to behave on the (E)ISA bus when/if DMAing (on<<4) + off in us */ 331184902Srwatson#define EISA_BRST_TIM ((15<<4) + 1) /* 15us on, 1us off */ 332184902Srwatson 333184902Srwatson#define FIFOSIZE 128 334184902Srwatson