if_age.c revision 242348
1223637Sbz/*- 2223637Sbz * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3126353Smlaier * All rights reserved. 4126353Smlaier * 5126353Smlaier * Redistribution and use in source and binary forms, with or without 6126353Smlaier * modification, are permitted provided that the following conditions 7126353Smlaier * are met: 8126353Smlaier * 1. Redistributions of source code must retain the above copyright 9126353Smlaier * notice unmodified, this list of conditions, and the following 10126353Smlaier * disclaimer. 11126353Smlaier * 2. Redistributions in binary form must reproduce the above copyright 12126353Smlaier * notice, this list of conditions and the following disclaimer in the 13126353Smlaier * documentation and/or other materials provided with the distribution. 14126353Smlaier * 15126353Smlaier * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16126353Smlaier * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17126353Smlaier * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18126353Smlaier * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19126353Smlaier * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20126353Smlaier * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21126353Smlaier * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22126353Smlaier * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23126353Smlaier * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24126353Smlaier * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25126353Smlaier * SUCH DAMAGE. 26126353Smlaier */ 27126353Smlaier 28126353Smlaier/* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 29126353Smlaier 30126353Smlaier#include <sys/cdefs.h> 31240233Sglebius__FBSDID("$FreeBSD: head/sys/dev/age/if_age.c 242348 2012-10-30 07:55:03Z yongari $"); 32126353Smlaier 33126353Smlaier#include <sys/param.h> 34126353Smlaier#include <sys/systm.h> 35126353Smlaier#include <sys/bus.h> 36126353Smlaier#include <sys/endian.h> 37126353Smlaier#include <sys/kernel.h> 38126353Smlaier#include <sys/malloc.h> 39126353Smlaier#include <sys/mbuf.h> 40126353Smlaier#include <sys/rman.h> 41126353Smlaier#include <sys/module.h> 42126353Smlaier#include <sys/queue.h> 43126353Smlaier#include <sys/socket.h> 44126353Smlaier#include <sys/sockio.h> 45126353Smlaier#include <sys/sysctl.h> 46126353Smlaier#include <sys/taskqueue.h> 47126353Smlaier 48126353Smlaier#include <net/bpf.h> 49126353Smlaier#include <net/if.h> 50126353Smlaier#include <net/if_arp.h> 51126353Smlaier#include <net/ethernet.h> 52126353Smlaier#include <net/if_dl.h> 53126353Smlaier#include <net/if_media.h> 54126353Smlaier#include <net/if_types.h> 55126353Smlaier#include <net/if_vlan_var.h> 56126353Smlaier 57126353Smlaier#include <netinet/in.h> 58126353Smlaier#include <netinet/in_systm.h> 59126353Smlaier#include <netinet/ip.h> 60126353Smlaier#include <netinet/tcp.h> 61126353Smlaier 62126353Smlaier#include <dev/mii/mii.h> 63126353Smlaier#include <dev/mii/miivar.h> 64126353Smlaier 65126353Smlaier#include <dev/pci/pcireg.h> 66171172Smlaier#include <dev/pci/pcivar.h> 67126353Smlaier 68126353Smlaier#include <machine/bus.h> 69126353Smlaier#include <machine/in_cksum.h> 70126353Smlaier 71126353Smlaier#include <dev/age/if_agereg.h> 72126353Smlaier#include <dev/age/if_agevar.h> 73126353Smlaier 74126353Smlaier/* "device miibus" required. See GENERIC if you get errors here. */ 75126353Smlaier#include "miibus_if.h" 76126353Smlaier 77126353Smlaier#define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 78126353Smlaier 79126353SmlaierMODULE_DEPEND(age, pci, 1, 1, 1); 80126353SmlaierMODULE_DEPEND(age, ether, 1, 1, 1); 81126353SmlaierMODULE_DEPEND(age, miibus, 1, 1, 1); 82223637Sbz 83223637Sbz/* Tunables. */ 84223637Sbzstatic int msi_disable = 0; 85223637Sbzstatic int msix_disable = 0; 86223637SbzTUNABLE_INT("hw.age.msi_disable", &msi_disable); 87223637SbzTUNABLE_INT("hw.age.msix_disable", &msix_disable); 88223637Sbz 89223637Sbz/* 90223637Sbz * Devices supported by this driver. 91223637Sbz */ 92223637Sbzstatic struct age_dev { 93126353Smlaier uint16_t age_vendorid; 94171172Smlaier uint16_t age_deviceid; 95126353Smlaier const char *age_name; 96126353Smlaier} age_devs[] = { 97126353Smlaier { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 98126353Smlaier "Attansic Technology Corp, L1 Gigabit Ethernet" }, 99126353Smlaier}; 100126353Smlaier 101126353Smlaierstatic int age_miibus_readreg(device_t, int, int); 102126353Smlaierstatic int age_miibus_writereg(device_t, int, int, int); 103126353Smlaierstatic void age_miibus_statchg(device_t); 104126353Smlaierstatic void age_mediastatus(struct ifnet *, struct ifmediareq *); 105126353Smlaierstatic int age_mediachange(struct ifnet *); 106126353Smlaierstatic int age_probe(device_t); 107171172Smlaierstatic void age_get_macaddr(struct age_softc *); 108171172Smlaierstatic void age_phy_reset(struct age_softc *); 109126353Smlaierstatic int age_attach(device_t); 110126353Smlaierstatic int age_detach(device_t); 111126353Smlaierstatic void age_sysctl_node(struct age_softc *); 112126353Smlaierstatic void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 113126353Smlaierstatic int age_check_boundary(struct age_softc *); 114126353Smlaierstatic int age_dma_alloc(struct age_softc *); 115126353Smlaierstatic void age_dma_free(struct age_softc *); 116126353Smlaierstatic int age_shutdown(device_t); 117126353Smlaierstatic void age_setwol(struct age_softc *); 118126353Smlaierstatic int age_suspend(device_t); 119126353Smlaierstatic int age_resume(device_t); 120126353Smlaierstatic int age_encap(struct age_softc *, struct mbuf **); 121126353Smlaierstatic void age_start(struct ifnet *); 122126353Smlaierstatic void age_start_locked(struct ifnet *); 123126353Smlaierstatic void age_watchdog(struct age_softc *); 124126353Smlaierstatic int age_ioctl(struct ifnet *, u_long, caddr_t); 125126353Smlaierstatic void age_mac_config(struct age_softc *); 126126353Smlaierstatic void age_link_task(void *, int); 127126353Smlaierstatic void age_stats_update(struct age_softc *); 128126353Smlaierstatic int age_intr(void *); 129126353Smlaierstatic void age_int_task(void *, int); 130126353Smlaierstatic void age_txintr(struct age_softc *, int); 131126353Smlaierstatic void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 132126353Smlaierstatic int age_rxintr(struct age_softc *, int, int); 133126353Smlaierstatic void age_tick(void *); 134126353Smlaierstatic void age_reset(struct age_softc *); 135126353Smlaierstatic void age_init(void *); 136126353Smlaierstatic void age_init_locked(struct age_softc *); 137126353Smlaierstatic void age_stop(struct age_softc *); 138126353Smlaierstatic void age_stop_txmac(struct age_softc *); 139126353Smlaierstatic void age_stop_rxmac(struct age_softc *); 140126353Smlaierstatic void age_init_tx_ring(struct age_softc *); 141126353Smlaierstatic int age_init_rx_ring(struct age_softc *); 142126353Smlaierstatic void age_init_rr_ring(struct age_softc *); 143126353Smlaierstatic void age_init_cmb_block(struct age_softc *); 144126353Smlaierstatic void age_init_smb_block(struct age_softc *); 145126353Smlaierstatic int age_newbuf(struct age_softc *, struct age_rxdesc *); 146126353Smlaierstatic void age_rxvlan(struct age_softc *); 147126353Smlaierstatic void age_rxfilter(struct age_softc *); 148126353Smlaierstatic int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 149126353Smlaierstatic int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 150126353Smlaierstatic int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); 151126353Smlaierstatic int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 152126353Smlaier 153126353Smlaier 154126353Smlaierstatic device_method_t age_methods[] = { 155126353Smlaier /* Device interface. */ 156126353Smlaier DEVMETHOD(device_probe, age_probe), 157126353Smlaier DEVMETHOD(device_attach, age_attach), 158126353Smlaier DEVMETHOD(device_detach, age_detach), 159126353Smlaier DEVMETHOD(device_shutdown, age_shutdown), 160126353Smlaier DEVMETHOD(device_suspend, age_suspend), 161126353Smlaier DEVMETHOD(device_resume, age_resume), 162126353Smlaier 163126353Smlaier /* MII interface. */ 164126353Smlaier DEVMETHOD(miibus_readreg, age_miibus_readreg), 165126353Smlaier DEVMETHOD(miibus_writereg, age_miibus_writereg), 166126353Smlaier DEVMETHOD(miibus_statchg, age_miibus_statchg), 167126353Smlaier 168223637Sbz { NULL, NULL } 169126353Smlaier}; 170126353Smlaier 171126353Smlaierstatic driver_t age_driver = { 172126353Smlaier "age", 173126353Smlaier age_methods, 174126353Smlaier sizeof(struct age_softc) 175126353Smlaier}; 176126353Smlaier 177126353Smlaierstatic devclass_t age_devclass; 178126353Smlaier 179126353SmlaierDRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0); 180126353SmlaierDRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0); 181126353Smlaier 182126353Smlaierstatic struct resource_spec age_res_spec_mem[] = { 183126353Smlaier { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 184126353Smlaier { -1, 0, 0 } 185170194Sremko}; 186126353Smlaier 187223637Sbzstatic struct resource_spec age_irq_spec_legacy[] = { 188223637Sbz { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 189223637Sbz { -1, 0, 0 } 190223637Sbz}; 191223637Sbz 192126353Smlaierstatic struct resource_spec age_irq_spec_msi[] = { 193126353Smlaier { SYS_RES_IRQ, 1, RF_ACTIVE }, 194126353Smlaier { -1, 0, 0 } 195126353Smlaier}; 196171172Smlaier 197171172Smlaierstatic struct resource_spec age_irq_spec_msix[] = { 198171172Smlaier { SYS_RES_IRQ, 1, RF_ACTIVE }, 199126353Smlaier { -1, 0, 0 } 200126353Smlaier}; 201126353Smlaier 202126353Smlaier/* 203126353Smlaier * Read a PHY register on the MII of the L1. 204126353Smlaier */ 205126353Smlaierstatic int 206126353Smlaierage_miibus_readreg(device_t dev, int phy, int reg) 207126353Smlaier{ 208126353Smlaier struct age_softc *sc; 209126353Smlaier uint32_t v; 210126353Smlaier int i; 211126353Smlaier 212126353Smlaier sc = device_get_softc(dev); 213126353Smlaier 214126353Smlaier CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 215126353Smlaier MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 216171172Smlaier for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 217171172Smlaier DELAY(1); 218126353Smlaier v = CSR_READ_4(sc, AGE_MDIO); 219126353Smlaier if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 220126353Smlaier break; 221126353Smlaier } 222126353Smlaier 223126353Smlaier if (i == 0) { 224126353Smlaier device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 225126353Smlaier return (0); 226126353Smlaier } 227126353Smlaier 228126353Smlaier return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 229126353Smlaier} 230126353Smlaier 231126353Smlaier/* 232171172Smlaier * Write a PHY register on the MII of the L1. 233126353Smlaier */ 234126353Smlaierstatic int 235126353Smlaierage_miibus_writereg(device_t dev, int phy, int reg, int val) 236126353Smlaier{ 237126353Smlaier struct age_softc *sc; 238126353Smlaier uint32_t v; 239126353Smlaier int i; 240126353Smlaier 241126353Smlaier sc = device_get_softc(dev); 242126353Smlaier 243126353Smlaier CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 244145840Smlaier (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 245126353Smlaier MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 246126353Smlaier for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 247126353Smlaier DELAY(1); 248126353Smlaier v = CSR_READ_4(sc, AGE_MDIO); 249130614Smlaier if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 250130614Smlaier break; 251130614Smlaier } 252126353Smlaier 253126353Smlaier if (i == 0) 254126353Smlaier device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 255126353Smlaier 256126353Smlaier return (0); 257126353Smlaier} 258126353Smlaier 259126353Smlaier/* 260126353Smlaier * Callback from MII layer when media changes. 261126353Smlaier */ 262126353Smlaierstatic void 263126353Smlaierage_miibus_statchg(device_t dev) 264126353Smlaier{ 265126353Smlaier struct age_softc *sc; 266126353Smlaier 267126353Smlaier sc = device_get_softc(dev); 268126353Smlaier taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); 269126353Smlaier} 270126353Smlaier 271126353Smlaier/* 272126353Smlaier * Get the current interface media status. 273126353Smlaier */ 274126353Smlaierstatic void 275126353Smlaierage_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 276126353Smlaier{ 277126353Smlaier struct age_softc *sc; 278126353Smlaier struct mii_data *mii; 279126353Smlaier 280126353Smlaier sc = ifp->if_softc; 281126353Smlaier AGE_LOCK(sc); 282126353Smlaier mii = device_get_softc(sc->age_miibus); 283126353Smlaier 284126353Smlaier mii_pollstat(mii); 285126353Smlaier ifmr->ifm_status = mii->mii_media_status; 286126353Smlaier ifmr->ifm_active = mii->mii_media_active; 287126353Smlaier AGE_UNLOCK(sc); 288126353Smlaier} 289126353Smlaier 290126353Smlaier/* 291126353Smlaier * Set hardware to newly-selected media. 292126353Smlaier */ 293126353Smlaierstatic int 294126353Smlaierage_mediachange(struct ifnet *ifp) 295126353Smlaier{ 296126353Smlaier struct age_softc *sc; 297126353Smlaier struct mii_data *mii; 298126353Smlaier struct mii_softc *miisc; 299126353Smlaier int error; 300126353Smlaier 301126353Smlaier sc = ifp->if_softc; 302126353Smlaier AGE_LOCK(sc); 303126353Smlaier mii = device_get_softc(sc->age_miibus); 304126353Smlaier LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 305126353Smlaier PHY_RESET(miisc); 306126353Smlaier error = mii_mediachg(mii); 307126353Smlaier AGE_UNLOCK(sc); 308126353Smlaier 309126353Smlaier return (error); 310126353Smlaier} 311126353Smlaier 312126353Smlaierstatic int 313126353Smlaierage_probe(device_t dev) 314126353Smlaier{ 315126353Smlaier struct age_dev *sp; 316126353Smlaier int i; 317126353Smlaier uint16_t vendor, devid; 318126353Smlaier 319126353Smlaier vendor = pci_get_vendor(dev); 320126353Smlaier devid = pci_get_device(dev); 321126353Smlaier sp = age_devs; 322126353Smlaier for (i = 0; i < sizeof(age_devs) / sizeof(age_devs[0]); 323126353Smlaier i++, sp++) { 324126353Smlaier if (vendor == sp->age_vendorid && 325171172Smlaier devid == sp->age_deviceid) { 326171172Smlaier device_set_desc(dev, sp->age_name); 327171172Smlaier return (BUS_PROBE_DEFAULT); 328171172Smlaier } 329171172Smlaier } 330171172Smlaier 331126353Smlaier return (ENXIO); 332126353Smlaier} 333126353Smlaier 334126353Smlaierstatic void 335126353Smlaierage_get_macaddr(struct age_softc *sc) 336126353Smlaier{ 337126353Smlaier uint32_t ea[2], reg; 338126353Smlaier int i, vpdc; 339126353Smlaier 340126353Smlaier reg = CSR_READ_4(sc, AGE_SPI_CTRL); 341126353Smlaier if ((reg & SPI_VPD_ENB) != 0) { 342126353Smlaier /* Get VPD stored in TWSI EEPROM. */ 343126353Smlaier reg &= ~SPI_VPD_ENB; 344126353Smlaier CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 345126353Smlaier } 346126353Smlaier 347223637Sbz if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { 348223637Sbz /* 349126353Smlaier * PCI VPD capability found, let TWSI reload EEPROM. 350126353Smlaier * This will set ethernet address of controller. 351126353Smlaier */ 352126353Smlaier CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 353126353Smlaier TWSI_CTRL_SW_LD_START); 354126353Smlaier for (i = 100; i > 0; i--) { 355126353Smlaier DELAY(1000); 356126353Smlaier reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 357126353Smlaier if ((reg & TWSI_CTRL_SW_LD_START) == 0) 358126353Smlaier break; 359126353Smlaier } 360126353Smlaier if (i == 0) 361126353Smlaier device_printf(sc->age_dev, 362126353Smlaier "reloading EEPROM timeout!\n"); 363126353Smlaier } else { 364126353Smlaier if (bootverbose) 365126353Smlaier device_printf(sc->age_dev, 366126353Smlaier "PCI VPD capability not found!\n"); 367126353Smlaier } 368126353Smlaier 369137693Smlaier ea[0] = CSR_READ_4(sc, AGE_PAR0); 370126353Smlaier ea[1] = CSR_READ_4(sc, AGE_PAR1); 371126353Smlaier sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 372126353Smlaier sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 373126353Smlaier sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 374126353Smlaier sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 375126353Smlaier sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 376126353Smlaier sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 377126353Smlaier} 378126353Smlaier 379171172Smlaierstatic void 380171172Smlaierage_phy_reset(struct age_softc *sc) 381171172Smlaier{ 382171172Smlaier uint16_t reg, pn; 383126353Smlaier int i, linkup; 384126353Smlaier 385126353Smlaier /* Reset PHY. */ 386126353Smlaier CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 387126353Smlaier DELAY(2000); 388126353Smlaier CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 389126353Smlaier DELAY(2000); 390126353Smlaier 391126353Smlaier#define ATPHY_DBG_ADDR 0x1D 392171172Smlaier#define ATPHY_DBG_DATA 0x1E 393130614Smlaier#define ATPHY_CDTC 0x16 394130614Smlaier#define PHY_CDTC_ENB 0x0001 395130614Smlaier#define PHY_CDTC_POFF 8 396126353Smlaier#define ATPHY_CDTS 0x1C 397130614Smlaier#define PHY_CDTS_STAT_OK 0x0000 398130614Smlaier#define PHY_CDTS_STAT_SHORT 0x0100 399130614Smlaier#define PHY_CDTS_STAT_OPEN 0x0200 400130614Smlaier#define PHY_CDTS_STAT_INVAL 0x0300 401171172Smlaier#define PHY_CDTS_STAT_MASK 0x0300 402130614Smlaier 403171172Smlaier /* Check power saving mode. Magic from Linux. */ 404171172Smlaier age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 405171172Smlaier for (linkup = 0, pn = 0; pn < 4; pn++) { 406171172Smlaier age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC, 407171172Smlaier (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 408130614Smlaier for (i = 200; i > 0; i--) { 409171172Smlaier DELAY(1000); 410171172Smlaier reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 411171172Smlaier ATPHY_CDTC); 412171172Smlaier if ((reg & PHY_CDTC_ENB) == 0) 413171172Smlaier break; 414171172Smlaier } 415126353Smlaier DELAY(1000); 416130614Smlaier reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 417126353Smlaier ATPHY_CDTS); 418126353Smlaier if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 419171172Smlaier linkup++; 420171172Smlaier break; 421171172Smlaier } 422171172Smlaier } 423223637Sbz age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, 424223637Sbz BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 425171172Smlaier if (linkup == 0) { 426223637Sbz age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 427171172Smlaier ATPHY_DBG_ADDR, 0); 428171172Smlaier age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 429171172Smlaier ATPHY_DBG_DATA, 0x124E); 430171172Smlaier age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 431171172Smlaier ATPHY_DBG_ADDR, 1); 432171172Smlaier reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 433171172Smlaier ATPHY_DBG_DATA); 434171172Smlaier age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 435171172Smlaier ATPHY_DBG_DATA, reg | 0x03); 436171172Smlaier /* XXX */ 437171172Smlaier DELAY(1500 * 1000); 438171172Smlaier age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 439171172Smlaier ATPHY_DBG_ADDR, 0); 440171172Smlaier age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 441171172Smlaier ATPHY_DBG_DATA, 0x024E); 442171172Smlaier } 443171172Smlaier 444171172Smlaier#undef ATPHY_DBG_ADDR 445171172Smlaier#undef ATPHY_DBG_DATA 446171172Smlaier#undef ATPHY_CDTC 447171172Smlaier#undef PHY_CDTC_ENB 448171172Smlaier#undef PHY_CDTC_POFF 449171172Smlaier#undef ATPHY_CDTS 450171172Smlaier#undef PHY_CDTS_STAT_OK 451171172Smlaier#undef PHY_CDTS_STAT_SHORT 452171172Smlaier#undef PHY_CDTS_STAT_OPEN 453171172Smlaier#undef PHY_CDTS_STAT_INVAL 454171172Smlaier#undef PHY_CDTS_STAT_MASK 455171172Smlaier} 456171172Smlaier 457126353Smlaierstatic int 458171172Smlaierage_attach(device_t dev) 459126353Smlaier{ 460126353Smlaier struct age_softc *sc; 461126353Smlaier struct ifnet *ifp; 462126353Smlaier uint16_t burst; 463126353Smlaier int error, i, msic, msixc, pmc; 464126353Smlaier 465126353Smlaier error = 0; 466126353Smlaier sc = device_get_softc(dev); 467126353Smlaier sc->age_dev = dev; 468126353Smlaier 469126353Smlaier mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 470126353Smlaier MTX_DEF); 471126353Smlaier callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); 472126353Smlaier TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); 473126353Smlaier TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); 474126353Smlaier 475126353Smlaier /* Map the device. */ 476126353Smlaier pci_enable_busmaster(dev); 477126353Smlaier sc->age_res_spec = age_res_spec_mem; 478126353Smlaier sc->age_irq_spec = age_irq_spec_legacy; 479126353Smlaier error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); 480126353Smlaier if (error != 0) { 481126353Smlaier device_printf(dev, "cannot allocate memory resources.\n"); 482126353Smlaier goto fail; 483126353Smlaier } 484126353Smlaier 485126353Smlaier /* Set PHY address. */ 486126353Smlaier sc->age_phyaddr = AGE_PHY_ADDR; 487126353Smlaier 488126353Smlaier /* Reset PHY. */ 489126353Smlaier age_phy_reset(sc); 490126353Smlaier 491126353Smlaier /* Reset the ethernet controller. */ 492126353Smlaier age_reset(sc); 493126353Smlaier 494126353Smlaier /* Get PCI and chip id/revision. */ 495126353Smlaier sc->age_rev = pci_get_revid(dev); 496126353Smlaier sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 497126353Smlaier MASTER_CHIP_REV_SHIFT; 498126353Smlaier if (bootverbose) { 499126353Smlaier device_printf(dev, "PCI device revision : 0x%04x\n", 500126353Smlaier sc->age_rev); 501126353Smlaier device_printf(dev, "Chip id/revision : 0x%04x\n", 502126353Smlaier sc->age_chip_rev); 503126353Smlaier } 504126353Smlaier 505130614Smlaier /* 506130614Smlaier * XXX 507130614Smlaier * Unintialized hardware returns an invalid chip id/revision 508130614Smlaier * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 509130614Smlaier * unplugged cable results in putting hardware into automatic 510130614Smlaier * power down mode which in turn returns invalld chip revision. 511130614Smlaier */ 512130614Smlaier if (sc->age_chip_rev == 0xFFFF) { 513130614Smlaier device_printf(dev,"invalid chip revision : 0x%04x -- " 514130614Smlaier "not initialized?\n", sc->age_chip_rev); 515130614Smlaier error = ENXIO; 516130614Smlaier goto fail; 517130614Smlaier } 518130614Smlaier 519130614Smlaier device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 520130614Smlaier CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 521223637Sbz CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 522223637Sbz 523223637Sbz /* Allocate IRQ resources. */ 524223637Sbz msixc = pci_msix_count(dev); 525223637Sbz msic = pci_msi_count(dev); 526223637Sbz if (bootverbose) { 527223637Sbz device_printf(dev, "MSIX count : %d\n", msixc); 528223637Sbz device_printf(dev, "MSI count : %d\n", msic); 529223637Sbz } 530223637Sbz 531171172Smlaier /* Prefer MSIX over MSI. */ 532171172Smlaier if (msix_disable == 0 || msi_disable == 0) { 533171172Smlaier if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && 534171172Smlaier pci_alloc_msix(dev, &msixc) == 0) { 535171172Smlaier if (msic == AGE_MSIX_MESSAGES) { 536171172Smlaier device_printf(dev, "Using %d MSIX messages.\n", 537171172Smlaier msixc); 538171172Smlaier sc->age_flags |= AGE_FLAG_MSIX; 539171172Smlaier sc->age_irq_spec = age_irq_spec_msix; 540171172Smlaier } else 541171172Smlaier pci_release_msi(dev); 542171172Smlaier } 543171172Smlaier if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && 544171172Smlaier msic == AGE_MSI_MESSAGES && 545171172Smlaier pci_alloc_msi(dev, &msic) == 0) { 546126353Smlaier if (msic == AGE_MSI_MESSAGES) { 547126353Smlaier device_printf(dev, "Using %d MSI messages.\n", 548126353Smlaier msic); 549126353Smlaier sc->age_flags |= AGE_FLAG_MSI; 550126353Smlaier sc->age_irq_spec = age_irq_spec_msi; 551126353Smlaier } else 552126353Smlaier pci_release_msi(dev); 553126353Smlaier } 554126353Smlaier } 555126353Smlaier 556126353Smlaier error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); 557126353Smlaier if (error != 0) { 558126353Smlaier device_printf(dev, "cannot allocate IRQ resources.\n"); 559126353Smlaier goto fail; 560126353Smlaier } 561126353Smlaier 562126353Smlaier 563126353Smlaier /* Get DMA parameters from PCIe device control register. */ 564126353Smlaier if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 565126353Smlaier sc->age_flags |= AGE_FLAG_PCIE; 566126353Smlaier burst = pci_read_config(dev, i + 0x08, 2); 567126353Smlaier /* Max read request size. */ 568126353Smlaier sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << 569126353Smlaier DMA_CFG_RD_BURST_SHIFT; 570126353Smlaier /* Max payload size. */ 571126353Smlaier sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << 572126353Smlaier DMA_CFG_WR_BURST_SHIFT; 573126353Smlaier if (bootverbose) { 574126353Smlaier device_printf(dev, "Read request size : %d bytes.\n", 575126353Smlaier 128 << ((burst >> 12) & 0x07)); 576130614Smlaier device_printf(dev, "TLP payload size : %d bytes.\n", 577171172Smlaier 128 << ((burst >> 5) & 0x07)); 578145840Smlaier } 579145840Smlaier } else { 580145840Smlaier sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 581145840Smlaier sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 582145840Smlaier } 583145840Smlaier 584145840Smlaier /* Create device sysctl node. */ 585145840Smlaier age_sysctl_node(sc); 586145840Smlaier 587130614Smlaier if ((error = age_dma_alloc(sc) != 0)) 588130614Smlaier goto fail; 589130614Smlaier 590130614Smlaier /* Load station address. */ 591130614Smlaier age_get_macaddr(sc); 592130614Smlaier 593130614Smlaier ifp = sc->age_ifp = if_alloc(IFT_ETHER); 594130614Smlaier if (ifp == NULL) { 595130614Smlaier device_printf(dev, "cannot allocate ifnet structure.\n"); 596130614Smlaier error = ENXIO; 597130614Smlaier goto fail; 598130614Smlaier } 599130614Smlaier 600130614Smlaier ifp->if_softc = sc; 601126353Smlaier if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 602130614Smlaier ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 603126353Smlaier ifp->if_ioctl = age_ioctl; 604126353Smlaier ifp->if_start = age_start; 605126353Smlaier ifp->if_init = age_init; 606126353Smlaier ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1; 607126353Smlaier IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 608126353Smlaier IFQ_SET_READY(&ifp->if_snd); 609126353Smlaier ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 610126353Smlaier ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO; 611126353Smlaier if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 612126353Smlaier sc->age_flags |= AGE_FLAG_PMCAP; 613126353Smlaier ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 614126353Smlaier } 615126353Smlaier ifp->if_capenable = ifp->if_capabilities; 616126353Smlaier 617126353Smlaier /* Set up MII bus. */ 618126353Smlaier error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange, 619126353Smlaier age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY, 620126353Smlaier 0); 621126353Smlaier if (error != 0) { 622126353Smlaier device_printf(dev, "attaching PHYs failed\n"); 623126353Smlaier goto fail; 624126353Smlaier } 625126353Smlaier 626126353Smlaier ether_ifattach(ifp, sc->age_eaddr); 627126353Smlaier 628126353Smlaier /* VLAN capability setup. */ 629126353Smlaier ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 630126353Smlaier IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 631126353Smlaier ifp->if_capenable = ifp->if_capabilities; 632126353Smlaier 633126353Smlaier /* Tell the upper layer(s) we support long frames. */ 634126353Smlaier ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 635126353Smlaier 636126353Smlaier /* Create local taskq. */ 637126353Smlaier sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, 638126353Smlaier taskqueue_thread_enqueue, &sc->age_tq); 639126353Smlaier if (sc->age_tq == NULL) { 640126353Smlaier device_printf(dev, "could not create taskqueue.\n"); 641126353Smlaier ether_ifdetach(ifp); 642126353Smlaier error = ENXIO; 643126353Smlaier goto fail; 644171172Smlaier } 645126353Smlaier taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", 646171172Smlaier device_get_nameunit(sc->age_dev)); 647126353Smlaier 648223637Sbz if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 649223637Sbz msic = AGE_MSIX_MESSAGES; 650223637Sbz else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 651223637Sbz msic = AGE_MSI_MESSAGES; 652223637Sbz else 653223637Sbz msic = 1; 654223637Sbz for (i = 0; i < msic; i++) { 655223637Sbz error = bus_setup_intr(dev, sc->age_irq[i], 656223637Sbz INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, 657223637Sbz &sc->age_intrhand[i]); 658223637Sbz if (error != 0) 659223637Sbz break; 660223637Sbz } 661126353Smlaier if (error != 0) { 662126353Smlaier device_printf(dev, "could not set up interrupt handler.\n"); 663126353Smlaier taskqueue_free(sc->age_tq); 664145840Smlaier sc->age_tq = NULL; 665126353Smlaier ether_ifdetach(ifp); 666126353Smlaier goto fail; 667126353Smlaier } 668126353Smlaier 669126353Smlaierfail: 670126353Smlaier if (error != 0) 671126353Smlaier age_detach(dev); 672126353Smlaier 673126353Smlaier return (error); 674126353Smlaier} 675126353Smlaier 676126353Smlaierstatic int 677126353Smlaierage_detach(device_t dev) 678126353Smlaier{ 679126353Smlaier struct age_softc *sc; 680126353Smlaier struct ifnet *ifp; 681126353Smlaier int i, msic; 682126353Smlaier 683126353Smlaier sc = device_get_softc(dev); 684126353Smlaier 685126353Smlaier ifp = sc->age_ifp; 686126353Smlaier if (device_is_attached(dev)) { 687126353Smlaier AGE_LOCK(sc); 688126353Smlaier sc->age_flags |= AGE_FLAG_DETACH; 689126353Smlaier age_stop(sc); 690126353Smlaier AGE_UNLOCK(sc); 691126353Smlaier callout_drain(&sc->age_tick_ch); 692126353Smlaier taskqueue_drain(sc->age_tq, &sc->age_int_task); 693126353Smlaier taskqueue_drain(taskqueue_swi, &sc->age_link_task); 694126353Smlaier ether_ifdetach(ifp); 695126353Smlaier } 696126353Smlaier 697126353Smlaier if (sc->age_tq != NULL) { 698126353Smlaier taskqueue_drain(sc->age_tq, &sc->age_int_task); 699126353Smlaier taskqueue_free(sc->age_tq); 700126353Smlaier sc->age_tq = NULL; 701126353Smlaier } 702126353Smlaier 703126353Smlaier if (sc->age_miibus != NULL) { 704126353Smlaier device_delete_child(dev, sc->age_miibus); 705126353Smlaier sc->age_miibus = NULL; 706126353Smlaier } 707126353Smlaier bus_generic_detach(dev); 708126353Smlaier age_dma_free(sc); 709126353Smlaier 710126353Smlaier if (ifp != NULL) { 711126353Smlaier if_free(ifp); 712126353Smlaier sc->age_ifp = NULL; 713126353Smlaier } 714126353Smlaier 715126353Smlaier if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 716126353Smlaier msic = AGE_MSIX_MESSAGES; 717126353Smlaier else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 718145840Smlaier msic = AGE_MSI_MESSAGES; 719126353Smlaier else 720126353Smlaier msic = 1; 721126353Smlaier for (i = 0; i < msic; i++) { 722126353Smlaier if (sc->age_intrhand[i] != NULL) { 723126353Smlaier bus_teardown_intr(dev, sc->age_irq[i], 724126353Smlaier sc->age_intrhand[i]); 725126353Smlaier sc->age_intrhand[i] = NULL; 726126353Smlaier } 727126353Smlaier } 728126353Smlaier 729126353Smlaier bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); 730126353Smlaier if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) 731126353Smlaier pci_release_msi(dev); 732126353Smlaier bus_release_resources(dev, sc->age_res_spec, sc->age_res); 733126353Smlaier mtx_destroy(&sc->age_mtx); 734126353Smlaier 735145840Smlaier return (0); 736145840Smlaier} 737145840Smlaier 738145840Smlaierstatic void 739145840Smlaierage_sysctl_node(struct age_softc *sc) 740145840Smlaier{ 741145840Smlaier int error; 742145840Smlaier 743145840Smlaier SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 744145840Smlaier SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 745145840Smlaier "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats, 746145840Smlaier "I", "Statistics"); 747145840Smlaier 748145840Smlaier SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 749145840Smlaier SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 750145840Smlaier "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0, 751145840Smlaier sysctl_hw_age_int_mod, "I", "age interrupt moderation"); 752145840Smlaier 753126353Smlaier /* Pull in device tunables. */ 754126353Smlaier sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 755126353Smlaier error = resource_int_value(device_get_name(sc->age_dev), 756126353Smlaier device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 757126353Smlaier if (error == 0) { 758126353Smlaier if (sc->age_int_mod < AGE_IM_TIMER_MIN || 759126353Smlaier sc->age_int_mod > AGE_IM_TIMER_MAX) { 760145840Smlaier device_printf(sc->age_dev, 761145840Smlaier "int_mod value out of range; using default: %d\n", 762145840Smlaier AGE_IM_TIMER_DEFAULT); 763145840Smlaier sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 764145840Smlaier } 765145840Smlaier } 766145840Smlaier 767145840Smlaier SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 768145840Smlaier SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 769223637Sbz "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->age_process_limit, 770141456Smlaier 0, sysctl_hw_age_proc_limit, "I", 771141456Smlaier "max number of Rx events to process"); 772141456Smlaier 773141456Smlaier /* Pull in device tunables. */ 774141490Smlaier sc->age_process_limit = AGE_PROC_DEFAULT; 775141456Smlaier error = resource_int_value(device_get_name(sc->age_dev), 776141490Smlaier device_get_unit(sc->age_dev), "process_limit", 777141456Smlaier &sc->age_process_limit); 778126353Smlaier if (error == 0) { 779126353Smlaier if (sc->age_process_limit < AGE_PROC_MIN || 780126353Smlaier sc->age_process_limit > AGE_PROC_MAX) { 781126353Smlaier device_printf(sc->age_dev, 782126353Smlaier "process_limit value out of range; " 783126353Smlaier "using default: %d\n", AGE_PROC_DEFAULT); 784126353Smlaier sc->age_process_limit = AGE_PROC_DEFAULT; 785126353Smlaier } 786126353Smlaier } 787126353Smlaier} 788126353Smlaier 789126353Smlaierstruct age_dmamap_arg { 790126353Smlaier bus_addr_t age_busaddr; 791126353Smlaier}; 792126353Smlaier 793126353Smlaierstatic void 794126353Smlaierage_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 795126353Smlaier{ 796126353Smlaier struct age_dmamap_arg *ctx; 797126353Smlaier 798126353Smlaier if (error != 0) 799126353Smlaier return; 800126353Smlaier 801126353Smlaier KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 802126353Smlaier 803126353Smlaier ctx = (struct age_dmamap_arg *)arg; 804126353Smlaier ctx->age_busaddr = segs[0].ds_addr; 805126353Smlaier} 806126353Smlaier 807126353Smlaier/* 808126353Smlaier * Attansic L1 controller have single register to specify high 809126353Smlaier * address part of DMA blocks. So all descriptor structures and 810126353Smlaier * DMA memory blocks should have the same high address of given 811126353Smlaier * 4GB address space(i.e. crossing 4GB boundary is not allowed). 812126353Smlaier */ 813126353Smlaierstatic int 814126353Smlaierage_check_boundary(struct age_softc *sc) 815126353Smlaier{ 816145840Smlaier bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 817145840Smlaier bus_addr_t cmb_block_end, smb_block_end; 818145840Smlaier 819145840Smlaier /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 820145840Smlaier tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 821145840Smlaier rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 822145840Smlaier rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 823145840Smlaier cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 824145840Smlaier smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 825145840Smlaier 826145840Smlaier if ((AGE_ADDR_HI(tx_ring_end) != 827145840Smlaier AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 828126353Smlaier (AGE_ADDR_HI(rx_ring_end) != 829126353Smlaier AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 830126353Smlaier (AGE_ADDR_HI(rr_ring_end) != 831126353Smlaier AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 832126353Smlaier (AGE_ADDR_HI(cmb_block_end) != 833126353Smlaier AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 834126353Smlaier (AGE_ADDR_HI(smb_block_end) != 835126353Smlaier AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 836126353Smlaier return (EFBIG); 837126353Smlaier 838126353Smlaier if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 839126353Smlaier (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 840126353Smlaier (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 841126353Smlaier (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 842126353Smlaier return (EFBIG); 843126353Smlaier 844126353Smlaier return (0); 845126353Smlaier} 846126353Smlaier 847126353Smlaierstatic int 848126353Smlaierage_dma_alloc(struct age_softc *sc) 849126353Smlaier{ 850126353Smlaier struct age_txdesc *txd; 851126353Smlaier struct age_rxdesc *rxd; 852126353Smlaier bus_addr_t lowaddr; 853126353Smlaier struct age_dmamap_arg ctx; 854126353Smlaier int error, i; 855126353Smlaier 856126353Smlaier lowaddr = BUS_SPACE_MAXADDR; 857126353Smlaier 858126353Smlaieragain: 859126353Smlaier /* Create parent ring/DMA block tag. */ 860223637Sbz error = bus_dma_tag_create( 861145840Smlaier bus_get_dma_tag(sc->age_dev), /* parent */ 862145840Smlaier 1, 0, /* alignment, boundary */ 863145840Smlaier lowaddr, /* lowaddr */ 864145840Smlaier BUS_SPACE_MAXADDR, /* highaddr */ 865145840Smlaier NULL, NULL, /* filter, filterarg */ 866145840Smlaier BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 867145840Smlaier 0, /* nsegments */ 868145840Smlaier BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 869126353Smlaier 0, /* flags */ 870126353Smlaier NULL, NULL, /* lockfunc, lockarg */ 871126353Smlaier &sc->age_cdata.age_parent_tag); 872126353Smlaier if (error != 0) { 873126353Smlaier device_printf(sc->age_dev, 874126353Smlaier "could not create parent DMA tag.\n"); 875126353Smlaier goto fail; 876126353Smlaier } 877126353Smlaier 878171172Smlaier /* Create tag for Tx ring. */ 879126353Smlaier error = bus_dma_tag_create( 880171172Smlaier sc->age_cdata.age_parent_tag, /* parent */ 881126353Smlaier AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 882126353Smlaier BUS_SPACE_MAXADDR, /* lowaddr */ 883126353Smlaier BUS_SPACE_MAXADDR, /* highaddr */ 884126353Smlaier NULL, NULL, /* filter, filterarg */ 885126353Smlaier AGE_TX_RING_SZ, /* maxsize */ 886126353Smlaier 1, /* nsegments */ 887126353Smlaier AGE_TX_RING_SZ, /* maxsegsize */ 888126353Smlaier 0, /* flags */ 889126353Smlaier NULL, NULL, /* lockfunc, lockarg */ 890171172Smlaier &sc->age_cdata.age_tx_ring_tag); 891126353Smlaier if (error != 0) { 892126353Smlaier device_printf(sc->age_dev, 893126353Smlaier "could not create Tx ring DMA tag.\n"); 894126353Smlaier goto fail; 895126353Smlaier } 896126353Smlaier 897126353Smlaier /* Create tag for Rx ring. */ 898126353Smlaier error = bus_dma_tag_create( 899126353Smlaier sc->age_cdata.age_parent_tag, /* parent */ 900126353Smlaier AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 901126353Smlaier BUS_SPACE_MAXADDR, /* lowaddr */ 902126353Smlaier BUS_SPACE_MAXADDR, /* highaddr */ 903126353Smlaier NULL, NULL, /* filter, filterarg */ 904126353Smlaier AGE_RX_RING_SZ, /* maxsize */ 905126353Smlaier 1, /* nsegments */ 906126353Smlaier AGE_RX_RING_SZ, /* maxsegsize */ 907126353Smlaier 0, /* flags */ 908171172Smlaier NULL, NULL, /* lockfunc, lockarg */ 909171172Smlaier &sc->age_cdata.age_rx_ring_tag); 910171172Smlaier if (error != 0) { 911171172Smlaier device_printf(sc->age_dev, 912126353Smlaier "could not create Rx ring DMA tag.\n"); 913126353Smlaier goto fail; 914171172Smlaier } 915126353Smlaier 916126353Smlaier /* Create tag for Rx return ring. */ 917126353Smlaier error = bus_dma_tag_create( 918171172Smlaier sc->age_cdata.age_parent_tag, /* parent */ 919126353Smlaier AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 920126353Smlaier BUS_SPACE_MAXADDR, /* lowaddr */ 921126353Smlaier BUS_SPACE_MAXADDR, /* highaddr */ 922126353Smlaier NULL, NULL, /* filter, filterarg */ 923223637Sbz AGE_RR_RING_SZ, /* maxsize */ 924126353Smlaier 1, /* nsegments */ 925126353Smlaier AGE_RR_RING_SZ, /* maxsegsize */ 926126353Smlaier 0, /* flags */ 927126353Smlaier NULL, NULL, /* lockfunc, lockarg */ 928126353Smlaier &sc->age_cdata.age_rr_ring_tag); 929126353Smlaier if (error != 0) { 930126353Smlaier device_printf(sc->age_dev, 931126353Smlaier "could not create Rx return ring DMA tag.\n"); 932126353Smlaier goto fail; 933126353Smlaier } 934126353Smlaier 935126353Smlaier /* Create tag for coalesing message block. */ 936126353Smlaier error = bus_dma_tag_create( 937126353Smlaier sc->age_cdata.age_parent_tag, /* parent */ 938126353Smlaier AGE_CMB_ALIGN, 0, /* alignment, boundary */ 939126353Smlaier BUS_SPACE_MAXADDR, /* lowaddr */ 940126353Smlaier BUS_SPACE_MAXADDR, /* highaddr */ 941126353Smlaier NULL, NULL, /* filter, filterarg */ 942126353Smlaier AGE_CMB_BLOCK_SZ, /* maxsize */ 943126353Smlaier 1, /* nsegments */ 944126353Smlaier AGE_CMB_BLOCK_SZ, /* maxsegsize */ 945126353Smlaier 0, /* flags */ 946126353Smlaier NULL, NULL, /* lockfunc, lockarg */ 947171172Smlaier &sc->age_cdata.age_cmb_block_tag); 948126353Smlaier if (error != 0) { 949126353Smlaier device_printf(sc->age_dev, 950171172Smlaier "could not create CMB DMA tag.\n"); 951126353Smlaier goto fail; 952126353Smlaier } 953126353Smlaier 954126353Smlaier /* Create tag for statistics message block. */ 955126353Smlaier error = bus_dma_tag_create( 956145840Smlaier sc->age_cdata.age_parent_tag, /* parent */ 957126353Smlaier AGE_SMB_ALIGN, 0, /* alignment, boundary */ 958126353Smlaier BUS_SPACE_MAXADDR, /* lowaddr */ 959126353Smlaier BUS_SPACE_MAXADDR, /* highaddr */ 960171172Smlaier NULL, NULL, /* filter, filterarg */ 961126353Smlaier AGE_SMB_BLOCK_SZ, /* maxsize */ 962126353Smlaier 1, /* nsegments */ 963126353Smlaier AGE_SMB_BLOCK_SZ, /* maxsegsize */ 964126353Smlaier 0, /* flags */ 965126353Smlaier NULL, NULL, /* lockfunc, lockarg */ 966126353Smlaier &sc->age_cdata.age_smb_block_tag); 967126353Smlaier if (error != 0) { 968126353Smlaier device_printf(sc->age_dev, 969126353Smlaier "could not create SMB DMA tag.\n"); 970126353Smlaier goto fail; 971126353Smlaier } 972126353Smlaier 973126353Smlaier /* Allocate DMA'able memory and load the DMA map. */ 974126353Smlaier error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 975126353Smlaier (void **)&sc->age_rdata.age_tx_ring, 976171172Smlaier BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 977126353Smlaier &sc->age_cdata.age_tx_ring_map); 978126353Smlaier if (error != 0) { 979126353Smlaier device_printf(sc->age_dev, 980126353Smlaier "could not allocate DMA'able memory for Tx ring.\n"); 981126353Smlaier goto fail; 982126353Smlaier } 983126353Smlaier ctx.age_busaddr = 0; 984171172Smlaier error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 985171172Smlaier sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 986171172Smlaier AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 987126353Smlaier if (error != 0 || ctx.age_busaddr == 0) { 988126353Smlaier device_printf(sc->age_dev, 989126353Smlaier "could not load DMA'able memory for Tx ring.\n"); 990126353Smlaier goto fail; 991126353Smlaier } 992126353Smlaier sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 993126353Smlaier /* Rx ring */ 994126353Smlaier error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 995126353Smlaier (void **)&sc->age_rdata.age_rx_ring, 996126353Smlaier BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 997126353Smlaier &sc->age_cdata.age_rx_ring_map); 998126353Smlaier if (error != 0) { 999126353Smlaier device_printf(sc->age_dev, 1000126353Smlaier "could not allocate DMA'able memory for Rx ring.\n"); 1001126353Smlaier goto fail; 1002126353Smlaier } 1003126353Smlaier ctx.age_busaddr = 0; 1004126353Smlaier error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 1005126353Smlaier sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 1006126353Smlaier AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 1007126353Smlaier if (error != 0 || ctx.age_busaddr == 0) { 1008126353Smlaier device_printf(sc->age_dev, 1009126353Smlaier "could not load DMA'able memory for Rx ring.\n"); 1010126353Smlaier goto fail; 1011126353Smlaier } 1012126353Smlaier sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 1013126353Smlaier /* Rx return ring */ 1014126353Smlaier error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 1015126353Smlaier (void **)&sc->age_rdata.age_rr_ring, 1016126353Smlaier BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1017126353Smlaier &sc->age_cdata.age_rr_ring_map); 1018126353Smlaier if (error != 0) { 1019126353Smlaier device_printf(sc->age_dev, 1020171172Smlaier "could not allocate DMA'able memory for Rx return ring.\n"); 1021126353Smlaier goto fail; 1022171172Smlaier } 1023126353Smlaier ctx.age_busaddr = 0; 1024171172Smlaier error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 1025126353Smlaier sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 1026126353Smlaier AGE_RR_RING_SZ, age_dmamap_cb, 1027126353Smlaier &ctx, 0); 1028171172Smlaier if (error != 0 || ctx.age_busaddr == 0) { 1029171172Smlaier device_printf(sc->age_dev, 1030126353Smlaier "could not load DMA'able memory for Rx return ring.\n"); 1031126353Smlaier goto fail; 1032126353Smlaier } 1033126353Smlaier sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 1034126353Smlaier /* CMB block */ 1035126353Smlaier error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 1036126353Smlaier (void **)&sc->age_rdata.age_cmb_block, 1037126353Smlaier BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1038126353Smlaier &sc->age_cdata.age_cmb_block_map); 1039126353Smlaier if (error != 0) { 1040126353Smlaier device_printf(sc->age_dev, 1041126353Smlaier "could not allocate DMA'able memory for CMB block.\n"); 1042126353Smlaier goto fail; 1043126353Smlaier } 1044126353Smlaier ctx.age_busaddr = 0; 1045126353Smlaier error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1046126353Smlaier sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1047126353Smlaier AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1048126353Smlaier if (error != 0 || ctx.age_busaddr == 0) { 1049126353Smlaier device_printf(sc->age_dev, 1050126353Smlaier "could not load DMA'able memory for CMB block.\n"); 1051126353Smlaier goto fail; 1052126353Smlaier } 1053126353Smlaier sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1054126353Smlaier /* SMB block */ 1055126353Smlaier error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1056126353Smlaier (void **)&sc->age_rdata.age_smb_block, 1057126353Smlaier BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1058126353Smlaier &sc->age_cdata.age_smb_block_map); 1059126353Smlaier if (error != 0) { 1060126353Smlaier device_printf(sc->age_dev, 1061126353Smlaier "could not allocate DMA'able memory for SMB block.\n"); 1062126353Smlaier goto fail; 1063126353Smlaier } 1064126353Smlaier ctx.age_busaddr = 0; 1065126353Smlaier error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1066126353Smlaier sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1067126353Smlaier AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1068126353Smlaier if (error != 0 || ctx.age_busaddr == 0) { 1069126353Smlaier device_printf(sc->age_dev, 1070126353Smlaier "could not load DMA'able memory for SMB block.\n"); 1071126353Smlaier goto fail; 1072126353Smlaier } 1073126353Smlaier sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1074126353Smlaier 1075126353Smlaier /* 1076126353Smlaier * All ring buffer and DMA blocks should have the same 1077126353Smlaier * high address part of 64bit DMA address space. 1078126353Smlaier */ 1079126353Smlaier if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1080126353Smlaier (error = age_check_boundary(sc)) != 0) { 1081126353Smlaier device_printf(sc->age_dev, "4GB boundary crossed, " 1082126353Smlaier "switching to 32bit DMA addressing mode.\n"); 1083126353Smlaier age_dma_free(sc); 1084126353Smlaier /* Limit DMA address space to 32bit and try again. */ 1085126353Smlaier lowaddr = BUS_SPACE_MAXADDR_32BIT; 1086126353Smlaier goto again; 1087126353Smlaier } 1088145840Smlaier 1089145840Smlaier /* 1090126353Smlaier * Create Tx/Rx buffer parent tag. 1091126353Smlaier * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1092126353Smlaier * so it needs separate parent DMA tag. 1093171172Smlaier * XXX 1094126353Smlaier * It seems enabling 64bit DMA causes data corruption. Limit 1095171172Smlaier * DMA address space to 32bit. 1096126353Smlaier */ 1097171172Smlaier error = bus_dma_tag_create( 1098126353Smlaier bus_get_dma_tag(sc->age_dev), /* parent */ 1099171172Smlaier 1, 0, /* alignment, boundary */ 1100126353Smlaier BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1101126353Smlaier BUS_SPACE_MAXADDR, /* highaddr */ 1102126353Smlaier NULL, NULL, /* filter, filterarg */ 1103126353Smlaier BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1104126353Smlaier 0, /* nsegments */ 1105126353Smlaier BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1106126353Smlaier 0, /* flags */ 1107126353Smlaier NULL, NULL, /* lockfunc, lockarg */ 1108126353Smlaier &sc->age_cdata.age_buffer_tag); 1109126353Smlaier if (error != 0) { 1110126353Smlaier device_printf(sc->age_dev, 1111126353Smlaier "could not create parent buffer DMA tag.\n"); 1112126353Smlaier goto fail; 1113145840Smlaier } 1114145840Smlaier 1115126353Smlaier /* Create tag for Tx buffers. */ 1116126353Smlaier error = bus_dma_tag_create( 1117126353Smlaier sc->age_cdata.age_buffer_tag, /* parent */ 1118126353Smlaier 1, 0, /* alignment, boundary */ 1119126353Smlaier BUS_SPACE_MAXADDR, /* lowaddr */ 1120126353Smlaier BUS_SPACE_MAXADDR, /* highaddr */ 1121126353Smlaier NULL, NULL, /* filter, filterarg */ 1122126353Smlaier AGE_TSO_MAXSIZE, /* maxsize */ 1123126353Smlaier AGE_MAXTXSEGS, /* nsegments */ 1124126353Smlaier AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1125126353Smlaier 0, /* flags */ 1126126353Smlaier NULL, NULL, /* lockfunc, lockarg */ 1127126353Smlaier &sc->age_cdata.age_tx_tag); 1128126353Smlaier if (error != 0) { 1129126353Smlaier device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1130126353Smlaier goto fail; 1131126353Smlaier } 1132126353Smlaier 1133126353Smlaier /* Create tag for Rx buffers. */ 1134126353Smlaier error = bus_dma_tag_create( 1135126353Smlaier sc->age_cdata.age_buffer_tag, /* parent */ 1136126353Smlaier 1, 0, /* alignment, boundary */ 1137126353Smlaier BUS_SPACE_MAXADDR, /* lowaddr */ 1138126353Smlaier BUS_SPACE_MAXADDR, /* highaddr */ 1139126353Smlaier NULL, NULL, /* filter, filterarg */ 1140126353Smlaier MCLBYTES, /* maxsize */ 1141126353Smlaier 1, /* nsegments */ 1142126353Smlaier MCLBYTES, /* maxsegsize */ 1143126353Smlaier 0, /* flags */ 1144126353Smlaier NULL, NULL, /* lockfunc, lockarg */ 1145126353Smlaier &sc->age_cdata.age_rx_tag); 1146126353Smlaier if (error != 0) { 1147126353Smlaier device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1148126353Smlaier goto fail; 1149126353Smlaier } 1150126353Smlaier 1151126353Smlaier /* Create DMA maps for Tx buffers. */ 1152126353Smlaier for (i = 0; i < AGE_TX_RING_CNT; i++) { 1153126353Smlaier txd = &sc->age_cdata.age_txdesc[i]; 1154126353Smlaier txd->tx_m = NULL; 1155126353Smlaier txd->tx_dmamap = NULL; 1156126353Smlaier error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1157126353Smlaier &txd->tx_dmamap); 1158126353Smlaier if (error != 0) { 1159171172Smlaier device_printf(sc->age_dev, 1160126353Smlaier "could not create Tx dmamap.\n"); 1161171172Smlaier goto fail; 1162126353Smlaier } 1163126353Smlaier } 1164126353Smlaier /* Create DMA maps for Rx buffers. */ 1165126353Smlaier if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1166126353Smlaier &sc->age_cdata.age_rx_sparemap)) != 0) { 1167126353Smlaier device_printf(sc->age_dev, 1168126353Smlaier "could not create spare Rx dmamap.\n"); 1169126353Smlaier goto fail; 1170126353Smlaier } 1171126353Smlaier for (i = 0; i < AGE_RX_RING_CNT; i++) { 1172126353Smlaier rxd = &sc->age_cdata.age_rxdesc[i]; 1173126353Smlaier rxd->rx_m = NULL; 1174126353Smlaier rxd->rx_dmamap = NULL; 1175126353Smlaier error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1176126353Smlaier &rxd->rx_dmamap); 1177126353Smlaier if (error != 0) { 1178126353Smlaier device_printf(sc->age_dev, 1179171172Smlaier "could not create Rx dmamap.\n"); 1180171172Smlaier goto fail; 1181171172Smlaier } 1182171172Smlaier } 1183171172Smlaier 1184171172Smlaierfail: 1185171172Smlaier return (error); 1186171172Smlaier} 1187171172Smlaier 1188171172Smlaierstatic void 1189171172Smlaierage_dma_free(struct age_softc *sc) 1190126353Smlaier{ 1191126353Smlaier struct age_txdesc *txd; 1192126353Smlaier struct age_rxdesc *rxd; 1193126353Smlaier int i; 1194126353Smlaier 1195126353Smlaier /* Tx buffers */ 1196126353Smlaier if (sc->age_cdata.age_tx_tag != NULL) { 1197126353Smlaier for (i = 0; i < AGE_TX_RING_CNT; i++) { 1198126353Smlaier txd = &sc->age_cdata.age_txdesc[i]; 1199126353Smlaier if (txd->tx_dmamap != NULL) { 1200126353Smlaier bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1201126353Smlaier txd->tx_dmamap); 1202126353Smlaier txd->tx_dmamap = NULL; 1203126353Smlaier } 1204126353Smlaier } 1205126353Smlaier bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1206126353Smlaier sc->age_cdata.age_tx_tag = NULL; 1207126353Smlaier } 1208126353Smlaier /* Rx buffers */ 1209126353Smlaier if (sc->age_cdata.age_rx_tag != NULL) { 1210126353Smlaier for (i = 0; i < AGE_RX_RING_CNT; i++) { 1211126353Smlaier rxd = &sc->age_cdata.age_rxdesc[i]; 1212126353Smlaier if (rxd->rx_dmamap != NULL) { 1213126353Smlaier bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1214126353Smlaier rxd->rx_dmamap); 1215223637Sbz rxd->rx_dmamap = NULL; 1216126353Smlaier } 1217126353Smlaier } 1218126353Smlaier if (sc->age_cdata.age_rx_sparemap != NULL) { 1219126353Smlaier bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1220126353Smlaier sc->age_cdata.age_rx_sparemap); 1221126353Smlaier sc->age_cdata.age_rx_sparemap = NULL; 1222126353Smlaier } 1223126353Smlaier bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1224126353Smlaier sc->age_cdata.age_rx_tag = NULL; 1225126353Smlaier } 1226126353Smlaier /* Tx ring. */ 1227126353Smlaier if (sc->age_cdata.age_tx_ring_tag != NULL) { 1228126353Smlaier if (sc->age_cdata.age_tx_ring_map != NULL) 1229126353Smlaier bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1230126353Smlaier sc->age_cdata.age_tx_ring_map); 1231126353Smlaier if (sc->age_cdata.age_tx_ring_map != NULL && 1232126353Smlaier sc->age_rdata.age_tx_ring != NULL) 1233126353Smlaier bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1234126353Smlaier sc->age_rdata.age_tx_ring, 1235126353Smlaier sc->age_cdata.age_tx_ring_map); 1236126353Smlaier sc->age_rdata.age_tx_ring = NULL; 1237126353Smlaier sc->age_cdata.age_tx_ring_map = NULL; 1238126353Smlaier bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1239126353Smlaier sc->age_cdata.age_tx_ring_tag = NULL; 1240126353Smlaier } 1241126353Smlaier /* Rx ring. */ 1242126353Smlaier if (sc->age_cdata.age_rx_ring_tag != NULL) { 1243126353Smlaier if (sc->age_cdata.age_rx_ring_map != NULL) 1244126353Smlaier bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1245126353Smlaier sc->age_cdata.age_rx_ring_map); 1246126353Smlaier if (sc->age_cdata.age_rx_ring_map != NULL && 1247126353Smlaier sc->age_rdata.age_rx_ring != NULL) 1248126353Smlaier bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1249126353Smlaier sc->age_rdata.age_rx_ring, 1250126353Smlaier sc->age_cdata.age_rx_ring_map); 1251171172Smlaier sc->age_rdata.age_rx_ring = NULL; 1252171172Smlaier sc->age_cdata.age_rx_ring_map = NULL; 1253126353Smlaier bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1254126353Smlaier sc->age_cdata.age_rx_ring_tag = NULL; 1255126353Smlaier } 1256126353Smlaier /* Rx return ring. */ 1257126353Smlaier if (sc->age_cdata.age_rr_ring_tag != NULL) { 1258126353Smlaier if (sc->age_cdata.age_rr_ring_map != NULL) 1259126353Smlaier bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1260126353Smlaier sc->age_cdata.age_rr_ring_map); 1261126353Smlaier if (sc->age_cdata.age_rr_ring_map != NULL && 1262126353Smlaier sc->age_rdata.age_rr_ring != NULL) 1263126353Smlaier bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1264126353Smlaier sc->age_rdata.age_rr_ring, 1265126353Smlaier sc->age_cdata.age_rr_ring_map); 1266126353Smlaier sc->age_rdata.age_rr_ring = NULL; 1267126353Smlaier sc->age_cdata.age_rr_ring_map = NULL; 1268126353Smlaier bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1269126353Smlaier sc->age_cdata.age_rr_ring_tag = NULL; 1270126353Smlaier } 1271126353Smlaier /* CMB block */ 1272126353Smlaier if (sc->age_cdata.age_cmb_block_tag != NULL) { 1273126353Smlaier if (sc->age_cdata.age_cmb_block_map != NULL) 1274126353Smlaier bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1275126353Smlaier sc->age_cdata.age_cmb_block_map); 1276126353Smlaier if (sc->age_cdata.age_cmb_block_map != NULL && 1277126353Smlaier sc->age_rdata.age_cmb_block != NULL) 1278126353Smlaier bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1279126353Smlaier sc->age_rdata.age_cmb_block, 1280126353Smlaier sc->age_cdata.age_cmb_block_map); 1281126353Smlaier sc->age_rdata.age_cmb_block = NULL; 1282126353Smlaier sc->age_cdata.age_cmb_block_map = NULL; 1283126353Smlaier bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1284126353Smlaier sc->age_cdata.age_cmb_block_tag = NULL; 1285126353Smlaier } 1286126353Smlaier /* SMB block */ 1287145840Smlaier if (sc->age_cdata.age_smb_block_tag != NULL) { 1288126353Smlaier if (sc->age_cdata.age_smb_block_map != NULL) 1289126353Smlaier bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1290150673Smlaier sc->age_cdata.age_smb_block_map); 1291145840Smlaier if (sc->age_cdata.age_smb_block_map != NULL && 1292171172Smlaier sc->age_rdata.age_smb_block != NULL) 1293171172Smlaier bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1294171172Smlaier sc->age_rdata.age_smb_block, 1295171172Smlaier sc->age_cdata.age_smb_block_map); 1296171172Smlaier sc->age_rdata.age_smb_block = NULL; 1297171172Smlaier sc->age_cdata.age_smb_block_map = NULL; 1298126353Smlaier bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1299171172Smlaier sc->age_cdata.age_smb_block_tag = NULL; 1300223637Sbz } 1301171172Smlaier 1302171172Smlaier if (sc->age_cdata.age_buffer_tag != NULL) { 1303126353Smlaier bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1304126353Smlaier sc->age_cdata.age_buffer_tag = NULL; 1305171172Smlaier } 1306171172Smlaier if (sc->age_cdata.age_parent_tag != NULL) { 1307171172Smlaier bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1308171172Smlaier sc->age_cdata.age_parent_tag = NULL; 1309171172Smlaier } 1310171172Smlaier} 1311171172Smlaier 1312171172Smlaier/* 1313171172Smlaier * Make sure the interface is stopped at reboot time. 1314126353Smlaier */ 1315171172Smlaierstatic int 1316171172Smlaierage_shutdown(device_t dev) 1317171172Smlaier{ 1318171172Smlaier 1319171172Smlaier return (age_suspend(dev)); 1320171172Smlaier} 1321171172Smlaier 1322171172Smlaierstatic void 1323171172Smlaierage_setwol(struct age_softc *sc) 1324171172Smlaier{ 1325171172Smlaier struct ifnet *ifp; 1326171172Smlaier struct mii_data *mii; 1327171172Smlaier uint32_t reg, pmcs; 1328171172Smlaier uint16_t pmstat; 1329126353Smlaier int aneg, i, pmc; 1330171172Smlaier 1331126353Smlaier AGE_LOCK_ASSERT(sc); 1332126353Smlaier 1333171172Smlaier if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) { 1334171172Smlaier CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1335171172Smlaier /* 1336126353Smlaier * No PME capability, PHY power down. 1337171172Smlaier * XXX 1338171172Smlaier * Due to an unknown reason powering down PHY resulted 1339171172Smlaier * in unexpected results such as inaccessbility of 1340171172Smlaier * hardware of freshly rebooted system. Disable 1341171172Smlaier * powering down PHY until I got more information for 1342171172Smlaier * Attansic/Atheros PHY hardwares. 1343171172Smlaier */ 1344171172Smlaier#ifdef notyet 1345171172Smlaier age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1346171172Smlaier MII_BMCR, BMCR_PDOWN); 1347171172Smlaier#endif 1348171172Smlaier return; 1349171172Smlaier } 1350171172Smlaier 1351171172Smlaier ifp = sc->age_ifp; 1352171172Smlaier if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1353171172Smlaier /* 1354171172Smlaier * Note, this driver resets the link speed to 10/100Mbps with 1355171172Smlaier * auto-negotiation but we don't know whether that operation 1356171172Smlaier * would succeed or not as it have no control after powering 1357171172Smlaier * off. If the renegotiation fail WOL may not work. Running 1358171172Smlaier * at 1Gbps will draw more power than 375mA at 3.3V which is 1359171172Smlaier * specified in PCI specification and that would result in 1360171172Smlaier * complete shutdowning power to ethernet controller. 1361171172Smlaier * 1362171172Smlaier * TODO 1363171172Smlaier * Save current negotiated media speed/duplex/flow-control 1364171172Smlaier * to softc and restore the same link again after resuming. 1365171172Smlaier * PHY handling such as power down/resetting to 100Mbps 1366171172Smlaier * may be better handled in suspend method in phy driver. 1367171172Smlaier */ 1368171172Smlaier mii = device_get_softc(sc->age_miibus); 1369171172Smlaier mii_pollstat(mii); 1370126353Smlaier aneg = 0; 1371171172Smlaier if ((mii->mii_media_status & IFM_AVALID) != 0) { 1372171172Smlaier switch IFM_SUBTYPE(mii->mii_media_active) { 1373126353Smlaier case IFM_10_T: 1374126353Smlaier case IFM_100_TX: 1375126353Smlaier goto got_link; 1376126353Smlaier case IFM_1000_T: 1377126353Smlaier aneg++; 1378126353Smlaier default: 1379126353Smlaier break; 1380126353Smlaier } 1381126353Smlaier } 1382126353Smlaier age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1383126353Smlaier MII_100T2CR, 0); 1384126353Smlaier age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1385126353Smlaier MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1386126353Smlaier ANAR_10 | ANAR_CSMA); 1387126353Smlaier age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1388126353Smlaier MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1389126353Smlaier DELAY(1000); 1390126353Smlaier if (aneg != 0) { 1391126353Smlaier /* Poll link state until age(4) get a 10/100 link. */ 1392171172Smlaier for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1393171172Smlaier mii_pollstat(mii); 1394171172Smlaier if ((mii->mii_media_status & IFM_AVALID) != 0) { 1395171172Smlaier switch (IFM_SUBTYPE( 1396171172Smlaier mii->mii_media_active)) { 1397126353Smlaier case IFM_10_T: 1398171172Smlaier case IFM_100_TX: 1399171172Smlaier age_mac_config(sc); 1400126353Smlaier goto got_link; 1401126353Smlaier default: 1402126353Smlaier break; 1403126353Smlaier } 1404126353Smlaier } 1405126353Smlaier AGE_UNLOCK(sc); 1406126353Smlaier pause("agelnk", hz); 1407171172Smlaier AGE_LOCK(sc); 1408171172Smlaier } 1409171172Smlaier if (i == MII_ANEGTICKS_GIGE) 1410171172Smlaier device_printf(sc->age_dev, 1411171172Smlaier "establishing link failed, " 1412126353Smlaier "WOL may not work!"); 1413126353Smlaier } 1414126353Smlaier /* 1415126353Smlaier * No link, force MAC to have 100Mbps, full-duplex link. 1416171172Smlaier * This is the last resort and may/may not work. 1417171172Smlaier */ 1418171172Smlaier mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1419171172Smlaier mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1420171172Smlaier age_mac_config(sc); 1421171172Smlaier } 1422171172Smlaier 1423171172Smlaiergot_link: 1424240233Sglebius pmcs = 0; 1425171172Smlaier if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1426171172Smlaier pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1427171172Smlaier CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1428171172Smlaier reg = CSR_READ_4(sc, AGE_MAC_CFG); 1429171172Smlaier reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1430171172Smlaier reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1431171172Smlaier if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1432171172Smlaier reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1433126353Smlaier if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1434126353Smlaier reg |= MAC_CFG_RX_ENB; 1435126353Smlaier CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1436126353Smlaier } 1437126353Smlaier 1438126353Smlaier /* Request PME. */ 1439171172Smlaier pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1440126353Smlaier pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1441171172Smlaier if ((ifp->if_capenable & IFCAP_WOL) != 0) 1442171172Smlaier pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1443171172Smlaier pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1444171172Smlaier#ifdef notyet 1445171172Smlaier /* See above for powering down PHY issues. */ 1446171172Smlaier if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1447171172Smlaier /* No WOL, PHY power down. */ 1448126353Smlaier age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1449126353Smlaier MII_BMCR, BMCR_PDOWN); 1450126353Smlaier } 1451126353Smlaier#endif 1452126353Smlaier} 1453171172Smlaier 1454126353Smlaierstatic int 1455126353Smlaierage_suspend(device_t dev) 1456126353Smlaier{ 1457126353Smlaier struct age_softc *sc; 1458126353Smlaier 1459126353Smlaier sc = device_get_softc(dev); 1460126353Smlaier 1461126353Smlaier AGE_LOCK(sc); 1462126353Smlaier age_stop(sc); 1463126353Smlaier age_setwol(sc); 1464250604Sjoel AGE_UNLOCK(sc); 1465126353Smlaier 1466171172Smlaier return (0); 1467171172Smlaier} 1468171172Smlaier 1469171172Smlaierstatic int 1470171172Smlaierage_resume(device_t dev) 1471126353Smlaier{ 1472126353Smlaier struct age_softc *sc; 1473126353Smlaier struct ifnet *ifp; 1474126353Smlaier 1475126353Smlaier sc = device_get_softc(dev); 1476223637Sbz 1477223637Sbz AGE_LOCK(sc); 1478126353Smlaier age_phy_reset(sc); 1479145840Smlaier ifp = sc->age_ifp; 1480126353Smlaier if ((ifp->if_flags & IFF_UP) != 0) 1481126353Smlaier age_init_locked(sc); 1482126353Smlaier 1483126353Smlaier AGE_UNLOCK(sc); 1484171172Smlaier 1485171172Smlaier return (0); 1486171172Smlaier} 1487171172Smlaier 1488171172Smlaierstatic int 1489126353Smlaierage_encap(struct age_softc *sc, struct mbuf **m_head) 1490126353Smlaier{ 1491126353Smlaier struct age_txdesc *txd, *txd_last; 1492223637Sbz struct tx_desc *desc; 1493223637Sbz struct mbuf *m; 1494223637Sbz struct ip *ip; 1495223637Sbz struct tcphdr *tcp; 1496223637Sbz bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1497223637Sbz bus_dmamap_t map; 1498223637Sbz uint32_t cflags, hdrlen, ip_off, poff, vtag; 1499126353Smlaier int error, i, nsegs, prod, si; 1500223637Sbz 1501223637Sbz AGE_LOCK_ASSERT(sc); 1502126353Smlaier 1503126353Smlaier M_ASSERTPKTHDR((*m_head)); 1504126353Smlaier 1505126353Smlaier m = *m_head; 1506126353Smlaier ip = NULL; 1507130614Smlaier tcp = NULL; 1508223637Sbz cflags = vtag = 0; 1509130614Smlaier ip_off = poff = 0; 1510130614Smlaier if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1511126353Smlaier /* 1512126353Smlaier * L1 requires offset of TCP/UDP payload in its Tx 1513130614Smlaier * descriptor to perform hardware Tx checksum offload. 1514130614Smlaier * Additionally, TSO requires IP/TCP header size and 1515130614Smlaier * modification of IP/TCP header in order to make TSO 1516130614Smlaier * engine work. This kind of operation takes many CPU 1517130614Smlaier * cycles on FreeBSD so fast host CPU is needed to get 1518126353Smlaier * smooth TSO performance. 1519126353Smlaier */ 1520126353Smlaier struct ether_header *eh; 1521126353Smlaier 1522126353Smlaier if (M_WRITABLE(m) == 0) { 1523130614Smlaier /* Get a writable copy. */ 1524130614Smlaier m = m_dup(*m_head, M_DONTWAIT); 1525126353Smlaier /* Release original mbufs. */ 1526126353Smlaier m_freem(*m_head); 1527126353Smlaier if (m == NULL) { 1528126353Smlaier *m_head = NULL; 1529126353Smlaier return (ENOBUFS); 1530126353Smlaier } 1531126353Smlaier *m_head = m; 1532126353Smlaier } 1533126353Smlaier ip_off = sizeof(struct ether_header); 1534126353Smlaier m = m_pullup(m, ip_off); 1535126353Smlaier if (m == NULL) { 1536126353Smlaier *m_head = NULL; 1537126353Smlaier return (ENOBUFS); 1538126353Smlaier } 1539126353Smlaier eh = mtod(m, struct ether_header *); 1540126353Smlaier /* 1541126353Smlaier * Check if hardware VLAN insertion is off. 1542126353Smlaier * Additional check for LLC/SNAP frame? 1543171172Smlaier */ 1544171172Smlaier if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1545171172Smlaier ip_off = sizeof(struct ether_vlan_header); 1546171172Smlaier m = m_pullup(m, ip_off); 1547130614Smlaier if (m == NULL) { 1548171172Smlaier *m_head = NULL; 1549171172Smlaier return (ENOBUFS); 1550126353Smlaier } 1551126353Smlaier } 1552171172Smlaier m = m_pullup(m, ip_off + sizeof(struct ip)); 1553171172Smlaier if (m == NULL) { 1554171172Smlaier *m_head = NULL; 1555171172Smlaier return (ENOBUFS); 1556130614Smlaier } 1557126353Smlaier ip = (struct ip *)(mtod(m, char *) + ip_off); 1558126353Smlaier poff = ip_off + (ip->ip_hl << 2); 1559130614Smlaier if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1560130614Smlaier m = m_pullup(m, poff + sizeof(struct tcphdr)); 1561171172Smlaier if (m == NULL) { 1562130614Smlaier *m_head = NULL; 1563171172Smlaier return (ENOBUFS); 1564126353Smlaier } 1565171172Smlaier tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1566126353Smlaier m = m_pullup(m, poff + (tcp->th_off << 2)); 1567171172Smlaier if (m == NULL) { 1568126353Smlaier *m_head = NULL; 1569171172Smlaier return (ENOBUFS); 1570126353Smlaier } 1571126353Smlaier /* 1572126353Smlaier * L1 requires IP/TCP header size and offset as 1573126353Smlaier * well as TCP pseudo checksum which complicates 1574126353Smlaier * TSO configuration. I guess this comes from the 1575126353Smlaier * adherence to Microsoft NDIS Large Send 1576126353Smlaier * specification which requires insertion of 1577126353Smlaier * pseudo checksum by upper stack. The pseudo 1578126353Smlaier * checksum that NDIS refers to doesn't include 1579126353Smlaier * TCP payload length so age(4) should recompute 1580126353Smlaier * the pseudo checksum here. Hopefully this wouldn't 1581126353Smlaier * be much burden on modern CPUs. 1582126353Smlaier * Reset IP checksum and recompute TCP pseudo 1583126353Smlaier * checksum as NDIS specification said. 1584126353Smlaier */ 1585171172Smlaier ip = (struct ip *)(mtod(m, char *) + ip_off); 1586126353Smlaier tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1587171172Smlaier ip->ip_sum = 0; 1588126353Smlaier tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1589171172Smlaier ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1590126353Smlaier } 1591126353Smlaier *m_head = m; 1592126353Smlaier } 1593171172Smlaier 1594126353Smlaier si = prod = sc->age_cdata.age_tx_prod; 1595126353Smlaier txd = &sc->age_cdata.age_txdesc[prod]; 1596126353Smlaier txd_last = txd; 1597171172Smlaier map = txd->tx_dmamap; 1598126353Smlaier 1599126353Smlaier error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1600126353Smlaier *m_head, txsegs, &nsegs, 0); 1601126353Smlaier if (error == EFBIG) { 1602126353Smlaier m = m_collapse(*m_head, M_DONTWAIT, AGE_MAXTXSEGS); 1603126353Smlaier if (m == NULL) { 1604126353Smlaier m_freem(*m_head); 1605126353Smlaier *m_head = NULL; 1606126353Smlaier return (ENOMEM); 1607126353Smlaier } 1608126353Smlaier *m_head = m; 1609126353Smlaier error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1610126353Smlaier *m_head, txsegs, &nsegs, 0); 1611126353Smlaier if (error != 0) { 1612126353Smlaier m_freem(*m_head); 1613126353Smlaier *m_head = NULL; 1614126353Smlaier return (error); 1615126353Smlaier } 1616126353Smlaier } else if (error != 0) 1617126353Smlaier return (error); 1618126353Smlaier if (nsegs == 0) { 1619126353Smlaier m_freem(*m_head); 1620126353Smlaier *m_head = NULL; 1621126353Smlaier return (EIO); 1622126353Smlaier } 1623126353Smlaier 1624126353Smlaier /* Check descriptor overrun. */ 1625126353Smlaier if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1626126353Smlaier bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1627126353Smlaier return (ENOBUFS); 1628126353Smlaier } 1629126353Smlaier 1630171172Smlaier m = *m_head; 1631126353Smlaier /* Configure VLAN hardware tag insertion. */ 1632126353Smlaier if ((m->m_flags & M_VLANTAG) != 0) { 1633126353Smlaier vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1634126353Smlaier vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1635126353Smlaier cflags |= AGE_TD_INSERT_VLAN_TAG; 1636126353Smlaier } 1637126353Smlaier 1638126353Smlaier desc = NULL; 1639126353Smlaier i = 0; 1640171172Smlaier if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1641126353Smlaier /* Request TSO and set MSS. */ 1642126353Smlaier cflags |= AGE_TD_TSO_IPV4; 1643126353Smlaier cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1644126353Smlaier cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << 1645126353Smlaier AGE_TD_TSO_MSS_SHIFT); 1646171172Smlaier /* Set IP/TCP header size. */ 1647126353Smlaier cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; 1648171172Smlaier cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; 1649171172Smlaier /* 1650171172Smlaier * L1 requires the first buffer should only hold IP/TCP 1651171172Smlaier * header data. TCP payload should be handled in other 1652171172Smlaier * descriptors. 1653126353Smlaier */ 1654171172Smlaier hdrlen = poff + (tcp->th_off << 2); 1655126353Smlaier desc = &sc->age_rdata.age_tx_ring[prod]; 1656171172Smlaier desc->addr = htole64(txsegs[0].ds_addr); 1657126353Smlaier desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag); 1658171172Smlaier desc->flags = htole32(cflags); 1659126353Smlaier sc->age_cdata.age_tx_cnt++; 1660171172Smlaier AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1661171172Smlaier if (m->m_len - hdrlen > 0) { 1662223637Sbz /* Handle remaining payload of the 1st fragment. */ 1663171172Smlaier desc = &sc->age_rdata.age_tx_ring[prod]; 1664126353Smlaier desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 1665126353Smlaier desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) | 1666126353Smlaier vtag); 1667126353Smlaier desc->flags = htole32(cflags); 1668126353Smlaier sc->age_cdata.age_tx_cnt++; 1669126353Smlaier AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1670171172Smlaier } 1671126353Smlaier /* Handle remaining fragments. */ 1672126353Smlaier i = 1; 1673126353Smlaier } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1674126353Smlaier /* Configure Tx IP/TCP/UDP checksum offload. */ 1675126353Smlaier cflags |= AGE_TD_CSUM; 1676126353Smlaier if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1677126353Smlaier cflags |= AGE_TD_TCPCSUM; 1678171172Smlaier if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1679171172Smlaier cflags |= AGE_TD_UDPCSUM; 1680171172Smlaier /* Set checksum start offset. */ 1681171172Smlaier cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1682171172Smlaier /* Set checksum insertion position of TCP/UDP. */ 1683171172Smlaier cflags |= ((poff + m->m_pkthdr.csum_data) << 1684171172Smlaier AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1685171172Smlaier } 1686171172Smlaier for (; i < nsegs; i++) { 1687171172Smlaier desc = &sc->age_rdata.age_tx_ring[prod]; 1688171172Smlaier desc->addr = htole64(txsegs[i].ds_addr); 1689171172Smlaier desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1690171172Smlaier desc->flags = htole32(cflags); 1691171172Smlaier sc->age_cdata.age_tx_cnt++; 1692171172Smlaier AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1693171172Smlaier } 1694171172Smlaier /* Update producer index. */ 1695171172Smlaier sc->age_cdata.age_tx_prod = prod; 1696171172Smlaier 1697171172Smlaier /* Set EOP on the last descriptor. */ 1698171172Smlaier prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1699171172Smlaier desc = &sc->age_rdata.age_tx_ring[prod]; 1700171172Smlaier desc->flags |= htole32(AGE_TD_EOP); 1701171172Smlaier 1702171172Smlaier /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ 1703171172Smlaier if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1704171172Smlaier desc = &sc->age_rdata.age_tx_ring[si]; 1705171172Smlaier desc->flags |= htole32(AGE_TD_TSO_HDR); 1706171172Smlaier } 1707171172Smlaier 1708171172Smlaier /* Swap dmamap of the first and the last. */ 1709171172Smlaier txd = &sc->age_cdata.age_txdesc[prod]; 1710126353Smlaier map = txd_last->tx_dmamap; 1711126353Smlaier txd_last->tx_dmamap = txd->tx_dmamap; 1712145840Smlaier txd->tx_dmamap = map; 1713145840Smlaier txd->tx_m = m; 1714145840Smlaier 1715145840Smlaier /* Sync descriptors. */ 1716126353Smlaier bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1717126353Smlaier bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1718145840Smlaier sc->age_cdata.age_tx_ring_map, 1719145840Smlaier BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1720145840Smlaier 1721145840Smlaier return (0); 1722145840Smlaier} 1723145840Smlaier 1724126353Smlaierstatic void 1725171172Smlaierage_start(struct ifnet *ifp) 1726171172Smlaier{ 1727171172Smlaier struct age_softc *sc; 1728171172Smlaier 1729171172Smlaier sc = ifp->if_softc; 1730171172Smlaier AGE_LOCK(sc); 1731171172Smlaier age_start_locked(ifp); 1732171172Smlaier AGE_UNLOCK(sc); 1733171172Smlaier} 1734171172Smlaier 1735171172Smlaierstatic void 1736171172Smlaierage_start_locked(struct ifnet *ifp) 1737171172Smlaier{ 1738171172Smlaier struct age_softc *sc; 1739171172Smlaier struct mbuf *m_head; 1740171172Smlaier int enq; 1741171172Smlaier 1742171172Smlaier sc = ifp->if_softc; 1743171172Smlaier 1744171172Smlaier AGE_LOCK_ASSERT(sc); 1745126353Smlaier 1746169844Sdhartmei if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1747169844Sdhartmei IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) 1748126353Smlaier return; 1749126353Smlaier 1750126353Smlaier for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1751126353Smlaier IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1752126353Smlaier if (m_head == NULL) 1753169844Sdhartmei break; 1754126353Smlaier /* 1755126353Smlaier * Pack the data into the transmit ring. If we 1756126353Smlaier * don't have room, set the OACTIVE flag and wait 1757126353Smlaier * for the NIC to drain the ring. 1758126353Smlaier */ 1759126353Smlaier if (age_encap(sc, &m_head)) { 1760171172Smlaier if (m_head == NULL) 1761126353Smlaier break; 1762126353Smlaier IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1763126353Smlaier ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1764126353Smlaier break; 1765126353Smlaier } 1766126353Smlaier 1767126353Smlaier enq++; 1768126353Smlaier /* 1769126353Smlaier * If there's a BPF listener, bounce a copy of this frame 1770126353Smlaier * to him. 1771126353Smlaier */ 1772126353Smlaier ETHER_BPF_MTAP(ifp, m_head); 1773126353Smlaier } 1774126353Smlaier 1775126353Smlaier if (enq > 0) { 1776126353Smlaier /* Update mbox. */ 1777126353Smlaier AGE_COMMIT_MBOX(sc); 1778126353Smlaier /* Set a timeout in case the chip goes out to lunch. */ 1779126353Smlaier sc->age_watchdog_timer = AGE_TX_TIMEOUT; 1780126353Smlaier } 1781126353Smlaier} 1782126353Smlaier 1783126353Smlaierstatic void 1784126353Smlaierage_watchdog(struct age_softc *sc) 1785126353Smlaier{ 1786126353Smlaier struct ifnet *ifp; 1787126353Smlaier 1788126353Smlaier AGE_LOCK_ASSERT(sc); 1789171172Smlaier 1790126353Smlaier if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) 1791126353Smlaier return; 1792126353Smlaier 1793126353Smlaier ifp = sc->age_ifp; 1794126353Smlaier if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1795171172Smlaier if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); 1796126353Smlaier ifp->if_oerrors++; 1797171172Smlaier ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1798126353Smlaier age_init_locked(sc); 1799126353Smlaier return; 1800126353Smlaier } 1801126353Smlaier if (sc->age_cdata.age_tx_cnt == 0) { 1802126353Smlaier if_printf(sc->age_ifp, 1803171172Smlaier "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1804171172Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1805171172Smlaier age_start_locked(ifp); 1806171172Smlaier return; 1807126353Smlaier } 1808126353Smlaier if_printf(sc->age_ifp, "watchdog timeout\n"); 1809171172Smlaier ifp->if_oerrors++; 1810126353Smlaier ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1811126353Smlaier age_init_locked(sc); 1812126353Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1813126353Smlaier age_start_locked(ifp); 1814223637Sbz} 1815126353Smlaier 1816126353Smlaierstatic int 1817126353Smlaierage_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1818126353Smlaier{ 1819126353Smlaier struct age_softc *sc; 1820126353Smlaier struct ifreq *ifr; 1821126353Smlaier struct mii_data *mii; 1822171172Smlaier uint32_t reg; 1823126353Smlaier int error, mask; 1824126353Smlaier 1825126353Smlaier sc = ifp->if_softc; 1826126353Smlaier ifr = (struct ifreq *)data; 1827126353Smlaier error = 0; 1828126353Smlaier switch (cmd) { 1829126353Smlaier case SIOCSIFMTU: 1830126353Smlaier if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) 1831126353Smlaier error = EINVAL; 1832126353Smlaier else if (ifp->if_mtu != ifr->ifr_mtu) { 1833126353Smlaier AGE_LOCK(sc); 1834126353Smlaier ifp->if_mtu = ifr->ifr_mtu; 1835126353Smlaier if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1836126353Smlaier ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1837126353Smlaier age_init_locked(sc); 1838126353Smlaier } 1839126353Smlaier AGE_UNLOCK(sc); 1840126353Smlaier } 1841126353Smlaier break; 1842126353Smlaier case SIOCSIFFLAGS: 1843130614Smlaier AGE_LOCK(sc); 1844171172Smlaier if ((ifp->if_flags & IFF_UP) != 0) { 1845223637Sbz if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1846223637Sbz if (((ifp->if_flags ^ sc->age_if_flags) 1847126353Smlaier & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1848126353Smlaier age_rxfilter(sc); 1849126353Smlaier } else { 1850126353Smlaier if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1851126353Smlaier age_init_locked(sc); 1852126353Smlaier } 1853126353Smlaier } else { 1854171172Smlaier if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1855171172Smlaier age_stop(sc); 1856171172Smlaier } 1857223637Sbz sc->age_if_flags = ifp->if_flags; 1858223637Sbz AGE_UNLOCK(sc); 1859223637Sbz break; 1860223637Sbz case SIOCADDMULTI: 1861223637Sbz case SIOCDELMULTI: 1862223637Sbz AGE_LOCK(sc); 1863223637Sbz if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1864223637Sbz age_rxfilter(sc); 1865223637Sbz AGE_UNLOCK(sc); 1866223637Sbz break; 1867223637Sbz case SIOCSIFMEDIA: 1868223637Sbz case SIOCGIFMEDIA: 1869223637Sbz mii = device_get_softc(sc->age_miibus); 1870223637Sbz error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1871223637Sbz break; 1872223637Sbz case SIOCSIFCAP: 1873171172Smlaier AGE_LOCK(sc); 1874145840Smlaier mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1875145840Smlaier if ((mask & IFCAP_TXCSUM) != 0 && 1876145840Smlaier (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1877145840Smlaier ifp->if_capenable ^= IFCAP_TXCSUM; 1878145840Smlaier if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1879145840Smlaier ifp->if_hwassist |= AGE_CSUM_FEATURES; 1880145840Smlaier else 1881145840Smlaier ifp->if_hwassist &= ~AGE_CSUM_FEATURES; 1882126353Smlaier } 1883126353Smlaier if ((mask & IFCAP_RXCSUM) != 0 && 1884126353Smlaier (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1885126353Smlaier ifp->if_capenable ^= IFCAP_RXCSUM; 1886126353Smlaier reg = CSR_READ_4(sc, AGE_MAC_CFG); 1887126353Smlaier reg &= ~MAC_CFG_RXCSUM_ENB; 1888126353Smlaier if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1889126353Smlaier reg |= MAC_CFG_RXCSUM_ENB; 1890126353Smlaier CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1891126353Smlaier } 1892126353Smlaier if ((mask & IFCAP_TSO4) != 0 && 1893126353Smlaier (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1894126353Smlaier ifp->if_capenable ^= IFCAP_TSO4; 1895126353Smlaier if ((ifp->if_capenable & IFCAP_TSO4) != 0) 1896126353Smlaier ifp->if_hwassist |= CSUM_TSO; 1897126353Smlaier else 1898126353Smlaier ifp->if_hwassist &= ~CSUM_TSO; 1899126353Smlaier } 1900126353Smlaier 1901126353Smlaier if ((mask & IFCAP_WOL_MCAST) != 0 && 1902126353Smlaier (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 1903126353Smlaier ifp->if_capenable ^= IFCAP_WOL_MCAST; 1904126353Smlaier if ((mask & IFCAP_WOL_MAGIC) != 0 && 1905126353Smlaier (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1906126353Smlaier ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1907126353Smlaier if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1908126353Smlaier (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1909126353Smlaier ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1910126353Smlaier if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1911126353Smlaier (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1912145840Smlaier ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1913126353Smlaier if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1914126353Smlaier (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1915126353Smlaier ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1916126353Smlaier if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 1917126353Smlaier ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 1918126353Smlaier age_rxvlan(sc); 1919126353Smlaier } 1920126353Smlaier AGE_UNLOCK(sc); 1921126353Smlaier VLAN_CAPABILITIES(ifp); 1922126353Smlaier break; 1923126353Smlaier default: 1924126353Smlaier error = ether_ioctl(ifp, cmd, data); 1925126353Smlaier break; 1926126353Smlaier } 1927126353Smlaier 1928126353Smlaier return (error); 1929126353Smlaier} 1930126353Smlaier 1931126353Smlaierstatic void 1932126353Smlaierage_mac_config(struct age_softc *sc) 1933126353Smlaier{ 1934126353Smlaier struct mii_data *mii; 1935126353Smlaier uint32_t reg; 1936126353Smlaier 1937126353Smlaier AGE_LOCK_ASSERT(sc); 1938126353Smlaier 1939126353Smlaier mii = device_get_softc(sc->age_miibus); 1940126353Smlaier reg = CSR_READ_4(sc, AGE_MAC_CFG); 1941126353Smlaier reg &= ~MAC_CFG_FULL_DUPLEX; 1942126353Smlaier reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1943126353Smlaier reg &= ~MAC_CFG_SPEED_MASK; 1944126353Smlaier /* Reprogram MAC with resolved speed/duplex. */ 1945126353Smlaier switch (IFM_SUBTYPE(mii->mii_media_active)) { 1946126353Smlaier case IFM_10_T: 1947126353Smlaier case IFM_100_TX: 1948126353Smlaier reg |= MAC_CFG_SPEED_10_100; 1949126353Smlaier break; 1950126353Smlaier case IFM_1000_T: 1951126353Smlaier reg |= MAC_CFG_SPEED_1000; 1952126353Smlaier break; 1953126353Smlaier } 1954126353Smlaier if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1955126353Smlaier reg |= MAC_CFG_FULL_DUPLEX; 1956126353Smlaier#ifdef notyet 1957126353Smlaier if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1958126353Smlaier reg |= MAC_CFG_TX_FC; 1959126353Smlaier if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1960126353Smlaier reg |= MAC_CFG_RX_FC; 1961126353Smlaier#endif 1962126353Smlaier } 1963126353Smlaier 1964126353Smlaier CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1965126353Smlaier} 1966126353Smlaier 1967126353Smlaierstatic void 1968126353Smlaierage_link_task(void *arg, int pending) 1969126353Smlaier{ 1970126353Smlaier struct age_softc *sc; 1971126353Smlaier struct mii_data *mii; 1972126353Smlaier struct ifnet *ifp; 1973126353Smlaier uint32_t reg; 1974126353Smlaier 1975126353Smlaier sc = (struct age_softc *)arg; 1976126353Smlaier 1977126353Smlaier AGE_LOCK(sc); 1978130614Smlaier mii = device_get_softc(sc->age_miibus); 1979130614Smlaier ifp = sc->age_ifp; 1980130614Smlaier if (mii == NULL || ifp == NULL || 1981130614Smlaier (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1982130614Smlaier AGE_UNLOCK(sc); 1983130614Smlaier return; 1984130614Smlaier } 1985130614Smlaier 1986130614Smlaier sc->age_flags &= ~AGE_FLAG_LINK; 1987130614Smlaier if ((mii->mii_media_status & IFM_AVALID) != 0) { 1988130614Smlaier switch (IFM_SUBTYPE(mii->mii_media_active)) { 1989130614Smlaier case IFM_10_T: 1990130614Smlaier case IFM_100_TX: 1991223637Sbz case IFM_1000_T: 1992130614Smlaier sc->age_flags |= AGE_FLAG_LINK; 1993130614Smlaier break; 1994130614Smlaier default: 1995126353Smlaier break; 1996126353Smlaier } 1997126353Smlaier } 1998126353Smlaier 1999126353Smlaier /* Stop Rx/Tx MACs. */ 2000126353Smlaier age_stop_rxmac(sc); 2001126353Smlaier age_stop_txmac(sc); 2002126353Smlaier 2003126353Smlaier /* Program MACs with resolved speed/duplex/flow-control. */ 2004126353Smlaier if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 2005126353Smlaier age_mac_config(sc); 2006126353Smlaier reg = CSR_READ_4(sc, AGE_MAC_CFG); 2007126353Smlaier /* Restart DMA engine and Tx/Rx MAC. */ 2008126353Smlaier CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 2009126353Smlaier DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 2010126353Smlaier reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2011126353Smlaier CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2012126353Smlaier } 2013126353Smlaier 2014126353Smlaier AGE_UNLOCK(sc); 2015126353Smlaier} 2016126353Smlaier 2017171172Smlaierstatic void 2018126353Smlaierage_stats_update(struct age_softc *sc) 2019126353Smlaier{ 2020171172Smlaier struct age_stats *stat; 2021126353Smlaier struct smb *smb; 2022126353Smlaier struct ifnet *ifp; 2023126353Smlaier 2024126353Smlaier AGE_LOCK_ASSERT(sc); 2025126353Smlaier 2026126353Smlaier stat = &sc->age_stat; 2027126353Smlaier 2028126353Smlaier bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2029171172Smlaier sc->age_cdata.age_smb_block_map, 2030171172Smlaier BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2031171172Smlaier 2032126353Smlaier smb = sc->age_rdata.age_smb_block; 2033171172Smlaier if (smb->updated == 0) 2034171172Smlaier return; 2035171172Smlaier 2036171172Smlaier ifp = sc->age_ifp; 2037171172Smlaier /* Rx stats. */ 2038171172Smlaier stat->rx_frames += smb->rx_frames; 2039171172Smlaier stat->rx_bcast_frames += smb->rx_bcast_frames; 2040171172Smlaier stat->rx_mcast_frames += smb->rx_mcast_frames; 2041171172Smlaier stat->rx_pause_frames += smb->rx_pause_frames; 2042171172Smlaier stat->rx_control_frames += smb->rx_control_frames; 2043126353Smlaier stat->rx_crcerrs += smb->rx_crcerrs; 2044126353Smlaier stat->rx_lenerrs += smb->rx_lenerrs; 2045126353Smlaier stat->rx_bytes += smb->rx_bytes; 2046126353Smlaier stat->rx_runts += smb->rx_runts; 2047126353Smlaier stat->rx_fragments += smb->rx_fragments; 2048126353Smlaier stat->rx_pkts_64 += smb->rx_pkts_64; 2049126353Smlaier stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2050126353Smlaier stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2051126353Smlaier stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2052126353Smlaier stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2053126353Smlaier stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2054126353Smlaier stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2055126353Smlaier stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2056126353Smlaier stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2057126353Smlaier stat->rx_desc_oflows += smb->rx_desc_oflows; 2058126353Smlaier stat->rx_alignerrs += smb->rx_alignerrs; 2059126353Smlaier stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2060126353Smlaier stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2061126353Smlaier stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2062126353Smlaier 2063126353Smlaier /* Tx stats. */ 2064130614Smlaier stat->tx_frames += smb->tx_frames; 2065126353Smlaier stat->tx_bcast_frames += smb->tx_bcast_frames; 2066126353Smlaier stat->tx_mcast_frames += smb->tx_mcast_frames; 2067126353Smlaier stat->tx_pause_frames += smb->tx_pause_frames; 2068126353Smlaier stat->tx_excess_defer += smb->tx_excess_defer; 2069126353Smlaier stat->tx_control_frames += smb->tx_control_frames; 2070171172Smlaier stat->tx_deferred += smb->tx_deferred; 2071126353Smlaier stat->tx_bytes += smb->tx_bytes; 2072126353Smlaier stat->tx_pkts_64 += smb->tx_pkts_64; 2073126353Smlaier stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2074126353Smlaier stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2075126353Smlaier stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2076126353Smlaier stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2077223637Sbz stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2078126353Smlaier stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2079126353Smlaier stat->tx_single_colls += smb->tx_single_colls; 2080126353Smlaier stat->tx_multi_colls += smb->tx_multi_colls; 2081171172Smlaier stat->tx_late_colls += smb->tx_late_colls; 2082126353Smlaier stat->tx_excess_colls += smb->tx_excess_colls; 2083126353Smlaier stat->tx_underrun += smb->tx_underrun; 2084171172Smlaier stat->tx_desc_underrun += smb->tx_desc_underrun; 2085171172Smlaier stat->tx_lenerrs += smb->tx_lenerrs; 2086126353Smlaier stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2087126353Smlaier stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2088126353Smlaier stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2089126353Smlaier 2090171172Smlaier /* Update counters in ifnet. */ 2091171172Smlaier ifp->if_opackets += smb->tx_frames; 2092171172Smlaier 2093126353Smlaier ifp->if_collisions += smb->tx_single_colls + 2094126353Smlaier smb->tx_multi_colls + smb->tx_late_colls + 2095171172Smlaier smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 2096126353Smlaier 2097223637Sbz ifp->if_oerrors += smb->tx_excess_colls + 2098223637Sbz smb->tx_late_colls + smb->tx_underrun + 2099130614Smlaier smb->tx_pkts_truncated; 2100130614Smlaier 2101130614Smlaier ifp->if_ipackets += smb->rx_frames; 2102130614Smlaier 2103171172Smlaier ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2104171172Smlaier smb->rx_runts + smb->rx_pkts_truncated + 2105171172Smlaier smb->rx_fifo_oflows + smb->rx_desc_oflows + 2106126353Smlaier smb->rx_alignerrs; 2107145840Smlaier 2108145840Smlaier /* Update done, clear. */ 2109145840Smlaier smb->updated = 0; 2110200930Sdelphij 2111200930Sdelphij bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2112200930Sdelphij sc->age_cdata.age_smb_block_map, 2113200930Sdelphij BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2114200930Sdelphij} 2115223637Sbz 2116200930Sdelphijstatic int 2117223637Sbzage_intr(void *arg) 2118223637Sbz{ 2119223637Sbz struct age_softc *sc; 2120223637Sbz uint32_t status; 2121145840Smlaier 2122130614Smlaier sc = (struct age_softc *)arg; 2123145840Smlaier 2124145840Smlaier status = CSR_READ_4(sc, AGE_INTR_STATUS); 2125145840Smlaier if (status == 0 || (status & AGE_INTRS) == 0) 2126171172Smlaier return (FILTER_STRAY); 2127145840Smlaier /* Disable interrupts. */ 2128145840Smlaier CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2129145840Smlaier taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2130145840Smlaier 2131130614Smlaier return (FILTER_HANDLED); 2132130614Smlaier} 2133130614Smlaier 2134145840Smlaierstatic void 2135145840Smlaierage_int_task(void *arg, int pending) 2136145840Smlaier{ 2137145840Smlaier struct age_softc *sc; 2138145840Smlaier struct ifnet *ifp; 2139145840Smlaier struct cmb *cmb; 2140171172Smlaier uint32_t status; 2141145840Smlaier 2142145840Smlaier sc = (struct age_softc *)arg; 2143145840Smlaier 2144145840Smlaier AGE_LOCK(sc); 2145145840Smlaier 2146145840Smlaier bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2147145840Smlaier sc->age_cdata.age_cmb_block_map, 2148145840Smlaier BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2149145840Smlaier cmb = sc->age_rdata.age_cmb_block; 2150145840Smlaier status = le32toh(cmb->intr_status); 2151145840Smlaier if (sc->age_morework != 0) 2152145840Smlaier status |= INTR_CMB_RX; 2153145840Smlaier if ((status & AGE_INTRS) == 0) 2154130614Smlaier goto done; 2155130614Smlaier 2156145840Smlaier sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 2157171172Smlaier TPD_CONS_SHIFT; 2158130614Smlaier sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 2159130614Smlaier RRD_PROD_SHIFT; 2160171172Smlaier /* Let hardware know CMB was served. */ 2161130614Smlaier cmb->intr_status = 0; 2162130614Smlaier bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2163130614Smlaier sc->age_cdata.age_cmb_block_map, 2164126353Smlaier BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2165145840Smlaier 2166145840Smlaier#if 0 2167145840Smlaier printf("INTR: 0x%08x\n", status); 2168145840Smlaier status &= ~INTR_DIS_DMA; 2169145840Smlaier CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2170171172Smlaier#endif 2171145840Smlaier ifp = sc->age_ifp; 2172145840Smlaier if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2173171172Smlaier if ((status & INTR_CMB_RX) != 0) 2174171172Smlaier sc->age_morework = age_rxintr(sc, sc->age_rr_prod, 2175171172Smlaier sc->age_process_limit); 2176145840Smlaier if ((status & INTR_CMB_TX) != 0) 2177145840Smlaier age_txintr(sc, sc->age_tpd_cons); 2178145840Smlaier if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2179145840Smlaier if ((status & INTR_DMA_RD_TO_RST) != 0) 2180145840Smlaier device_printf(sc->age_dev, 2181145840Smlaier "DMA read error! -- resetting\n"); 2182145840Smlaier if ((status & INTR_DMA_WR_TO_RST) != 0) 2183171172Smlaier device_printf(sc->age_dev, 2184145840Smlaier "DMA write error! -- resetting\n"); 2185145840Smlaier ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2186145840Smlaier age_init_locked(sc); 2187145840Smlaier } 2188145840Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2189145840Smlaier age_start_locked(ifp); 2190145840Smlaier if ((status & INTR_SMB) != 0) 2191145840Smlaier age_stats_update(sc); 2192145840Smlaier } 2193145840Smlaier 2194145840Smlaier /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 2195145840Smlaier bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2196145840Smlaier sc->age_cdata.age_cmb_block_map, 2197145840Smlaier BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2198145840Smlaier status = le32toh(cmb->intr_status); 2199145840Smlaier if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { 2200145840Smlaier taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2201145840Smlaier AGE_UNLOCK(sc); 2202171172Smlaier return; 2203171172Smlaier } 2204171172Smlaier 2205145840Smlaierdone: 2206145840Smlaier /* Re-enable interrupts. */ 2207145840Smlaier CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2208171172Smlaier AGE_UNLOCK(sc); 2209171172Smlaier} 2210171172Smlaier 2211126353Smlaierstatic void 2212126353Smlaierage_txintr(struct age_softc *sc, int tpd_cons) 2213126353Smlaier{ 2214126353Smlaier struct ifnet *ifp; 2215126353Smlaier struct age_txdesc *txd; 2216126353Smlaier int cons, prog; 2217126353Smlaier 2218126353Smlaier AGE_LOCK_ASSERT(sc); 2219126353Smlaier 2220126353Smlaier ifp = sc->age_ifp; 2221126353Smlaier 2222145840Smlaier bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2223171172Smlaier sc->age_cdata.age_tx_ring_map, 2224171172Smlaier BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2225171172Smlaier 2226126353Smlaier /* 2227126353Smlaier * Go through our Tx list and free mbufs for those 2228171172Smlaier * frames which have been transmitted. 2229171172Smlaier */ 2230171172Smlaier cons = sc->age_cdata.age_tx_cons; 2231126353Smlaier for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 2232126353Smlaier if (sc->age_cdata.age_tx_cnt <= 0) 2233126353Smlaier break; 2234126353Smlaier prog++; 2235126353Smlaier ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2236126353Smlaier sc->age_cdata.age_tx_cnt--; 2237171172Smlaier txd = &sc->age_cdata.age_txdesc[cons]; 2238171172Smlaier /* 2239171172Smlaier * Clear Tx descriptors, it's not required but would 2240126353Smlaier * help debugging in case of Tx issues. 2241126353Smlaier */ 2242126353Smlaier txd->tx_desc->addr = 0; 2243126353Smlaier txd->tx_desc->len = 0; 2244126353Smlaier txd->tx_desc->flags = 0; 2245126353Smlaier 2246126353Smlaier if (txd->tx_m == NULL) 2247126353Smlaier continue; 2248126353Smlaier /* Reclaim transmitted mbufs. */ 2249126353Smlaier bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, 2250126353Smlaier BUS_DMASYNC_POSTWRITE); 2251126353Smlaier bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 2252126353Smlaier m_freem(txd->tx_m); 2253126353Smlaier txd->tx_m = NULL; 2254126353Smlaier } 2255126353Smlaier 2256126353Smlaier if (prog > 0) { 2257126353Smlaier sc->age_cdata.age_tx_cons = cons; 2258126353Smlaier 2259126353Smlaier /* 2260126353Smlaier * Unarm watchdog timer only when there are no pending 2261126353Smlaier * Tx descriptors in queue. 2262126353Smlaier */ 2263126353Smlaier if (sc->age_cdata.age_tx_cnt == 0) 2264126353Smlaier sc->age_watchdog_timer = 0; 2265126353Smlaier bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2266126353Smlaier sc->age_cdata.age_tx_ring_map, 2267171172Smlaier BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2268126353Smlaier } 2269126353Smlaier} 2270126353Smlaier 2271126353Smlaier/* Receive a frame. */ 2272171172Smlaierstatic void 2273126353Smlaierage_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2274126353Smlaier{ 2275126353Smlaier struct age_rxdesc *rxd; 2276126353Smlaier struct rx_desc *desc; 2277126353Smlaier struct ifnet *ifp; 2278126353Smlaier struct mbuf *mp, *m; 2279126353Smlaier uint32_t status, index, vtag; 2280126353Smlaier int count, nsegs, pktlen; 2281126353Smlaier int rx_cons; 2282126353Smlaier 2283126353Smlaier AGE_LOCK_ASSERT(sc); 2284126353Smlaier 2285126353Smlaier ifp = sc->age_ifp; 2286126353Smlaier status = le32toh(rxrd->flags); 2287126353Smlaier index = le32toh(rxrd->index); 2288126353Smlaier rx_cons = AGE_RX_CONS(index); 2289126353Smlaier nsegs = AGE_RX_NSEGS(index); 2290126353Smlaier 2291126353Smlaier sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2292126353Smlaier if ((status & AGE_RRD_ERROR) != 0 && 2293126353Smlaier (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2294126353Smlaier AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 2295126353Smlaier /* 2296126353Smlaier * We want to pass the following frames to upper 2297126353Smlaier * layer regardless of error status of Rx return 2298126353Smlaier * ring. 2299126353Smlaier * 2300126353Smlaier * o IP/TCP/UDP checksum is bad. 2301126353Smlaier * o frame length and protocol specific length 2302126353Smlaier * does not match. 2303126353Smlaier */ 2304126353Smlaier sc->age_cdata.age_rx_cons += nsegs; 2305126353Smlaier sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2306126353Smlaier return; 2307126353Smlaier } 2308126353Smlaier 2309126353Smlaier pktlen = 0; 2310126353Smlaier for (count = 0; count < nsegs; count++, 2311126353Smlaier AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2312126353Smlaier rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2313126353Smlaier mp = rxd->rx_m; 2314126353Smlaier desc = rxd->rx_desc; 2315126353Smlaier /* Add a new receive buffer to the ring. */ 2316126353Smlaier if (age_newbuf(sc, rxd) != 0) { 2317126353Smlaier ifp->if_iqdrops++; 2318126353Smlaier /* Reuse Rx buffers. */ 2319126353Smlaier if (sc->age_cdata.age_rxhead != NULL) { 2320126353Smlaier m_freem(sc->age_cdata.age_rxhead); 2321126353Smlaier AGE_RXCHAIN_RESET(sc); 2322126353Smlaier } 2323126353Smlaier break; 2324126353Smlaier } 2325126353Smlaier 2326126353Smlaier /* The length of the first mbuf is computed last. */ 2327126353Smlaier if (count != 0) { 2328130614Smlaier mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 2329126353Smlaier pktlen += mp->m_len; 2330126353Smlaier } 2331126353Smlaier 2332126353Smlaier /* Chain received mbufs. */ 2333126353Smlaier if (sc->age_cdata.age_rxhead == NULL) { 2334126353Smlaier sc->age_cdata.age_rxhead = mp; 2335126353Smlaier sc->age_cdata.age_rxtail = mp; 2336126353Smlaier } else { 2337126353Smlaier mp->m_flags &= ~M_PKTHDR; 2338126353Smlaier sc->age_cdata.age_rxprev_tail = 2339126353Smlaier sc->age_cdata.age_rxtail; 2340126353Smlaier sc->age_cdata.age_rxtail->m_next = mp; 2341126353Smlaier sc->age_cdata.age_rxtail = mp; 2342126353Smlaier } 2343126353Smlaier 2344126353Smlaier if (count == nsegs - 1) { 2345126353Smlaier /* 2346126353Smlaier * It seems that L1 controller has no way 2347126353Smlaier * to tell hardware to strip CRC bytes. 2348126353Smlaier */ 2349126353Smlaier sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 2350126353Smlaier if (nsegs > 1) { 2351126353Smlaier /* Remove the CRC bytes in chained mbufs. */ 2352126353Smlaier pktlen -= ETHER_CRC_LEN; 2353126353Smlaier if (mp->m_len <= ETHER_CRC_LEN) { 2354126353Smlaier sc->age_cdata.age_rxtail = 2355126353Smlaier sc->age_cdata.age_rxprev_tail; 2356126353Smlaier sc->age_cdata.age_rxtail->m_len -= 2357126353Smlaier (ETHER_CRC_LEN - mp->m_len); 2358126353Smlaier sc->age_cdata.age_rxtail->m_next = NULL; 2359126353Smlaier m_freem(mp); 2360126353Smlaier } else { 2361126353Smlaier mp->m_len -= ETHER_CRC_LEN; 2362126353Smlaier } 2363126353Smlaier } 2364126353Smlaier 2365126353Smlaier m = sc->age_cdata.age_rxhead; 2366126353Smlaier m->m_flags |= M_PKTHDR; 2367126353Smlaier m->m_pkthdr.rcvif = ifp; 2368126353Smlaier m->m_pkthdr.len = sc->age_cdata.age_rxlen; 2369126353Smlaier /* Set the first mbuf length. */ 2370126353Smlaier m->m_len = sc->age_cdata.age_rxlen - pktlen; 2371126353Smlaier 2372126353Smlaier /* 2373126353Smlaier * Set checksum information. 2374126353Smlaier * It seems that L1 controller can compute partial 2375126353Smlaier * checksum. The partial checksum value can be used 2376126353Smlaier * to accelerate checksum computation for fragmented 2377126353Smlaier * TCP/UDP packets. Upper network stack already 2378126353Smlaier * takes advantage of the partial checksum value in 2379126353Smlaier * IP reassembly stage. But I'm not sure the 2380126353Smlaier * correctness of the partial hardware checksum 2381126353Smlaier * assistance due to lack of data sheet. If it is 2382126353Smlaier * proven to work on L1 I'll enable it. 2383126353Smlaier */ 2384126353Smlaier if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2385126353Smlaier (status & AGE_RRD_IPV4) != 0) { 2386126353Smlaier m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2387126353Smlaier if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2388126353Smlaier m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2389126353Smlaier if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2390126353Smlaier (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2391126353Smlaier m->m_pkthdr.csum_flags |= 2392126353Smlaier CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2393145840Smlaier m->m_pkthdr.csum_data = 0xffff; 2394126353Smlaier } 2395126353Smlaier /* 2396145840Smlaier * Don't mark bad checksum for TCP/UDP frames 2397126353Smlaier * as fragmented frames may always have set 2398126353Smlaier * bad checksummed bit of descriptor status. 2399126353Smlaier */ 2400126353Smlaier } 2401145840Smlaier 2402145840Smlaier /* Check for VLAN tagged frames. */ 2403126353Smlaier if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2404126353Smlaier (status & AGE_RRD_VLAN) != 0) { 2405145840Smlaier vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2406126353Smlaier m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); 2407145840Smlaier m->m_flags |= M_VLANTAG; 2408145840Smlaier } 2409145840Smlaier 2410145840Smlaier /* Pass it on. */ 2411145840Smlaier AGE_UNLOCK(sc); 2412145840Smlaier (*ifp->if_input)(ifp, m); 2413145840Smlaier AGE_LOCK(sc); 2414145840Smlaier 2415145840Smlaier /* Reset mbuf chains. */ 2416126353Smlaier AGE_RXCHAIN_RESET(sc); 2417145840Smlaier } 2418126353Smlaier } 2419126353Smlaier 2420126353Smlaier if (count != nsegs) { 2421171172Smlaier sc->age_cdata.age_rx_cons += nsegs; 2422126353Smlaier sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2423126353Smlaier } else 2424145840Smlaier sc->age_cdata.age_rx_cons = rx_cons; 2425126353Smlaier} 2426171172Smlaier 2427126353Smlaierstatic int 2428126353Smlaierage_rxintr(struct age_softc *sc, int rr_prod, int count) 2429145840Smlaier{ 2430126353Smlaier struct rx_rdesc *rxrd; 2431171172Smlaier int rr_cons, nsegs, pktlen, prog; 2432126353Smlaier 2433126353Smlaier AGE_LOCK_ASSERT(sc); 2434145840Smlaier 2435126353Smlaier rr_cons = sc->age_cdata.age_rr_cons; 2436171172Smlaier if (rr_cons == rr_prod) 2437145840Smlaier return (0); 2438126353Smlaier 2439171172Smlaier bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2440171172Smlaier sc->age_cdata.age_rr_ring_map, 2441171172Smlaier BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2442171172Smlaier bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2443145840Smlaier sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2444145840Smlaier 2445145840Smlaier for (prog = 0; rr_cons != rr_prod; prog++) { 2446126353Smlaier if (count <= 0) 2447126353Smlaier break; 2448126353Smlaier rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2449126353Smlaier nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2450126353Smlaier if (nsegs == 0) 2451126353Smlaier break; 2452145840Smlaier /* 2453126353Smlaier * Check number of segments against received bytes. 2454171172Smlaier * Non-matching value would indicate that hardware 2455126353Smlaier * is still trying to update Rx return descriptors. 2456145840Smlaier * I'm not sure whether this check is really needed. 2457171172Smlaier */ 2458171172Smlaier pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2459171172Smlaier if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 2460171172Smlaier (MCLBYTES - ETHER_ALIGN))) 2461171172Smlaier break; 2462171172Smlaier 2463171172Smlaier prog++; 2464171172Smlaier /* Received a frame. */ 2465126353Smlaier age_rxeof(sc, rxrd); 2466126353Smlaier /* Clear return ring. */ 2467145840Smlaier rxrd->index = 0; 2468145840Smlaier AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2469126353Smlaier } 2470145840Smlaier 2471145840Smlaier if (prog > 0) { 2472145840Smlaier /* Update the consumer index. */ 2473145840Smlaier sc->age_cdata.age_rr_cons = rr_cons; 2474145840Smlaier 2475145840Smlaier bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2476126353Smlaier sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 2477145840Smlaier /* Sync descriptors. */ 2478126353Smlaier bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2479126353Smlaier sc->age_cdata.age_rr_ring_map, 2480145840Smlaier BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2481126353Smlaier 2482145840Smlaier /* Notify hardware availability of new Rx buffers. */ 2483126353Smlaier AGE_COMMIT_MBOX(sc); 2484126353Smlaier } 2485126353Smlaier 2486126353Smlaier return (count > 0 ? 0 : EAGAIN); 2487126353Smlaier} 2488171172Smlaier 2489126353Smlaierstatic void 2490171172Smlaierage_tick(void *arg) 2491126353Smlaier{ 2492126353Smlaier struct age_softc *sc; 2493126353Smlaier struct mii_data *mii; 2494145840Smlaier 2495126353Smlaier sc = (struct age_softc *)arg; 2496126353Smlaier 2497126353Smlaier AGE_LOCK_ASSERT(sc); 2498126353Smlaier 2499126353Smlaier mii = device_get_softc(sc->age_miibus); 2500145840Smlaier mii_tick(mii); 2501126353Smlaier age_watchdog(sc); 2502126353Smlaier callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2503145840Smlaier} 2504126353Smlaier 2505126353Smlaierstatic void 2506126353Smlaierage_reset(struct age_softc *sc) 2507145840Smlaier{ 2508126353Smlaier uint32_t reg; 2509126353Smlaier int i; 2510126353Smlaier 2511126353Smlaier CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2512126353Smlaier CSR_READ_4(sc, AGE_MASTER_CFG); 2513126353Smlaier DELAY(1000); 2514145840Smlaier for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2515126353Smlaier if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2516126353Smlaier break; 2517126353Smlaier DELAY(10); 2518126353Smlaier } 2519126353Smlaier 2520126353Smlaier if (i == 0) 2521126353Smlaier device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2522126353Smlaier /* Initialize PCIe module. From Linux. */ 2523145840Smlaier CSR_WRITE_4(sc, 0x12FC, 0x6500); 2524126353Smlaier CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2525126353Smlaier} 2526126353Smlaier 2527223637Sbzstatic void 2528223637Sbzage_init(void *xsc) 2529126353Smlaier{ 2530126353Smlaier struct age_softc *sc; 2531126353Smlaier 2532145840Smlaier sc = (struct age_softc *)xsc; 2533126353Smlaier AGE_LOCK(sc); 2534126353Smlaier age_init_locked(sc); 2535126353Smlaier AGE_UNLOCK(sc); 2536171172Smlaier} 2537171172Smlaier 2538126353Smlaierstatic void 2539126353Smlaierage_init_locked(struct age_softc *sc) 2540126353Smlaier{ 2541126353Smlaier struct ifnet *ifp; 2542126353Smlaier struct mii_data *mii; 2543126353Smlaier uint8_t eaddr[ETHER_ADDR_LEN]; 2544126353Smlaier bus_addr_t paddr; 2545126353Smlaier uint32_t reg, fsize; 2546126353Smlaier uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2547126353Smlaier int error; 2548145840Smlaier 2549126353Smlaier AGE_LOCK_ASSERT(sc); 2550126353Smlaier 2551126353Smlaier ifp = sc->age_ifp; 2552145840Smlaier mii = device_get_softc(sc->age_miibus); 2553145840Smlaier 2554145840Smlaier if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2555145840Smlaier return; 2556145840Smlaier 2557145840Smlaier /* 2558145840Smlaier * Cancel any pending I/O. 2559145840Smlaier */ 2560145840Smlaier age_stop(sc); 2561145840Smlaier 2562145840Smlaier /* 2563145840Smlaier * Reset the chip to a known state. 2564145840Smlaier */ 2565145840Smlaier age_reset(sc); 2566145840Smlaier 2567145840Smlaier /* Initialize descriptors. */ 2568145840Smlaier error = age_init_rx_ring(sc); 2569145840Smlaier if (error != 0) { 2570145840Smlaier device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2571145840Smlaier age_stop(sc); 2572145840Smlaier return; 2573145840Smlaier } 2574145840Smlaier age_init_rr_ring(sc); 2575145840Smlaier age_init_tx_ring(sc); 2576145840Smlaier age_init_cmb_block(sc); 2577145840Smlaier age_init_smb_block(sc); 2578145840Smlaier 2579145840Smlaier /* Reprogram the station address. */ 2580145840Smlaier bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2581145840Smlaier CSR_WRITE_4(sc, AGE_PAR0, 2582145840Smlaier eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2583145840Smlaier CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2584145840Smlaier 2585145840Smlaier /* Set descriptor base addresses. */ 2586145840Smlaier paddr = sc->age_rdata.age_tx_ring_paddr; 2587145840Smlaier CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2588145840Smlaier paddr = sc->age_rdata.age_rx_ring_paddr; 2589145840Smlaier CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2590145840Smlaier paddr = sc->age_rdata.age_rr_ring_paddr; 2591145840Smlaier CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2592171172Smlaier paddr = sc->age_rdata.age_tx_ring_paddr; 2593171172Smlaier CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2594171172Smlaier paddr = sc->age_rdata.age_cmb_block_paddr; 2595171172Smlaier CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2596171172Smlaier paddr = sc->age_rdata.age_smb_block_paddr; 2597171172Smlaier CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2598171172Smlaier /* Set Rx/Rx return descriptor counter. */ 2599171172Smlaier CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2600171172Smlaier ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2601171172Smlaier DESC_RRD_CNT_MASK) | 2602171172Smlaier ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2603171172Smlaier /* Set Tx descriptor counter. */ 2604171172Smlaier CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2605171172Smlaier (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2606171172Smlaier 2607171172Smlaier /* Tell hardware that we're ready to load descriptors. */ 2608145840Smlaier CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2609176196Sremko 2610176196Sremko /* 2611145840Smlaier * Initialize mailbox register. 2612145840Smlaier * Updated producer/consumer index information is exchanged 2613145840Smlaier * through this mailbox register. However Tx producer and 2614126353Smlaier * Rx return consumer/Rx producer are all shared such that 2615126353Smlaier * it's hard to separate code path between Tx and Rx without 2616126353Smlaier * locking. If L1 hardware have a separate mail box register 2617126353Smlaier * for Tx and Rx consumer/producer management we could have 2618126353Smlaier * indepent Tx/Rx handler which in turn Rx handler could have 2619130614Smlaier * been run without any locking. 2620130614Smlaier */ 2621130614Smlaier AGE_COMMIT_MBOX(sc); 2622126353Smlaier 2623171172Smlaier /* Configure IPG/IFG parameters. */ 2624126353Smlaier CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2625126353Smlaier ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2626126353Smlaier ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2627126353Smlaier ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2628126353Smlaier ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2629126353Smlaier 2630126353Smlaier /* Set parameters for half-duplex media. */ 2631171172Smlaier CSR_WRITE_4(sc, AGE_HDPX_CFG, 2632130614Smlaier ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2633126353Smlaier HDPX_CFG_LCOL_MASK) | 2634126353Smlaier ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2635126353Smlaier HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2636126353Smlaier ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2637126353Smlaier HDPX_CFG_ABEBT_MASK) | 2638126353Smlaier ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2639126353Smlaier HDPX_CFG_JAMIPG_MASK)); 2640126353Smlaier 2641126353Smlaier /* Configure interrupt moderation timer. */ 2642126353Smlaier CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2643126353Smlaier reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2644171172Smlaier reg &= ~MASTER_MTIMER_ENB; 2645126353Smlaier if (AGE_USECS(sc->age_int_mod) == 0) 2646126353Smlaier reg &= ~MASTER_ITIMER_ENB; 2647130614Smlaier else 2648130614Smlaier reg |= MASTER_ITIMER_ENB; 2649126353Smlaier CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2650126353Smlaier if (bootverbose) 2651126353Smlaier device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2652126353Smlaier sc->age_int_mod); 2653126353Smlaier CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2654130614Smlaier 2655171172Smlaier /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2656126353Smlaier if (ifp->if_mtu < ETHERMTU) 2657126353Smlaier sc->age_max_frame_size = ETHERMTU; 2658130614Smlaier else 2659130614Smlaier sc->age_max_frame_size = ifp->if_mtu; 2660126353Smlaier sc->age_max_frame_size += ETHER_HDR_LEN + 2661126353Smlaier sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2662130614Smlaier CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2663130614Smlaier /* Configure jumbo frame. */ 2664171172Smlaier fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2665130614Smlaier CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2666126353Smlaier (((fsize / sizeof(uint64_t)) << 2667126353Smlaier RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2668126353Smlaier ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2669130614Smlaier RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2670171172Smlaier ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2671126353Smlaier RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2672171172Smlaier 2673171172Smlaier /* Configure flow-control parameters. From Linux. */ 2674171172Smlaier if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2675171172Smlaier /* 2676171172Smlaier * Magic workaround for old-L1. 2677171172Smlaier * Don't know which hw revision requires this magic. 2678126353Smlaier */ 2679126353Smlaier CSR_WRITE_4(sc, 0x12FC, 0x6500); 2680126353Smlaier /* 2681126353Smlaier * Another magic workaround for flow-control mode 2682171172Smlaier * change. From Linux. 2683126353Smlaier */ 2684126353Smlaier CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2685126353Smlaier } 2686126353Smlaier /* 2687126353Smlaier * TODO 2688171172Smlaier * Should understand pause parameter relationships between FIFO 2689126353Smlaier * size and number of Rx descriptors and Rx return descriptors. 2690126353Smlaier * 2691126353Smlaier * Magic parameters came from Linux. 2692126353Smlaier */ 2693126353Smlaier switch (sc->age_chip_rev) { 2694126353Smlaier case 0x8001: 2695171172Smlaier case 0x9001: 2696126353Smlaier case 0x9002: 2697126353Smlaier case 0x9003: 2698126353Smlaier rxf_hi = AGE_RX_RING_CNT / 16; 2699126353Smlaier rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2700130614Smlaier rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2701171172Smlaier rrd_lo = AGE_RR_RING_CNT / 16; 2702130614Smlaier break; 2703171172Smlaier default: 2704126353Smlaier reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2705126353Smlaier rxf_lo = reg / 16; 2706126353Smlaier if (rxf_lo < 192) 2707126353Smlaier rxf_lo = 192; 2708171172Smlaier rxf_hi = (reg * 7) / 8; 2709126353Smlaier if (rxf_hi < rxf_lo) 2710126353Smlaier rxf_hi = rxf_lo + 16; 2711126353Smlaier reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2712126353Smlaier rrd_lo = reg / 8; 2713126353Smlaier rrd_hi = (reg * 7) / 8; 2714126353Smlaier if (rrd_lo < 2) 2715126353Smlaier rrd_lo = 2; 2716126353Smlaier if (rrd_hi < rrd_lo) 2717126353Smlaier rrd_hi = rrd_lo + 3; 2718126353Smlaier break; 2719126353Smlaier } 2720171172Smlaier CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2721126353Smlaier ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2722126353Smlaier RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2723126353Smlaier ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2724126353Smlaier RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2725130614Smlaier CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2726171172Smlaier ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2727126353Smlaier RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2728126353Smlaier ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2729126353Smlaier RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2730126353Smlaier 2731126353Smlaier /* Configure RxQ. */ 2732126353Smlaier CSR_WRITE_4(sc, AGE_RXQ_CFG, 2733126353Smlaier ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2734126353Smlaier RXQ_CFG_RD_BURST_MASK) | 2735126353Smlaier ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2736126353Smlaier RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2737126353Smlaier ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2738126353Smlaier RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2739126353Smlaier RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2740126353Smlaier 2741126353Smlaier /* Configure TxQ. */ 2742126353Smlaier CSR_WRITE_4(sc, AGE_TXQ_CFG, 2743126353Smlaier ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2744126353Smlaier TXQ_CFG_TPD_BURST_MASK) | 2745126353Smlaier ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2746171172Smlaier TXQ_CFG_TX_FIFO_BURST_MASK) | 2747171172Smlaier ((TXQ_CFG_TPD_FETCH_DEFAULT << 2748171172Smlaier TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2749171172Smlaier TXQ_CFG_ENB); 2750126353Smlaier 2751126353Smlaier CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2752126353Smlaier (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2753126353Smlaier TX_JUMBO_TPD_TH_MASK) | 2754126353Smlaier ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2755126353Smlaier TX_JUMBO_TPD_IPG_MASK)); 2756126353Smlaier /* Configure DMA parameters. */ 2757126353Smlaier CSR_WRITE_4(sc, AGE_DMA_CFG, 2758126353Smlaier DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2759126353Smlaier sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2760126353Smlaier sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2761126353Smlaier 2762126353Smlaier /* Configure CMB DMA write threshold. */ 2763126353Smlaier CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2764126353Smlaier ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2765126353Smlaier CMB_WR_THRESH_RRD_MASK) | 2766126353Smlaier ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2767126353Smlaier CMB_WR_THRESH_TPD_MASK)); 2768126353Smlaier 2769126353Smlaier /* Set CMB/SMB timer and enable them. */ 2770126353Smlaier CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2771171172Smlaier ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2772126353Smlaier ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2773126353Smlaier /* Request SMB updates for every seconds. */ 2774126353Smlaier CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2775126353Smlaier CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2776171172Smlaier 2777126353Smlaier /* 2778126353Smlaier * Disable all WOL bits as WOL can interfere normal Rx 2779171172Smlaier * operation. 2780126353Smlaier */ 2781126353Smlaier CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2782126353Smlaier 2783126353Smlaier /* 2784126353Smlaier * Configure Tx/Rx MACs. 2785126353Smlaier * - Auto-padding for short frames. 2786126353Smlaier * - Enable CRC generation. 2787126353Smlaier * Start with full-duplex/1000Mbps media. Actual reconfiguration 2788171172Smlaier * of MAC is followed after link establishment. 2789126353Smlaier */ 2790126353Smlaier CSR_WRITE_4(sc, AGE_MAC_CFG, 2791126353Smlaier MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2792126353Smlaier MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2793126353Smlaier ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2794126353Smlaier MAC_CFG_PREAMBLE_MASK)); 2795171172Smlaier /* Set up the receive filter. */ 2796171172Smlaier age_rxfilter(sc); 2797171172Smlaier age_rxvlan(sc); 2798171172Smlaier 2799171172Smlaier reg = CSR_READ_4(sc, AGE_MAC_CFG); 2800171172Smlaier if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2801126353Smlaier reg |= MAC_CFG_RXCSUM_ENB; 2802126353Smlaier 2803126353Smlaier /* Ack all pending interrupts and clear it. */ 2804126353Smlaier CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2805126353Smlaier CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2806126353Smlaier 2807126353Smlaier /* Finally enable Tx/Rx MAC. */ 2808126353Smlaier CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2809171172Smlaier 2810171172Smlaier sc->age_flags &= ~AGE_FLAG_LINK; 2811126353Smlaier /* Switch to the current media. */ 2812126353Smlaier mii_mediachg(mii); 2813171172Smlaier 2814171172Smlaier callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2815126353Smlaier 2816126353Smlaier ifp->if_drv_flags |= IFF_DRV_RUNNING; 2817126353Smlaier ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2818126353Smlaier} 2819171172Smlaier 2820171172Smlaierstatic void 2821126353Smlaierage_stop(struct age_softc *sc) 2822126353Smlaier{ 2823171172Smlaier struct ifnet *ifp; 2824126353Smlaier struct age_txdesc *txd; 2825126353Smlaier struct age_rxdesc *rxd; 2826126353Smlaier uint32_t reg; 2827126353Smlaier int i; 2828126353Smlaier 2829126353Smlaier AGE_LOCK_ASSERT(sc); 2830126353Smlaier /* 2831171172Smlaier * Mark the interface down and cancel the watchdog timer. 2832223637Sbz */ 2833223637Sbz ifp = sc->age_ifp; 2834126353Smlaier ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2835126353Smlaier sc->age_flags &= ~AGE_FLAG_LINK; 2836223637Sbz callout_stop(&sc->age_tick_ch); 2837126353Smlaier sc->age_watchdog_timer = 0; 2838126353Smlaier 2839126353Smlaier /* 2840126353Smlaier * Disable interrupts. 2841126353Smlaier */ 2842126353Smlaier CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2843171172Smlaier CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2844223637Sbz /* Stop CMB/SMB updates. */ 2845126353Smlaier CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2846130614Smlaier /* Stop Rx/Tx MAC. */ 2847223637Sbz age_stop_rxmac(sc); 2848130614Smlaier age_stop_txmac(sc); 2849126353Smlaier /* Stop DMA. */ 2850126353Smlaier CSR_WRITE_4(sc, AGE_DMA_CFG, 2851171172Smlaier CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2852171172Smlaier /* Stop TxQ/RxQ. */ 2853126353Smlaier CSR_WRITE_4(sc, AGE_TXQ_CFG, 2854126353Smlaier CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2855171172Smlaier CSR_WRITE_4(sc, AGE_RXQ_CFG, 2856171172Smlaier CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2857171172Smlaier for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2858126353Smlaier if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2859223637Sbz break; 2860171172Smlaier DELAY(10); 2861126353Smlaier } 2862223637Sbz if (i == 0) 2863126353Smlaier device_printf(sc->age_dev, 2864126353Smlaier "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2865171172Smlaier 2866145840Smlaier /* Reclaim Rx buffers that have been processed. */ 2867171172Smlaier if (sc->age_cdata.age_rxhead != NULL) 2868126353Smlaier m_freem(sc->age_cdata.age_rxhead); 2869171172Smlaier AGE_RXCHAIN_RESET(sc); 2870171172Smlaier /* 2871145840Smlaier * Free RX and TX mbufs still in the queues. 2872171172Smlaier */ 2873126353Smlaier for (i = 0; i < AGE_RX_RING_CNT; i++) { 2874126353Smlaier rxd = &sc->age_cdata.age_rxdesc[i]; 2875171172Smlaier if (rxd->rx_m != NULL) { 2876171172Smlaier bus_dmamap_sync(sc->age_cdata.age_rx_tag, 2877171172Smlaier rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2878126353Smlaier bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2879145840Smlaier rxd->rx_dmamap); 2880171172Smlaier m_freem(rxd->rx_m); 2881126353Smlaier rxd->rx_m = NULL; 2882171172Smlaier } 2883171172Smlaier } 2884145840Smlaier for (i = 0; i < AGE_TX_RING_CNT; i++) { 2885171172Smlaier txd = &sc->age_cdata.age_txdesc[i]; 2886126353Smlaier if (txd->tx_m != NULL) { 2887126353Smlaier bus_dmamap_sync(sc->age_cdata.age_tx_tag, 2888126353Smlaier txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2889223637Sbz bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2890126353Smlaier txd->tx_dmamap); 2891171172Smlaier m_freem(txd->tx_m); 2892126353Smlaier txd->tx_m = NULL; 2893223637Sbz } 2894126353Smlaier } 2895126353Smlaier} 2896126353Smlaier 2897223637Sbzstatic void 2898223637Sbzage_stop_txmac(struct age_softc *sc) 2899126353Smlaier{ 2900126353Smlaier uint32_t reg; 2901126353Smlaier int i; 2902126353Smlaier 2903126353Smlaier AGE_LOCK_ASSERT(sc); 2904126353Smlaier 2905171172Smlaier reg = CSR_READ_4(sc, AGE_MAC_CFG); 2906223637Sbz if ((reg & MAC_CFG_TX_ENB) != 0) { 2907126353Smlaier reg &= ~MAC_CFG_TX_ENB; 2908171172Smlaier CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2909171172Smlaier } 2910126353Smlaier /* Stop Tx DMA engine. */ 2911126353Smlaier reg = CSR_READ_4(sc, AGE_DMA_CFG); 2912126353Smlaier if ((reg & DMA_CFG_RD_ENB) != 0) { 2913145840Smlaier reg &= ~DMA_CFG_RD_ENB; 2914126353Smlaier CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2915126353Smlaier } 2916126353Smlaier for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2917126353Smlaier if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2918126353Smlaier (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2919126353Smlaier break; 2920126353Smlaier DELAY(10); 2921126353Smlaier } 2922145840Smlaier if (i == 0) 2923126353Smlaier device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2924171172Smlaier} 2925126353Smlaier 2926126353Smlaierstatic void 2927126353Smlaierage_stop_rxmac(struct age_softc *sc) 2928126353Smlaier{ 2929223637Sbz uint32_t reg; 2930223637Sbz int i; 2931223637Sbz 2932223637Sbz AGE_LOCK_ASSERT(sc); 2933171172Smlaier 2934126353Smlaier reg = CSR_READ_4(sc, AGE_MAC_CFG); 2935126353Smlaier if ((reg & MAC_CFG_RX_ENB) != 0) { 2936126353Smlaier reg &= ~MAC_CFG_RX_ENB; 2937126353Smlaier CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2938126353Smlaier } 2939126353Smlaier /* Stop Rx DMA engine. */ 2940126353Smlaier reg = CSR_READ_4(sc, AGE_DMA_CFG); 2941126353Smlaier if ((reg & DMA_CFG_WR_ENB) != 0) { 2942126353Smlaier reg &= ~DMA_CFG_WR_ENB; 2943171172Smlaier CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2944240233Sglebius } 2945126353Smlaier for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2946240233Sglebius if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2947126353Smlaier (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2948126353Smlaier break; 2949171172Smlaier DELAY(10); 2950126353Smlaier } 2951171172Smlaier if (i == 0) 2952223637Sbz device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2953223637Sbz} 2954223637Sbz 2955126353Smlaierstatic void 2956126353Smlaierage_init_tx_ring(struct age_softc *sc) 2957126353Smlaier{ 2958126353Smlaier struct age_ring_data *rd; 2959126353Smlaier struct age_txdesc *txd; 2960126353Smlaier int i; 2961126353Smlaier 2962126353Smlaier AGE_LOCK_ASSERT(sc); 2963126353Smlaier 2964126353Smlaier sc->age_cdata.age_tx_prod = 0; 2965171172Smlaier sc->age_cdata.age_tx_cons = 0; 2966126353Smlaier sc->age_cdata.age_tx_cnt = 0; 2967171172Smlaier 2968126353Smlaier rd = &sc->age_rdata; 2969126353Smlaier bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2970126353Smlaier for (i = 0; i < AGE_TX_RING_CNT; i++) { 2971126353Smlaier txd = &sc->age_cdata.age_txdesc[i]; 2972126353Smlaier txd->tx_desc = &rd->age_tx_ring[i]; 2973171172Smlaier txd->tx_m = NULL; 2974126353Smlaier } 2975126353Smlaier 2976126353Smlaier bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2977126353Smlaier sc->age_cdata.age_tx_ring_map, 2978126353Smlaier BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2979126353Smlaier} 2980126353Smlaier 2981126353Smlaierstatic int 2982126353Smlaierage_init_rx_ring(struct age_softc *sc) 2983223637Sbz{ 2984126353Smlaier struct age_ring_data *rd; 2985126353Smlaier struct age_rxdesc *rxd; 2986126353Smlaier int i; 2987223637Sbz 2988130614Smlaier AGE_LOCK_ASSERT(sc); 2989145840Smlaier 2990145840Smlaier sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2991145840Smlaier sc->age_morework = 0; 2992171172Smlaier rd = &sc->age_rdata; 2993171172Smlaier bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 2994126353Smlaier for (i = 0; i < AGE_RX_RING_CNT; i++) { 2995126353Smlaier rxd = &sc->age_cdata.age_rxdesc[i]; 2996126353Smlaier rxd->rx_m = NULL; 2997126353Smlaier rxd->rx_desc = &rd->age_rx_ring[i]; 2998126353Smlaier if (age_newbuf(sc, rxd) != 0) 2999126353Smlaier return (ENOBUFS); 3000126353Smlaier } 3001126353Smlaier 3002126353Smlaier bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 3003126353Smlaier sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 3004130614Smlaier 3005126353Smlaier return (0); 3006126353Smlaier} 3007126353Smlaier 3008130614Smlaierstatic void 3009126353Smlaierage_init_rr_ring(struct age_softc *sc) 3010126353Smlaier{ 3011126353Smlaier struct age_ring_data *rd; 3012130614Smlaier 3013126353Smlaier AGE_LOCK_ASSERT(sc); 3014126353Smlaier 3015126353Smlaier sc->age_cdata.age_rr_cons = 0; 3016126353Smlaier AGE_RXCHAIN_RESET(sc); 3017126353Smlaier 3018126353Smlaier rd = &sc->age_rdata; 3019126353Smlaier bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 3020126353Smlaier bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 3021126353Smlaier sc->age_cdata.age_rr_ring_map, 3022126353Smlaier BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3023126353Smlaier} 3024126353Smlaier 3025126353Smlaierstatic void 3026126353Smlaierage_init_cmb_block(struct age_softc *sc) 3027126353Smlaier{ 3028223637Sbz struct age_ring_data *rd; 3029126353Smlaier 3030126353Smlaier AGE_LOCK_ASSERT(sc); 3031223637Sbz 3032126353Smlaier rd = &sc->age_rdata; 3033126353Smlaier bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 3034126353Smlaier bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 3035126353Smlaier sc->age_cdata.age_cmb_block_map, 3036126353Smlaier BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3037126353Smlaier} 3038126353Smlaier 3039126353Smlaierstatic void 3040126353Smlaierage_init_smb_block(struct age_softc *sc) 3041126353Smlaier{ 3042126353Smlaier struct age_ring_data *rd; 3043126353Smlaier 3044141456Smlaier AGE_LOCK_ASSERT(sc); 3045171172Smlaier 3046126353Smlaier rd = &sc->age_rdata; 3047126353Smlaier bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 3048126353Smlaier bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 3049126353Smlaier sc->age_cdata.age_smb_block_map, 3050126353Smlaier BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3051223637Sbz} 3052130614Smlaier 3053126353Smlaierstatic int 3054126353Smlaierage_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 3055126353Smlaier{ 3056126353Smlaier struct rx_desc *desc; 3057126353Smlaier struct mbuf *m; 3058126353Smlaier bus_dma_segment_t segs[1]; 3059126353Smlaier bus_dmamap_t map; 3060126353Smlaier int nsegs; 3061269498Sgjb 3062126353Smlaier AGE_LOCK_ASSERT(sc); 3063126353Smlaier 3064126353Smlaier m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3065126353Smlaier if (m == NULL) 3066126353Smlaier return (ENOBUFS); 3067 m->m_len = m->m_pkthdr.len = MCLBYTES; 3068 m_adj(m, ETHER_ALIGN); 3069 3070 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, 3071 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3072 m_freem(m); 3073 return (ENOBUFS); 3074 } 3075 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3076 3077 if (rxd->rx_m != NULL) { 3078 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3079 BUS_DMASYNC_POSTREAD); 3080 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 3081 } 3082 map = rxd->rx_dmamap; 3083 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 3084 sc->age_cdata.age_rx_sparemap = map; 3085 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3086 BUS_DMASYNC_PREREAD); 3087 rxd->rx_m = m; 3088 3089 desc = rxd->rx_desc; 3090 desc->addr = htole64(segs[0].ds_addr); 3091 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 3092 AGE_RD_LEN_SHIFT); 3093 return (0); 3094} 3095 3096static void 3097age_rxvlan(struct age_softc *sc) 3098{ 3099 struct ifnet *ifp; 3100 uint32_t reg; 3101 3102 AGE_LOCK_ASSERT(sc); 3103 3104 ifp = sc->age_ifp; 3105 reg = CSR_READ_4(sc, AGE_MAC_CFG); 3106 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3107 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3108 reg |= MAC_CFG_VLAN_TAG_STRIP; 3109 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 3110} 3111 3112static void 3113age_rxfilter(struct age_softc *sc) 3114{ 3115 struct ifnet *ifp; 3116 struct ifmultiaddr *ifma; 3117 uint32_t crc; 3118 uint32_t mchash[2]; 3119 uint32_t rxcfg; 3120 3121 AGE_LOCK_ASSERT(sc); 3122 3123 ifp = sc->age_ifp; 3124 3125 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 3126 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3127 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3128 rxcfg |= MAC_CFG_BCAST; 3129 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3130 if ((ifp->if_flags & IFF_PROMISC) != 0) 3131 rxcfg |= MAC_CFG_PROMISC; 3132 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3133 rxcfg |= MAC_CFG_ALLMULTI; 3134 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 3135 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 3136 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3137 return; 3138 } 3139 3140 /* Program new filter. */ 3141 bzero(mchash, sizeof(mchash)); 3142 3143 if_maddr_rlock(ifp); 3144 TAILQ_FOREACH(ifma, &sc->age_ifp->if_multiaddrs, ifma_link) { 3145 if (ifma->ifma_addr->sa_family != AF_LINK) 3146 continue; 3147 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3148 ifma->ifma_addr), ETHER_ADDR_LEN); 3149 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3150 } 3151 if_maddr_runlock(ifp); 3152 3153 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 3154 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 3155 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3156} 3157 3158static int 3159sysctl_age_stats(SYSCTL_HANDLER_ARGS) 3160{ 3161 struct age_softc *sc; 3162 struct age_stats *stats; 3163 int error, result; 3164 3165 result = -1; 3166 error = sysctl_handle_int(oidp, &result, 0, req); 3167 3168 if (error != 0 || req->newptr == NULL) 3169 return (error); 3170 3171 if (result != 1) 3172 return (error); 3173 3174 sc = (struct age_softc *)arg1; 3175 stats = &sc->age_stat; 3176 printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 3177 printf("Transmit good frames : %ju\n", 3178 (uintmax_t)stats->tx_frames); 3179 printf("Transmit good broadcast frames : %ju\n", 3180 (uintmax_t)stats->tx_bcast_frames); 3181 printf("Transmit good multicast frames : %ju\n", 3182 (uintmax_t)stats->tx_mcast_frames); 3183 printf("Transmit pause control frames : %u\n", 3184 stats->tx_pause_frames); 3185 printf("Transmit control frames : %u\n", 3186 stats->tx_control_frames); 3187 printf("Transmit frames with excessive deferrals : %u\n", 3188 stats->tx_excess_defer); 3189 printf("Transmit deferrals : %u\n", 3190 stats->tx_deferred); 3191 printf("Transmit good octets : %ju\n", 3192 (uintmax_t)stats->tx_bytes); 3193 printf("Transmit good broadcast octets : %ju\n", 3194 (uintmax_t)stats->tx_bcast_bytes); 3195 printf("Transmit good multicast octets : %ju\n", 3196 (uintmax_t)stats->tx_mcast_bytes); 3197 printf("Transmit frames 64 bytes : %ju\n", 3198 (uintmax_t)stats->tx_pkts_64); 3199 printf("Transmit frames 65 to 127 bytes : %ju\n", 3200 (uintmax_t)stats->tx_pkts_65_127); 3201 printf("Transmit frames 128 to 255 bytes : %ju\n", 3202 (uintmax_t)stats->tx_pkts_128_255); 3203 printf("Transmit frames 256 to 511 bytes : %ju\n", 3204 (uintmax_t)stats->tx_pkts_256_511); 3205 printf("Transmit frames 512 to 1024 bytes : %ju\n", 3206 (uintmax_t)stats->tx_pkts_512_1023); 3207 printf("Transmit frames 1024 to 1518 bytes : %ju\n", 3208 (uintmax_t)stats->tx_pkts_1024_1518); 3209 printf("Transmit frames 1519 to MTU bytes : %ju\n", 3210 (uintmax_t)stats->tx_pkts_1519_max); 3211 printf("Transmit single collisions : %u\n", 3212 stats->tx_single_colls); 3213 printf("Transmit multiple collisions : %u\n", 3214 stats->tx_multi_colls); 3215 printf("Transmit late collisions : %u\n", 3216 stats->tx_late_colls); 3217 printf("Transmit abort due to excessive collisions : %u\n", 3218 stats->tx_excess_colls); 3219 printf("Transmit underruns due to FIFO underruns : %u\n", 3220 stats->tx_underrun); 3221 printf("Transmit descriptor write-back errors : %u\n", 3222 stats->tx_desc_underrun); 3223 printf("Transmit frames with length mismatched frame size : %u\n", 3224 stats->tx_lenerrs); 3225 printf("Transmit frames with truncated due to MTU size : %u\n", 3226 stats->tx_lenerrs); 3227 3228 printf("Receive good frames : %ju\n", 3229 (uintmax_t)stats->rx_frames); 3230 printf("Receive good broadcast frames : %ju\n", 3231 (uintmax_t)stats->rx_bcast_frames); 3232 printf("Receive good multicast frames : %ju\n", 3233 (uintmax_t)stats->rx_mcast_frames); 3234 printf("Receive pause control frames : %u\n", 3235 stats->rx_pause_frames); 3236 printf("Receive control frames : %u\n", 3237 stats->rx_control_frames); 3238 printf("Receive CRC errors : %u\n", 3239 stats->rx_crcerrs); 3240 printf("Receive frames with length errors : %u\n", 3241 stats->rx_lenerrs); 3242 printf("Receive good octets : %ju\n", 3243 (uintmax_t)stats->rx_bytes); 3244 printf("Receive good broadcast octets : %ju\n", 3245 (uintmax_t)stats->rx_bcast_bytes); 3246 printf("Receive good multicast octets : %ju\n", 3247 (uintmax_t)stats->rx_mcast_bytes); 3248 printf("Receive frames too short : %u\n", 3249 stats->rx_runts); 3250 printf("Receive fragmented frames : %ju\n", 3251 (uintmax_t)stats->rx_fragments); 3252 printf("Receive frames 64 bytes : %ju\n", 3253 (uintmax_t)stats->rx_pkts_64); 3254 printf("Receive frames 65 to 127 bytes : %ju\n", 3255 (uintmax_t)stats->rx_pkts_65_127); 3256 printf("Receive frames 128 to 255 bytes : %ju\n", 3257 (uintmax_t)stats->rx_pkts_128_255); 3258 printf("Receive frames 256 to 511 bytes : %ju\n", 3259 (uintmax_t)stats->rx_pkts_256_511); 3260 printf("Receive frames 512 to 1024 bytes : %ju\n", 3261 (uintmax_t)stats->rx_pkts_512_1023); 3262 printf("Receive frames 1024 to 1518 bytes : %ju\n", 3263 (uintmax_t)stats->rx_pkts_1024_1518); 3264 printf("Receive frames 1519 to MTU bytes : %ju\n", 3265 (uintmax_t)stats->rx_pkts_1519_max); 3266 printf("Receive frames too long : %ju\n", 3267 (uint64_t)stats->rx_pkts_truncated); 3268 printf("Receive frames with FIFO overflow : %u\n", 3269 stats->rx_fifo_oflows); 3270 printf("Receive frames with return descriptor overflow : %u\n", 3271 stats->rx_desc_oflows); 3272 printf("Receive frames with alignment errors : %u\n", 3273 stats->rx_alignerrs); 3274 printf("Receive frames dropped due to address filtering : %ju\n", 3275 (uint64_t)stats->rx_pkts_filtered); 3276 3277 return (error); 3278} 3279 3280static int 3281sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3282{ 3283 int error, value; 3284 3285 if (arg1 == NULL) 3286 return (EINVAL); 3287 value = *(int *)arg1; 3288 error = sysctl_handle_int(oidp, &value, 0, req); 3289 if (error || req->newptr == NULL) 3290 return (error); 3291 if (value < low || value > high) 3292 return (EINVAL); 3293 *(int *)arg1 = value; 3294 3295 return (0); 3296} 3297 3298static int 3299sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) 3300{ 3301 return (sysctl_int_range(oidp, arg1, arg2, req, 3302 AGE_PROC_MIN, AGE_PROC_MAX)); 3303} 3304 3305static int 3306sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 3307{ 3308 3309 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 3310 AGE_IM_TIMER_MAX)); 3311} 3312