1183567Sstas/*- 2183567Sstas * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>. 3183567Sstas * All rights reserved. 4183567Sstas * 5183567Sstas * Redistribution and use in source and binary forms, with or without 6183567Sstas * modification, are permitted provided that the following conditions 7183567Sstas * are met: 8183567Sstas * 1. Redistributions of source code must retain the above copyright 9183567Sstas * notice, this list of conditions and the following disclaimer. 10183567Sstas * 2. Redistributions in binary form must reproduce the above copyright 11183567Sstas * notice, this list of conditions and the following disclaimer in the 12183567Sstas * documentation and/or other materials provided with the distribution. 13183567Sstas * 14183567Sstas * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15183567Sstas * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16183567Sstas * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17183567Sstas * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18183567Sstas * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19183567Sstas * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20183567Sstas * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21183567Sstas * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22183567Sstas * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23183567Sstas * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24183567Sstas * 25183567Sstas * $FreeBSD$ 26183567Sstas */ 27183567Sstas 28183567Sstas#ifndef IF_AEVAR_H 29183567Sstas#define IF_AEVAR_H 30183567Sstas 31183567Sstas/* 32183567Sstas * Supported chips identifiers. 33183567Sstas*/ 34183567Sstas#define VENDORID_ATTANSIC 0x1969 35183567Sstas#define DEVICEID_ATTANSIC_L2 0x2048 36183567Sstas 37183567Sstas/* How much to wait for reset to complete (10 microsecond units). */ 38183567Sstas#define AE_RESET_TIMEOUT 100 39183567Sstas 40183567Sstas/* How much to wait for device to enter idle state (100 microsecond units). */ 41183567Sstas#define AE_IDLE_TIMEOUT 100 42183567Sstas 43183567Sstas/* How much to wait for MDIO to do the work (2 microsecond units). */ 44183567Sstas#define AE_MDIO_TIMEOUT 10 45183567Sstas 46183567Sstas/* How much to wait for VPD reading operation to complete (2 ms units). */ 47183567Sstas#define AE_VPD_TIMEOUT 10 48183567Sstas 49183567Sstas/* How much to wait for send operation to complete (HZ units). */ 50183567Sstas#define AE_TX_TIMEOUT 5 51183567Sstas 52183567Sstas/* Default PHY address. */ 53183567Sstas#define AE_PHYADDR_DEFAULT 0 54183567Sstas 55183567Sstas/* Tx packet descriptor header format. */ 56183567Sstastypedef struct ae_txd { 57183567Sstas uint16_t len; 58183567Sstas uint16_t vlan; 59183567Sstas} __packed ae_txd_t; 60183567Sstas 61183567Sstas/* Tx status descriptor format. */ 62183567Sstastypedef struct ae_txs { 63183567Sstas uint16_t len; 64183567Sstas uint16_t flags; 65183567Sstas} __packed ae_txs_t; 66183567Sstas 67183567Sstas/* Rx packet descriptor format. */ 68183567Sstastypedef struct ae_rxd { 69183567Sstas uint16_t len; 70183567Sstas uint16_t flags; 71183567Sstas uint16_t vlan; 72183567Sstas uint16_t __pad; 73183567Sstas uint8_t data[1528]; 74183567Sstas} __packed ae_rxd_t; 75183567Sstas 76183567Sstas/* Statistics. */ 77183567Sstastypedef struct ae_stats { 78183567Sstas uint32_t rx_bcast; 79183567Sstas uint32_t rx_mcast; 80183567Sstas uint32_t rx_pause; 81183567Sstas uint32_t rx_ctrl; 82183567Sstas uint32_t rx_crcerr; 83183567Sstas uint32_t rx_codeerr; 84183567Sstas uint32_t rx_runt; 85183567Sstas uint32_t rx_frag; 86183567Sstas uint32_t rx_trunc; 87183567Sstas uint32_t rx_align; 88183567Sstas uint32_t tx_bcast; 89183567Sstas uint32_t tx_mcast; 90183567Sstas uint32_t tx_pause; 91183567Sstas uint32_t tx_ctrl; 92183567Sstas uint32_t tx_defer; 93183567Sstas uint32_t tx_excdefer; 94183567Sstas uint32_t tx_singlecol; 95183567Sstas uint32_t tx_multicol; 96183567Sstas uint32_t tx_latecol; 97183567Sstas uint32_t tx_abortcol; 98183567Sstas uint32_t tx_underrun; 99183567Sstas} ae_stats_t; 100183567Sstas 101183567Sstas/* Software state structure. */ 102183567Sstastypedef struct ae_softc { 103183567Sstas struct ifnet *ifp; 104183567Sstas device_t dev; 105183567Sstas device_t miibus; 106183567Sstas struct resource *mem[1]; 107183567Sstas struct resource_spec *spec_mem; 108183567Sstas struct resource *irq[1]; 109183567Sstas struct resource_spec *spec_irq; 110183567Sstas void *intrhand; 111183567Sstas 112183567Sstas struct mtx mtx; 113183567Sstas 114183567Sstas uint8_t eaddr[ETHER_ADDR_LEN]; 115183567Sstas uint8_t flags; 116183567Sstas int if_flags; 117183567Sstas 118183567Sstas struct callout tick_ch; 119183567Sstas 120183567Sstas /* Tasks. */ 121183567Sstas struct task int_task; 122183567Sstas struct task link_task; 123183567Sstas struct taskqueue *tq; 124183567Sstas 125183567Sstas /* DMA tags. */ 126183567Sstas bus_dma_tag_t dma_parent_tag; 127183567Sstas bus_dma_tag_t dma_rxd_tag; 128183567Sstas bus_dma_tag_t dma_txd_tag; 129183567Sstas bus_dma_tag_t dma_txs_tag; 130183567Sstas bus_dmamap_t dma_rxd_map; 131183567Sstas bus_dmamap_t dma_txd_map; 132183567Sstas bus_dmamap_t dma_txs_map; 133183567Sstas 134183567Sstas bus_addr_t dma_rxd_busaddr; 135183567Sstas bus_addr_t dma_txd_busaddr; 136183567Sstas bus_addr_t dma_txs_busaddr; 137183567Sstas 138183567Sstas char *rxd_base_dma; /* Start of allocated area. */ 139183567Sstas ae_rxd_t *rxd_base; /* Start of RxD ring. */ 140183567Sstas char *txd_base; /* Start of TxD ring. */ 141183567Sstas ae_txs_t *txs_base; /* Start of TxS ring. */ 142183567Sstas 143183567Sstas /* Ring pointers. */ 144183567Sstas unsigned int rxd_cur; 145183567Sstas unsigned int txd_cur; 146183567Sstas unsigned int txs_cur; 147183567Sstas unsigned int txs_ack; 148183567Sstas unsigned int txd_ack; 149183567Sstas 150183567Sstas int tx_inproc; /* Active Tx frames in ring. */ 151183567Sstas int wd_timer; 152183567Sstas 153183567Sstas ae_stats_t stats; 154183567Sstas} ae_softc_t; 155183567Sstas 156183567Sstas#define AE_LOCK(_sc) mtx_lock(&(_sc)->mtx) 157183567Sstas#define AE_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 158183567Sstas#define AE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) 159183567Sstas 160183567Sstas#define BUS_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 161183567Sstas#define BUS_ADDR_HI(x) ((uint64_t) (x) >> 32) 162183567Sstas 163183567Sstas#define AE_FLAG_LINK 0x01 /* Has link. */ 164183567Sstas#define AE_FLAG_DETACH 0x02 /* Is detaching. */ 165183567Sstas#define AE_FLAG_TXAVAIL 0x04 /* Tx'es available. */ 166183567Sstas#define AE_FLAG_MSI 0x08 /* Using MSI. */ 167183567Sstas#define AE_FLAG_PMG 0x10 /* Supports PCI power management. */ 168183567Sstas 169183567Sstas#endif /* IF_AEVAR_H */ 170