octeon-pci-console.c revision 215990
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46#define CVMX_USE_1_TO_1_TLB_MAPPINGS 0 47#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 48#include <linux/kernel.h> 49#include <asm/octeon/cvmx.h> 50#include <asm/octeon/cvmx-spinlock.h> 51#include <asm/octeon/octeon-pci-console.h> 52 53#define MIN(a,b) min((a),(b)) 54 55#else 56#include "cvmx-platform.h" 57 58#include "cvmx.h" 59#include "cvmx-spinlock.h" 60#define MIN(a,b) (((a)<(b))?(a):(b)) 61 62#include "cvmx-bootmem.h" 63#include "octeon-pci-console.h" 64#endif 65 66 67#if defined(__linux__) && !defined(__KERNEL__) && !defined(OCTEON_TARGET) 68#include "octeon-pci.h" 69#endif 70 71 72/* The following code is only used in standalone CVMX applications. It does 73 not apply for kernel or Linux programming */ 74#if defined(OCTEON_TARGET) && !defined(__linux__) 75 76static int cvmx_pci_console_num = 0; 77static int per_core_pci_consoles = 0; 78static uint64_t pci_console_desc_addr = 0; 79/* This function for simple executive internal use only - do not use in any application */ 80int __cvmx_pci_console_write (int fd, char *buf, int nbytes) 81{ 82 int console_num; 83 if (fd >= 0x10000000) 84 { 85 console_num = fd & 0xFFFF; 86 } 87 else if (per_core_pci_consoles) 88 { 89 console_num = cvmx_get_core_num(); 90 } 91 else 92 console_num = cvmx_pci_console_num; 93 94 if (!pci_console_desc_addr) 95 { 96 const cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block(OCTEON_PCI_CONSOLE_BLOCK_NAME); 97 pci_console_desc_addr = block_desc->base_addr; 98 } 99 100 101 return octeon_pci_console_write(pci_console_desc_addr, console_num, buf, nbytes, 0); 102 103} 104 105#endif 106 107 108#if !defined(CONFIG_OCTEON_U_BOOT) || (defined(CONFIG_OCTEON_U_BOOT) && defined(CFG_PCI_CONSOLE)) 109int octeon_pci_console_buffer_free_bytes(uint32_t buffer_size, uint32_t wr_idx, uint32_t rd_idx) 110{ 111 if (rd_idx >= buffer_size || wr_idx >= buffer_size) 112 return -1; 113 114 return (((buffer_size -1) - (wr_idx - rd_idx))%buffer_size); 115} 116int octeon_pci_console_buffer_avail_bytes(uint32_t buffer_size, uint32_t wr_idx, uint32_t rd_idx) 117{ 118 if (rd_idx >= buffer_size || wr_idx >= buffer_size) 119 return -1; 120 121 return (buffer_size - 1 - octeon_pci_console_buffer_free_bytes(buffer_size, wr_idx, rd_idx)); 122} 123#endif 124 125 126 127/* The following code is only used under Linux userspace when you are using 128 CVMX */ 129#if defined(__linux__) && !defined(__KERNEL__) && !defined(OCTEON_TARGET) 130int octeon_pci_console_host_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int write_reqest_size, uint32_t flags) 131{ 132 if (!console_desc_addr) 133 return -1; 134 135 /* Get global pci console information and look up specific console structure. */ 136 uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles)); 137// printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size); 138 if (console_num >= num_consoles) 139 { 140 printf("ERROR: attempting to read non-existant console: %d\n", console_num); 141 return(-1); 142 } 143 uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8); 144// printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr); 145 146 uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size)); 147 /* Check to see if any data is available */ 148 uint32_t rd_idx, wr_idx; 149 uint64_t base_addr; 150 151 base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, input_base_addr)); 152 rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_read_index)); 153 wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index)); 154 155// printf("Input base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx); 156 int bytes_to_write = octeon_pci_console_buffer_free_bytes(console_buffer_size, wr_idx, rd_idx); 157 if (bytes_to_write <= 0) 158 return bytes_to_write; 159 bytes_to_write = MIN(bytes_to_write, write_reqest_size); 160 /* Check to see if what we want to write is not contiguous, and limit ourselves to the contiguous block*/ 161 if (wr_idx + bytes_to_write >= console_buffer_size) 162 bytes_to_write = console_buffer_size - wr_idx; 163 164// printf("Attempting to write %d bytes, (buf size: %d)\n", bytes_to_write, write_reqest_size); 165 166 octeon_pci_write_mem(base_addr + wr_idx, buffer, bytes_to_write, OCTEON_PCI_ENDIAN_64BIT_SWAP); 167 octeon_write_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index), (wr_idx + bytes_to_write)%console_buffer_size); 168 169 return bytes_to_write; 170 171} 172 173int octeon_pci_console_host_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buf_size, uint32_t flags) 174{ 175 if (!console_desc_addr) 176 return -1; 177 178 /* Get global pci console information and look up specific console structure. */ 179 uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles)); 180// printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size); 181 if (console_num >= num_consoles) 182 { 183 printf("ERROR: attempting to read non-existant console: %d\n", console_num); 184 return(-1); 185 } 186 uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8); 187 uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size)); 188// printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr); 189 190 /* Check to see if any data is available */ 191 uint32_t rd_idx, wr_idx; 192 uint64_t base_addr; 193 194 base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, output_base_addr)); 195 rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index)); 196 wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_write_index)); 197 198// printf("Read buffer base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx); 199 int bytes_to_read = octeon_pci_console_buffer_avail_bytes(console_buffer_size, wr_idx, rd_idx); 200 if (bytes_to_read <= 0) 201 return bytes_to_read; 202 203 204 bytes_to_read = MIN(bytes_to_read, buf_size); 205 /* Check to see if what we want to read is not contiguous, and limit ourselves to the contiguous block*/ 206 if (rd_idx + bytes_to_read >= console_buffer_size) 207 bytes_to_read = console_buffer_size - rd_idx; 208 209 210 octeon_pci_read_mem(buffer, base_addr + rd_idx, bytes_to_read,OCTEON_PCI_ENDIAN_64BIT_SWAP); 211 octeon_write_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index), (rd_idx + bytes_to_read)%console_buffer_size); 212 213 return bytes_to_read; 214} 215 216 217int octeon_pci_console_host_write_avail(uint64_t console_desc_addr, unsigned int console_num) 218{ 219 if (!console_desc_addr) 220 return -1; 221 222 /* Get global pci console information and look up specific console structure. */ 223 uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles)); 224// printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size); 225 if (console_num >= num_consoles) 226 { 227 printf("ERROR: attempting to read non-existant console: %d\n", console_num); 228 return -1; 229 } 230 uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8); 231// printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr); 232 233 uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size)); 234 /* Check to see if any data is available */ 235 uint32_t rd_idx, wr_idx; 236 uint64_t base_addr; 237 238 base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, input_base_addr)); 239 rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_read_index)); 240 wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index)); 241 242// printf("Input base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx); 243 return octeon_pci_console_buffer_free_bytes(console_buffer_size, wr_idx, rd_idx); 244} 245 246 247int octeon_pci_console_host_read_avail(uint64_t console_desc_addr, unsigned int console_num) 248{ 249 if (!console_desc_addr) 250 return -1; 251 252 /* Get global pci console information and look up specific console structure. */ 253 uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles)); 254// printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size); 255 if (console_num >= num_consoles) 256 { 257 printf("ERROR: attempting to read non-existant console: %d\n", console_num); 258 return(-1); 259 } 260 uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8); 261 uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size)); 262// printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr); 263 264 /* Check to see if any data is available */ 265 uint32_t rd_idx, wr_idx; 266 uint64_t base_addr; 267 268 base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, output_base_addr)); 269 rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index)); 270 wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_write_index)); 271 272// printf("Read buffer base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx); 273 return octeon_pci_console_buffer_avail_bytes(console_buffer_size, wr_idx, rd_idx); 274} 275 276 277#endif /* TARGET_HOST */ 278 279 280 281 282 283 284/* This code is only available in a kernel or CVMX standalone. It can't be used 285 from userspace */ 286#if (!defined(CONFIG_OCTEON_U_BOOT) && (!defined(__linux__) || defined(__KERNEL__))) || (defined(CONFIG_OCTEON_U_BOOT) && defined(CFG_PCI_CONSOLE)) 287 288static octeon_pci_console_t *octeon_pci_console_get_ptr(uint64_t console_desc_addr, unsigned int console_num) 289{ 290 octeon_pci_console_desc_t *cons_desc_ptr; 291 292 if (!console_desc_addr) 293 return NULL; 294 295 cons_desc_ptr = (octeon_pci_console_desc_t *)cvmx_phys_to_ptr(console_desc_addr); 296 if (console_num >= cons_desc_ptr->num_consoles) 297 return NULL; 298 299 return (octeon_pci_console_t *)cvmx_phys_to_ptr(cons_desc_ptr->console_addr_array[console_num]); 300} 301 302 303int octeon_pci_console_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int bytes_to_write, uint32_t flags) 304{ 305 octeon_pci_console_t *cons_ptr; 306 cvmx_spinlock_t *lock; 307 int bytes_available; 308 char *buf_ptr; 309 int bytes_written; 310 311 cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num); 312 if (!cons_ptr) 313 return -1; 314 315 lock = (cvmx_spinlock_t *)&cons_ptr->lock; 316 317 buf_ptr = (char*)cvmx_phys_to_ptr(cons_ptr->output_base_addr); 318 bytes_written = 0; 319 cvmx_spinlock_lock(lock); 320 while (bytes_to_write > 0) 321 { 322 bytes_available = octeon_pci_console_buffer_free_bytes(cons_ptr->buf_size, cons_ptr->output_write_index, cons_ptr->output_read_index); 323// printf("Console %d has %d bytes available for writes\n", console_num, bytes_available); 324 if (bytes_available > 0) 325 { 326 int write_size = MIN(bytes_available, bytes_to_write); 327 /* Limit ourselves to what we can output in a contiguous block */ 328 if (cons_ptr->output_write_index + write_size >= cons_ptr->buf_size) 329 write_size = cons_ptr->buf_size - cons_ptr->output_write_index; 330 331 memcpy(buf_ptr + cons_ptr->output_write_index, buffer + bytes_written, write_size); 332 CVMX_SYNCW; /* Make sure data is visible before changing write index */ 333 cons_ptr->output_write_index = (cons_ptr->output_write_index + write_size)%cons_ptr->buf_size; 334 bytes_to_write -= write_size; 335 bytes_written += write_size; 336 } 337 else if (bytes_available == 0) 338 { 339 /* Check to see if we should wait for room, or return after a partial write */ 340 if (flags & OCT_PCI_CON_FLAG_NONBLOCK) 341 goto done; 342 343 cvmx_wait(1000000); /* Delay if we are spinning */ 344 } 345 else 346 { 347 bytes_written = -1; 348 goto done; 349 } 350 } 351 352done: 353 cvmx_spinlock_unlock(lock); 354 return(bytes_written); 355} 356 357int octeon_pci_console_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buffer_size, uint32_t flags) 358{ 359 int bytes_available; 360 char *buf_ptr; 361 cvmx_spinlock_t *lock; 362 int bytes_read; 363 int read_size; 364 octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num); 365 if (!cons_ptr) 366 return -1; 367 368 buf_ptr = (char*)cvmx_phys_to_ptr(cons_ptr->input_base_addr); 369 370 bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index); 371 if (bytes_available < 0) 372 return bytes_available; 373 374 lock = (cvmx_spinlock_t *)&cons_ptr->lock; 375 cvmx_spinlock_lock(lock); 376 377 if (!(flags & OCT_PCI_CON_FLAG_NONBLOCK)) 378 { 379 /* Wait for some data to be available */ 380 while (0 == (bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index))) 381 cvmx_wait(1000000); 382 } 383 384 bytes_read = 0; 385// printf("Console %d has %d bytes available for writes\n", console_num, bytes_available); 386 387 /* Don't overflow the buffer passed to us */ 388 read_size = MIN(bytes_available, buffer_size); 389 390 /* Limit ourselves to what we can input in a contiguous block */ 391 if (cons_ptr->input_read_index + read_size >= cons_ptr->buf_size) 392 read_size = cons_ptr->buf_size - cons_ptr->input_read_index; 393 394 memcpy(buffer, buf_ptr + cons_ptr->input_read_index, read_size); 395 cons_ptr->input_read_index = (cons_ptr->input_read_index + read_size)%cons_ptr->buf_size; 396 bytes_read += read_size; 397 398 cvmx_spinlock_unlock(lock); 399 return(bytes_read); 400} 401 402 403int octeon_pci_console_write_avail(uint64_t console_desc_addr, unsigned int console_num) 404{ 405 int bytes_available; 406 octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num); 407 if (!cons_ptr) 408 return -1; 409 410 bytes_available = octeon_pci_console_buffer_free_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index); 411 if (bytes_available >= 0) 412 return(bytes_available); 413 else 414 return 0; 415} 416 417 418int octeon_pci_console_read_avail(uint64_t console_desc_addr, unsigned int console_num) 419{ 420 int bytes_available; 421 octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num); 422 if (!cons_ptr) 423 return -1; 424 425 bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index); 426 if (bytes_available >= 0) 427 return(bytes_available); 428 else 429 return 0; 430} 431 432#endif 433 434 435/* This code can only be used in the bootloader */ 436#if defined(CONFIG_OCTEON_U_BOOT) && defined(CFG_PCI_CONSOLE) 437#define DDR0_TOP 0x10000000 438#define DDR2_BASE 0x20000000 439uint64_t octeon_pci_console_init(int num_consoles, int buffer_size) 440{ 441 octeon_pci_console_desc_t *cons_desc_ptr; 442 octeon_pci_console_t *cons_ptr; 443 444 /* Compute size required for pci console structure */ 445 int alloc_size = num_consoles * (buffer_size * 2 + sizeof(octeon_pci_console_t) + sizeof(uint64_t)) + sizeof(octeon_pci_console_desc_t); 446 447 /* Allocate memory for the consoles. This must be in the range addresssible by the bootloader. 448 ** Try to do so in a manner which minimizes fragmentation. We try to put it at the top of DDR0 or bottom of 449 ** DDR2 first, and only do generic allocation if those fail */ 450 int64_t console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, DDR0_TOP - alloc_size - 128, DDR0_TOP, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC); 451 if (console_block_addr < 0) 452 console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, DDR2_BASE + 1, DDR2_BASE + alloc_size + 128, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC); 453 if (console_block_addr < 0) 454 console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, 0, 0x7fffffff, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC); 455 if (console_block_addr < 0) 456 return 0; 457 458 cons_desc_ptr = (void *)(uint32_t)console_block_addr; 459 460 memset(cons_desc_ptr, 0, alloc_size); /* Clear entire alloc'ed memory */ 461 462 cons_desc_ptr->lock = 1; /* initialize as locked until we are done */ 463 CVMX_SYNCW; 464 cons_desc_ptr->num_consoles = num_consoles; 465 cons_desc_ptr->flags = 0; 466 cons_desc_ptr->major_version = OCTEON_PCI_CONSOLE_MAJOR_VERSION; 467 cons_desc_ptr->minor_version = OCTEON_PCI_CONSOLE_MINOR_VERSION; 468 469 int i; 470 uint64_t avail_addr = console_block_addr + sizeof(octeon_pci_console_desc_t) + num_consoles * sizeof(uint64_t); 471 for (i = 0; i < num_consoles;i++) 472 { 473 cons_desc_ptr->console_addr_array[i] = avail_addr; 474 cons_ptr = (void *)(uint32_t)cons_desc_ptr->console_addr_array[i]; 475 avail_addr += sizeof(octeon_pci_console_t); 476 cons_ptr->input_base_addr = avail_addr; 477 avail_addr += buffer_size; 478 cons_ptr->output_base_addr = avail_addr; 479 avail_addr += buffer_size; 480 cons_ptr->buf_size = buffer_size; 481 } 482 CVMX_SYNCW; 483 cons_desc_ptr->lock = 0; 484 485 return console_block_addr; 486 487 488} 489#endif 490