cvmx-zip-defs.h revision 215976
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-zip-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon zip. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_ZIP_TYPEDEFS_H__ 53#define __CVMX_ZIP_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_ZIP_CMD_BIST_RESULT CVMX_ZIP_CMD_BIST_RESULT_FUNC() 57static inline uint64_t CVMX_ZIP_CMD_BIST_RESULT_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 60 cvmx_warn("CVMX_ZIP_CMD_BIST_RESULT not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x0001180038000080ull); 62} 63#else 64#define CVMX_ZIP_CMD_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180038000080ull)) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67#define CVMX_ZIP_CMD_BUF CVMX_ZIP_CMD_BUF_FUNC() 68static inline uint64_t CVMX_ZIP_CMD_BUF_FUNC(void) 69{ 70 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 71 cvmx_warn("CVMX_ZIP_CMD_BUF not supported on this chip\n"); 72 return CVMX_ADD_IO_SEG(0x0001180038000008ull); 73} 74#else 75#define CVMX_ZIP_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180038000008ull)) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78#define CVMX_ZIP_CMD_CTL CVMX_ZIP_CMD_CTL_FUNC() 79static inline uint64_t CVMX_ZIP_CMD_CTL_FUNC(void) 80{ 81 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 82 cvmx_warn("CVMX_ZIP_CMD_CTL not supported on this chip\n"); 83 return CVMX_ADD_IO_SEG(0x0001180038000000ull); 84} 85#else 86#define CVMX_ZIP_CMD_CTL (CVMX_ADD_IO_SEG(0x0001180038000000ull)) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89#define CVMX_ZIP_CONSTANTS CVMX_ZIP_CONSTANTS_FUNC() 90static inline uint64_t CVMX_ZIP_CONSTANTS_FUNC(void) 91{ 92 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 93 cvmx_warn("CVMX_ZIP_CONSTANTS not supported on this chip\n"); 94 return CVMX_ADD_IO_SEG(0x00011800380000A0ull); 95} 96#else 97#define CVMX_ZIP_CONSTANTS (CVMX_ADD_IO_SEG(0x00011800380000A0ull)) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100#define CVMX_ZIP_DEBUG0 CVMX_ZIP_DEBUG0_FUNC() 101static inline uint64_t CVMX_ZIP_DEBUG0_FUNC(void) 102{ 103 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 104 cvmx_warn("CVMX_ZIP_DEBUG0 not supported on this chip\n"); 105 return CVMX_ADD_IO_SEG(0x0001180038000098ull); 106} 107#else 108#define CVMX_ZIP_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180038000098ull)) 109#endif 110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111#define CVMX_ZIP_ERROR CVMX_ZIP_ERROR_FUNC() 112static inline uint64_t CVMX_ZIP_ERROR_FUNC(void) 113{ 114 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 115 cvmx_warn("CVMX_ZIP_ERROR not supported on this chip\n"); 116 return CVMX_ADD_IO_SEG(0x0001180038000088ull); 117} 118#else 119#define CVMX_ZIP_ERROR (CVMX_ADD_IO_SEG(0x0001180038000088ull)) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122#define CVMX_ZIP_INT_MASK CVMX_ZIP_INT_MASK_FUNC() 123static inline uint64_t CVMX_ZIP_INT_MASK_FUNC(void) 124{ 125 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 126 cvmx_warn("CVMX_ZIP_INT_MASK not supported on this chip\n"); 127 return CVMX_ADD_IO_SEG(0x0001180038000090ull); 128} 129#else 130#define CVMX_ZIP_INT_MASK (CVMX_ADD_IO_SEG(0x0001180038000090ull)) 131#endif 132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133#define CVMX_ZIP_THROTTLE CVMX_ZIP_THROTTLE_FUNC() 134static inline uint64_t CVMX_ZIP_THROTTLE_FUNC(void) 135{ 136 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 137 cvmx_warn("CVMX_ZIP_THROTTLE not supported on this chip\n"); 138 return CVMX_ADD_IO_SEG(0x0001180038000010ull); 139} 140#else 141#define CVMX_ZIP_THROTTLE (CVMX_ADD_IO_SEG(0x0001180038000010ull)) 142#endif 143 144/** 145 * cvmx_zip_cmd_bist_result 146 * 147 * Notes: 148 * Access to the internal BiST results 149 * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail). 150 */ 151union cvmx_zip_cmd_bist_result 152{ 153 uint64_t u64; 154 struct cvmx_zip_cmd_bist_result_s 155 { 156#if __BYTE_ORDER == __BIG_ENDIAN 157 uint64_t reserved_43_63 : 21; 158 uint64_t zip_core : 39; /**< BiST result of the ZIP_CORE memories */ 159 uint64_t zip_ctl : 4; /**< BiST result of the ZIP_CTL memories */ 160#else 161 uint64_t zip_ctl : 4; 162 uint64_t zip_core : 39; 163 uint64_t reserved_43_63 : 21; 164#endif 165 } s; 166 struct cvmx_zip_cmd_bist_result_cn31xx 167 { 168#if __BYTE_ORDER == __BIG_ENDIAN 169 uint64_t reserved_31_63 : 33; 170 uint64_t zip_core : 27; /**< BiST result of the ZIP_CORE memories */ 171 uint64_t zip_ctl : 4; /**< BiST result of the ZIP_CTL memories */ 172#else 173 uint64_t zip_ctl : 4; 174 uint64_t zip_core : 27; 175 uint64_t reserved_31_63 : 33; 176#endif 177 } cn31xx; 178 struct cvmx_zip_cmd_bist_result_cn31xx cn38xx; 179 struct cvmx_zip_cmd_bist_result_cn31xx cn38xxp2; 180 struct cvmx_zip_cmd_bist_result_cn31xx cn56xx; 181 struct cvmx_zip_cmd_bist_result_cn31xx cn56xxp1; 182 struct cvmx_zip_cmd_bist_result_cn31xx cn58xx; 183 struct cvmx_zip_cmd_bist_result_cn31xx cn58xxp1; 184 struct cvmx_zip_cmd_bist_result_s cn63xx; 185 struct cvmx_zip_cmd_bist_result_s cn63xxp1; 186}; 187typedef union cvmx_zip_cmd_bist_result cvmx_zip_cmd_bist_result_t; 188 189/** 190 * cvmx_zip_cmd_buf 191 * 192 * Notes: 193 * Sets the command buffer parameters 194 * The size of the command buffer segments is measured in uint64s. The pool specifies (1 of 8 free 195 * lists to be used when freeing command buffer segments. The PTR field is overwritten with the next 196 * pointer each time that the command buffer segment is exhausted. 197 * When quiescent (i.e. outstanding doorbell count is 0), it is safe to rewrite 198 * this register to effectively reset the command buffer state machine. New commands will then be 199 * read from the newly specified command buffer pointer. 200 */ 201union cvmx_zip_cmd_buf 202{ 203 uint64_t u64; 204 struct cvmx_zip_cmd_buf_s 205 { 206#if __BYTE_ORDER == __BIG_ENDIAN 207 uint64_t reserved_58_63 : 6; 208 uint64_t dwb : 9; /**< Number of DontWriteBacks */ 209 uint64_t pool : 3; /**< Free list used to free command buffer segments */ 210 uint64_t size : 13; /**< Number of uint64s per command buffer segment */ 211 uint64_t ptr : 33; /**< Initial command buffer pointer[39:7] (128B-aligned) */ 212#else 213 uint64_t ptr : 33; 214 uint64_t size : 13; 215 uint64_t pool : 3; 216 uint64_t dwb : 9; 217 uint64_t reserved_58_63 : 6; 218#endif 219 } s; 220 struct cvmx_zip_cmd_buf_s cn31xx; 221 struct cvmx_zip_cmd_buf_s cn38xx; 222 struct cvmx_zip_cmd_buf_s cn38xxp2; 223 struct cvmx_zip_cmd_buf_s cn56xx; 224 struct cvmx_zip_cmd_buf_s cn56xxp1; 225 struct cvmx_zip_cmd_buf_s cn58xx; 226 struct cvmx_zip_cmd_buf_s cn58xxp1; 227 struct cvmx_zip_cmd_buf_s cn63xx; 228 struct cvmx_zip_cmd_buf_s cn63xxp1; 229}; 230typedef union cvmx_zip_cmd_buf cvmx_zip_cmd_buf_t; 231 232/** 233 * cvmx_zip_cmd_ctl 234 */ 235union cvmx_zip_cmd_ctl 236{ 237 uint64_t u64; 238 struct cvmx_zip_cmd_ctl_s 239 { 240#if __BYTE_ORDER == __BIG_ENDIAN 241 uint64_t reserved_2_63 : 62; 242 uint64_t forceclk : 1; /**< Force zip_ctl__clock_on_b == 1 when set */ 243 uint64_t reset : 1; /**< Reset oneshot pulse for zip core */ 244#else 245 uint64_t reset : 1; 246 uint64_t forceclk : 1; 247 uint64_t reserved_2_63 : 62; 248#endif 249 } s; 250 struct cvmx_zip_cmd_ctl_s cn31xx; 251 struct cvmx_zip_cmd_ctl_s cn38xx; 252 struct cvmx_zip_cmd_ctl_s cn38xxp2; 253 struct cvmx_zip_cmd_ctl_s cn56xx; 254 struct cvmx_zip_cmd_ctl_s cn56xxp1; 255 struct cvmx_zip_cmd_ctl_s cn58xx; 256 struct cvmx_zip_cmd_ctl_s cn58xxp1; 257 struct cvmx_zip_cmd_ctl_s cn63xx; 258 struct cvmx_zip_cmd_ctl_s cn63xxp1; 259}; 260typedef union cvmx_zip_cmd_ctl cvmx_zip_cmd_ctl_t; 261 262/** 263 * cvmx_zip_constants 264 * 265 * Notes: 266 * Note that this CSR is present only in chip revisions beginning with pass2. 267 * 268 */ 269union cvmx_zip_constants 270{ 271 uint64_t u64; 272 struct cvmx_zip_constants_s 273 { 274#if __BYTE_ORDER == __BIG_ENDIAN 275 uint64_t reserved_48_63 : 16; 276 uint64_t depth : 16; /**< Maximum search depth for compression */ 277 uint64_t onfsize : 12; /**< Output near full threshhold in bytes */ 278 uint64_t ctxsize : 12; /**< Context size in bytes */ 279 uint64_t reserved_1_7 : 7; 280 uint64_t disabled : 1; /**< 1=zip unit isdisabled, 0=zip unit not disabled */ 281#else 282 uint64_t disabled : 1; 283 uint64_t reserved_1_7 : 7; 284 uint64_t ctxsize : 12; 285 uint64_t onfsize : 12; 286 uint64_t depth : 16; 287 uint64_t reserved_48_63 : 16; 288#endif 289 } s; 290 struct cvmx_zip_constants_s cn31xx; 291 struct cvmx_zip_constants_s cn38xx; 292 struct cvmx_zip_constants_s cn38xxp2; 293 struct cvmx_zip_constants_s cn56xx; 294 struct cvmx_zip_constants_s cn56xxp1; 295 struct cvmx_zip_constants_s cn58xx; 296 struct cvmx_zip_constants_s cn58xxp1; 297 struct cvmx_zip_constants_s cn63xx; 298 struct cvmx_zip_constants_s cn63xxp1; 299}; 300typedef union cvmx_zip_constants cvmx_zip_constants_t; 301 302/** 303 * cvmx_zip_debug0 304 * 305 * Notes: 306 * Note that this CSR is present only in chip revisions beginning with pass2. 307 * 308 */ 309union cvmx_zip_debug0 310{ 311 uint64_t u64; 312 struct cvmx_zip_debug0_s 313 { 314#if __BYTE_ORDER == __BIG_ENDIAN 315 uint64_t reserved_17_63 : 47; 316 uint64_t asserts : 17; /**< FIFO assertion checks */ 317#else 318 uint64_t asserts : 17; 319 uint64_t reserved_17_63 : 47; 320#endif 321 } s; 322 struct cvmx_zip_debug0_cn31xx 323 { 324#if __BYTE_ORDER == __BIG_ENDIAN 325 uint64_t reserved_14_63 : 50; 326 uint64_t asserts : 14; /**< FIFO assertion checks */ 327#else 328 uint64_t asserts : 14; 329 uint64_t reserved_14_63 : 50; 330#endif 331 } cn31xx; 332 struct cvmx_zip_debug0_cn31xx cn38xx; 333 struct cvmx_zip_debug0_cn31xx cn38xxp2; 334 struct cvmx_zip_debug0_cn31xx cn56xx; 335 struct cvmx_zip_debug0_cn31xx cn56xxp1; 336 struct cvmx_zip_debug0_cn31xx cn58xx; 337 struct cvmx_zip_debug0_cn31xx cn58xxp1; 338 struct cvmx_zip_debug0_s cn63xx; 339 struct cvmx_zip_debug0_s cn63xxp1; 340}; 341typedef union cvmx_zip_debug0 cvmx_zip_debug0_t; 342 343/** 344 * cvmx_zip_error 345 * 346 * Notes: 347 * Note that this CSR is present only in chip revisions beginning with pass2. 348 * 349 */ 350union cvmx_zip_error 351{ 352 uint64_t u64; 353 struct cvmx_zip_error_s 354 { 355#if __BYTE_ORDER == __BIG_ENDIAN 356 uint64_t reserved_1_63 : 63; 357 uint64_t doorbell : 1; /**< A doorbell count has overflowed */ 358#else 359 uint64_t doorbell : 1; 360 uint64_t reserved_1_63 : 63; 361#endif 362 } s; 363 struct cvmx_zip_error_s cn31xx; 364 struct cvmx_zip_error_s cn38xx; 365 struct cvmx_zip_error_s cn38xxp2; 366 struct cvmx_zip_error_s cn56xx; 367 struct cvmx_zip_error_s cn56xxp1; 368 struct cvmx_zip_error_s cn58xx; 369 struct cvmx_zip_error_s cn58xxp1; 370 struct cvmx_zip_error_s cn63xx; 371 struct cvmx_zip_error_s cn63xxp1; 372}; 373typedef union cvmx_zip_error cvmx_zip_error_t; 374 375/** 376 * cvmx_zip_int_mask 377 * 378 * Notes: 379 * Note that this CSR is present only in chip revisions beginning with pass2. 380 * When a mask bit is set, the corresponding interrupt is enabled. 381 */ 382union cvmx_zip_int_mask 383{ 384 uint64_t u64; 385 struct cvmx_zip_int_mask_s 386 { 387#if __BYTE_ORDER == __BIG_ENDIAN 388 uint64_t reserved_1_63 : 63; 389 uint64_t doorbell : 1; /**< Bit mask corresponding to ZIP_ERROR[0] above */ 390#else 391 uint64_t doorbell : 1; 392 uint64_t reserved_1_63 : 63; 393#endif 394 } s; 395 struct cvmx_zip_int_mask_s cn31xx; 396 struct cvmx_zip_int_mask_s cn38xx; 397 struct cvmx_zip_int_mask_s cn38xxp2; 398 struct cvmx_zip_int_mask_s cn56xx; 399 struct cvmx_zip_int_mask_s cn56xxp1; 400 struct cvmx_zip_int_mask_s cn58xx; 401 struct cvmx_zip_int_mask_s cn58xxp1; 402 struct cvmx_zip_int_mask_s cn63xx; 403 struct cvmx_zip_int_mask_s cn63xxp1; 404}; 405typedef union cvmx_zip_int_mask cvmx_zip_int_mask_t; 406 407/** 408 * cvmx_zip_throttle 409 * 410 * Notes: 411 * The maximum number of inflight data fetch transactions. Values > 8 are illegal. 412 * Writing 0 to this register causes the ZIP module to temporarily suspend NCB 413 * accesses; it is not recommended for normal operation, but may be useful for 414 * diagnostics. 415 */ 416union cvmx_zip_throttle 417{ 418 uint64_t u64; 419 struct cvmx_zip_throttle_s 420 { 421#if __BYTE_ORDER == __BIG_ENDIAN 422 uint64_t reserved_4_63 : 60; 423 uint64_t max_infl : 4; /**< Maximum number of inflight data fetch transactions on NCB */ 424#else 425 uint64_t max_infl : 4; 426 uint64_t reserved_4_63 : 60; 427#endif 428 } s; 429 struct cvmx_zip_throttle_s cn63xx; 430 struct cvmx_zip_throttle_s cn63xxp1; 431}; 432typedef union cvmx_zip_throttle cvmx_zip_throttle_t; 433 434#endif 435