cvmx-uahcx-defs.h revision 215990
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-uahcx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon uahcx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_UAHCX_TYPEDEFS_H__ 53#define __CVMX_UAHCX_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_UAHCX_EHCI_ASYNCLISTADDR(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 60 cvmx_warn("CVMX_UAHCX_EHCI_ASYNCLISTADDR(%lu) is invalid on this chip\n", block_id); 61 return CVMX_ADD_IO_SEG(0x00016F0000000028ull); 62} 63#else 64#define CVMX_UAHCX_EHCI_ASYNCLISTADDR(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000028ull)) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67static inline uint64_t CVMX_UAHCX_EHCI_CONFIGFLAG(unsigned long block_id) 68{ 69 if (!( 70 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 71 cvmx_warn("CVMX_UAHCX_EHCI_CONFIGFLAG(%lu) is invalid on this chip\n", block_id); 72 return CVMX_ADD_IO_SEG(0x00016F0000000050ull); 73} 74#else 75#define CVMX_UAHCX_EHCI_CONFIGFLAG(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000050ull)) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78static inline uint64_t CVMX_UAHCX_EHCI_CTRLDSSEGMENT(unsigned long block_id) 79{ 80 if (!( 81 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 82 cvmx_warn("CVMX_UAHCX_EHCI_CTRLDSSEGMENT(%lu) is invalid on this chip\n", block_id); 83 return CVMX_ADD_IO_SEG(0x00016F0000000020ull); 84} 85#else 86#define CVMX_UAHCX_EHCI_CTRLDSSEGMENT(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000020ull)) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89static inline uint64_t CVMX_UAHCX_EHCI_FRINDEX(unsigned long block_id) 90{ 91 if (!( 92 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 93 cvmx_warn("CVMX_UAHCX_EHCI_FRINDEX(%lu) is invalid on this chip\n", block_id); 94 return CVMX_ADD_IO_SEG(0x00016F000000001Cull); 95} 96#else 97#define CVMX_UAHCX_EHCI_FRINDEX(block_id) (CVMX_ADD_IO_SEG(0x00016F000000001Cull)) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100static inline uint64_t CVMX_UAHCX_EHCI_HCCAPBASE(unsigned long block_id) 101{ 102 if (!( 103 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 104 cvmx_warn("CVMX_UAHCX_EHCI_HCCAPBASE(%lu) is invalid on this chip\n", block_id); 105 return CVMX_ADD_IO_SEG(0x00016F0000000000ull); 106} 107#else 108#define CVMX_UAHCX_EHCI_HCCAPBASE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000000ull)) 109#endif 110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111static inline uint64_t CVMX_UAHCX_EHCI_HCCPARAMS(unsigned long block_id) 112{ 113 if (!( 114 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 115 cvmx_warn("CVMX_UAHCX_EHCI_HCCPARAMS(%lu) is invalid on this chip\n", block_id); 116 return CVMX_ADD_IO_SEG(0x00016F0000000008ull); 117} 118#else 119#define CVMX_UAHCX_EHCI_HCCPARAMS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000008ull)) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122static inline uint64_t CVMX_UAHCX_EHCI_HCSPARAMS(unsigned long block_id) 123{ 124 if (!( 125 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 126 cvmx_warn("CVMX_UAHCX_EHCI_HCSPARAMS(%lu) is invalid on this chip\n", block_id); 127 return CVMX_ADD_IO_SEG(0x00016F0000000004ull); 128} 129#else 130#define CVMX_UAHCX_EHCI_HCSPARAMS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000004ull)) 131#endif 132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133static inline uint64_t CVMX_UAHCX_EHCI_INSNREG00(unsigned long block_id) 134{ 135 if (!( 136 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 137 cvmx_warn("CVMX_UAHCX_EHCI_INSNREG00(%lu) is invalid on this chip\n", block_id); 138 return CVMX_ADD_IO_SEG(0x00016F0000000090ull); 139} 140#else 141#define CVMX_UAHCX_EHCI_INSNREG00(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000090ull)) 142#endif 143#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144static inline uint64_t CVMX_UAHCX_EHCI_INSNREG03(unsigned long block_id) 145{ 146 if (!( 147 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 148 cvmx_warn("CVMX_UAHCX_EHCI_INSNREG03(%lu) is invalid on this chip\n", block_id); 149 return CVMX_ADD_IO_SEG(0x00016F000000009Cull); 150} 151#else 152#define CVMX_UAHCX_EHCI_INSNREG03(block_id) (CVMX_ADD_IO_SEG(0x00016F000000009Cull)) 153#endif 154#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155static inline uint64_t CVMX_UAHCX_EHCI_INSNREG04(unsigned long block_id) 156{ 157 if (!( 158 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 159 cvmx_warn("CVMX_UAHCX_EHCI_INSNREG04(%lu) is invalid on this chip\n", block_id); 160 return CVMX_ADD_IO_SEG(0x00016F00000000A0ull); 161} 162#else 163#define CVMX_UAHCX_EHCI_INSNREG04(block_id) (CVMX_ADD_IO_SEG(0x00016F00000000A0ull)) 164#endif 165#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166static inline uint64_t CVMX_UAHCX_EHCI_INSNREG06(unsigned long block_id) 167{ 168 if (!( 169 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 170 cvmx_warn("CVMX_UAHCX_EHCI_INSNREG06(%lu) is invalid on this chip\n", block_id); 171 return CVMX_ADD_IO_SEG(0x00016F00000000E8ull); 172} 173#else 174#define CVMX_UAHCX_EHCI_INSNREG06(block_id) (CVMX_ADD_IO_SEG(0x00016F00000000E8ull)) 175#endif 176#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177static inline uint64_t CVMX_UAHCX_EHCI_INSNREG07(unsigned long block_id) 178{ 179 if (!( 180 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 181 cvmx_warn("CVMX_UAHCX_EHCI_INSNREG07(%lu) is invalid on this chip\n", block_id); 182 return CVMX_ADD_IO_SEG(0x00016F00000000ECull); 183} 184#else 185#define CVMX_UAHCX_EHCI_INSNREG07(block_id) (CVMX_ADD_IO_SEG(0x00016F00000000ECull)) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188static inline uint64_t CVMX_UAHCX_EHCI_PERIODICLISTBASE(unsigned long block_id) 189{ 190 if (!( 191 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 192 cvmx_warn("CVMX_UAHCX_EHCI_PERIODICLISTBASE(%lu) is invalid on this chip\n", block_id); 193 return CVMX_ADD_IO_SEG(0x00016F0000000024ull); 194} 195#else 196#define CVMX_UAHCX_EHCI_PERIODICLISTBASE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000024ull)) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199static inline uint64_t CVMX_UAHCX_EHCI_PORTSCX(unsigned long offset, unsigned long block_id) 200{ 201 if (!( 202 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))))) 203 cvmx_warn("CVMX_UAHCX_EHCI_PORTSCX(%lu,%lu) is invalid on this chip\n", offset, block_id); 204 return CVMX_ADD_IO_SEG(0x00016F0000000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4; 205} 206#else 207#define CVMX_UAHCX_EHCI_PORTSCX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0000000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4) 208#endif 209#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210static inline uint64_t CVMX_UAHCX_EHCI_USBCMD(unsigned long block_id) 211{ 212 if (!( 213 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 214 cvmx_warn("CVMX_UAHCX_EHCI_USBCMD(%lu) is invalid on this chip\n", block_id); 215 return CVMX_ADD_IO_SEG(0x00016F0000000010ull); 216} 217#else 218#define CVMX_UAHCX_EHCI_USBCMD(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000010ull)) 219#endif 220#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221static inline uint64_t CVMX_UAHCX_EHCI_USBINTR(unsigned long block_id) 222{ 223 if (!( 224 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 225 cvmx_warn("CVMX_UAHCX_EHCI_USBINTR(%lu) is invalid on this chip\n", block_id); 226 return CVMX_ADD_IO_SEG(0x00016F0000000018ull); 227} 228#else 229#define CVMX_UAHCX_EHCI_USBINTR(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000018ull)) 230#endif 231#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232static inline uint64_t CVMX_UAHCX_EHCI_USBSTS(unsigned long block_id) 233{ 234 if (!( 235 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 236 cvmx_warn("CVMX_UAHCX_EHCI_USBSTS(%lu) is invalid on this chip\n", block_id); 237 return CVMX_ADD_IO_SEG(0x00016F0000000014ull); 238} 239#else 240#define CVMX_UAHCX_EHCI_USBSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000014ull)) 241#endif 242#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243static inline uint64_t CVMX_UAHCX_OHCI0_HCBULKCURRENTED(unsigned long block_id) 244{ 245 if (!( 246 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 247 cvmx_warn("CVMX_UAHCX_OHCI0_HCBULKCURRENTED(%lu) is invalid on this chip\n", block_id); 248 return CVMX_ADD_IO_SEG(0x00016F000000042Cull); 249} 250#else 251#define CVMX_UAHCX_OHCI0_HCBULKCURRENTED(block_id) (CVMX_ADD_IO_SEG(0x00016F000000042Cull)) 252#endif 253#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254static inline uint64_t CVMX_UAHCX_OHCI0_HCBULKHEADED(unsigned long block_id) 255{ 256 if (!( 257 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 258 cvmx_warn("CVMX_UAHCX_OHCI0_HCBULKHEADED(%lu) is invalid on this chip\n", block_id); 259 return CVMX_ADD_IO_SEG(0x00016F0000000428ull); 260} 261#else 262#define CVMX_UAHCX_OHCI0_HCBULKHEADED(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000428ull)) 263#endif 264#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265static inline uint64_t CVMX_UAHCX_OHCI0_HCCOMMANDSTATUS(unsigned long block_id) 266{ 267 if (!( 268 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 269 cvmx_warn("CVMX_UAHCX_OHCI0_HCCOMMANDSTATUS(%lu) is invalid on this chip\n", block_id); 270 return CVMX_ADD_IO_SEG(0x00016F0000000408ull); 271} 272#else 273#define CVMX_UAHCX_OHCI0_HCCOMMANDSTATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000408ull)) 274#endif 275#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276static inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROL(unsigned long block_id) 277{ 278 if (!( 279 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 280 cvmx_warn("CVMX_UAHCX_OHCI0_HCCONTROL(%lu) is invalid on this chip\n", block_id); 281 return CVMX_ADD_IO_SEG(0x00016F0000000404ull); 282} 283#else 284#define CVMX_UAHCX_OHCI0_HCCONTROL(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000404ull)) 285#endif 286#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287static inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROLCURRENTED(unsigned long block_id) 288{ 289 if (!( 290 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 291 cvmx_warn("CVMX_UAHCX_OHCI0_HCCONTROLCURRENTED(%lu) is invalid on this chip\n", block_id); 292 return CVMX_ADD_IO_SEG(0x00016F0000000424ull); 293} 294#else 295#define CVMX_UAHCX_OHCI0_HCCONTROLCURRENTED(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000424ull)) 296#endif 297#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298static inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROLHEADED(unsigned long block_id) 299{ 300 if (!( 301 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 302 cvmx_warn("CVMX_UAHCX_OHCI0_HCCONTROLHEADED(%lu) is invalid on this chip\n", block_id); 303 return CVMX_ADD_IO_SEG(0x00016F0000000420ull); 304} 305#else 306#define CVMX_UAHCX_OHCI0_HCCONTROLHEADED(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000420ull)) 307#endif 308#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309static inline uint64_t CVMX_UAHCX_OHCI0_HCDONEHEAD(unsigned long block_id) 310{ 311 if (!( 312 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 313 cvmx_warn("CVMX_UAHCX_OHCI0_HCDONEHEAD(%lu) is invalid on this chip\n", block_id); 314 return CVMX_ADD_IO_SEG(0x00016F0000000430ull); 315} 316#else 317#define CVMX_UAHCX_OHCI0_HCDONEHEAD(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000430ull)) 318#endif 319#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 320static inline uint64_t CVMX_UAHCX_OHCI0_HCFMINTERVAL(unsigned long block_id) 321{ 322 if (!( 323 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 324 cvmx_warn("CVMX_UAHCX_OHCI0_HCFMINTERVAL(%lu) is invalid on this chip\n", block_id); 325 return CVMX_ADD_IO_SEG(0x00016F0000000434ull); 326} 327#else 328#define CVMX_UAHCX_OHCI0_HCFMINTERVAL(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000434ull)) 329#endif 330#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 331static inline uint64_t CVMX_UAHCX_OHCI0_HCFMNUMBER(unsigned long block_id) 332{ 333 if (!( 334 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 335 cvmx_warn("CVMX_UAHCX_OHCI0_HCFMNUMBER(%lu) is invalid on this chip\n", block_id); 336 return CVMX_ADD_IO_SEG(0x00016F000000043Cull); 337} 338#else 339#define CVMX_UAHCX_OHCI0_HCFMNUMBER(block_id) (CVMX_ADD_IO_SEG(0x00016F000000043Cull)) 340#endif 341#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342static inline uint64_t CVMX_UAHCX_OHCI0_HCFMREMAINING(unsigned long block_id) 343{ 344 if (!( 345 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 346 cvmx_warn("CVMX_UAHCX_OHCI0_HCFMREMAINING(%lu) is invalid on this chip\n", block_id); 347 return CVMX_ADD_IO_SEG(0x00016F0000000438ull); 348} 349#else 350#define CVMX_UAHCX_OHCI0_HCFMREMAINING(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000438ull)) 351#endif 352#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 353static inline uint64_t CVMX_UAHCX_OHCI0_HCHCCA(unsigned long block_id) 354{ 355 if (!( 356 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 357 cvmx_warn("CVMX_UAHCX_OHCI0_HCHCCA(%lu) is invalid on this chip\n", block_id); 358 return CVMX_ADD_IO_SEG(0x00016F0000000418ull); 359} 360#else 361#define CVMX_UAHCX_OHCI0_HCHCCA(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000418ull)) 362#endif 363#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 364static inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTDISABLE(unsigned long block_id) 365{ 366 if (!( 367 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 368 cvmx_warn("CVMX_UAHCX_OHCI0_HCINTERRUPTDISABLE(%lu) is invalid on this chip\n", block_id); 369 return CVMX_ADD_IO_SEG(0x00016F0000000414ull); 370} 371#else 372#define CVMX_UAHCX_OHCI0_HCINTERRUPTDISABLE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000414ull)) 373#endif 374#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 375static inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTENABLE(unsigned long block_id) 376{ 377 if (!( 378 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 379 cvmx_warn("CVMX_UAHCX_OHCI0_HCINTERRUPTENABLE(%lu) is invalid on this chip\n", block_id); 380 return CVMX_ADD_IO_SEG(0x00016F0000000410ull); 381} 382#else 383#define CVMX_UAHCX_OHCI0_HCINTERRUPTENABLE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000410ull)) 384#endif 385#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386static inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTSTATUS(unsigned long block_id) 387{ 388 if (!( 389 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 390 cvmx_warn("CVMX_UAHCX_OHCI0_HCINTERRUPTSTATUS(%lu) is invalid on this chip\n", block_id); 391 return CVMX_ADD_IO_SEG(0x00016F000000040Cull); 392} 393#else 394#define CVMX_UAHCX_OHCI0_HCINTERRUPTSTATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F000000040Cull)) 395#endif 396#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 397static inline uint64_t CVMX_UAHCX_OHCI0_HCLSTHRESHOLD(unsigned long block_id) 398{ 399 if (!( 400 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 401 cvmx_warn("CVMX_UAHCX_OHCI0_HCLSTHRESHOLD(%lu) is invalid on this chip\n", block_id); 402 return CVMX_ADD_IO_SEG(0x00016F0000000444ull); 403} 404#else 405#define CVMX_UAHCX_OHCI0_HCLSTHRESHOLD(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000444ull)) 406#endif 407#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 408static inline uint64_t CVMX_UAHCX_OHCI0_HCPERIODCURRENTED(unsigned long block_id) 409{ 410 if (!( 411 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 412 cvmx_warn("CVMX_UAHCX_OHCI0_HCPERIODCURRENTED(%lu) is invalid on this chip\n", block_id); 413 return CVMX_ADD_IO_SEG(0x00016F000000041Cull); 414} 415#else 416#define CVMX_UAHCX_OHCI0_HCPERIODCURRENTED(block_id) (CVMX_ADD_IO_SEG(0x00016F000000041Cull)) 417#endif 418#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 419static inline uint64_t CVMX_UAHCX_OHCI0_HCPERIODICSTART(unsigned long block_id) 420{ 421 if (!( 422 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 423 cvmx_warn("CVMX_UAHCX_OHCI0_HCPERIODICSTART(%lu) is invalid on this chip\n", block_id); 424 return CVMX_ADD_IO_SEG(0x00016F0000000440ull); 425} 426#else 427#define CVMX_UAHCX_OHCI0_HCPERIODICSTART(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000440ull)) 428#endif 429#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430static inline uint64_t CVMX_UAHCX_OHCI0_HCREVISION(unsigned long block_id) 431{ 432 if (!( 433 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 434 cvmx_warn("CVMX_UAHCX_OHCI0_HCREVISION(%lu) is invalid on this chip\n", block_id); 435 return CVMX_ADD_IO_SEG(0x00016F0000000400ull); 436} 437#else 438#define CVMX_UAHCX_OHCI0_HCREVISION(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000400ull)) 439#endif 440#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 441static inline uint64_t CVMX_UAHCX_OHCI0_HCRHDESCRIPTORA(unsigned long block_id) 442{ 443 if (!( 444 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 445 cvmx_warn("CVMX_UAHCX_OHCI0_HCRHDESCRIPTORA(%lu) is invalid on this chip\n", block_id); 446 return CVMX_ADD_IO_SEG(0x00016F0000000448ull); 447} 448#else 449#define CVMX_UAHCX_OHCI0_HCRHDESCRIPTORA(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000448ull)) 450#endif 451#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452static inline uint64_t CVMX_UAHCX_OHCI0_HCRHDESCRIPTORB(unsigned long block_id) 453{ 454 if (!( 455 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 456 cvmx_warn("CVMX_UAHCX_OHCI0_HCRHDESCRIPTORB(%lu) is invalid on this chip\n", block_id); 457 return CVMX_ADD_IO_SEG(0x00016F000000044Cull); 458} 459#else 460#define CVMX_UAHCX_OHCI0_HCRHDESCRIPTORB(block_id) (CVMX_ADD_IO_SEG(0x00016F000000044Cull)) 461#endif 462#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 463static inline uint64_t CVMX_UAHCX_OHCI0_HCRHPORTSTATUSX(unsigned long offset, unsigned long block_id) 464{ 465 if (!( 466 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))))) 467 cvmx_warn("CVMX_UAHCX_OHCI0_HCRHPORTSTATUSX(%lu,%lu) is invalid on this chip\n", offset, block_id); 468 return CVMX_ADD_IO_SEG(0x00016F0000000450ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4; 469} 470#else 471#define CVMX_UAHCX_OHCI0_HCRHPORTSTATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0000000450ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4) 472#endif 473#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 474static inline uint64_t CVMX_UAHCX_OHCI0_HCRHSTATUS(unsigned long block_id) 475{ 476 if (!( 477 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 478 cvmx_warn("CVMX_UAHCX_OHCI0_HCRHSTATUS(%lu) is invalid on this chip\n", block_id); 479 return CVMX_ADD_IO_SEG(0x00016F0000000450ull); 480} 481#else 482#define CVMX_UAHCX_OHCI0_HCRHSTATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000450ull)) 483#endif 484#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485static inline uint64_t CVMX_UAHCX_OHCI0_INSNREG06(unsigned long block_id) 486{ 487 if (!( 488 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 489 cvmx_warn("CVMX_UAHCX_OHCI0_INSNREG06(%lu) is invalid on this chip\n", block_id); 490 return CVMX_ADD_IO_SEG(0x00016F0000000498ull); 491} 492#else 493#define CVMX_UAHCX_OHCI0_INSNREG06(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000498ull)) 494#endif 495#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 496static inline uint64_t CVMX_UAHCX_OHCI0_INSNREG07(unsigned long block_id) 497{ 498 if (!( 499 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 500 cvmx_warn("CVMX_UAHCX_OHCI0_INSNREG07(%lu) is invalid on this chip\n", block_id); 501 return CVMX_ADD_IO_SEG(0x00016F000000049Cull); 502} 503#else 504#define CVMX_UAHCX_OHCI0_INSNREG07(block_id) (CVMX_ADD_IO_SEG(0x00016F000000049Cull)) 505#endif 506 507/** 508 * cvmx_uahc#_ehci_asynclistaddr 509 * 510 * ASYNCLISTADDR = Current Asynchronous List Address Register 511 * 512 * This 32-bit register contains the address of the next asynchronous queue head to be executed. If the host 513 * controller is in 64-bit mode (as indicated by a one in 64-bit Addressing Capability field in the 514 * HCCPARAMS register), then the most significant 32 bits of every control data structure address comes from 515 * the CTRLDSSEGMENT register (See Section 2.3.5). Bits [4:0] of this register cannot be modified by system 516 * software and will always return a zero when read. The memory structure referenced by this physical memory 517 * pointer is assumed to be 32-byte (cache line) aligned. 518 */ 519union cvmx_uahcx_ehci_asynclistaddr 520{ 521 uint32_t u32; 522 struct cvmx_uahcx_ehci_asynclistaddr_s 523 { 524#if __BYTE_ORDER == __BIG_ENDIAN 525 uint32_t lpl : 27; /**< Link Pointer Low (LPL). These bits correspond to memory address signals [31:5], 526 respectively. This field may only reference a Queue Head (QH). */ 527 uint32_t reserved_0_4 : 5; 528#else 529 uint32_t reserved_0_4 : 5; 530 uint32_t lpl : 27; 531#endif 532 } s; 533 struct cvmx_uahcx_ehci_asynclistaddr_s cn63xx; 534 struct cvmx_uahcx_ehci_asynclistaddr_s cn63xxp1; 535}; 536typedef union cvmx_uahcx_ehci_asynclistaddr cvmx_uahcx_ehci_asynclistaddr_t; 537 538/** 539 * cvmx_uahc#_ehci_configflag 540 * 541 * CONFIGFLAG = Configure Flag Register 542 * This register is in the auxiliary power well. It is only reset by hardware when the auxiliary power is initially 543 * applied or in response to a host controller reset. 544 */ 545union cvmx_uahcx_ehci_configflag 546{ 547 uint32_t u32; 548 struct cvmx_uahcx_ehci_configflag_s 549 { 550#if __BYTE_ORDER == __BIG_ENDIAN 551 uint32_t reserved_1_31 : 31; 552 uint32_t cf : 1; /**< Configure Flag (CF) .Host software sets this bit as the last action in 553 its process of configuring the Host Controller (see Section 4.1). This bit controls the 554 default port-routing control logic. Bit values and side-effects are listed below. 555 0b: Port routing control logic default-routes each port to an implementation 556 dependent classic host controller. 557 1b: Port routing control logic default-routes all ports to this host controller. */ 558#else 559 uint32_t cf : 1; 560 uint32_t reserved_1_31 : 31; 561#endif 562 } s; 563 struct cvmx_uahcx_ehci_configflag_s cn63xx; 564 struct cvmx_uahcx_ehci_configflag_s cn63xxp1; 565}; 566typedef union cvmx_uahcx_ehci_configflag cvmx_uahcx_ehci_configflag_t; 567 568/** 569 * cvmx_uahc#_ehci_ctrldssegment 570 * 571 * CTRLDSSEGMENT = Control Data Structure Segment Register 572 * 573 * This 32-bit register corresponds to the most significant address bits [63:32] for all EHCI data structures. If 574 * the 64-bit Addressing Capability field in HCCPARAMS is a zero, then this register is not used. Software 575 * cannot write to it and a read from this register will return zeros. 576 * 577 * If the 64-bit Addressing Capability field in HCCPARAMS is a one, then this register is used with the link 578 * pointers to construct 64-bit addresses to EHCI control data structures. This register is concatenated with the 579 * link pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data structure link 580 * field to construct a 64-bit address. 581 * 582 * This register allows the host software to locate all control data structures within the same 4 Gigabyte 583 * memory segment. 584 */ 585union cvmx_uahcx_ehci_ctrldssegment 586{ 587 uint32_t u32; 588 struct cvmx_uahcx_ehci_ctrldssegment_s 589 { 590#if __BYTE_ORDER == __BIG_ENDIAN 591 uint32_t ctrldsseg : 32; /**< Control Data Strucute Semgent Address Bit [63:32] */ 592#else 593 uint32_t ctrldsseg : 32; 594#endif 595 } s; 596 struct cvmx_uahcx_ehci_ctrldssegment_s cn63xx; 597 struct cvmx_uahcx_ehci_ctrldssegment_s cn63xxp1; 598}; 599typedef union cvmx_uahcx_ehci_ctrldssegment cvmx_uahcx_ehci_ctrldssegment_t; 600 601/** 602 * cvmx_uahc#_ehci_frindex 603 * 604 * FRINDEX = Frame Index Register 605 * This register is used by the host controller to index into the periodic frame list. The register updates every 606 * 125 microseconds (once each micro-frame). Bits [N:3] are used to select a particular entry in the Periodic 607 * Frame List during periodic schedule execution. The number of bits used for the index depends on the size of 608 * the frame list as set by system software in the Frame List Size field in the USBCMD register. 609 * This register cannot be written unless the Host Controller is in the Halted state as indicated by the 610 * HCHalted bit. A write to this register while the Run/Stop bit is set to a one (USBCMD register) produces 611 * undefined results. Writes to this register also affect the SOF value. 612 */ 613union cvmx_uahcx_ehci_frindex 614{ 615 uint32_t u32; 616 struct cvmx_uahcx_ehci_frindex_s 617 { 618#if __BYTE_ORDER == __BIG_ENDIAN 619 uint32_t reserved_14_31 : 18; 620 uint32_t fi : 14; /**< Frame Index. The value in this register increments at the end of each time frame (e.g. 621 micro-frame). Bits [N:3] are used for the Frame List current index. This means that each 622 location of the frame list is accessed 8 times (frames or micro-frames) before moving to 623 the next index. The following illustrates values of N based on the value of the Frame List 624 Size field in the USBCMD register. 625 USBCMD[Frame List Size] Number Elements N 626 00b (1024) 12 627 01b (512) 11 628 10b (256) 10 629 11b Reserved */ 630#else 631 uint32_t fi : 14; 632 uint32_t reserved_14_31 : 18; 633#endif 634 } s; 635 struct cvmx_uahcx_ehci_frindex_s cn63xx; 636 struct cvmx_uahcx_ehci_frindex_s cn63xxp1; 637}; 638typedef union cvmx_uahcx_ehci_frindex cvmx_uahcx_ehci_frindex_t; 639 640/** 641 * cvmx_uahc#_ehci_hccapbase 642 * 643 * HCCAPBASE = Host Controller BASE Capability Register 644 * 645 */ 646union cvmx_uahcx_ehci_hccapbase 647{ 648 uint32_t u32; 649 struct cvmx_uahcx_ehci_hccapbase_s 650 { 651#if __BYTE_ORDER == __BIG_ENDIAN 652 uint32_t hciversion : 16; /**< Host Controller Interface Version Number */ 653 uint32_t reserved_8_15 : 8; 654 uint32_t caplength : 8; /**< Capabitlity Registers Length */ 655#else 656 uint32_t caplength : 8; 657 uint32_t reserved_8_15 : 8; 658 uint32_t hciversion : 16; 659#endif 660 } s; 661 struct cvmx_uahcx_ehci_hccapbase_s cn63xx; 662 struct cvmx_uahcx_ehci_hccapbase_s cn63xxp1; 663}; 664typedef union cvmx_uahcx_ehci_hccapbase cvmx_uahcx_ehci_hccapbase_t; 665 666/** 667 * cvmx_uahc#_ehci_hccparams 668 * 669 * HCCPARAMS = Host Controller Capability Parameters 670 * Multiple Mode control (time-base bit functionality), addressing capability 671 */ 672union cvmx_uahcx_ehci_hccparams 673{ 674 uint32_t u32; 675 struct cvmx_uahcx_ehci_hccparams_s 676 { 677#if __BYTE_ORDER == __BIG_ENDIAN 678 uint32_t reserved_16_31 : 16; 679 uint32_t eecp : 8; /**< EHCI Extended Capabilities Pointer. Default = Implementation Dependent. 680 This optional field indicates the existence of a capabilities list. A value of 00h indicates 681 no extended capabilities are implemented. A non-zero value in this register indicates the 682 offset in PCI configuration space of the first EHCI extended capability. The pointer value 683 must be 40h or greater if implemented to maintain the consistency of the PCI header 684 defined for this class of device. */ 685 uint32_t ist : 4; /**< Isochronous Scheduling Threshold. Default = implementation dependent. This field 686 indicates, relative to the current position of the executing host controller, where software 687 can reliably update the isochronous schedule. When bit [7] is zero, the value of the least 688 significant 3 bits indicates the number of micro-frames a host controller can hold a set of 689 isochronous data structures (one or more) before flushing the state. When bit [7] is a 690 one, then host software assumes the host controller may cache an isochronous data 691 structure for an entire frame. Refer to Section 4.7.2.1 for details on how software uses 692 this information for scheduling isochronous transfers. */ 693 uint32_t reserved_3_3 : 1; 694 uint32_t aspc : 1; /**< Asynchronous Schedule Park Capability. Default = Implementation dependent. If this 695 bit is set to a one, then the host controller supports the park feature for high-speed 696 queue heads in the Asynchronous Schedule. The feature can be disabled or enabled 697 and set to a specific level by using the Asynchronous Schedule Park Mode Enable and 698 Asynchronous Schedule Park Mode Count fields in the USBCMD register. */ 699 uint32_t pflf : 1; /**< Programmable Frame List Flag. Default = Implementation dependent. If this bit is set 700 to a zero, then system software must use a frame list length of 1024 elements with this 701 host controller. The USBCMD register Frame List Size field is a read-only register and 702 should be set to zero. 703 If set to a one, then system software can specify and use a smaller frame list and 704 configure the host controller via the USBCMD register Frame List Size field. The frame 705 list must always be aligned on a 4K page boundary. This requirement ensures that the 706 frame list is always physically contiguous. */ 707 uint32_t ac64 : 1; /**< 64-bit Addressing Capability1 . This field documents the addressing range capability of 708 this implementation. The value of this field determines whether software should use the 709 data structures defined in Section 3 (32-bit) or those defined in Appendix B (64-bit). 710 Values for this field have the following interpretation: 711 - 0: data structures using 32-bit address memory pointers 712 - 1: data structures using 64-bit address memory pointers */ 713#else 714 uint32_t ac64 : 1; 715 uint32_t pflf : 1; 716 uint32_t aspc : 1; 717 uint32_t reserved_3_3 : 1; 718 uint32_t ist : 4; 719 uint32_t eecp : 8; 720 uint32_t reserved_16_31 : 16; 721#endif 722 } s; 723 struct cvmx_uahcx_ehci_hccparams_s cn63xx; 724 struct cvmx_uahcx_ehci_hccparams_s cn63xxp1; 725}; 726typedef union cvmx_uahcx_ehci_hccparams cvmx_uahcx_ehci_hccparams_t; 727 728/** 729 * cvmx_uahc#_ehci_hcsparams 730 * 731 * HCSPARAMS = Host Controller Structural Parameters 732 * This is a set of fields that are structural parameters: Number of downstream ports, etc. 733 */ 734union cvmx_uahcx_ehci_hcsparams 735{ 736 uint32_t u32; 737 struct cvmx_uahcx_ehci_hcsparams_s 738 { 739#if __BYTE_ORDER == __BIG_ENDIAN 740 uint32_t reserved_24_31 : 8; 741 uint32_t dpn : 4; /**< Debug Port Number. Optional. This register identifies which of the host controller ports 742 is the debug port. The value is the port number (one-based) of the debug port. A nonzero 743 value in this field indicates the presence of a debug port. The value in this register 744 must not be greater than N_PORTS (see below). */ 745 uint32_t reserved_17_19 : 3; 746 uint32_t p_indicator : 1; /**< Port Indicator. This bit indicates whether the ports support port 747 indicator control. When this bit is a one, the port status and control 748 registers include a read/writeable field for controlling the state of 749 the port indicator. */ 750 uint32_t n_cc : 4; /**< Number of Companion Controller. This field indicates the number of 751 companion controllers associated with this USB 2.0 host controller. 752 A zero in this field indicates there are no companion host controllers. 753 Port-ownership hand-off is not supported. Only high-speed devices are 754 supported on the host controller root ports. 755 A value larger than zero in this field indicates there are companion USB 1.1 host 756 controller(s). Port-ownership hand-offs are supported. High, Full-and Low-speed 757 devices are supported on the host controller root ports. */ 758 uint32_t n_pcc : 4; /**< Number of Ports per Companion Controller (N_PCC). This field indicates 759 the number of ports supported per companion host controller. It is used to 760 indicate the port routing configuration to system software. */ 761 uint32_t prr : 1; /**< Port Routing Rules. This field indicates the method used by this implementation for 762 how all ports are mapped to companion controllers. The value of this field has 763 the following interpretation: 764 0 The first N_PCC ports are routed to the lowest numbered function 765 companion host controller, the next N_PCC port are routed to the next 766 lowest function companion controller, and so on. 767 1 The port routing is explicitly enumerated by the first N_PORTS elements 768 of the HCSP-PORTROUTE array. */ 769 uint32_t reserved_5_6 : 2; 770 uint32_t ppc : 1; /**< Port Power Control. This field indicates whether the host controller 771 implementation includes port power control. A one in this bit indicates the ports have 772 port power switches. A zero in this bit indicates the port do not have port power 773 switches. The value of this field affects the functionality of the Port Power field 774 in each port status and control register (see Section 2.3.8). */ 775 uint32_t n_ports : 4; /**< This field specifies the number of physical downstream ports implemented 776 on this host controller. The value of this field determines how many port registers are 777 addressable in the Operational Register Space (see Table 2-8). Valid values are in the 778 range of 1H to FH. A zero in this field is undefined. */ 779#else 780 uint32_t n_ports : 4; 781 uint32_t ppc : 1; 782 uint32_t reserved_5_6 : 2; 783 uint32_t prr : 1; 784 uint32_t n_pcc : 4; 785 uint32_t n_cc : 4; 786 uint32_t p_indicator : 1; 787 uint32_t reserved_17_19 : 3; 788 uint32_t dpn : 4; 789 uint32_t reserved_24_31 : 8; 790#endif 791 } s; 792 struct cvmx_uahcx_ehci_hcsparams_s cn63xx; 793 struct cvmx_uahcx_ehci_hcsparams_s cn63xxp1; 794}; 795typedef union cvmx_uahcx_ehci_hcsparams cvmx_uahcx_ehci_hcsparams_t; 796 797/** 798 * cvmx_uahc#_ehci_insnreg00 799 * 800 * EHCI_INSNREG00 = EHCI Programmable Microframe Base Value Register (Synopsys Speicific) 801 * This register allows you to change the microframe length value (default is microframe SOF = 125 s) to reduce the simulation time. 802 */ 803union cvmx_uahcx_ehci_insnreg00 804{ 805 uint32_t u32; 806 struct cvmx_uahcx_ehci_insnreg00_s 807 { 808#if __BYTE_ORDER == __BIG_ENDIAN 809 uint32_t reserved_14_31 : 18; 810 uint32_t mfmc : 13; /**< For byte interface (8-bits), <13:1> is used as the 1-microframe counter. 811 For word interface (16_bits> <12:1> is used as the 1-microframe counter with word 812 interface (16-bits). */ 813 uint32_t en : 1; /**< Writing 1b1 enables this register. 814 Note: Do not enable this register for the gate-level netlist */ 815#else 816 uint32_t en : 1; 817 uint32_t mfmc : 13; 818 uint32_t reserved_14_31 : 18; 819#endif 820 } s; 821 struct cvmx_uahcx_ehci_insnreg00_s cn63xx; 822 struct cvmx_uahcx_ehci_insnreg00_s cn63xxp1; 823}; 824typedef union cvmx_uahcx_ehci_insnreg00 cvmx_uahcx_ehci_insnreg00_t; 825 826/** 827 * cvmx_uahc#_ehci_insnreg03 828 * 829 * EHCI_INSNREG03 = EHCI Timing Adjust Register (Synopsys Speicific) 830 * This register allows you to change the timing of Phy Tx turnaround delay etc. 831 */ 832union cvmx_uahcx_ehci_insnreg03 833{ 834 uint32_t u32; 835 struct cvmx_uahcx_ehci_insnreg03_s 836 { 837#if __BYTE_ORDER == __BIG_ENDIAN 838 uint32_t reserved_13_31 : 19; 839 uint32_t txtx_tadao : 3; /**< Tx-Tx turnaround Delay Add on. This field specifies the extra delays in phy_clks to 840 be added to the "Transmit to Transmit turnaround delay" value maintained in the core. 841 The default value of this register field is 0. This default value of 0 is sufficient 842 for most PHYs. But for some PHYs which puts wait states during the token packet, it 843 may be required to program a value greater than 0 to meet the transmit to transmit 844 minimum turnaround time. The recommendation to use the default value of 0 and change 845 it only if there is an issue with minimum transmit-to- transmit turnaround time. This 846 value should be programmed during core initialization and should not be changed afterwards. */ 847 uint32_t reserved_9_9 : 1; 848 uint32_t ta_off : 8; /**< Time-Available Offset. This value indicates the additional number of bytes to be 849 accommodated for the time-available calculation. The USB traffic on the bus can be started 850 only when sufficient time is available to complete the packet within the EOF1 point. Refer 851 to the USB 2.0 specification for details of the EOF1 point. This time-available 852 calculation is done in the hardware, and can be further offset by programming a value in 853 this location. 854 Note: Time-available calculation is added for future flexibility. The application is not 855 required to program this field by default. */ 856 uint32_t reserved_0_0 : 1; 857#else 858 uint32_t reserved_0_0 : 1; 859 uint32_t ta_off : 8; 860 uint32_t reserved_9_9 : 1; 861 uint32_t txtx_tadao : 3; 862 uint32_t reserved_13_31 : 19; 863#endif 864 } s; 865 struct cvmx_uahcx_ehci_insnreg03_s cn63xx; 866 struct cvmx_uahcx_ehci_insnreg03_s cn63xxp1; 867}; 868typedef union cvmx_uahcx_ehci_insnreg03 cvmx_uahcx_ehci_insnreg03_t; 869 870/** 871 * cvmx_uahc#_ehci_insnreg04 872 * 873 * EHCI_INSNREG04 = EHCI Debug Register (Synopsys Speicific) 874 * This register is used only for debug purposes. 875 */ 876union cvmx_uahcx_ehci_insnreg04 877{ 878 uint32_t u32; 879 struct cvmx_uahcx_ehci_insnreg04_s 880 { 881#if __BYTE_ORDER == __BIG_ENDIAN 882 uint32_t reserved_6_31 : 26; 883 uint32_t auto_dis : 1; /**< Automatic feature disable. 884 1'b0: 0 by default, the automatic feature is enabled. The Suspend signal is deasserted 885 (logic level 1'b1) when run/stop is reset by software, but the hchalted bit is not 886 yet set. 887 1'b1: Disables the automatic feature, which takes all ports out of suspend when software 888 clears the run/stop bit. This is for backward compatibility. 889 This bit has an added functionality in release 2.80a and later. For systems where the host 890 is halted without waking up all ports out of suspend, the port can become stuck because 891 the PHYCLK is not running when the halt is programmed. To avoid this, the DWC H20AHB host 892 core automatically pulls ports out of suspend when the host is halted by software. This bit 893 is used to disable this automatic function. */ 894 uint32_t nakrf_dis : 1; /**< NAK Reload Fix Disable. 895 1b0: NAK reload fix enabled. 896 1b1: NAK reload fix disabled. (Incorrect NAK reload transition at the end of a microframe 897 for backward compatibility with Release 2.40c. For more information see the USB 2.0 898 Host-AHB Release Notes. */ 899 uint32_t reserved_3_3 : 1; 900 uint32_t pesd : 1; /**< Scales down port enumeration time. 901 1'b1: scale down enabled 902 1'b0: scale downd disabled 903 This is for simulation only. */ 904 uint32_t hcp_fw : 1; /**< HCCPARAMS Field Writeable. 905 1'b1: The HCCPARAMS register's bits 17, 15:4, and 2:0 become writable. 906 1'b0: The HCCPARAMS register's bits 17, 15:4, and 2:0 are not writable. */ 907 uint32_t hcp_rw : 1; /**< HCCPARAMS Reigster Writeable. 908 1'b1: The HCCPARAMS register becomes writable. 909 1'b0: The HCCPARAMS register is not writable. */ 910#else 911 uint32_t hcp_rw : 1; 912 uint32_t hcp_fw : 1; 913 uint32_t pesd : 1; 914 uint32_t reserved_3_3 : 1; 915 uint32_t nakrf_dis : 1; 916 uint32_t auto_dis : 1; 917 uint32_t reserved_6_31 : 26; 918#endif 919 } s; 920 struct cvmx_uahcx_ehci_insnreg04_s cn63xx; 921 struct cvmx_uahcx_ehci_insnreg04_s cn63xxp1; 922}; 923typedef union cvmx_uahcx_ehci_insnreg04 cvmx_uahcx_ehci_insnreg04_t; 924 925/** 926 * cvmx_uahc#_ehci_insnreg06 927 * 928 * EHCI_INSNREG06 = EHCI AHB Error Status Register (Synopsys Speicific) 929 * This register contains AHB Error Status. 930 */ 931union cvmx_uahcx_ehci_insnreg06 932{ 933 uint32_t u32; 934 struct cvmx_uahcx_ehci_insnreg06_s 935 { 936#if __BYTE_ORDER == __BIG_ENDIAN 937 uint32_t vld : 1; /**< AHB Error Captured. Indicator that an AHB error was encountered and values were captured. 938 To clear this field the application must write a 0 to it. */ 939 uint32_t reserved_0_30 : 31; 940#else 941 uint32_t reserved_0_30 : 31; 942 uint32_t vld : 1; 943#endif 944 } s; 945 struct cvmx_uahcx_ehci_insnreg06_s cn63xx; 946 struct cvmx_uahcx_ehci_insnreg06_s cn63xxp1; 947}; 948typedef union cvmx_uahcx_ehci_insnreg06 cvmx_uahcx_ehci_insnreg06_t; 949 950/** 951 * cvmx_uahc#_ehci_insnreg07 952 * 953 * EHCI_INSNREG07 = EHCI AHB Error Address Register (Synopsys Speicific) 954 * This register contains AHB Error Status. 955 */ 956union cvmx_uahcx_ehci_insnreg07 957{ 958 uint32_t u32; 959 struct cvmx_uahcx_ehci_insnreg07_s 960 { 961#if __BYTE_ORDER == __BIG_ENDIAN 962 uint32_t err_addr : 32; /**< AHB Master Error Address. AHB address of the control phase at which the AHB error occurred */ 963#else 964 uint32_t err_addr : 32; 965#endif 966 } s; 967 struct cvmx_uahcx_ehci_insnreg07_s cn63xx; 968 struct cvmx_uahcx_ehci_insnreg07_s cn63xxp1; 969}; 970typedef union cvmx_uahcx_ehci_insnreg07 cvmx_uahcx_ehci_insnreg07_t; 971 972/** 973 * cvmx_uahc#_ehci_periodiclistbase 974 * 975 * PERIODICLISTBASE = Periodic Frame List Base Address Register 976 * 977 * This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. If the 978 * host controller is in 64-bit mode (as indicated by a one in the 64-bit Addressing Capability field in the 979 * HCCSPARAMS register), then the most significant 32 bits of every control data structure address comes 980 * from the CTRLDSSEGMENT register (see Section 2.3.5). System software loads this register prior to 981 * starting the schedule execution by the Host Controller (see 4.1). The memory structure referenced by this 982 * physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this register are combined with 983 * the Frame Index Register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List 984 * in sequence. 985 */ 986union cvmx_uahcx_ehci_periodiclistbase 987{ 988 uint32_t u32; 989 struct cvmx_uahcx_ehci_periodiclistbase_s 990 { 991#if __BYTE_ORDER == __BIG_ENDIAN 992 uint32_t baddr : 20; /**< Base Address (Low). These bits correspond to memory address signals [31:12],respectively. */ 993 uint32_t reserved_0_11 : 12; 994#else 995 uint32_t reserved_0_11 : 12; 996 uint32_t baddr : 20; 997#endif 998 } s; 999 struct cvmx_uahcx_ehci_periodiclistbase_s cn63xx; 1000 struct cvmx_uahcx_ehci_periodiclistbase_s cn63xxp1; 1001}; 1002typedef union cvmx_uahcx_ehci_periodiclistbase cvmx_uahcx_ehci_periodiclistbase_t; 1003 1004/** 1005 * cvmx_uahc#_ehci_portsc# 1006 * 1007 * PORTSCX = Port X Status and Control Register 1008 * Default: 00002000h (w/PPC set to one); 00003000h (w/PPC set to a zero) 1009 */ 1010union cvmx_uahcx_ehci_portscx 1011{ 1012 uint32_t u32; 1013 struct cvmx_uahcx_ehci_portscx_s 1014 { 1015#if __BYTE_ORDER == __BIG_ENDIAN 1016 uint32_t reserved_23_31 : 9; 1017 uint32_t wkoc_e : 1; /**< Wake on Over-current Enable.Writing this bit to a 1018 one enables the port to be sensitive to over-current conditions as wake-up events. 1019 This field is zero if Port Power is zero. */ 1020 uint32_t wkdscnnt_e : 1; /**< Wake on Disconnect Enable. Writing this bit to a one enables the port to be 1021 sensitive to device disconnects as wake-up events. 1022 This field is zero if Port Power is zero. */ 1023 uint32_t wkcnnt_e : 1; /**< Wake on Connect Enable. Writing this bit to a one enables the port to be 1024 sensitive to device connects as wake-up events. 1025 This field is zero if Port Power is zero. */ 1026 uint32_t ptc : 4; /**< Port Test Control. When this field is zero, the port is NOT 1027 operating in a test mode. A non-zero value indicates that it is operating 1028 in test mode and the specific test mode is indicated by the specific value. 1029 The encoding of the test mode bits are (0110b - 1111b are reserved): 1030 Bits Test Mode 1031 0000b Test mode not enabled 1032 0001b Test J_STATE 1033 0010b Test K_STATE 1034 0011b Test SE0_NAK 1035 0100b Test Packet 1036 0101b Test FORCE_ENABLE */ 1037 uint32_t pic : 2; /**< Port Indicator Control. Writing to these bits has no effect if the 1038 P_INDICATOR bit in the HCSPARAMS register is a zero. If P_INDICATOR bit is a one, 1039 then the bit encodings are: 1040 Bit Value Meaning 1041 00b Port indicators are off 1042 01b Amber 1043 10b Green 1044 11b Undefined 1045 This field is zero if Port Power is zero. */ 1046 uint32_t po : 1; /**< Port Owner.This bit unconditionally goes to a 0b when the 1047 Configured bit in the CONFIGFLAG register makes a 0b to 1b transition. This bit 1048 unconditionally goes to 1b whenever the Configured bit is zero. 1049 System software uses this field to release ownership of the port to a selected host 1050 controller (in the event that the attached device is not a high-speed device). Software 1051 writes a one to this bit when the attached device is not a high-speed device. A one in 1052 this bit means that a companion host controller owns and controls the port. */ 1053 uint32_t pp : 1; /**< Port Power. The function of this bit depends on the value of the Port 1054 Power Control (PPC) field in the HCSPARAMS register. The behavior is as follows: 1055 PPC PP Operation 1056 0b 1b RO - Host controller does not have port power control switches. 1057 Each port is hard-wired to power. 1058 1b 1b/0b R/W - Host controller has port power control switches. This bit 1059 represents the current setting of the switch (0 = off, 1 = on). When 1060 power is not available on a port (i.e. PP equals a 0), the port is 1061 nonfunctional and will not report attaches, detaches, etc. 1062 When an over-current condition is detected on a powered port and PPC is a one, the PP 1063 bit in each affected port may be transitioned by the host controller from a 1 to 0 1064 (removing power from the port). */ 1065 uint32_t lsts : 2; /**< Line Status.These bits reflect the current logical levels of the D+ (bit 11) and D(bit 10) 1066 signal lines. These bits are used for detection of low-speed USB devices prior to 1067 the port reset and enable sequence. This field is valid only when the port enable bit is 1068 zero and the current connect status bit is set to a one. 1069 The encoding of the bits are: 1070 Bits[11:10] USB State Interpretation 1071 00b SE0 Not Low-speed device, perform EHCI reset 1072 10b J-state Not Low-speed device, perform EHCI reset 1073 01b K-state Low-speed device, release ownership of port 1074 11b Undefined Not Low-speed device, perform EHCI reset. 1075 This value of this field is undefined if Port Power is zero. */ 1076 uint32_t reserved_9_9 : 1; 1077 uint32_t prst : 1; /**< Port Reset.1=Port is in Reset. 0=Port is not in Reset. Default = 0. When 1078 software writes a one to this bit (from a zero), the bus reset sequence as defined in the 1079 USB Specification Revision 2.0 is started. Software writes a zero to this bit to terminate 1080 the bus reset sequence. Software must keep this bit at a one long enough to ensure the 1081 reset sequence, as specified in the USB Specification Revision 2.0, completes. Note: 1082 when software writes this bit to a one, it must also write a zero to the Port Enable bit. 1083 Note that when software writes a zero to this bit there may be a delay before the bit 1084 status changes to a zero. The bit status will not read as a zero until after the reset has 1085 completed. If the port is in high-speed mode after reset is complete, the host controller 1086 will automatically enable this port (e.g. set the Port Enable bit to a one). A host controller 1087 must terminate the reset and stabilize the state of the port within 2 milliseconds of 1088 software transitioning this bit from a one to a zero. For example: if the port detects that 1089 the attached device is high-speed during reset, then the host controller must have the 1090 port in the enabled state within 2ms of software writing this bit to a zero. 1091 The HCHalted bit in the USBSTS register should be a zero before software attempts to 1092 use this bit. The host controller may hold Port Reset asserted to a one when the 1093 HCHalted bit is a one. 1094 This field is zero if Port Power is zero. */ 1095 uint32_t spd : 1; /**< Suspend. 1=Port in suspend state. 0=Port not in suspend state. Default = 0. Port 1096 Enabled Bit and Suspend bit of this register define the port states as follows: 1097 Bits [Port Enabled, Suspend] Port State 1098 0X Disable 1099 10 Enable 1100 11 Suspend 1101 When in suspend state, downstream propagation of data is blocked on this port, except 1102 for port reset. The blocking occurs at the end of the current transaction, if a transaction 1103 was in progress when this bit was written to 1. In the suspend state, the port is sensitive 1104 to resume detection. Note that the bit status does not change until the port is 1105 suspended and that there may be a delay in suspending a port if there is a transaction 1106 currently in progress on the USB. 1107 A write of zero to this bit is ignored by the host controller. The host controller will 1108 unconditionally set this bit to a zero when: 1109 . Software sets the Force Port Resume bit to a zero (from a one). 1110 . Software sets the Port Reset bit to a one (from a zero). 1111 If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is 1112 a zero) the results are undefined. 1113 This field is zero if Port Power is zero. */ 1114 uint32_t fpr : 1; /**< Force Port Resume. 1115 1= Resume detected/driven on port. 0=No resume (Kstate) 1116 detected/driven on port. Default = 0. This functionality defined for manipulating 1117 this bit depends on the value of the Suspend bit. For example, if the port is not 1118 suspended (Suspend and Enabled bits are a one) and software transitions this bit to a 1119 one, then the effects on the bus are undefined. 1120 Software sets this bit to a 1 to drive resume signaling. The Host Controller sets this bit to 1121 a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit 1122 transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in 1123 the USBSTS register is also set to a one. If software sets this bit to a one, the host 1124 controller must not set the Port Change Detect bit. 1125 Note that when the EHCI controller owns the port, the resume sequence follows the 1126 defined sequence documented in the USB Specification Revision 2.0. The resume 1127 signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. Software 1128 must appropriately time the Resume and set this bit to a zero when the appropriate 1129 amount of time has elapsed. Writing a zero (from one) causes the port to return to high- 1130 speed mode (forcing the bus below the port into a high-speed idle). This bit will remain a 1131 one until the port has switched to the high-speed idle. The host controller must complete 1132 this transition within 2 milliseconds of software setting this bit to a zero. 1133 This field is zero if Port Power is zero. */ 1134 uint32_t occ : 1; /**< Over-current Change. 1=This bit gets set to a one when there is a change to Over-current Active. 1135 Software clears this bit by writing a one to this bit position. */ 1136 uint32_t oca : 1; /**< Over-current Active. 1=This port currently has an over-current condition. 0=This port does not 1137 have an over-current condition. This bit will automatically transition from a one to a zero when 1138 the over current condition is removed. */ 1139 uint32_t pedc : 1; /**< Port Enable/Disable Change. 1=Port enabled/disabled status has changed. 1140 0=No change. Default = 0. For the root hub, this bit gets set to a one only when a port is 1141 disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of 1142 the USB Specification for the definition of a Port Error). Software clears this bit by writing 1143 a 1 to it. 1144 This field is zero if Port Power is zero. */ 1145 uint32_t ped : 1; /**< Port Enabled/Disabled. 1=Enable. 0=Disable. Ports can only be 1146 enabled by the host controller as a part of the reset and enable. Software cannot enable 1147 a port by writing a one to this field. The host controller will only set this bit to a one when 1148 the reset sequence determines that the attached device is a high-speed device. 1149 Ports can be disabled by either a fault condition (disconnect event or other fault 1150 condition) or by host software. Note that the bit status does not change until the port 1151 state actually changes. There may be a delay in disabling or enabling a port due to other 1152 host controller and bus events. See Section 4.2 for full details on port reset and enable. 1153 When the port is disabled (0b) downstream propagation of data is blocked on this port, 1154 except for reset. 1155 This field is zero if Port Power is zero. */ 1156 uint32_t csc : 1; /**< Connect Status Change. 1=Change in Current Connect Status. 0=No change. Indicates a change 1157 has occurred in the port's Current Connect Status. The host controller sets this bit for all 1158 changes to the port device connect status, even if system software has not cleared an existing 1159 connect status change. For example, the insertion status changes twice before system software 1160 has cleared the changed condition, hub hardware will be setting an already-set bit 1161 (i.e., the bit will remain set). Software sets this bit to 0 by writing a 1 to it. 1162 This field is zero if Port Power is zero. */ 1163 uint32_t ccs : 1; /**< Current Connect Status. 1=Device is present on port. 0=No device is present. 1164 This value reflects the current state of the port, and may not correspond 1165 directly to the event that caused the Connect Status Change bit (Bit 1) to be set. 1166 This field is zero if Port Power is zero. */ 1167#else 1168 uint32_t ccs : 1; 1169 uint32_t csc : 1; 1170 uint32_t ped : 1; 1171 uint32_t pedc : 1; 1172 uint32_t oca : 1; 1173 uint32_t occ : 1; 1174 uint32_t fpr : 1; 1175 uint32_t spd : 1; 1176 uint32_t prst : 1; 1177 uint32_t reserved_9_9 : 1; 1178 uint32_t lsts : 2; 1179 uint32_t pp : 1; 1180 uint32_t po : 1; 1181 uint32_t pic : 2; 1182 uint32_t ptc : 4; 1183 uint32_t wkcnnt_e : 1; 1184 uint32_t wkdscnnt_e : 1; 1185 uint32_t wkoc_e : 1; 1186 uint32_t reserved_23_31 : 9; 1187#endif 1188 } s; 1189 struct cvmx_uahcx_ehci_portscx_s cn63xx; 1190 struct cvmx_uahcx_ehci_portscx_s cn63xxp1; 1191}; 1192typedef union cvmx_uahcx_ehci_portscx cvmx_uahcx_ehci_portscx_t; 1193 1194/** 1195 * cvmx_uahc#_ehci_usbcmd 1196 * 1197 * USBCMD = USB Command Register 1198 * The Command Register indicates the command to be executed by the serial bus host controller. Writing to the register causes a command to be executed. 1199 */ 1200union cvmx_uahcx_ehci_usbcmd 1201{ 1202 uint32_t u32; 1203 struct cvmx_uahcx_ehci_usbcmd_s 1204 { 1205#if __BYTE_ORDER == __BIG_ENDIAN 1206 uint32_t reserved_24_31 : 8; 1207 uint32_t itc : 8; /**< Interrupt Threshold Control. This field is used by system software 1208 to select the maximum rate at which the host controller will issue interrupts. The only 1209 valid values are defined below. If software writes an invalid value to this register, the 1210 results are undefined. Value Maximum Interrupt Interval 1211 00h Reserved 1212 01h 1 micro-frame 1213 02h 2 micro-frames 1214 04h 4 micro-frames 1215 08h 8 micro-frames (default, equates to 1 ms) 1216 10h 16 micro-frames (2 ms) 1217 20h 32 micro-frames (4 ms) 1218 40h 64 micro-frames (8 ms) */ 1219 uint32_t reserved_12_15 : 4; 1220 uint32_t aspm_en : 1; /**< Asynchronous Schedule Park Mode Enable. */ 1221 uint32_t reserved_10_10 : 1; 1222 uint32_t aspmc : 2; /**< Asynchronous Schedule Park Mode Count. */ 1223 uint32_t lhcr : 1; /**< Light Host Controller Reset */ 1224 uint32_t iaa_db : 1; /**< Interrupt on Async Advance Doorbell.This bit is used as a doorbell by 1225 software to tell the host controller to issue an interrupt the next time it advances 1226 asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. 1227 When the host controller has evicted all appropriate cached schedule state, it sets the 1228 Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Async 1229 Advance Enable bit in the USBINTR register is a one then the host controller will assert 1230 an interrupt at the next interrupt threshold. */ 1231 uint32_t as_en : 1; /**< Asynchronous Schedule Enable .This bit controls whether the host 1232 controller skips processing the Asynchronous Schedule. Values mean: 1233 - 0: Do not process the Asynchronous Schedule 1234 - 1: Use the ASYNCLISTADDR register to access the Asynchronous Schedule. */ 1235 uint32_t ps_en : 1; /**< Periodic Schedule Enable. This bit controls whether the host 1236 controller skips processing the Periodic Schedule. Values mean: 1237 - 0: Do not process the Periodic Schedule 1238 - 1: Use the PERIODICLISTBASE register to access the Periodic Schedule. */ 1239 uint32_t fls : 2; /**< Frame List Size. This field is R/W only if Programmable 1240 Frame List Flag in the HCCPARAMS registers is set to a one. This field specifies the 1241 size of the frame list. The size the frame list controls which bits in the Frame Index 1242 Register should be used for the Frame List Current index. Values mean: 1243 00b: 1024 elements (4096 bytes) Default value 1244 01b: 512 elements (2048 bytes) 1245 10b: 256 elements (1024 bytes) - for resource-constrained environments 1246 11b: Reserved */ 1247 uint32_t hcreset : 1; /**< Host Controller Reset (HCRESET). This control bit is used by software to reset 1248 the host controller. The effects of this on Root Hub registers are similar to a Chip 1249 Hardware Reset. When software writes a one to this bit, the Host Controller resets 1250 its internal pipelines, timers, counters, state machines, etc. to their initial 1251 value. Any transaction currently in progress on USB is immediately terminated. 1252 A USB reset is not driven on downstream ports. 1253 This bit is set to zero by the Host Controller when the reset process is complete. Software can not 1254 terminate the reset process early by writing zero to this register. 1255 Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. 1256 Attempting to reset an activtely running host controller will result in undefined behavior. */ 1257 uint32_t rs : 1; /**< Run/Stop (RS). 1258 1=Run. 0=Stop. 1259 When set to a 1, the Host Controller proceeds with execution of the schedule. 1260 The Host Controller continues execution as long as this bit is set to a 1. 1261 When this bit is set to 0, the Host Controller completes the current and any 1262 actively pipelined transactions on the USB and then halts. The Host 1263 Controller must halt within 16 micro-frames after software clears the Run bit. The HC 1264 Halted bit in the status register indicates when the Host Controller has finished its 1265 pending pipelined transactions and has entered the stopped state. Software must not 1266 write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in 1267 the USBSTS register is a one). Doing so will yield undefined results. */ 1268#else 1269 uint32_t rs : 1; 1270 uint32_t hcreset : 1; 1271 uint32_t fls : 2; 1272 uint32_t ps_en : 1; 1273 uint32_t as_en : 1; 1274 uint32_t iaa_db : 1; 1275 uint32_t lhcr : 1; 1276 uint32_t aspmc : 2; 1277 uint32_t reserved_10_10 : 1; 1278 uint32_t aspm_en : 1; 1279 uint32_t reserved_12_15 : 4; 1280 uint32_t itc : 8; 1281 uint32_t reserved_24_31 : 8; 1282#endif 1283 } s; 1284 struct cvmx_uahcx_ehci_usbcmd_s cn63xx; 1285 struct cvmx_uahcx_ehci_usbcmd_s cn63xxp1; 1286}; 1287typedef union cvmx_uahcx_ehci_usbcmd cvmx_uahcx_ehci_usbcmd_t; 1288 1289/** 1290 * cvmx_uahc#_ehci_usbintr 1291 * 1292 * USBINTR = USB Interrupt Enable Register 1293 * This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set 1294 * and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are 1295 * disabled in this register still appear in the USBSTS to allow the software to poll for events. 1296 * Each interrupt enable bit description indicates whether it is dependent on the interrupt threshold mechanism. 1297 * Note: for all enable register bits, 1= Enabled, 0= Disabled 1298 */ 1299union cvmx_uahcx_ehci_usbintr 1300{ 1301 uint32_t u32; 1302 struct cvmx_uahcx_ehci_usbintr_s 1303 { 1304#if __BYTE_ORDER == __BIG_ENDIAN 1305 uint32_t reserved_6_31 : 26; 1306 uint32_t ioaa_en : 1; /**< Interrupt on Async Advance Enable When this bit is a one, and the Interrupt on 1307 Async Advance bit in the USBSTS register is a one, the host controller will issue an 1308 interrupt at the next interrupt threshold. The interrupt is acknowledged by software 1309 clearing the Interrupt on Async Advance bit. */ 1310 uint32_t hserr_en : 1; /**< Host System Error Enable When this bit is a one, and the Host System 1311 Error Status bit in the USBSTS register is a one, the host controller will issue an 1312 interrupt. The interrupt is acknowledged by software clearing the Host System Error bit. */ 1313 uint32_t flro_en : 1; /**< Frame List Rollover Enable. When this bit is a one, and the Frame List 1314 Rollover bit in the USBSTS register is a one, the host controller will issue an 1315 interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. */ 1316 uint32_t pci_en : 1; /**< Port Change Interrupt Enable. When this bit is a one, and the Port Change Detect bit in 1317 the USBSTS register is a one, the host controller will issue an interrupt. 1318 The interrupt is acknowledged by software clearing the Port Change Detect bit. */ 1319 uint32_t usberrint_en : 1; /**< USB Error Interrupt Enable. When this bit is a one, and the USBERRINT 1320 bit in the USBSTS register is a one, the host controller will issue an interrupt at the next 1321 interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit. */ 1322 uint32_t usbint_en : 1; /**< USB Interrupt Enable. When this bit is a one, and the USBINT bit in the USBSTS register 1323 is a one, the host controller will issue an interrupt at the next interrupt threshold. 1324 The interrupt is acknowledged by software clearing the USBINT bit. */ 1325#else 1326 uint32_t usbint_en : 1; 1327 uint32_t usberrint_en : 1; 1328 uint32_t pci_en : 1; 1329 uint32_t flro_en : 1; 1330 uint32_t hserr_en : 1; 1331 uint32_t ioaa_en : 1; 1332 uint32_t reserved_6_31 : 26; 1333#endif 1334 } s; 1335 struct cvmx_uahcx_ehci_usbintr_s cn63xx; 1336 struct cvmx_uahcx_ehci_usbintr_s cn63xxp1; 1337}; 1338typedef union cvmx_uahcx_ehci_usbintr cvmx_uahcx_ehci_usbintr_t; 1339 1340/** 1341 * cvmx_uahc#_ehci_usbsts 1342 * 1343 * USBSTS = USB Status Register 1344 * This register indicates pending interrupts and various states of the Host Controller. The status resulting from 1345 * a transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this register by 1346 * writing a 1 to it. 1347 */ 1348union cvmx_uahcx_ehci_usbsts 1349{ 1350 uint32_t u32; 1351 struct cvmx_uahcx_ehci_usbsts_s 1352 { 1353#if __BYTE_ORDER == __BIG_ENDIAN 1354 uint32_t reserved_16_31 : 16; 1355 uint32_t ass : 1; /**< Asynchronous Schedule Status. The bit reports the current real 1356 status of the Asynchronous Schedule. If this bit is a zero then the status of the 1357 Asynchronous Schedule is disabled. If this bit is a one then the status of the 1358 Asynchronous Schedule is enabled. The Host Controller is not required to immediately 1359 disable or enable the Asynchronous Schedule when software transitions the 1360 Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the 1361 Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is 1362 either enabled (1) or disabled (0). */ 1363 uint32_t pss : 1; /**< Periodic Schedule Status. The bit reports the current real status of 1364 the Periodic Schedule. If this bit is a zero then the status of the Periodic 1365 Schedule is disabled. If this bit is a one then the status of the Periodic Schedule 1366 is enabled. The Host Controller is not required to immediately disable or enable the 1367 Periodic Schedule when software transitions the Periodic Schedule Enable bit in 1368 the USBCMD register. When this bit and the Periodic Schedule Enable bit are the 1369 same value, the Periodic Schedule is either enabled (1) or disabled (0). */ 1370 uint32_t reclm : 1; /**< Reclamation.This is a read-only status bit, which is used to detect an 1371 empty asynchronous schedule. */ 1372 uint32_t hchtd : 1; /**< HCHalted. This bit is a zero whenever the Run/Stop bit is a one. The 1373 Host Controller sets this bit to one after it has stopped executing as a result of the 1374 Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. 1375 internal error). */ 1376 uint32_t reserved_6_11 : 6; 1377 uint32_t ioaa : 1; /**< Interrupt on Async Advance. System software can force the host 1378 controller to issue an interrupt the next time the host controller advances the 1379 asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit 1380 in the USBCMD register. This status bit indicates the assertion of that interrupt source. */ 1381 uint32_t hsyserr : 1; /**< Host System Error. The Host Controller sets this bit to 1 when a serious error 1382 occurs during a host system access involving the Host Controller module. */ 1383 uint32_t flro : 1; /**< Frame List Rollover. The Host Controller sets this bit to a one when the 1384 Frame List Index rolls over from its maximum value to zero. The exact value at 1385 which the rollover occurs depends on the frame list size. For example, if 1386 the frame list size (as programmed in the Frame List Size field of the USBCMD register) 1387 is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles. Similarly, 1388 if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] 1389 toggles. */ 1390 uint32_t pcd : 1; /**< Port Change Detect. The Host Controller sets this bit to a one when any port 1391 for which the Port Owner bit is set to zero (see Section 2.3.9) has a change bit transition 1392 from a zero to a one or a Force Port Resume bit transition from a zero to a one as a 1393 result of a J-K transition detected on a suspended port. This bit will also be set as a 1394 result of the Connect Status Change being set to a one after system software has 1395 relinquished ownership of a connected port by writing a one to a port's Port Owner bit. */ 1396 uint32_t usberrint : 1; /**< USB Error Interrupt. The Host Controller sets this bit to 1 when completion of a USB 1397 transaction results in an error condition (e.g., error counter underflow). If the TD on 1398 which the error interrupt occurred also had its IOC bit set, both this bit and USBINT 1399 bit are set. */ 1400 uint32_t usbint : 1; /**< USB Interrupt. The Host Controller sets this bit to 1 on the completion of a USB 1401 transaction, which results in the retirement of a Transfer Descriptor that had its 1402 IOC bit set. The Host Controller also sets this bit to 1 when a short packet is 1403 detected (actual number of bytes received was less than the expected number of bytes). */ 1404#else 1405 uint32_t usbint : 1; 1406 uint32_t usberrint : 1; 1407 uint32_t pcd : 1; 1408 uint32_t flro : 1; 1409 uint32_t hsyserr : 1; 1410 uint32_t ioaa : 1; 1411 uint32_t reserved_6_11 : 6; 1412 uint32_t hchtd : 1; 1413 uint32_t reclm : 1; 1414 uint32_t pss : 1; 1415 uint32_t ass : 1; 1416 uint32_t reserved_16_31 : 16; 1417#endif 1418 } s; 1419 struct cvmx_uahcx_ehci_usbsts_s cn63xx; 1420 struct cvmx_uahcx_ehci_usbsts_s cn63xxp1; 1421}; 1422typedef union cvmx_uahcx_ehci_usbsts cvmx_uahcx_ehci_usbsts_t; 1423 1424/** 1425 * cvmx_uahc#_ohci0_hcbulkcurrented 1426 * 1427 * HCBULKCURRENTED = Host Controller Bulk Current ED Register 1428 * 1429 * The HcBulkCurrentED register contains the physical address of the current endpoint of the Bulk list. As the Bulk list will be served in a round-robin 1430 * fashion, the endpoints will be ordered according to their insertion to the list. 1431 */ 1432union cvmx_uahcx_ohci0_hcbulkcurrented 1433{ 1434 uint32_t u32; 1435 struct cvmx_uahcx_ohci0_hcbulkcurrented_s 1436 { 1437#if __BYTE_ORDER == __BIG_ENDIAN 1438 uint32_t bced : 28; /**< BulkCurrentED. This is advanced to the next ED after the HC has served the 1439 present one. HC continues processing the list from where it left off in the 1440 last Frame. When it reaches the end of the Bulk list, HC checks the 1441 ControlListFilled of HcControl. If set, it copies the content of HcBulkHeadED 1442 to HcBulkCurrentED and clears the bit. If it is not set, it does nothing. 1443 HCD is only allowed to modify this register when the BulkListEnable of 1444 HcControl is cleared. When set, the HCD only reads the instantaneous value of 1445 this register. This is initially set to zero to indicate the end of the Bulk 1446 list. */ 1447 uint32_t reserved_0_3 : 4; 1448#else 1449 uint32_t reserved_0_3 : 4; 1450 uint32_t bced : 28; 1451#endif 1452 } s; 1453 struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn63xx; 1454 struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn63xxp1; 1455}; 1456typedef union cvmx_uahcx_ohci0_hcbulkcurrented cvmx_uahcx_ohci0_hcbulkcurrented_t; 1457 1458/** 1459 * cvmx_uahc#_ohci0_hcbulkheaded 1460 * 1461 * HCBULKHEADED = Host Controller Bulk Head ED Register 1462 * 1463 * The HcBulkHeadED register contains the physical address of the first Endpoint Descriptor of the Bulk list. 1464 */ 1465union cvmx_uahcx_ohci0_hcbulkheaded 1466{ 1467 uint32_t u32; 1468 struct cvmx_uahcx_ohci0_hcbulkheaded_s 1469 { 1470#if __BYTE_ORDER == __BIG_ENDIAN 1471 uint32_t bhed : 28; /**< BulkHeadED. HC traverses the Bulk list starting with the HcBulkHeadED 1472 pointer. The content is loaded from HCCA during the initialization of HC. */ 1473 uint32_t reserved_0_3 : 4; 1474#else 1475 uint32_t reserved_0_3 : 4; 1476 uint32_t bhed : 28; 1477#endif 1478 } s; 1479 struct cvmx_uahcx_ohci0_hcbulkheaded_s cn63xx; 1480 struct cvmx_uahcx_ohci0_hcbulkheaded_s cn63xxp1; 1481}; 1482typedef union cvmx_uahcx_ohci0_hcbulkheaded cvmx_uahcx_ohci0_hcbulkheaded_t; 1483 1484/** 1485 * cvmx_uahc#_ohci0_hccommandstatus 1486 * 1487 * HCCOMMANDSTATUS = Host Controller Command Status Register 1488 * 1489 * The HcCommandStatus register is used by the Host Controller to receive commands issued by the Host Controller Driver, as well as reflecting the 1490 * current status of the Host Controller. To the Host Controller Driver, it appears to be a "write to set" register. The Host Controller must ensure 1491 * that bits written as '1' become set in the register while bits written as '0' remain unchanged in the register. The Host Controller Driver 1492 * may issue multiple distinct commands to the Host Controller without concern for corrupting previously issued commands. The Host Controller Driver 1493 * has normal read access to all bits. 1494 * The SchedulingOverrunCount field indicates the number of frames with which the Host Controller has detected the scheduling overrun error. This 1495 * occurs when the Periodic list does not complete before EOF. When a scheduling overrun error is detected, the Host Controller increments the counter 1496 * and sets the SchedulingOverrun field in the HcInterruptStatus register. 1497 */ 1498union cvmx_uahcx_ohci0_hccommandstatus 1499{ 1500 uint32_t u32; 1501 struct cvmx_uahcx_ohci0_hccommandstatus_s 1502 { 1503#if __BYTE_ORDER == __BIG_ENDIAN 1504 uint32_t reserved_18_31 : 14; 1505 uint32_t soc : 2; /**< SchedulingOverrunCount. These bits are incremented on each scheduling overrun 1506 error. It is initialized to 00b and wraps around at 11b. This will be 1507 incremented when a scheduling overrun is detected even if SchedulingOverrun 1508 in HcInterruptStatus has already been set. This is used by HCD to monitor 1509 any persistent scheduling problems. */ 1510 uint32_t reserved_4_15 : 12; 1511 uint32_t ocr : 1; /**< OwnershipChangeRequest. This bit is set by an OS HCD to request a change of 1512 control of the HC. When set HC will set the OwnershipChange field in 1513 HcInterruptStatus. After the changeover, this bit is cleared and remains so 1514 until the next request from OS HCD. */ 1515 uint32_t blf : 1; /**< BulkListFilled This bit is used to indicate whether there are any TDs on the 1516 Bulk list. It is set by HCD whenever it adds a TD to an ED in the Bulk list. 1517 When HC begins to process the head of the Bulk list, it checks BF. As long 1518 as BulkListFilled is 0, HC will not start processing the Bulk list. If 1519 BulkListFilled is 1, HC will start processing the Bulk list and will set BF 1520 to 0. If HC finds a TD on the list, then HC will set BulkListFilled to 1 1521 causing the Bulk list processing to continue. If no TD is found on the Bulk 1522 list,and if HCD does not set BulkListFilled, then BulkListFilled will still 1523 be 0 when HC completes processing the Bulk list and Bulk list processing will 1524 stop. */ 1525 uint32_t clf : 1; /**< ControlListFilled. This bit is used to indicate whether there are any TDs 1526 on the Control list. It is set by HCD whenever it adds a TD to an ED in the 1527 Control list. When HC begins to process the head of the Control list, it 1528 checks CLF. As long as ControlListFilled is 0, HC will not start processing 1529 the Control list. If CF is 1, HC will start processing the Control list and 1530 will set ControlListFilled to 0. If HC finds a TD on the list, then HC will 1531 set ControlListFilled to 1 causing the Control list processing to continue. 1532 If no TD is found on the Control list, and if the HCD does not set 1533 ControlListFilled, then ControlListFilled will still be 0 when HC completes 1534 processing the Control list and Control list processing will stop. */ 1535 uint32_t hcr : 1; /**< HostControllerReset. This bit is set by HCD to initiate a software reset of 1536 HC. Regardless of the functional state of HC, it moves to the USBSUSPEND 1537 state in which most of the operational registers are reset except those 1538 stated otherwise; e.g., the InterruptRouting field of HcControl, and no 1539 Host bus accesses are allowed. This bit is cleared by HC upon the 1540 completion of the reset operation. The reset operation must be completed 1541 within 10 ms. This bit, when set, should not cause a reset to the Root Hub 1542 and no subsequent reset signaling should be asserted to its downstream ports. */ 1543#else 1544 uint32_t hcr : 1; 1545 uint32_t clf : 1; 1546 uint32_t blf : 1; 1547 uint32_t ocr : 1; 1548 uint32_t reserved_4_15 : 12; 1549 uint32_t soc : 2; 1550 uint32_t reserved_18_31 : 14; 1551#endif 1552 } s; 1553 struct cvmx_uahcx_ohci0_hccommandstatus_s cn63xx; 1554 struct cvmx_uahcx_ohci0_hccommandstatus_s cn63xxp1; 1555}; 1556typedef union cvmx_uahcx_ohci0_hccommandstatus cvmx_uahcx_ohci0_hccommandstatus_t; 1557 1558/** 1559 * cvmx_uahc#_ohci0_hccontrol 1560 * 1561 * HCCONTROL = Host Controller Control Register 1562 * 1563 * The HcControl register defines the operating modes for the Host Controller. Most of the fields in this register are modified only by the Host Controller 1564 * Driver, except HostControllerFunctionalState and RemoteWakeupConnected. 1565 */ 1566union cvmx_uahcx_ohci0_hccontrol 1567{ 1568 uint32_t u32; 1569 struct cvmx_uahcx_ohci0_hccontrol_s 1570 { 1571#if __BYTE_ORDER == __BIG_ENDIAN 1572 uint32_t reserved_11_31 : 21; 1573 uint32_t rwe : 1; /**< RemoteWakeupEnable. This bit is used by HCD to enable or disable the remote wakeup 1574 feature upon the detection of upstream resume signaling. When this bit is set and 1575 the ResumeDetected bit in HcInterruptStatus is set, a remote wakeup is signaled 1576 to the host system. Setting this bit has no impact on the generation of hardware 1577 interrupt. */ 1578 uint32_t rwc : 1; /**< RemoteWakeupConnected.This bit indicates whether HC supports remote wakeup signaling. 1579 If remote wakeup is supported and used by the system it is the responsibility of 1580 system firmware to set this bit during POST. HC clears the bit upon a hardware reset 1581 but does not alter it upon a software reset. Remote wakeup signaling of the host 1582 system is host-bus-specific and is not described in this specification. */ 1583 uint32_t ir : 1; /**< InterruptRouting 1584 This bit determines the routing of interrupts generated by events registered in 1585 HcInterruptStatus. If clear, all interrupts are routed to the normal host bus 1586 interrupt mechanism. If set, interrupts are routed to the System Management 1587 Interrupt. HCD clears this bit upon a hardware reset, but it does not alter 1588 this bit upon a software reset. HCD uses this bit as a tag to indicate the 1589 ownership of HC. */ 1590 uint32_t hcfs : 2; /**< HostControllerFunctionalState for USB 1591 00b: USBRESET 1592 01b: USBRESUME 1593 10b: USBOPERATIONAL 1594 11b: USBSUSPEND 1595 A transition to USBOPERATIONAL from another state causes SOF generation to begin 1596 1 ms later. HCD may determine whether HC has begun sending SOFs by reading the 1597 StartofFrame field of HcInterruptStatus. 1598 This field may be changed by HC only when in the USBSUSPEND state. HC may move from 1599 the USBSUSPEND state to the USBRESUME state after detecting the resume signaling 1600 from a downstream port. 1601 HC enters USBSUSPEND after a software reset, whereas it enters USBRESET after a 1602 hardware reset. The latter also resets the Root Hub and asserts subsequent reset 1603 signaling to downstream ports. */ 1604 uint32_t ble : 1; /**< BulkListEnable. This bit is set to enable the processing of the Bulk list in the 1605 next Frame. If cleared by HCD, processing of the Bulk list does not occur after 1606 the next SOF. HC checks this bit whenever it determines to process the list. When 1607 disabled, HCD may modify the list. If HcBulkCurrentED is pointing to an ED to be 1608 removed, HCD must advance the pointer by updating HcBulkCurrentED before re-enabling 1609 processing of the list. */ 1610 uint32_t cle : 1; /**< ControlListEnable. This bit is set to enable the processing of the Control list in 1611 the next Frame. If cleared by HCD, processing of the Control list does not occur 1612 after the next SOF. HC must check this bit whenever it determines to process the 1613 list. When disabled, HCD may modify the list. If HcControlCurrentED is pointing to 1614 an ED to be removed, HCD must advance the pointer by updating HcControlCurrentED 1615 before re-enabling processing of the list. */ 1616 uint32_t ie : 1; /**< IsochronousEnable This bit is used by HCD to enable/disable processing of 1617 isochronous EDs. While processing the periodic list in a Frame, HC checks the 1618 status of this bit when it finds an Isochronous ED (F=1). If set (enabled), HC 1619 continues processing the EDs. If cleared (disabled), HC halts processing of the 1620 periodic list (which now contains only isochronous EDs) and begins processing the 1621 Bulk/Control lists. Setting this bit is guaranteed to take effect in the next 1622 Frame (not the current Frame). */ 1623 uint32_t ple : 1; /**< PeriodicListEnable. This bit is set to enable the processing of the periodic list 1624 in the next Frame. If cleared by HCD, processing of the periodic list does not 1625 occur after the next SOF. HC must check this bit before it starts processing 1626 the list. */ 1627 uint32_t cbsr : 2; /**< ControlBulkServiceRatio. This specifies the service ratio between Control and 1628 Bulk EDs. Before processing any of the nonperiodic lists, HC must compare the 1629 ratio specified with its internal count on how many nonempty Control EDs have 1630 been processed, in determining whether to continue serving another Control ED 1631 or switching to Bulk EDs. The internal count will be retained when crossing 1632 the frame boundary. In case of reset, HCD is responsible for restoring this 1633 value. 1634 1635 CBSR No. of Control EDs Over Bulk EDs Served 1636 0 1:1 1637 1 2:1 1638 2 3:1 1639 3 4:1 */ 1640#else 1641 uint32_t cbsr : 2; 1642 uint32_t ple : 1; 1643 uint32_t ie : 1; 1644 uint32_t cle : 1; 1645 uint32_t ble : 1; 1646 uint32_t hcfs : 2; 1647 uint32_t ir : 1; 1648 uint32_t rwc : 1; 1649 uint32_t rwe : 1; 1650 uint32_t reserved_11_31 : 21; 1651#endif 1652 } s; 1653 struct cvmx_uahcx_ohci0_hccontrol_s cn63xx; 1654 struct cvmx_uahcx_ohci0_hccontrol_s cn63xxp1; 1655}; 1656typedef union cvmx_uahcx_ohci0_hccontrol cvmx_uahcx_ohci0_hccontrol_t; 1657 1658/** 1659 * cvmx_uahc#_ohci0_hccontrolcurrented 1660 * 1661 * HCCONTROLCURRENTED = Host Controller Control Current ED Register 1662 * 1663 * The HcControlCurrentED register contains the physical address of the current Endpoint Descriptor of the Control list. 1664 */ 1665union cvmx_uahcx_ohci0_hccontrolcurrented 1666{ 1667 uint32_t u32; 1668 struct cvmx_uahcx_ohci0_hccontrolcurrented_s 1669 { 1670#if __BYTE_ORDER == __BIG_ENDIAN 1671 uint32_t cced : 28; /**< ControlCurrentED. This pointer is advanced to the next ED after serving the 1672 present one. HC will continue processing the list from where it left off in 1673 the last Frame. When it reaches the end of the Control list, HC checks the 1674 ControlListFilled of in HcCommandStatus. If set, it copies the content of 1675 HcControlHeadED to HcControlCurrentED and clears the bit. If not set, it 1676 does nothing. HCD is allowed to modify this register only when the 1677 ControlListEnable of HcControl is cleared. When set, HCD only reads the 1678 instantaneous value of this register. Initially, this is set to zero to 1679 indicate the end of the Control list. */ 1680 uint32_t reserved_0_3 : 4; 1681#else 1682 uint32_t reserved_0_3 : 4; 1683 uint32_t cced : 28; 1684#endif 1685 } s; 1686 struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn63xx; 1687 struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn63xxp1; 1688}; 1689typedef union cvmx_uahcx_ohci0_hccontrolcurrented cvmx_uahcx_ohci0_hccontrolcurrented_t; 1690 1691/** 1692 * cvmx_uahc#_ohci0_hccontrolheaded 1693 * 1694 * HCCONTROLHEADED = Host Controller Control Head ED Register 1695 * 1696 * The HcControlHeadED register contains the physical address of the first Endpoint Descriptor of the Control list. 1697 */ 1698union cvmx_uahcx_ohci0_hccontrolheaded 1699{ 1700 uint32_t u32; 1701 struct cvmx_uahcx_ohci0_hccontrolheaded_s 1702 { 1703#if __BYTE_ORDER == __BIG_ENDIAN 1704 uint32_t ched : 28; /**< ControlHeadED. HC traverses the Control list starting with the HcControlHeadED 1705 pointer. The content is loaded from HCCA during the initialization of HC. */ 1706 uint32_t reserved_0_3 : 4; 1707#else 1708 uint32_t reserved_0_3 : 4; 1709 uint32_t ched : 28; 1710#endif 1711 } s; 1712 struct cvmx_uahcx_ohci0_hccontrolheaded_s cn63xx; 1713 struct cvmx_uahcx_ohci0_hccontrolheaded_s cn63xxp1; 1714}; 1715typedef union cvmx_uahcx_ohci0_hccontrolheaded cvmx_uahcx_ohci0_hccontrolheaded_t; 1716 1717/** 1718 * cvmx_uahc#_ohci0_hcdonehead 1719 * 1720 * HCDONEHEAD = Host Controller Done Head Register 1721 * 1722 * The HcDoneHead register contains the physical address of the last completed Transfer Descriptor that was added to the Done queue. In normal operation, 1723 * the Host Controller Driver should not need to read this register as its content is periodically written to the HCCA. 1724 */ 1725union cvmx_uahcx_ohci0_hcdonehead 1726{ 1727 uint32_t u32; 1728 struct cvmx_uahcx_ohci0_hcdonehead_s 1729 { 1730#if __BYTE_ORDER == __BIG_ENDIAN 1731 uint32_t dh : 28; /**< DoneHead. When a TD is completed, HC writes the content of HcDoneHead to the 1732 NextTD field of the TD. HC then overwrites the content of HcDoneHead with the 1733 address of this TD. This is set to zero whenever HC writes the content of 1734 this register to HCCA. It also sets the WritebackDoneHead of HcInterruptStatus. */ 1735 uint32_t reserved_0_3 : 4; 1736#else 1737 uint32_t reserved_0_3 : 4; 1738 uint32_t dh : 28; 1739#endif 1740 } s; 1741 struct cvmx_uahcx_ohci0_hcdonehead_s cn63xx; 1742 struct cvmx_uahcx_ohci0_hcdonehead_s cn63xxp1; 1743}; 1744typedef union cvmx_uahcx_ohci0_hcdonehead cvmx_uahcx_ohci0_hcdonehead_t; 1745 1746/** 1747 * cvmx_uahc#_ohci0_hcfminterval 1748 * 1749 * HCFMINTERVAL = Host Controller Frame Interval Register 1750 * 1751 * The HcFmInterval register contains a 14-bit value which indicates the bit time interval in a Frame, (i.e., between two consecutive SOFs), and a 15-bit value 1752 * indicating the Full Speed maximum packet size that the Host Controller may transmit or receive without causing scheduling overrun. The Host Controller Driver 1753 * may carry out minor adjustment on the FrameInterval by writing a new value over the present one at each SOF. This provides the programmability necessary for 1754 * the Host Controller to synchronize with an external clocking resource and to adjust any unknown local clock offset. 1755 */ 1756union cvmx_uahcx_ohci0_hcfminterval 1757{ 1758 uint32_t u32; 1759 struct cvmx_uahcx_ohci0_hcfminterval_s 1760 { 1761#if __BYTE_ORDER == __BIG_ENDIAN 1762 uint32_t fit : 1; /**< FrameIntervalToggle. HCD toggles this bit whenever it loads a new value to 1763 FrameInterval. */ 1764 uint32_t fsmps : 15; /**< FSLargestDataPacket. This field specifies a value which is loaded into the 1765 Largest Data Packet Counter at the beginning of each frame. The counter value 1766 represents the largest amount of data in bits which can be sent or received by 1767 the HC in a single transaction at any given time without causing scheduling 1768 overrun. The field value is calculated by the HCD. */ 1769 uint32_t reserved_14_15 : 2; 1770 uint32_t fi : 14; /**< FrameInterval. This specifies the interval between two consecutive SOFs in bit 1771 times. The nominal value is set to be 11,999. HCD should store the current 1772 value of this field before resetting HC. By setting the HostControllerReset 1773 field of HcCommandStatus as this will cause the HC to reset this field to its 1774 nominal value. HCD may choose to restore the stored value upon the completion 1775 of the Reset sequence. */ 1776#else 1777 uint32_t fi : 14; 1778 uint32_t reserved_14_15 : 2; 1779 uint32_t fsmps : 15; 1780 uint32_t fit : 1; 1781#endif 1782 } s; 1783 struct cvmx_uahcx_ohci0_hcfminterval_s cn63xx; 1784 struct cvmx_uahcx_ohci0_hcfminterval_s cn63xxp1; 1785}; 1786typedef union cvmx_uahcx_ohci0_hcfminterval cvmx_uahcx_ohci0_hcfminterval_t; 1787 1788/** 1789 * cvmx_uahc#_ohci0_hcfmnumber 1790 * 1791 * HCFMNUMBER = Host Cotroller Frame Number Register 1792 * 1793 * The HcFmNumber register is a 16-bit counter. It provides a timing reference among events happening in the Host Controller and the Host Controller Driver. 1794 * The Host Controller Driver may use the 16-bit value specified in this register and generate a 32-bit frame number without requiring frequent access to 1795 * the register. 1796 */ 1797union cvmx_uahcx_ohci0_hcfmnumber 1798{ 1799 uint32_t u32; 1800 struct cvmx_uahcx_ohci0_hcfmnumber_s 1801 { 1802#if __BYTE_ORDER == __BIG_ENDIAN 1803 uint32_t reserved_16_31 : 16; 1804 uint32_t fn : 16; /**< FrameNumber. This is incremented when HcFmRemaining is re-loaded. It will be 1805 rolled over to 0h after ffffh. When entering the USBOPERATIONAL state, 1806 this will be incremented automatically. The content will be written to HCCA 1807 after HC has incremented the FrameNumber at each frame boundary and sent a 1808 SOF but before HC reads the first ED in that Frame. After writing to HCCA, 1809 HC will set the StartofFrame in HcInterruptStatus. */ 1810#else 1811 uint32_t fn : 16; 1812 uint32_t reserved_16_31 : 16; 1813#endif 1814 } s; 1815 struct cvmx_uahcx_ohci0_hcfmnumber_s cn63xx; 1816 struct cvmx_uahcx_ohci0_hcfmnumber_s cn63xxp1; 1817}; 1818typedef union cvmx_uahcx_ohci0_hcfmnumber cvmx_uahcx_ohci0_hcfmnumber_t; 1819 1820/** 1821 * cvmx_uahc#_ohci0_hcfmremaining 1822 * 1823 * HCFMREMAINING = Host Controller Frame Remaining Register 1824 * The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current Frame. 1825 */ 1826union cvmx_uahcx_ohci0_hcfmremaining 1827{ 1828 uint32_t u32; 1829 struct cvmx_uahcx_ohci0_hcfmremaining_s 1830 { 1831#if __BYTE_ORDER == __BIG_ENDIAN 1832 uint32_t frt : 1; /**< FrameRemainingToggle. This bit is loaded from the FrameIntervalToggle field 1833 of HcFmInterval whenever FrameRemaining reaches 0. This bit is used by HCD 1834 for the synchronization between FrameInterval and FrameRemaining. */ 1835 uint32_t reserved_14_30 : 17; 1836 uint32_t fr : 14; /**< FrameRemaining. This counter is decremented at each bit time. When it 1837 reaches zero, it is reset by loading the FrameInterval value specified in 1838 HcFmInterval at the next bit time boundary. When entering the USBOPERATIONAL 1839 state, HC re-loads the content with the FrameInterval of HcFmInterval and uses 1840 the updated value from the next SOF. */ 1841#else 1842 uint32_t fr : 14; 1843 uint32_t reserved_14_30 : 17; 1844 uint32_t frt : 1; 1845#endif 1846 } s; 1847 struct cvmx_uahcx_ohci0_hcfmremaining_s cn63xx; 1848 struct cvmx_uahcx_ohci0_hcfmremaining_s cn63xxp1; 1849}; 1850typedef union cvmx_uahcx_ohci0_hcfmremaining cvmx_uahcx_ohci0_hcfmremaining_t; 1851 1852/** 1853 * cvmx_uahc#_ohci0_hchcca 1854 * 1855 * HCHCCA = Host Controller Host Controller Communication Area Register 1856 * 1857 * The HcHCCA register contains the physical address of the Host Controller Communication Area. The Host Controller Driver determines the alignment restrictions 1858 * by writing all 1s to HcHCCA and reading the content of HcHCCA. The alignment is evaluated by examining the number of zeroes in the lower order bits. The 1859 * minimum alignment is 256 bytes; therefore, bits 0 through 7 must always return '0' when read. Detailed description can be found in Chapter 4. This area 1860 * is used to hold the control structures and the Interrupt table that are accessed by both the Host Controller and the Host Controller Driver. 1861 */ 1862union cvmx_uahcx_ohci0_hchcca 1863{ 1864 uint32_t u32; 1865 struct cvmx_uahcx_ohci0_hchcca_s 1866 { 1867#if __BYTE_ORDER == __BIG_ENDIAN 1868 uint32_t hcca : 24; /**< This is the base address (bits [31:8]) of the Host Controller Communication Area. */ 1869 uint32_t reserved_0_7 : 8; 1870#else 1871 uint32_t reserved_0_7 : 8; 1872 uint32_t hcca : 24; 1873#endif 1874 } s; 1875 struct cvmx_uahcx_ohci0_hchcca_s cn63xx; 1876 struct cvmx_uahcx_ohci0_hchcca_s cn63xxp1; 1877}; 1878typedef union cvmx_uahcx_ohci0_hchcca cvmx_uahcx_ohci0_hchcca_t; 1879 1880/** 1881 * cvmx_uahc#_ohci0_hcinterruptdisable 1882 * 1883 * HCINTERRUPTDISABLE = Host Controller InterruptDisable Register 1884 * 1885 * Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable 1886 * register is coupled with the HcInterruptEnable register. Thus, writing a '1' to a bit in this register clears the corresponding bit in the HcInterruptEnable 1887 * register, whereas writing a '0' to a bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On read, the current 1888 * value of the HcInterruptEnable register is returned. 1889 */ 1890union cvmx_uahcx_ohci0_hcinterruptdisable 1891{ 1892 uint32_t u32; 1893 struct cvmx_uahcx_ohci0_hcinterruptdisable_s 1894 { 1895#if __BYTE_ORDER == __BIG_ENDIAN 1896 uint32_t mie : 1; /**< A '0' written to this field is ignored by HC. 1897 A '1' written to this field disables interrupt generation due to events 1898 specified in the other bits of this register. This field is set after a 1899 hardware or software reset. */ 1900 uint32_t oc : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Ownership Change. */ 1901 uint32_t reserved_7_29 : 23; 1902 uint32_t rhsc : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Root Hub Status Change. */ 1903 uint32_t fno : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Frame Number Overflow. */ 1904 uint32_t ue : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Unrecoverable Error. */ 1905 uint32_t rd : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Resume Detect. */ 1906 uint32_t sf : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Start of Frame. */ 1907 uint32_t wdh : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to HcDoneHead Writeback. */ 1908 uint32_t so : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Scheduling Overrun. */ 1909#else 1910 uint32_t so : 1; 1911 uint32_t wdh : 1; 1912 uint32_t sf : 1; 1913 uint32_t rd : 1; 1914 uint32_t ue : 1; 1915 uint32_t fno : 1; 1916 uint32_t rhsc : 1; 1917 uint32_t reserved_7_29 : 23; 1918 uint32_t oc : 1; 1919 uint32_t mie : 1; 1920#endif 1921 } s; 1922 struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn63xx; 1923 struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn63xxp1; 1924}; 1925typedef union cvmx_uahcx_ohci0_hcinterruptdisable cvmx_uahcx_ohci0_hcinterruptdisable_t; 1926 1927/** 1928 * cvmx_uahc#_ohci0_hcinterruptenable 1929 * 1930 * HCINTERRUPTENABLE = Host Controller InterruptEnable Register 1931 * 1932 * Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable 1933 * register is used to control which events generate a hardware interrupt. When a bit is set in the HcInterruptStatus register AND the corresponding bit 1934 * in the HcInterruptEnable register is set AND the MasterInterruptEnable bit is set, then a hardware interrupt is requested on the host bus. 1935 * Writing a '1' to a bit in this register sets the corresponding bit, whereas writing a '0' to a bit in this register leaves the corresponding bit 1936 * unchanged. On read, the current value of this register is returned. 1937 */ 1938union cvmx_uahcx_ohci0_hcinterruptenable 1939{ 1940 uint32_t u32; 1941 struct cvmx_uahcx_ohci0_hcinterruptenable_s 1942 { 1943#if __BYTE_ORDER == __BIG_ENDIAN 1944 uint32_t mie : 1; /**< A '0' written to this field is ignored by HC. 1945 A '1' written to this field enables interrupt generation due to events 1946 specified in the other bits of this register. This is used by HCD as a Master 1947 Interrupt Enable. */ 1948 uint32_t oc : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Ownership Change. */ 1949 uint32_t reserved_7_29 : 23; 1950 uint32_t rhsc : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Root Hub Status Change. */ 1951 uint32_t fno : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Frame Number Overflow. */ 1952 uint32_t ue : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Unrecoverable Error. */ 1953 uint32_t rd : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Resume Detect. */ 1954 uint32_t sf : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Start of Frame. */ 1955 uint32_t wdh : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to HcDoneHead Writeback. */ 1956 uint32_t so : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Scheduling Overrun. */ 1957#else 1958 uint32_t so : 1; 1959 uint32_t wdh : 1; 1960 uint32_t sf : 1; 1961 uint32_t rd : 1; 1962 uint32_t ue : 1; 1963 uint32_t fno : 1; 1964 uint32_t rhsc : 1; 1965 uint32_t reserved_7_29 : 23; 1966 uint32_t oc : 1; 1967 uint32_t mie : 1; 1968#endif 1969 } s; 1970 struct cvmx_uahcx_ohci0_hcinterruptenable_s cn63xx; 1971 struct cvmx_uahcx_ohci0_hcinterruptenable_s cn63xxp1; 1972}; 1973typedef union cvmx_uahcx_ohci0_hcinterruptenable cvmx_uahcx_ohci0_hcinterruptenable_t; 1974 1975/** 1976 * cvmx_uahc#_ohci0_hcinterruptstatus 1977 * 1978 * HCINTERRUPTSTATUS = Host Controller InterruptStatus Register 1979 * 1980 * This register provides status on various events that cause hardware interrupts. When an event occurs, Host Controller sets the corresponding bit 1981 * in this register. When a bit becomes set, a hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register 1982 * and the MasterInterruptEnable bit is set. The Host Controller Driver may clear specific bits in this register by writing '1' to bit positions 1983 * to be cleared. The Host Controller Driver may not set any of these bits. The Host Controller will never clear the bit. 1984 */ 1985union cvmx_uahcx_ohci0_hcinterruptstatus 1986{ 1987 uint32_t u32; 1988 struct cvmx_uahcx_ohci0_hcinterruptstatus_s 1989 { 1990#if __BYTE_ORDER == __BIG_ENDIAN 1991 uint32_t reserved_31_31 : 1; 1992 uint32_t oc : 1; /**< OwnershipChange. This bit is set by HC when HCD sets the OwnershipChangeRequest 1993 field in HcCommandStatus. This event, when unmasked, will always generate an 1994 System Management Interrupt (SMI) immediately. This bit is tied to 0b when the 1995 SMI pin is not implemented. */ 1996 uint32_t reserved_7_29 : 23; 1997 uint32_t rhsc : 1; /**< RootHubStatusChange. This bit is set when the content of HcRhStatus or the 1998 content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. */ 1999 uint32_t fno : 1; /**< FrameNumberOverflow. This bit is set when the MSb of HcFmNumber (bit 15) 2000 changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been 2001 updated. */ 2002 uint32_t ue : 1; /**< UnrecoverableError. This bit is set when HC detects a system error not related 2003 to USB. HC should not proceed with any processing nor signaling before the 2004 system error has been corrected. HCD clears this bit after HC has been reset. */ 2005 uint32_t rd : 1; /**< ResumeDetected. This bit is set when HC detects that a device on the USB is 2006 asserting resume signaling. It is the transition from no resume signaling to 2007 resume signaling causing this bit to be set. This bit is not set when HCD 2008 sets the USBRESUME state. */ 2009 uint32_t sf : 1; /**< StartofFrame. This bit is set by HC at each start of a frame and after the 2010 update of HccaFrameNumber. HC also generates a SOF token at the same time. */ 2011 uint32_t wdh : 1; /**< WritebackDoneHead. This bit is set immediately after HC has written 2012 HcDoneHead to HccaDoneHead. Further updates of the HccaDoneHead will not 2013 occur until this bit has been cleared. HCD should only clear this bit after 2014 it has saved the content of HccaDoneHead. */ 2015 uint32_t so : 1; /**< SchedulingOverrun. This bit is set when the USB schedule for the current 2016 Frame overruns and after the update of HccaFrameNumber. A scheduling overrun 2017 will also cause the SchedulingOverrunCount of HcCommandStatus to be 2018 incremented. */ 2019#else 2020 uint32_t so : 1; 2021 uint32_t wdh : 1; 2022 uint32_t sf : 1; 2023 uint32_t rd : 1; 2024 uint32_t ue : 1; 2025 uint32_t fno : 1; 2026 uint32_t rhsc : 1; 2027 uint32_t reserved_7_29 : 23; 2028 uint32_t oc : 1; 2029 uint32_t reserved_31_31 : 1; 2030#endif 2031 } s; 2032 struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn63xx; 2033 struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn63xxp1; 2034}; 2035typedef union cvmx_uahcx_ohci0_hcinterruptstatus cvmx_uahcx_ohci0_hcinterruptstatus_t; 2036 2037/** 2038 * cvmx_uahc#_ohci0_hclsthreshold 2039 * 2040 * HCLSTHRESHOLD = Host Controller LS Threshold Register 2041 * 2042 * The HcLSThreshold register contains an 11-bit value used by the Host Controller to determine whether to commit to the transfer of a maximum of 8-byte 2043 * LS packet before EOF. Neither the Host Controller nor the Host Controller Driver are allowed to change this value. 2044 */ 2045union cvmx_uahcx_ohci0_hclsthreshold 2046{ 2047 uint32_t u32; 2048 struct cvmx_uahcx_ohci0_hclsthreshold_s 2049 { 2050#if __BYTE_ORDER == __BIG_ENDIAN 2051 uint32_t reserved_12_31 : 20; 2052 uint32_t lst : 12; /**< LSThreshold 2053 This field contains a value which is compared to the FrameRemaining field 2054 prior to initiating a Low Speed transaction. The transaction is started only 2055 if FrameRemaining >= this field. The value is calculated by HCD 2056 with the consideration of transmission and setup overhead. */ 2057#else 2058 uint32_t lst : 12; 2059 uint32_t reserved_12_31 : 20; 2060#endif 2061 } s; 2062 struct cvmx_uahcx_ohci0_hclsthreshold_s cn63xx; 2063 struct cvmx_uahcx_ohci0_hclsthreshold_s cn63xxp1; 2064}; 2065typedef union cvmx_uahcx_ohci0_hclsthreshold cvmx_uahcx_ohci0_hclsthreshold_t; 2066 2067/** 2068 * cvmx_uahc#_ohci0_hcperiodcurrented 2069 * 2070 * HCPERIODCURRENTED = Host Controller Period Current ED Register 2071 * 2072 * The HcPeriodCurrentED register contains the physical address of the current Isochronous or Interrupt Endpoint Descriptor. 2073 */ 2074union cvmx_uahcx_ohci0_hcperiodcurrented 2075{ 2076 uint32_t u32; 2077 struct cvmx_uahcx_ohci0_hcperiodcurrented_s 2078 { 2079#if __BYTE_ORDER == __BIG_ENDIAN 2080 uint32_t pced : 28; /**< PeriodCurrentED. This is used by HC to point to the head of one of the 2081 Periodic lists which will be processed in the current Frame. The content of 2082 this register is updated by HC after a periodic ED has been processed. HCD 2083 may read the content in determining which ED is currently being processed 2084 at the time of reading. */ 2085 uint32_t reserved_0_3 : 4; 2086#else 2087 uint32_t reserved_0_3 : 4; 2088 uint32_t pced : 28; 2089#endif 2090 } s; 2091 struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn63xx; 2092 struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn63xxp1; 2093}; 2094typedef union cvmx_uahcx_ohci0_hcperiodcurrented cvmx_uahcx_ohci0_hcperiodcurrented_t; 2095 2096/** 2097 * cvmx_uahc#_ohci0_hcperiodicstart 2098 * 2099 * HCPERIODICSTART = Host Controller Periodic Start Register 2100 * 2101 * The HcPeriodicStart register has a 14-bit programmable value which determines when is the earliest time HC should start processing the periodic list. 2102 */ 2103union cvmx_uahcx_ohci0_hcperiodicstart 2104{ 2105 uint32_t u32; 2106 struct cvmx_uahcx_ohci0_hcperiodicstart_s 2107 { 2108#if __BYTE_ORDER == __BIG_ENDIAN 2109 uint32_t reserved_14_31 : 18; 2110 uint32_t ps : 14; /**< PeriodicStart After a hardware reset, this field is cleared. This is then set 2111 by HCD during the HC initialization. The value is calculated roughly as 10% 2112 off from HcFmInterval.. A typical value will be 3E67h. When HcFmRemaining 2113 reaches the value specified, processing of the periodic lists will have 2114 priority over Control/Bulk processing. HC will therefore start processing 2115 the Interrupt list after completing the current Control or Bulk transaction 2116 that is in progress. */ 2117#else 2118 uint32_t ps : 14; 2119 uint32_t reserved_14_31 : 18; 2120#endif 2121 } s; 2122 struct cvmx_uahcx_ohci0_hcperiodicstart_s cn63xx; 2123 struct cvmx_uahcx_ohci0_hcperiodicstart_s cn63xxp1; 2124}; 2125typedef union cvmx_uahcx_ohci0_hcperiodicstart cvmx_uahcx_ohci0_hcperiodicstart_t; 2126 2127/** 2128 * cvmx_uahc#_ohci0_hcrevision 2129 * 2130 * HCREVISION = Host Controller Revision Register 2131 * 2132 */ 2133union cvmx_uahcx_ohci0_hcrevision 2134{ 2135 uint32_t u32; 2136 struct cvmx_uahcx_ohci0_hcrevision_s 2137 { 2138#if __BYTE_ORDER == __BIG_ENDIAN 2139 uint32_t reserved_8_31 : 24; 2140 uint32_t rev : 8; /**< Revision This read-only field contains the BCD representation of the version 2141 of the HCI specification that is implemented by this HC. For example, a value 2142 of 11h corresponds to version 1.1. All of the HC implementations that are 2143 compliant with this specification will have a value of 10h. */ 2144#else 2145 uint32_t rev : 8; 2146 uint32_t reserved_8_31 : 24; 2147#endif 2148 } s; 2149 struct cvmx_uahcx_ohci0_hcrevision_s cn63xx; 2150 struct cvmx_uahcx_ohci0_hcrevision_s cn63xxp1; 2151}; 2152typedef union cvmx_uahcx_ohci0_hcrevision cvmx_uahcx_ohci0_hcrevision_t; 2153 2154/** 2155 * cvmx_uahc#_ohci0_hcrhdescriptora 2156 * 2157 * HCRHDESCRIPTORA = Host Controller Root Hub DescriptorA Register 2158 * 2159 * The HcRhDescriptorA register is the first register of two describing the characteristics of the Root Hub. Reset values are implementation-specific. 2160 * The descriptor length (11), descriptor type (TBD), and hub controller current (0) fields of the hub Class Descriptor are emulated by the HCD. All 2161 * other fields are located in the HcRhDescriptorA and HcRhDescriptorB registers. 2162 */ 2163union cvmx_uahcx_ohci0_hcrhdescriptora 2164{ 2165 uint32_t u32; 2166 struct cvmx_uahcx_ohci0_hcrhdescriptora_s 2167 { 2168#if __BYTE_ORDER == __BIG_ENDIAN 2169 uint32_t potpgt : 8; /**< PowerOnToPowerGoodTime. This byte specifies the duration HCD has to wait before 2170 accessing a powered-on port of the Root Hub. It is implementation-specific. The 2171 unit of time is 2 ms. The duration is calculated as POTPGT * 2 ms. */ 2172 uint32_t reserved_13_23 : 11; 2173 uint32_t nocp : 1; /**< NoOverCurrentProtection. This bit describes how the overcurrent status for the 2174 Root Hub ports are reported. When this bit is cleared, the 2175 OverCurrentProtectionMode field specifies global or per-port reporting. 2176 - 0: Over-current status is reported collectively for all downstream ports 2177 - 1: No overcurrent protection supported */ 2178 uint32_t ocpm : 1; /**< OverCurrentProtectionMode. This bit describes how the overcurrent status for 2179 the Root Hub ports are reported. At reset, this fields should reflect the same 2180 mode as PowerSwitchingMode. This field is valid only if the 2181 NoOverCurrentProtection field is cleared. 0: over-current status is reported 2182 collectively for all downstream ports 1: over-current status is reported on a 2183 per-port basis */ 2184 uint32_t dt : 1; /**< DeviceType. This bit specifies that the Root Hub is not a compound device. The 2185 Root Hub is not permitted to be a compound device. This field should always 2186 read/write 0. */ 2187 uint32_t psm : 1; /**< PowerSwitchingMode. This bit is used to specify how the power switching of 2188 the Root Hub ports is controlled. It is implementation-specific. This field 2189 is only valid if the NoPowerSwitching field is cleared. 0: all ports are 2190 powered at the same time. 1: each port is powered individually. This mode 2191 allows port power to be controlled by either the global switch or per-port 2192 switching. If the PortPowerControlMask bit is set, the port responds only 2193 to port power commands (Set/ClearPortPower). If the port mask is cleared, 2194 then the port is controlled only by the global power switch 2195 (Set/ClearGlobalPower). */ 2196 uint32_t nps : 1; /**< NoPowerSwitching These bits are used to specify whether power switching is 2197 supported or port are always powered. It is implementation-specific. When 2198 this bit is cleared, the PowerSwitchingMode specifies global or per-port 2199 switching. 2200 - 0: Ports are power switched 2201 - 1: Ports are always powered on when the HC is powered on */ 2202 uint32_t ndp : 8; /**< NumberDownstreamPorts. These bits specify the number of downstream ports 2203 supported by the Root Hub. It is implementation-specific. The minimum number 2204 of ports is 1. The maximum number of ports supported by OpenHCI is 15. */ 2205#else 2206 uint32_t ndp : 8; 2207 uint32_t nps : 1; 2208 uint32_t psm : 1; 2209 uint32_t dt : 1; 2210 uint32_t ocpm : 1; 2211 uint32_t nocp : 1; 2212 uint32_t reserved_13_23 : 11; 2213 uint32_t potpgt : 8; 2214#endif 2215 } s; 2216 struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn63xx; 2217 struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn63xxp1; 2218}; 2219typedef union cvmx_uahcx_ohci0_hcrhdescriptora cvmx_uahcx_ohci0_hcrhdescriptora_t; 2220 2221/** 2222 * cvmx_uahc#_ohci0_hcrhdescriptorb 2223 * 2224 * HCRHDESCRIPTORB = Host Controller Root Hub DescriptorB Register 2225 * 2226 * The HcRhDescriptorB register is the second register of two describing the characteristics of the Root Hub. These fields are written during 2227 * initialization to correspond with the system implementation. Reset values are implementation-specific. 2228 */ 2229union cvmx_uahcx_ohci0_hcrhdescriptorb 2230{ 2231 uint32_t u32; 2232 struct cvmx_uahcx_ohci0_hcrhdescriptorb_s 2233 { 2234#if __BYTE_ORDER == __BIG_ENDIAN 2235 uint32_t ppcm : 16; /**< PortPowerControlMask. 2236 Each bit indicates if a port is affected by a global power control command 2237 when PowerSwitchingMode is set. When set, the port's power state is only 2238 affected by per-port power control (Set/ClearPortPower). When cleared, the 2239 port is controlled by the global power switch (Set/ClearGlobalPower). If 2240 the device is configured to global switching mode (PowerSwitchingMode=0), 2241 this field is not valid. 2242 bit 0: Reserved 2243 bit 1: Ganged-power mask on Port \#1 2244 bit 2: Ganged-power mask on Port \#2 2245 - ... 2246 bit15: Ganged-power mask on Port \#15 */ 2247 uint32_t dr : 16; /**< DeviceRemovable. 2248 Each bit is dedicated to a port of the Root Hub. When cleared,the attached 2249 device is removable. When set, the attached device is not removable. 2250 bit 0: Reserved 2251 bit 1: Device attached to Port \#1 2252 bit 2: Device attached to Port \#2 2253 - ... 2254 bit15: Device attached to Port \#15 */ 2255#else 2256 uint32_t dr : 16; 2257 uint32_t ppcm : 16; 2258#endif 2259 } s; 2260 struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn63xx; 2261 struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn63xxp1; 2262}; 2263typedef union cvmx_uahcx_ohci0_hcrhdescriptorb cvmx_uahcx_ohci0_hcrhdescriptorb_t; 2264 2265/** 2266 * cvmx_uahc#_ohci0_hcrhportstatus# 2267 * 2268 * HCRHPORTSTATUSX = Host Controller Root Hub Port X Status Registers 2269 * 2270 * The HcRhPortStatus[1:NDP] register is used to control and report port events on a per-port basis. NumberDownstreamPorts represents the number 2271 * of HcRhPortStatus registers that are implemented in hardware. The lower word is used to reflect the port status, whereas the upper word reflects 2272 * the status change bits. Some status bits are implemented with special write behavior (see below). If a transaction (token through handshake) is 2273 * in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes. 2274 * Reserved bits should always be written '0'. 2275 */ 2276union cvmx_uahcx_ohci0_hcrhportstatusx 2277{ 2278 uint32_t u32; 2279 struct cvmx_uahcx_ohci0_hcrhportstatusx_s 2280 { 2281#if __BYTE_ORDER == __BIG_ENDIAN 2282 uint32_t reserved_21_31 : 11; 2283 uint32_t prsc : 1; /**< PortResetStatusChange. This bit is set at the end of the 10-ms port reset 2284 signal. The HCD writes a '1' to clear this bit. Writing a '0' has no effect. 2285 0 = port reset is not complete 2286 1 = port reset is complete */ 2287 uint32_t ocic : 1; /**< PortOverCurrentIndicatorChange. This bit is valid only if overcurrent 2288 conditions are reported on a per-port basis. This bit is set when Root Hub 2289 changes the PortOverCurrentIndicator bit. The HCD writes a '1' to clear this 2290 bit. Writing a '0' has no effect. 2291 0 = no change in PortOverCurrentIndicator 2292 1 = PortOverCurrentIndicator has changed */ 2293 uint32_t pssc : 1; /**< PortSuspendStatusChange. This bit is set when the full resume sequence has 2294 been completed. This sequence includes the 20-s resume pulse, LS EOP, and 2295 3-ms resychronization delay. 2296 The HCD writes a '1' to clear this bit. Writing a '0' has no effect. This 2297 bit is also cleared when ResetStatusChange is set. 2298 0 = resume is not completed 2299 1 = resume completed */ 2300 uint32_t pesc : 1; /**< PortEnableStatusChange. This bit is set when hardware events cause the 2301 PortEnableStatus bit to be cleared. Changes from HCD writes do not set this 2302 bit. The HCD writes a '1' to clear this bit. Writing a '0' has no effect. 2303 0 = no change in PortEnableStatus 2304 1 = change in PortEnableStatus */ 2305 uint32_t csc : 1; /**< ConnectStatusChange. This bit is set whenever a connect or disconnect event 2306 occurs. The HCD writes a '1' to clear this bit. Writing a '0' has no 2307 effect. If CurrentConnectStatus is cleared when a SetPortReset,SetPortEnable, 2308 or SetPortSuspend write occurs, this bit is set to force the driver to 2309 re-evaluate the connection status since these writes should not occur if the 2310 port is disconnected. 2311 0 = no change in CurrentConnectStatus 2312 1 = change in CurrentConnectStatus 2313 Note: If the DeviceRemovable[NDP] bit is set, this bit is set only after a 2314 Root Hub reset to inform the system that the device is attached. Description */ 2315 uint32_t reserved_10_15 : 6; 2316 uint32_t lsda : 1; /**< (read) LowSpeedDeviceAttached. This bit indicates the speed of the device 2317 attached to this port. When set, a Low Speed device is attached to this 2318 port. When clear, a Full Speed device is attached to this port. This 2319 field is valid only when the CurrentConnectStatus is set. 2320 0 = full speed device attached 2321 1 = low speed device attached 2322 (write) ClearPortPower. The HCD clears the PortPowerStatus bit by writing a 2323 '1' to this bit. Writing a '0' has no effect. */ 2324 uint32_t pps : 1; /**< (read) PortPowerStatus. This bit reflects the port's power status, regardless 2325 of the type of power switching implemented. This bit is cleared if an 2326 overcurrent condition is detected. HCD sets this bit by writing 2327 SetPortPower or SetGlobalPower. HCD clears this bit by writing 2328 ClearPortPower or ClearGlobalPower. Which power control switches are 2329 enabled is determined by PowerSwitchingMode and PortPortControlMask[NDP]. 2330 In global switching mode (PowerSwitchingMode=0), only Set/ClearGlobalPower 2331 controls this bit. In per-port power switching (PowerSwitchingMode=1), 2332 if the PortPowerControlMask[NDP] bit for the port is set, only 2333 Set/ClearPortPower commands are enabled. If the mask is not set, only 2334 Set/ClearGlobalPower commands are enabled. When port power is disabled, 2335 CurrentConnectStatus, PortEnableStatus, PortSuspendStatus, and 2336 PortResetStatus should be reset. 2337 0 = port power is off 2338 1 = port power is on 2339 (write) SetPortPower. The HCD writes a '1' to set the PortPowerStatus bit. 2340 Writing a '0' has no effect. Note: This bit is always reads '1' 2341 if power switching is not supported. */ 2342 uint32_t reserved_5_7 : 3; 2343 uint32_t prs : 1; /**< (read) PortResetStatus. When this bit is set by a write to SetPortReset, port 2344 reset signaling is asserted. When reset is completed, this bit is 2345 cleared when PortResetStatusChange is set. This bit cannot be set if 2346 CurrentConnectStatus is cleared. 2347 0 = port reset signal is not active 2348 1 = port reset signal is active 2349 (write) SetPortReset. The HCD sets the port reset signaling by writing a '1' 2350 to this bit. Writing a '0'has no effect. If CurrentConnectStatus is 2351 cleared, this write does not set PortResetStatus, but instead sets 2352 ConnectStatusChange. This informs the driver that it attempted to reset 2353 a disconnected port. Description */ 2354 uint32_t poci : 1; /**< (read) PortOverCurrentIndicator. This bit is only valid when the Root Hub is 2355 configured in such a way that overcurrent conditions are reported on a 2356 per-port basis. If per-port overcurrent reporting is not supported, this 2357 bit is set to 0. If cleared, all power operations are normal for this 2358 port. If set, an overcurrent condition exists on this port. This bit 2359 always reflects the overcurrent input signal 2360 0 = no overcurrent condition. 2361 1 = overcurrent condition detected. 2362 (write) ClearSuspendStatus. The HCD writes a '1' to initiate a resume. 2363 Writing a '0' has no effect. A resume is initiated only if 2364 PortSuspendStatus is set. */ 2365 uint32_t pss : 1; /**< (read) PortSuspendStatus. This bit indicates the port is suspended or in the 2366 resume sequence. It is set by a SetSuspendState write and cleared when 2367 PortSuspendStatusChange is set at the end of the resume interval. This 2368 bit cannot be set if CurrentConnectStatus is cleared. This bit is also 2369 cleared when PortResetStatusChange is set at the end of the port reset 2370 or when the HC is placed in the USBRESUME state. If an upstream resume is 2371 in progress, it should propagate to the HC. 2372 0 = port is not suspended 2373 1 = port is suspended 2374 (write) SetPortSuspend. The HCD sets the PortSuspendStatus bit by writing a 2375 '1' to this bit. Writing a '0' has no effect. If CurrentConnectStatus 2376 is cleared, this write does not set PortSuspendStatus; instead it sets 2377 ConnectStatusChange.This informs the driver that it attempted to suspend 2378 a disconnected port. */ 2379 uint32_t pes : 1; /**< (read) PortEnableStatus. This bit indicates whether the port is enabled or 2380 disabled. The Root Hub may clear this bit when an overcurrent condition, 2381 disconnect event, switched-off power, or operational bus error such 2382 as babble is detected. This change also causes PortEnabledStatusChange 2383 to be set. HCD sets this bit by writing SetPortEnable and clears it by 2384 writing ClearPortEnable. This bit cannot be set when CurrentConnectStatus 2385 is cleared. This bit is also set, if not already, at the completion of a 2386 port reset when ResetStatusChange is set or port suspend when 2387 SuspendStatusChange is set. 2388 0 = port is disabled 2389 1 = port is enabled 2390 (write) SetPortEnable. The HCD sets PortEnableStatus by writing a '1'. 2391 Writing a '0' has no effect. If CurrentConnectStatus is cleared, this 2392 write does not set PortEnableStatus, but instead sets ConnectStatusChange. 2393 This informs the driver that it attempted to enable a disconnected port. */ 2394 uint32_t ccs : 1; /**< (read) CurrentConnectStatus. This bit reflects the current state of the 2395 downstream port. 2396 0 = no device connected 2397 1 = device connected 2398 (write) ClearPortEnable. 2399 The HCD writes a '1' to this bit to clear the PortEnableStatus bit. 2400 Writing a '0' has no effect. The CurrentConnectStatus is not 2401 affected by any write. 2402 Note: This bit is always read '1b' when the attached device is 2403 nonremovable (DeviceRemoveable[NDP]). */ 2404#else 2405 uint32_t ccs : 1; 2406 uint32_t pes : 1; 2407 uint32_t pss : 1; 2408 uint32_t poci : 1; 2409 uint32_t prs : 1; 2410 uint32_t reserved_5_7 : 3; 2411 uint32_t pps : 1; 2412 uint32_t lsda : 1; 2413 uint32_t reserved_10_15 : 6; 2414 uint32_t csc : 1; 2415 uint32_t pesc : 1; 2416 uint32_t pssc : 1; 2417 uint32_t ocic : 1; 2418 uint32_t prsc : 1; 2419 uint32_t reserved_21_31 : 11; 2420#endif 2421 } s; 2422 struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn63xx; 2423 struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn63xxp1; 2424}; 2425typedef union cvmx_uahcx_ohci0_hcrhportstatusx cvmx_uahcx_ohci0_hcrhportstatusx_t; 2426 2427/** 2428 * cvmx_uahc#_ohci0_hcrhstatus 2429 * 2430 * HCRHSTATUS = Host Controller Root Hub Status Register 2431 * 2432 * The HcRhStatus register is divided into two parts. The lower word of a Dword represents the Hub Status field and the upper word represents the Hub 2433 * Status Change field. Reserved bits should always be written '0'. 2434 */ 2435union cvmx_uahcx_ohci0_hcrhstatus 2436{ 2437 uint32_t u32; 2438 struct cvmx_uahcx_ohci0_hcrhstatus_s 2439 { 2440#if __BYTE_ORDER == __BIG_ENDIAN 2441 uint32_t crwe : 1; /**< (write) ClearRemoteWakeupEnable Writing a '1' clears DeviceRemoveWakeupEnable. 2442 Writing a '0' has no effect. */ 2443 uint32_t reserved_18_30 : 13; 2444 uint32_t ccic : 1; /**< OverCurrentIndicatorChange. This bit is set by hardware when a change has 2445 occurred to the OCI field of this register. The HCD clears this bit by 2446 writing a '1'. Writing a '0' has no effect. */ 2447 uint32_t lpsc : 1; /**< (read) LocalPowerStatusChange. The Root Hub does not support the local power 2448 status feature; thus, this bit is always read as '0'. 2449 (write) SetGlobalPower In global power mode (PowerSwitchingMode=0), This bit 2450 is written to '1' to turn on power to all ports (clear PortPowerStatus). 2451 In per-port power mode, it sets PortPowerStatus only on ports whose 2452 PortPowerControlMask bit is not set. Writing a '0' has no effect. */ 2453 uint32_t drwe : 1; /**< (read) DeviceRemoteWakeupEnable. This bit enables a ConnectStatusChange bit as 2454 a resume event, causing a USBSUSPEND to USBRESUME state transition and 2455 setting the ResumeDetected interrupt. 0 = ConnectStatusChange is not a 2456 remote wakeup event. 1 = ConnectStatusChange is a remote wakeup event. 2457 (write) SetRemoteWakeupEnable Writing a '1' sets DeviceRemoveWakeupEnable. 2458 Writing a '0' has no effect. */ 2459 uint32_t reserved_2_14 : 13; 2460 uint32_t oci : 1; /**< OverCurrentIndicator. This bit reports overcurrent conditions when the global 2461 reporting is implemented. When set, an overcurrent condition exists. When 2462 cleared, all power operations are normal. If per-port overcurrent protection 2463 is implemented this bit is always '0' */ 2464 uint32_t lps : 1; /**< (read) LocalPowerStatus. The Root Hub does not support the local power status 2465 feature; thus, this bit is always read as '0. 2466 (write) ClearGlobalPower. In global power mode (PowerSwitchingMode=0), This 2467 bit is written to '1' to turn off power to all ports 2468 (clear PortPowerStatus). In per-port power mode, it clears 2469 PortPowerStatus only on ports whose PortPowerControlMask bit is not 2470 set. Writing a '0' has no effect. Description */ 2471#else 2472 uint32_t lps : 1; 2473 uint32_t oci : 1; 2474 uint32_t reserved_2_14 : 13; 2475 uint32_t drwe : 1; 2476 uint32_t lpsc : 1; 2477 uint32_t ccic : 1; 2478 uint32_t reserved_18_30 : 13; 2479 uint32_t crwe : 1; 2480#endif 2481 } s; 2482 struct cvmx_uahcx_ohci0_hcrhstatus_s cn63xx; 2483 struct cvmx_uahcx_ohci0_hcrhstatus_s cn63xxp1; 2484}; 2485typedef union cvmx_uahcx_ohci0_hcrhstatus cvmx_uahcx_ohci0_hcrhstatus_t; 2486 2487/** 2488 * cvmx_uahc#_ohci0_insnreg06 2489 * 2490 * OHCI0_INSNREG06 = OHCI AHB Error Status Register (Synopsys Speicific) 2491 * 2492 * This register contains AHB Error Status. 2493 */ 2494union cvmx_uahcx_ohci0_insnreg06 2495{ 2496 uint32_t u32; 2497 struct cvmx_uahcx_ohci0_insnreg06_s 2498 { 2499#if __BYTE_ORDER == __BIG_ENDIAN 2500 uint32_t vld : 1; /**< AHB Error Captured. Indicator that an AHB error was encountered and values were captured. 2501 To clear this field the application must write a 0 to it. */ 2502 uint32_t reserved_0_30 : 31; 2503#else 2504 uint32_t reserved_0_30 : 31; 2505 uint32_t vld : 1; 2506#endif 2507 } s; 2508 struct cvmx_uahcx_ohci0_insnreg06_s cn63xx; 2509 struct cvmx_uahcx_ohci0_insnreg06_s cn63xxp1; 2510}; 2511typedef union cvmx_uahcx_ohci0_insnreg06 cvmx_uahcx_ohci0_insnreg06_t; 2512 2513/** 2514 * cvmx_uahc#_ohci0_insnreg07 2515 * 2516 * OHCI0_INSNREG07 = OHCI AHB Error Address Register (Synopsys Speicific) 2517 * 2518 * This register contains AHB Error Status. 2519 */ 2520union cvmx_uahcx_ohci0_insnreg07 2521{ 2522 uint32_t u32; 2523 struct cvmx_uahcx_ohci0_insnreg07_s 2524 { 2525#if __BYTE_ORDER == __BIG_ENDIAN 2526 uint32_t err_addr : 32; /**< AHB Master Error Address. AHB address of the control phase at which the AHB error occurred */ 2527#else 2528 uint32_t err_addr : 32; 2529#endif 2530 } s; 2531 struct cvmx_uahcx_ohci0_insnreg07_s cn63xx; 2532 struct cvmx_uahcx_ohci0_insnreg07_s cn63xxp1; 2533}; 2534typedef union cvmx_uahcx_ohci0_insnreg07 cvmx_uahcx_ohci0_insnreg07_t; 2535 2536#endif 2537