cvmx-trax-defs.h revision 232812
1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-trax-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon trax. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_TRAX_DEFS_H__ 53#define __CVMX_TRAX_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_TRAX_BIST_STATUS(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 60 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 61 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 62 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 63 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 64 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 65 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 66 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 67 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 68 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 69 cvmx_warn("CVMX_TRAX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 70 return CVMX_ADD_IO_SEG(0x00011800A8000010ull) + ((block_id) & 3) * 0x100000ull; 71} 72#else 73#define CVMX_TRAX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000010ull) + ((block_id) & 3) * 0x100000ull) 74#endif 75#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 76static inline uint64_t CVMX_TRAX_CTL(unsigned long block_id) 77{ 78 if (!( 79 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 80 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 81 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 82 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 83 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 84 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 85 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 86 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 87 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 88 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 89 cvmx_warn("CVMX_TRAX_CTL(%lu) is invalid on this chip\n", block_id); 90 return CVMX_ADD_IO_SEG(0x00011800A8000000ull) + ((block_id) & 3) * 0x100000ull; 91} 92#else 93#define CVMX_TRAX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000000ull) + ((block_id) & 3) * 0x100000ull) 94#endif 95#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 96static inline uint64_t CVMX_TRAX_CYCLES_SINCE(unsigned long block_id) 97{ 98 if (!( 99 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 100 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 101 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 102 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 103 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 104 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 105 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 106 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 107 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 108 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 109 cvmx_warn("CVMX_TRAX_CYCLES_SINCE(%lu) is invalid on this chip\n", block_id); 110 return CVMX_ADD_IO_SEG(0x00011800A8000018ull) + ((block_id) & 3) * 0x100000ull; 111} 112#else 113#define CVMX_TRAX_CYCLES_SINCE(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000018ull) + ((block_id) & 3) * 0x100000ull) 114#endif 115#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116static inline uint64_t CVMX_TRAX_CYCLES_SINCE1(unsigned long block_id) 117{ 118 if (!( 119 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 120 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 121 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 122 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 123 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 124 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 125 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 126 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 127 cvmx_warn("CVMX_TRAX_CYCLES_SINCE1(%lu) is invalid on this chip\n", block_id); 128 return CVMX_ADD_IO_SEG(0x00011800A8000028ull) + ((block_id) & 3) * 0x100000ull; 129} 130#else 131#define CVMX_TRAX_CYCLES_SINCE1(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000028ull) + ((block_id) & 3) * 0x100000ull) 132#endif 133#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 134static inline uint64_t CVMX_TRAX_FILT_ADR_ADR(unsigned long block_id) 135{ 136 if (!( 137 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 138 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 139 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 140 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 141 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 142 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 143 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 144 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 145 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 146 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 147 cvmx_warn("CVMX_TRAX_FILT_ADR_ADR(%lu) is invalid on this chip\n", block_id); 148 return CVMX_ADD_IO_SEG(0x00011800A8000058ull) + ((block_id) & 3) * 0x100000ull; 149} 150#else 151#define CVMX_TRAX_FILT_ADR_ADR(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000058ull) + ((block_id) & 3) * 0x100000ull) 152#endif 153#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 154static inline uint64_t CVMX_TRAX_FILT_ADR_MSK(unsigned long block_id) 155{ 156 if (!( 157 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 158 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 159 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 160 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 161 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 162 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 163 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 164 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 165 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 166 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 167 cvmx_warn("CVMX_TRAX_FILT_ADR_MSK(%lu) is invalid on this chip\n", block_id); 168 return CVMX_ADD_IO_SEG(0x00011800A8000060ull) + ((block_id) & 3) * 0x100000ull; 169} 170#else 171#define CVMX_TRAX_FILT_ADR_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000060ull) + ((block_id) & 3) * 0x100000ull) 172#endif 173#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 174static inline uint64_t CVMX_TRAX_FILT_CMD(unsigned long block_id) 175{ 176 if (!( 177 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 178 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 179 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 180 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 181 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 182 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 183 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 184 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 185 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 186 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 187 cvmx_warn("CVMX_TRAX_FILT_CMD(%lu) is invalid on this chip\n", block_id); 188 return CVMX_ADD_IO_SEG(0x00011800A8000040ull) + ((block_id) & 3) * 0x100000ull; 189} 190#else 191#define CVMX_TRAX_FILT_CMD(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000040ull) + ((block_id) & 3) * 0x100000ull) 192#endif 193#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 194static inline uint64_t CVMX_TRAX_FILT_DID(unsigned long block_id) 195{ 196 if (!( 197 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 198 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 199 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 200 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 201 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 202 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 203 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 204 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 205 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 206 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 207 cvmx_warn("CVMX_TRAX_FILT_DID(%lu) is invalid on this chip\n", block_id); 208 return CVMX_ADD_IO_SEG(0x00011800A8000050ull) + ((block_id) & 3) * 0x100000ull; 209} 210#else 211#define CVMX_TRAX_FILT_DID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000050ull) + ((block_id) & 3) * 0x100000ull) 212#endif 213#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 214static inline uint64_t CVMX_TRAX_FILT_SID(unsigned long block_id) 215{ 216 if (!( 217 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 218 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 219 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 220 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 221 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 222 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 223 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 224 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 225 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 226 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 227 cvmx_warn("CVMX_TRAX_FILT_SID(%lu) is invalid on this chip\n", block_id); 228 return CVMX_ADD_IO_SEG(0x00011800A8000048ull) + ((block_id) & 3) * 0x100000ull; 229} 230#else 231#define CVMX_TRAX_FILT_SID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000048ull) + ((block_id) & 3) * 0x100000ull) 232#endif 233#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 234static inline uint64_t CVMX_TRAX_INT_STATUS(unsigned long block_id) 235{ 236 if (!( 237 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 238 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 239 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 240 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 241 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 242 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 243 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 244 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 245 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 246 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 247 cvmx_warn("CVMX_TRAX_INT_STATUS(%lu) is invalid on this chip\n", block_id); 248 return CVMX_ADD_IO_SEG(0x00011800A8000008ull) + ((block_id) & 3) * 0x100000ull; 249} 250#else 251#define CVMX_TRAX_INT_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000008ull) + ((block_id) & 3) * 0x100000ull) 252#endif 253#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254static inline uint64_t CVMX_TRAX_READ_DAT(unsigned long block_id) 255{ 256 if (!( 257 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 258 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 259 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 260 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 261 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 262 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 263 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 264 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 265 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 266 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 267 cvmx_warn("CVMX_TRAX_READ_DAT(%lu) is invalid on this chip\n", block_id); 268 return CVMX_ADD_IO_SEG(0x00011800A8000020ull) + ((block_id) & 3) * 0x100000ull; 269} 270#else 271#define CVMX_TRAX_READ_DAT(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000020ull) + ((block_id) & 3) * 0x100000ull) 272#endif 273#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 274static inline uint64_t CVMX_TRAX_READ_DAT_HI(unsigned long block_id) 275{ 276 if (!( 277 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 278 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 279 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 280 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 281 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 282 cvmx_warn("CVMX_TRAX_READ_DAT_HI(%lu) is invalid on this chip\n", block_id); 283 return CVMX_ADD_IO_SEG(0x00011800A8000030ull) + ((block_id) & 3) * 0x100000ull; 284} 285#else 286#define CVMX_TRAX_READ_DAT_HI(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000030ull) + ((block_id) & 3) * 0x100000ull) 287#endif 288#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 289static inline uint64_t CVMX_TRAX_TRIG0_ADR_ADR(unsigned long block_id) 290{ 291 if (!( 292 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 293 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 294 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 295 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 296 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 297 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 298 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 299 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 300 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 301 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 302 cvmx_warn("CVMX_TRAX_TRIG0_ADR_ADR(%lu) is invalid on this chip\n", block_id); 303 return CVMX_ADD_IO_SEG(0x00011800A8000098ull) + ((block_id) & 3) * 0x100000ull; 304} 305#else 306#define CVMX_TRAX_TRIG0_ADR_ADR(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000098ull) + ((block_id) & 3) * 0x100000ull) 307#endif 308#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309static inline uint64_t CVMX_TRAX_TRIG0_ADR_MSK(unsigned long block_id) 310{ 311 if (!( 312 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 313 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 314 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 315 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 316 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 317 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 318 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 319 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 320 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 321 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 322 cvmx_warn("CVMX_TRAX_TRIG0_ADR_MSK(%lu) is invalid on this chip\n", block_id); 323 return CVMX_ADD_IO_SEG(0x00011800A80000A0ull) + ((block_id) & 3) * 0x100000ull; 324} 325#else 326#define CVMX_TRAX_TRIG0_ADR_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000A0ull) + ((block_id) & 3) * 0x100000ull) 327#endif 328#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 329static inline uint64_t CVMX_TRAX_TRIG0_CMD(unsigned long block_id) 330{ 331 if (!( 332 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 333 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 334 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 335 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 336 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 337 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 338 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 339 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 340 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 341 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 342 cvmx_warn("CVMX_TRAX_TRIG0_CMD(%lu) is invalid on this chip\n", block_id); 343 return CVMX_ADD_IO_SEG(0x00011800A8000080ull) + ((block_id) & 3) * 0x100000ull; 344} 345#else 346#define CVMX_TRAX_TRIG0_CMD(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000080ull) + ((block_id) & 3) * 0x100000ull) 347#endif 348#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 349static inline uint64_t CVMX_TRAX_TRIG0_DID(unsigned long block_id) 350{ 351 if (!( 352 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 353 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 354 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 355 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 356 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 357 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 358 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 359 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 360 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 361 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 362 cvmx_warn("CVMX_TRAX_TRIG0_DID(%lu) is invalid on this chip\n", block_id); 363 return CVMX_ADD_IO_SEG(0x00011800A8000090ull) + ((block_id) & 3) * 0x100000ull; 364} 365#else 366#define CVMX_TRAX_TRIG0_DID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000090ull) + ((block_id) & 3) * 0x100000ull) 367#endif 368#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 369static inline uint64_t CVMX_TRAX_TRIG0_SID(unsigned long block_id) 370{ 371 if (!( 372 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 373 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 374 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 375 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 376 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 377 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 378 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 379 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 380 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 381 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 382 cvmx_warn("CVMX_TRAX_TRIG0_SID(%lu) is invalid on this chip\n", block_id); 383 return CVMX_ADD_IO_SEG(0x00011800A8000088ull) + ((block_id) & 3) * 0x100000ull; 384} 385#else 386#define CVMX_TRAX_TRIG0_SID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000088ull) + ((block_id) & 3) * 0x100000ull) 387#endif 388#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 389static inline uint64_t CVMX_TRAX_TRIG1_ADR_ADR(unsigned long block_id) 390{ 391 if (!( 392 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 393 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 394 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 395 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 396 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 397 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 398 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 399 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 400 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 401 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 402 cvmx_warn("CVMX_TRAX_TRIG1_ADR_ADR(%lu) is invalid on this chip\n", block_id); 403 return CVMX_ADD_IO_SEG(0x00011800A80000D8ull) + ((block_id) & 3) * 0x100000ull; 404} 405#else 406#define CVMX_TRAX_TRIG1_ADR_ADR(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000D8ull) + ((block_id) & 3) * 0x100000ull) 407#endif 408#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 409static inline uint64_t CVMX_TRAX_TRIG1_ADR_MSK(unsigned long block_id) 410{ 411 if (!( 412 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 413 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 414 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 415 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 416 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 417 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 418 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 419 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 420 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 421 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 422 cvmx_warn("CVMX_TRAX_TRIG1_ADR_MSK(%lu) is invalid on this chip\n", block_id); 423 return CVMX_ADD_IO_SEG(0x00011800A80000E0ull) + ((block_id) & 3) * 0x100000ull; 424} 425#else 426#define CVMX_TRAX_TRIG1_ADR_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000E0ull) + ((block_id) & 3) * 0x100000ull) 427#endif 428#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 429static inline uint64_t CVMX_TRAX_TRIG1_CMD(unsigned long block_id) 430{ 431 if (!( 432 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 433 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 434 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 435 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 436 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 437 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 438 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 439 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 440 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 441 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 442 cvmx_warn("CVMX_TRAX_TRIG1_CMD(%lu) is invalid on this chip\n", block_id); 443 return CVMX_ADD_IO_SEG(0x00011800A80000C0ull) + ((block_id) & 3) * 0x100000ull; 444} 445#else 446#define CVMX_TRAX_TRIG1_CMD(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000C0ull) + ((block_id) & 3) * 0x100000ull) 447#endif 448#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 449static inline uint64_t CVMX_TRAX_TRIG1_DID(unsigned long block_id) 450{ 451 if (!( 452 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 453 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 454 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 455 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 456 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 457 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 458 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 459 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 460 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 461 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 462 cvmx_warn("CVMX_TRAX_TRIG1_DID(%lu) is invalid on this chip\n", block_id); 463 return CVMX_ADD_IO_SEG(0x00011800A80000D0ull) + ((block_id) & 3) * 0x100000ull; 464} 465#else 466#define CVMX_TRAX_TRIG1_DID(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000D0ull) + ((block_id) & 3) * 0x100000ull) 467#endif 468#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 469static inline uint64_t CVMX_TRAX_TRIG1_SID(unsigned long block_id) 470{ 471 if (!( 472 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 473 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 474 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 475 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 476 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 477 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 478 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 479 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 480 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 481 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 482 cvmx_warn("CVMX_TRAX_TRIG1_SID(%lu) is invalid on this chip\n", block_id); 483 return CVMX_ADD_IO_SEG(0x00011800A80000C8ull) + ((block_id) & 3) * 0x100000ull; 484} 485#else 486#define CVMX_TRAX_TRIG1_SID(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000C8ull) + ((block_id) & 3) * 0x100000ull) 487#endif 488 489/** 490 * cvmx_tra#_bist_status 491 * 492 * TRA_BIST_STATUS = Trace Buffer BiST Status 493 * 494 * Description: 495 */ 496union cvmx_trax_bist_status { 497 uint64_t u64; 498 struct cvmx_trax_bist_status_s { 499#ifdef __BIG_ENDIAN_BITFIELD 500 uint64_t reserved_3_63 : 61; 501 uint64_t tcf : 1; /**< Bist Results for TCF memory 502 - 0: GOOD (or bist in progress/never run) 503 - 1: BAD */ 504 uint64_t tdf1 : 1; /**< Bist Results for TDF memory 1 505 - 0: GOOD (or bist in progress/never run) 506 - 1: BAD */ 507 uint64_t reserved_0_0 : 1; 508#else 509 uint64_t reserved_0_0 : 1; 510 uint64_t tdf1 : 1; 511 uint64_t tcf : 1; 512 uint64_t reserved_3_63 : 61; 513#endif 514 } s; 515 struct cvmx_trax_bist_status_cn31xx { 516#ifdef __BIG_ENDIAN_BITFIELD 517 uint64_t reserved_3_63 : 61; 518 uint64_t tcf : 1; /**< Bist Results for TCF memory 519 - 0: GOOD (or bist in progress/never run) 520 - 1: BAD */ 521 uint64_t tdf1 : 1; /**< Bist Results for TDF memory 1 522 - 0: GOOD (or bist in progress/never run) 523 - 1: BAD */ 524 uint64_t tdf0 : 1; /**< Bist Results for TCF memory 0 525 - 0: GOOD (or bist in progress/never run) 526 - 1: BAD */ 527#else 528 uint64_t tdf0 : 1; 529 uint64_t tdf1 : 1; 530 uint64_t tcf : 1; 531 uint64_t reserved_3_63 : 61; 532#endif 533 } cn31xx; 534 struct cvmx_trax_bist_status_cn31xx cn38xx; 535 struct cvmx_trax_bist_status_cn31xx cn38xxp2; 536 struct cvmx_trax_bist_status_cn31xx cn52xx; 537 struct cvmx_trax_bist_status_cn31xx cn52xxp1; 538 struct cvmx_trax_bist_status_cn31xx cn56xx; 539 struct cvmx_trax_bist_status_cn31xx cn56xxp1; 540 struct cvmx_trax_bist_status_cn31xx cn58xx; 541 struct cvmx_trax_bist_status_cn31xx cn58xxp1; 542 struct cvmx_trax_bist_status_cn61xx { 543#ifdef __BIG_ENDIAN_BITFIELD 544 uint64_t reserved_1_63 : 63; 545 uint64_t tdf : 1; /**< Bist Results for TCF memory 546 - 0: GOOD (or bist in progress/never run) 547 - 1: BAD */ 548#else 549 uint64_t tdf : 1; 550 uint64_t reserved_1_63 : 63; 551#endif 552 } cn61xx; 553 struct cvmx_trax_bist_status_cn61xx cn63xx; 554 struct cvmx_trax_bist_status_cn61xx cn63xxp1; 555 struct cvmx_trax_bist_status_cn61xx cn66xx; 556 struct cvmx_trax_bist_status_cn61xx cn68xx; 557 struct cvmx_trax_bist_status_cn61xx cn68xxp1; 558 struct cvmx_trax_bist_status_cn61xx cnf71xx; 559}; 560typedef union cvmx_trax_bist_status cvmx_trax_bist_status_t; 561 562/** 563 * cvmx_tra#_ctl 564 * 565 * TRA_CTL = Trace Buffer Control 566 * 567 * Description: 568 * 569 * Notes: 570 * It is illegal to change the values of WRAP, TRIG_CTL, IGNORE_O while tracing (i.e. when ENA=1). 571 * Note that the following fields are present only in chip revisions beginning with pass2: IGNORE_O 572 */ 573union cvmx_trax_ctl { 574 uint64_t u64; 575 struct cvmx_trax_ctl_s { 576#ifdef __BIG_ENDIAN_BITFIELD 577 uint64_t reserved_17_63 : 47; 578 uint64_t rdat_md : 1; /**< TRA_READ_DAT mode bit 579 If set, the TRA_READ_DAT reads will return the lower 580 64 bits of the TRA entry and the upper bits must be 581 read through TRA_READ_DAT_HI. If not set the return 582 value from TRA_READ_DAT accesses will switch between 583 the lower bits and the upper bits of the TRA entry. */ 584 uint64_t clkalways : 1; /**< Conditional clock enable 585 If set, the TRA clock is never disabled. */ 586 uint64_t ignore_o : 1; /**< Ignore overflow during wrap mode 587 If set and wrapping mode is enabled, then tracing 588 will not stop at the overflow condition. Each 589 write during an overflow will overwrite the 590 oldest, unread entry and the read pointer is 591 incremented by one entry. This bit has no effect 592 if WRAP=0. */ 593 uint64_t mcd0_ena : 1; /**< MCD0 enable 594 If set and any PP sends the MCD0 signal, the 595 tracing is disabled. */ 596 uint64_t mcd0_thr : 1; /**< MCD0_threshold 597 At a fill threshold event, sends an MCD0 598 wire pulse that can cause cores to enter debug 599 mode, if enabled. This MCD0 wire pulse will not 600 occur while (TRA_INT_STATUS.MCD0_THR == 1). */ 601 uint64_t mcd0_trg : 1; /**< MCD0_trigger 602 At an end trigger event, sends an MCD0 603 wire pulse that can cause cores to enter debug 604 mode, if enabled. This MCD0 wire pulse will not 605 occur while (TRA_INT_STATUS.MCD0_TRG == 1). */ 606 uint64_t ciu_thr : 1; /**< CIU_threshold 607 When set during a fill threshold event, 608 TRA_INT_STATUS[CIU_THR] is set, which can cause 609 core interrupts, if enabled. */ 610 uint64_t ciu_trg : 1; /**< CIU_trigger 611 When set during an end trigger event, 612 TRA_INT_STATUS[CIU_TRG] is set, which can cause 613 core interrupts, if enabled. */ 614 uint64_t full_thr : 2; /**< Full Threshhold 615 0=none 616 1=1/2 full 617 2=3/4 full 618 3=4/4 full */ 619 uint64_t time_grn : 3; /**< Timestamp granularity 620 granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */ 621 uint64_t trig_ctl : 2; /**< Trigger Control 622 Note: trigger events are written to the trace 623 0=no triggers 624 1=trigger0=start trigger, trigger1=stop trigger 625 2=(trigger0 || trigger1)=start trigger 626 3=(trigger0 || trigger1)=stop trigger */ 627 uint64_t wrap : 1; /**< Wrap mode 628 When WRAP=0, the trace buffer will disable itself 629 after having logged 1024 entries. When WRAP=1, 630 the trace buffer will never disable itself. 631 In this case, tracing may or may not be 632 temporarily suspended during the overflow 633 condition (see IGNORE_O above). 634 0=do not wrap 635 1=wrap */ 636 uint64_t ena : 1; /**< Enable Trace 637 Master enable. Tracing only happens when ENA=1. 638 When ENA changes from 0 to 1, the read and write 639 pointers are reset to 0x00 to begin a new trace. 640 The MCD0 event may set ENA=0 (see MCD0_ENA 641 above). When using triggers, tracing occurs only 642 between start and stop triggers (including the 643 triggers themselves). 644 0=disable 645 1=enable */ 646#else 647 uint64_t ena : 1; 648 uint64_t wrap : 1; 649 uint64_t trig_ctl : 2; 650 uint64_t time_grn : 3; 651 uint64_t full_thr : 2; 652 uint64_t ciu_trg : 1; 653 uint64_t ciu_thr : 1; 654 uint64_t mcd0_trg : 1; 655 uint64_t mcd0_thr : 1; 656 uint64_t mcd0_ena : 1; 657 uint64_t ignore_o : 1; 658 uint64_t clkalways : 1; 659 uint64_t rdat_md : 1; 660 uint64_t reserved_17_63 : 47; 661#endif 662 } s; 663 struct cvmx_trax_ctl_cn31xx { 664#ifdef __BIG_ENDIAN_BITFIELD 665 uint64_t reserved_15_63 : 49; 666 uint64_t ignore_o : 1; /**< Ignore overflow during wrap mode 667 If set and wrapping mode is enabled, then tracing 668 will not stop at the overflow condition. Each 669 write during an overflow will overwrite the 670 oldest, unread entry and the read pointer is 671 incremented by one entry. This bit has no effect 672 if WRAP=0. */ 673 uint64_t mcd0_ena : 1; /**< MCD0 enable 674 If set and any PP sends the MCD0 signal, the 675 tracing is disabled. */ 676 uint64_t mcd0_thr : 1; /**< MCD0_threshold 677 At a fill threshold event, sends an MCD0 678 wire pulse that can cause cores to enter debug 679 mode, if enabled. This MCD0 wire pulse will not 680 occur while (TRA(0..0)_INT_STATUS.MCD0_THR == 1). */ 681 uint64_t mcd0_trg : 1; /**< MCD0_trigger 682 At an end trigger event, sends an MCD0 683 wire pulse that can cause cores to enter debug 684 mode, if enabled. This MCD0 wire pulse will not 685 occur while (TRA(0..0)_INT_STATUS.MCD0_TRG == 1). */ 686 uint64_t ciu_thr : 1; /**< CIU_threshold 687 When set during a fill threshold event, 688 TRA(0..0)_INT_STATUS[CIU_THR] is set, which can cause 689 core interrupts, if enabled. */ 690 uint64_t ciu_trg : 1; /**< CIU_trigger 691 When set during an end trigger event, 692 TRA(0..0)_INT_STATUS[CIU_TRG] is set, which can cause 693 core interrupts, if enabled. */ 694 uint64_t full_thr : 2; /**< Full Threshhold 695 0=none 696 1=1/2 full 697 2=3/4 full 698 3=4/4 full */ 699 uint64_t time_grn : 3; /**< Timestamp granularity 700 granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */ 701 uint64_t trig_ctl : 2; /**< Trigger Control 702 Note: trigger events are written to the trace 703 0=no triggers 704 1=trigger0=start trigger, trigger1=stop trigger 705 2=(trigger0 || trigger1)=start trigger 706 3=(trigger0 || trigger1)=stop trigger */ 707 uint64_t wrap : 1; /**< Wrap mode 708 When WRAP=0, the trace buffer will disable itself 709 after having logged 256 entries. When WRAP=1, 710 the trace buffer will never disable itself. 711 In this case, tracing may or may not be 712 temporarily suspended during the overflow 713 condition (see IGNORE_O above). 714 0=do not wrap 715 1=wrap */ 716 uint64_t ena : 1; /**< Enable Trace 717 Master enable. Tracing only happens when ENA=1. 718 When ENA changes from 0 to 1, the read and write 719 pointers are reset to 0x00 to begin a new trace. 720 The MCD0 event may set ENA=0 (see MCD0_ENA 721 above). When using triggers, tracing occurs only 722 between start and stop triggers (including the 723 triggers themselves). 724 0=disable 725 1=enable */ 726#else 727 uint64_t ena : 1; 728 uint64_t wrap : 1; 729 uint64_t trig_ctl : 2; 730 uint64_t time_grn : 3; 731 uint64_t full_thr : 2; 732 uint64_t ciu_trg : 1; 733 uint64_t ciu_thr : 1; 734 uint64_t mcd0_trg : 1; 735 uint64_t mcd0_thr : 1; 736 uint64_t mcd0_ena : 1; 737 uint64_t ignore_o : 1; 738 uint64_t reserved_15_63 : 49; 739#endif 740 } cn31xx; 741 struct cvmx_trax_ctl_cn31xx cn38xx; 742 struct cvmx_trax_ctl_cn31xx cn38xxp2; 743 struct cvmx_trax_ctl_cn31xx cn52xx; 744 struct cvmx_trax_ctl_cn31xx cn52xxp1; 745 struct cvmx_trax_ctl_cn31xx cn56xx; 746 struct cvmx_trax_ctl_cn31xx cn56xxp1; 747 struct cvmx_trax_ctl_cn31xx cn58xx; 748 struct cvmx_trax_ctl_cn31xx cn58xxp1; 749 struct cvmx_trax_ctl_s cn61xx; 750 struct cvmx_trax_ctl_s cn63xx; 751 struct cvmx_trax_ctl_cn63xxp1 { 752#ifdef __BIG_ENDIAN_BITFIELD 753 uint64_t reserved_16_63 : 48; 754 uint64_t clkalways : 1; /**< Conditional clock enable 755 If set, the TRA clock is never disabled. */ 756 uint64_t ignore_o : 1; /**< Ignore overflow during wrap mode 757 If set and wrapping mode is enabled, then tracing 758 will not stop at the overflow condition. Each 759 write during an overflow will overwrite the 760 oldest, unread entry and the read pointer is 761 incremented by one entry. This bit has no effect 762 if WRAP=0. */ 763 uint64_t mcd0_ena : 1; /**< MCD0 enable 764 If set and any PP sends the MCD0 signal, the 765 tracing is disabled. */ 766 uint64_t mcd0_thr : 1; /**< MCD0_threshold 767 At a fill threshold event, sends an MCD0 768 wire pulse that can cause cores to enter debug 769 mode, if enabled. This MCD0 wire pulse will not 770 occur while (TRA_INT_STATUS.MCD0_THR == 1). */ 771 uint64_t mcd0_trg : 1; /**< MCD0_trigger 772 At an end trigger event, sends an MCD0 773 wire pulse that can cause cores to enter debug 774 mode, if enabled. This MCD0 wire pulse will not 775 occur while (TRA_INT_STATUS.MCD0_TRG == 1). */ 776 uint64_t ciu_thr : 1; /**< CIU_threshold 777 When set during a fill threshold event, 778 TRA_INT_STATUS[CIU_THR] is set, which can cause 779 core interrupts, if enabled. */ 780 uint64_t ciu_trg : 1; /**< CIU_trigger 781 When set during an end trigger event, 782 TRA_INT_STATUS[CIU_TRG] is set, which can cause 783 core interrupts, if enabled. */ 784 uint64_t full_thr : 2; /**< Full Threshhold 785 0=none 786 1=1/2 full 787 2=3/4 full 788 3=4/4 full */ 789 uint64_t time_grn : 3; /**< Timestamp granularity 790 granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */ 791 uint64_t trig_ctl : 2; /**< Trigger Control 792 Note: trigger events are written to the trace 793 0=no triggers 794 1=trigger0=start trigger, trigger1=stop trigger 795 2=(trigger0 || trigger1)=start trigger 796 3=(trigger0 || trigger1)=stop trigger */ 797 uint64_t wrap : 1; /**< Wrap mode 798 When WRAP=0, the trace buffer will disable itself 799 after having logged 1024 entries. When WRAP=1, 800 the trace buffer will never disable itself. 801 In this case, tracing may or may not be 802 temporarily suspended during the overflow 803 condition (see IGNORE_O above). 804 0=do not wrap 805 1=wrap */ 806 uint64_t ena : 1; /**< Enable Trace 807 Master enable. Tracing only happens when ENA=1. 808 When ENA changes from 0 to 1, the read and write 809 pointers are reset to 0x00 to begin a new trace. 810 The MCD0 event may set ENA=0 (see MCD0_ENA 811 above). When using triggers, tracing occurs only 812 between start and stop triggers (including the 813 triggers themselves). 814 0=disable 815 1=enable */ 816#else 817 uint64_t ena : 1; 818 uint64_t wrap : 1; 819 uint64_t trig_ctl : 2; 820 uint64_t time_grn : 3; 821 uint64_t full_thr : 2; 822 uint64_t ciu_trg : 1; 823 uint64_t ciu_thr : 1; 824 uint64_t mcd0_trg : 1; 825 uint64_t mcd0_thr : 1; 826 uint64_t mcd0_ena : 1; 827 uint64_t ignore_o : 1; 828 uint64_t clkalways : 1; 829 uint64_t reserved_16_63 : 48; 830#endif 831 } cn63xxp1; 832 struct cvmx_trax_ctl_s cn66xx; 833 struct cvmx_trax_ctl_s cn68xx; 834 struct cvmx_trax_ctl_s cn68xxp1; 835 struct cvmx_trax_ctl_s cnf71xx; 836}; 837typedef union cvmx_trax_ctl cvmx_trax_ctl_t; 838 839/** 840 * cvmx_tra#_cycles_since 841 * 842 * TRA_CYCLES_SINCE = Trace Buffer Cycles Since Last Write, Read/Write pointers 843 * 844 * Description: 845 * 846 * Notes: 847 * This CSR is obsolete. Use TRA_CYCLES_SINCE1 instead. 848 * 849 */ 850union cvmx_trax_cycles_since { 851 uint64_t u64; 852 struct cvmx_trax_cycles_since_s { 853#ifdef __BIG_ENDIAN_BITFIELD 854 uint64_t cycles : 48; /**< Cycles since the last entry was written */ 855 uint64_t rptr : 8; /**< Read pointer */ 856 uint64_t wptr : 8; /**< Write pointer */ 857#else 858 uint64_t wptr : 8; 859 uint64_t rptr : 8; 860 uint64_t cycles : 48; 861#endif 862 } s; 863 struct cvmx_trax_cycles_since_s cn31xx; 864 struct cvmx_trax_cycles_since_s cn38xx; 865 struct cvmx_trax_cycles_since_s cn38xxp2; 866 struct cvmx_trax_cycles_since_s cn52xx; 867 struct cvmx_trax_cycles_since_s cn52xxp1; 868 struct cvmx_trax_cycles_since_s cn56xx; 869 struct cvmx_trax_cycles_since_s cn56xxp1; 870 struct cvmx_trax_cycles_since_s cn58xx; 871 struct cvmx_trax_cycles_since_s cn58xxp1; 872 struct cvmx_trax_cycles_since_s cn61xx; 873 struct cvmx_trax_cycles_since_s cn63xx; 874 struct cvmx_trax_cycles_since_s cn63xxp1; 875 struct cvmx_trax_cycles_since_s cn66xx; 876 struct cvmx_trax_cycles_since_s cn68xx; 877 struct cvmx_trax_cycles_since_s cn68xxp1; 878 struct cvmx_trax_cycles_since_s cnf71xx; 879}; 880typedef union cvmx_trax_cycles_since cvmx_trax_cycles_since_t; 881 882/** 883 * cvmx_tra#_cycles_since1 884 * 885 * TRA_CYCLES_SINCE1 = Trace Buffer Cycles Since Last Write, Read/Write pointers 886 * 887 * Description: 888 */ 889union cvmx_trax_cycles_since1 { 890 uint64_t u64; 891 struct cvmx_trax_cycles_since1_s { 892#ifdef __BIG_ENDIAN_BITFIELD 893 uint64_t cycles : 40; /**< Cycles since the last entry was written */ 894 uint64_t reserved_22_23 : 2; 895 uint64_t rptr : 10; /**< Read pointer */ 896 uint64_t reserved_10_11 : 2; 897 uint64_t wptr : 10; /**< Write pointer */ 898#else 899 uint64_t wptr : 10; 900 uint64_t reserved_10_11 : 2; 901 uint64_t rptr : 10; 902 uint64_t reserved_22_23 : 2; 903 uint64_t cycles : 40; 904#endif 905 } s; 906 struct cvmx_trax_cycles_since1_s cn52xx; 907 struct cvmx_trax_cycles_since1_s cn52xxp1; 908 struct cvmx_trax_cycles_since1_s cn56xx; 909 struct cvmx_trax_cycles_since1_s cn56xxp1; 910 struct cvmx_trax_cycles_since1_s cn58xx; 911 struct cvmx_trax_cycles_since1_s cn58xxp1; 912 struct cvmx_trax_cycles_since1_s cn61xx; 913 struct cvmx_trax_cycles_since1_s cn63xx; 914 struct cvmx_trax_cycles_since1_s cn63xxp1; 915 struct cvmx_trax_cycles_since1_s cn66xx; 916 struct cvmx_trax_cycles_since1_s cn68xx; 917 struct cvmx_trax_cycles_since1_s cn68xxp1; 918 struct cvmx_trax_cycles_since1_s cnf71xx; 919}; 920typedef union cvmx_trax_cycles_since1 cvmx_trax_cycles_since1_t; 921 922/** 923 * cvmx_tra#_filt_adr_adr 924 * 925 * TRA_FILT_ADR_ADR = Trace Buffer Filter Address Address 926 * 927 * Description: 928 */ 929union cvmx_trax_filt_adr_adr { 930 uint64_t u64; 931 struct cvmx_trax_filt_adr_adr_s { 932#ifdef __BIG_ENDIAN_BITFIELD 933 uint64_t reserved_38_63 : 26; 934 uint64_t adr : 38; /**< Unmasked Address 935 The combination of TRA_FILT_ADR_ADR and 936 TRA_FILT_ADR_MSK is a masked address to 937 enable tracing of only those commands whose 938 masked address matches */ 939#else 940 uint64_t adr : 38; 941 uint64_t reserved_38_63 : 26; 942#endif 943 } s; 944 struct cvmx_trax_filt_adr_adr_cn31xx { 945#ifdef __BIG_ENDIAN_BITFIELD 946 uint64_t reserved_36_63 : 28; 947 uint64_t adr : 36; /**< Unmasked Address 948 The combination of TRA(0..0)_FILT_ADR_ADR and 949 TRA(0..0)_FILT_ADR_MSK is a masked address to 950 enable tracing of only those commands whose 951 masked address matches */ 952#else 953 uint64_t adr : 36; 954 uint64_t reserved_36_63 : 28; 955#endif 956 } cn31xx; 957 struct cvmx_trax_filt_adr_adr_cn31xx cn38xx; 958 struct cvmx_trax_filt_adr_adr_cn31xx cn38xxp2; 959 struct cvmx_trax_filt_adr_adr_cn31xx cn52xx; 960 struct cvmx_trax_filt_adr_adr_cn31xx cn52xxp1; 961 struct cvmx_trax_filt_adr_adr_cn31xx cn56xx; 962 struct cvmx_trax_filt_adr_adr_cn31xx cn56xxp1; 963 struct cvmx_trax_filt_adr_adr_cn31xx cn58xx; 964 struct cvmx_trax_filt_adr_adr_cn31xx cn58xxp1; 965 struct cvmx_trax_filt_adr_adr_s cn61xx; 966 struct cvmx_trax_filt_adr_adr_s cn63xx; 967 struct cvmx_trax_filt_adr_adr_s cn63xxp1; 968 struct cvmx_trax_filt_adr_adr_s cn66xx; 969 struct cvmx_trax_filt_adr_adr_s cn68xx; 970 struct cvmx_trax_filt_adr_adr_s cn68xxp1; 971 struct cvmx_trax_filt_adr_adr_s cnf71xx; 972}; 973typedef union cvmx_trax_filt_adr_adr cvmx_trax_filt_adr_adr_t; 974 975/** 976 * cvmx_tra#_filt_adr_msk 977 * 978 * TRA_FILT_ADR_MSK = Trace Buffer Filter Address Mask 979 * 980 * Description: 981 */ 982union cvmx_trax_filt_adr_msk { 983 uint64_t u64; 984 struct cvmx_trax_filt_adr_msk_s { 985#ifdef __BIG_ENDIAN_BITFIELD 986 uint64_t reserved_38_63 : 26; 987 uint64_t adr : 38; /**< Address Mask 988 The combination of TRA_FILT_ADR_ADR and 989 TRA_FILT_ADR_MSK is a masked address to 990 enable tracing of only those commands whose 991 masked address matches. When a mask bit is not 992 set, the corresponding address bits are assumed 993 to match. Also, note that IOBDMAs do not have 994 proper addresses, so when TRA_FILT_CMD[IOBDMA] 995 is set, TRA_FILT_ADR_MSK must be zero to 996 guarantee that any IOBDMAs enter the trace. */ 997#else 998 uint64_t adr : 38; 999 uint64_t reserved_38_63 : 26; 1000#endif 1001 } s; 1002 struct cvmx_trax_filt_adr_msk_cn31xx { 1003#ifdef __BIG_ENDIAN_BITFIELD 1004 uint64_t reserved_36_63 : 28; 1005 uint64_t adr : 36; /**< Address Mask 1006 The combination of TRA(0..0)_FILT_ADR_ADR and 1007 TRA(0..0)_FILT_ADR_MSK is a masked address to 1008 enable tracing of only those commands whose 1009 masked address matches. When a mask bit is not 1010 set, the corresponding address bits are assumed 1011 to match. Also, note that IOBDMAs do not have 1012 proper addresses, so when TRA(0..0)_FILT_CMD[IOBDMA] 1013 is set, TRA(0..0)_FILT_ADR_MSK must be zero to 1014 guarantee that any IOBDMAs enter the trace. */ 1015#else 1016 uint64_t adr : 36; 1017 uint64_t reserved_36_63 : 28; 1018#endif 1019 } cn31xx; 1020 struct cvmx_trax_filt_adr_msk_cn31xx cn38xx; 1021 struct cvmx_trax_filt_adr_msk_cn31xx cn38xxp2; 1022 struct cvmx_trax_filt_adr_msk_cn31xx cn52xx; 1023 struct cvmx_trax_filt_adr_msk_cn31xx cn52xxp1; 1024 struct cvmx_trax_filt_adr_msk_cn31xx cn56xx; 1025 struct cvmx_trax_filt_adr_msk_cn31xx cn56xxp1; 1026 struct cvmx_trax_filt_adr_msk_cn31xx cn58xx; 1027 struct cvmx_trax_filt_adr_msk_cn31xx cn58xxp1; 1028 struct cvmx_trax_filt_adr_msk_s cn61xx; 1029 struct cvmx_trax_filt_adr_msk_s cn63xx; 1030 struct cvmx_trax_filt_adr_msk_s cn63xxp1; 1031 struct cvmx_trax_filt_adr_msk_s cn66xx; 1032 struct cvmx_trax_filt_adr_msk_s cn68xx; 1033 struct cvmx_trax_filt_adr_msk_s cn68xxp1; 1034 struct cvmx_trax_filt_adr_msk_s cnf71xx; 1035}; 1036typedef union cvmx_trax_filt_adr_msk cvmx_trax_filt_adr_msk_t; 1037 1038/** 1039 * cvmx_tra#_filt_cmd 1040 * 1041 * TRA_FILT_CMD = Trace Buffer Filter Command Mask 1042 * 1043 * Description: 1044 * 1045 * Notes: 1046 * Note that the trace buffer does not do proper IOBDMA address compares. Thus, if IOBDMA is set, then 1047 * the address compare must be disabled (i.e. TRA_FILT_ADR_MSK set to zero) to guarantee that IOBDMAs 1048 * enter the trace. 1049 */ 1050union cvmx_trax_filt_cmd { 1051 uint64_t u64; 1052 struct cvmx_trax_filt_cmd_s { 1053#ifdef __BIG_ENDIAN_BITFIELD 1054 uint64_t saa64 : 1; /**< Enable SAA64 tracing 1055 0=disable, 1=enable */ 1056 uint64_t saa32 : 1; /**< Enable SAA32 tracing 1057 0=disable, 1=enable */ 1058 uint64_t reserved_60_61 : 2; 1059 uint64_t faa64 : 1; /**< Enable FAA64 tracing 1060 0=disable, 1=enable */ 1061 uint64_t faa32 : 1; /**< Enable FAA32 tracing 1062 0=disable, 1=enable */ 1063 uint64_t reserved_56_57 : 2; 1064 uint64_t decr64 : 1; /**< Enable DECR64 tracing 1065 0=disable, 1=enable */ 1066 uint64_t decr32 : 1; /**< Enable DECR32 tracing 1067 0=disable, 1=enable */ 1068 uint64_t decr16 : 1; /**< Enable DECR16 tracing 1069 0=disable, 1=enable */ 1070 uint64_t decr8 : 1; /**< Enable DECR8 tracing 1071 0=disable, 1=enable */ 1072 uint64_t incr64 : 1; /**< Enable INCR64 tracing 1073 0=disable, 1=enable */ 1074 uint64_t incr32 : 1; /**< Enable INCR32 tracing 1075 0=disable, 1=enable */ 1076 uint64_t incr16 : 1; /**< Enable INCR16 tracing 1077 0=disable, 1=enable */ 1078 uint64_t incr8 : 1; /**< Enable INCR8 tracing 1079 0=disable, 1=enable */ 1080 uint64_t clr64 : 1; /**< Enable CLR64 tracing 1081 0=disable, 1=enable */ 1082 uint64_t clr32 : 1; /**< Enable CLR32 tracing 1083 0=disable, 1=enable */ 1084 uint64_t clr16 : 1; /**< Enable CLR16 tracing 1085 0=disable, 1=enable */ 1086 uint64_t clr8 : 1; /**< Enable CLR8 tracing 1087 0=disable, 1=enable */ 1088 uint64_t set64 : 1; /**< Enable SET64 tracing 1089 0=disable, 1=enable */ 1090 uint64_t set32 : 1; /**< Enable SET32 tracing 1091 0=disable, 1=enable */ 1092 uint64_t set16 : 1; /**< Enable SET16 tracing 1093 0=disable, 1=enable */ 1094 uint64_t set8 : 1; /**< Enable SET8 tracing 1095 0=disable, 1=enable */ 1096 uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 1097 0=disable, 1=enable */ 1098 uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 1099 0=disable, 1=enable */ 1100 uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 1101 0=disable, 1=enable */ 1102 uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 1103 0=disable, 1=enable */ 1104 uint64_t reserved_32_35 : 4; 1105 uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 1106 0=disable, 1=enable */ 1107 uint64_t wbl2 : 1; /**< Enable WBL2 tracing 1108 0=disable, 1=enable */ 1109 uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 1110 0=disable, 1=enable */ 1111 uint64_t invl2 : 1; /**< Enable INVL2 tracing 1112 0=disable, 1=enable */ 1113 uint64_t reserved_27_27 : 1; 1114 uint64_t stgl2i : 1; /**< Enable STGL2I tracing 1115 0=disable, 1=enable */ 1116 uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 1117 0=disable, 1=enable */ 1118 uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 1119 0=disable, 1=enable */ 1120 uint64_t fas64 : 1; /**< Enable FAS64 tracing 1121 0=disable, 1=enable */ 1122 uint64_t fas32 : 1; /**< Enable FAS32 tracing 1123 0=disable, 1=enable */ 1124 uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 1125 0=disable, 1=enable */ 1126 uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 1127 0=disable, 1=enable */ 1128 uint64_t reserved_16_19 : 4; 1129 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 1130 0=disable, 1=enable */ 1131 uint64_t iobst : 1; /**< Enable IOBST tracing 1132 0=disable, 1=enable */ 1133 uint64_t reserved_0_13 : 14; 1134#else 1135 uint64_t reserved_0_13 : 14; 1136 uint64_t iobst : 1; 1137 uint64_t iobdma : 1; 1138 uint64_t reserved_16_19 : 4; 1139 uint64_t stfil1 : 1; 1140 uint64_t sttil1 : 1; 1141 uint64_t fas32 : 1; 1142 uint64_t fas64 : 1; 1143 uint64_t wbil2i : 1; 1144 uint64_t ltgl2i : 1; 1145 uint64_t stgl2i : 1; 1146 uint64_t reserved_27_27 : 1; 1147 uint64_t invl2 : 1; 1148 uint64_t wbil2 : 1; 1149 uint64_t wbl2 : 1; 1150 uint64_t lckl2 : 1; 1151 uint64_t reserved_32_35 : 4; 1152 uint64_t iobst8 : 1; 1153 uint64_t iobst16 : 1; 1154 uint64_t iobst32 : 1; 1155 uint64_t iobst64 : 1; 1156 uint64_t set8 : 1; 1157 uint64_t set16 : 1; 1158 uint64_t set32 : 1; 1159 uint64_t set64 : 1; 1160 uint64_t clr8 : 1; 1161 uint64_t clr16 : 1; 1162 uint64_t clr32 : 1; 1163 uint64_t clr64 : 1; 1164 uint64_t incr8 : 1; 1165 uint64_t incr16 : 1; 1166 uint64_t incr32 : 1; 1167 uint64_t incr64 : 1; 1168 uint64_t decr8 : 1; 1169 uint64_t decr16 : 1; 1170 uint64_t decr32 : 1; 1171 uint64_t decr64 : 1; 1172 uint64_t reserved_56_57 : 2; 1173 uint64_t faa32 : 1; 1174 uint64_t faa64 : 1; 1175 uint64_t reserved_60_61 : 2; 1176 uint64_t saa32 : 1; 1177 uint64_t saa64 : 1; 1178#endif 1179 } s; 1180 struct cvmx_trax_filt_cmd_cn31xx { 1181#ifdef __BIG_ENDIAN_BITFIELD 1182 uint64_t reserved_16_63 : 48; 1183 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 1184 0=disable, 1=enable */ 1185 uint64_t iobst : 1; /**< Enable IOBST tracing 1186 0=disable, 1=enable */ 1187 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 1188 0=disable, 1=enable */ 1189 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 1190 0=disable, 1=enable */ 1191 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 1192 0=disable, 1=enable */ 1193 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 1194 0=disable, 1=enable */ 1195 uint64_t stt : 1; /**< Enable STT tracing 1196 0=disable, 1=enable */ 1197 uint64_t stp : 1; /**< Enable STP tracing 1198 0=disable, 1=enable */ 1199 uint64_t stc : 1; /**< Enable STC tracing 1200 0=disable, 1=enable */ 1201 uint64_t stf : 1; /**< Enable STF tracing 1202 0=disable, 1=enable */ 1203 uint64_t ldt : 1; /**< Enable LDT tracing 1204 0=disable, 1=enable */ 1205 uint64_t ldi : 1; /**< Enable LDI tracing 1206 0=disable, 1=enable */ 1207 uint64_t ldd : 1; /**< Enable LDD tracing 1208 0=disable, 1=enable */ 1209 uint64_t psl1 : 1; /**< Enable PSL1 tracing 1210 0=disable, 1=enable */ 1211 uint64_t pl2 : 1; /**< Enable PL2 tracing 1212 0=disable, 1=enable */ 1213 uint64_t dwb : 1; /**< Enable DWB tracing 1214 0=disable, 1=enable */ 1215#else 1216 uint64_t dwb : 1; 1217 uint64_t pl2 : 1; 1218 uint64_t psl1 : 1; 1219 uint64_t ldd : 1; 1220 uint64_t ldi : 1; 1221 uint64_t ldt : 1; 1222 uint64_t stf : 1; 1223 uint64_t stc : 1; 1224 uint64_t stp : 1; 1225 uint64_t stt : 1; 1226 uint64_t iobld8 : 1; 1227 uint64_t iobld16 : 1; 1228 uint64_t iobld32 : 1; 1229 uint64_t iobld64 : 1; 1230 uint64_t iobst : 1; 1231 uint64_t iobdma : 1; 1232 uint64_t reserved_16_63 : 48; 1233#endif 1234 } cn31xx; 1235 struct cvmx_trax_filt_cmd_cn31xx cn38xx; 1236 struct cvmx_trax_filt_cmd_cn31xx cn38xxp2; 1237 struct cvmx_trax_filt_cmd_cn52xx { 1238#ifdef __BIG_ENDIAN_BITFIELD 1239 uint64_t reserved_17_63 : 47; 1240 uint64_t saa : 1; /**< Enable SAA tracing 1241 0=disable, 1=enable */ 1242 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 1243 0=disable, 1=enable */ 1244 uint64_t iobst : 1; /**< Enable IOBST tracing 1245 0=disable, 1=enable */ 1246 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 1247 0=disable, 1=enable */ 1248 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 1249 0=disable, 1=enable */ 1250 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 1251 0=disable, 1=enable */ 1252 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 1253 0=disable, 1=enable */ 1254 uint64_t stt : 1; /**< Enable STT tracing 1255 0=disable, 1=enable */ 1256 uint64_t stp : 1; /**< Enable STP tracing 1257 0=disable, 1=enable */ 1258 uint64_t stc : 1; /**< Enable STC tracing 1259 0=disable, 1=enable */ 1260 uint64_t stf : 1; /**< Enable STF tracing 1261 0=disable, 1=enable */ 1262 uint64_t ldt : 1; /**< Enable LDT tracing 1263 0=disable, 1=enable */ 1264 uint64_t ldi : 1; /**< Enable LDI tracing 1265 0=disable, 1=enable */ 1266 uint64_t ldd : 1; /**< Enable LDD tracing 1267 0=disable, 1=enable */ 1268 uint64_t psl1 : 1; /**< Enable PSL1 tracing 1269 0=disable, 1=enable */ 1270 uint64_t pl2 : 1; /**< Enable PL2 tracing 1271 0=disable, 1=enable */ 1272 uint64_t dwb : 1; /**< Enable DWB tracing 1273 0=disable, 1=enable */ 1274#else 1275 uint64_t dwb : 1; 1276 uint64_t pl2 : 1; 1277 uint64_t psl1 : 1; 1278 uint64_t ldd : 1; 1279 uint64_t ldi : 1; 1280 uint64_t ldt : 1; 1281 uint64_t stf : 1; 1282 uint64_t stc : 1; 1283 uint64_t stp : 1; 1284 uint64_t stt : 1; 1285 uint64_t iobld8 : 1; 1286 uint64_t iobld16 : 1; 1287 uint64_t iobld32 : 1; 1288 uint64_t iobld64 : 1; 1289 uint64_t iobst : 1; 1290 uint64_t iobdma : 1; 1291 uint64_t saa : 1; 1292 uint64_t reserved_17_63 : 47; 1293#endif 1294 } cn52xx; 1295 struct cvmx_trax_filt_cmd_cn52xx cn52xxp1; 1296 struct cvmx_trax_filt_cmd_cn52xx cn56xx; 1297 struct cvmx_trax_filt_cmd_cn52xx cn56xxp1; 1298 struct cvmx_trax_filt_cmd_cn52xx cn58xx; 1299 struct cvmx_trax_filt_cmd_cn52xx cn58xxp1; 1300 struct cvmx_trax_filt_cmd_cn61xx { 1301#ifdef __BIG_ENDIAN_BITFIELD 1302 uint64_t saa64 : 1; /**< Enable SAA64 tracing 1303 0=disable, 1=enable */ 1304 uint64_t saa32 : 1; /**< Enable SAA32 tracing 1305 0=disable, 1=enable */ 1306 uint64_t reserved_60_61 : 2; 1307 uint64_t faa64 : 1; /**< Enable FAA64 tracing 1308 0=disable, 1=enable */ 1309 uint64_t faa32 : 1; /**< Enable FAA32 tracing 1310 0=disable, 1=enable */ 1311 uint64_t reserved_56_57 : 2; 1312 uint64_t decr64 : 1; /**< Enable DECR64 tracing 1313 0=disable, 1=enable */ 1314 uint64_t decr32 : 1; /**< Enable DECR32 tracing 1315 0=disable, 1=enable */ 1316 uint64_t decr16 : 1; /**< Enable DECR16 tracing 1317 0=disable, 1=enable */ 1318 uint64_t decr8 : 1; /**< Enable DECR8 tracing 1319 0=disable, 1=enable */ 1320 uint64_t incr64 : 1; /**< Enable INCR64 tracing 1321 0=disable, 1=enable */ 1322 uint64_t incr32 : 1; /**< Enable INCR32 tracing 1323 0=disable, 1=enable */ 1324 uint64_t incr16 : 1; /**< Enable INCR16 tracing 1325 0=disable, 1=enable */ 1326 uint64_t incr8 : 1; /**< Enable INCR8 tracing 1327 0=disable, 1=enable */ 1328 uint64_t clr64 : 1; /**< Enable CLR64 tracing 1329 0=disable, 1=enable */ 1330 uint64_t clr32 : 1; /**< Enable CLR32 tracing 1331 0=disable, 1=enable */ 1332 uint64_t clr16 : 1; /**< Enable CLR16 tracing 1333 0=disable, 1=enable */ 1334 uint64_t clr8 : 1; /**< Enable CLR8 tracing 1335 0=disable, 1=enable */ 1336 uint64_t set64 : 1; /**< Enable SET64 tracing 1337 0=disable, 1=enable */ 1338 uint64_t set32 : 1; /**< Enable SET32 tracing 1339 0=disable, 1=enable */ 1340 uint64_t set16 : 1; /**< Enable SET16 tracing 1341 0=disable, 1=enable */ 1342 uint64_t set8 : 1; /**< Enable SET8 tracing 1343 0=disable, 1=enable */ 1344 uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 1345 0=disable, 1=enable */ 1346 uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 1347 0=disable, 1=enable */ 1348 uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 1349 0=disable, 1=enable */ 1350 uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 1351 0=disable, 1=enable */ 1352 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 1353 0=disable, 1=enable */ 1354 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 1355 0=disable, 1=enable */ 1356 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 1357 0=disable, 1=enable */ 1358 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 1359 0=disable, 1=enable */ 1360 uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 1361 0=disable, 1=enable */ 1362 uint64_t wbl2 : 1; /**< Enable WBL2 tracing 1363 0=disable, 1=enable */ 1364 uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 1365 0=disable, 1=enable */ 1366 uint64_t invl2 : 1; /**< Enable INVL2 tracing 1367 0=disable, 1=enable */ 1368 uint64_t reserved_27_27 : 1; 1369 uint64_t stgl2i : 1; /**< Enable STGL2I tracing 1370 0=disable, 1=enable */ 1371 uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 1372 0=disable, 1=enable */ 1373 uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 1374 0=disable, 1=enable */ 1375 uint64_t fas64 : 1; /**< Enable FAS64 tracing 1376 0=disable, 1=enable */ 1377 uint64_t fas32 : 1; /**< Enable FAS32 tracing 1378 0=disable, 1=enable */ 1379 uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 1380 0=disable, 1=enable */ 1381 uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 1382 0=disable, 1=enable */ 1383 uint64_t stc : 1; /**< Enable STC tracing 1384 0=disable, 1=enable */ 1385 uint64_t stp : 1; /**< Enable STP tracing 1386 0=disable, 1=enable */ 1387 uint64_t stt : 1; /**< Enable STT tracing 1388 0=disable, 1=enable */ 1389 uint64_t stf : 1; /**< Enable STF tracing 1390 0=disable, 1=enable */ 1391 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 1392 0=disable, 1=enable */ 1393 uint64_t reserved_10_14 : 5; 1394 uint64_t psl1 : 1; /**< Enable PSL1 tracing 1395 0=disable, 1=enable */ 1396 uint64_t ldd : 1; /**< Enable LDD tracing 1397 0=disable, 1=enable */ 1398 uint64_t reserved_6_7 : 2; 1399 uint64_t dwb : 1; /**< Enable DWB tracing 1400 0=disable, 1=enable */ 1401 uint64_t rpl2 : 1; /**< Enable RPL2 tracing 1402 0=disable, 1=enable */ 1403 uint64_t pl2 : 1; /**< Enable PL2 tracing 1404 0=disable, 1=enable */ 1405 uint64_t ldi : 1; /**< Enable LDI tracing 1406 0=disable, 1=enable */ 1407 uint64_t ldt : 1; /**< Enable LDT tracing 1408 0=disable, 1=enable */ 1409 uint64_t nop : 1; /**< Enable NOP tracing 1410 0=disable, 1=enable */ 1411#else 1412 uint64_t nop : 1; 1413 uint64_t ldt : 1; 1414 uint64_t ldi : 1; 1415 uint64_t pl2 : 1; 1416 uint64_t rpl2 : 1; 1417 uint64_t dwb : 1; 1418 uint64_t reserved_6_7 : 2; 1419 uint64_t ldd : 1; 1420 uint64_t psl1 : 1; 1421 uint64_t reserved_10_14 : 5; 1422 uint64_t iobdma : 1; 1423 uint64_t stf : 1; 1424 uint64_t stt : 1; 1425 uint64_t stp : 1; 1426 uint64_t stc : 1; 1427 uint64_t stfil1 : 1; 1428 uint64_t sttil1 : 1; 1429 uint64_t fas32 : 1; 1430 uint64_t fas64 : 1; 1431 uint64_t wbil2i : 1; 1432 uint64_t ltgl2i : 1; 1433 uint64_t stgl2i : 1; 1434 uint64_t reserved_27_27 : 1; 1435 uint64_t invl2 : 1; 1436 uint64_t wbil2 : 1; 1437 uint64_t wbl2 : 1; 1438 uint64_t lckl2 : 1; 1439 uint64_t iobld8 : 1; 1440 uint64_t iobld16 : 1; 1441 uint64_t iobld32 : 1; 1442 uint64_t iobld64 : 1; 1443 uint64_t iobst8 : 1; 1444 uint64_t iobst16 : 1; 1445 uint64_t iobst32 : 1; 1446 uint64_t iobst64 : 1; 1447 uint64_t set8 : 1; 1448 uint64_t set16 : 1; 1449 uint64_t set32 : 1; 1450 uint64_t set64 : 1; 1451 uint64_t clr8 : 1; 1452 uint64_t clr16 : 1; 1453 uint64_t clr32 : 1; 1454 uint64_t clr64 : 1; 1455 uint64_t incr8 : 1; 1456 uint64_t incr16 : 1; 1457 uint64_t incr32 : 1; 1458 uint64_t incr64 : 1; 1459 uint64_t decr8 : 1; 1460 uint64_t decr16 : 1; 1461 uint64_t decr32 : 1; 1462 uint64_t decr64 : 1; 1463 uint64_t reserved_56_57 : 2; 1464 uint64_t faa32 : 1; 1465 uint64_t faa64 : 1; 1466 uint64_t reserved_60_61 : 2; 1467 uint64_t saa32 : 1; 1468 uint64_t saa64 : 1; 1469#endif 1470 } cn61xx; 1471 struct cvmx_trax_filt_cmd_cn61xx cn63xx; 1472 struct cvmx_trax_filt_cmd_cn61xx cn63xxp1; 1473 struct cvmx_trax_filt_cmd_cn61xx cn66xx; 1474 struct cvmx_trax_filt_cmd_cn61xx cn68xx; 1475 struct cvmx_trax_filt_cmd_cn61xx cn68xxp1; 1476 struct cvmx_trax_filt_cmd_cn61xx cnf71xx; 1477}; 1478typedef union cvmx_trax_filt_cmd cvmx_trax_filt_cmd_t; 1479 1480/** 1481 * cvmx_tra#_filt_did 1482 * 1483 * TRA_FILT_DID = Trace Buffer Filter DestinationId Mask 1484 * 1485 * Description: 1486 */ 1487union cvmx_trax_filt_did { 1488 uint64_t u64; 1489 struct cvmx_trax_filt_did_s { 1490#ifdef __BIG_ENDIAN_BITFIELD 1491 uint64_t reserved_13_63 : 51; 1492 uint64_t pow : 1; /**< Enable tracing of requests to POW 1493 (get work, add work, status/memory/index 1494 loads, NULLRd loads, CSR's) */ 1495 uint64_t reserved_9_11 : 3; 1496 uint64_t rng : 1; /**< Enable tracing of requests to RNG 1497 (loads/IOBDMA's are legal) */ 1498 uint64_t zip : 1; /**< Enable tracing of requests to ZIP 1499 (doorbell stores are legal) */ 1500 uint64_t dfa : 1; /**< Enable tracing of requests to DFA 1501 (CSR's and operations are legal) */ 1502 uint64_t fpa : 1; /**< Enable tracing of requests to FPA 1503 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 1504 uint64_t key : 1; /**< Enable tracing of requests to KEY memory 1505 (loads/IOBDMA's/stores are legal) */ 1506 uint64_t reserved_3_3 : 1; 1507 uint64_t illegal3 : 2; /**< Illegal destinations */ 1508 uint64_t mio : 1; /**< Enable tracing of MIO accesses 1509 (CIU and GPIO CSR's, boot bus accesses) */ 1510#else 1511 uint64_t mio : 1; 1512 uint64_t illegal3 : 2; 1513 uint64_t reserved_3_3 : 1; 1514 uint64_t key : 1; 1515 uint64_t fpa : 1; 1516 uint64_t dfa : 1; 1517 uint64_t zip : 1; 1518 uint64_t rng : 1; 1519 uint64_t reserved_9_11 : 3; 1520 uint64_t pow : 1; 1521 uint64_t reserved_13_63 : 51; 1522#endif 1523 } s; 1524 struct cvmx_trax_filt_did_cn31xx { 1525#ifdef __BIG_ENDIAN_BITFIELD 1526 uint64_t reserved_32_63 : 32; 1527 uint64_t illegal : 19; /**< Illegal destinations */ 1528 uint64_t pow : 1; /**< Enable tracing of requests to POW 1529 (get work, add work, status/memory/index 1530 loads, NULLRd loads, CSR's) */ 1531 uint64_t illegal2 : 3; /**< Illegal destinations */ 1532 uint64_t rng : 1; /**< Enable tracing of requests to RNG 1533 (loads/IOBDMA's are legal) */ 1534 uint64_t zip : 1; /**< Enable tracing of requests to ZIP 1535 (doorbell stores are legal) */ 1536 uint64_t dfa : 1; /**< Enable tracing of requests to DFA 1537 (CSR's and operations are legal) */ 1538 uint64_t fpa : 1; /**< Enable tracing of requests to FPA 1539 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 1540 uint64_t key : 1; /**< Enable tracing of requests to KEY memory 1541 (loads/IOBDMA's/stores are legal) */ 1542 uint64_t pci : 1; /**< Enable tracing of requests to PCI and RSL-type 1543 CSR's (RSL CSR's, PCI bus operations, PCI 1544 CSR's) */ 1545 uint64_t illegal3 : 2; /**< Illegal destinations */ 1546 uint64_t mio : 1; /**< Enable tracing of CIU and GPIO CSR's */ 1547#else 1548 uint64_t mio : 1; 1549 uint64_t illegal3 : 2; 1550 uint64_t pci : 1; 1551 uint64_t key : 1; 1552 uint64_t fpa : 1; 1553 uint64_t dfa : 1; 1554 uint64_t zip : 1; 1555 uint64_t rng : 1; 1556 uint64_t illegal2 : 3; 1557 uint64_t pow : 1; 1558 uint64_t illegal : 19; 1559 uint64_t reserved_32_63 : 32; 1560#endif 1561 } cn31xx; 1562 struct cvmx_trax_filt_did_cn31xx cn38xx; 1563 struct cvmx_trax_filt_did_cn31xx cn38xxp2; 1564 struct cvmx_trax_filt_did_cn31xx cn52xx; 1565 struct cvmx_trax_filt_did_cn31xx cn52xxp1; 1566 struct cvmx_trax_filt_did_cn31xx cn56xx; 1567 struct cvmx_trax_filt_did_cn31xx cn56xxp1; 1568 struct cvmx_trax_filt_did_cn31xx cn58xx; 1569 struct cvmx_trax_filt_did_cn31xx cn58xxp1; 1570 struct cvmx_trax_filt_did_cn61xx { 1571#ifdef __BIG_ENDIAN_BITFIELD 1572 uint64_t reserved_32_63 : 32; 1573 uint64_t illegal5 : 1; /**< Illegal destinations */ 1574 uint64_t fau : 1; /**< Enable tracing of FAU accesses */ 1575 uint64_t illegal4 : 2; /**< Illegal destinations */ 1576 uint64_t dpi : 1; /**< Enable tracing of DPI accesses 1577 (DPI NCB CSRs) */ 1578 uint64_t illegal : 12; /**< Illegal destinations */ 1579 uint64_t rad : 1; /**< Enable tracing of RAD accesses 1580 (doorbells) */ 1581 uint64_t usb0 : 1; /**< Enable tracing of USB0 accesses 1582 (UAHC0 EHCI and OHCI NCB CSRs) */ 1583 uint64_t pow : 1; /**< Enable tracing of requests to POW 1584 (get work, add work, status/memory/index 1585 loads, NULLRd loads, CSR's) */ 1586 uint64_t illegal2 : 1; /**< Illegal destination */ 1587 uint64_t pko : 1; /**< Enable tracing of PKO accesses 1588 (doorbells) */ 1589 uint64_t ipd : 1; /**< Enable tracing of IPD CSR accesses 1590 (IPD CSRs) */ 1591 uint64_t rng : 1; /**< Enable tracing of requests to RNG 1592 (loads/IOBDMA's are legal) */ 1593 uint64_t zip : 1; /**< Enable tracing of requests to ZIP 1594 (doorbell stores are legal) */ 1595 uint64_t dfa : 1; /**< Enable tracing of requests to DFA 1596 (CSR's and operations are legal) */ 1597 uint64_t fpa : 1; /**< Enable tracing of requests to FPA 1598 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 1599 uint64_t key : 1; /**< Enable tracing of requests to KEY memory 1600 (loads/IOBDMA's/stores are legal) */ 1601 uint64_t sli : 1; /**< Enable tracing of requests to SLI and RSL-type 1602 CSR's (RSL CSR's, PCI/sRIO bus operations, SLI 1603 CSR's) */ 1604 uint64_t illegal3 : 2; /**< Illegal destinations */ 1605 uint64_t mio : 1; /**< Enable tracing of MIO accesses 1606 (CIU and GPIO CSR's, boot bus accesses) */ 1607#else 1608 uint64_t mio : 1; 1609 uint64_t illegal3 : 2; 1610 uint64_t sli : 1; 1611 uint64_t key : 1; 1612 uint64_t fpa : 1; 1613 uint64_t dfa : 1; 1614 uint64_t zip : 1; 1615 uint64_t rng : 1; 1616 uint64_t ipd : 1; 1617 uint64_t pko : 1; 1618 uint64_t illegal2 : 1; 1619 uint64_t pow : 1; 1620 uint64_t usb0 : 1; 1621 uint64_t rad : 1; 1622 uint64_t illegal : 12; 1623 uint64_t dpi : 1; 1624 uint64_t illegal4 : 2; 1625 uint64_t fau : 1; 1626 uint64_t illegal5 : 1; 1627 uint64_t reserved_32_63 : 32; 1628#endif 1629 } cn61xx; 1630 struct cvmx_trax_filt_did_cn61xx cn63xx; 1631 struct cvmx_trax_filt_did_cn61xx cn63xxp1; 1632 struct cvmx_trax_filt_did_cn61xx cn66xx; 1633 struct cvmx_trax_filt_did_cn61xx cn68xx; 1634 struct cvmx_trax_filt_did_cn61xx cn68xxp1; 1635 struct cvmx_trax_filt_did_cn61xx cnf71xx; 1636}; 1637typedef union cvmx_trax_filt_did cvmx_trax_filt_did_t; 1638 1639/** 1640 * cvmx_tra#_filt_sid 1641 * 1642 * TRA_FILT_SID = Trace Buffer Filter SourceId Mask 1643 * 1644 * Description: 1645 */ 1646union cvmx_trax_filt_sid { 1647 uint64_t u64; 1648 struct cvmx_trax_filt_sid_s { 1649#ifdef __BIG_ENDIAN_BITFIELD 1650 uint64_t reserved_20_63 : 44; 1651 uint64_t dwb : 1; /**< Enable tracing of requests from the IOB DWB engine */ 1652 uint64_t iobreq : 1; /**< Enable tracing of requests from FPA,TIM,DFA, 1653 PCI,ZIP,POW, and PKO (writes) */ 1654 uint64_t pko : 1; /**< Enable tracing of read requests from PKO */ 1655 uint64_t pki : 1; /**< Enable tracing of write requests from PIP/IPD */ 1656 uint64_t pp : 16; /**< Enable tracing from PP[N] with matching SourceID 1657 0=disable, 1=enable per bit N where 0<=N<=3 */ 1658#else 1659 uint64_t pp : 16; 1660 uint64_t pki : 1; 1661 uint64_t pko : 1; 1662 uint64_t iobreq : 1; 1663 uint64_t dwb : 1; 1664 uint64_t reserved_20_63 : 44; 1665#endif 1666 } s; 1667 struct cvmx_trax_filt_sid_s cn31xx; 1668 struct cvmx_trax_filt_sid_s cn38xx; 1669 struct cvmx_trax_filt_sid_s cn38xxp2; 1670 struct cvmx_trax_filt_sid_s cn52xx; 1671 struct cvmx_trax_filt_sid_s cn52xxp1; 1672 struct cvmx_trax_filt_sid_s cn56xx; 1673 struct cvmx_trax_filt_sid_s cn56xxp1; 1674 struct cvmx_trax_filt_sid_s cn58xx; 1675 struct cvmx_trax_filt_sid_s cn58xxp1; 1676 struct cvmx_trax_filt_sid_cn61xx { 1677#ifdef __BIG_ENDIAN_BITFIELD 1678 uint64_t reserved_20_63 : 44; 1679 uint64_t dwb : 1; /**< Enable tracing of requests from the IOB DWB engine */ 1680 uint64_t iobreq : 1; /**< Enable tracing of requests from FPA,TIM,DFA, 1681 PCI,ZIP,POW, and PKO (writes) */ 1682 uint64_t pko : 1; /**< Enable tracing of read requests from PKO */ 1683 uint64_t pki : 1; /**< Enable tracing of write requests from PIP/IPD */ 1684 uint64_t reserved_4_15 : 12; 1685 uint64_t pp : 4; /**< Enable tracing from PP[N] with matching SourceID 1686 0=disable, 1=enable per bit N where 0<=N<=3 */ 1687#else 1688 uint64_t pp : 4; 1689 uint64_t reserved_4_15 : 12; 1690 uint64_t pki : 1; 1691 uint64_t pko : 1; 1692 uint64_t iobreq : 1; 1693 uint64_t dwb : 1; 1694 uint64_t reserved_20_63 : 44; 1695#endif 1696 } cn61xx; 1697 struct cvmx_trax_filt_sid_cn63xx { 1698#ifdef __BIG_ENDIAN_BITFIELD 1699 uint64_t reserved_20_63 : 44; 1700 uint64_t dwb : 1; /**< Enable tracing of requests from the IOB DWB engine */ 1701 uint64_t iobreq : 1; /**< Enable tracing of requests from FPA,TIM,DFA, 1702 PCI,ZIP,POW, and PKO (writes) */ 1703 uint64_t pko : 1; /**< Enable tracing of read requests from PKO */ 1704 uint64_t pki : 1; /**< Enable tracing of write requests from PIP/IPD */ 1705 uint64_t reserved_8_15 : 8; 1706 uint64_t pp : 8; /**< Enable tracing from PP[N] with matching SourceID 1707 0=disable, 1=enableper bit N where 0<=N<=15 */ 1708#else 1709 uint64_t pp : 8; 1710 uint64_t reserved_8_15 : 8; 1711 uint64_t pki : 1; 1712 uint64_t pko : 1; 1713 uint64_t iobreq : 1; 1714 uint64_t dwb : 1; 1715 uint64_t reserved_20_63 : 44; 1716#endif 1717 } cn63xx; 1718 struct cvmx_trax_filt_sid_cn63xxp1 { 1719#ifdef __BIG_ENDIAN_BITFIELD 1720 uint64_t reserved_20_63 : 44; 1721 uint64_t dwb : 1; /**< Enable tracing of requests from the IOB DWB engine */ 1722 uint64_t iobreq : 1; /**< Enable tracing of requests from FPA,TIM,DFA, 1723 PCI,ZIP,POW, and PKO (writes) */ 1724 uint64_t pko : 1; /**< Enable tracing of read requests from PKO */ 1725 uint64_t pki : 1; /**< Enable tracing of write requests from PIP/IPD */ 1726 uint64_t reserved_6_15 : 10; 1727 uint64_t pp : 6; /**< Enable tracing from PP[N] with matching SourceID 1728 0=disable, 1=enable per bit N where 0<=N<=5 */ 1729#else 1730 uint64_t pp : 6; 1731 uint64_t reserved_6_15 : 10; 1732 uint64_t pki : 1; 1733 uint64_t pko : 1; 1734 uint64_t iobreq : 1; 1735 uint64_t dwb : 1; 1736 uint64_t reserved_20_63 : 44; 1737#endif 1738 } cn63xxp1; 1739 struct cvmx_trax_filt_sid_cn66xx { 1740#ifdef __BIG_ENDIAN_BITFIELD 1741 uint64_t reserved_20_63 : 44; 1742 uint64_t dwb : 1; /**< Enable tracing of requests from the IOB DWB engine */ 1743 uint64_t iobreq : 1; /**< Enable tracing of requests from FPA,TIM,DFA, 1744 PCI,ZIP,POW, and PKO (writes) */ 1745 uint64_t pko : 1; /**< Enable tracing of read requests from PKO */ 1746 uint64_t pki : 1; /**< Enable tracing of write requests from PIP/IPD */ 1747 uint64_t reserved_10_15 : 6; 1748 uint64_t pp : 10; /**< Enable tracing from PP[N] with matching SourceID 1749 0=disable, 1=enableper bit N where 0<=N<=15 */ 1750#else 1751 uint64_t pp : 10; 1752 uint64_t reserved_10_15 : 6; 1753 uint64_t pki : 1; 1754 uint64_t pko : 1; 1755 uint64_t iobreq : 1; 1756 uint64_t dwb : 1; 1757 uint64_t reserved_20_63 : 44; 1758#endif 1759 } cn66xx; 1760 struct cvmx_trax_filt_sid_cn63xx cn68xx; 1761 struct cvmx_trax_filt_sid_cn63xx cn68xxp1; 1762 struct cvmx_trax_filt_sid_cn61xx cnf71xx; 1763}; 1764typedef union cvmx_trax_filt_sid cvmx_trax_filt_sid_t; 1765 1766/** 1767 * cvmx_tra#_int_status 1768 * 1769 * TRA_INT_STATUS = Trace Buffer Interrupt Status 1770 * 1771 * Description: 1772 * 1773 * Notes: 1774 * During a CSR write to this register, the write data is used as a mask to clear the selected status 1775 * bits (status'[3:0] = status[3:0] & ~write_data[3:0]). 1776 */ 1777union cvmx_trax_int_status { 1778 uint64_t u64; 1779 struct cvmx_trax_int_status_s { 1780#ifdef __BIG_ENDIAN_BITFIELD 1781 uint64_t reserved_4_63 : 60; 1782 uint64_t mcd0_thr : 1; /**< MCD0 full threshold interrupt status 1783 0=trace buffer did not generate MCD0 wire pulse 1784 1=trace buffer did generate MCD0 wire pulse 1785 and prevents additional MCD0_THR MCD0 wire pulses */ 1786 uint64_t mcd0_trg : 1; /**< MCD0 end trigger interrupt status 1787 0=trace buffer did not generate interrupt 1788 1=trace buffer did generate interrupt 1789 and prevents additional MCD0_TRG MCD0 wire pulses */ 1790 uint64_t ciu_thr : 1; /**< CIU full threshold interrupt status 1791 0=trace buffer did not generate interrupt 1792 1=trace buffer did generate interrupt */ 1793 uint64_t ciu_trg : 1; /**< CIU end trigger interrupt status 1794 0=trace buffer did not generate interrupt 1795 1=trace buffer did generate interrupt */ 1796#else 1797 uint64_t ciu_trg : 1; 1798 uint64_t ciu_thr : 1; 1799 uint64_t mcd0_trg : 1; 1800 uint64_t mcd0_thr : 1; 1801 uint64_t reserved_4_63 : 60; 1802#endif 1803 } s; 1804 struct cvmx_trax_int_status_s cn31xx; 1805 struct cvmx_trax_int_status_s cn38xx; 1806 struct cvmx_trax_int_status_s cn38xxp2; 1807 struct cvmx_trax_int_status_s cn52xx; 1808 struct cvmx_trax_int_status_s cn52xxp1; 1809 struct cvmx_trax_int_status_s cn56xx; 1810 struct cvmx_trax_int_status_s cn56xxp1; 1811 struct cvmx_trax_int_status_s cn58xx; 1812 struct cvmx_trax_int_status_s cn58xxp1; 1813 struct cvmx_trax_int_status_s cn61xx; 1814 struct cvmx_trax_int_status_s cn63xx; 1815 struct cvmx_trax_int_status_s cn63xxp1; 1816 struct cvmx_trax_int_status_s cn66xx; 1817 struct cvmx_trax_int_status_s cn68xx; 1818 struct cvmx_trax_int_status_s cn68xxp1; 1819 struct cvmx_trax_int_status_s cnf71xx; 1820}; 1821typedef union cvmx_trax_int_status cvmx_trax_int_status_t; 1822 1823/** 1824 * cvmx_tra#_read_dat 1825 * 1826 * TRA_READ_DAT = Trace Buffer Read Data 1827 * 1828 * Description: 1829 * 1830 * Notes: 1831 * This CSR is a memory of 1024 entries. When the trace was enabled, the read pointer was set to entry 1832 * 0 by hardware. Each read to this address increments the read pointer. 1833 */ 1834union cvmx_trax_read_dat { 1835 uint64_t u64; 1836 struct cvmx_trax_read_dat_s { 1837#ifdef __BIG_ENDIAN_BITFIELD 1838 uint64_t data : 64; /**< Trace buffer data for current entry 1839 if TRA_CTL[16]== 1; returns lower 64 bits of entry 1840 else two access are necessary to get all of 69bits 1841 first access of a pair is the lower 64 bits and 1842 second access is the upper 5 bits. */ 1843#else 1844 uint64_t data : 64; 1845#endif 1846 } s; 1847 struct cvmx_trax_read_dat_s cn31xx; 1848 struct cvmx_trax_read_dat_s cn38xx; 1849 struct cvmx_trax_read_dat_s cn38xxp2; 1850 struct cvmx_trax_read_dat_s cn52xx; 1851 struct cvmx_trax_read_dat_s cn52xxp1; 1852 struct cvmx_trax_read_dat_s cn56xx; 1853 struct cvmx_trax_read_dat_s cn56xxp1; 1854 struct cvmx_trax_read_dat_s cn58xx; 1855 struct cvmx_trax_read_dat_s cn58xxp1; 1856 struct cvmx_trax_read_dat_s cn61xx; 1857 struct cvmx_trax_read_dat_s cn63xx; 1858 struct cvmx_trax_read_dat_s cn63xxp1; 1859 struct cvmx_trax_read_dat_s cn66xx; 1860 struct cvmx_trax_read_dat_s cn68xx; 1861 struct cvmx_trax_read_dat_s cn68xxp1; 1862 struct cvmx_trax_read_dat_s cnf71xx; 1863}; 1864typedef union cvmx_trax_read_dat cvmx_trax_read_dat_t; 1865 1866/** 1867 * cvmx_tra#_read_dat_hi 1868 * 1869 * TRA_READ_DAT_HI = Trace Buffer Read Data- upper 5 bits do not use if TRA_CTL[16]==0 1870 * 1871 * Description: 1872 * 1873 * Notes: 1874 * This CSR is a memory of 1024 entries. Reads to this address do not increment the read pointer. The 1875 * 5 bits read are the upper 5 bits of the TRA entry last read by the TRA_READ_DAT reg. 1876 */ 1877union cvmx_trax_read_dat_hi { 1878 uint64_t u64; 1879 struct cvmx_trax_read_dat_hi_s { 1880#ifdef __BIG_ENDIAN_BITFIELD 1881 uint64_t reserved_5_63 : 59; 1882 uint64_t data : 5; /**< Trace buffer data[68:64] for current entry */ 1883#else 1884 uint64_t data : 5; 1885 uint64_t reserved_5_63 : 59; 1886#endif 1887 } s; 1888 struct cvmx_trax_read_dat_hi_s cn61xx; 1889 struct cvmx_trax_read_dat_hi_s cn63xx; 1890 struct cvmx_trax_read_dat_hi_s cn66xx; 1891 struct cvmx_trax_read_dat_hi_s cn68xx; 1892 struct cvmx_trax_read_dat_hi_s cn68xxp1; 1893 struct cvmx_trax_read_dat_hi_s cnf71xx; 1894}; 1895typedef union cvmx_trax_read_dat_hi cvmx_trax_read_dat_hi_t; 1896 1897/** 1898 * cvmx_tra#_trig0_adr_adr 1899 * 1900 * TRA_TRIG0_ADR_ADR = Trace Buffer Filter Address Address 1901 * 1902 * Description: 1903 */ 1904union cvmx_trax_trig0_adr_adr { 1905 uint64_t u64; 1906 struct cvmx_trax_trig0_adr_adr_s { 1907#ifdef __BIG_ENDIAN_BITFIELD 1908 uint64_t reserved_38_63 : 26; 1909 uint64_t adr : 38; /**< Unmasked Address 1910 The combination of TRA_TRIG0_ADR_ADR and 1911 TRA_TRIG0_ADR_MSK is a masked address to 1912 enable tracing of only those commands whose 1913 masked address matches */ 1914#else 1915 uint64_t adr : 38; 1916 uint64_t reserved_38_63 : 26; 1917#endif 1918 } s; 1919 struct cvmx_trax_trig0_adr_adr_cn31xx { 1920#ifdef __BIG_ENDIAN_BITFIELD 1921 uint64_t reserved_36_63 : 28; 1922 uint64_t adr : 36; /**< Unmasked Address 1923 The combination of TRA(0..0)_TRIG0_ADR_ADR and 1924 TRA(0..0)_TRIG0_ADR_MSK is a masked address to 1925 enable tracing of only those commands whose 1926 masked address matches */ 1927#else 1928 uint64_t adr : 36; 1929 uint64_t reserved_36_63 : 28; 1930#endif 1931 } cn31xx; 1932 struct cvmx_trax_trig0_adr_adr_cn31xx cn38xx; 1933 struct cvmx_trax_trig0_adr_adr_cn31xx cn38xxp2; 1934 struct cvmx_trax_trig0_adr_adr_cn31xx cn52xx; 1935 struct cvmx_trax_trig0_adr_adr_cn31xx cn52xxp1; 1936 struct cvmx_trax_trig0_adr_adr_cn31xx cn56xx; 1937 struct cvmx_trax_trig0_adr_adr_cn31xx cn56xxp1; 1938 struct cvmx_trax_trig0_adr_adr_cn31xx cn58xx; 1939 struct cvmx_trax_trig0_adr_adr_cn31xx cn58xxp1; 1940 struct cvmx_trax_trig0_adr_adr_s cn61xx; 1941 struct cvmx_trax_trig0_adr_adr_s cn63xx; 1942 struct cvmx_trax_trig0_adr_adr_s cn63xxp1; 1943 struct cvmx_trax_trig0_adr_adr_s cn66xx; 1944 struct cvmx_trax_trig0_adr_adr_s cn68xx; 1945 struct cvmx_trax_trig0_adr_adr_s cn68xxp1; 1946 struct cvmx_trax_trig0_adr_adr_s cnf71xx; 1947}; 1948typedef union cvmx_trax_trig0_adr_adr cvmx_trax_trig0_adr_adr_t; 1949 1950/** 1951 * cvmx_tra#_trig0_adr_msk 1952 * 1953 * TRA_TRIG0_ADR_MSK = Trace Buffer Filter Address Mask 1954 * 1955 * Description: 1956 */ 1957union cvmx_trax_trig0_adr_msk { 1958 uint64_t u64; 1959 struct cvmx_trax_trig0_adr_msk_s { 1960#ifdef __BIG_ENDIAN_BITFIELD 1961 uint64_t reserved_38_63 : 26; 1962 uint64_t adr : 38; /**< Address Mask 1963 The combination of TRA_TRIG0_ADR_ADR and 1964 TRA_TRIG0_ADR_MSK is a masked address to 1965 enable tracing of only those commands whose 1966 masked address matches. When a mask bit is not 1967 set, the corresponding address bits are assumed 1968 to match. Also, note that IOBDMAs do not have 1969 proper addresses, so when TRA_TRIG0_CMD[IOBDMA] 1970 is set, TRA_FILT_TRIG0_MSK must be zero to 1971 guarantee that any IOBDMAs are recognized as 1972 triggers. */ 1973#else 1974 uint64_t adr : 38; 1975 uint64_t reserved_38_63 : 26; 1976#endif 1977 } s; 1978 struct cvmx_trax_trig0_adr_msk_cn31xx { 1979#ifdef __BIG_ENDIAN_BITFIELD 1980 uint64_t reserved_36_63 : 28; 1981 uint64_t adr : 36; /**< Address Mask 1982 The combination of TRA(0..0)_TRIG0_ADR_ADR and 1983 TRA(0..0)_TRIG0_ADR_MSK is a masked address to 1984 enable tracing of only those commands whose 1985 masked address matches. When a mask bit is not 1986 set, the corresponding address bits are assumed 1987 to match. Also, note that IOBDMAs do not have 1988 proper addresses, so when TRA(0..0)_TRIG0_CMD[IOBDMA] 1989 is set, TRA(0..0)_FILT_TRIG0_MSK must be zero to 1990 guarantee that any IOBDMAs are recognized as 1991 triggers. */ 1992#else 1993 uint64_t adr : 36; 1994 uint64_t reserved_36_63 : 28; 1995#endif 1996 } cn31xx; 1997 struct cvmx_trax_trig0_adr_msk_cn31xx cn38xx; 1998 struct cvmx_trax_trig0_adr_msk_cn31xx cn38xxp2; 1999 struct cvmx_trax_trig0_adr_msk_cn31xx cn52xx; 2000 struct cvmx_trax_trig0_adr_msk_cn31xx cn52xxp1; 2001 struct cvmx_trax_trig0_adr_msk_cn31xx cn56xx; 2002 struct cvmx_trax_trig0_adr_msk_cn31xx cn56xxp1; 2003 struct cvmx_trax_trig0_adr_msk_cn31xx cn58xx; 2004 struct cvmx_trax_trig0_adr_msk_cn31xx cn58xxp1; 2005 struct cvmx_trax_trig0_adr_msk_s cn61xx; 2006 struct cvmx_trax_trig0_adr_msk_s cn63xx; 2007 struct cvmx_trax_trig0_adr_msk_s cn63xxp1; 2008 struct cvmx_trax_trig0_adr_msk_s cn66xx; 2009 struct cvmx_trax_trig0_adr_msk_s cn68xx; 2010 struct cvmx_trax_trig0_adr_msk_s cn68xxp1; 2011 struct cvmx_trax_trig0_adr_msk_s cnf71xx; 2012}; 2013typedef union cvmx_trax_trig0_adr_msk cvmx_trax_trig0_adr_msk_t; 2014 2015/** 2016 * cvmx_tra#_trig0_cmd 2017 * 2018 * TRA_TRIG0_CMD = Trace Buffer Filter Command Mask 2019 * 2020 * Description: 2021 * 2022 * Notes: 2023 * Note that the trace buffer does not do proper IOBDMA address compares. Thus, if IOBDMA is set, then 2024 * the address compare must be disabled (i.e. TRA_TRIG0_ADR_MSK set to zero) to guarantee that IOBDMAs 2025 * are recognized as triggers. 2026 */ 2027union cvmx_trax_trig0_cmd { 2028 uint64_t u64; 2029 struct cvmx_trax_trig0_cmd_s { 2030#ifdef __BIG_ENDIAN_BITFIELD 2031 uint64_t saa64 : 1; /**< Enable SAA64 tracing 2032 0=disable, 1=enable */ 2033 uint64_t saa32 : 1; /**< Enable SAA32 tracing 2034 0=disable, 1=enable */ 2035 uint64_t reserved_60_61 : 2; 2036 uint64_t faa64 : 1; /**< Enable FAA64 tracing 2037 0=disable, 1=enable */ 2038 uint64_t faa32 : 1; /**< Enable FAA32 tracing 2039 0=disable, 1=enable */ 2040 uint64_t reserved_56_57 : 2; 2041 uint64_t decr64 : 1; /**< Enable DECR64 tracing 2042 0=disable, 1=enable */ 2043 uint64_t decr32 : 1; /**< Enable DECR32 tracing 2044 0=disable, 1=enable */ 2045 uint64_t decr16 : 1; /**< Enable DECR16 tracing 2046 0=disable, 1=enable */ 2047 uint64_t decr8 : 1; /**< Enable DECR8 tracing 2048 0=disable, 1=enable */ 2049 uint64_t incr64 : 1; /**< Enable INCR64 tracing 2050 0=disable, 1=enable */ 2051 uint64_t incr32 : 1; /**< Enable INCR32 tracing 2052 0=disable, 1=enable */ 2053 uint64_t incr16 : 1; /**< Enable INCR16 tracing 2054 0=disable, 1=enable */ 2055 uint64_t incr8 : 1; /**< Enable INCR8 tracing 2056 0=disable, 1=enable */ 2057 uint64_t clr64 : 1; /**< Enable CLR64 tracing 2058 0=disable, 1=enable */ 2059 uint64_t clr32 : 1; /**< Enable CLR32 tracing 2060 0=disable, 1=enable */ 2061 uint64_t clr16 : 1; /**< Enable CLR16 tracing 2062 0=disable, 1=enable */ 2063 uint64_t clr8 : 1; /**< Enable CLR8 tracing 2064 0=disable, 1=enable */ 2065 uint64_t set64 : 1; /**< Enable SET64 tracing 2066 0=disable, 1=enable */ 2067 uint64_t set32 : 1; /**< Enable SET32 tracing 2068 0=disable, 1=enable */ 2069 uint64_t set16 : 1; /**< Enable SET16 tracing 2070 0=disable, 1=enable */ 2071 uint64_t set8 : 1; /**< Enable SET8 tracing 2072 0=disable, 1=enable */ 2073 uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 2074 0=disable, 1=enable */ 2075 uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 2076 0=disable, 1=enable */ 2077 uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 2078 0=disable, 1=enable */ 2079 uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 2080 0=disable, 1=enable */ 2081 uint64_t reserved_32_35 : 4; 2082 uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 2083 0=disable, 1=enable */ 2084 uint64_t wbl2 : 1; /**< Enable WBL2 tracing 2085 0=disable, 1=enable */ 2086 uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 2087 0=disable, 1=enable */ 2088 uint64_t invl2 : 1; /**< Enable INVL2 tracing 2089 0=disable, 1=enable */ 2090 uint64_t reserved_27_27 : 1; 2091 uint64_t stgl2i : 1; /**< Enable STGL2I tracing 2092 0=disable, 1=enable */ 2093 uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 2094 0=disable, 1=enable */ 2095 uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 2096 0=disable, 1=enable */ 2097 uint64_t fas64 : 1; /**< Enable FAS64 tracing 2098 0=disable, 1=enable */ 2099 uint64_t fas32 : 1; /**< Enable FAS32 tracing 2100 0=disable, 1=enable */ 2101 uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 2102 0=disable, 1=enable */ 2103 uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 2104 0=disable, 1=enable */ 2105 uint64_t reserved_16_19 : 4; 2106 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 2107 0=disable, 1=enable */ 2108 uint64_t iobst : 1; /**< Enable IOBST tracing 2109 0=disable, 1=enable */ 2110 uint64_t reserved_0_13 : 14; 2111#else 2112 uint64_t reserved_0_13 : 14; 2113 uint64_t iobst : 1; 2114 uint64_t iobdma : 1; 2115 uint64_t reserved_16_19 : 4; 2116 uint64_t stfil1 : 1; 2117 uint64_t sttil1 : 1; 2118 uint64_t fas32 : 1; 2119 uint64_t fas64 : 1; 2120 uint64_t wbil2i : 1; 2121 uint64_t ltgl2i : 1; 2122 uint64_t stgl2i : 1; 2123 uint64_t reserved_27_27 : 1; 2124 uint64_t invl2 : 1; 2125 uint64_t wbil2 : 1; 2126 uint64_t wbl2 : 1; 2127 uint64_t lckl2 : 1; 2128 uint64_t reserved_32_35 : 4; 2129 uint64_t iobst8 : 1; 2130 uint64_t iobst16 : 1; 2131 uint64_t iobst32 : 1; 2132 uint64_t iobst64 : 1; 2133 uint64_t set8 : 1; 2134 uint64_t set16 : 1; 2135 uint64_t set32 : 1; 2136 uint64_t set64 : 1; 2137 uint64_t clr8 : 1; 2138 uint64_t clr16 : 1; 2139 uint64_t clr32 : 1; 2140 uint64_t clr64 : 1; 2141 uint64_t incr8 : 1; 2142 uint64_t incr16 : 1; 2143 uint64_t incr32 : 1; 2144 uint64_t incr64 : 1; 2145 uint64_t decr8 : 1; 2146 uint64_t decr16 : 1; 2147 uint64_t decr32 : 1; 2148 uint64_t decr64 : 1; 2149 uint64_t reserved_56_57 : 2; 2150 uint64_t faa32 : 1; 2151 uint64_t faa64 : 1; 2152 uint64_t reserved_60_61 : 2; 2153 uint64_t saa32 : 1; 2154 uint64_t saa64 : 1; 2155#endif 2156 } s; 2157 struct cvmx_trax_trig0_cmd_cn31xx { 2158#ifdef __BIG_ENDIAN_BITFIELD 2159 uint64_t reserved_16_63 : 48; 2160 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 2161 0=disable, 1=enable */ 2162 uint64_t iobst : 1; /**< Enable IOBST tracing 2163 0=disable, 1=enable */ 2164 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 2165 0=disable, 1=enable */ 2166 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 2167 0=disable, 1=enable */ 2168 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 2169 0=disable, 1=enable */ 2170 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 2171 0=disable, 1=enable */ 2172 uint64_t stt : 1; /**< Enable STT tracing 2173 0=disable, 1=enable */ 2174 uint64_t stp : 1; /**< Enable STP tracing 2175 0=disable, 1=enable */ 2176 uint64_t stc : 1; /**< Enable STC tracing 2177 0=disable, 1=enable */ 2178 uint64_t stf : 1; /**< Enable STF tracing 2179 0=disable, 1=enable */ 2180 uint64_t ldt : 1; /**< Enable LDT tracing 2181 0=disable, 1=enable */ 2182 uint64_t ldi : 1; /**< Enable LDI tracing 2183 0=disable, 1=enable */ 2184 uint64_t ldd : 1; /**< Enable LDD tracing 2185 0=disable, 1=enable */ 2186 uint64_t psl1 : 1; /**< Enable PSL1 tracing 2187 0=disable, 1=enable */ 2188 uint64_t pl2 : 1; /**< Enable PL2 tracing 2189 0=disable, 1=enable */ 2190 uint64_t dwb : 1; /**< Enable DWB tracing 2191 0=disable, 1=enable */ 2192#else 2193 uint64_t dwb : 1; 2194 uint64_t pl2 : 1; 2195 uint64_t psl1 : 1; 2196 uint64_t ldd : 1; 2197 uint64_t ldi : 1; 2198 uint64_t ldt : 1; 2199 uint64_t stf : 1; 2200 uint64_t stc : 1; 2201 uint64_t stp : 1; 2202 uint64_t stt : 1; 2203 uint64_t iobld8 : 1; 2204 uint64_t iobld16 : 1; 2205 uint64_t iobld32 : 1; 2206 uint64_t iobld64 : 1; 2207 uint64_t iobst : 1; 2208 uint64_t iobdma : 1; 2209 uint64_t reserved_16_63 : 48; 2210#endif 2211 } cn31xx; 2212 struct cvmx_trax_trig0_cmd_cn31xx cn38xx; 2213 struct cvmx_trax_trig0_cmd_cn31xx cn38xxp2; 2214 struct cvmx_trax_trig0_cmd_cn52xx { 2215#ifdef __BIG_ENDIAN_BITFIELD 2216 uint64_t reserved_17_63 : 47; 2217 uint64_t saa : 1; /**< Enable SAA tracing 2218 0=disable, 1=enable */ 2219 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 2220 0=disable, 1=enable */ 2221 uint64_t iobst : 1; /**< Enable IOBST tracing 2222 0=disable, 1=enable */ 2223 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 2224 0=disable, 1=enable */ 2225 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 2226 0=disable, 1=enable */ 2227 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 2228 0=disable, 1=enable */ 2229 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 2230 0=disable, 1=enable */ 2231 uint64_t stt : 1; /**< Enable STT tracing 2232 0=disable, 1=enable */ 2233 uint64_t stp : 1; /**< Enable STP tracing 2234 0=disable, 1=enable */ 2235 uint64_t stc : 1; /**< Enable STC tracing 2236 0=disable, 1=enable */ 2237 uint64_t stf : 1; /**< Enable STF tracing 2238 0=disable, 1=enable */ 2239 uint64_t ldt : 1; /**< Enable LDT tracing 2240 0=disable, 1=enable */ 2241 uint64_t ldi : 1; /**< Enable LDI tracing 2242 0=disable, 1=enable */ 2243 uint64_t ldd : 1; /**< Enable LDD tracing 2244 0=disable, 1=enable */ 2245 uint64_t psl1 : 1; /**< Enable PSL1 tracing 2246 0=disable, 1=enable */ 2247 uint64_t pl2 : 1; /**< Enable PL2 tracing 2248 0=disable, 1=enable */ 2249 uint64_t dwb : 1; /**< Enable DWB tracing 2250 0=disable, 1=enable */ 2251#else 2252 uint64_t dwb : 1; 2253 uint64_t pl2 : 1; 2254 uint64_t psl1 : 1; 2255 uint64_t ldd : 1; 2256 uint64_t ldi : 1; 2257 uint64_t ldt : 1; 2258 uint64_t stf : 1; 2259 uint64_t stc : 1; 2260 uint64_t stp : 1; 2261 uint64_t stt : 1; 2262 uint64_t iobld8 : 1; 2263 uint64_t iobld16 : 1; 2264 uint64_t iobld32 : 1; 2265 uint64_t iobld64 : 1; 2266 uint64_t iobst : 1; 2267 uint64_t iobdma : 1; 2268 uint64_t saa : 1; 2269 uint64_t reserved_17_63 : 47; 2270#endif 2271 } cn52xx; 2272 struct cvmx_trax_trig0_cmd_cn52xx cn52xxp1; 2273 struct cvmx_trax_trig0_cmd_cn52xx cn56xx; 2274 struct cvmx_trax_trig0_cmd_cn52xx cn56xxp1; 2275 struct cvmx_trax_trig0_cmd_cn52xx cn58xx; 2276 struct cvmx_trax_trig0_cmd_cn52xx cn58xxp1; 2277 struct cvmx_trax_trig0_cmd_cn61xx { 2278#ifdef __BIG_ENDIAN_BITFIELD 2279 uint64_t saa64 : 1; /**< Enable SAA64 tracing 2280 0=disable, 1=enable */ 2281 uint64_t saa32 : 1; /**< Enable SAA32 tracing 2282 0=disable, 1=enable */ 2283 uint64_t reserved_60_61 : 2; 2284 uint64_t faa64 : 1; /**< Enable FAA64 tracing 2285 0=disable, 1=enable */ 2286 uint64_t faa32 : 1; /**< Enable FAA32 tracing 2287 0=disable, 1=enable */ 2288 uint64_t reserved_56_57 : 2; 2289 uint64_t decr64 : 1; /**< Enable DECR64 tracing 2290 0=disable, 1=enable */ 2291 uint64_t decr32 : 1; /**< Enable DECR32 tracing 2292 0=disable, 1=enable */ 2293 uint64_t decr16 : 1; /**< Enable DECR16 tracing 2294 0=disable, 1=enable */ 2295 uint64_t decr8 : 1; /**< Enable DECR8 tracing 2296 0=disable, 1=enable */ 2297 uint64_t incr64 : 1; /**< Enable INCR64 tracing 2298 0=disable, 1=enable */ 2299 uint64_t incr32 : 1; /**< Enable INCR32 tracing 2300 0=disable, 1=enable */ 2301 uint64_t incr16 : 1; /**< Enable INCR16 tracing 2302 0=disable, 1=enable */ 2303 uint64_t incr8 : 1; /**< Enable INCR8 tracing 2304 0=disable, 1=enable */ 2305 uint64_t clr64 : 1; /**< Enable CLR64 tracing 2306 0=disable, 1=enable */ 2307 uint64_t clr32 : 1; /**< Enable CLR32 tracing 2308 0=disable, 1=enable */ 2309 uint64_t clr16 : 1; /**< Enable CLR16 tracing 2310 0=disable, 1=enable */ 2311 uint64_t clr8 : 1; /**< Enable CLR8 tracing 2312 0=disable, 1=enable */ 2313 uint64_t set64 : 1; /**< Enable SET64 tracing 2314 0=disable, 1=enable */ 2315 uint64_t set32 : 1; /**< Enable SET32 tracing 2316 0=disable, 1=enable */ 2317 uint64_t set16 : 1; /**< Enable SET16 tracing 2318 0=disable, 1=enable */ 2319 uint64_t set8 : 1; /**< Enable SET8 tracing 2320 0=disable, 1=enable */ 2321 uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 2322 0=disable, 1=enable */ 2323 uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 2324 0=disable, 1=enable */ 2325 uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 2326 0=disable, 1=enable */ 2327 uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 2328 0=disable, 1=enable */ 2329 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 2330 0=disable, 1=enable */ 2331 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 2332 0=disable, 1=enable */ 2333 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 2334 0=disable, 1=enable */ 2335 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 2336 0=disable, 1=enable */ 2337 uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 2338 0=disable, 1=enable */ 2339 uint64_t wbl2 : 1; /**< Enable WBL2 tracing 2340 0=disable, 1=enable */ 2341 uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 2342 0=disable, 1=enable */ 2343 uint64_t invl2 : 1; /**< Enable INVL2 tracing 2344 0=disable, 1=enable */ 2345 uint64_t reserved_27_27 : 1; 2346 uint64_t stgl2i : 1; /**< Enable STGL2I tracing 2347 0=disable, 1=enable */ 2348 uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 2349 0=disable, 1=enable */ 2350 uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 2351 0=disable, 1=enable */ 2352 uint64_t fas64 : 1; /**< Enable FAS64 tracing 2353 0=disable, 1=enable */ 2354 uint64_t fas32 : 1; /**< Enable FAS32 tracing 2355 0=disable, 1=enable */ 2356 uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 2357 0=disable, 1=enable */ 2358 uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 2359 0=disable, 1=enable */ 2360 uint64_t stc : 1; /**< Enable STC tracing 2361 0=disable, 1=enable */ 2362 uint64_t stp : 1; /**< Enable STP tracing 2363 0=disable, 1=enable */ 2364 uint64_t stt : 1; /**< Enable STT tracing 2365 0=disable, 1=enable */ 2366 uint64_t stf : 1; /**< Enable STF tracing 2367 0=disable, 1=enable */ 2368 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 2369 0=disable, 1=enable */ 2370 uint64_t reserved_10_14 : 5; 2371 uint64_t psl1 : 1; /**< Enable PSL1 tracing 2372 0=disable, 1=enable */ 2373 uint64_t ldd : 1; /**< Enable LDD tracing 2374 0=disable, 1=enable */ 2375 uint64_t reserved_6_7 : 2; 2376 uint64_t dwb : 1; /**< Enable DWB tracing 2377 0=disable, 1=enable */ 2378 uint64_t rpl2 : 1; /**< Enable RPL2 tracing 2379 0=disable, 1=enable */ 2380 uint64_t pl2 : 1; /**< Enable PL2 tracing 2381 0=disable, 1=enable */ 2382 uint64_t ldi : 1; /**< Enable LDI tracing 2383 0=disable, 1=enable */ 2384 uint64_t ldt : 1; /**< Enable LDT tracing 2385 0=disable, 1=enable */ 2386 uint64_t nop : 1; /**< Enable NOP tracing 2387 0=disable, 1=enable */ 2388#else 2389 uint64_t nop : 1; 2390 uint64_t ldt : 1; 2391 uint64_t ldi : 1; 2392 uint64_t pl2 : 1; 2393 uint64_t rpl2 : 1; 2394 uint64_t dwb : 1; 2395 uint64_t reserved_6_7 : 2; 2396 uint64_t ldd : 1; 2397 uint64_t psl1 : 1; 2398 uint64_t reserved_10_14 : 5; 2399 uint64_t iobdma : 1; 2400 uint64_t stf : 1; 2401 uint64_t stt : 1; 2402 uint64_t stp : 1; 2403 uint64_t stc : 1; 2404 uint64_t stfil1 : 1; 2405 uint64_t sttil1 : 1; 2406 uint64_t fas32 : 1; 2407 uint64_t fas64 : 1; 2408 uint64_t wbil2i : 1; 2409 uint64_t ltgl2i : 1; 2410 uint64_t stgl2i : 1; 2411 uint64_t reserved_27_27 : 1; 2412 uint64_t invl2 : 1; 2413 uint64_t wbil2 : 1; 2414 uint64_t wbl2 : 1; 2415 uint64_t lckl2 : 1; 2416 uint64_t iobld8 : 1; 2417 uint64_t iobld16 : 1; 2418 uint64_t iobld32 : 1; 2419 uint64_t iobld64 : 1; 2420 uint64_t iobst8 : 1; 2421 uint64_t iobst16 : 1; 2422 uint64_t iobst32 : 1; 2423 uint64_t iobst64 : 1; 2424 uint64_t set8 : 1; 2425 uint64_t set16 : 1; 2426 uint64_t set32 : 1; 2427 uint64_t set64 : 1; 2428 uint64_t clr8 : 1; 2429 uint64_t clr16 : 1; 2430 uint64_t clr32 : 1; 2431 uint64_t clr64 : 1; 2432 uint64_t incr8 : 1; 2433 uint64_t incr16 : 1; 2434 uint64_t incr32 : 1; 2435 uint64_t incr64 : 1; 2436 uint64_t decr8 : 1; 2437 uint64_t decr16 : 1; 2438 uint64_t decr32 : 1; 2439 uint64_t decr64 : 1; 2440 uint64_t reserved_56_57 : 2; 2441 uint64_t faa32 : 1; 2442 uint64_t faa64 : 1; 2443 uint64_t reserved_60_61 : 2; 2444 uint64_t saa32 : 1; 2445 uint64_t saa64 : 1; 2446#endif 2447 } cn61xx; 2448 struct cvmx_trax_trig0_cmd_cn61xx cn63xx; 2449 struct cvmx_trax_trig0_cmd_cn61xx cn63xxp1; 2450 struct cvmx_trax_trig0_cmd_cn61xx cn66xx; 2451 struct cvmx_trax_trig0_cmd_cn61xx cn68xx; 2452 struct cvmx_trax_trig0_cmd_cn61xx cn68xxp1; 2453 struct cvmx_trax_trig0_cmd_cn61xx cnf71xx; 2454}; 2455typedef union cvmx_trax_trig0_cmd cvmx_trax_trig0_cmd_t; 2456 2457/** 2458 * cvmx_tra#_trig0_did 2459 * 2460 * TRA_TRIG0_DID = Trace Buffer Filter DestinationId Mask 2461 * 2462 * Description: 2463 */ 2464union cvmx_trax_trig0_did { 2465 uint64_t u64; 2466 struct cvmx_trax_trig0_did_s { 2467#ifdef __BIG_ENDIAN_BITFIELD 2468 uint64_t reserved_13_63 : 51; 2469 uint64_t pow : 1; /**< Enable triggering on requests to POW 2470 (get work, add work, status/memory/index 2471 loads, NULLRd loads, CSR's) */ 2472 uint64_t reserved_9_11 : 3; 2473 uint64_t rng : 1; /**< Enable triggering on requests to RNG 2474 (loads/IOBDMA's are legal) */ 2475 uint64_t zip : 1; /**< Enable triggering on requests to ZIP 2476 (doorbell stores are legal) */ 2477 uint64_t dfa : 1; /**< Enable triggering on requests to DFA 2478 (CSR's and operations are legal) */ 2479 uint64_t fpa : 1; /**< Enable triggering on requests to FPA 2480 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 2481 uint64_t key : 1; /**< Enable triggering on requests to KEY memory 2482 (loads/IOBDMA's/stores are legal) */ 2483 uint64_t reserved_3_3 : 1; 2484 uint64_t illegal3 : 2; /**< Illegal destinations */ 2485 uint64_t mio : 1; /**< Enable triggering on MIO accesses 2486 (CIU and GPIO CSR's, boot bus accesses) */ 2487#else 2488 uint64_t mio : 1; 2489 uint64_t illegal3 : 2; 2490 uint64_t reserved_3_3 : 1; 2491 uint64_t key : 1; 2492 uint64_t fpa : 1; 2493 uint64_t dfa : 1; 2494 uint64_t zip : 1; 2495 uint64_t rng : 1; 2496 uint64_t reserved_9_11 : 3; 2497 uint64_t pow : 1; 2498 uint64_t reserved_13_63 : 51; 2499#endif 2500 } s; 2501 struct cvmx_trax_trig0_did_cn31xx { 2502#ifdef __BIG_ENDIAN_BITFIELD 2503 uint64_t reserved_32_63 : 32; 2504 uint64_t illegal : 19; /**< Illegal destinations */ 2505 uint64_t pow : 1; /**< Enable triggering on requests to POW 2506 (get work, add work, status/memory/index 2507 loads, NULLRd loads, CSR's) */ 2508 uint64_t illegal2 : 3; /**< Illegal destinations */ 2509 uint64_t rng : 1; /**< Enable triggering on requests to RNG 2510 (loads/IOBDMA's are legal) */ 2511 uint64_t zip : 1; /**< Enable triggering on requests to ZIP 2512 (doorbell stores are legal) */ 2513 uint64_t dfa : 1; /**< Enable triggering on requests to DFA 2514 (CSR's and operations are legal) */ 2515 uint64_t fpa : 1; /**< Enable triggering on requests to FPA 2516 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 2517 uint64_t key : 1; /**< Enable triggering on requests to KEY memory 2518 (loads/IOBDMA's/stores are legal) */ 2519 uint64_t pci : 1; /**< Enable triggering on requests to PCI and RSL-type 2520 CSR's (RSL CSR's, PCI bus operations, PCI 2521 CSR's) */ 2522 uint64_t illegal3 : 2; /**< Illegal destinations */ 2523 uint64_t mio : 1; /**< Enable triggering on CIU and GPIO CSR's */ 2524#else 2525 uint64_t mio : 1; 2526 uint64_t illegal3 : 2; 2527 uint64_t pci : 1; 2528 uint64_t key : 1; 2529 uint64_t fpa : 1; 2530 uint64_t dfa : 1; 2531 uint64_t zip : 1; 2532 uint64_t rng : 1; 2533 uint64_t illegal2 : 3; 2534 uint64_t pow : 1; 2535 uint64_t illegal : 19; 2536 uint64_t reserved_32_63 : 32; 2537#endif 2538 } cn31xx; 2539 struct cvmx_trax_trig0_did_cn31xx cn38xx; 2540 struct cvmx_trax_trig0_did_cn31xx cn38xxp2; 2541 struct cvmx_trax_trig0_did_cn31xx cn52xx; 2542 struct cvmx_trax_trig0_did_cn31xx cn52xxp1; 2543 struct cvmx_trax_trig0_did_cn31xx cn56xx; 2544 struct cvmx_trax_trig0_did_cn31xx cn56xxp1; 2545 struct cvmx_trax_trig0_did_cn31xx cn58xx; 2546 struct cvmx_trax_trig0_did_cn31xx cn58xxp1; 2547 struct cvmx_trax_trig0_did_cn61xx { 2548#ifdef __BIG_ENDIAN_BITFIELD 2549 uint64_t reserved_32_63 : 32; 2550 uint64_t illegal5 : 1; /**< Illegal destinations */ 2551 uint64_t fau : 1; /**< Enable triggering on FAU accesses */ 2552 uint64_t illegal4 : 2; /**< Illegal destinations */ 2553 uint64_t dpi : 1; /**< Enable triggering on DPI accesses 2554 (DPI NCB CSRs) */ 2555 uint64_t illegal : 12; /**< Illegal destinations */ 2556 uint64_t rad : 1; /**< Enable triggering on RAD accesses 2557 (doorbells) */ 2558 uint64_t usb0 : 1; /**< Enable triggering on USB0 accesses 2559 (UAHC0 EHCI and OHCI NCB CSRs) */ 2560 uint64_t pow : 1; /**< Enable triggering on requests to POW 2561 (get work, add work, status/memory/index 2562 loads, NULLRd loads, CSR's) */ 2563 uint64_t illegal2 : 1; /**< Illegal destination */ 2564 uint64_t pko : 1; /**< Enable triggering on PKO accesses 2565 (doorbells) */ 2566 uint64_t ipd : 1; /**< Enable triggering on IPD CSR accesses 2567 (IPD CSRs) */ 2568 uint64_t rng : 1; /**< Enable triggering on requests to RNG 2569 (loads/IOBDMA's are legal) */ 2570 uint64_t zip : 1; /**< Enable triggering on requests to ZIP 2571 (doorbell stores are legal) */ 2572 uint64_t dfa : 1; /**< Enable triggering on requests to DFA 2573 (CSR's and operations are legal) */ 2574 uint64_t fpa : 1; /**< Enable triggering on requests to FPA 2575 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 2576 uint64_t key : 1; /**< Enable triggering on requests to KEY memory 2577 (loads/IOBDMA's/stores are legal) */ 2578 uint64_t sli : 1; /**< Enable triggering on requests to SLI and RSL-type 2579 CSR's (RSL CSR's, PCI/sRIO bus operations, SLI 2580 CSR's) */ 2581 uint64_t illegal3 : 2; /**< Illegal destinations */ 2582 uint64_t mio : 1; /**< Enable triggering on MIO accesses 2583 (CIU and GPIO CSR's, boot bus accesses) */ 2584#else 2585 uint64_t mio : 1; 2586 uint64_t illegal3 : 2; 2587 uint64_t sli : 1; 2588 uint64_t key : 1; 2589 uint64_t fpa : 1; 2590 uint64_t dfa : 1; 2591 uint64_t zip : 1; 2592 uint64_t rng : 1; 2593 uint64_t ipd : 1; 2594 uint64_t pko : 1; 2595 uint64_t illegal2 : 1; 2596 uint64_t pow : 1; 2597 uint64_t usb0 : 1; 2598 uint64_t rad : 1; 2599 uint64_t illegal : 12; 2600 uint64_t dpi : 1; 2601 uint64_t illegal4 : 2; 2602 uint64_t fau : 1; 2603 uint64_t illegal5 : 1; 2604 uint64_t reserved_32_63 : 32; 2605#endif 2606 } cn61xx; 2607 struct cvmx_trax_trig0_did_cn61xx cn63xx; 2608 struct cvmx_trax_trig0_did_cn61xx cn63xxp1; 2609 struct cvmx_trax_trig0_did_cn61xx cn66xx; 2610 struct cvmx_trax_trig0_did_cn61xx cn68xx; 2611 struct cvmx_trax_trig0_did_cn61xx cn68xxp1; 2612 struct cvmx_trax_trig0_did_cn61xx cnf71xx; 2613}; 2614typedef union cvmx_trax_trig0_did cvmx_trax_trig0_did_t; 2615 2616/** 2617 * cvmx_tra#_trig0_sid 2618 * 2619 * TRA_TRIG0_SID = Trace Buffer Filter SourceId Mask 2620 * 2621 * Description: 2622 */ 2623union cvmx_trax_trig0_sid { 2624 uint64_t u64; 2625 struct cvmx_trax_trig0_sid_s { 2626#ifdef __BIG_ENDIAN_BITFIELD 2627 uint64_t reserved_20_63 : 44; 2628 uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 2629 uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 2630 PCI,ZIP,POW, and PKO (writes) */ 2631 uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 2632 uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 2633 uint64_t pp : 16; /**< Enable triggering from PP[N] with matching SourceID 2634 0=disable, 1=enable per bit N where 0<=N<=3 */ 2635#else 2636 uint64_t pp : 16; 2637 uint64_t pki : 1; 2638 uint64_t pko : 1; 2639 uint64_t iobreq : 1; 2640 uint64_t dwb : 1; 2641 uint64_t reserved_20_63 : 44; 2642#endif 2643 } s; 2644 struct cvmx_trax_trig0_sid_s cn31xx; 2645 struct cvmx_trax_trig0_sid_s cn38xx; 2646 struct cvmx_trax_trig0_sid_s cn38xxp2; 2647 struct cvmx_trax_trig0_sid_s cn52xx; 2648 struct cvmx_trax_trig0_sid_s cn52xxp1; 2649 struct cvmx_trax_trig0_sid_s cn56xx; 2650 struct cvmx_trax_trig0_sid_s cn56xxp1; 2651 struct cvmx_trax_trig0_sid_s cn58xx; 2652 struct cvmx_trax_trig0_sid_s cn58xxp1; 2653 struct cvmx_trax_trig0_sid_cn61xx { 2654#ifdef __BIG_ENDIAN_BITFIELD 2655 uint64_t reserved_20_63 : 44; 2656 uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 2657 uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 2658 PCI,ZIP,POW, and PKO (writes) */ 2659 uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 2660 uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 2661 uint64_t reserved_4_15 : 12; 2662 uint64_t pp : 4; /**< Enable triggering from PP[N] with matching SourceID 2663 0=disable, 1=enable per bit N where 0<=N<=3 */ 2664#else 2665 uint64_t pp : 4; 2666 uint64_t reserved_4_15 : 12; 2667 uint64_t pki : 1; 2668 uint64_t pko : 1; 2669 uint64_t iobreq : 1; 2670 uint64_t dwb : 1; 2671 uint64_t reserved_20_63 : 44; 2672#endif 2673 } cn61xx; 2674 struct cvmx_trax_trig0_sid_cn63xx { 2675#ifdef __BIG_ENDIAN_BITFIELD 2676 uint64_t reserved_20_63 : 44; 2677 uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 2678 uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 2679 PCI,ZIP,POW, and PKO (writes) */ 2680 uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 2681 uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 2682 uint64_t reserved_8_15 : 8; 2683 uint64_t pp : 8; /**< Enable triggering from PP[N] with matching SourceID 2684 0=disable, 1=enableper bit N where 0<=N<=15 */ 2685#else 2686 uint64_t pp : 8; 2687 uint64_t reserved_8_15 : 8; 2688 uint64_t pki : 1; 2689 uint64_t pko : 1; 2690 uint64_t iobreq : 1; 2691 uint64_t dwb : 1; 2692 uint64_t reserved_20_63 : 44; 2693#endif 2694 } cn63xx; 2695 struct cvmx_trax_trig0_sid_cn63xxp1 { 2696#ifdef __BIG_ENDIAN_BITFIELD 2697 uint64_t reserved_20_63 : 44; 2698 uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 2699 uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 2700 PCI,ZIP,POW, and PKO (writes) */ 2701 uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 2702 uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 2703 uint64_t reserved_6_15 : 10; 2704 uint64_t pp : 6; /**< Enable triggering from PP[N] with matching SourceID 2705 0=disable, 1=enable per bit N where 0<=N<=5 */ 2706#else 2707 uint64_t pp : 6; 2708 uint64_t reserved_6_15 : 10; 2709 uint64_t pki : 1; 2710 uint64_t pko : 1; 2711 uint64_t iobreq : 1; 2712 uint64_t dwb : 1; 2713 uint64_t reserved_20_63 : 44; 2714#endif 2715 } cn63xxp1; 2716 struct cvmx_trax_trig0_sid_cn66xx { 2717#ifdef __BIG_ENDIAN_BITFIELD 2718 uint64_t reserved_20_63 : 44; 2719 uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 2720 uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 2721 PCI,ZIP,POW, and PKO (writes) */ 2722 uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 2723 uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 2724 uint64_t reserved_10_15 : 6; 2725 uint64_t pp : 10; /**< Enable triggering from PP[N] with matching SourceID 2726 0=disable, 1=enableper bit N where 0<=N<=15 */ 2727#else 2728 uint64_t pp : 10; 2729 uint64_t reserved_10_15 : 6; 2730 uint64_t pki : 1; 2731 uint64_t pko : 1; 2732 uint64_t iobreq : 1; 2733 uint64_t dwb : 1; 2734 uint64_t reserved_20_63 : 44; 2735#endif 2736 } cn66xx; 2737 struct cvmx_trax_trig0_sid_cn63xx cn68xx; 2738 struct cvmx_trax_trig0_sid_cn63xx cn68xxp1; 2739 struct cvmx_trax_trig0_sid_cn61xx cnf71xx; 2740}; 2741typedef union cvmx_trax_trig0_sid cvmx_trax_trig0_sid_t; 2742 2743/** 2744 * cvmx_tra#_trig1_adr_adr 2745 * 2746 * TRA_TRIG1_ADR_ADR = Trace Buffer Filter Address Address 2747 * 2748 * Description: 2749 */ 2750union cvmx_trax_trig1_adr_adr { 2751 uint64_t u64; 2752 struct cvmx_trax_trig1_adr_adr_s { 2753#ifdef __BIG_ENDIAN_BITFIELD 2754 uint64_t reserved_38_63 : 26; 2755 uint64_t adr : 38; /**< Unmasked Address 2756 The combination of TRA_TRIG1_ADR_ADR and 2757 TRA_TRIG1_ADR_MSK is a masked address to 2758 enable tracing of only those commands whose 2759 masked address matches */ 2760#else 2761 uint64_t adr : 38; 2762 uint64_t reserved_38_63 : 26; 2763#endif 2764 } s; 2765 struct cvmx_trax_trig1_adr_adr_cn31xx { 2766#ifdef __BIG_ENDIAN_BITFIELD 2767 uint64_t reserved_36_63 : 28; 2768 uint64_t adr : 36; /**< Unmasked Address 2769 The combination of TRA(0..0)_TRIG1_ADR_ADR and 2770 TRA(0..0)_TRIG1_ADR_MSK is a masked address to 2771 enable tracing of only those commands whose 2772 masked address matches */ 2773#else 2774 uint64_t adr : 36; 2775 uint64_t reserved_36_63 : 28; 2776#endif 2777 } cn31xx; 2778 struct cvmx_trax_trig1_adr_adr_cn31xx cn38xx; 2779 struct cvmx_trax_trig1_adr_adr_cn31xx cn38xxp2; 2780 struct cvmx_trax_trig1_adr_adr_cn31xx cn52xx; 2781 struct cvmx_trax_trig1_adr_adr_cn31xx cn52xxp1; 2782 struct cvmx_trax_trig1_adr_adr_cn31xx cn56xx; 2783 struct cvmx_trax_trig1_adr_adr_cn31xx cn56xxp1; 2784 struct cvmx_trax_trig1_adr_adr_cn31xx cn58xx; 2785 struct cvmx_trax_trig1_adr_adr_cn31xx cn58xxp1; 2786 struct cvmx_trax_trig1_adr_adr_s cn61xx; 2787 struct cvmx_trax_trig1_adr_adr_s cn63xx; 2788 struct cvmx_trax_trig1_adr_adr_s cn63xxp1; 2789 struct cvmx_trax_trig1_adr_adr_s cn66xx; 2790 struct cvmx_trax_trig1_adr_adr_s cn68xx; 2791 struct cvmx_trax_trig1_adr_adr_s cn68xxp1; 2792 struct cvmx_trax_trig1_adr_adr_s cnf71xx; 2793}; 2794typedef union cvmx_trax_trig1_adr_adr cvmx_trax_trig1_adr_adr_t; 2795 2796/** 2797 * cvmx_tra#_trig1_adr_msk 2798 * 2799 * TRA_TRIG1_ADR_MSK = Trace Buffer Filter Address Mask 2800 * 2801 * Description: 2802 */ 2803union cvmx_trax_trig1_adr_msk { 2804 uint64_t u64; 2805 struct cvmx_trax_trig1_adr_msk_s { 2806#ifdef __BIG_ENDIAN_BITFIELD 2807 uint64_t reserved_38_63 : 26; 2808 uint64_t adr : 38; /**< Address Mask 2809 The combination of TRA_TRIG1_ADR_ADR and 2810 TRA_TRIG1_ADR_MSK is a masked address to 2811 enable tracing of only those commands whose 2812 masked address matches. When a mask bit is not 2813 set, the corresponding address bits are assumed 2814 to match. Also, note that IOBDMAs do not have 2815 proper addresses, so when TRA_TRIG1_CMD[IOBDMA] 2816 is set, TRA_FILT_TRIG1_MSK must be zero to 2817 guarantee that any IOBDMAs are recognized as 2818 triggers. */ 2819#else 2820 uint64_t adr : 38; 2821 uint64_t reserved_38_63 : 26; 2822#endif 2823 } s; 2824 struct cvmx_trax_trig1_adr_msk_cn31xx { 2825#ifdef __BIG_ENDIAN_BITFIELD 2826 uint64_t reserved_36_63 : 28; 2827 uint64_t adr : 36; /**< Address Mask 2828 The combination of TRA(0..0)_TRIG1_ADR_ADR and 2829 TRA(0..0)_TRIG1_ADR_MSK is a masked address to 2830 enable tracing of only those commands whose 2831 masked address matches. When a mask bit is not 2832 set, the corresponding address bits are assumed 2833 to match. Also, note that IOBDMAs do not have 2834 proper addresses, so when TRA(0..0)_TRIG1_CMD[IOBDMA] 2835 is set, TRA(0..0)_FILT_TRIG1_MSK must be zero to 2836 guarantee that any IOBDMAs are recognized as 2837 triggers. */ 2838#else 2839 uint64_t adr : 36; 2840 uint64_t reserved_36_63 : 28; 2841#endif 2842 } cn31xx; 2843 struct cvmx_trax_trig1_adr_msk_cn31xx cn38xx; 2844 struct cvmx_trax_trig1_adr_msk_cn31xx cn38xxp2; 2845 struct cvmx_trax_trig1_adr_msk_cn31xx cn52xx; 2846 struct cvmx_trax_trig1_adr_msk_cn31xx cn52xxp1; 2847 struct cvmx_trax_trig1_adr_msk_cn31xx cn56xx; 2848 struct cvmx_trax_trig1_adr_msk_cn31xx cn56xxp1; 2849 struct cvmx_trax_trig1_adr_msk_cn31xx cn58xx; 2850 struct cvmx_trax_trig1_adr_msk_cn31xx cn58xxp1; 2851 struct cvmx_trax_trig1_adr_msk_s cn61xx; 2852 struct cvmx_trax_trig1_adr_msk_s cn63xx; 2853 struct cvmx_trax_trig1_adr_msk_s cn63xxp1; 2854 struct cvmx_trax_trig1_adr_msk_s cn66xx; 2855 struct cvmx_trax_trig1_adr_msk_s cn68xx; 2856 struct cvmx_trax_trig1_adr_msk_s cn68xxp1; 2857 struct cvmx_trax_trig1_adr_msk_s cnf71xx; 2858}; 2859typedef union cvmx_trax_trig1_adr_msk cvmx_trax_trig1_adr_msk_t; 2860 2861/** 2862 * cvmx_tra#_trig1_cmd 2863 * 2864 * TRA_TRIG1_CMD = Trace Buffer Filter Command Mask 2865 * 2866 * Description: 2867 * 2868 * Notes: 2869 * Note that the trace buffer does not do proper IOBDMA address compares. Thus, if IOBDMA is set, then 2870 * the address compare must be disabled (i.e. TRA_TRIG1_ADR_MSK set to zero) to guarantee that IOBDMAs 2871 * are recognized as triggers. 2872 */ 2873union cvmx_trax_trig1_cmd { 2874 uint64_t u64; 2875 struct cvmx_trax_trig1_cmd_s { 2876#ifdef __BIG_ENDIAN_BITFIELD 2877 uint64_t saa64 : 1; /**< Enable SAA64 tracing 2878 0=disable, 1=enable */ 2879 uint64_t saa32 : 1; /**< Enable SAA32 tracing 2880 0=disable, 1=enable */ 2881 uint64_t reserved_60_61 : 2; 2882 uint64_t faa64 : 1; /**< Enable FAA64 tracing 2883 0=disable, 1=enable */ 2884 uint64_t faa32 : 1; /**< Enable FAA32 tracing 2885 0=disable, 1=enable */ 2886 uint64_t reserved_56_57 : 2; 2887 uint64_t decr64 : 1; /**< Enable DECR64 tracing 2888 0=disable, 1=enable */ 2889 uint64_t decr32 : 1; /**< Enable DECR32 tracing 2890 0=disable, 1=enable */ 2891 uint64_t decr16 : 1; /**< Enable DECR16 tracing 2892 0=disable, 1=enable */ 2893 uint64_t decr8 : 1; /**< Enable DECR8 tracing 2894 0=disable, 1=enable */ 2895 uint64_t incr64 : 1; /**< Enable INCR64 tracing 2896 0=disable, 1=enable */ 2897 uint64_t incr32 : 1; /**< Enable INCR32 tracing 2898 0=disable, 1=enable */ 2899 uint64_t incr16 : 1; /**< Enable INCR16 tracing 2900 0=disable, 1=enable */ 2901 uint64_t incr8 : 1; /**< Enable INCR8 tracing 2902 0=disable, 1=enable */ 2903 uint64_t clr64 : 1; /**< Enable CLR64 tracing 2904 0=disable, 1=enable */ 2905 uint64_t clr32 : 1; /**< Enable CLR32 tracing 2906 0=disable, 1=enable */ 2907 uint64_t clr16 : 1; /**< Enable CLR16 tracing 2908 0=disable, 1=enable */ 2909 uint64_t clr8 : 1; /**< Enable CLR8 tracing 2910 0=disable, 1=enable */ 2911 uint64_t set64 : 1; /**< Enable SET64 tracing 2912 0=disable, 1=enable */ 2913 uint64_t set32 : 1; /**< Enable SET32 tracing 2914 0=disable, 1=enable */ 2915 uint64_t set16 : 1; /**< Enable SET16 tracing 2916 0=disable, 1=enable */ 2917 uint64_t set8 : 1; /**< Enable SET8 tracing 2918 0=disable, 1=enable */ 2919 uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 2920 0=disable, 1=enable */ 2921 uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 2922 0=disable, 1=enable */ 2923 uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 2924 0=disable, 1=enable */ 2925 uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 2926 0=disable, 1=enable */ 2927 uint64_t reserved_32_35 : 4; 2928 uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 2929 0=disable, 1=enable */ 2930 uint64_t wbl2 : 1; /**< Enable WBL2 tracing 2931 0=disable, 1=enable */ 2932 uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 2933 0=disable, 1=enable */ 2934 uint64_t invl2 : 1; /**< Enable INVL2 tracing 2935 0=disable, 1=enable */ 2936 uint64_t reserved_27_27 : 1; 2937 uint64_t stgl2i : 1; /**< Enable STGL2I tracing 2938 0=disable, 1=enable */ 2939 uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 2940 0=disable, 1=enable */ 2941 uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 2942 0=disable, 1=enable */ 2943 uint64_t fas64 : 1; /**< Enable FAS64 tracing 2944 0=disable, 1=enable */ 2945 uint64_t fas32 : 1; /**< Enable FAS32 tracing 2946 0=disable, 1=enable */ 2947 uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 2948 0=disable, 1=enable */ 2949 uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 2950 0=disable, 1=enable */ 2951 uint64_t reserved_16_19 : 4; 2952 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 2953 0=disable, 1=enable */ 2954 uint64_t iobst : 1; /**< Enable IOBST tracing 2955 0=disable, 1=enable */ 2956 uint64_t reserved_0_13 : 14; 2957#else 2958 uint64_t reserved_0_13 : 14; 2959 uint64_t iobst : 1; 2960 uint64_t iobdma : 1; 2961 uint64_t reserved_16_19 : 4; 2962 uint64_t stfil1 : 1; 2963 uint64_t sttil1 : 1; 2964 uint64_t fas32 : 1; 2965 uint64_t fas64 : 1; 2966 uint64_t wbil2i : 1; 2967 uint64_t ltgl2i : 1; 2968 uint64_t stgl2i : 1; 2969 uint64_t reserved_27_27 : 1; 2970 uint64_t invl2 : 1; 2971 uint64_t wbil2 : 1; 2972 uint64_t wbl2 : 1; 2973 uint64_t lckl2 : 1; 2974 uint64_t reserved_32_35 : 4; 2975 uint64_t iobst8 : 1; 2976 uint64_t iobst16 : 1; 2977 uint64_t iobst32 : 1; 2978 uint64_t iobst64 : 1; 2979 uint64_t set8 : 1; 2980 uint64_t set16 : 1; 2981 uint64_t set32 : 1; 2982 uint64_t set64 : 1; 2983 uint64_t clr8 : 1; 2984 uint64_t clr16 : 1; 2985 uint64_t clr32 : 1; 2986 uint64_t clr64 : 1; 2987 uint64_t incr8 : 1; 2988 uint64_t incr16 : 1; 2989 uint64_t incr32 : 1; 2990 uint64_t incr64 : 1; 2991 uint64_t decr8 : 1; 2992 uint64_t decr16 : 1; 2993 uint64_t decr32 : 1; 2994 uint64_t decr64 : 1; 2995 uint64_t reserved_56_57 : 2; 2996 uint64_t faa32 : 1; 2997 uint64_t faa64 : 1; 2998 uint64_t reserved_60_61 : 2; 2999 uint64_t saa32 : 1; 3000 uint64_t saa64 : 1; 3001#endif 3002 } s; 3003 struct cvmx_trax_trig1_cmd_cn31xx { 3004#ifdef __BIG_ENDIAN_BITFIELD 3005 uint64_t reserved_16_63 : 48; 3006 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 3007 0=disable, 1=enable */ 3008 uint64_t iobst : 1; /**< Enable IOBST tracing 3009 0=disable, 1=enable */ 3010 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 3011 0=disable, 1=enable */ 3012 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 3013 0=disable, 1=enable */ 3014 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 3015 0=disable, 1=enable */ 3016 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 3017 0=disable, 1=enable */ 3018 uint64_t stt : 1; /**< Enable STT tracing 3019 0=disable, 1=enable */ 3020 uint64_t stp : 1; /**< Enable STP tracing 3021 0=disable, 1=enable */ 3022 uint64_t stc : 1; /**< Enable STC tracing 3023 0=disable, 1=enable */ 3024 uint64_t stf : 1; /**< Enable STF tracing 3025 0=disable, 1=enable */ 3026 uint64_t ldt : 1; /**< Enable LDT tracing 3027 0=disable, 1=enable */ 3028 uint64_t ldi : 1; /**< Enable LDI tracing 3029 0=disable, 1=enable */ 3030 uint64_t ldd : 1; /**< Enable LDD tracing 3031 0=disable, 1=enable */ 3032 uint64_t psl1 : 1; /**< Enable PSL1 tracing 3033 0=disable, 1=enable */ 3034 uint64_t pl2 : 1; /**< Enable PL2 tracing 3035 0=disable, 1=enable */ 3036 uint64_t dwb : 1; /**< Enable DWB tracing 3037 0=disable, 1=enable */ 3038#else 3039 uint64_t dwb : 1; 3040 uint64_t pl2 : 1; 3041 uint64_t psl1 : 1; 3042 uint64_t ldd : 1; 3043 uint64_t ldi : 1; 3044 uint64_t ldt : 1; 3045 uint64_t stf : 1; 3046 uint64_t stc : 1; 3047 uint64_t stp : 1; 3048 uint64_t stt : 1; 3049 uint64_t iobld8 : 1; 3050 uint64_t iobld16 : 1; 3051 uint64_t iobld32 : 1; 3052 uint64_t iobld64 : 1; 3053 uint64_t iobst : 1; 3054 uint64_t iobdma : 1; 3055 uint64_t reserved_16_63 : 48; 3056#endif 3057 } cn31xx; 3058 struct cvmx_trax_trig1_cmd_cn31xx cn38xx; 3059 struct cvmx_trax_trig1_cmd_cn31xx cn38xxp2; 3060 struct cvmx_trax_trig1_cmd_cn52xx { 3061#ifdef __BIG_ENDIAN_BITFIELD 3062 uint64_t reserved_17_63 : 47; 3063 uint64_t saa : 1; /**< Enable SAA tracing 3064 0=disable, 1=enable */ 3065 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 3066 0=disable, 1=enable */ 3067 uint64_t iobst : 1; /**< Enable IOBST tracing 3068 0=disable, 1=enable */ 3069 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 3070 0=disable, 1=enable */ 3071 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 3072 0=disable, 1=enable */ 3073 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 3074 0=disable, 1=enable */ 3075 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 3076 0=disable, 1=enable */ 3077 uint64_t stt : 1; /**< Enable STT tracing 3078 0=disable, 1=enable */ 3079 uint64_t stp : 1; /**< Enable STP tracing 3080 0=disable, 1=enable */ 3081 uint64_t stc : 1; /**< Enable STC tracing 3082 0=disable, 1=enable */ 3083 uint64_t stf : 1; /**< Enable STF tracing 3084 0=disable, 1=enable */ 3085 uint64_t ldt : 1; /**< Enable LDT tracing 3086 0=disable, 1=enable */ 3087 uint64_t ldi : 1; /**< Enable LDI tracing 3088 0=disable, 1=enable */ 3089 uint64_t ldd : 1; /**< Enable LDD tracing 3090 0=disable, 1=enable */ 3091 uint64_t psl1 : 1; /**< Enable PSL1 tracing 3092 0=disable, 1=enable */ 3093 uint64_t pl2 : 1; /**< Enable PL2 tracing 3094 0=disable, 1=enable */ 3095 uint64_t dwb : 1; /**< Enable DWB tracing 3096 0=disable, 1=enable */ 3097#else 3098 uint64_t dwb : 1; 3099 uint64_t pl2 : 1; 3100 uint64_t psl1 : 1; 3101 uint64_t ldd : 1; 3102 uint64_t ldi : 1; 3103 uint64_t ldt : 1; 3104 uint64_t stf : 1; 3105 uint64_t stc : 1; 3106 uint64_t stp : 1; 3107 uint64_t stt : 1; 3108 uint64_t iobld8 : 1; 3109 uint64_t iobld16 : 1; 3110 uint64_t iobld32 : 1; 3111 uint64_t iobld64 : 1; 3112 uint64_t iobst : 1; 3113 uint64_t iobdma : 1; 3114 uint64_t saa : 1; 3115 uint64_t reserved_17_63 : 47; 3116#endif 3117 } cn52xx; 3118 struct cvmx_trax_trig1_cmd_cn52xx cn52xxp1; 3119 struct cvmx_trax_trig1_cmd_cn52xx cn56xx; 3120 struct cvmx_trax_trig1_cmd_cn52xx cn56xxp1; 3121 struct cvmx_trax_trig1_cmd_cn52xx cn58xx; 3122 struct cvmx_trax_trig1_cmd_cn52xx cn58xxp1; 3123 struct cvmx_trax_trig1_cmd_cn61xx { 3124#ifdef __BIG_ENDIAN_BITFIELD 3125 uint64_t saa64 : 1; /**< Enable SAA64 tracing 3126 0=disable, 1=enable */ 3127 uint64_t saa32 : 1; /**< Enable SAA32 tracing 3128 0=disable, 1=enable */ 3129 uint64_t reserved_60_61 : 2; 3130 uint64_t faa64 : 1; /**< Enable FAA64 tracing 3131 0=disable, 1=enable */ 3132 uint64_t faa32 : 1; /**< Enable FAA32 tracing 3133 0=disable, 1=enable */ 3134 uint64_t reserved_56_57 : 2; 3135 uint64_t decr64 : 1; /**< Enable DECR64 tracing 3136 0=disable, 1=enable */ 3137 uint64_t decr32 : 1; /**< Enable DECR32 tracing 3138 0=disable, 1=enable */ 3139 uint64_t decr16 : 1; /**< Enable DECR16 tracing 3140 0=disable, 1=enable */ 3141 uint64_t decr8 : 1; /**< Enable DECR8 tracing 3142 0=disable, 1=enable */ 3143 uint64_t incr64 : 1; /**< Enable INCR64 tracing 3144 0=disable, 1=enable */ 3145 uint64_t incr32 : 1; /**< Enable INCR32 tracing 3146 0=disable, 1=enable */ 3147 uint64_t incr16 : 1; /**< Enable INCR16 tracing 3148 0=disable, 1=enable */ 3149 uint64_t incr8 : 1; /**< Enable INCR8 tracing 3150 0=disable, 1=enable */ 3151 uint64_t clr64 : 1; /**< Enable CLR64 tracing 3152 0=disable, 1=enable */ 3153 uint64_t clr32 : 1; /**< Enable CLR32 tracing 3154 0=disable, 1=enable */ 3155 uint64_t clr16 : 1; /**< Enable CLR16 tracing 3156 0=disable, 1=enable */ 3157 uint64_t clr8 : 1; /**< Enable CLR8 tracing 3158 0=disable, 1=enable */ 3159 uint64_t set64 : 1; /**< Enable SET64 tracing 3160 0=disable, 1=enable */ 3161 uint64_t set32 : 1; /**< Enable SET32 tracing 3162 0=disable, 1=enable */ 3163 uint64_t set16 : 1; /**< Enable SET16 tracing 3164 0=disable, 1=enable */ 3165 uint64_t set8 : 1; /**< Enable SET8 tracing 3166 0=disable, 1=enable */ 3167 uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 3168 0=disable, 1=enable */ 3169 uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 3170 0=disable, 1=enable */ 3171 uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 3172 0=disable, 1=enable */ 3173 uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 3174 0=disable, 1=enable */ 3175 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 3176 0=disable, 1=enable */ 3177 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 3178 0=disable, 1=enable */ 3179 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 3180 0=disable, 1=enable */ 3181 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 3182 0=disable, 1=enable */ 3183 uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 3184 0=disable, 1=enable */ 3185 uint64_t wbl2 : 1; /**< Enable WBL2 tracing 3186 0=disable, 1=enable */ 3187 uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 3188 0=disable, 1=enable */ 3189 uint64_t invl2 : 1; /**< Enable INVL2 tracing 3190 0=disable, 1=enable */ 3191 uint64_t reserved_27_27 : 1; 3192 uint64_t stgl2i : 1; /**< Enable STGL2I tracing 3193 0=disable, 1=enable */ 3194 uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 3195 0=disable, 1=enable */ 3196 uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 3197 0=disable, 1=enable */ 3198 uint64_t fas64 : 1; /**< Enable FAS64 tracing 3199 0=disable, 1=enable */ 3200 uint64_t fas32 : 1; /**< Enable FAS32 tracing 3201 0=disable, 1=enable */ 3202 uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 3203 0=disable, 1=enable */ 3204 uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 3205 0=disable, 1=enable */ 3206 uint64_t stc : 1; /**< Enable STC tracing 3207 0=disable, 1=enable */ 3208 uint64_t stp : 1; /**< Enable STP tracing 3209 0=disable, 1=enable */ 3210 uint64_t stt : 1; /**< Enable STT tracing 3211 0=disable, 1=enable */ 3212 uint64_t stf : 1; /**< Enable STF tracing 3213 0=disable, 1=enable */ 3214 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 3215 0=disable, 1=enable */ 3216 uint64_t reserved_10_14 : 5; 3217 uint64_t psl1 : 1; /**< Enable PSL1 tracing 3218 0=disable, 1=enable */ 3219 uint64_t ldd : 1; /**< Enable LDD tracing 3220 0=disable, 1=enable */ 3221 uint64_t reserved_6_7 : 2; 3222 uint64_t dwb : 1; /**< Enable DWB tracing 3223 0=disable, 1=enable */ 3224 uint64_t rpl2 : 1; /**< Enable RPL2 tracing 3225 0=disable, 1=enable */ 3226 uint64_t pl2 : 1; /**< Enable PL2 tracing 3227 0=disable, 1=enable */ 3228 uint64_t ldi : 1; /**< Enable LDI tracing 3229 0=disable, 1=enable */ 3230 uint64_t ldt : 1; /**< Enable LDT tracing 3231 0=disable, 1=enable */ 3232 uint64_t nop : 1; /**< Enable NOP tracing 3233 0=disable, 1=enable */ 3234#else 3235 uint64_t nop : 1; 3236 uint64_t ldt : 1; 3237 uint64_t ldi : 1; 3238 uint64_t pl2 : 1; 3239 uint64_t rpl2 : 1; 3240 uint64_t dwb : 1; 3241 uint64_t reserved_6_7 : 2; 3242 uint64_t ldd : 1; 3243 uint64_t psl1 : 1; 3244 uint64_t reserved_10_14 : 5; 3245 uint64_t iobdma : 1; 3246 uint64_t stf : 1; 3247 uint64_t stt : 1; 3248 uint64_t stp : 1; 3249 uint64_t stc : 1; 3250 uint64_t stfil1 : 1; 3251 uint64_t sttil1 : 1; 3252 uint64_t fas32 : 1; 3253 uint64_t fas64 : 1; 3254 uint64_t wbil2i : 1; 3255 uint64_t ltgl2i : 1; 3256 uint64_t stgl2i : 1; 3257 uint64_t reserved_27_27 : 1; 3258 uint64_t invl2 : 1; 3259 uint64_t wbil2 : 1; 3260 uint64_t wbl2 : 1; 3261 uint64_t lckl2 : 1; 3262 uint64_t iobld8 : 1; 3263 uint64_t iobld16 : 1; 3264 uint64_t iobld32 : 1; 3265 uint64_t iobld64 : 1; 3266 uint64_t iobst8 : 1; 3267 uint64_t iobst16 : 1; 3268 uint64_t iobst32 : 1; 3269 uint64_t iobst64 : 1; 3270 uint64_t set8 : 1; 3271 uint64_t set16 : 1; 3272 uint64_t set32 : 1; 3273 uint64_t set64 : 1; 3274 uint64_t clr8 : 1; 3275 uint64_t clr16 : 1; 3276 uint64_t clr32 : 1; 3277 uint64_t clr64 : 1; 3278 uint64_t incr8 : 1; 3279 uint64_t incr16 : 1; 3280 uint64_t incr32 : 1; 3281 uint64_t incr64 : 1; 3282 uint64_t decr8 : 1; 3283 uint64_t decr16 : 1; 3284 uint64_t decr32 : 1; 3285 uint64_t decr64 : 1; 3286 uint64_t reserved_56_57 : 2; 3287 uint64_t faa32 : 1; 3288 uint64_t faa64 : 1; 3289 uint64_t reserved_60_61 : 2; 3290 uint64_t saa32 : 1; 3291 uint64_t saa64 : 1; 3292#endif 3293 } cn61xx; 3294 struct cvmx_trax_trig1_cmd_cn61xx cn63xx; 3295 struct cvmx_trax_trig1_cmd_cn61xx cn63xxp1; 3296 struct cvmx_trax_trig1_cmd_cn61xx cn66xx; 3297 struct cvmx_trax_trig1_cmd_cn61xx cn68xx; 3298 struct cvmx_trax_trig1_cmd_cn61xx cn68xxp1; 3299 struct cvmx_trax_trig1_cmd_cn61xx cnf71xx; 3300}; 3301typedef union cvmx_trax_trig1_cmd cvmx_trax_trig1_cmd_t; 3302 3303/** 3304 * cvmx_tra#_trig1_did 3305 * 3306 * TRA_TRIG1_DID = Trace Buffer Filter DestinationId Mask 3307 * 3308 * Description: 3309 */ 3310union cvmx_trax_trig1_did { 3311 uint64_t u64; 3312 struct cvmx_trax_trig1_did_s { 3313#ifdef __BIG_ENDIAN_BITFIELD 3314 uint64_t reserved_13_63 : 51; 3315 uint64_t pow : 1; /**< Enable triggering on requests to POW 3316 (get work, add work, status/memory/index 3317 loads, NULLRd loads, CSR's) */ 3318 uint64_t reserved_9_11 : 3; 3319 uint64_t rng : 1; /**< Enable triggering on requests to RNG 3320 (loads/IOBDMA's are legal) */ 3321 uint64_t zip : 1; /**< Enable triggering on requests to ZIP 3322 (doorbell stores are legal) */ 3323 uint64_t dfa : 1; /**< Enable triggering on requests to DFA 3324 (CSR's and operations are legal) */ 3325 uint64_t fpa : 1; /**< Enable triggering on requests to FPA 3326 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 3327 uint64_t key : 1; /**< Enable triggering on requests to KEY memory 3328 (loads/IOBDMA's/stores are legal) */ 3329 uint64_t reserved_3_3 : 1; 3330 uint64_t illegal3 : 2; /**< Illegal destinations */ 3331 uint64_t mio : 1; /**< Enable triggering on MIO accesses 3332 (CIU and GPIO CSR's, boot bus accesses) */ 3333#else 3334 uint64_t mio : 1; 3335 uint64_t illegal3 : 2; 3336 uint64_t reserved_3_3 : 1; 3337 uint64_t key : 1; 3338 uint64_t fpa : 1; 3339 uint64_t dfa : 1; 3340 uint64_t zip : 1; 3341 uint64_t rng : 1; 3342 uint64_t reserved_9_11 : 3; 3343 uint64_t pow : 1; 3344 uint64_t reserved_13_63 : 51; 3345#endif 3346 } s; 3347 struct cvmx_trax_trig1_did_cn31xx { 3348#ifdef __BIG_ENDIAN_BITFIELD 3349 uint64_t reserved_32_63 : 32; 3350 uint64_t illegal : 19; /**< Illegal destinations */ 3351 uint64_t pow : 1; /**< Enable triggering on requests to POW 3352 (get work, add work, status/memory/index 3353 loads, NULLRd loads, CSR's) */ 3354 uint64_t illegal2 : 3; /**< Illegal destinations */ 3355 uint64_t rng : 1; /**< Enable triggering on requests to RNG 3356 (loads/IOBDMA's are legal) */ 3357 uint64_t zip : 1; /**< Enable triggering on requests to ZIP 3358 (doorbell stores are legal) */ 3359 uint64_t dfa : 1; /**< Enable triggering on requests to DFA 3360 (CSR's and operations are legal) */ 3361 uint64_t fpa : 1; /**< Enable triggering on requests to FPA 3362 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 3363 uint64_t key : 1; /**< Enable triggering on requests to KEY memory 3364 (loads/IOBDMA's/stores are legal) */ 3365 uint64_t pci : 1; /**< Enable triggering on requests to PCI and RSL-type 3366 CSR's (RSL CSR's, PCI bus operations, PCI 3367 CSR's) */ 3368 uint64_t illegal3 : 2; /**< Illegal destinations */ 3369 uint64_t mio : 1; /**< Enable triggering on CIU and GPIO CSR's */ 3370#else 3371 uint64_t mio : 1; 3372 uint64_t illegal3 : 2; 3373 uint64_t pci : 1; 3374 uint64_t key : 1; 3375 uint64_t fpa : 1; 3376 uint64_t dfa : 1; 3377 uint64_t zip : 1; 3378 uint64_t rng : 1; 3379 uint64_t illegal2 : 3; 3380 uint64_t pow : 1; 3381 uint64_t illegal : 19; 3382 uint64_t reserved_32_63 : 32; 3383#endif 3384 } cn31xx; 3385 struct cvmx_trax_trig1_did_cn31xx cn38xx; 3386 struct cvmx_trax_trig1_did_cn31xx cn38xxp2; 3387 struct cvmx_trax_trig1_did_cn31xx cn52xx; 3388 struct cvmx_trax_trig1_did_cn31xx cn52xxp1; 3389 struct cvmx_trax_trig1_did_cn31xx cn56xx; 3390 struct cvmx_trax_trig1_did_cn31xx cn56xxp1; 3391 struct cvmx_trax_trig1_did_cn31xx cn58xx; 3392 struct cvmx_trax_trig1_did_cn31xx cn58xxp1; 3393 struct cvmx_trax_trig1_did_cn61xx { 3394#ifdef __BIG_ENDIAN_BITFIELD 3395 uint64_t reserved_32_63 : 32; 3396 uint64_t illegal5 : 1; /**< Illegal destinations */ 3397 uint64_t fau : 1; /**< Enable triggering on FAU accesses */ 3398 uint64_t illegal4 : 2; /**< Illegal destinations */ 3399 uint64_t dpi : 1; /**< Enable triggering on DPI accesses 3400 (DPI NCB CSRs) */ 3401 uint64_t illegal : 12; /**< Illegal destinations */ 3402 uint64_t rad : 1; /**< Enable triggering on RAD accesses 3403 (doorbells) */ 3404 uint64_t usb0 : 1; /**< Enable triggering on USB0 accesses 3405 (UAHC0 EHCI and OHCI NCB CSRs) */ 3406 uint64_t pow : 1; /**< Enable triggering on requests to POW 3407 (get work, add work, status/memory/index 3408 loads, NULLRd loads, CSR's) */ 3409 uint64_t illegal2 : 1; /**< Illegal destination */ 3410 uint64_t pko : 1; /**< Enable triggering on PKO accesses 3411 (doorbells) */ 3412 uint64_t ipd : 1; /**< Enable triggering on IPD CSR accesses 3413 (IPD CSRs) */ 3414 uint64_t rng : 1; /**< Enable triggering on requests to RNG 3415 (loads/IOBDMA's are legal) */ 3416 uint64_t zip : 1; /**< Enable triggering on requests to ZIP 3417 (doorbell stores are legal) */ 3418 uint64_t dfa : 1; /**< Enable triggering on requests to DFA 3419 (CSR's and operations are legal) */ 3420 uint64_t fpa : 1; /**< Enable triggering on requests to FPA 3421 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 3422 uint64_t key : 1; /**< Enable triggering on requests to KEY memory 3423 (loads/IOBDMA's/stores are legal) */ 3424 uint64_t sli : 1; /**< Enable triggering on requests to SLI and RSL-type 3425 CSR's (RSL CSR's, PCI/sRIO bus operations, SLI 3426 CSR's) */ 3427 uint64_t illegal3 : 2; /**< Illegal destinations */ 3428 uint64_t mio : 1; /**< Enable triggering on MIO accesses 3429 (CIU and GPIO CSR's, boot bus accesses) */ 3430#else 3431 uint64_t mio : 1; 3432 uint64_t illegal3 : 2; 3433 uint64_t sli : 1; 3434 uint64_t key : 1; 3435 uint64_t fpa : 1; 3436 uint64_t dfa : 1; 3437 uint64_t zip : 1; 3438 uint64_t rng : 1; 3439 uint64_t ipd : 1; 3440 uint64_t pko : 1; 3441 uint64_t illegal2 : 1; 3442 uint64_t pow : 1; 3443 uint64_t usb0 : 1; 3444 uint64_t rad : 1; 3445 uint64_t illegal : 12; 3446 uint64_t dpi : 1; 3447 uint64_t illegal4 : 2; 3448 uint64_t fau : 1; 3449 uint64_t illegal5 : 1; 3450 uint64_t reserved_32_63 : 32; 3451#endif 3452 } cn61xx; 3453 struct cvmx_trax_trig1_did_cn61xx cn63xx; 3454 struct cvmx_trax_trig1_did_cn61xx cn63xxp1; 3455 struct cvmx_trax_trig1_did_cn61xx cn66xx; 3456 struct cvmx_trax_trig1_did_cn61xx cn68xx; 3457 struct cvmx_trax_trig1_did_cn61xx cn68xxp1; 3458 struct cvmx_trax_trig1_did_cn61xx cnf71xx; 3459}; 3460typedef union cvmx_trax_trig1_did cvmx_trax_trig1_did_t; 3461 3462/** 3463 * cvmx_tra#_trig1_sid 3464 * 3465 * TRA_TRIG1_SID = Trace Buffer Filter SourceId Mask 3466 * 3467 * Description: 3468 */ 3469union cvmx_trax_trig1_sid { 3470 uint64_t u64; 3471 struct cvmx_trax_trig1_sid_s { 3472#ifdef __BIG_ENDIAN_BITFIELD 3473 uint64_t reserved_20_63 : 44; 3474 uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 3475 uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 3476 PCI,ZIP,POW, and PKO (writes) */ 3477 uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 3478 uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 3479 uint64_t pp : 16; /**< Enable trigering from PP[N] with matching SourceID 3480 0=disable, 1=enable per bit N where 0<=N<=3 */ 3481#else 3482 uint64_t pp : 16; 3483 uint64_t pki : 1; 3484 uint64_t pko : 1; 3485 uint64_t iobreq : 1; 3486 uint64_t dwb : 1; 3487 uint64_t reserved_20_63 : 44; 3488#endif 3489 } s; 3490 struct cvmx_trax_trig1_sid_s cn31xx; 3491 struct cvmx_trax_trig1_sid_s cn38xx; 3492 struct cvmx_trax_trig1_sid_s cn38xxp2; 3493 struct cvmx_trax_trig1_sid_s cn52xx; 3494 struct cvmx_trax_trig1_sid_s cn52xxp1; 3495 struct cvmx_trax_trig1_sid_s cn56xx; 3496 struct cvmx_trax_trig1_sid_s cn56xxp1; 3497 struct cvmx_trax_trig1_sid_s cn58xx; 3498 struct cvmx_trax_trig1_sid_s cn58xxp1; 3499 struct cvmx_trax_trig1_sid_cn61xx { 3500#ifdef __BIG_ENDIAN_BITFIELD 3501 uint64_t reserved_20_63 : 44; 3502 uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 3503 uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 3504 PCI,ZIP,POW, and PKO (writes) */ 3505 uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 3506 uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 3507 uint64_t reserved_4_15 : 12; 3508 uint64_t pp : 4; /**< Enable trigering from PP[N] with matching SourceID 3509 0=disable, 1=enable per bit N where 0<=N<=3 */ 3510#else 3511 uint64_t pp : 4; 3512 uint64_t reserved_4_15 : 12; 3513 uint64_t pki : 1; 3514 uint64_t pko : 1; 3515 uint64_t iobreq : 1; 3516 uint64_t dwb : 1; 3517 uint64_t reserved_20_63 : 44; 3518#endif 3519 } cn61xx; 3520 struct cvmx_trax_trig1_sid_cn63xx { 3521#ifdef __BIG_ENDIAN_BITFIELD 3522 uint64_t reserved_20_63 : 44; 3523 uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 3524 uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 3525 PCI,ZIP,POW, and PKO (writes) */ 3526 uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 3527 uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 3528 uint64_t reserved_8_15 : 8; 3529 uint64_t pp : 8; /**< Enable trigering from PP[N] with matching SourceID 3530 0=disable, 1=enableper bit N where 0<=N<=15 */ 3531#else 3532 uint64_t pp : 8; 3533 uint64_t reserved_8_15 : 8; 3534 uint64_t pki : 1; 3535 uint64_t pko : 1; 3536 uint64_t iobreq : 1; 3537 uint64_t dwb : 1; 3538 uint64_t reserved_20_63 : 44; 3539#endif 3540 } cn63xx; 3541 struct cvmx_trax_trig1_sid_cn63xxp1 { 3542#ifdef __BIG_ENDIAN_BITFIELD 3543 uint64_t reserved_20_63 : 44; 3544 uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 3545 uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 3546 PCI,ZIP,POW, and PKO (writes) */ 3547 uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 3548 uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 3549 uint64_t reserved_6_15 : 10; 3550 uint64_t pp : 6; /**< Enable trigering from PP[N] with matching SourceID 3551 0=disable, 1=enable per bit N where 0<=N<=5 */ 3552#else 3553 uint64_t pp : 6; 3554 uint64_t reserved_6_15 : 10; 3555 uint64_t pki : 1; 3556 uint64_t pko : 1; 3557 uint64_t iobreq : 1; 3558 uint64_t dwb : 1; 3559 uint64_t reserved_20_63 : 44; 3560#endif 3561 } cn63xxp1; 3562 struct cvmx_trax_trig1_sid_cn66xx { 3563#ifdef __BIG_ENDIAN_BITFIELD 3564 uint64_t reserved_20_63 : 44; 3565 uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 3566 uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 3567 PCI,ZIP,POW, and PKO (writes) */ 3568 uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 3569 uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 3570 uint64_t reserved_10_15 : 6; 3571 uint64_t pp : 10; /**< Enable trigering from PP[N] with matching SourceID 3572 0=disable, 1=enableper bit N where 0<=N<=15 */ 3573#else 3574 uint64_t pp : 10; 3575 uint64_t reserved_10_15 : 6; 3576 uint64_t pki : 1; 3577 uint64_t pko : 1; 3578 uint64_t iobreq : 1; 3579 uint64_t dwb : 1; 3580 uint64_t reserved_20_63 : 44; 3581#endif 3582 } cn66xx; 3583 struct cvmx_trax_trig1_sid_cn63xx cn68xx; 3584 struct cvmx_trax_trig1_sid_cn63xx cn68xxp1; 3585 struct cvmx_trax_trig1_sid_cn61xx cnf71xx; 3586}; 3587typedef union cvmx_trax_trig1_sid cvmx_trax_trig1_sid_t; 3588 3589#include "cvmx-tra-defs.h" 3590#endif 3591