cvmx-tim-defs.h revision 215976
1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-tim-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon tim. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_TIM_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_TIM_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#define CVMX_TIM_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180058001100ull)) 56215976Sjmallett#define CVMX_TIM_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180058001108ull)) 57215976Sjmallett#define CVMX_TIM_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180058001110ull)) 58215976Sjmallett#define CVMX_TIM_MEM_RING0 (CVMX_ADD_IO_SEG(0x0001180058001000ull)) 59215976Sjmallett#define CVMX_TIM_MEM_RING1 (CVMX_ADD_IO_SEG(0x0001180058001008ull)) 60215976Sjmallett#define CVMX_TIM_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180058000080ull)) 61215976Sjmallett#define CVMX_TIM_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180058000088ull)) 62215976Sjmallett#define CVMX_TIM_REG_FLAGS (CVMX_ADD_IO_SEG(0x0001180058000000ull)) 63215976Sjmallett#define CVMX_TIM_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180058000090ull)) 64215976Sjmallett#define CVMX_TIM_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180058000008ull)) 65215976Sjmallett 66215976Sjmallett/** 67215976Sjmallett * cvmx_tim_mem_debug0 68215976Sjmallett * 69215976Sjmallett * Notes: 70215976Sjmallett * Internal per-ring state intended for debug use only - tim.ctl[47:0] 71215976Sjmallett * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any 72215976Sjmallett * CSR read operations to this address can be performed. 73215976Sjmallett */ 74215976Sjmallettunion cvmx_tim_mem_debug0 75215976Sjmallett{ 76215976Sjmallett uint64_t u64; 77215976Sjmallett struct cvmx_tim_mem_debug0_s 78215976Sjmallett { 79215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 80215976Sjmallett uint64_t reserved_48_63 : 16; 81215976Sjmallett uint64_t ena : 1; /**< Ring timer enable */ 82215976Sjmallett uint64_t reserved_46_46 : 1; 83215976Sjmallett uint64_t count : 22; /**< Time offset for the ring 84215976Sjmallett Set to INTERVAL and counts down by 1 every 1024 85215976Sjmallett cycles when ENA==1. The HW forces a bucket 86215976Sjmallett traversal (and resets COUNT to INTERVAL) whenever 87215976Sjmallett the decrement would cause COUNT to go negative. 88215976Sjmallett COUNT is unpredictable whenever ENA==0. 89215976Sjmallett COUNT is reset to INTERVAL whenever TIM_MEM_RING1 90215976Sjmallett is written for the ring. */ 91215976Sjmallett uint64_t reserved_22_23 : 2; 92215976Sjmallett uint64_t interval : 22; /**< Timer interval - 1 */ 93215976Sjmallett#else 94215976Sjmallett uint64_t interval : 22; 95215976Sjmallett uint64_t reserved_22_23 : 2; 96215976Sjmallett uint64_t count : 22; 97215976Sjmallett uint64_t reserved_46_46 : 1; 98215976Sjmallett uint64_t ena : 1; 99215976Sjmallett uint64_t reserved_48_63 : 16; 100215976Sjmallett#endif 101215976Sjmallett } s; 102215976Sjmallett struct cvmx_tim_mem_debug0_s cn30xx; 103215976Sjmallett struct cvmx_tim_mem_debug0_s cn31xx; 104215976Sjmallett struct cvmx_tim_mem_debug0_s cn38xx; 105215976Sjmallett struct cvmx_tim_mem_debug0_s cn38xxp2; 106215976Sjmallett struct cvmx_tim_mem_debug0_s cn50xx; 107215976Sjmallett struct cvmx_tim_mem_debug0_s cn52xx; 108215976Sjmallett struct cvmx_tim_mem_debug0_s cn52xxp1; 109215976Sjmallett struct cvmx_tim_mem_debug0_s cn56xx; 110215976Sjmallett struct cvmx_tim_mem_debug0_s cn56xxp1; 111215976Sjmallett struct cvmx_tim_mem_debug0_s cn58xx; 112215976Sjmallett struct cvmx_tim_mem_debug0_s cn58xxp1; 113215976Sjmallett struct cvmx_tim_mem_debug0_s cn63xx; 114215976Sjmallett struct cvmx_tim_mem_debug0_s cn63xxp1; 115215976Sjmallett}; 116215976Sjmalletttypedef union cvmx_tim_mem_debug0 cvmx_tim_mem_debug0_t; 117215976Sjmallett 118215976Sjmallett/** 119215976Sjmallett * cvmx_tim_mem_debug1 120215976Sjmallett * 121215976Sjmallett * Notes: 122215976Sjmallett * Internal per-ring state intended for debug use only - tim.sta[63:0] 123215976Sjmallett * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any 124215976Sjmallett * CSR read operations to this address can be performed. 125215976Sjmallett */ 126215976Sjmallettunion cvmx_tim_mem_debug1 127215976Sjmallett{ 128215976Sjmallett uint64_t u64; 129215976Sjmallett struct cvmx_tim_mem_debug1_s 130215976Sjmallett { 131215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 132215976Sjmallett uint64_t bucket : 13; /**< Current bucket[12:0] 133215976Sjmallett Reset to 0 whenever TIM_MEM_RING0 is written for 134215976Sjmallett the ring. Incremented (modulo BSIZE) once per 135215976Sjmallett bucket traversal. 136215976Sjmallett See TIM_MEM_DEBUG2[BUCKET]. */ 137215976Sjmallett uint64_t base : 31; /**< Pointer[35:5] to bucket[0] */ 138215976Sjmallett uint64_t bsize : 20; /**< Number of buckets - 1 */ 139215976Sjmallett#else 140215976Sjmallett uint64_t bsize : 20; 141215976Sjmallett uint64_t base : 31; 142215976Sjmallett uint64_t bucket : 13; 143215976Sjmallett#endif 144215976Sjmallett } s; 145215976Sjmallett struct cvmx_tim_mem_debug1_s cn30xx; 146215976Sjmallett struct cvmx_tim_mem_debug1_s cn31xx; 147215976Sjmallett struct cvmx_tim_mem_debug1_s cn38xx; 148215976Sjmallett struct cvmx_tim_mem_debug1_s cn38xxp2; 149215976Sjmallett struct cvmx_tim_mem_debug1_s cn50xx; 150215976Sjmallett struct cvmx_tim_mem_debug1_s cn52xx; 151215976Sjmallett struct cvmx_tim_mem_debug1_s cn52xxp1; 152215976Sjmallett struct cvmx_tim_mem_debug1_s cn56xx; 153215976Sjmallett struct cvmx_tim_mem_debug1_s cn56xxp1; 154215976Sjmallett struct cvmx_tim_mem_debug1_s cn58xx; 155215976Sjmallett struct cvmx_tim_mem_debug1_s cn58xxp1; 156215976Sjmallett struct cvmx_tim_mem_debug1_s cn63xx; 157215976Sjmallett struct cvmx_tim_mem_debug1_s cn63xxp1; 158215976Sjmallett}; 159215976Sjmalletttypedef union cvmx_tim_mem_debug1 cvmx_tim_mem_debug1_t; 160215976Sjmallett 161215976Sjmallett/** 162215976Sjmallett * cvmx_tim_mem_debug2 163215976Sjmallett * 164215976Sjmallett * Notes: 165215976Sjmallett * Internal per-ring state intended for debug use only - tim.sta[95:64] 166215976Sjmallett * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any 167215976Sjmallett * CSR read operations to this address can be performed. 168215976Sjmallett */ 169215976Sjmallettunion cvmx_tim_mem_debug2 170215976Sjmallett{ 171215976Sjmallett uint64_t u64; 172215976Sjmallett struct cvmx_tim_mem_debug2_s 173215976Sjmallett { 174215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 175215976Sjmallett uint64_t reserved_24_63 : 40; 176215976Sjmallett uint64_t cpool : 3; /**< Free list used to free chunks */ 177215976Sjmallett uint64_t csize : 13; /**< Number of words per chunk */ 178215976Sjmallett uint64_t reserved_7_7 : 1; 179215976Sjmallett uint64_t bucket : 7; /**< Current bucket[19:13] 180215976Sjmallett See TIM_MEM_DEBUG1[BUCKET]. */ 181215976Sjmallett#else 182215976Sjmallett uint64_t bucket : 7; 183215976Sjmallett uint64_t reserved_7_7 : 1; 184215976Sjmallett uint64_t csize : 13; 185215976Sjmallett uint64_t cpool : 3; 186215976Sjmallett uint64_t reserved_24_63 : 40; 187215976Sjmallett#endif 188215976Sjmallett } s; 189215976Sjmallett struct cvmx_tim_mem_debug2_s cn30xx; 190215976Sjmallett struct cvmx_tim_mem_debug2_s cn31xx; 191215976Sjmallett struct cvmx_tim_mem_debug2_s cn38xx; 192215976Sjmallett struct cvmx_tim_mem_debug2_s cn38xxp2; 193215976Sjmallett struct cvmx_tim_mem_debug2_s cn50xx; 194215976Sjmallett struct cvmx_tim_mem_debug2_s cn52xx; 195215976Sjmallett struct cvmx_tim_mem_debug2_s cn52xxp1; 196215976Sjmallett struct cvmx_tim_mem_debug2_s cn56xx; 197215976Sjmallett struct cvmx_tim_mem_debug2_s cn56xxp1; 198215976Sjmallett struct cvmx_tim_mem_debug2_s cn58xx; 199215976Sjmallett struct cvmx_tim_mem_debug2_s cn58xxp1; 200215976Sjmallett struct cvmx_tim_mem_debug2_s cn63xx; 201215976Sjmallett struct cvmx_tim_mem_debug2_s cn63xxp1; 202215976Sjmallett}; 203215976Sjmalletttypedef union cvmx_tim_mem_debug2 cvmx_tim_mem_debug2_t; 204215976Sjmallett 205215976Sjmallett/** 206215976Sjmallett * cvmx_tim_mem_ring0 207215976Sjmallett * 208215976Sjmallett * Notes: 209215976Sjmallett * TIM_MEM_RING0 must not be written for a ring when TIM_MEM_RING1[ENA] is set for the ring. 210215976Sjmallett * Every write to TIM_MEM_RING0 clears the current bucket for the ring. (The current bucket is 211215976Sjmallett * readable via TIM_MEM_DEBUG2[BUCKET],TIM_MEM_DEBUG1[BUCKET].) 212215976Sjmallett * BASE is a 32-byte aligned pointer[35:0]. Only pointer[35:5] are stored because pointer[4:0] = 0. 213215976Sjmallett * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any 214215976Sjmallett * CSR read operations to this address can be performed. 215215976Sjmallett */ 216215976Sjmallettunion cvmx_tim_mem_ring0 217215976Sjmallett{ 218215976Sjmallett uint64_t u64; 219215976Sjmallett struct cvmx_tim_mem_ring0_s 220215976Sjmallett { 221215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 222215976Sjmallett uint64_t reserved_55_63 : 9; 223215976Sjmallett uint64_t first_bucket : 31; /**< Pointer[35:5] to bucket[0] */ 224215976Sjmallett uint64_t num_buckets : 20; /**< Number of buckets - 1 */ 225215976Sjmallett uint64_t ring : 4; /**< Ring ID */ 226215976Sjmallett#else 227215976Sjmallett uint64_t ring : 4; 228215976Sjmallett uint64_t num_buckets : 20; 229215976Sjmallett uint64_t first_bucket : 31; 230215976Sjmallett uint64_t reserved_55_63 : 9; 231215976Sjmallett#endif 232215976Sjmallett } s; 233215976Sjmallett struct cvmx_tim_mem_ring0_s cn30xx; 234215976Sjmallett struct cvmx_tim_mem_ring0_s cn31xx; 235215976Sjmallett struct cvmx_tim_mem_ring0_s cn38xx; 236215976Sjmallett struct cvmx_tim_mem_ring0_s cn38xxp2; 237215976Sjmallett struct cvmx_tim_mem_ring0_s cn50xx; 238215976Sjmallett struct cvmx_tim_mem_ring0_s cn52xx; 239215976Sjmallett struct cvmx_tim_mem_ring0_s cn52xxp1; 240215976Sjmallett struct cvmx_tim_mem_ring0_s cn56xx; 241215976Sjmallett struct cvmx_tim_mem_ring0_s cn56xxp1; 242215976Sjmallett struct cvmx_tim_mem_ring0_s cn58xx; 243215976Sjmallett struct cvmx_tim_mem_ring0_s cn58xxp1; 244215976Sjmallett struct cvmx_tim_mem_ring0_s cn63xx; 245215976Sjmallett struct cvmx_tim_mem_ring0_s cn63xxp1; 246215976Sjmallett}; 247215976Sjmalletttypedef union cvmx_tim_mem_ring0 cvmx_tim_mem_ring0_t; 248215976Sjmallett 249215976Sjmallett/** 250215976Sjmallett * cvmx_tim_mem_ring1 251215976Sjmallett * 252215976Sjmallett * Notes: 253215976Sjmallett * After a 1->0 transition on ENA, the HW will still complete a bucket traversal for the ring 254215976Sjmallett * if it was pending or active prior to the transition. (SW must delay to ensure the completion 255215976Sjmallett * of the traversal before reprogramming the ring.) 256215976Sjmallett * Every write to TIM_MEM_RING1 resets the current time offset for the ring to the INTERVAL value. 257215976Sjmallett * (The current time offset for the ring is readable via TIM_MEM_DEBUG0[COUNT].) 258215976Sjmallett * CSIZE must be at least 16. It is illegal to program CSIZE to a value that is less than 16. 259215976Sjmallett * This CSR is a memory of 16 entries, and thus, the TIM_REG_READ_IDX CSR must be written before any 260215976Sjmallett * CSR read operations to this address can be performed. 261215976Sjmallett */ 262215976Sjmallettunion cvmx_tim_mem_ring1 263215976Sjmallett{ 264215976Sjmallett uint64_t u64; 265215976Sjmallett struct cvmx_tim_mem_ring1_s 266215976Sjmallett { 267215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 268215976Sjmallett uint64_t reserved_43_63 : 21; 269215976Sjmallett uint64_t enable : 1; /**< Ring timer enable 270215976Sjmallett When clear, the ring is disabled and TIM 271215976Sjmallett will not traverse any new buckets for the ring. */ 272215976Sjmallett uint64_t pool : 3; /**< Free list used to free chunks */ 273215976Sjmallett uint64_t words_per_chunk : 13; /**< Number of words per chunk */ 274215976Sjmallett uint64_t interval : 22; /**< Timer interval - 1, measured in 1024 cycle ticks */ 275215976Sjmallett uint64_t ring : 4; /**< Ring ID */ 276215976Sjmallett#else 277215976Sjmallett uint64_t ring : 4; 278215976Sjmallett uint64_t interval : 22; 279215976Sjmallett uint64_t words_per_chunk : 13; 280215976Sjmallett uint64_t pool : 3; 281215976Sjmallett uint64_t enable : 1; 282215976Sjmallett uint64_t reserved_43_63 : 21; 283215976Sjmallett#endif 284215976Sjmallett } s; 285215976Sjmallett struct cvmx_tim_mem_ring1_s cn30xx; 286215976Sjmallett struct cvmx_tim_mem_ring1_s cn31xx; 287215976Sjmallett struct cvmx_tim_mem_ring1_s cn38xx; 288215976Sjmallett struct cvmx_tim_mem_ring1_s cn38xxp2; 289215976Sjmallett struct cvmx_tim_mem_ring1_s cn50xx; 290215976Sjmallett struct cvmx_tim_mem_ring1_s cn52xx; 291215976Sjmallett struct cvmx_tim_mem_ring1_s cn52xxp1; 292215976Sjmallett struct cvmx_tim_mem_ring1_s cn56xx; 293215976Sjmallett struct cvmx_tim_mem_ring1_s cn56xxp1; 294215976Sjmallett struct cvmx_tim_mem_ring1_s cn58xx; 295215976Sjmallett struct cvmx_tim_mem_ring1_s cn58xxp1; 296215976Sjmallett struct cvmx_tim_mem_ring1_s cn63xx; 297215976Sjmallett struct cvmx_tim_mem_ring1_s cn63xxp1; 298215976Sjmallett}; 299215976Sjmalletttypedef union cvmx_tim_mem_ring1 cvmx_tim_mem_ring1_t; 300215976Sjmallett 301215976Sjmallett/** 302215976Sjmallett * cvmx_tim_reg_bist_result 303215976Sjmallett * 304215976Sjmallett * Notes: 305215976Sjmallett * Access to the internal BiST results 306215976Sjmallett * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail). 307215976Sjmallett */ 308215976Sjmallettunion cvmx_tim_reg_bist_result 309215976Sjmallett{ 310215976Sjmallett uint64_t u64; 311215976Sjmallett struct cvmx_tim_reg_bist_result_s 312215976Sjmallett { 313215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 314215976Sjmallett uint64_t reserved_4_63 : 60; 315215976Sjmallett uint64_t sta : 2; /**< BiST result of the STA memories (0=pass, !0=fail) */ 316215976Sjmallett uint64_t ncb : 1; /**< BiST result of the NCB memories (0=pass, !0=fail) */ 317215976Sjmallett uint64_t ctl : 1; /**< BiST result of the CTL memories (0=pass, !0=fail) */ 318215976Sjmallett#else 319215976Sjmallett uint64_t ctl : 1; 320215976Sjmallett uint64_t ncb : 1; 321215976Sjmallett uint64_t sta : 2; 322215976Sjmallett uint64_t reserved_4_63 : 60; 323215976Sjmallett#endif 324215976Sjmallett } s; 325215976Sjmallett struct cvmx_tim_reg_bist_result_s cn30xx; 326215976Sjmallett struct cvmx_tim_reg_bist_result_s cn31xx; 327215976Sjmallett struct cvmx_tim_reg_bist_result_s cn38xx; 328215976Sjmallett struct cvmx_tim_reg_bist_result_s cn38xxp2; 329215976Sjmallett struct cvmx_tim_reg_bist_result_s cn50xx; 330215976Sjmallett struct cvmx_tim_reg_bist_result_s cn52xx; 331215976Sjmallett struct cvmx_tim_reg_bist_result_s cn52xxp1; 332215976Sjmallett struct cvmx_tim_reg_bist_result_s cn56xx; 333215976Sjmallett struct cvmx_tim_reg_bist_result_s cn56xxp1; 334215976Sjmallett struct cvmx_tim_reg_bist_result_s cn58xx; 335215976Sjmallett struct cvmx_tim_reg_bist_result_s cn58xxp1; 336215976Sjmallett struct cvmx_tim_reg_bist_result_s cn63xx; 337215976Sjmallett struct cvmx_tim_reg_bist_result_s cn63xxp1; 338215976Sjmallett}; 339215976Sjmalletttypedef union cvmx_tim_reg_bist_result cvmx_tim_reg_bist_result_t; 340215976Sjmallett 341215976Sjmallett/** 342215976Sjmallett * cvmx_tim_reg_error 343215976Sjmallett * 344215976Sjmallett * Notes: 345215976Sjmallett * A ring is in error if its interval has elapsed more than once without having been serviced. 346215976Sjmallett * During a CSR write to this register, the write data is used as a mask to clear the selected mask 347215976Sjmallett * bits (mask'[15:0] = mask[15:0] & ~write_data[15:0]). 348215976Sjmallett */ 349215976Sjmallettunion cvmx_tim_reg_error 350215976Sjmallett{ 351215976Sjmallett uint64_t u64; 352215976Sjmallett struct cvmx_tim_reg_error_s 353215976Sjmallett { 354215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 355215976Sjmallett uint64_t reserved_16_63 : 48; 356215976Sjmallett uint64_t mask : 16; /**< Bit mask indicating the rings in error */ 357215976Sjmallett#else 358215976Sjmallett uint64_t mask : 16; 359215976Sjmallett uint64_t reserved_16_63 : 48; 360215976Sjmallett#endif 361215976Sjmallett } s; 362215976Sjmallett struct cvmx_tim_reg_error_s cn30xx; 363215976Sjmallett struct cvmx_tim_reg_error_s cn31xx; 364215976Sjmallett struct cvmx_tim_reg_error_s cn38xx; 365215976Sjmallett struct cvmx_tim_reg_error_s cn38xxp2; 366215976Sjmallett struct cvmx_tim_reg_error_s cn50xx; 367215976Sjmallett struct cvmx_tim_reg_error_s cn52xx; 368215976Sjmallett struct cvmx_tim_reg_error_s cn52xxp1; 369215976Sjmallett struct cvmx_tim_reg_error_s cn56xx; 370215976Sjmallett struct cvmx_tim_reg_error_s cn56xxp1; 371215976Sjmallett struct cvmx_tim_reg_error_s cn58xx; 372215976Sjmallett struct cvmx_tim_reg_error_s cn58xxp1; 373215976Sjmallett struct cvmx_tim_reg_error_s cn63xx; 374215976Sjmallett struct cvmx_tim_reg_error_s cn63xxp1; 375215976Sjmallett}; 376215976Sjmalletttypedef union cvmx_tim_reg_error cvmx_tim_reg_error_t; 377215976Sjmallett 378215976Sjmallett/** 379215976Sjmallett * cvmx_tim_reg_flags 380215976Sjmallett * 381215976Sjmallett * Notes: 382215976Sjmallett * TIM has a counter that causes a periodic tick every 1024 cycles. This counter is shared by all 383215976Sjmallett * rings. (Each tick causes the HW to decrement the time offset (i.e. COUNT) for all enabled rings.) 384215976Sjmallett * When ENA_TIM==0, the HW stops this shared periodic counter, so there are no more ticks, and there 385215976Sjmallett * are no more new bucket traversals (for any ring). 386215976Sjmallett * 387215976Sjmallett * If ENA_TIM transitions 1->0, TIM will no longer create new bucket traversals, but there may 388215976Sjmallett * have been previous ones. If there are ring bucket traversals that were already pending but 389215976Sjmallett * not currently active (i.e. bucket traversals that need to be done by the HW, but haven't been yet) 390215976Sjmallett * during this ENA_TIM 1->0 transition, then these bucket traversals will remain pending until 391215976Sjmallett * ENA_TIM is later set to one. Bucket traversals that were already in progress will complete 392215976Sjmallett * after the 1->0 ENA_TIM transition, though. 393215976Sjmallett */ 394215976Sjmallettunion cvmx_tim_reg_flags 395215976Sjmallett{ 396215976Sjmallett uint64_t u64; 397215976Sjmallett struct cvmx_tim_reg_flags_s 398215976Sjmallett { 399215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 400215976Sjmallett uint64_t reserved_3_63 : 61; 401215976Sjmallett uint64_t reset : 1; /**< Reset oneshot pulse for free-running structures */ 402215976Sjmallett uint64_t enable_dwb : 1; /**< Enables non-zero DonwWriteBacks when set 403215976Sjmallett When set, enables the use of 404215976Sjmallett DontWriteBacks during the buffer freeing 405215976Sjmallett operations. */ 406215976Sjmallett uint64_t enable_timers : 1; /**< Enables the TIM section when set 407215976Sjmallett When set, TIM is in normal operation. 408215976Sjmallett When clear, time is effectively stopped for all 409215976Sjmallett rings in TIM. */ 410215976Sjmallett#else 411215976Sjmallett uint64_t enable_timers : 1; 412215976Sjmallett uint64_t enable_dwb : 1; 413215976Sjmallett uint64_t reset : 1; 414215976Sjmallett uint64_t reserved_3_63 : 61; 415215976Sjmallett#endif 416215976Sjmallett } s; 417215976Sjmallett struct cvmx_tim_reg_flags_s cn30xx; 418215976Sjmallett struct cvmx_tim_reg_flags_s cn31xx; 419215976Sjmallett struct cvmx_tim_reg_flags_s cn38xx; 420215976Sjmallett struct cvmx_tim_reg_flags_s cn38xxp2; 421215976Sjmallett struct cvmx_tim_reg_flags_s cn50xx; 422215976Sjmallett struct cvmx_tim_reg_flags_s cn52xx; 423215976Sjmallett struct cvmx_tim_reg_flags_s cn52xxp1; 424215976Sjmallett struct cvmx_tim_reg_flags_s cn56xx; 425215976Sjmallett struct cvmx_tim_reg_flags_s cn56xxp1; 426215976Sjmallett struct cvmx_tim_reg_flags_s cn58xx; 427215976Sjmallett struct cvmx_tim_reg_flags_s cn58xxp1; 428215976Sjmallett struct cvmx_tim_reg_flags_s cn63xx; 429215976Sjmallett struct cvmx_tim_reg_flags_s cn63xxp1; 430215976Sjmallett}; 431215976Sjmalletttypedef union cvmx_tim_reg_flags cvmx_tim_reg_flags_t; 432215976Sjmallett 433215976Sjmallett/** 434215976Sjmallett * cvmx_tim_reg_int_mask 435215976Sjmallett * 436215976Sjmallett * Notes: 437215976Sjmallett * Note that this CSR is present only in chip revisions beginning with pass2. 438215976Sjmallett * When mask bit is set, the interrupt is enabled. 439215976Sjmallett */ 440215976Sjmallettunion cvmx_tim_reg_int_mask 441215976Sjmallett{ 442215976Sjmallett uint64_t u64; 443215976Sjmallett struct cvmx_tim_reg_int_mask_s 444215976Sjmallett { 445215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 446215976Sjmallett uint64_t reserved_16_63 : 48; 447215976Sjmallett uint64_t mask : 16; /**< Bit mask corresponding to TIM_REG_ERROR.MASK above */ 448215976Sjmallett#else 449215976Sjmallett uint64_t mask : 16; 450215976Sjmallett uint64_t reserved_16_63 : 48; 451215976Sjmallett#endif 452215976Sjmallett } s; 453215976Sjmallett struct cvmx_tim_reg_int_mask_s cn30xx; 454215976Sjmallett struct cvmx_tim_reg_int_mask_s cn31xx; 455215976Sjmallett struct cvmx_tim_reg_int_mask_s cn38xx; 456215976Sjmallett struct cvmx_tim_reg_int_mask_s cn38xxp2; 457215976Sjmallett struct cvmx_tim_reg_int_mask_s cn50xx; 458215976Sjmallett struct cvmx_tim_reg_int_mask_s cn52xx; 459215976Sjmallett struct cvmx_tim_reg_int_mask_s cn52xxp1; 460215976Sjmallett struct cvmx_tim_reg_int_mask_s cn56xx; 461215976Sjmallett struct cvmx_tim_reg_int_mask_s cn56xxp1; 462215976Sjmallett struct cvmx_tim_reg_int_mask_s cn58xx; 463215976Sjmallett struct cvmx_tim_reg_int_mask_s cn58xxp1; 464215976Sjmallett struct cvmx_tim_reg_int_mask_s cn63xx; 465215976Sjmallett struct cvmx_tim_reg_int_mask_s cn63xxp1; 466215976Sjmallett}; 467215976Sjmalletttypedef union cvmx_tim_reg_int_mask cvmx_tim_reg_int_mask_t; 468215976Sjmallett 469215976Sjmallett/** 470215976Sjmallett * cvmx_tim_reg_read_idx 471215976Sjmallett * 472215976Sjmallett * Notes: 473215976Sjmallett * Provides the read index during a CSR read operation to any of the CSRs that are physically stored 474215976Sjmallett * as memories. The names of these CSRs begin with the prefix "TIM_MEM_". 475215976Sjmallett * IDX[7:0] is the read index. INC[7:0] is an increment that is added to IDX[7:0] after any CSR read. 476215976Sjmallett * The intended use is to initially write this CSR such that IDX=0 and INC=1. Then, the entire 477215976Sjmallett * contents of a CSR memory can be read with consecutive CSR read commands. 478215976Sjmallett */ 479215976Sjmallettunion cvmx_tim_reg_read_idx 480215976Sjmallett{ 481215976Sjmallett uint64_t u64; 482215976Sjmallett struct cvmx_tim_reg_read_idx_s 483215976Sjmallett { 484215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 485215976Sjmallett uint64_t reserved_16_63 : 48; 486215976Sjmallett uint64_t inc : 8; /**< Increment to add to current index for next index */ 487215976Sjmallett uint64_t index : 8; /**< Index to use for next memory CSR read */ 488215976Sjmallett#else 489215976Sjmallett uint64_t index : 8; 490215976Sjmallett uint64_t inc : 8; 491215976Sjmallett uint64_t reserved_16_63 : 48; 492215976Sjmallett#endif 493215976Sjmallett } s; 494215976Sjmallett struct cvmx_tim_reg_read_idx_s cn30xx; 495215976Sjmallett struct cvmx_tim_reg_read_idx_s cn31xx; 496215976Sjmallett struct cvmx_tim_reg_read_idx_s cn38xx; 497215976Sjmallett struct cvmx_tim_reg_read_idx_s cn38xxp2; 498215976Sjmallett struct cvmx_tim_reg_read_idx_s cn50xx; 499215976Sjmallett struct cvmx_tim_reg_read_idx_s cn52xx; 500215976Sjmallett struct cvmx_tim_reg_read_idx_s cn52xxp1; 501215976Sjmallett struct cvmx_tim_reg_read_idx_s cn56xx; 502215976Sjmallett struct cvmx_tim_reg_read_idx_s cn56xxp1; 503215976Sjmallett struct cvmx_tim_reg_read_idx_s cn58xx; 504215976Sjmallett struct cvmx_tim_reg_read_idx_s cn58xxp1; 505215976Sjmallett struct cvmx_tim_reg_read_idx_s cn63xx; 506215976Sjmallett struct cvmx_tim_reg_read_idx_s cn63xxp1; 507215976Sjmallett}; 508215976Sjmalletttypedef union cvmx_tim_reg_read_idx cvmx_tim_reg_read_idx_t; 509215976Sjmallett 510215976Sjmallett#endif 511