cvmx-stxx-defs.h revision 215976
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-stxx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon stxx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_STXX_TYPEDEFS_H__ 53#define __CVMX_STXX_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_STXX_ARB_CTL(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 60 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 61 cvmx_warn("CVMX_STXX_ARB_CTL(%lu) is invalid on this chip\n", block_id); 62 return CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull; 63} 64#else 65#define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull) 66#endif 67#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68static inline uint64_t CVMX_STXX_BCKPRS_CNT(unsigned long block_id) 69{ 70 if (!( 71 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 72 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 73 cvmx_warn("CVMX_STXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id); 74 return CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull; 75} 76#else 77#define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull) 78#endif 79#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80static inline uint64_t CVMX_STXX_COM_CTL(unsigned long block_id) 81{ 82 if (!( 83 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 84 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 85 cvmx_warn("CVMX_STXX_COM_CTL(%lu) is invalid on this chip\n", block_id); 86 return CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull; 87} 88#else 89#define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull) 90#endif 91#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 92static inline uint64_t CVMX_STXX_DIP_CNT(unsigned long block_id) 93{ 94 if (!( 95 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 96 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 97 cvmx_warn("CVMX_STXX_DIP_CNT(%lu) is invalid on this chip\n", block_id); 98 return CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull; 99} 100#else 101#define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull) 102#endif 103#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104static inline uint64_t CVMX_STXX_IGN_CAL(unsigned long block_id) 105{ 106 if (!( 107 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 108 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 109 cvmx_warn("CVMX_STXX_IGN_CAL(%lu) is invalid on this chip\n", block_id); 110 return CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull; 111} 112#else 113#define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull) 114#endif 115#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116static inline uint64_t CVMX_STXX_INT_MSK(unsigned long block_id) 117{ 118 if (!( 119 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 120 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 121 cvmx_warn("CVMX_STXX_INT_MSK(%lu) is invalid on this chip\n", block_id); 122 return CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull; 123} 124#else 125#define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull) 126#endif 127#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 128static inline uint64_t CVMX_STXX_INT_REG(unsigned long block_id) 129{ 130 if (!( 131 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 132 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 133 cvmx_warn("CVMX_STXX_INT_REG(%lu) is invalid on this chip\n", block_id); 134 return CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull; 135} 136#else 137#define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull) 138#endif 139#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 140static inline uint64_t CVMX_STXX_INT_SYNC(unsigned long block_id) 141{ 142 if (!( 143 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 144 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 145 cvmx_warn("CVMX_STXX_INT_SYNC(%lu) is invalid on this chip\n", block_id); 146 return CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull; 147} 148#else 149#define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull) 150#endif 151#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 152static inline uint64_t CVMX_STXX_MIN_BST(unsigned long block_id) 153{ 154 if (!( 155 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 156 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 157 cvmx_warn("CVMX_STXX_MIN_BST(%lu) is invalid on this chip\n", block_id); 158 return CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull; 159} 160#else 161#define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull) 162#endif 163#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 164static inline uint64_t CVMX_STXX_SPI4_CALX(unsigned long offset, unsigned long block_id) 165{ 166 if (!( 167 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) || 168 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1)))))) 169 cvmx_warn("CVMX_STXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id); 170 return CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8; 171} 172#else 173#define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8) 174#endif 175#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176static inline uint64_t CVMX_STXX_SPI4_DAT(unsigned long block_id) 177{ 178 if (!( 179 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 180 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 181 cvmx_warn("CVMX_STXX_SPI4_DAT(%lu) is invalid on this chip\n", block_id); 182 return CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull; 183} 184#else 185#define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188static inline uint64_t CVMX_STXX_SPI4_STAT(unsigned long block_id) 189{ 190 if (!( 191 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 192 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 193 cvmx_warn("CVMX_STXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id); 194 return CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull; 195} 196#else 197#define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull) 198#endif 199#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 200static inline uint64_t CVMX_STXX_STAT_BYTES_HI(unsigned long block_id) 201{ 202 if (!( 203 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 204 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 205 cvmx_warn("CVMX_STXX_STAT_BYTES_HI(%lu) is invalid on this chip\n", block_id); 206 return CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull; 207} 208#else 209#define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull) 210#endif 211#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212static inline uint64_t CVMX_STXX_STAT_BYTES_LO(unsigned long block_id) 213{ 214 if (!( 215 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 216 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 217 cvmx_warn("CVMX_STXX_STAT_BYTES_LO(%lu) is invalid on this chip\n", block_id); 218 return CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull; 219} 220#else 221#define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull) 222#endif 223#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 224static inline uint64_t CVMX_STXX_STAT_CTL(unsigned long block_id) 225{ 226 if (!( 227 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 228 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 229 cvmx_warn("CVMX_STXX_STAT_CTL(%lu) is invalid on this chip\n", block_id); 230 return CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull; 231} 232#else 233#define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull) 234#endif 235#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236static inline uint64_t CVMX_STXX_STAT_PKT_XMT(unsigned long block_id) 237{ 238 if (!( 239 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || 240 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) 241 cvmx_warn("CVMX_STXX_STAT_PKT_XMT(%lu) is invalid on this chip\n", block_id); 242 return CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull; 243} 244#else 245#define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull) 246#endif 247 248/** 249 * cvmx_stx#_arb_ctl 250 * 251 * STX_ARB_CTL - Spi transmit arbitration control 252 * 253 * 254 * Notes: 255 * If STX_ARB_CTL[MINTRN] is set in Spi4 mode, then the data_max_t 256 * parameter will have to be adjusted. Please see the 257 * STX_SPI4_DAT[MAX_T] section for additional information. In 258 * addition, the min_burst can only be guaranteed on the initial data 259 * burst of a given packet (i.e. the first data burst which contains 260 * the SOP tick). All subsequent bursts could be truncated by training 261 * sequences at any point during transmission and could be arbitrarily 262 * small. This mode is only for use in Spi4 mode. 263 */ 264union cvmx_stxx_arb_ctl 265{ 266 uint64_t u64; 267 struct cvmx_stxx_arb_ctl_s 268 { 269#if __BYTE_ORDER == __BIG_ENDIAN 270 uint64_t reserved_6_63 : 58; 271 uint64_t mintrn : 1; /**< Hold off training cycles until STX_MIN_BST[MINB] 272 is satisfied */ 273 uint64_t reserved_4_4 : 1; 274 uint64_t igntpa : 1; /**< User switch to ignore any TPA information from the 275 Spi interface. This CSR forces all TPA terms to 276 be masked out. It is only intended as backdoor 277 or debug feature. */ 278 uint64_t reserved_0_2 : 3; 279#else 280 uint64_t reserved_0_2 : 3; 281 uint64_t igntpa : 1; 282 uint64_t reserved_4_4 : 1; 283 uint64_t mintrn : 1; 284 uint64_t reserved_6_63 : 58; 285#endif 286 } s; 287 struct cvmx_stxx_arb_ctl_s cn38xx; 288 struct cvmx_stxx_arb_ctl_s cn38xxp2; 289 struct cvmx_stxx_arb_ctl_s cn58xx; 290 struct cvmx_stxx_arb_ctl_s cn58xxp1; 291}; 292typedef union cvmx_stxx_arb_ctl cvmx_stxx_arb_ctl_t; 293 294/** 295 * cvmx_stx#_bckprs_cnt 296 * 297 * Notes: 298 * This register reports the total number of cycles (STX data clks - 299 * stx_clk) in which the port defined in STX_STAT_CTL[BCKPRS] has lost TPA 300 * or is otherwise receiving backpressure. 301 * 302 * In Spi4 mode, this is defined as a loss of TPA which is indicated when 303 * the receiving device reports SATISFIED for the given port. The calendar 304 * status is brought into N2 on the spi4_tx*_sclk and synchronized into the 305 * N2 Spi TX clock domain which is 1/2 the frequency of the spi4_tx*_dclk 306 * clock (internally, this the stx_clk). The counter will update on the 307 * rising edge in which backpressure is reported. 308 * 309 * This register will be cleared when software writes all '1's to 310 * the STX_BCKPRS_CNT. 311 */ 312union cvmx_stxx_bckprs_cnt 313{ 314 uint64_t u64; 315 struct cvmx_stxx_bckprs_cnt_s 316 { 317#if __BYTE_ORDER == __BIG_ENDIAN 318 uint64_t reserved_32_63 : 32; 319 uint64_t cnt : 32; /**< Number of cycles when back-pressure is received 320 for port defined in STX_STAT_CTL[BCKPRS] */ 321#else 322 uint64_t cnt : 32; 323 uint64_t reserved_32_63 : 32; 324#endif 325 } s; 326 struct cvmx_stxx_bckprs_cnt_s cn38xx; 327 struct cvmx_stxx_bckprs_cnt_s cn38xxp2; 328 struct cvmx_stxx_bckprs_cnt_s cn58xx; 329 struct cvmx_stxx_bckprs_cnt_s cn58xxp1; 330}; 331typedef union cvmx_stxx_bckprs_cnt cvmx_stxx_bckprs_cnt_t; 332 333/** 334 * cvmx_stx#_com_ctl 335 * 336 * STX_COM_CTL - TX Common Control Register 337 * 338 * 339 * Notes: 340 * Restrictions: 341 * Both the calendar table and the LEN and M parameters must be 342 * completely setup before writing the Interface enable (INF_EN) and 343 * Status channel enabled (ST_EN) asserted. 344 */ 345union cvmx_stxx_com_ctl 346{ 347 uint64_t u64; 348 struct cvmx_stxx_com_ctl_s 349 { 350#if __BYTE_ORDER == __BIG_ENDIAN 351 uint64_t reserved_4_63 : 60; 352 uint64_t st_en : 1; /**< Status channel enabled */ 353 uint64_t reserved_1_2 : 2; 354 uint64_t inf_en : 1; /**< Interface enable */ 355#else 356 uint64_t inf_en : 1; 357 uint64_t reserved_1_2 : 2; 358 uint64_t st_en : 1; 359 uint64_t reserved_4_63 : 60; 360#endif 361 } s; 362 struct cvmx_stxx_com_ctl_s cn38xx; 363 struct cvmx_stxx_com_ctl_s cn38xxp2; 364 struct cvmx_stxx_com_ctl_s cn58xx; 365 struct cvmx_stxx_com_ctl_s cn58xxp1; 366}; 367typedef union cvmx_stxx_com_ctl cvmx_stxx_com_ctl_t; 368 369/** 370 * cvmx_stx#_dip_cnt 371 * 372 * Notes: 373 * * DIPMAX 374 * This counts the number of consecutive DIP2 states in which the the 375 * received DIP2 is bad. The expected range is 1-15 cycles with the 376 * value of 0 meaning disabled. 377 * 378 * * FRMMAX 379 * This counts the number of consecutive unexpected framing patterns (11) 380 * states. The expected range is 1-15 cycles with the value of 0 meaning 381 * disabled. 382 */ 383union cvmx_stxx_dip_cnt 384{ 385 uint64_t u64; 386 struct cvmx_stxx_dip_cnt_s 387 { 388#if __BYTE_ORDER == __BIG_ENDIAN 389 uint64_t reserved_8_63 : 56; 390 uint64_t frmmax : 4; /**< Number of consecutive unexpected framing patterns 391 before loss of sync */ 392 uint64_t dipmax : 4; /**< Number of consecutive DIP2 error before loss 393 of sync */ 394#else 395 uint64_t dipmax : 4; 396 uint64_t frmmax : 4; 397 uint64_t reserved_8_63 : 56; 398#endif 399 } s; 400 struct cvmx_stxx_dip_cnt_s cn38xx; 401 struct cvmx_stxx_dip_cnt_s cn38xxp2; 402 struct cvmx_stxx_dip_cnt_s cn58xx; 403 struct cvmx_stxx_dip_cnt_s cn58xxp1; 404}; 405typedef union cvmx_stxx_dip_cnt cvmx_stxx_dip_cnt_t; 406 407/** 408 * cvmx_stx#_ign_cal 409 * 410 * STX_IGN_CAL - Ignore Calendar Status from Spi4 Status Channel 411 * 412 */ 413union cvmx_stxx_ign_cal 414{ 415 uint64_t u64; 416 struct cvmx_stxx_ign_cal_s 417 { 418#if __BYTE_ORDER == __BIG_ENDIAN 419 uint64_t reserved_16_63 : 48; 420 uint64_t igntpa : 16; /**< Ignore Calendar Status from Spi4 Status Channel 421 per Spi4 port 422 - 0: Use the status channel info 423 - 1: Grant the given port MAX_BURST1 credits */ 424#else 425 uint64_t igntpa : 16; 426 uint64_t reserved_16_63 : 48; 427#endif 428 } s; 429 struct cvmx_stxx_ign_cal_s cn38xx; 430 struct cvmx_stxx_ign_cal_s cn38xxp2; 431 struct cvmx_stxx_ign_cal_s cn58xx; 432 struct cvmx_stxx_ign_cal_s cn58xxp1; 433}; 434typedef union cvmx_stxx_ign_cal cvmx_stxx_ign_cal_t; 435 436/** 437 * cvmx_stx#_int_msk 438 * 439 * Notes: 440 * If the bit is enabled, then the coresponding exception condition will 441 * result in an interrupt to the system. 442 */ 443union cvmx_stxx_int_msk 444{ 445 uint64_t u64; 446 struct cvmx_stxx_int_msk_s 447 { 448#if __BYTE_ORDER == __BIG_ENDIAN 449 uint64_t reserved_8_63 : 56; 450 uint64_t frmerr : 1; /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */ 451 uint64_t unxfrm : 1; /**< Unexpected framing sequence */ 452 uint64_t nosync : 1; /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */ 453 uint64_t diperr : 1; /**< DIP2 error on the Spi4 Status channel */ 454 uint64_t datovr : 1; /**< Spi4 FIFO overflow error */ 455 uint64_t ovrbst : 1; /**< Transmit packet burst too big */ 456 uint64_t calpar1 : 1; /**< STX Calendar Table Parity Error Bank1 */ 457 uint64_t calpar0 : 1; /**< STX Calendar Table Parity Error Bank0 */ 458#else 459 uint64_t calpar0 : 1; 460 uint64_t calpar1 : 1; 461 uint64_t ovrbst : 1; 462 uint64_t datovr : 1; 463 uint64_t diperr : 1; 464 uint64_t nosync : 1; 465 uint64_t unxfrm : 1; 466 uint64_t frmerr : 1; 467 uint64_t reserved_8_63 : 56; 468#endif 469 } s; 470 struct cvmx_stxx_int_msk_s cn38xx; 471 struct cvmx_stxx_int_msk_s cn38xxp2; 472 struct cvmx_stxx_int_msk_s cn58xx; 473 struct cvmx_stxx_int_msk_s cn58xxp1; 474}; 475typedef union cvmx_stxx_int_msk cvmx_stxx_int_msk_t; 476 477/** 478 * cvmx_stx#_int_reg 479 * 480 * Notes: 481 * * CALPAR0 482 * This bit indicates that the Spi4 calendar table encountered a parity 483 * error on bank0 of the calendar table memory. This error bit is 484 * associated with the calendar table on the TX interface - the interface 485 * that drives the Spi databus. The calendar table is used in Spi4 mode 486 * when using the status channel. Parity errors can occur during normal 487 * operation when the calendar table is constantly being read for the port 488 * information, or during initialization time, when the user has access. 489 * This errors will force the the status channel to the reset state and 490 * begin driving training sequences. The status channel will also reset. 491 * Software must follow the init sequence to resynch the interface. This 492 * includes toggling INF_EN which will cancel all outstanding accumulated 493 * credits. 494 * 495 * * CALPAR1 496 * Identical to CALPAR0 except that it indicates that the error occured 497 * on bank1 (instead of bank0). 498 * 499 * * OVRBST 500 * STX can track upto a 512KB data burst. Any packet larger than that is 501 * illegal and will cause confusion in the STX state machine. BMI is 502 * responsible for throwing away these out of control packets from the 503 * input and the Execs should never generate them on the output. This is 504 * a fatal error and should have STX_INT_SYNC[OVRBST] set. 505 * 506 * * DATOVR 507 * FIFO where the Spi4 data ramps upto its transmit frequency has 508 * overflowed. This is a fatal error and should have 509 * STX_INT_SYNC[DATOVR] set. 510 * 511 * * DIPERR 512 * This bit will fire if any DIP2 error is caught by the Spi4 status 513 * channel. 514 * 515 * * NOSYNC 516 * This bit indicates that the number of consecutive DIP2 errors exceeds 517 * STX_DIP_CNT[MAXDIP] and that the interface should be taken down. The 518 * datapath will be notified and send continuous training sequences until 519 * software resynchronizes the interface. This error condition should 520 * have STX_INT_SYNC[NOSYNC] set. 521 * 522 * * UNXFRM 523 * Unexpected framing data was seen on the status channel. 524 * 525 * * FRMERR 526 * This bit indicates that the number of consecutive unexpected framing 527 * sequences STX_DIP_CNT[MAXFRM] and that the interface should be taken 528 * down. The datapath will be notified and send continuous training 529 * sequences until software resynchronizes the interface. This error 530 * condition should have STX_INT_SYNC[FRMERR] set. 531 * 532 * * SYNCERR 533 * Indicates that an exception marked in STX_INT_SYNC has occured and the 534 * TX datapath is disabled. It is recommended that the OVRBST, DATOVR, 535 * NOSYNC, and FRMERR error conditions all have their bits set in the 536 * STX_INT_SYNC register. 537 */ 538union cvmx_stxx_int_reg 539{ 540 uint64_t u64; 541 struct cvmx_stxx_int_reg_s 542 { 543#if __BYTE_ORDER == __BIG_ENDIAN 544 uint64_t reserved_9_63 : 55; 545 uint64_t syncerr : 1; /**< Interface encountered a fatal error */ 546 uint64_t frmerr : 1; /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */ 547 uint64_t unxfrm : 1; /**< Unexpected framing sequence */ 548 uint64_t nosync : 1; /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */ 549 uint64_t diperr : 1; /**< DIP2 error on the Spi4 Status channel */ 550 uint64_t datovr : 1; /**< Spi4 FIFO overflow error */ 551 uint64_t ovrbst : 1; /**< Transmit packet burst too big */ 552 uint64_t calpar1 : 1; /**< STX Calendar Table Parity Error Bank1 */ 553 uint64_t calpar0 : 1; /**< STX Calendar Table Parity Error Bank0 */ 554#else 555 uint64_t calpar0 : 1; 556 uint64_t calpar1 : 1; 557 uint64_t ovrbst : 1; 558 uint64_t datovr : 1; 559 uint64_t diperr : 1; 560 uint64_t nosync : 1; 561 uint64_t unxfrm : 1; 562 uint64_t frmerr : 1; 563 uint64_t syncerr : 1; 564 uint64_t reserved_9_63 : 55; 565#endif 566 } s; 567 struct cvmx_stxx_int_reg_s cn38xx; 568 struct cvmx_stxx_int_reg_s cn38xxp2; 569 struct cvmx_stxx_int_reg_s cn58xx; 570 struct cvmx_stxx_int_reg_s cn58xxp1; 571}; 572typedef union cvmx_stxx_int_reg cvmx_stxx_int_reg_t; 573 574/** 575 * cvmx_stx#_int_sync 576 * 577 * Notes: 578 * If the bit is enabled, then the coresponding exception condition is flagged 579 * to be fatal. In Spi4 mode, the exception condition will result in a loss 580 * of sync condition on the Spi4 interface and the datapath will send 581 * continuous traing sequences. 582 * 583 * It is recommended that software set the OVRBST, DATOVR, NOSYNC, and 584 * FRMERR errors as synchronization events. Software is free to 585 * synchronize the bus on other conditions, but this is the minimum 586 * recommended set. 587 */ 588union cvmx_stxx_int_sync 589{ 590 uint64_t u64; 591 struct cvmx_stxx_int_sync_s 592 { 593#if __BYTE_ORDER == __BIG_ENDIAN 594 uint64_t reserved_8_63 : 56; 595 uint64_t frmerr : 1; /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */ 596 uint64_t unxfrm : 1; /**< Unexpected framing sequence */ 597 uint64_t nosync : 1; /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */ 598 uint64_t diperr : 1; /**< DIP2 error on the Spi4 Status channel */ 599 uint64_t datovr : 1; /**< Spi4 FIFO overflow error */ 600 uint64_t ovrbst : 1; /**< Transmit packet burst too big */ 601 uint64_t calpar1 : 1; /**< STX Calendar Table Parity Error Bank1 */ 602 uint64_t calpar0 : 1; /**< STX Calendar Table Parity Error Bank0 */ 603#else 604 uint64_t calpar0 : 1; 605 uint64_t calpar1 : 1; 606 uint64_t ovrbst : 1; 607 uint64_t datovr : 1; 608 uint64_t diperr : 1; 609 uint64_t nosync : 1; 610 uint64_t unxfrm : 1; 611 uint64_t frmerr : 1; 612 uint64_t reserved_8_63 : 56; 613#endif 614 } s; 615 struct cvmx_stxx_int_sync_s cn38xx; 616 struct cvmx_stxx_int_sync_s cn38xxp2; 617 struct cvmx_stxx_int_sync_s cn58xx; 618 struct cvmx_stxx_int_sync_s cn58xxp1; 619}; 620typedef union cvmx_stxx_int_sync cvmx_stxx_int_sync_t; 621 622/** 623 * cvmx_stx#_min_bst 624 * 625 * STX_MIN_BST - Min Burst to enforce when inserting training sequence 626 * 627 */ 628union cvmx_stxx_min_bst 629{ 630 uint64_t u64; 631 struct cvmx_stxx_min_bst_s 632 { 633#if __BYTE_ORDER == __BIG_ENDIAN 634 uint64_t reserved_9_63 : 55; 635 uint64_t minb : 9; /**< When STX_ARB_CTL[MINTRN] is set, MINB indicates 636 the number of 8B blocks to send before inserting 637 a training sequence. Normally MINB will be set 638 to GMX_TX_SPI_THRESH[THRESH]. MINB should always 639 be set to an even number (ie. multiple of 16B) */ 640#else 641 uint64_t minb : 9; 642 uint64_t reserved_9_63 : 55; 643#endif 644 } s; 645 struct cvmx_stxx_min_bst_s cn38xx; 646 struct cvmx_stxx_min_bst_s cn38xxp2; 647 struct cvmx_stxx_min_bst_s cn58xx; 648 struct cvmx_stxx_min_bst_s cn58xxp1; 649}; 650typedef union cvmx_stxx_min_bst cvmx_stxx_min_bst_t; 651 652/** 653 * cvmx_stx#_spi4_cal# 654 * 655 * specify the RSL base addresses for the block 656 * STX_SPI4_CAL - Spi4 Calender table 657 * direct_calendar_write / direct_calendar_read 658 * 659 * Notes: 660 * There are 32 calendar table CSR's, each containing 4 entries for a 661 * total of 128 entries. In the above definition... 662 * 663 * n = calendar table offset * 4 664 * 665 * Example, offset 0x00 contains the calendar table entries 0, 1, 2, 3 666 * (with n == 0). Offset 0x10 is the 16th entry in the calendar table 667 * and would contain entries (16*4) = 64, 65, 66, and 67. 668 * 669 * Restrictions: 670 * Calendar table entry accesses (read or write) can only occur 671 * if the interface is disabled. All other accesses will be 672 * unpredictable. 673 * 674 * Both the calendar table and the LEN and M parameters must be 675 * completely setup before writing the Interface enable (INF_EN) and 676 * Status channel enabled (ST_EN) asserted. 677 */ 678union cvmx_stxx_spi4_calx 679{ 680 uint64_t u64; 681 struct cvmx_stxx_spi4_calx_s 682 { 683#if __BYTE_ORDER == __BIG_ENDIAN 684 uint64_t reserved_17_63 : 47; 685 uint64_t oddpar : 1; /**< Odd parity over STX_SPI4_CAL[15:0] 686 (^STX_SPI4_CAL[16:0] === 1'b1) | $NS NS */ 687 uint64_t prt3 : 4; /**< Status for port n+3 */ 688 uint64_t prt2 : 4; /**< Status for port n+2 */ 689 uint64_t prt1 : 4; /**< Status for port n+1 */ 690 uint64_t prt0 : 4; /**< Status for port n+0 */ 691#else 692 uint64_t prt0 : 4; 693 uint64_t prt1 : 4; 694 uint64_t prt2 : 4; 695 uint64_t prt3 : 4; 696 uint64_t oddpar : 1; 697 uint64_t reserved_17_63 : 47; 698#endif 699 } s; 700 struct cvmx_stxx_spi4_calx_s cn38xx; 701 struct cvmx_stxx_spi4_calx_s cn38xxp2; 702 struct cvmx_stxx_spi4_calx_s cn58xx; 703 struct cvmx_stxx_spi4_calx_s cn58xxp1; 704}; 705typedef union cvmx_stxx_spi4_calx cvmx_stxx_spi4_calx_t; 706 707/** 708 * cvmx_stx#_spi4_dat 709 * 710 * STX_SPI4_DAT - Spi4 datapath channel control register 711 * 712 * 713 * Notes: 714 * Restrictions: 715 * * DATA_MAX_T must be in MOD 4 cycles 716 * 717 * * DATA_MAX_T must at least 0x20 718 * 719 * * DATA_MAX_T == 0 or ALPHA == 0 will disable the training sequnce 720 * 721 * * If STX_ARB_CTL[MINTRN] is set, then training cycles will stall 722 * waiting for min bursts to complete. In the worst case, this will 723 * add the entire min burst transmission time to the interval between 724 * trainging sequence. The observed MAX_T on the Spi4 bus will be... 725 * 726 * STX_SPI4_DAT[MAX_T] + (STX_MIN_BST[MINB] * 4) 727 * 728 * If STX_ARB_CTL[MINTRN] is set in Spi4 mode, then the data_max_t 729 * parameter will have to be adjusted. Please see the 730 * STX_SPI4_DAT[MAX_T] section for additional information. In 731 * addition, the min_burst can only be guaranteed on the initial data 732 * burst of a given packet (i.e. the first data burst which contains 733 * the SOP tick). All subsequent bursts could be truncated by training 734 * sequences at any point during transmission and could be arbitrarily 735 * small. This mode is only for use in Spi4 mode. 736 */ 737union cvmx_stxx_spi4_dat 738{ 739 uint64_t u64; 740 struct cvmx_stxx_spi4_dat_s 741 { 742#if __BYTE_ORDER == __BIG_ENDIAN 743 uint64_t reserved_32_63 : 32; 744 uint64_t alpha : 16; /**< alpha (from spi4.2 spec) */ 745 uint64_t max_t : 16; /**< DATA_MAX_T (from spi4.2 spec) */ 746#else 747 uint64_t max_t : 16; 748 uint64_t alpha : 16; 749 uint64_t reserved_32_63 : 32; 750#endif 751 } s; 752 struct cvmx_stxx_spi4_dat_s cn38xx; 753 struct cvmx_stxx_spi4_dat_s cn38xxp2; 754 struct cvmx_stxx_spi4_dat_s cn58xx; 755 struct cvmx_stxx_spi4_dat_s cn58xxp1; 756}; 757typedef union cvmx_stxx_spi4_dat cvmx_stxx_spi4_dat_t; 758 759/** 760 * cvmx_stx#_spi4_stat 761 * 762 * STX_SPI4_STAT - Spi4 status channel control register 763 * 764 * 765 * Notes: 766 * Restrictions: 767 * Both the calendar table and the LEN and M parameters must be 768 * completely setup before writing the Interface enable (INF_EN) and 769 * Status channel enabled (ST_EN) asserted. 770 * 771 * The calendar table will only be enabled when LEN > 0. 772 * 773 * Current rev will only support LVTTL status IO. 774 */ 775union cvmx_stxx_spi4_stat 776{ 777 uint64_t u64; 778 struct cvmx_stxx_spi4_stat_s 779 { 780#if __BYTE_ORDER == __BIG_ENDIAN 781 uint64_t reserved_16_63 : 48; 782 uint64_t m : 8; /**< CALENDAR_M (from spi4.2 spec) */ 783 uint64_t reserved_7_7 : 1; 784 uint64_t len : 7; /**< CALENDAR_LEN (from spi4.2 spec) */ 785#else 786 uint64_t len : 7; 787 uint64_t reserved_7_7 : 1; 788 uint64_t m : 8; 789 uint64_t reserved_16_63 : 48; 790#endif 791 } s; 792 struct cvmx_stxx_spi4_stat_s cn38xx; 793 struct cvmx_stxx_spi4_stat_s cn38xxp2; 794 struct cvmx_stxx_spi4_stat_s cn58xx; 795 struct cvmx_stxx_spi4_stat_s cn58xxp1; 796}; 797typedef union cvmx_stxx_spi4_stat cvmx_stxx_spi4_stat_t; 798 799/** 800 * cvmx_stx#_stat_bytes_hi 801 */ 802union cvmx_stxx_stat_bytes_hi 803{ 804 uint64_t u64; 805 struct cvmx_stxx_stat_bytes_hi_s 806 { 807#if __BYTE_ORDER == __BIG_ENDIAN 808 uint64_t reserved_32_63 : 32; 809 uint64_t cnt : 32; /**< Number of bytes sent (CNT[63:32]) */ 810#else 811 uint64_t cnt : 32; 812 uint64_t reserved_32_63 : 32; 813#endif 814 } s; 815 struct cvmx_stxx_stat_bytes_hi_s cn38xx; 816 struct cvmx_stxx_stat_bytes_hi_s cn38xxp2; 817 struct cvmx_stxx_stat_bytes_hi_s cn58xx; 818 struct cvmx_stxx_stat_bytes_hi_s cn58xxp1; 819}; 820typedef union cvmx_stxx_stat_bytes_hi cvmx_stxx_stat_bytes_hi_t; 821 822/** 823 * cvmx_stx#_stat_bytes_lo 824 */ 825union cvmx_stxx_stat_bytes_lo 826{ 827 uint64_t u64; 828 struct cvmx_stxx_stat_bytes_lo_s 829 { 830#if __BYTE_ORDER == __BIG_ENDIAN 831 uint64_t reserved_32_63 : 32; 832 uint64_t cnt : 32; /**< Number of bytes sent (CNT[31:0]) */ 833#else 834 uint64_t cnt : 32; 835 uint64_t reserved_32_63 : 32; 836#endif 837 } s; 838 struct cvmx_stxx_stat_bytes_lo_s cn38xx; 839 struct cvmx_stxx_stat_bytes_lo_s cn38xxp2; 840 struct cvmx_stxx_stat_bytes_lo_s cn58xx; 841 struct cvmx_stxx_stat_bytes_lo_s cn58xxp1; 842}; 843typedef union cvmx_stxx_stat_bytes_lo cvmx_stxx_stat_bytes_lo_t; 844 845/** 846 * cvmx_stx#_stat_ctl 847 */ 848union cvmx_stxx_stat_ctl 849{ 850 uint64_t u64; 851 struct cvmx_stxx_stat_ctl_s 852 { 853#if __BYTE_ORDER == __BIG_ENDIAN 854 uint64_t reserved_5_63 : 59; 855 uint64_t clr : 1; /**< Clear all statistics counters 856 - STX_STAT_PKT_XMT 857 - STX_STAT_BYTES_HI 858 - STX_STAT_BYTES_LO */ 859 uint64_t bckprs : 4; /**< The selected port for STX_BCKPRS_CNT */ 860#else 861 uint64_t bckprs : 4; 862 uint64_t clr : 1; 863 uint64_t reserved_5_63 : 59; 864#endif 865 } s; 866 struct cvmx_stxx_stat_ctl_s cn38xx; 867 struct cvmx_stxx_stat_ctl_s cn38xxp2; 868 struct cvmx_stxx_stat_ctl_s cn58xx; 869 struct cvmx_stxx_stat_ctl_s cn58xxp1; 870}; 871typedef union cvmx_stxx_stat_ctl cvmx_stxx_stat_ctl_t; 872 873/** 874 * cvmx_stx#_stat_pkt_xmt 875 */ 876union cvmx_stxx_stat_pkt_xmt 877{ 878 uint64_t u64; 879 struct cvmx_stxx_stat_pkt_xmt_s 880 { 881#if __BYTE_ORDER == __BIG_ENDIAN 882 uint64_t reserved_32_63 : 32; 883 uint64_t cnt : 32; /**< Number of packets sent */ 884#else 885 uint64_t cnt : 32; 886 uint64_t reserved_32_63 : 32; 887#endif 888 } s; 889 struct cvmx_stxx_stat_pkt_xmt_s cn38xx; 890 struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2; 891 struct cvmx_stxx_stat_pkt_xmt_s cn58xx; 892 struct cvmx_stxx_stat_pkt_xmt_s cn58xxp1; 893}; 894typedef union cvmx_stxx_stat_pkt_xmt cvmx_stxx_stat_pkt_xmt_t; 895 896#endif 897