1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett 42215976Sjmallett/** 43215976Sjmallett * @file 44215976Sjmallett * 45215976Sjmallett * Interface to SRIO 46215976Sjmallett * 47215976Sjmallett * <hr>$Revision: 41586 $<hr> 48215976Sjmallett */ 49215976Sjmallett 50215976Sjmallett#ifndef __CVMX_SRIO_H__ 51215976Sjmallett#define __CVMX_SRIO_H__ 52215976Sjmallett 53215976Sjmallett#ifdef __cplusplus 54215976Sjmallettextern "C" { 55215976Sjmallett#endif 56215976Sjmallett 57215976Sjmallett/** 58215976Sjmallett * Enumeration of the type of operations that can be performed 59215976Sjmallett * by a mapped write operation. 60215976Sjmallett */ 61215976Sjmalletttypedef enum 62215976Sjmallett{ 63215976Sjmallett CVMX_SRIO_WRITE_MODE_NWRITE = 0, /**< Only create NWrite operations */ 64215976Sjmallett CVMX_SRIO_WRITE_MODE_NWRITE_RESP = 1, /**< Create NWrite with response */ 65215976Sjmallett CVMX_SRIO_WRITE_MODE_AUTO = 2, /**< Intelligently breaks writes into multiple transactions based on alignment */ 66215976Sjmallett CVMX_SRIO_WRITE_MODE_AUTO_RESP = 3, /**< CVMX_SRIO_WRITE_MODE_WRITE followed with a response */ 67215976Sjmallett CVMX_SRIO_WRITE_MODE_MAINTENANCE = 6, /**< Create a MAINTENANCE transaction. Use cvmx_srio_config_write32() instead */ 68215976Sjmallett CVMX_SRIO_WRITE_MODE_PORT = 7 /**< Port Write? */ 69215976Sjmallett} cvmx_srio_write_mode_t; 70215976Sjmallett 71215976Sjmallett/** 72215976Sjmallett * Enumeration of the type of operations that can be performed 73215976Sjmallett * by a mapped read operation. 74215976Sjmallett */ 75215976Sjmalletttypedef enum 76215976Sjmallett{ 77215976Sjmallett CVMX_SRIO_READ_MODE_NORMAL = 0, /**< Perform a normal read */ 78215976Sjmallett CVMX_SRIO_READ_MODE_ATOMIC_SET = 2, /**< Atomically sets bits in data on remote device */ 79215976Sjmallett CVMX_SRIO_READ_MODE_ATOMIC_CLEAR = 3, /**< Atomically clears bits in data on remote device */ 80215976Sjmallett CVMX_SRIO_READ_MODE_ATOMIC_INCREMENT = 4,/**< Atomically increments data on remote device */ 81215976Sjmallett CVMX_SRIO_READ_MODE_ATOMIC_DECREMENT = 5,/**< Atomically decrements data on remote device */ 82215976Sjmallett CVMX_SRIO_READ_MODE_MAINTENANCE = 6 /**< Create a MAINTENANCE transaction. Use cvmx_srio_config_read32() instead */ 83215976Sjmallett} cvmx_srio_read_mode_t; 84215976Sjmallett 85215976Sjmallett/** 86215976Sjmallett * Initialization flags for SRIO 87215976Sjmallett */ 88215976Sjmalletttypedef enum 89215976Sjmallett{ 90215976Sjmallett CVMX_SRIO_INITIALIZE_DEBUG = 1, 91215976Sjmallett} cvmx_srio_initialize_flags_t; 92215976Sjmallett 93215976Sjmallett/** 94215976Sjmallett * The possible results from a doorbell operation 95215976Sjmallett */ 96215976Sjmalletttypedef enum 97215976Sjmallett{ 98215976Sjmallett CVMX_SRIO_DOORBELL_DONE, /**< The doorbell is complete */ 99215976Sjmallett CVMX_SRIO_DOORBELL_NONE, /**< There wasn't an outstanding doorbell */ 100215976Sjmallett CVMX_SRIO_DOORBELL_BUSY, /**< The doorbell is still processing */ 101215976Sjmallett CVMX_SRIO_DOORBELL_RETRY, /**< The doorbell needs to be retried */ 102232812Sjmallett CVMX_SRIO_DOORBELL_ERROR, /**< The doorbell failed with an error */ 103232812Sjmallett CVMX_SRIO_DOORBELL_TMOUT /**< The doorbell failed due to timeout */ 104215976Sjmallett} cvmx_srio_doorbell_status_t; 105215976Sjmallett 106215976Sjmallett/** 107215976Sjmallett * This structure represents the SRIO header received from SRIO on 108215976Sjmallett * the top of every received message. This header passes through 109215976Sjmallett * IPD/PIP unmodified. 110215976Sjmallett */ 111215976Sjmalletttypedef struct 112215976Sjmallett{ 113215976Sjmallett union 114215976Sjmallett { 115215976Sjmallett uint64_t u64; 116215976Sjmallett struct 117215976Sjmallett { 118232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 119215976Sjmallett uint64_t prio : 2; /**< The sRIO prio (priority) field in the 120215976Sjmallett first sRIO message segment received for the 121215976Sjmallett message. */ 122215976Sjmallett uint64_t tt : 1; /**< When set, indicates that the first sRIO 123215976Sjmallett message segment received for the message had 124215976Sjmallett 16-bit source and destination ID's. When 125215976Sjmallett clear, indicates 8-bit ID were present. */ 126215976Sjmallett uint64_t dis : 1; /**< When set, indicates that the destination 127215976Sjmallett ID in the first sRIO message segment received 128215976Sjmallett for the message matched the 63xx's secondary 129215976Sjmallett ID. When clear, indicates that the destination 130215976Sjmallett ID in the first sRIO message segment 131215976Sjmallett received for the message matched the 63xx's 132215976Sjmallett primary ID. Note that the full destination 133215976Sjmallett ID in the received sRIO message can be 134215976Sjmallett determined via the combination of 135215976Sjmallett WORD0[DIS] in the sRIO inbound message 136215976Sjmallett header and WORD1[iprt] in the work queue 137215976Sjmallett entry created by PIP/IPD. */ 138215976Sjmallett uint64_t ssize : 4; /**< The RIO ssize (standard message packet data 139215976Sjmallett size) field used for the message. */ 140215976Sjmallett uint64_t sid : 16; /**< The source ID in the first sRIO message 141215976Sjmallett segment received for the message. When TT is 142215976Sjmallett clear, the most-significant 8 bits are zero. */ 143215976Sjmallett uint64_t xmbox : 4; /**< The RIO xmbox (recipient mailbox extension) 144215976Sjmallett field in the first sRIO message segment 145215976Sjmallett received for the message. Always zero for 146215976Sjmallett multi-segment messages. */ 147215976Sjmallett uint64_t mbox : 2; /**< The RIO mbox (recipient mailbox) field in 148215976Sjmallett the first sRIO message segment received for 149215976Sjmallett the message. */ 150215976Sjmallett uint64_t letter : 2; /**< The RIO letter (slot within a mailbox) 151215976Sjmallett field in the first sRIO message segment 152215976Sjmallett received for the message. */ 153215976Sjmallett uint64_t seq : 32; /**< A sequence number. Whenever the OCTEON 154215976Sjmallett 63xx sRIO hardware accepts the first sRIO 155215976Sjmallett segment of either a message or doorbell, it 156215976Sjmallett samples the current value of a counter 157215976Sjmallett register and increments the counter 158215976Sjmallett register. SEQ is the value sampled for the 159215976Sjmallett message. The counter increments once per 160215976Sjmallett message/doorbell. SEQ can be used to 161215976Sjmallett determine the relative order of 162215976Sjmallett packets/doorbells. Note that the SEQ-implied 163215976Sjmallett order may differ from the order that the 164215976Sjmallett WQE's are received by software for a number 165215976Sjmallett of reasons, including the fact that the WQE 166215976Sjmallett is not created until the end of the message, 167215976Sjmallett while SEQ is sampled when the first segment. */ 168215976Sjmallett#else 169215976Sjmallett uint64_t seq : 32; 170215976Sjmallett uint64_t letter : 2; 171215976Sjmallett uint64_t mbox : 2; 172215976Sjmallett uint64_t xmbox : 4; 173215976Sjmallett uint64_t sid : 16; 174215976Sjmallett uint64_t ssize : 4; 175215976Sjmallett uint64_t dis : 1; 176215976Sjmallett uint64_t tt : 1; 177215976Sjmallett uint64_t prio : 2; 178215976Sjmallett#endif 179215976Sjmallett } s; 180215976Sjmallett } word0; 181215976Sjmallett union 182215976Sjmallett { 183215976Sjmallett uint64_t u64; 184215976Sjmallett struct 185215976Sjmallett { 186232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 187215976Sjmallett uint64_t r : 1; /**< When set, WORD1[R]/PKT_INST_HDR[R] selects 188215976Sjmallett either RAWFULL or RAWSCHED special PIP 189215976Sjmallett instruction form. WORD1[R] may commonly be 190215976Sjmallett set so that WORD1[QOS,GRP] will be directly 191215976Sjmallett used by the PIP hardware. */ 192215976Sjmallett uint64_t reserved_62_58 : 5; 193215976Sjmallett uint64_t pm : 2; /**< WORD1[PM]/PKT_INST_HDR[PM] selects the PIP 194215976Sjmallett parse mode (uninterpreted, skip-to-L2, 195215976Sjmallett skip-to-IP), and chooses between 196215976Sjmallett RAWFULL/RAWSCHED when WORD1[R] is set. */ 197215976Sjmallett uint64_t reserved_55 : 1; 198215976Sjmallett uint64_t sl : 7; /**< WORD1[SL]/PKT_INST_HDR[SL] selects the 199215976Sjmallett skip II length. WORD1[SL] may typically be 200215976Sjmallett set to 8 (or larger) so that PIP skips this 201215976Sjmallett WORD1. */ 202215976Sjmallett uint64_t reserved_47_46 : 2; 203215976Sjmallett uint64_t nqos : 1; /**< WORD1[NQOS] must not be set when WORD1[R] 204215976Sjmallett is clear and PIP interprets WORD1 as a 205215976Sjmallett PKT_INST_HDR. When set, WORD1[NQOS]/PKT_INST_HDR[NQOS] 206215976Sjmallett prevents PIP from directly using 207215976Sjmallett WORD1[QOS]/PKT_INST_HDR[QOS] for the QOS 208215976Sjmallett value in the work queue entry created by 209215976Sjmallett PIP. WORD1[NQOS] may commonly be clear so 210215976Sjmallett that WORD1[QOS] will be directly used by the 211215976Sjmallett PIP hardware. PKT_INST_HDR[NQOS] is new to 212215976Sjmallett 63xx - this functionality did not exist in 213215976Sjmallett prior OCTEON's. */ 214215976Sjmallett uint64_t ngrp : 1; /**< WORD1[NGRP] must not be set when WORD1[R] 215215976Sjmallett is clear and PIP interprets WORD1 as a 216215976Sjmallett PKT_INST_HDR. When set, WORD1[NGRP]/PKT_INST_HDR[NGRP] 217215976Sjmallett prevents PIP from directly using 218215976Sjmallett WORD1[GRP]/PKT_INST_HDR[GRP] for the GRP 219215976Sjmallett value in the work queue entry created by 220215976Sjmallett PIP. WORD1[NGRP] may commonly be clear so 221215976Sjmallett that WORD1[GRP] will be directly used by the 222215976Sjmallett PIP hardware. PKT_INST_HDR[NGRP] is new to 223215976Sjmallett 63xx - this functionality did not exist in 224215976Sjmallett prior OCTEON's. */ 225215976Sjmallett uint64_t ntt : 1; /**< WORD1[NTT] must not be set when WORD1[R] 226215976Sjmallett is clear and PIP interprets WORD1 as a 227215976Sjmallett PKT_INST_HDR. When set, WORD1[NTT]/PKT_INST_HDR[NTT] 228215976Sjmallett prevents PIP from directly using 229215976Sjmallett WORD1[TT]/PKT_INST_HDR[TT] for the TT value 230215976Sjmallett in the work queue entry created by PIP. 231215976Sjmallett PKT_INST_HDR[NTT] is new to 63xx - this 232215976Sjmallett functionality did not exist in prior OCTEON's. */ 233215976Sjmallett uint64_t ntag : 1; /**< WORD1[NTAG] must not be set when WORD1[R] 234215976Sjmallett is clear and PIP interprets WORD1 as a 235215976Sjmallett PKT_INST_HDR. When set, WORD1[NTAG]/PKT_INST_HDR[NTAG] 236215976Sjmallett prevents PIP from directly using 237215976Sjmallett WORD1[TAG]/PKT_INST_HDR[TAG] for the TAG 238215976Sjmallett value in the work queue entry created by PIP. 239215976Sjmallett PKT_INST_HDR[NTAG] is new to 63xx - this 240215976Sjmallett functionality did not exist in prior OCTEON's. */ 241215976Sjmallett uint64_t qos : 3; /**< Created by the hardware from an entry in a 242215976Sjmallett 256-entry table. The 8-bit value 243215976Sjmallett WORD0[PRIO,TT,DIS,MBOX,LETTER] selects the 244215976Sjmallett table entry. When WORD1[R] is set and WORD1[NQOS] 245215976Sjmallett is clear, WORD1[QOS] becomes the QOS value 246215976Sjmallett in the work queue entry created by PIP. The 247215976Sjmallett QOS value in the work queue entry determines 248215976Sjmallett the priority that SSO/POW will schedule the 249215976Sjmallett work, and can also control how/if the sRIO 250215976Sjmallett message gets dropped by PIP/IPD. The 256-entry 251215976Sjmallett table is unique to each sRIO core, but 252215976Sjmallett shared by the two controllers associated 253215976Sjmallett with the sRIO core. */ 254215976Sjmallett uint64_t grp : 4; /**< Created by the hardware from an entry in a 255215976Sjmallett 256-entry table. The 8-bit value 256215976Sjmallett WORD0[PRIO,TT,DIS,MBOX,LETTER] selects the 257215976Sjmallett table entry. When WORD1[R] is set and WORD1[NGRP] 258215976Sjmallett is clear, WORD1[GRP] becomes the GRP value 259215976Sjmallett in the work queue entry created by PIP. The 260215976Sjmallett GRP value in the work queue entry can direct 261215976Sjmallett the work to particular cores or particular 262215976Sjmallett groups of cores. The 256-entry table is 263215976Sjmallett unique to each sRIO core, but shared by the 264215976Sjmallett two controllers associated with the sRIO core. */ 265215976Sjmallett uint64_t rs : 1; /**< In some configurations, enables the sRIO 266215976Sjmallett message to be buffered solely in the work 267215976Sjmallett queue entry, and not otherwise in L2/DRAM. */ 268215976Sjmallett uint64_t tt : 2; /**< When WORD1[R] is set and WORD1[NTT] is 269215976Sjmallett clear, WORD1[TT]/PKT_INST_HDR[TT] becomes 270215976Sjmallett the TT value in the work queue entry created 271215976Sjmallett by PIP. The TT and TAG values in the work 272215976Sjmallett queue entry determine the scheduling/synchronization 273215976Sjmallett constraints for the work (no constraints, 274215976Sjmallett tag order, atomic tag order). */ 275215976Sjmallett uint64_t tag : 32; /**< Created by the hardware from a CSR 276215976Sjmallett associated with the sRIO inbound message 277215976Sjmallett controller. When WORD1[R] is set and WORD1[NTAG] 278215976Sjmallett is clear, WORD1[TAG]/PKT_INST_HDR[TAG] 279215976Sjmallett becomes the TAG value in the work queue 280215976Sjmallett entry created by PIP. The TT and TAG values 281215976Sjmallett in the work queue entry determine the 282215976Sjmallett scheduling/synchronization constraints for 283215976Sjmallett the work (no constraints, tag order, atomic 284215976Sjmallett tag order). */ 285215976Sjmallett#else 286215976Sjmallett uint64_t tag : 32; 287215976Sjmallett uint64_t tt : 2; 288215976Sjmallett uint64_t rs : 1; 289215976Sjmallett uint64_t grp : 4; 290215976Sjmallett uint64_t qos : 3; 291215976Sjmallett uint64_t ntag : 1; 292215976Sjmallett uint64_t ntt : 1; 293215976Sjmallett uint64_t ngrp : 1; 294215976Sjmallett uint64_t nqos : 1; 295215976Sjmallett uint64_t reserved_47_46 : 2; 296215976Sjmallett uint64_t sl : 7; 297215976Sjmallett uint64_t reserved_55 : 1; 298215976Sjmallett uint64_t pm : 2; 299215976Sjmallett uint64_t reserved_62_58 : 5; 300215976Sjmallett uint64_t r : 1; 301215976Sjmallett#endif 302215976Sjmallett } s; 303215976Sjmallett } word1; 304215976Sjmallett} cvmx_srio_rx_message_header_t; 305215976Sjmallett 306215976Sjmallett/** 307215976Sjmallett * This structure represents the SRIO header required on the front 308215976Sjmallett * of PKO packets destine for SRIO message queues. 309215976Sjmallett */ 310215976Sjmalletttypedef union 311215976Sjmallett{ 312215976Sjmallett uint64_t u64; 313215976Sjmallett struct 314215976Sjmallett { 315232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 316215976Sjmallett uint64_t prio : 2; /**< The sRIO prio (priority) field for all 317215976Sjmallett segments in the message. */ 318215976Sjmallett uint64_t tt : 1; /**< When set, the sRIO message segments use a 319215976Sjmallett 16-bit source and destination ID for all the 320215976Sjmallett segments in the message. When clear, the 321215976Sjmallett message segments use an 8-bit ID. */ 322215976Sjmallett uint64_t sis : 1; /**< When set, the sRIO message segments use the 323215976Sjmallett 63xx's secondary ID as the source ID. When 324215976Sjmallett clear, the sRIO message segments use the 325215976Sjmallett primary ID as the source ID. */ 326215976Sjmallett uint64_t ssize : 4; /**< The RIO ssize (standard message segment 327215976Sjmallett data size) field used for the message. */ 328215976Sjmallett uint64_t did : 16; /**< The destination ID in the sRIO message 329215976Sjmallett segments of the message. When TT is clear, 330215976Sjmallett the most-significant 8 bits must be zero. */ 331215976Sjmallett uint64_t xmbox : 4; /**< The RIO xmbox (recipient mailbox extension) 332215976Sjmallett field in the sRIO message segment for a 333215976Sjmallett single-segment message. Must be zero for 334215976Sjmallett multi-segment messages. */ 335215976Sjmallett uint64_t mbox : 2; /**< The RIO mbox (recipient mailbox) field in 336215976Sjmallett the sRIO message segments of the message. */ 337215976Sjmallett uint64_t letter : 2; /**< The RIO letter (slot within mailbox) field 338215976Sjmallett in the sRIO message segments of the message 339215976Sjmallett when LNS is clear. When LNS is set, this 340215976Sjmallett LETTER field is not used and must be zero. */ 341215976Sjmallett uint64_t reserved_31_2 : 30; 342215976Sjmallett uint64_t lns : 1; /**< When set, the outbound message controller 343215976Sjmallett will dynamically selects an sRIO letter 344215976Sjmallett field for the message (based on LETTER_SP or 345215976Sjmallett LETTER_MP - see appendix A), and the LETTER 346215976Sjmallett field in this sRIO outbound message 347215976Sjmallett descriptor is unused. When clear, the LETTER 348215976Sjmallett field in this sRIO outbound message 349215976Sjmallett descriptor selects the sRIO letter used for 350215976Sjmallett the message. */ 351215976Sjmallett uint64_t intr : 1; /**< When set, the outbound message controller 352215976Sjmallett will set an interrupt bit after all sRIO 353215976Sjmallett segments of the message receive a message 354215976Sjmallett DONE response. If the message transfer has 355215976Sjmallett errors, the interrupt bit is not set (but 356215976Sjmallett others are). */ 357215976Sjmallett#else 358215976Sjmallett uint64_t intr : 1; 359215976Sjmallett uint64_t lns : 1; 360215976Sjmallett uint64_t reserved_31_2 : 30; 361215976Sjmallett uint64_t letter : 2; 362215976Sjmallett uint64_t mbox : 2; 363215976Sjmallett uint64_t xmbox : 4; 364215976Sjmallett uint64_t did : 16; 365215976Sjmallett uint64_t ssize : 4; 366215976Sjmallett uint64_t sis : 1; 367215976Sjmallett uint64_t tt : 1; 368215976Sjmallett uint64_t prio : 2; 369215976Sjmallett#endif 370215976Sjmallett } s; 371215976Sjmallett} cvmx_srio_tx_message_header_t; 372215976Sjmallett 373215976Sjmallett/** 374232812Sjmallett * Reset SRIO to link partner 375232812Sjmallett * 376232812Sjmallett * @param srio_port SRIO port to initialize 377232812Sjmallett * 378232812Sjmallett * @return Zero on success 379232812Sjmallett */ 380232812Sjmallettint cvmx_srio_link_rst(int srio_port); 381232812Sjmallett 382232812Sjmallett/** 383215976Sjmallett * Initialize a SRIO port for use. 384215976Sjmallett * 385215976Sjmallett * @param srio_port SRIO port to initialize 386215976Sjmallett * @param flags Optional flags 387215976Sjmallett * 388215976Sjmallett * @return Zero on success 389215976Sjmallett */ 390215976Sjmallettint cvmx_srio_initialize(int srio_port, cvmx_srio_initialize_flags_t flags); 391215976Sjmallett 392215976Sjmallett/** 393215976Sjmallett * Read 32bits from a Device's config space 394215976Sjmallett * 395215976Sjmallett * @param srio_port SRIO port the device is on 396215976Sjmallett * @param srcid_index 397215976Sjmallett * Which SRIO source ID to use. 0 = Primary, 1 = Secondary 398215976Sjmallett * @param destid RapidIO device ID, or -1 for the local Octeon. 399215976Sjmallett * @param is16bit Non zero if the transactions should use 16bit device IDs. Zero 400215976Sjmallett * if transactions should use 8bit device IDs. 401215976Sjmallett * @param hopcount Number of hops to the remote device. Use 0 for the local Octeon. 402215976Sjmallett * @param offset Offset in config space. This must be a multiple of 32 bits. 403215976Sjmallett * @param result Result of the read. This will be unmodified on failure. 404215976Sjmallett * 405215976Sjmallett * @return Zero on success, negative on failure. 406215976Sjmallett */ 407215976Sjmallettint cvmx_srio_config_read32(int srio_port, int srcid_index, int destid, 408215976Sjmallett int is16bit, uint8_t hopcount, uint32_t offset, 409215976Sjmallett uint32_t *result); 410215976Sjmallett 411215976Sjmallett/** 412215976Sjmallett * Write 32bits to a Device's config space 413215976Sjmallett * 414215976Sjmallett * @param srio_port SRIO port the device is on 415215976Sjmallett * @param srcid_index 416215976Sjmallett * Which SRIO source ID to use. 0 = Primary, 1 = Secondary 417215976Sjmallett * @param destid RapidIO device ID, or -1 for the local Octeon. 418215976Sjmallett * @param is16bit Non zero if the transactions should use 16bit device IDs. Zero 419215976Sjmallett * if transactions should use 8bit device IDs. 420215976Sjmallett * @param hopcount Number of hops to the remote device. Use 0 for the local Octeon. 421215976Sjmallett * @param offset Offset in config space. This must be a multiple of 32 bits. 422215976Sjmallett * @param data Data to write. 423215976Sjmallett * 424215976Sjmallett * @return Zero on success, negative on failure. 425215976Sjmallett */ 426215976Sjmallettint cvmx_srio_config_write32(int srio_port, int srcid_index, int destid, 427215976Sjmallett int is16bit, uint8_t hopcount, uint32_t offset, 428215976Sjmallett uint32_t data); 429215976Sjmallett 430215976Sjmallett/** 431215976Sjmallett * Send a RapidIO doorbell to a remote device 432215976Sjmallett * 433215976Sjmallett * @param srio_port SRIO port the device is on 434215976Sjmallett * @param srcid_index 435215976Sjmallett * Which SRIO source ID to use. 0 = Primary, 1 = Secondary 436215976Sjmallett * @param destid RapidIO device ID. 437215976Sjmallett * @param is16bit Non zero if the transactions should use 16bit device IDs. Zero 438215976Sjmallett * if transactions should use 8bit device IDs. 439215976Sjmallett * @param priority Doorbell priority (0-3) 440215976Sjmallett * @param data Data for doorbell. 441215976Sjmallett * 442215976Sjmallett * @return Zero on success, negative on failure. 443215976Sjmallett */ 444215976Sjmallettint cvmx_srio_send_doorbell(int srio_port, int srcid_index, int destid, 445215976Sjmallett int is16bit, int priority, uint16_t data); 446215976Sjmallett 447215976Sjmallett/** 448215976Sjmallett * Get the status of the last doorbell sent. If the dooorbell 449215976Sjmallett * hardware is done, then the status is cleared to get ready for 450215976Sjmallett * the next doorbell (or retry). 451215976Sjmallett * 452215976Sjmallett * @param srio_port SRIO port to check doorbell on 453215976Sjmallett * 454215976Sjmallett * @return Doorbell status 455215976Sjmallett */ 456215976Sjmallettcvmx_srio_doorbell_status_t cvmx_srio_send_doorbell_status(int srio_port); 457215976Sjmallett 458215976Sjmallett/** 459215976Sjmallett * Read a received doorbell and report data about it. 460215976Sjmallett * 461215976Sjmallett * @param srio_port SRIO port to check for the received doorbell 462215976Sjmallett * @param destid_index 463215976Sjmallett * Which Octeon destination ID was the doorbell for 464215976Sjmallett * @param sequence_num 465215976Sjmallett * Sequence number of doorbell (32bits) 466215976Sjmallett * @param srcid RapidIO source ID of the doorbell sender 467215976Sjmallett * @param priority Priority of the doorbell (0-3) 468215976Sjmallett * @param is16bit Non zero if the transactions should use 16bit device IDs. Zero 469215976Sjmallett * if transactions should use 8bit device IDs. 470215976Sjmallett * @param data Data in the doorbell (16 bits) 471215976Sjmallett * 472215976Sjmallett * @return Doorbell status. Either DONE, NONE, or ERROR. 473215976Sjmallett */ 474215976Sjmallettcvmx_srio_doorbell_status_t cvmx_srio_receive_doorbell(int srio_port, 475215976Sjmallett int *destid_index, uint32_t *sequence_num, int *srcid, int *priority, 476215976Sjmallett int *is16bit, uint16_t *data); 477215976Sjmallett 478215976Sjmallett/** 479215976Sjmallett * Receive a packet from the Soft Packet FIFO (SPF). 480215976Sjmallett * 481215976Sjmallett * @param srio_port SRIO port to read the packet from. 482215976Sjmallett * @param buffer Buffer to receive the packet. 483215976Sjmallett * @param buffer_length 484215976Sjmallett * Length of the buffer in bytes. 485215976Sjmallett * 486215976Sjmallett * @return Returns the length of the packet read. Negative on failure. 487215976Sjmallett * Zero if no packets are available. 488215976Sjmallett */ 489215976Sjmallettint cvmx_srio_receive_spf(int srio_port, void *buffer, int buffer_length); 490215976Sjmallett 491215976Sjmallett/** 492215976Sjmallett * Map a remote device's memory region into Octeon's physical 493215976Sjmallett * address area. The caller can then map this into a core using 494215976Sjmallett * the TLB or XKPHYS. 495215976Sjmallett * 496215976Sjmallett * @param srio_port SRIO port to map the device on 497215976Sjmallett * @param write_op Type of operation to perform on a write to the device. 498215976Sjmallett * Normally should be CVMX_SRIO_WRITE_MODE_AUTO. 499215976Sjmallett * @param write_priority 500215976Sjmallett * SRIO priority of writes (0-3) 501215976Sjmallett * @param read_op Type of operation to perform on reads to the device. 502215976Sjmallett * Normally should be CVMX_SRIO_READ_MODE_NORMAL. 503215976Sjmallett * @param read_priority 504215976Sjmallett * SRIO priority of reads (0-3) 505215976Sjmallett * @param srcid_index 506215976Sjmallett * Which SRIO source ID to use. 0 = Primary, 1 = Secondary 507215976Sjmallett * @param destid RapidIO device ID. 508215976Sjmallett * @param is16bit Non zero if the transactions should use 16bit device IDs. Zero 509215976Sjmallett * if transactions should use 8bit device IDs. 510215976Sjmallett * @param base Device base address to start the mapping 511215976Sjmallett * @param size Size of the mapping in bytes 512215976Sjmallett * 513215976Sjmallett * @return Octeon 64bit physical address that accesses the remote device, 514215976Sjmallett * or zero on failure. 515215976Sjmallett */ 516215976Sjmallettuint64_t cvmx_srio_physical_map(int srio_port, cvmx_srio_write_mode_t write_op, 517215976Sjmallett int write_priority, cvmx_srio_read_mode_t read_op, int read_priority, 518215976Sjmallett int srcid_index, int destid, int is16bit, uint64_t base, uint64_t size); 519215976Sjmallett 520215976Sjmallett/** 521215976Sjmallett * Unmap a physical address window created by cvmx_srio_phys_map(). 522215976Sjmallett * 523215976Sjmallett * @param physical_address 524215976Sjmallett * Physical address returned by cvmx_srio_phys_map(). 525215976Sjmallett * @param size Size used on original call. 526215976Sjmallett * 527215976Sjmallett * @return Zero on success, negative on failure. 528215976Sjmallett */ 529215976Sjmallettint cvmx_srio_physical_unmap(uint64_t physical_address, uint64_t size); 530215976Sjmallett 531232812Sjmallett#ifdef CVMX_ENABLE_PKO_FUNCTIONS 532232812Sjmallett/** 533232812Sjmallett * fill out outbound message descriptor 534232812Sjmallett * 535232812Sjmallett * @param buf_ptr pointer to a buffer pointer. the buffer pointer points 536232812Sjmallett * to a chain of buffers that hold an outbound srio packet. 537232812Sjmallett * the packet can take the format of (1) a pip/ipd inbound 538232812Sjmallett * message or (2) an application-generated outbound message 539232812Sjmallett * @param desc_ptr pointer to an outbound message descriptor. should be null 540232812Sjmallett * if *buf_ptr is in the format (1) 541232812Sjmallett * 542232812Sjmallett * @return 0 on success; negative of failure. 543232812Sjmallett */ 544232812Sjmallettint cvmx_srio_omsg_desc (uint64_t port, cvmx_buf_ptr_t *buf_ptr, 545232812Sjmallett cvmx_srio_tx_message_header_t *desc_ptr); 546232812Sjmallett#endif 547232812Sjmallett 548232812Sjmallett 549215976Sjmallett#ifdef __cplusplus 550215976Sjmallett} 551215976Sjmallett#endif 552215976Sjmallett 553215976Sjmallett#endif 554