cvmx-rnm-defs.h revision 215976
1136644Sache/***********************license start*************** 2136644Sache * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 321308Sache * reserved. 421308Sache * 521308Sache * 621308Sache * Redistribution and use in source and binary forms, with or without 721308Sache * modification, are permitted provided that the following conditions are 821308Sache * met: 958310Sache * 1021308Sache * * Redistributions of source code must retain the above copyright 1121308Sache * notice, this list of conditions and the following disclaimer. 1221308Sache * 1321308Sache * * Redistributions in binary form must reproduce the above 1421308Sache * copyright notice, this list of conditions and the following 1521308Sache * disclaimer in the documentation and/or other materials provided 1621308Sache * with the distribution. 1721308Sache 1821308Sache * * Neither the name of Cavium Networks nor the names of 1921308Sache * its contributors may be used to endorse or promote products 2058310Sache * derived from this software without specific prior written 2121308Sache * permission. 2221308Sache 2321308Sache * This Software, including technical data, may be subject to U.S. export control 2421308Sache * laws, including the U.S. Export Administration Act and its associated 2547558Sache * regulations, and may be subject to export or import regulations in other 2647558Sache * countries. 2747558Sache 2847558Sache * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29136644Sache * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30136644Sache * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 3147558Sache * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 3247558Sache * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 3375406Sache * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 3447558Sache * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 3547558Sache * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 3675406Sache * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 3747558Sache * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 3847558Sache ***********************license end**************************************/ 3947558Sache 4047558Sache 4147558Sache/** 4247558Sache * cvmx-rnm-defs.h 4347558Sache * 4447558Sache * Configuration and status register (CSR) type definitions for 4521308Sache * Octeon rnm. 4621308Sache * 4721308Sache * This file is auto generated. Do not edit. 48136644Sache * 4947558Sache * <hr>$Revision$<hr> 5021308Sache * 5121308Sache */ 52136644Sache#ifndef __CVMX_RNM_TYPEDEFS_H__ 53136644Sache#define __CVMX_RNM_TYPEDEFS_H__ 54136644Sache 5521308Sache#define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull)) 5621308Sache#define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull)) 5721308Sache#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 5821308Sache#define CVMX_RNM_EER_DBG CVMX_RNM_EER_DBG_FUNC() 5921308Sachestatic inline uint64_t CVMX_RNM_EER_DBG_FUNC(void) 6021308Sache{ 6121308Sache if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 6221308Sache cvmx_warn("CVMX_RNM_EER_DBG not supported on this chip\n"); 6321308Sache return CVMX_ADD_IO_SEG(0x0001180040000018ull); 6421308Sache} 6521308Sache#else 6621308Sache#define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull)) 6721308Sache#endif 6821308Sache#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 6921308Sache#define CVMX_RNM_EER_KEY CVMX_RNM_EER_KEY_FUNC() 7021308Sachestatic inline uint64_t CVMX_RNM_EER_KEY_FUNC(void) 71119610Sache{ 7221308Sache if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 7321308Sache cvmx_warn("CVMX_RNM_EER_KEY not supported on this chip\n"); 74119610Sache return CVMX_ADD_IO_SEG(0x0001180040000010ull); 7521308Sache} 7621308Sache#else 77119610Sache#define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull)) 7821308Sache#endif 7921308Sache#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 8021308Sache#define CVMX_RNM_SERIAL_NUM CVMX_RNM_SERIAL_NUM_FUNC() 8121308Sachestatic inline uint64_t CVMX_RNM_SERIAL_NUM_FUNC(void) 8221308Sache{ 83119610Sache if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 8421308Sache cvmx_warn("CVMX_RNM_SERIAL_NUM not supported on this chip\n"); 85136644Sache return CVMX_ADD_IO_SEG(0x0001180040000020ull); 86136644Sache} 87136644Sache#else 88136644Sache#define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull)) 8921308Sache#endif 9021308Sache 9121308Sache/** 92119610Sache * cvmx_rnm_bist_status 9321308Sache * 94136644Sache * RNM_BIST_STATUS = RNM's BIST Status Register 95136644Sache * 96136644Sache * The RNM's Memory Bist Status register. 97136644Sache */ 9821308Sacheunion cvmx_rnm_bist_status 9921308Sache{ 10021308Sache uint64_t u64; 101119610Sache struct cvmx_rnm_bist_status_s 10221308Sache { 10321308Sache#if __BYTE_ORDER == __BIG_ENDIAN 104119610Sache uint64_t reserved_2_63 : 62; 10521308Sache uint64_t rrc : 1; /**< Status of RRC block bist. */ 10621308Sache uint64_t mem : 1; /**< Status of MEM block bist. */ 107119610Sache#else 10821308Sache uint64_t mem : 1; 10921308Sache uint64_t rrc : 1; 11021308Sache uint64_t reserved_2_63 : 62; 11121308Sache#endif 112119610Sache } s; 11321308Sache struct cvmx_rnm_bist_status_s cn30xx; 11421308Sache struct cvmx_rnm_bist_status_s cn31xx; 115119610Sache struct cvmx_rnm_bist_status_s cn38xx; 11621308Sache struct cvmx_rnm_bist_status_s cn38xxp2; 11721308Sache struct cvmx_rnm_bist_status_s cn50xx; 11821308Sache struct cvmx_rnm_bist_status_s cn52xx; 11921308Sache struct cvmx_rnm_bist_status_s cn52xxp1; 12021308Sache struct cvmx_rnm_bist_status_s cn56xx; 12121308Sache struct cvmx_rnm_bist_status_s cn56xxp1; 122119610Sache struct cvmx_rnm_bist_status_s cn58xx; 12321308Sache struct cvmx_rnm_bist_status_s cn58xxp1; 12421308Sache struct cvmx_rnm_bist_status_s cn63xx; 12521308Sache struct cvmx_rnm_bist_status_s cn63xxp1; 126119610Sache}; 12721308Sachetypedef union cvmx_rnm_bist_status cvmx_rnm_bist_status_t; 12821308Sache 12921308Sache/** 130119610Sache * cvmx_rnm_ctl_status 13121308Sache * 13221308Sache * RNM_CTL_STATUS = RNM's Control/Status Register 13321308Sache * 134119610Sache * The RNM's interrupt enable register. 13521308Sache */ 136136644Sacheunion cvmx_rnm_ctl_status 137136644Sache{ 138136644Sache uint64_t u64; 139136644Sache struct cvmx_rnm_ctl_status_s 14021308Sache { 14121308Sache#if __BYTE_ORDER == __BIG_ENDIAN 142119610Sache uint64_t reserved_11_63 : 53; 14321308Sache uint64_t eer_lck : 1; /**< Encryption enable register locked */ 14421308Sache uint64_t eer_val : 1; /**< Dormant encryption key match */ 14521308Sache uint64_t ent_sel : 4; /**< ? */ 14621308Sache uint64_t exp_ent : 1; /**< Exported entropy enable for random number generator */ 147119610Sache uint64_t rng_rst : 1; /**< Reset RNG as core reset. */ 14821308Sache uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register 14921308Sache logic. */ 15021308Sache uint64_t rng_en : 1; /**< Enable the output of the RNG. */ 15121308Sache uint64_t ent_en : 1; /**< Entropy enable for random number generator. */ 152119610Sache#else 15321308Sache uint64_t ent_en : 1; 15421308Sache uint64_t rng_en : 1; 15521308Sache uint64_t rnm_rst : 1; 15621308Sache uint64_t rng_rst : 1; 157119610Sache uint64_t exp_ent : 1; 15821308Sache uint64_t ent_sel : 4; 15921308Sache uint64_t eer_val : 1; 16021308Sache uint64_t eer_lck : 1; 16121308Sache uint64_t reserved_11_63 : 53; 16221308Sache#endif 16321308Sache } s; 16421308Sache struct cvmx_rnm_ctl_status_cn30xx 16521308Sache { 16621308Sache#if __BYTE_ORDER == __BIG_ENDIAN 167119610Sache uint64_t reserved_4_63 : 60; 16821308Sache uint64_t rng_rst : 1; /**< Reset RNG as core reset. */ 16921308Sache uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register 17047558Sache logic. */ 17147558Sache uint64_t rng_en : 1; /**< Enable the output of the RNG. */ 172119610Sache uint64_t ent_en : 1; /**< Entropy enable for random number generator. */ 17321308Sache#else 17421308Sache uint64_t ent_en : 1; 17521308Sache uint64_t rng_en : 1; 17621308Sache uint64_t rnm_rst : 1; 17721308Sache uint64_t rng_rst : 1; 17821308Sache uint64_t reserved_4_63 : 60; 179119610Sache#endif 18021308Sache } cn30xx; 18121308Sache struct cvmx_rnm_ctl_status_cn30xx cn31xx; 18221308Sache struct cvmx_rnm_ctl_status_cn30xx cn38xx; 18321308Sache struct cvmx_rnm_ctl_status_cn30xx cn38xxp2; 18421308Sache struct cvmx_rnm_ctl_status_cn50xx 18521308Sache { 186119610Sache#if __BYTE_ORDER == __BIG_ENDIAN 18721308Sache uint64_t reserved_9_63 : 55; 18821308Sache uint64_t ent_sel : 4; /**< ? */ 18921308Sache uint64_t exp_ent : 1; /**< Exported entropy enable for random number generator */ 19021308Sache uint64_t rng_rst : 1; /**< Reset RNG as core reset. */ 19121308Sache uint64_t rnm_rst : 1; /**< Reset the RNM as core reset except for register 19221308Sache logic. */ 193119610Sache uint64_t rng_en : 1; /**< Enable the output of the RNG. */ 19421308Sache uint64_t ent_en : 1; /**< Entropy enable for random number generator. */ 19521308Sache#else 19621308Sache uint64_t ent_en : 1; 19721308Sache uint64_t rng_en : 1; 198119610Sache uint64_t rnm_rst : 1; 19921308Sache uint64_t rng_rst : 1; 20021308Sache uint64_t exp_ent : 1; 20121308Sache uint64_t ent_sel : 4; 202119610Sache uint64_t reserved_9_63 : 55; 20321308Sache#endif 20421308Sache } cn50xx; 205119610Sache struct cvmx_rnm_ctl_status_cn50xx cn52xx; 20621308Sache struct cvmx_rnm_ctl_status_cn50xx cn52xxp1; 20721308Sache struct cvmx_rnm_ctl_status_cn50xx cn56xx; 20821308Sache struct cvmx_rnm_ctl_status_cn50xx cn56xxp1; 20921308Sache struct cvmx_rnm_ctl_status_cn50xx cn58xx; 21021308Sache struct cvmx_rnm_ctl_status_cn50xx cn58xxp1; 21121308Sache struct cvmx_rnm_ctl_status_s cn63xx; 21221308Sache struct cvmx_rnm_ctl_status_s cn63xxp1; 21321308Sache}; 21421308Sachetypedef union cvmx_rnm_ctl_status cvmx_rnm_ctl_status_t; 21521308Sache 21621308Sache/** 21721308Sache * cvmx_rnm_eer_dbg 21821308Sache * 21921308Sache * RNM_EER_DBG = RNM's Encryption enable debug register 22021308Sache * 221119610Sache * The RNM's Encryption enable debug register 22221308Sache */ 22321308Sacheunion cvmx_rnm_eer_dbg 22421308Sache{ 22521308Sache uint64_t u64; 226119610Sache struct cvmx_rnm_eer_dbg_s 22721308Sache { 22821308Sache#if __BYTE_ORDER == __BIG_ENDIAN 22947558Sache uint64_t dat : 64; /**< Dormant encryption debug info. */ 23047558Sache#else 23147558Sache uint64_t dat : 64; 23247558Sache#endif 23347558Sache } s; 234119610Sache struct cvmx_rnm_eer_dbg_s cn63xx; 23521308Sache struct cvmx_rnm_eer_dbg_s cn63xxp1; 23621308Sache}; 23721308Sachetypedef union cvmx_rnm_eer_dbg cvmx_rnm_eer_dbg_t; 238119610Sache 23921308Sache/** 24021308Sache * cvmx_rnm_eer_key 24121308Sache * 24221308Sache * RNM_EER_KEY = RNM's Encryption enable register 24375406Sache * 24421308Sache * The RNM's Encryption enable register 24521308Sache */ 24675406Sacheunion cvmx_rnm_eer_key 24721308Sache{ 24821308Sache uint64_t u64; 24921308Sache struct cvmx_rnm_eer_key_s 25021308Sache { 25121308Sache#if __BYTE_ORDER == __BIG_ENDIAN 252136644Sache uint64_t key : 64; /**< Dormant encryption key. If dormant crypto is fuse 253136644Sache enabled, crypto can be enable by writing this 25475406Sache register with the correct key. */ 25575406Sache#else 25675406Sache uint64_t key : 64; 25726497Sache#endif 25826497Sache } s; 25926497Sache struct cvmx_rnm_eer_key_s cn63xx; 26075406Sache struct cvmx_rnm_eer_key_s cn63xxp1; 26126497Sache}; 26247558Sachetypedef union cvmx_rnm_eer_key cvmx_rnm_eer_key_t; 26347558Sache 26447558Sache/** 26547558Sache * cvmx_rnm_serial_num 26621308Sache * 267 * RNM_SERIAL_NUM = RNM's fuse serial number register 268 * 269 * The RNM's fuse serial number register 270 * 271 * Notes: 272 * Added RNM_SERIAL_NUM in pass 2.0 273 * 274 */ 275union cvmx_rnm_serial_num 276{ 277 uint64_t u64; 278 struct cvmx_rnm_serial_num_s 279 { 280#if __BYTE_ORDER == __BIG_ENDIAN 281 uint64_t dat : 64; /**< Dormant encryption serial number */ 282#else 283 uint64_t dat : 64; 284#endif 285 } s; 286 struct cvmx_rnm_serial_num_s cn63xx; 287}; 288typedef union cvmx_rnm_serial_num cvmx_rnm_serial_num_t; 289 290#endif 291