cvmx-rad-defs.h revision 232812
1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-rad-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon rad. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_RAD_DEFS_H__ 53#define __CVMX_RAD_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_RAD_MEM_DEBUG0 CVMX_RAD_MEM_DEBUG0_FUNC() 57static inline uint64_t CVMX_RAD_MEM_DEBUG0_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 60 cvmx_warn("CVMX_RAD_MEM_DEBUG0 not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x0001180070001000ull); 62} 63#else 64#define CVMX_RAD_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180070001000ull)) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67#define CVMX_RAD_MEM_DEBUG1 CVMX_RAD_MEM_DEBUG1_FUNC() 68static inline uint64_t CVMX_RAD_MEM_DEBUG1_FUNC(void) 69{ 70 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 71 cvmx_warn("CVMX_RAD_MEM_DEBUG1 not supported on this chip\n"); 72 return CVMX_ADD_IO_SEG(0x0001180070001008ull); 73} 74#else 75#define CVMX_RAD_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180070001008ull)) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78#define CVMX_RAD_MEM_DEBUG2 CVMX_RAD_MEM_DEBUG2_FUNC() 79static inline uint64_t CVMX_RAD_MEM_DEBUG2_FUNC(void) 80{ 81 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 82 cvmx_warn("CVMX_RAD_MEM_DEBUG2 not supported on this chip\n"); 83 return CVMX_ADD_IO_SEG(0x0001180070001010ull); 84} 85#else 86#define CVMX_RAD_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180070001010ull)) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89#define CVMX_RAD_REG_BIST_RESULT CVMX_RAD_REG_BIST_RESULT_FUNC() 90static inline uint64_t CVMX_RAD_REG_BIST_RESULT_FUNC(void) 91{ 92 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 93 cvmx_warn("CVMX_RAD_REG_BIST_RESULT not supported on this chip\n"); 94 return CVMX_ADD_IO_SEG(0x0001180070000080ull); 95} 96#else 97#define CVMX_RAD_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180070000080ull)) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100#define CVMX_RAD_REG_CMD_BUF CVMX_RAD_REG_CMD_BUF_FUNC() 101static inline uint64_t CVMX_RAD_REG_CMD_BUF_FUNC(void) 102{ 103 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 104 cvmx_warn("CVMX_RAD_REG_CMD_BUF not supported on this chip\n"); 105 return CVMX_ADD_IO_SEG(0x0001180070000008ull); 106} 107#else 108#define CVMX_RAD_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180070000008ull)) 109#endif 110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111#define CVMX_RAD_REG_CTL CVMX_RAD_REG_CTL_FUNC() 112static inline uint64_t CVMX_RAD_REG_CTL_FUNC(void) 113{ 114 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 115 cvmx_warn("CVMX_RAD_REG_CTL not supported on this chip\n"); 116 return CVMX_ADD_IO_SEG(0x0001180070000000ull); 117} 118#else 119#define CVMX_RAD_REG_CTL (CVMX_ADD_IO_SEG(0x0001180070000000ull)) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122#define CVMX_RAD_REG_DEBUG0 CVMX_RAD_REG_DEBUG0_FUNC() 123static inline uint64_t CVMX_RAD_REG_DEBUG0_FUNC(void) 124{ 125 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 126 cvmx_warn("CVMX_RAD_REG_DEBUG0 not supported on this chip\n"); 127 return CVMX_ADD_IO_SEG(0x0001180070000100ull); 128} 129#else 130#define CVMX_RAD_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180070000100ull)) 131#endif 132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133#define CVMX_RAD_REG_DEBUG1 CVMX_RAD_REG_DEBUG1_FUNC() 134static inline uint64_t CVMX_RAD_REG_DEBUG1_FUNC(void) 135{ 136 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 137 cvmx_warn("CVMX_RAD_REG_DEBUG1 not supported on this chip\n"); 138 return CVMX_ADD_IO_SEG(0x0001180070000108ull); 139} 140#else 141#define CVMX_RAD_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180070000108ull)) 142#endif 143#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144#define CVMX_RAD_REG_DEBUG10 CVMX_RAD_REG_DEBUG10_FUNC() 145static inline uint64_t CVMX_RAD_REG_DEBUG10_FUNC(void) 146{ 147 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 148 cvmx_warn("CVMX_RAD_REG_DEBUG10 not supported on this chip\n"); 149 return CVMX_ADD_IO_SEG(0x0001180070000150ull); 150} 151#else 152#define CVMX_RAD_REG_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180070000150ull)) 153#endif 154#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155#define CVMX_RAD_REG_DEBUG11 CVMX_RAD_REG_DEBUG11_FUNC() 156static inline uint64_t CVMX_RAD_REG_DEBUG11_FUNC(void) 157{ 158 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 159 cvmx_warn("CVMX_RAD_REG_DEBUG11 not supported on this chip\n"); 160 return CVMX_ADD_IO_SEG(0x0001180070000158ull); 161} 162#else 163#define CVMX_RAD_REG_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180070000158ull)) 164#endif 165#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166#define CVMX_RAD_REG_DEBUG12 CVMX_RAD_REG_DEBUG12_FUNC() 167static inline uint64_t CVMX_RAD_REG_DEBUG12_FUNC(void) 168{ 169 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 170 cvmx_warn("CVMX_RAD_REG_DEBUG12 not supported on this chip\n"); 171 return CVMX_ADD_IO_SEG(0x0001180070000160ull); 172} 173#else 174#define CVMX_RAD_REG_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180070000160ull)) 175#endif 176#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177#define CVMX_RAD_REG_DEBUG2 CVMX_RAD_REG_DEBUG2_FUNC() 178static inline uint64_t CVMX_RAD_REG_DEBUG2_FUNC(void) 179{ 180 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 181 cvmx_warn("CVMX_RAD_REG_DEBUG2 not supported on this chip\n"); 182 return CVMX_ADD_IO_SEG(0x0001180070000110ull); 183} 184#else 185#define CVMX_RAD_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180070000110ull)) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188#define CVMX_RAD_REG_DEBUG3 CVMX_RAD_REG_DEBUG3_FUNC() 189static inline uint64_t CVMX_RAD_REG_DEBUG3_FUNC(void) 190{ 191 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 192 cvmx_warn("CVMX_RAD_REG_DEBUG3 not supported on this chip\n"); 193 return CVMX_ADD_IO_SEG(0x0001180070000118ull); 194} 195#else 196#define CVMX_RAD_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180070000118ull)) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199#define CVMX_RAD_REG_DEBUG4 CVMX_RAD_REG_DEBUG4_FUNC() 200static inline uint64_t CVMX_RAD_REG_DEBUG4_FUNC(void) 201{ 202 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 203 cvmx_warn("CVMX_RAD_REG_DEBUG4 not supported on this chip\n"); 204 return CVMX_ADD_IO_SEG(0x0001180070000120ull); 205} 206#else 207#define CVMX_RAD_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180070000120ull)) 208#endif 209#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210#define CVMX_RAD_REG_DEBUG5 CVMX_RAD_REG_DEBUG5_FUNC() 211static inline uint64_t CVMX_RAD_REG_DEBUG5_FUNC(void) 212{ 213 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 214 cvmx_warn("CVMX_RAD_REG_DEBUG5 not supported on this chip\n"); 215 return CVMX_ADD_IO_SEG(0x0001180070000128ull); 216} 217#else 218#define CVMX_RAD_REG_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180070000128ull)) 219#endif 220#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221#define CVMX_RAD_REG_DEBUG6 CVMX_RAD_REG_DEBUG6_FUNC() 222static inline uint64_t CVMX_RAD_REG_DEBUG6_FUNC(void) 223{ 224 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 225 cvmx_warn("CVMX_RAD_REG_DEBUG6 not supported on this chip\n"); 226 return CVMX_ADD_IO_SEG(0x0001180070000130ull); 227} 228#else 229#define CVMX_RAD_REG_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180070000130ull)) 230#endif 231#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232#define CVMX_RAD_REG_DEBUG7 CVMX_RAD_REG_DEBUG7_FUNC() 233static inline uint64_t CVMX_RAD_REG_DEBUG7_FUNC(void) 234{ 235 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 236 cvmx_warn("CVMX_RAD_REG_DEBUG7 not supported on this chip\n"); 237 return CVMX_ADD_IO_SEG(0x0001180070000138ull); 238} 239#else 240#define CVMX_RAD_REG_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180070000138ull)) 241#endif 242#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243#define CVMX_RAD_REG_DEBUG8 CVMX_RAD_REG_DEBUG8_FUNC() 244static inline uint64_t CVMX_RAD_REG_DEBUG8_FUNC(void) 245{ 246 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 247 cvmx_warn("CVMX_RAD_REG_DEBUG8 not supported on this chip\n"); 248 return CVMX_ADD_IO_SEG(0x0001180070000140ull); 249} 250#else 251#define CVMX_RAD_REG_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180070000140ull)) 252#endif 253#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254#define CVMX_RAD_REG_DEBUG9 CVMX_RAD_REG_DEBUG9_FUNC() 255static inline uint64_t CVMX_RAD_REG_DEBUG9_FUNC(void) 256{ 257 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 258 cvmx_warn("CVMX_RAD_REG_DEBUG9 not supported on this chip\n"); 259 return CVMX_ADD_IO_SEG(0x0001180070000148ull); 260} 261#else 262#define CVMX_RAD_REG_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180070000148ull)) 263#endif 264#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265#define CVMX_RAD_REG_ERROR CVMX_RAD_REG_ERROR_FUNC() 266static inline uint64_t CVMX_RAD_REG_ERROR_FUNC(void) 267{ 268 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 269 cvmx_warn("CVMX_RAD_REG_ERROR not supported on this chip\n"); 270 return CVMX_ADD_IO_SEG(0x0001180070000088ull); 271} 272#else 273#define CVMX_RAD_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180070000088ull)) 274#endif 275#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276#define CVMX_RAD_REG_INT_MASK CVMX_RAD_REG_INT_MASK_FUNC() 277static inline uint64_t CVMX_RAD_REG_INT_MASK_FUNC(void) 278{ 279 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 280 cvmx_warn("CVMX_RAD_REG_INT_MASK not supported on this chip\n"); 281 return CVMX_ADD_IO_SEG(0x0001180070000090ull); 282} 283#else 284#define CVMX_RAD_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180070000090ull)) 285#endif 286#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287#define CVMX_RAD_REG_POLYNOMIAL CVMX_RAD_REG_POLYNOMIAL_FUNC() 288static inline uint64_t CVMX_RAD_REG_POLYNOMIAL_FUNC(void) 289{ 290 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 291 cvmx_warn("CVMX_RAD_REG_POLYNOMIAL not supported on this chip\n"); 292 return CVMX_ADD_IO_SEG(0x0001180070000010ull); 293} 294#else 295#define CVMX_RAD_REG_POLYNOMIAL (CVMX_ADD_IO_SEG(0x0001180070000010ull)) 296#endif 297#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298#define CVMX_RAD_REG_READ_IDX CVMX_RAD_REG_READ_IDX_FUNC() 299static inline uint64_t CVMX_RAD_REG_READ_IDX_FUNC(void) 300{ 301 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 302 cvmx_warn("CVMX_RAD_REG_READ_IDX not supported on this chip\n"); 303 return CVMX_ADD_IO_SEG(0x0001180070000018ull); 304} 305#else 306#define CVMX_RAD_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180070000018ull)) 307#endif 308 309/** 310 * cvmx_rad_mem_debug0 311 * 312 * Notes: 313 * This CSR is a memory of 32 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any 314 * CSR read operations to this address can be performed. A read of any entry that has not been 315 * previously written is illegal and will result in unpredictable CSR read data. 316 */ 317union cvmx_rad_mem_debug0 { 318 uint64_t u64; 319 struct cvmx_rad_mem_debug0_s { 320#ifdef __BIG_ENDIAN_BITFIELD 321 uint64_t iword : 64; /**< IWord */ 322#else 323 uint64_t iword : 64; 324#endif 325 } s; 326 struct cvmx_rad_mem_debug0_s cn52xx; 327 struct cvmx_rad_mem_debug0_s cn52xxp1; 328 struct cvmx_rad_mem_debug0_s cn56xx; 329 struct cvmx_rad_mem_debug0_s cn56xxp1; 330 struct cvmx_rad_mem_debug0_s cn61xx; 331 struct cvmx_rad_mem_debug0_s cn63xx; 332 struct cvmx_rad_mem_debug0_s cn63xxp1; 333 struct cvmx_rad_mem_debug0_s cn66xx; 334 struct cvmx_rad_mem_debug0_s cn68xx; 335 struct cvmx_rad_mem_debug0_s cn68xxp1; 336 struct cvmx_rad_mem_debug0_s cnf71xx; 337}; 338typedef union cvmx_rad_mem_debug0 cvmx_rad_mem_debug0_t; 339 340/** 341 * cvmx_rad_mem_debug1 342 * 343 * Notes: 344 * This CSR is a memory of 256 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any 345 * CSR read operations to this address can be performed. A read of any entry that has not been 346 * previously written is illegal and will result in unpredictable CSR read data. 347 */ 348union cvmx_rad_mem_debug1 { 349 uint64_t u64; 350 struct cvmx_rad_mem_debug1_s { 351#ifdef __BIG_ENDIAN_BITFIELD 352 uint64_t p_dat : 64; /**< P data */ 353#else 354 uint64_t p_dat : 64; 355#endif 356 } s; 357 struct cvmx_rad_mem_debug1_s cn52xx; 358 struct cvmx_rad_mem_debug1_s cn52xxp1; 359 struct cvmx_rad_mem_debug1_s cn56xx; 360 struct cvmx_rad_mem_debug1_s cn56xxp1; 361 struct cvmx_rad_mem_debug1_s cn61xx; 362 struct cvmx_rad_mem_debug1_s cn63xx; 363 struct cvmx_rad_mem_debug1_s cn63xxp1; 364 struct cvmx_rad_mem_debug1_s cn66xx; 365 struct cvmx_rad_mem_debug1_s cn68xx; 366 struct cvmx_rad_mem_debug1_s cn68xxp1; 367 struct cvmx_rad_mem_debug1_s cnf71xx; 368}; 369typedef union cvmx_rad_mem_debug1 cvmx_rad_mem_debug1_t; 370 371/** 372 * cvmx_rad_mem_debug2 373 * 374 * Notes: 375 * This CSR is a memory of 256 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any 376 * CSR read operations to this address can be performed. A read of any entry that has not been 377 * previously written is illegal and will result in unpredictable CSR read data. 378 */ 379union cvmx_rad_mem_debug2 { 380 uint64_t u64; 381 struct cvmx_rad_mem_debug2_s { 382#ifdef __BIG_ENDIAN_BITFIELD 383 uint64_t q_dat : 64; /**< Q data */ 384#else 385 uint64_t q_dat : 64; 386#endif 387 } s; 388 struct cvmx_rad_mem_debug2_s cn52xx; 389 struct cvmx_rad_mem_debug2_s cn52xxp1; 390 struct cvmx_rad_mem_debug2_s cn56xx; 391 struct cvmx_rad_mem_debug2_s cn56xxp1; 392 struct cvmx_rad_mem_debug2_s cn61xx; 393 struct cvmx_rad_mem_debug2_s cn63xx; 394 struct cvmx_rad_mem_debug2_s cn63xxp1; 395 struct cvmx_rad_mem_debug2_s cn66xx; 396 struct cvmx_rad_mem_debug2_s cn68xx; 397 struct cvmx_rad_mem_debug2_s cn68xxp1; 398 struct cvmx_rad_mem_debug2_s cnf71xx; 399}; 400typedef union cvmx_rad_mem_debug2 cvmx_rad_mem_debug2_t; 401 402/** 403 * cvmx_rad_reg_bist_result 404 * 405 * Notes: 406 * Access to the internal BiST results 407 * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail). 408 */ 409union cvmx_rad_reg_bist_result { 410 uint64_t u64; 411 struct cvmx_rad_reg_bist_result_s { 412#ifdef __BIG_ENDIAN_BITFIELD 413 uint64_t reserved_6_63 : 58; 414 uint64_t sta : 1; /**< BiST result of the STA memories */ 415 uint64_t ncb_oub : 1; /**< BiST result of the NCB_OUB memories */ 416 uint64_t ncb_inb : 2; /**< BiST result of the NCB_INB memories */ 417 uint64_t dat : 2; /**< BiST result of the DAT memories */ 418#else 419 uint64_t dat : 2; 420 uint64_t ncb_inb : 2; 421 uint64_t ncb_oub : 1; 422 uint64_t sta : 1; 423 uint64_t reserved_6_63 : 58; 424#endif 425 } s; 426 struct cvmx_rad_reg_bist_result_s cn52xx; 427 struct cvmx_rad_reg_bist_result_s cn52xxp1; 428 struct cvmx_rad_reg_bist_result_s cn56xx; 429 struct cvmx_rad_reg_bist_result_s cn56xxp1; 430 struct cvmx_rad_reg_bist_result_s cn61xx; 431 struct cvmx_rad_reg_bist_result_s cn63xx; 432 struct cvmx_rad_reg_bist_result_s cn63xxp1; 433 struct cvmx_rad_reg_bist_result_s cn66xx; 434 struct cvmx_rad_reg_bist_result_s cn68xx; 435 struct cvmx_rad_reg_bist_result_s cn68xxp1; 436 struct cvmx_rad_reg_bist_result_s cnf71xx; 437}; 438typedef union cvmx_rad_reg_bist_result cvmx_rad_reg_bist_result_t; 439 440/** 441 * cvmx_rad_reg_cmd_buf 442 * 443 * Notes: 444 * Sets the command buffer parameters 445 * The size of the command buffer segments is measured in uint64s. The pool specifies 1 of 8 free 446 * lists to be used when freeing command buffer segments. The PTR field is overwritten with the next 447 * pointer each time that the command buffer segment is exhausted. 448 */ 449union cvmx_rad_reg_cmd_buf { 450 uint64_t u64; 451 struct cvmx_rad_reg_cmd_buf_s { 452#ifdef __BIG_ENDIAN_BITFIELD 453 uint64_t reserved_58_63 : 6; 454 uint64_t dwb : 9; /**< Number of DontWriteBacks */ 455 uint64_t pool : 3; /**< Free list used to free command buffer segments */ 456 uint64_t size : 13; /**< Number of uint64s per command buffer segment */ 457 uint64_t ptr : 33; /**< Initial command buffer pointer[39:7] (128B-aligned) */ 458#else 459 uint64_t ptr : 33; 460 uint64_t size : 13; 461 uint64_t pool : 3; 462 uint64_t dwb : 9; 463 uint64_t reserved_58_63 : 6; 464#endif 465 } s; 466 struct cvmx_rad_reg_cmd_buf_s cn52xx; 467 struct cvmx_rad_reg_cmd_buf_s cn52xxp1; 468 struct cvmx_rad_reg_cmd_buf_s cn56xx; 469 struct cvmx_rad_reg_cmd_buf_s cn56xxp1; 470 struct cvmx_rad_reg_cmd_buf_s cn61xx; 471 struct cvmx_rad_reg_cmd_buf_s cn63xx; 472 struct cvmx_rad_reg_cmd_buf_s cn63xxp1; 473 struct cvmx_rad_reg_cmd_buf_s cn66xx; 474 struct cvmx_rad_reg_cmd_buf_s cn68xx; 475 struct cvmx_rad_reg_cmd_buf_s cn68xxp1; 476 struct cvmx_rad_reg_cmd_buf_s cnf71xx; 477}; 478typedef union cvmx_rad_reg_cmd_buf cvmx_rad_reg_cmd_buf_t; 479 480/** 481 * cvmx_rad_reg_ctl 482 * 483 * Notes: 484 * MAX_READ is a throttle to control NCB usage. Values >8 are illegal. 485 * 486 */ 487union cvmx_rad_reg_ctl { 488 uint64_t u64; 489 struct cvmx_rad_reg_ctl_s { 490#ifdef __BIG_ENDIAN_BITFIELD 491 uint64_t reserved_6_63 : 58; 492 uint64_t max_read : 4; /**< Maximum number of outstanding data read commands */ 493 uint64_t store_le : 1; /**< Force STORE0 byte write address to little endian */ 494 uint64_t reset : 1; /**< Reset oneshot pulse (lasts for 4 cycles) */ 495#else 496 uint64_t reset : 1; 497 uint64_t store_le : 1; 498 uint64_t max_read : 4; 499 uint64_t reserved_6_63 : 58; 500#endif 501 } s; 502 struct cvmx_rad_reg_ctl_s cn52xx; 503 struct cvmx_rad_reg_ctl_s cn52xxp1; 504 struct cvmx_rad_reg_ctl_s cn56xx; 505 struct cvmx_rad_reg_ctl_s cn56xxp1; 506 struct cvmx_rad_reg_ctl_s cn61xx; 507 struct cvmx_rad_reg_ctl_s cn63xx; 508 struct cvmx_rad_reg_ctl_s cn63xxp1; 509 struct cvmx_rad_reg_ctl_s cn66xx; 510 struct cvmx_rad_reg_ctl_s cn68xx; 511 struct cvmx_rad_reg_ctl_s cn68xxp1; 512 struct cvmx_rad_reg_ctl_s cnf71xx; 513}; 514typedef union cvmx_rad_reg_ctl cvmx_rad_reg_ctl_t; 515 516/** 517 * cvmx_rad_reg_debug0 518 */ 519union cvmx_rad_reg_debug0 { 520 uint64_t u64; 521 struct cvmx_rad_reg_debug0_s { 522#ifdef __BIG_ENDIAN_BITFIELD 523 uint64_t reserved_57_63 : 7; 524 uint64_t loop : 25; /**< Loop offset */ 525 uint64_t reserved_22_31 : 10; 526 uint64_t iridx : 6; /**< IWords read index */ 527 uint64_t reserved_14_15 : 2; 528 uint64_t iwidx : 6; /**< IWords write index */ 529 uint64_t owordqv : 1; /**< Valid for OWORDQ */ 530 uint64_t owordpv : 1; /**< Valid for OWORDP */ 531 uint64_t commit : 1; /**< Waiting for write commit */ 532 uint64_t state : 5; /**< Main state */ 533#else 534 uint64_t state : 5; 535 uint64_t commit : 1; 536 uint64_t owordpv : 1; 537 uint64_t owordqv : 1; 538 uint64_t iwidx : 6; 539 uint64_t reserved_14_15 : 2; 540 uint64_t iridx : 6; 541 uint64_t reserved_22_31 : 10; 542 uint64_t loop : 25; 543 uint64_t reserved_57_63 : 7; 544#endif 545 } s; 546 struct cvmx_rad_reg_debug0_s cn52xx; 547 struct cvmx_rad_reg_debug0_s cn52xxp1; 548 struct cvmx_rad_reg_debug0_s cn56xx; 549 struct cvmx_rad_reg_debug0_s cn56xxp1; 550 struct cvmx_rad_reg_debug0_s cn61xx; 551 struct cvmx_rad_reg_debug0_s cn63xx; 552 struct cvmx_rad_reg_debug0_s cn63xxp1; 553 struct cvmx_rad_reg_debug0_s cn66xx; 554 struct cvmx_rad_reg_debug0_s cn68xx; 555 struct cvmx_rad_reg_debug0_s cn68xxp1; 556 struct cvmx_rad_reg_debug0_s cnf71xx; 557}; 558typedef union cvmx_rad_reg_debug0 cvmx_rad_reg_debug0_t; 559 560/** 561 * cvmx_rad_reg_debug1 562 */ 563union cvmx_rad_reg_debug1 { 564 uint64_t u64; 565 struct cvmx_rad_reg_debug1_s { 566#ifdef __BIG_ENDIAN_BITFIELD 567 uint64_t cword : 64; /**< CWord */ 568#else 569 uint64_t cword : 64; 570#endif 571 } s; 572 struct cvmx_rad_reg_debug1_s cn52xx; 573 struct cvmx_rad_reg_debug1_s cn52xxp1; 574 struct cvmx_rad_reg_debug1_s cn56xx; 575 struct cvmx_rad_reg_debug1_s cn56xxp1; 576 struct cvmx_rad_reg_debug1_s cn61xx; 577 struct cvmx_rad_reg_debug1_s cn63xx; 578 struct cvmx_rad_reg_debug1_s cn63xxp1; 579 struct cvmx_rad_reg_debug1_s cn66xx; 580 struct cvmx_rad_reg_debug1_s cn68xx; 581 struct cvmx_rad_reg_debug1_s cn68xxp1; 582 struct cvmx_rad_reg_debug1_s cnf71xx; 583}; 584typedef union cvmx_rad_reg_debug1 cvmx_rad_reg_debug1_t; 585 586/** 587 * cvmx_rad_reg_debug10 588 */ 589union cvmx_rad_reg_debug10 { 590 uint64_t u64; 591 struct cvmx_rad_reg_debug10_s { 592#ifdef __BIG_ENDIAN_BITFIELD 593 uint64_t flags : 8; /**< OCTL flags */ 594 uint64_t size : 16; /**< OCTL size (bytes) */ 595 uint64_t ptr : 40; /**< OCTL pointer */ 596#else 597 uint64_t ptr : 40; 598 uint64_t size : 16; 599 uint64_t flags : 8; 600#endif 601 } s; 602 struct cvmx_rad_reg_debug10_s cn52xx; 603 struct cvmx_rad_reg_debug10_s cn52xxp1; 604 struct cvmx_rad_reg_debug10_s cn56xx; 605 struct cvmx_rad_reg_debug10_s cn56xxp1; 606 struct cvmx_rad_reg_debug10_s cn61xx; 607 struct cvmx_rad_reg_debug10_s cn63xx; 608 struct cvmx_rad_reg_debug10_s cn63xxp1; 609 struct cvmx_rad_reg_debug10_s cn66xx; 610 struct cvmx_rad_reg_debug10_s cn68xx; 611 struct cvmx_rad_reg_debug10_s cn68xxp1; 612 struct cvmx_rad_reg_debug10_s cnf71xx; 613}; 614typedef union cvmx_rad_reg_debug10 cvmx_rad_reg_debug10_t; 615 616/** 617 * cvmx_rad_reg_debug11 618 */ 619union cvmx_rad_reg_debug11 { 620 uint64_t u64; 621 struct cvmx_rad_reg_debug11_s { 622#ifdef __BIG_ENDIAN_BITFIELD 623 uint64_t reserved_13_63 : 51; 624 uint64_t q : 1; /**< OCTL q flag */ 625 uint64_t p : 1; /**< OCTL p flag */ 626 uint64_t wc : 1; /**< OCTL write commit flag */ 627 uint64_t eod : 1; /**< OCTL eod flag */ 628 uint64_t sod : 1; /**< OCTL sod flag */ 629 uint64_t index : 8; /**< OCTL index */ 630#else 631 uint64_t index : 8; 632 uint64_t sod : 1; 633 uint64_t eod : 1; 634 uint64_t wc : 1; 635 uint64_t p : 1; 636 uint64_t q : 1; 637 uint64_t reserved_13_63 : 51; 638#endif 639 } s; 640 struct cvmx_rad_reg_debug11_s cn52xx; 641 struct cvmx_rad_reg_debug11_s cn52xxp1; 642 struct cvmx_rad_reg_debug11_s cn56xx; 643 struct cvmx_rad_reg_debug11_s cn56xxp1; 644 struct cvmx_rad_reg_debug11_s cn61xx; 645 struct cvmx_rad_reg_debug11_s cn63xx; 646 struct cvmx_rad_reg_debug11_s cn63xxp1; 647 struct cvmx_rad_reg_debug11_s cn66xx; 648 struct cvmx_rad_reg_debug11_s cn68xx; 649 struct cvmx_rad_reg_debug11_s cn68xxp1; 650 struct cvmx_rad_reg_debug11_s cnf71xx; 651}; 652typedef union cvmx_rad_reg_debug11 cvmx_rad_reg_debug11_t; 653 654/** 655 * cvmx_rad_reg_debug12 656 */ 657union cvmx_rad_reg_debug12 { 658 uint64_t u64; 659 struct cvmx_rad_reg_debug12_s { 660#ifdef __BIG_ENDIAN_BITFIELD 661 uint64_t reserved_15_63 : 49; 662 uint64_t asserts : 15; /**< Various assertion checks */ 663#else 664 uint64_t asserts : 15; 665 uint64_t reserved_15_63 : 49; 666#endif 667 } s; 668 struct cvmx_rad_reg_debug12_s cn52xx; 669 struct cvmx_rad_reg_debug12_s cn52xxp1; 670 struct cvmx_rad_reg_debug12_s cn56xx; 671 struct cvmx_rad_reg_debug12_s cn56xxp1; 672 struct cvmx_rad_reg_debug12_s cn61xx; 673 struct cvmx_rad_reg_debug12_s cn63xx; 674 struct cvmx_rad_reg_debug12_s cn63xxp1; 675 struct cvmx_rad_reg_debug12_s cn66xx; 676 struct cvmx_rad_reg_debug12_s cn68xx; 677 struct cvmx_rad_reg_debug12_s cn68xxp1; 678 struct cvmx_rad_reg_debug12_s cnf71xx; 679}; 680typedef union cvmx_rad_reg_debug12 cvmx_rad_reg_debug12_t; 681 682/** 683 * cvmx_rad_reg_debug2 684 */ 685union cvmx_rad_reg_debug2 { 686 uint64_t u64; 687 struct cvmx_rad_reg_debug2_s { 688#ifdef __BIG_ENDIAN_BITFIELD 689 uint64_t owordp : 64; /**< OWordP */ 690#else 691 uint64_t owordp : 64; 692#endif 693 } s; 694 struct cvmx_rad_reg_debug2_s cn52xx; 695 struct cvmx_rad_reg_debug2_s cn52xxp1; 696 struct cvmx_rad_reg_debug2_s cn56xx; 697 struct cvmx_rad_reg_debug2_s cn56xxp1; 698 struct cvmx_rad_reg_debug2_s cn61xx; 699 struct cvmx_rad_reg_debug2_s cn63xx; 700 struct cvmx_rad_reg_debug2_s cn63xxp1; 701 struct cvmx_rad_reg_debug2_s cn66xx; 702 struct cvmx_rad_reg_debug2_s cn68xx; 703 struct cvmx_rad_reg_debug2_s cn68xxp1; 704 struct cvmx_rad_reg_debug2_s cnf71xx; 705}; 706typedef union cvmx_rad_reg_debug2 cvmx_rad_reg_debug2_t; 707 708/** 709 * cvmx_rad_reg_debug3 710 */ 711union cvmx_rad_reg_debug3 { 712 uint64_t u64; 713 struct cvmx_rad_reg_debug3_s { 714#ifdef __BIG_ENDIAN_BITFIELD 715 uint64_t owordq : 64; /**< OWordQ */ 716#else 717 uint64_t owordq : 64; 718#endif 719 } s; 720 struct cvmx_rad_reg_debug3_s cn52xx; 721 struct cvmx_rad_reg_debug3_s cn52xxp1; 722 struct cvmx_rad_reg_debug3_s cn56xx; 723 struct cvmx_rad_reg_debug3_s cn56xxp1; 724 struct cvmx_rad_reg_debug3_s cn61xx; 725 struct cvmx_rad_reg_debug3_s cn63xx; 726 struct cvmx_rad_reg_debug3_s cn63xxp1; 727 struct cvmx_rad_reg_debug3_s cn66xx; 728 struct cvmx_rad_reg_debug3_s cn68xx; 729 struct cvmx_rad_reg_debug3_s cn68xxp1; 730 struct cvmx_rad_reg_debug3_s cnf71xx; 731}; 732typedef union cvmx_rad_reg_debug3 cvmx_rad_reg_debug3_t; 733 734/** 735 * cvmx_rad_reg_debug4 736 */ 737union cvmx_rad_reg_debug4 { 738 uint64_t u64; 739 struct cvmx_rad_reg_debug4_s { 740#ifdef __BIG_ENDIAN_BITFIELD 741 uint64_t rword : 64; /**< RWord */ 742#else 743 uint64_t rword : 64; 744#endif 745 } s; 746 struct cvmx_rad_reg_debug4_s cn52xx; 747 struct cvmx_rad_reg_debug4_s cn52xxp1; 748 struct cvmx_rad_reg_debug4_s cn56xx; 749 struct cvmx_rad_reg_debug4_s cn56xxp1; 750 struct cvmx_rad_reg_debug4_s cn61xx; 751 struct cvmx_rad_reg_debug4_s cn63xx; 752 struct cvmx_rad_reg_debug4_s cn63xxp1; 753 struct cvmx_rad_reg_debug4_s cn66xx; 754 struct cvmx_rad_reg_debug4_s cn68xx; 755 struct cvmx_rad_reg_debug4_s cn68xxp1; 756 struct cvmx_rad_reg_debug4_s cnf71xx; 757}; 758typedef union cvmx_rad_reg_debug4 cvmx_rad_reg_debug4_t; 759 760/** 761 * cvmx_rad_reg_debug5 762 */ 763union cvmx_rad_reg_debug5 { 764 uint64_t u64; 765 struct cvmx_rad_reg_debug5_s { 766#ifdef __BIG_ENDIAN_BITFIELD 767 uint64_t reserved_53_63 : 11; 768 uint64_t niropc7 : 3; /**< NCBI ropc (stage7 grant) */ 769 uint64_t nirque7 : 2; /**< NCBI rque (stage7 grant) */ 770 uint64_t nirval7 : 5; /**< NCBI rval (stage7 grant) */ 771 uint64_t niropc6 : 3; /**< NCBI ropc (stage6 arb) */ 772 uint64_t nirque6 : 2; /**< NCBI rque (stage6 arb) */ 773 uint64_t nirarb6 : 1; /**< NCBI rarb (stage6 arb) */ 774 uint64_t nirval6 : 5; /**< NCBI rval (stage6 arb) */ 775 uint64_t niridx1 : 4; /**< NCBI ridx1 */ 776 uint64_t niwidx1 : 4; /**< NCBI widx1 */ 777 uint64_t niridx0 : 4; /**< NCBI ridx0 */ 778 uint64_t niwidx0 : 4; /**< NCBI widx0 */ 779 uint64_t wccreds : 2; /**< WC credits */ 780 uint64_t fpacreds : 2; /**< POW credits */ 781 uint64_t reserved_10_11 : 2; 782 uint64_t powcreds : 2; /**< POW credits */ 783 uint64_t n1creds : 4; /**< NCBI1 credits */ 784 uint64_t n0creds : 4; /**< NCBI0 credits */ 785#else 786 uint64_t n0creds : 4; 787 uint64_t n1creds : 4; 788 uint64_t powcreds : 2; 789 uint64_t reserved_10_11 : 2; 790 uint64_t fpacreds : 2; 791 uint64_t wccreds : 2; 792 uint64_t niwidx0 : 4; 793 uint64_t niridx0 : 4; 794 uint64_t niwidx1 : 4; 795 uint64_t niridx1 : 4; 796 uint64_t nirval6 : 5; 797 uint64_t nirarb6 : 1; 798 uint64_t nirque6 : 2; 799 uint64_t niropc6 : 3; 800 uint64_t nirval7 : 5; 801 uint64_t nirque7 : 2; 802 uint64_t niropc7 : 3; 803 uint64_t reserved_53_63 : 11; 804#endif 805 } s; 806 struct cvmx_rad_reg_debug5_s cn52xx; 807 struct cvmx_rad_reg_debug5_s cn52xxp1; 808 struct cvmx_rad_reg_debug5_s cn56xx; 809 struct cvmx_rad_reg_debug5_s cn56xxp1; 810 struct cvmx_rad_reg_debug5_s cn61xx; 811 struct cvmx_rad_reg_debug5_s cn63xx; 812 struct cvmx_rad_reg_debug5_s cn63xxp1; 813 struct cvmx_rad_reg_debug5_s cn66xx; 814 struct cvmx_rad_reg_debug5_s cn68xx; 815 struct cvmx_rad_reg_debug5_s cn68xxp1; 816 struct cvmx_rad_reg_debug5_s cnf71xx; 817}; 818typedef union cvmx_rad_reg_debug5 cvmx_rad_reg_debug5_t; 819 820/** 821 * cvmx_rad_reg_debug6 822 */ 823union cvmx_rad_reg_debug6 { 824 uint64_t u64; 825 struct cvmx_rad_reg_debug6_s { 826#ifdef __BIG_ENDIAN_BITFIELD 827 uint64_t cnt : 8; /**< CCTL count[7:0] (bytes) */ 828 uint64_t size : 16; /**< CCTL size (bytes) */ 829 uint64_t ptr : 40; /**< CCTL pointer */ 830#else 831 uint64_t ptr : 40; 832 uint64_t size : 16; 833 uint64_t cnt : 8; 834#endif 835 } s; 836 struct cvmx_rad_reg_debug6_s cn52xx; 837 struct cvmx_rad_reg_debug6_s cn52xxp1; 838 struct cvmx_rad_reg_debug6_s cn56xx; 839 struct cvmx_rad_reg_debug6_s cn56xxp1; 840 struct cvmx_rad_reg_debug6_s cn61xx; 841 struct cvmx_rad_reg_debug6_s cn63xx; 842 struct cvmx_rad_reg_debug6_s cn63xxp1; 843 struct cvmx_rad_reg_debug6_s cn66xx; 844 struct cvmx_rad_reg_debug6_s cn68xx; 845 struct cvmx_rad_reg_debug6_s cn68xxp1; 846 struct cvmx_rad_reg_debug6_s cnf71xx; 847}; 848typedef union cvmx_rad_reg_debug6 cvmx_rad_reg_debug6_t; 849 850/** 851 * cvmx_rad_reg_debug7 852 */ 853union cvmx_rad_reg_debug7 { 854 uint64_t u64; 855 struct cvmx_rad_reg_debug7_s { 856#ifdef __BIG_ENDIAN_BITFIELD 857 uint64_t reserved_15_63 : 49; 858 uint64_t cnt : 15; /**< CCTL count[22:8] (bytes) */ 859#else 860 uint64_t cnt : 15; 861 uint64_t reserved_15_63 : 49; 862#endif 863 } s; 864 struct cvmx_rad_reg_debug7_s cn52xx; 865 struct cvmx_rad_reg_debug7_s cn52xxp1; 866 struct cvmx_rad_reg_debug7_s cn56xx; 867 struct cvmx_rad_reg_debug7_s cn56xxp1; 868 struct cvmx_rad_reg_debug7_s cn61xx; 869 struct cvmx_rad_reg_debug7_s cn63xx; 870 struct cvmx_rad_reg_debug7_s cn63xxp1; 871 struct cvmx_rad_reg_debug7_s cn66xx; 872 struct cvmx_rad_reg_debug7_s cn68xx; 873 struct cvmx_rad_reg_debug7_s cn68xxp1; 874 struct cvmx_rad_reg_debug7_s cnf71xx; 875}; 876typedef union cvmx_rad_reg_debug7 cvmx_rad_reg_debug7_t; 877 878/** 879 * cvmx_rad_reg_debug8 880 */ 881union cvmx_rad_reg_debug8 { 882 uint64_t u64; 883 struct cvmx_rad_reg_debug8_s { 884#ifdef __BIG_ENDIAN_BITFIELD 885 uint64_t flags : 8; /**< ICTL flags */ 886 uint64_t size : 16; /**< ICTL size (bytes) */ 887 uint64_t ptr : 40; /**< ICTL pointer */ 888#else 889 uint64_t ptr : 40; 890 uint64_t size : 16; 891 uint64_t flags : 8; 892#endif 893 } s; 894 struct cvmx_rad_reg_debug8_s cn52xx; 895 struct cvmx_rad_reg_debug8_s cn52xxp1; 896 struct cvmx_rad_reg_debug8_s cn56xx; 897 struct cvmx_rad_reg_debug8_s cn56xxp1; 898 struct cvmx_rad_reg_debug8_s cn61xx; 899 struct cvmx_rad_reg_debug8_s cn63xx; 900 struct cvmx_rad_reg_debug8_s cn63xxp1; 901 struct cvmx_rad_reg_debug8_s cn66xx; 902 struct cvmx_rad_reg_debug8_s cn68xx; 903 struct cvmx_rad_reg_debug8_s cn68xxp1; 904 struct cvmx_rad_reg_debug8_s cnf71xx; 905}; 906typedef union cvmx_rad_reg_debug8 cvmx_rad_reg_debug8_t; 907 908/** 909 * cvmx_rad_reg_debug9 910 */ 911union cvmx_rad_reg_debug9 { 912 uint64_t u64; 913 struct cvmx_rad_reg_debug9_s { 914#ifdef __BIG_ENDIAN_BITFIELD 915 uint64_t reserved_20_63 : 44; 916 uint64_t eod : 1; /**< ICTL eod flag */ 917 uint64_t ini : 1; /**< ICTL init flag */ 918 uint64_t q : 1; /**< ICTL q enable */ 919 uint64_t p : 1; /**< ICTL p enable */ 920 uint64_t mul : 8; /**< ICTL multiplier */ 921 uint64_t index : 8; /**< ICTL index */ 922#else 923 uint64_t index : 8; 924 uint64_t mul : 8; 925 uint64_t p : 1; 926 uint64_t q : 1; 927 uint64_t ini : 1; 928 uint64_t eod : 1; 929 uint64_t reserved_20_63 : 44; 930#endif 931 } s; 932 struct cvmx_rad_reg_debug9_s cn52xx; 933 struct cvmx_rad_reg_debug9_s cn52xxp1; 934 struct cvmx_rad_reg_debug9_s cn56xx; 935 struct cvmx_rad_reg_debug9_s cn56xxp1; 936 struct cvmx_rad_reg_debug9_s cn61xx; 937 struct cvmx_rad_reg_debug9_s cn63xx; 938 struct cvmx_rad_reg_debug9_s cn63xxp1; 939 struct cvmx_rad_reg_debug9_s cn66xx; 940 struct cvmx_rad_reg_debug9_s cn68xx; 941 struct cvmx_rad_reg_debug9_s cn68xxp1; 942 struct cvmx_rad_reg_debug9_s cnf71xx; 943}; 944typedef union cvmx_rad_reg_debug9 cvmx_rad_reg_debug9_t; 945 946/** 947 * cvmx_rad_reg_error 948 */ 949union cvmx_rad_reg_error { 950 uint64_t u64; 951 struct cvmx_rad_reg_error_s { 952#ifdef __BIG_ENDIAN_BITFIELD 953 uint64_t reserved_1_63 : 63; 954 uint64_t doorbell : 1; /**< A doorbell count has overflowed */ 955#else 956 uint64_t doorbell : 1; 957 uint64_t reserved_1_63 : 63; 958#endif 959 } s; 960 struct cvmx_rad_reg_error_s cn52xx; 961 struct cvmx_rad_reg_error_s cn52xxp1; 962 struct cvmx_rad_reg_error_s cn56xx; 963 struct cvmx_rad_reg_error_s cn56xxp1; 964 struct cvmx_rad_reg_error_s cn61xx; 965 struct cvmx_rad_reg_error_s cn63xx; 966 struct cvmx_rad_reg_error_s cn63xxp1; 967 struct cvmx_rad_reg_error_s cn66xx; 968 struct cvmx_rad_reg_error_s cn68xx; 969 struct cvmx_rad_reg_error_s cn68xxp1; 970 struct cvmx_rad_reg_error_s cnf71xx; 971}; 972typedef union cvmx_rad_reg_error cvmx_rad_reg_error_t; 973 974/** 975 * cvmx_rad_reg_int_mask 976 * 977 * Notes: 978 * When a mask bit is set, the corresponding interrupt is enabled. 979 * 980 */ 981union cvmx_rad_reg_int_mask { 982 uint64_t u64; 983 struct cvmx_rad_reg_int_mask_s { 984#ifdef __BIG_ENDIAN_BITFIELD 985 uint64_t reserved_1_63 : 63; 986 uint64_t doorbell : 1; /**< Bit mask corresponding to RAD_REG_ERROR[0] above */ 987#else 988 uint64_t doorbell : 1; 989 uint64_t reserved_1_63 : 63; 990#endif 991 } s; 992 struct cvmx_rad_reg_int_mask_s cn52xx; 993 struct cvmx_rad_reg_int_mask_s cn52xxp1; 994 struct cvmx_rad_reg_int_mask_s cn56xx; 995 struct cvmx_rad_reg_int_mask_s cn56xxp1; 996 struct cvmx_rad_reg_int_mask_s cn61xx; 997 struct cvmx_rad_reg_int_mask_s cn63xx; 998 struct cvmx_rad_reg_int_mask_s cn63xxp1; 999 struct cvmx_rad_reg_int_mask_s cn66xx; 1000 struct cvmx_rad_reg_int_mask_s cn68xx; 1001 struct cvmx_rad_reg_int_mask_s cn68xxp1; 1002 struct cvmx_rad_reg_int_mask_s cnf71xx; 1003}; 1004typedef union cvmx_rad_reg_int_mask cvmx_rad_reg_int_mask_t; 1005 1006/** 1007 * cvmx_rad_reg_polynomial 1008 * 1009 * Notes: 1010 * The polynomial is x^8 + C7*x^7 + C6*x^6 + C5*x^5 + C4*x^4 + C3*x^3 + C2*x^2 + C1*x^1 + C0. 1011 * 1012 */ 1013union cvmx_rad_reg_polynomial { 1014 uint64_t u64; 1015 struct cvmx_rad_reg_polynomial_s { 1016#ifdef __BIG_ENDIAN_BITFIELD 1017 uint64_t reserved_8_63 : 56; 1018 uint64_t coeffs : 8; /**< coefficients of GF(2^8) irreducible polynomial */ 1019#else 1020 uint64_t coeffs : 8; 1021 uint64_t reserved_8_63 : 56; 1022#endif 1023 } s; 1024 struct cvmx_rad_reg_polynomial_s cn52xx; 1025 struct cvmx_rad_reg_polynomial_s cn52xxp1; 1026 struct cvmx_rad_reg_polynomial_s cn56xx; 1027 struct cvmx_rad_reg_polynomial_s cn56xxp1; 1028 struct cvmx_rad_reg_polynomial_s cn61xx; 1029 struct cvmx_rad_reg_polynomial_s cn63xx; 1030 struct cvmx_rad_reg_polynomial_s cn63xxp1; 1031 struct cvmx_rad_reg_polynomial_s cn66xx; 1032 struct cvmx_rad_reg_polynomial_s cn68xx; 1033 struct cvmx_rad_reg_polynomial_s cn68xxp1; 1034 struct cvmx_rad_reg_polynomial_s cnf71xx; 1035}; 1036typedef union cvmx_rad_reg_polynomial cvmx_rad_reg_polynomial_t; 1037 1038/** 1039 * cvmx_rad_reg_read_idx 1040 * 1041 * Notes: 1042 * Provides the read index during a CSR read operation to any of the CSRs that are physically stored 1043 * as memories. The names of these CSRs begin with the prefix "RAD_MEM_". 1044 * IDX[15:0] is the read index. INC[15:0] is an increment that is added to IDX[15:0] after any CSR read. 1045 * The intended use is to initially write this CSR such that IDX=0 and INC=1. Then, the entire 1046 * contents of a CSR memory can be read with consecutive CSR read commands. 1047 */ 1048union cvmx_rad_reg_read_idx { 1049 uint64_t u64; 1050 struct cvmx_rad_reg_read_idx_s { 1051#ifdef __BIG_ENDIAN_BITFIELD 1052 uint64_t reserved_32_63 : 32; 1053 uint64_t inc : 16; /**< Increment to add to current index for next index */ 1054 uint64_t index : 16; /**< Index to use for next memory CSR read */ 1055#else 1056 uint64_t index : 16; 1057 uint64_t inc : 16; 1058 uint64_t reserved_32_63 : 32; 1059#endif 1060 } s; 1061 struct cvmx_rad_reg_read_idx_s cn52xx; 1062 struct cvmx_rad_reg_read_idx_s cn52xxp1; 1063 struct cvmx_rad_reg_read_idx_s cn56xx; 1064 struct cvmx_rad_reg_read_idx_s cn56xxp1; 1065 struct cvmx_rad_reg_read_idx_s cn61xx; 1066 struct cvmx_rad_reg_read_idx_s cn63xx; 1067 struct cvmx_rad_reg_read_idx_s cn63xxp1; 1068 struct cvmx_rad_reg_read_idx_s cn66xx; 1069 struct cvmx_rad_reg_read_idx_s cn68xx; 1070 struct cvmx_rad_reg_read_idx_s cn68xxp1; 1071 struct cvmx_rad_reg_read_idx_s cnf71xx; 1072}; 1073typedef union cvmx_rad_reg_read_idx cvmx_rad_reg_read_idx_t; 1074 1075#endif 1076