cvmx-rad-defs.h revision 215990
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-rad-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon rad. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_RAD_TYPEDEFS_H__ 53#define __CVMX_RAD_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_RAD_MEM_DEBUG0 CVMX_RAD_MEM_DEBUG0_FUNC() 57static inline uint64_t CVMX_RAD_MEM_DEBUG0_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 60 cvmx_warn("CVMX_RAD_MEM_DEBUG0 not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x0001180070001000ull); 62} 63#else 64#define CVMX_RAD_MEM_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180070001000ull)) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67#define CVMX_RAD_MEM_DEBUG1 CVMX_RAD_MEM_DEBUG1_FUNC() 68static inline uint64_t CVMX_RAD_MEM_DEBUG1_FUNC(void) 69{ 70 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 71 cvmx_warn("CVMX_RAD_MEM_DEBUG1 not supported on this chip\n"); 72 return CVMX_ADD_IO_SEG(0x0001180070001008ull); 73} 74#else 75#define CVMX_RAD_MEM_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180070001008ull)) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78#define CVMX_RAD_MEM_DEBUG2 CVMX_RAD_MEM_DEBUG2_FUNC() 79static inline uint64_t CVMX_RAD_MEM_DEBUG2_FUNC(void) 80{ 81 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 82 cvmx_warn("CVMX_RAD_MEM_DEBUG2 not supported on this chip\n"); 83 return CVMX_ADD_IO_SEG(0x0001180070001010ull); 84} 85#else 86#define CVMX_RAD_MEM_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180070001010ull)) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89#define CVMX_RAD_REG_BIST_RESULT CVMX_RAD_REG_BIST_RESULT_FUNC() 90static inline uint64_t CVMX_RAD_REG_BIST_RESULT_FUNC(void) 91{ 92 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 93 cvmx_warn("CVMX_RAD_REG_BIST_RESULT not supported on this chip\n"); 94 return CVMX_ADD_IO_SEG(0x0001180070000080ull); 95} 96#else 97#define CVMX_RAD_REG_BIST_RESULT (CVMX_ADD_IO_SEG(0x0001180070000080ull)) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100#define CVMX_RAD_REG_CMD_BUF CVMX_RAD_REG_CMD_BUF_FUNC() 101static inline uint64_t CVMX_RAD_REG_CMD_BUF_FUNC(void) 102{ 103 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 104 cvmx_warn("CVMX_RAD_REG_CMD_BUF not supported on this chip\n"); 105 return CVMX_ADD_IO_SEG(0x0001180070000008ull); 106} 107#else 108#define CVMX_RAD_REG_CMD_BUF (CVMX_ADD_IO_SEG(0x0001180070000008ull)) 109#endif 110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111#define CVMX_RAD_REG_CTL CVMX_RAD_REG_CTL_FUNC() 112static inline uint64_t CVMX_RAD_REG_CTL_FUNC(void) 113{ 114 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 115 cvmx_warn("CVMX_RAD_REG_CTL not supported on this chip\n"); 116 return CVMX_ADD_IO_SEG(0x0001180070000000ull); 117} 118#else 119#define CVMX_RAD_REG_CTL (CVMX_ADD_IO_SEG(0x0001180070000000ull)) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122#define CVMX_RAD_REG_DEBUG0 CVMX_RAD_REG_DEBUG0_FUNC() 123static inline uint64_t CVMX_RAD_REG_DEBUG0_FUNC(void) 124{ 125 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 126 cvmx_warn("CVMX_RAD_REG_DEBUG0 not supported on this chip\n"); 127 return CVMX_ADD_IO_SEG(0x0001180070000100ull); 128} 129#else 130#define CVMX_RAD_REG_DEBUG0 (CVMX_ADD_IO_SEG(0x0001180070000100ull)) 131#endif 132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133#define CVMX_RAD_REG_DEBUG1 CVMX_RAD_REG_DEBUG1_FUNC() 134static inline uint64_t CVMX_RAD_REG_DEBUG1_FUNC(void) 135{ 136 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 137 cvmx_warn("CVMX_RAD_REG_DEBUG1 not supported on this chip\n"); 138 return CVMX_ADD_IO_SEG(0x0001180070000108ull); 139} 140#else 141#define CVMX_RAD_REG_DEBUG1 (CVMX_ADD_IO_SEG(0x0001180070000108ull)) 142#endif 143#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144#define CVMX_RAD_REG_DEBUG10 CVMX_RAD_REG_DEBUG10_FUNC() 145static inline uint64_t CVMX_RAD_REG_DEBUG10_FUNC(void) 146{ 147 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 148 cvmx_warn("CVMX_RAD_REG_DEBUG10 not supported on this chip\n"); 149 return CVMX_ADD_IO_SEG(0x0001180070000150ull); 150} 151#else 152#define CVMX_RAD_REG_DEBUG10 (CVMX_ADD_IO_SEG(0x0001180070000150ull)) 153#endif 154#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155#define CVMX_RAD_REG_DEBUG11 CVMX_RAD_REG_DEBUG11_FUNC() 156static inline uint64_t CVMX_RAD_REG_DEBUG11_FUNC(void) 157{ 158 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 159 cvmx_warn("CVMX_RAD_REG_DEBUG11 not supported on this chip\n"); 160 return CVMX_ADD_IO_SEG(0x0001180070000158ull); 161} 162#else 163#define CVMX_RAD_REG_DEBUG11 (CVMX_ADD_IO_SEG(0x0001180070000158ull)) 164#endif 165#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166#define CVMX_RAD_REG_DEBUG12 CVMX_RAD_REG_DEBUG12_FUNC() 167static inline uint64_t CVMX_RAD_REG_DEBUG12_FUNC(void) 168{ 169 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 170 cvmx_warn("CVMX_RAD_REG_DEBUG12 not supported on this chip\n"); 171 return CVMX_ADD_IO_SEG(0x0001180070000160ull); 172} 173#else 174#define CVMX_RAD_REG_DEBUG12 (CVMX_ADD_IO_SEG(0x0001180070000160ull)) 175#endif 176#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177#define CVMX_RAD_REG_DEBUG2 CVMX_RAD_REG_DEBUG2_FUNC() 178static inline uint64_t CVMX_RAD_REG_DEBUG2_FUNC(void) 179{ 180 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 181 cvmx_warn("CVMX_RAD_REG_DEBUG2 not supported on this chip\n"); 182 return CVMX_ADD_IO_SEG(0x0001180070000110ull); 183} 184#else 185#define CVMX_RAD_REG_DEBUG2 (CVMX_ADD_IO_SEG(0x0001180070000110ull)) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188#define CVMX_RAD_REG_DEBUG3 CVMX_RAD_REG_DEBUG3_FUNC() 189static inline uint64_t CVMX_RAD_REG_DEBUG3_FUNC(void) 190{ 191 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 192 cvmx_warn("CVMX_RAD_REG_DEBUG3 not supported on this chip\n"); 193 return CVMX_ADD_IO_SEG(0x0001180070000118ull); 194} 195#else 196#define CVMX_RAD_REG_DEBUG3 (CVMX_ADD_IO_SEG(0x0001180070000118ull)) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199#define CVMX_RAD_REG_DEBUG4 CVMX_RAD_REG_DEBUG4_FUNC() 200static inline uint64_t CVMX_RAD_REG_DEBUG4_FUNC(void) 201{ 202 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 203 cvmx_warn("CVMX_RAD_REG_DEBUG4 not supported on this chip\n"); 204 return CVMX_ADD_IO_SEG(0x0001180070000120ull); 205} 206#else 207#define CVMX_RAD_REG_DEBUG4 (CVMX_ADD_IO_SEG(0x0001180070000120ull)) 208#endif 209#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210#define CVMX_RAD_REG_DEBUG5 CVMX_RAD_REG_DEBUG5_FUNC() 211static inline uint64_t CVMX_RAD_REG_DEBUG5_FUNC(void) 212{ 213 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 214 cvmx_warn("CVMX_RAD_REG_DEBUG5 not supported on this chip\n"); 215 return CVMX_ADD_IO_SEG(0x0001180070000128ull); 216} 217#else 218#define CVMX_RAD_REG_DEBUG5 (CVMX_ADD_IO_SEG(0x0001180070000128ull)) 219#endif 220#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221#define CVMX_RAD_REG_DEBUG6 CVMX_RAD_REG_DEBUG6_FUNC() 222static inline uint64_t CVMX_RAD_REG_DEBUG6_FUNC(void) 223{ 224 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 225 cvmx_warn("CVMX_RAD_REG_DEBUG6 not supported on this chip\n"); 226 return CVMX_ADD_IO_SEG(0x0001180070000130ull); 227} 228#else 229#define CVMX_RAD_REG_DEBUG6 (CVMX_ADD_IO_SEG(0x0001180070000130ull)) 230#endif 231#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232#define CVMX_RAD_REG_DEBUG7 CVMX_RAD_REG_DEBUG7_FUNC() 233static inline uint64_t CVMX_RAD_REG_DEBUG7_FUNC(void) 234{ 235 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 236 cvmx_warn("CVMX_RAD_REG_DEBUG7 not supported on this chip\n"); 237 return CVMX_ADD_IO_SEG(0x0001180070000138ull); 238} 239#else 240#define CVMX_RAD_REG_DEBUG7 (CVMX_ADD_IO_SEG(0x0001180070000138ull)) 241#endif 242#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243#define CVMX_RAD_REG_DEBUG8 CVMX_RAD_REG_DEBUG8_FUNC() 244static inline uint64_t CVMX_RAD_REG_DEBUG8_FUNC(void) 245{ 246 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 247 cvmx_warn("CVMX_RAD_REG_DEBUG8 not supported on this chip\n"); 248 return CVMX_ADD_IO_SEG(0x0001180070000140ull); 249} 250#else 251#define CVMX_RAD_REG_DEBUG8 (CVMX_ADD_IO_SEG(0x0001180070000140ull)) 252#endif 253#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254#define CVMX_RAD_REG_DEBUG9 CVMX_RAD_REG_DEBUG9_FUNC() 255static inline uint64_t CVMX_RAD_REG_DEBUG9_FUNC(void) 256{ 257 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 258 cvmx_warn("CVMX_RAD_REG_DEBUG9 not supported on this chip\n"); 259 return CVMX_ADD_IO_SEG(0x0001180070000148ull); 260} 261#else 262#define CVMX_RAD_REG_DEBUG9 (CVMX_ADD_IO_SEG(0x0001180070000148ull)) 263#endif 264#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265#define CVMX_RAD_REG_ERROR CVMX_RAD_REG_ERROR_FUNC() 266static inline uint64_t CVMX_RAD_REG_ERROR_FUNC(void) 267{ 268 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 269 cvmx_warn("CVMX_RAD_REG_ERROR not supported on this chip\n"); 270 return CVMX_ADD_IO_SEG(0x0001180070000088ull); 271} 272#else 273#define CVMX_RAD_REG_ERROR (CVMX_ADD_IO_SEG(0x0001180070000088ull)) 274#endif 275#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276#define CVMX_RAD_REG_INT_MASK CVMX_RAD_REG_INT_MASK_FUNC() 277static inline uint64_t CVMX_RAD_REG_INT_MASK_FUNC(void) 278{ 279 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 280 cvmx_warn("CVMX_RAD_REG_INT_MASK not supported on this chip\n"); 281 return CVMX_ADD_IO_SEG(0x0001180070000090ull); 282} 283#else 284#define CVMX_RAD_REG_INT_MASK (CVMX_ADD_IO_SEG(0x0001180070000090ull)) 285#endif 286#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287#define CVMX_RAD_REG_POLYNOMIAL CVMX_RAD_REG_POLYNOMIAL_FUNC() 288static inline uint64_t CVMX_RAD_REG_POLYNOMIAL_FUNC(void) 289{ 290 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 291 cvmx_warn("CVMX_RAD_REG_POLYNOMIAL not supported on this chip\n"); 292 return CVMX_ADD_IO_SEG(0x0001180070000010ull); 293} 294#else 295#define CVMX_RAD_REG_POLYNOMIAL (CVMX_ADD_IO_SEG(0x0001180070000010ull)) 296#endif 297#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298#define CVMX_RAD_REG_READ_IDX CVMX_RAD_REG_READ_IDX_FUNC() 299static inline uint64_t CVMX_RAD_REG_READ_IDX_FUNC(void) 300{ 301 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 302 cvmx_warn("CVMX_RAD_REG_READ_IDX not supported on this chip\n"); 303 return CVMX_ADD_IO_SEG(0x0001180070000018ull); 304} 305#else 306#define CVMX_RAD_REG_READ_IDX (CVMX_ADD_IO_SEG(0x0001180070000018ull)) 307#endif 308 309/** 310 * cvmx_rad_mem_debug0 311 * 312 * Notes: 313 * This CSR is a memory of 32 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any 314 * CSR read operations to this address can be performed. A read of any entry that has not been 315 * previously written is illegal and will result in unpredictable CSR read data. 316 */ 317union cvmx_rad_mem_debug0 318{ 319 uint64_t u64; 320 struct cvmx_rad_mem_debug0_s 321 { 322#if __BYTE_ORDER == __BIG_ENDIAN 323 uint64_t iword : 64; /**< IWord */ 324#else 325 uint64_t iword : 64; 326#endif 327 } s; 328 struct cvmx_rad_mem_debug0_s cn52xx; 329 struct cvmx_rad_mem_debug0_s cn52xxp1; 330 struct cvmx_rad_mem_debug0_s cn56xx; 331 struct cvmx_rad_mem_debug0_s cn56xxp1; 332 struct cvmx_rad_mem_debug0_s cn63xx; 333 struct cvmx_rad_mem_debug0_s cn63xxp1; 334}; 335typedef union cvmx_rad_mem_debug0 cvmx_rad_mem_debug0_t; 336 337/** 338 * cvmx_rad_mem_debug1 339 * 340 * Notes: 341 * This CSR is a memory of 256 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any 342 * CSR read operations to this address can be performed. A read of any entry that has not been 343 * previously written is illegal and will result in unpredictable CSR read data. 344 */ 345union cvmx_rad_mem_debug1 346{ 347 uint64_t u64; 348 struct cvmx_rad_mem_debug1_s 349 { 350#if __BYTE_ORDER == __BIG_ENDIAN 351 uint64_t p_dat : 64; /**< P data */ 352#else 353 uint64_t p_dat : 64; 354#endif 355 } s; 356 struct cvmx_rad_mem_debug1_s cn52xx; 357 struct cvmx_rad_mem_debug1_s cn52xxp1; 358 struct cvmx_rad_mem_debug1_s cn56xx; 359 struct cvmx_rad_mem_debug1_s cn56xxp1; 360 struct cvmx_rad_mem_debug1_s cn63xx; 361 struct cvmx_rad_mem_debug1_s cn63xxp1; 362}; 363typedef union cvmx_rad_mem_debug1 cvmx_rad_mem_debug1_t; 364 365/** 366 * cvmx_rad_mem_debug2 367 * 368 * Notes: 369 * This CSR is a memory of 256 entries, and thus, the RAD_REG_READ_IDX CSR must be written before any 370 * CSR read operations to this address can be performed. A read of any entry that has not been 371 * previously written is illegal and will result in unpredictable CSR read data. 372 */ 373union cvmx_rad_mem_debug2 374{ 375 uint64_t u64; 376 struct cvmx_rad_mem_debug2_s 377 { 378#if __BYTE_ORDER == __BIG_ENDIAN 379 uint64_t q_dat : 64; /**< Q data */ 380#else 381 uint64_t q_dat : 64; 382#endif 383 } s; 384 struct cvmx_rad_mem_debug2_s cn52xx; 385 struct cvmx_rad_mem_debug2_s cn52xxp1; 386 struct cvmx_rad_mem_debug2_s cn56xx; 387 struct cvmx_rad_mem_debug2_s cn56xxp1; 388 struct cvmx_rad_mem_debug2_s cn63xx; 389 struct cvmx_rad_mem_debug2_s cn63xxp1; 390}; 391typedef union cvmx_rad_mem_debug2 cvmx_rad_mem_debug2_t; 392 393/** 394 * cvmx_rad_reg_bist_result 395 * 396 * Notes: 397 * Access to the internal BiST results 398 * Each bit is the BiST result of an individual memory (per bit, 0=pass and 1=fail). 399 */ 400union cvmx_rad_reg_bist_result 401{ 402 uint64_t u64; 403 struct cvmx_rad_reg_bist_result_s 404 { 405#if __BYTE_ORDER == __BIG_ENDIAN 406 uint64_t reserved_6_63 : 58; 407 uint64_t sta : 1; /**< BiST result of the STA memories */ 408 uint64_t ncb_oub : 1; /**< BiST result of the NCB_OUB memories */ 409 uint64_t ncb_inb : 2; /**< BiST result of the NCB_INB memories */ 410 uint64_t dat : 2; /**< BiST result of the DAT memories */ 411#else 412 uint64_t dat : 2; 413 uint64_t ncb_inb : 2; 414 uint64_t ncb_oub : 1; 415 uint64_t sta : 1; 416 uint64_t reserved_6_63 : 58; 417#endif 418 } s; 419 struct cvmx_rad_reg_bist_result_s cn52xx; 420 struct cvmx_rad_reg_bist_result_s cn52xxp1; 421 struct cvmx_rad_reg_bist_result_s cn56xx; 422 struct cvmx_rad_reg_bist_result_s cn56xxp1; 423 struct cvmx_rad_reg_bist_result_s cn63xx; 424 struct cvmx_rad_reg_bist_result_s cn63xxp1; 425}; 426typedef union cvmx_rad_reg_bist_result cvmx_rad_reg_bist_result_t; 427 428/** 429 * cvmx_rad_reg_cmd_buf 430 * 431 * Notes: 432 * Sets the command buffer parameters 433 * The size of the command buffer segments is measured in uint64s. The pool specifies 1 of 8 free 434 * lists to be used when freeing command buffer segments. The PTR field is overwritten with the next 435 * pointer each time that the command buffer segment is exhausted. 436 */ 437union cvmx_rad_reg_cmd_buf 438{ 439 uint64_t u64; 440 struct cvmx_rad_reg_cmd_buf_s 441 { 442#if __BYTE_ORDER == __BIG_ENDIAN 443 uint64_t reserved_58_63 : 6; 444 uint64_t dwb : 9; /**< Number of DontWriteBacks */ 445 uint64_t pool : 3; /**< Free list used to free command buffer segments */ 446 uint64_t size : 13; /**< Number of uint64s per command buffer segment */ 447 uint64_t ptr : 33; /**< Initial command buffer pointer[39:7] (128B-aligned) */ 448#else 449 uint64_t ptr : 33; 450 uint64_t size : 13; 451 uint64_t pool : 3; 452 uint64_t dwb : 9; 453 uint64_t reserved_58_63 : 6; 454#endif 455 } s; 456 struct cvmx_rad_reg_cmd_buf_s cn52xx; 457 struct cvmx_rad_reg_cmd_buf_s cn52xxp1; 458 struct cvmx_rad_reg_cmd_buf_s cn56xx; 459 struct cvmx_rad_reg_cmd_buf_s cn56xxp1; 460 struct cvmx_rad_reg_cmd_buf_s cn63xx; 461 struct cvmx_rad_reg_cmd_buf_s cn63xxp1; 462}; 463typedef union cvmx_rad_reg_cmd_buf cvmx_rad_reg_cmd_buf_t; 464 465/** 466 * cvmx_rad_reg_ctl 467 * 468 * Notes: 469 * MAX_READ is a throttle to control NCB usage. Values >8 are illegal. 470 * 471 */ 472union cvmx_rad_reg_ctl 473{ 474 uint64_t u64; 475 struct cvmx_rad_reg_ctl_s 476 { 477#if __BYTE_ORDER == __BIG_ENDIAN 478 uint64_t reserved_6_63 : 58; 479 uint64_t max_read : 4; /**< Maximum number of outstanding data read commands */ 480 uint64_t store_le : 1; /**< Force STORE0 byte write address to little endian */ 481 uint64_t reset : 1; /**< Reset oneshot pulse (lasts for 4 cycles) */ 482#else 483 uint64_t reset : 1; 484 uint64_t store_le : 1; 485 uint64_t max_read : 4; 486 uint64_t reserved_6_63 : 58; 487#endif 488 } s; 489 struct cvmx_rad_reg_ctl_s cn52xx; 490 struct cvmx_rad_reg_ctl_s cn52xxp1; 491 struct cvmx_rad_reg_ctl_s cn56xx; 492 struct cvmx_rad_reg_ctl_s cn56xxp1; 493 struct cvmx_rad_reg_ctl_s cn63xx; 494 struct cvmx_rad_reg_ctl_s cn63xxp1; 495}; 496typedef union cvmx_rad_reg_ctl cvmx_rad_reg_ctl_t; 497 498/** 499 * cvmx_rad_reg_debug0 500 */ 501union cvmx_rad_reg_debug0 502{ 503 uint64_t u64; 504 struct cvmx_rad_reg_debug0_s 505 { 506#if __BYTE_ORDER == __BIG_ENDIAN 507 uint64_t reserved_57_63 : 7; 508 uint64_t loop : 25; /**< Loop offset */ 509 uint64_t reserved_22_31 : 10; 510 uint64_t iridx : 6; /**< IWords read index */ 511 uint64_t reserved_14_15 : 2; 512 uint64_t iwidx : 6; /**< IWords write index */ 513 uint64_t owordqv : 1; /**< Valid for OWORDQ */ 514 uint64_t owordpv : 1; /**< Valid for OWORDP */ 515 uint64_t commit : 1; /**< Waiting for write commit */ 516 uint64_t state : 5; /**< Main state */ 517#else 518 uint64_t state : 5; 519 uint64_t commit : 1; 520 uint64_t owordpv : 1; 521 uint64_t owordqv : 1; 522 uint64_t iwidx : 6; 523 uint64_t reserved_14_15 : 2; 524 uint64_t iridx : 6; 525 uint64_t reserved_22_31 : 10; 526 uint64_t loop : 25; 527 uint64_t reserved_57_63 : 7; 528#endif 529 } s; 530 struct cvmx_rad_reg_debug0_s cn52xx; 531 struct cvmx_rad_reg_debug0_s cn52xxp1; 532 struct cvmx_rad_reg_debug0_s cn56xx; 533 struct cvmx_rad_reg_debug0_s cn56xxp1; 534 struct cvmx_rad_reg_debug0_s cn63xx; 535 struct cvmx_rad_reg_debug0_s cn63xxp1; 536}; 537typedef union cvmx_rad_reg_debug0 cvmx_rad_reg_debug0_t; 538 539/** 540 * cvmx_rad_reg_debug1 541 */ 542union cvmx_rad_reg_debug1 543{ 544 uint64_t u64; 545 struct cvmx_rad_reg_debug1_s 546 { 547#if __BYTE_ORDER == __BIG_ENDIAN 548 uint64_t cword : 64; /**< CWord */ 549#else 550 uint64_t cword : 64; 551#endif 552 } s; 553 struct cvmx_rad_reg_debug1_s cn52xx; 554 struct cvmx_rad_reg_debug1_s cn52xxp1; 555 struct cvmx_rad_reg_debug1_s cn56xx; 556 struct cvmx_rad_reg_debug1_s cn56xxp1; 557 struct cvmx_rad_reg_debug1_s cn63xx; 558 struct cvmx_rad_reg_debug1_s cn63xxp1; 559}; 560typedef union cvmx_rad_reg_debug1 cvmx_rad_reg_debug1_t; 561 562/** 563 * cvmx_rad_reg_debug10 564 */ 565union cvmx_rad_reg_debug10 566{ 567 uint64_t u64; 568 struct cvmx_rad_reg_debug10_s 569 { 570#if __BYTE_ORDER == __BIG_ENDIAN 571 uint64_t flags : 8; /**< OCTL flags */ 572 uint64_t size : 16; /**< OCTL size (bytes) */ 573 uint64_t ptr : 40; /**< OCTL pointer */ 574#else 575 uint64_t ptr : 40; 576 uint64_t size : 16; 577 uint64_t flags : 8; 578#endif 579 } s; 580 struct cvmx_rad_reg_debug10_s cn52xx; 581 struct cvmx_rad_reg_debug10_s cn52xxp1; 582 struct cvmx_rad_reg_debug10_s cn56xx; 583 struct cvmx_rad_reg_debug10_s cn56xxp1; 584 struct cvmx_rad_reg_debug10_s cn63xx; 585 struct cvmx_rad_reg_debug10_s cn63xxp1; 586}; 587typedef union cvmx_rad_reg_debug10 cvmx_rad_reg_debug10_t; 588 589/** 590 * cvmx_rad_reg_debug11 591 */ 592union cvmx_rad_reg_debug11 593{ 594 uint64_t u64; 595 struct cvmx_rad_reg_debug11_s 596 { 597#if __BYTE_ORDER == __BIG_ENDIAN 598 uint64_t reserved_13_63 : 51; 599 uint64_t q : 1; /**< OCTL q flag */ 600 uint64_t p : 1; /**< OCTL p flag */ 601 uint64_t wc : 1; /**< OCTL write commit flag */ 602 uint64_t eod : 1; /**< OCTL eod flag */ 603 uint64_t sod : 1; /**< OCTL sod flag */ 604 uint64_t index : 8; /**< OCTL index */ 605#else 606 uint64_t index : 8; 607 uint64_t sod : 1; 608 uint64_t eod : 1; 609 uint64_t wc : 1; 610 uint64_t p : 1; 611 uint64_t q : 1; 612 uint64_t reserved_13_63 : 51; 613#endif 614 } s; 615 struct cvmx_rad_reg_debug11_s cn52xx; 616 struct cvmx_rad_reg_debug11_s cn52xxp1; 617 struct cvmx_rad_reg_debug11_s cn56xx; 618 struct cvmx_rad_reg_debug11_s cn56xxp1; 619 struct cvmx_rad_reg_debug11_s cn63xx; 620 struct cvmx_rad_reg_debug11_s cn63xxp1; 621}; 622typedef union cvmx_rad_reg_debug11 cvmx_rad_reg_debug11_t; 623 624/** 625 * cvmx_rad_reg_debug12 626 */ 627union cvmx_rad_reg_debug12 628{ 629 uint64_t u64; 630 struct cvmx_rad_reg_debug12_s 631 { 632#if __BYTE_ORDER == __BIG_ENDIAN 633 uint64_t reserved_15_63 : 49; 634 uint64_t asserts : 15; /**< Various assertion checks */ 635#else 636 uint64_t asserts : 15; 637 uint64_t reserved_15_63 : 49; 638#endif 639 } s; 640 struct cvmx_rad_reg_debug12_s cn52xx; 641 struct cvmx_rad_reg_debug12_s cn52xxp1; 642 struct cvmx_rad_reg_debug12_s cn56xx; 643 struct cvmx_rad_reg_debug12_s cn56xxp1; 644 struct cvmx_rad_reg_debug12_s cn63xx; 645 struct cvmx_rad_reg_debug12_s cn63xxp1; 646}; 647typedef union cvmx_rad_reg_debug12 cvmx_rad_reg_debug12_t; 648 649/** 650 * cvmx_rad_reg_debug2 651 */ 652union cvmx_rad_reg_debug2 653{ 654 uint64_t u64; 655 struct cvmx_rad_reg_debug2_s 656 { 657#if __BYTE_ORDER == __BIG_ENDIAN 658 uint64_t owordp : 64; /**< OWordP */ 659#else 660 uint64_t owordp : 64; 661#endif 662 } s; 663 struct cvmx_rad_reg_debug2_s cn52xx; 664 struct cvmx_rad_reg_debug2_s cn52xxp1; 665 struct cvmx_rad_reg_debug2_s cn56xx; 666 struct cvmx_rad_reg_debug2_s cn56xxp1; 667 struct cvmx_rad_reg_debug2_s cn63xx; 668 struct cvmx_rad_reg_debug2_s cn63xxp1; 669}; 670typedef union cvmx_rad_reg_debug2 cvmx_rad_reg_debug2_t; 671 672/** 673 * cvmx_rad_reg_debug3 674 */ 675union cvmx_rad_reg_debug3 676{ 677 uint64_t u64; 678 struct cvmx_rad_reg_debug3_s 679 { 680#if __BYTE_ORDER == __BIG_ENDIAN 681 uint64_t owordq : 64; /**< OWordQ */ 682#else 683 uint64_t owordq : 64; 684#endif 685 } s; 686 struct cvmx_rad_reg_debug3_s cn52xx; 687 struct cvmx_rad_reg_debug3_s cn52xxp1; 688 struct cvmx_rad_reg_debug3_s cn56xx; 689 struct cvmx_rad_reg_debug3_s cn56xxp1; 690 struct cvmx_rad_reg_debug3_s cn63xx; 691 struct cvmx_rad_reg_debug3_s cn63xxp1; 692}; 693typedef union cvmx_rad_reg_debug3 cvmx_rad_reg_debug3_t; 694 695/** 696 * cvmx_rad_reg_debug4 697 */ 698union cvmx_rad_reg_debug4 699{ 700 uint64_t u64; 701 struct cvmx_rad_reg_debug4_s 702 { 703#if __BYTE_ORDER == __BIG_ENDIAN 704 uint64_t rword : 64; /**< RWord */ 705#else 706 uint64_t rword : 64; 707#endif 708 } s; 709 struct cvmx_rad_reg_debug4_s cn52xx; 710 struct cvmx_rad_reg_debug4_s cn52xxp1; 711 struct cvmx_rad_reg_debug4_s cn56xx; 712 struct cvmx_rad_reg_debug4_s cn56xxp1; 713 struct cvmx_rad_reg_debug4_s cn63xx; 714 struct cvmx_rad_reg_debug4_s cn63xxp1; 715}; 716typedef union cvmx_rad_reg_debug4 cvmx_rad_reg_debug4_t; 717 718/** 719 * cvmx_rad_reg_debug5 720 */ 721union cvmx_rad_reg_debug5 722{ 723 uint64_t u64; 724 struct cvmx_rad_reg_debug5_s 725 { 726#if __BYTE_ORDER == __BIG_ENDIAN 727 uint64_t reserved_53_63 : 11; 728 uint64_t niropc7 : 3; /**< NCBI ropc (stage7 grant) */ 729 uint64_t nirque7 : 2; /**< NCBI rque (stage7 grant) */ 730 uint64_t nirval7 : 5; /**< NCBI rval (stage7 grant) */ 731 uint64_t niropc6 : 3; /**< NCBI ropc (stage6 arb) */ 732 uint64_t nirque6 : 2; /**< NCBI rque (stage6 arb) */ 733 uint64_t nirarb6 : 1; /**< NCBI rarb (stage6 arb) */ 734 uint64_t nirval6 : 5; /**< NCBI rval (stage6 arb) */ 735 uint64_t niridx1 : 4; /**< NCBI ridx1 */ 736 uint64_t niwidx1 : 4; /**< NCBI widx1 */ 737 uint64_t niridx0 : 4; /**< NCBI ridx0 */ 738 uint64_t niwidx0 : 4; /**< NCBI widx0 */ 739 uint64_t wccreds : 2; /**< WC credits */ 740 uint64_t fpacreds : 2; /**< POW credits */ 741 uint64_t reserved_10_11 : 2; 742 uint64_t powcreds : 2; /**< POW credits */ 743 uint64_t n1creds : 4; /**< NCBI1 credits */ 744 uint64_t n0creds : 4; /**< NCBI0 credits */ 745#else 746 uint64_t n0creds : 4; 747 uint64_t n1creds : 4; 748 uint64_t powcreds : 2; 749 uint64_t reserved_10_11 : 2; 750 uint64_t fpacreds : 2; 751 uint64_t wccreds : 2; 752 uint64_t niwidx0 : 4; 753 uint64_t niridx0 : 4; 754 uint64_t niwidx1 : 4; 755 uint64_t niridx1 : 4; 756 uint64_t nirval6 : 5; 757 uint64_t nirarb6 : 1; 758 uint64_t nirque6 : 2; 759 uint64_t niropc6 : 3; 760 uint64_t nirval7 : 5; 761 uint64_t nirque7 : 2; 762 uint64_t niropc7 : 3; 763 uint64_t reserved_53_63 : 11; 764#endif 765 } s; 766 struct cvmx_rad_reg_debug5_s cn52xx; 767 struct cvmx_rad_reg_debug5_s cn52xxp1; 768 struct cvmx_rad_reg_debug5_s cn56xx; 769 struct cvmx_rad_reg_debug5_s cn56xxp1; 770 struct cvmx_rad_reg_debug5_s cn63xx; 771 struct cvmx_rad_reg_debug5_s cn63xxp1; 772}; 773typedef union cvmx_rad_reg_debug5 cvmx_rad_reg_debug5_t; 774 775/** 776 * cvmx_rad_reg_debug6 777 */ 778union cvmx_rad_reg_debug6 779{ 780 uint64_t u64; 781 struct cvmx_rad_reg_debug6_s 782 { 783#if __BYTE_ORDER == __BIG_ENDIAN 784 uint64_t cnt : 8; /**< CCTL count[7:0] (bytes) */ 785 uint64_t size : 16; /**< CCTL size (bytes) */ 786 uint64_t ptr : 40; /**< CCTL pointer */ 787#else 788 uint64_t ptr : 40; 789 uint64_t size : 16; 790 uint64_t cnt : 8; 791#endif 792 } s; 793 struct cvmx_rad_reg_debug6_s cn52xx; 794 struct cvmx_rad_reg_debug6_s cn52xxp1; 795 struct cvmx_rad_reg_debug6_s cn56xx; 796 struct cvmx_rad_reg_debug6_s cn56xxp1; 797 struct cvmx_rad_reg_debug6_s cn63xx; 798 struct cvmx_rad_reg_debug6_s cn63xxp1; 799}; 800typedef union cvmx_rad_reg_debug6 cvmx_rad_reg_debug6_t; 801 802/** 803 * cvmx_rad_reg_debug7 804 */ 805union cvmx_rad_reg_debug7 806{ 807 uint64_t u64; 808 struct cvmx_rad_reg_debug7_s 809 { 810#if __BYTE_ORDER == __BIG_ENDIAN 811 uint64_t reserved_15_63 : 49; 812 uint64_t cnt : 15; /**< CCTL count[22:8] (bytes) */ 813#else 814 uint64_t cnt : 15; 815 uint64_t reserved_15_63 : 49; 816#endif 817 } s; 818 struct cvmx_rad_reg_debug7_s cn52xx; 819 struct cvmx_rad_reg_debug7_s cn52xxp1; 820 struct cvmx_rad_reg_debug7_s cn56xx; 821 struct cvmx_rad_reg_debug7_s cn56xxp1; 822 struct cvmx_rad_reg_debug7_s cn63xx; 823 struct cvmx_rad_reg_debug7_s cn63xxp1; 824}; 825typedef union cvmx_rad_reg_debug7 cvmx_rad_reg_debug7_t; 826 827/** 828 * cvmx_rad_reg_debug8 829 */ 830union cvmx_rad_reg_debug8 831{ 832 uint64_t u64; 833 struct cvmx_rad_reg_debug8_s 834 { 835#if __BYTE_ORDER == __BIG_ENDIAN 836 uint64_t flags : 8; /**< ICTL flags */ 837 uint64_t size : 16; /**< ICTL size (bytes) */ 838 uint64_t ptr : 40; /**< ICTL pointer */ 839#else 840 uint64_t ptr : 40; 841 uint64_t size : 16; 842 uint64_t flags : 8; 843#endif 844 } s; 845 struct cvmx_rad_reg_debug8_s cn52xx; 846 struct cvmx_rad_reg_debug8_s cn52xxp1; 847 struct cvmx_rad_reg_debug8_s cn56xx; 848 struct cvmx_rad_reg_debug8_s cn56xxp1; 849 struct cvmx_rad_reg_debug8_s cn63xx; 850 struct cvmx_rad_reg_debug8_s cn63xxp1; 851}; 852typedef union cvmx_rad_reg_debug8 cvmx_rad_reg_debug8_t; 853 854/** 855 * cvmx_rad_reg_debug9 856 */ 857union cvmx_rad_reg_debug9 858{ 859 uint64_t u64; 860 struct cvmx_rad_reg_debug9_s 861 { 862#if __BYTE_ORDER == __BIG_ENDIAN 863 uint64_t reserved_20_63 : 44; 864 uint64_t eod : 1; /**< ICTL eod flag */ 865 uint64_t ini : 1; /**< ICTL init flag */ 866 uint64_t q : 1; /**< ICTL q enable */ 867 uint64_t p : 1; /**< ICTL p enable */ 868 uint64_t mul : 8; /**< ICTL multiplier */ 869 uint64_t index : 8; /**< ICTL index */ 870#else 871 uint64_t index : 8; 872 uint64_t mul : 8; 873 uint64_t p : 1; 874 uint64_t q : 1; 875 uint64_t ini : 1; 876 uint64_t eod : 1; 877 uint64_t reserved_20_63 : 44; 878#endif 879 } s; 880 struct cvmx_rad_reg_debug9_s cn52xx; 881 struct cvmx_rad_reg_debug9_s cn52xxp1; 882 struct cvmx_rad_reg_debug9_s cn56xx; 883 struct cvmx_rad_reg_debug9_s cn56xxp1; 884 struct cvmx_rad_reg_debug9_s cn63xx; 885 struct cvmx_rad_reg_debug9_s cn63xxp1; 886}; 887typedef union cvmx_rad_reg_debug9 cvmx_rad_reg_debug9_t; 888 889/** 890 * cvmx_rad_reg_error 891 */ 892union cvmx_rad_reg_error 893{ 894 uint64_t u64; 895 struct cvmx_rad_reg_error_s 896 { 897#if __BYTE_ORDER == __BIG_ENDIAN 898 uint64_t reserved_1_63 : 63; 899 uint64_t doorbell : 1; /**< A doorbell count has overflowed */ 900#else 901 uint64_t doorbell : 1; 902 uint64_t reserved_1_63 : 63; 903#endif 904 } s; 905 struct cvmx_rad_reg_error_s cn52xx; 906 struct cvmx_rad_reg_error_s cn52xxp1; 907 struct cvmx_rad_reg_error_s cn56xx; 908 struct cvmx_rad_reg_error_s cn56xxp1; 909 struct cvmx_rad_reg_error_s cn63xx; 910 struct cvmx_rad_reg_error_s cn63xxp1; 911}; 912typedef union cvmx_rad_reg_error cvmx_rad_reg_error_t; 913 914/** 915 * cvmx_rad_reg_int_mask 916 * 917 * Notes: 918 * When a mask bit is set, the corresponding interrupt is enabled. 919 * 920 */ 921union cvmx_rad_reg_int_mask 922{ 923 uint64_t u64; 924 struct cvmx_rad_reg_int_mask_s 925 { 926#if __BYTE_ORDER == __BIG_ENDIAN 927 uint64_t reserved_1_63 : 63; 928 uint64_t doorbell : 1; /**< Bit mask corresponding to RAD_REG_ERROR[0] above */ 929#else 930 uint64_t doorbell : 1; 931 uint64_t reserved_1_63 : 63; 932#endif 933 } s; 934 struct cvmx_rad_reg_int_mask_s cn52xx; 935 struct cvmx_rad_reg_int_mask_s cn52xxp1; 936 struct cvmx_rad_reg_int_mask_s cn56xx; 937 struct cvmx_rad_reg_int_mask_s cn56xxp1; 938 struct cvmx_rad_reg_int_mask_s cn63xx; 939 struct cvmx_rad_reg_int_mask_s cn63xxp1; 940}; 941typedef union cvmx_rad_reg_int_mask cvmx_rad_reg_int_mask_t; 942 943/** 944 * cvmx_rad_reg_polynomial 945 * 946 * Notes: 947 * The polynomial is x^8 + C7*x^7 + C6*x^6 + C5*x^5 + C4*x^4 + C3*x^3 + C2*x^2 + C1*x^1 + C0. 948 * 949 */ 950union cvmx_rad_reg_polynomial 951{ 952 uint64_t u64; 953 struct cvmx_rad_reg_polynomial_s 954 { 955#if __BYTE_ORDER == __BIG_ENDIAN 956 uint64_t reserved_8_63 : 56; 957 uint64_t coeffs : 8; /**< coefficients of GF(2^8) irreducible polynomial */ 958#else 959 uint64_t coeffs : 8; 960 uint64_t reserved_8_63 : 56; 961#endif 962 } s; 963 struct cvmx_rad_reg_polynomial_s cn52xx; 964 struct cvmx_rad_reg_polynomial_s cn52xxp1; 965 struct cvmx_rad_reg_polynomial_s cn56xx; 966 struct cvmx_rad_reg_polynomial_s cn56xxp1; 967 struct cvmx_rad_reg_polynomial_s cn63xx; 968 struct cvmx_rad_reg_polynomial_s cn63xxp1; 969}; 970typedef union cvmx_rad_reg_polynomial cvmx_rad_reg_polynomial_t; 971 972/** 973 * cvmx_rad_reg_read_idx 974 * 975 * Notes: 976 * Provides the read index during a CSR read operation to any of the CSRs that are physically stored 977 * as memories. The names of these CSRs begin with the prefix "RAD_MEM_". 978 * IDX[15:0] is the read index. INC[15:0] is an increment that is added to IDX[15:0] after any CSR read. 979 * The intended use is to initially write this CSR such that IDX=0 and INC=1. Then, the entire 980 * contents of a CSR memory can be read with consecutive CSR read commands. 981 */ 982union cvmx_rad_reg_read_idx 983{ 984 uint64_t u64; 985 struct cvmx_rad_reg_read_idx_s 986 { 987#if __BYTE_ORDER == __BIG_ENDIAN 988 uint64_t reserved_32_63 : 32; 989 uint64_t inc : 16; /**< Increment to add to current index for next index */ 990 uint64_t index : 16; /**< Index to use for next memory CSR read */ 991#else 992 uint64_t index : 16; 993 uint64_t inc : 16; 994 uint64_t reserved_32_63 : 32; 995#endif 996 } s; 997 struct cvmx_rad_reg_read_idx_s cn52xx; 998 struct cvmx_rad_reg_read_idx_s cn52xxp1; 999 struct cvmx_rad_reg_read_idx_s cn56xx; 1000 struct cvmx_rad_reg_read_idx_s cn56xxp1; 1001 struct cvmx_rad_reg_read_idx_s cn63xx; 1002 struct cvmx_rad_reg_read_idx_s cn63xxp1; 1003}; 1004typedef union cvmx_rad_reg_read_idx cvmx_rad_reg_read_idx_t; 1005 1006#endif 1007