cvmx-power-throttle.c revision 215990 
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39
40/**
41 * @file
42 *
43 * Interface to power-throttle control, measurement, and debugging
44 * facilities.
45 *
46 * <hr>$Revision<hr>
47 *
48 */
49
50#include "cvmx.h"
51#include "cvmx-asm.h"
52#include "cvmx-power-throttle.h"
53
54#define CVMX_PTH_PPID_BCAST	63
55#define CVMX_PTH_PPID_MAX	64
56
57/**
58 * @INTERNAL
59 * Set the POWLIM field as percentage% of the MAXPOW field in r.
60 */
61static uint64_t __cvmx_power_throttle_set_powlim(uint64_t r, uint8_t percentage)
62{
63    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
64    {
65        uint64_t t;
66
67        assert(percentage < 101);
68        t = percentage * cvmx_power_throttle_get_field(CVMX_PTH_INDEX_MAXPOW, r) / 100;
69        r = cvmx_power_throttle_set_field(CVMX_PTH_INDEX_POWLIM, r, t);
70
71        return r;
72    }
73    return 0;
74}
75
76/**
77 * @INTERNAL
78 * Given ppid, calculate its PowThrottle register's L2C_COP0_MAP CSR
79 * address. (ppid == PTH_PPID_BCAST is for broadcasting)
80 */
81static uint64_t __cvmx_power_throttle_csr_addr(uint64_t ppid)
82{
83    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
84    {
85        uint64_t csr_addr, reg_num, reg_reg, reg_sel;
86
87        assert(ppid < CVMX_PTH_PPID_MAX);
88        /*
89         * register 11 selection 6
90         */
91        reg_reg = 11;
92        reg_sel = 6;
93        reg_num = (ppid << 8) + (reg_reg << 3) + reg_sel;
94        csr_addr = CVMX_L2C_COP0_MAPX(0) + ((reg_num) << 3);
95
96        return csr_addr;
97    }
98    return 0;
99}
100
101/**
102 * Throttle power to percentage% of configured maximum (MAXPOW).
103 *
104 * @param percentage	0 to 100
105 * @return 0 for success
106 */
107int cvmx_power_throttle_self(uint8_t percentage)
108{
109    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
110    {
111        uint64_t r;
112
113        CVMX_MF_COP0(r, COP0_POWTHROTTLE);
114        r = __cvmx_power_throttle_set_powlim(r, percentage);
115        CVMX_MT_COP0(r, COP0_POWTHROTTLE);
116    }
117
118    return 0;
119}
120
121/**
122 * Throttle power to percentage% of configured maximum (MAXPOW)
123 * for the cores identified in coremask.
124 *
125 * @param percentage 	0 to 100
126 * @param coremask	bit mask where each bit identifies a core.
127 * @return 0 for success.
128 */
129int cvmx_power_throttle(uint8_t percentage, uint64_t coremask)
130{
131    if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
132    {
133        uint64_t ppid, csr_addr, b, r;
134
135        b = 1;
136        /*
137         * cvmx_read_csr() for PTH_PPID_BCAST does not make sense and
138         * therefore limit ppid to less.
139         */
140        for (ppid = 0; ppid < CVMX_PTH_PPID_BCAST; ppid ++)
141        {
142            if ((b << ppid) & coremask) {
143                csr_addr = __cvmx_power_throttle_csr_addr(ppid);
144                r = cvmx_read_csr(csr_addr);
145                r = __cvmx_power_throttle_set_powlim(r, percentage);
146                cvmx_write_csr(csr_addr, r);
147            }
148        }
149    }
150
151    return 0;
152}
153