1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pow-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon pow. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_POW_DEFS_H__ 53232812Sjmallett#define __CVMX_POW_DEFS_H__ 54215976Sjmallett 55232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56232812Sjmallett#define CVMX_POW_BIST_STAT CVMX_POW_BIST_STAT_FUNC() 57232812Sjmallettstatic inline uint64_t CVMX_POW_BIST_STAT_FUNC(void) 58232812Sjmallett{ 59232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 60232812Sjmallett cvmx_warn("CVMX_POW_BIST_STAT not supported on this chip\n"); 61232812Sjmallett return CVMX_ADD_IO_SEG(0x00016700000003F8ull); 62232812Sjmallett} 63232812Sjmallett#else 64215976Sjmallett#define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull)) 65232812Sjmallett#endif 66232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67232812Sjmallett#define CVMX_POW_DS_PC CVMX_POW_DS_PC_FUNC() 68232812Sjmallettstatic inline uint64_t CVMX_POW_DS_PC_FUNC(void) 69232812Sjmallett{ 70232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 71232812Sjmallett cvmx_warn("CVMX_POW_DS_PC not supported on this chip\n"); 72232812Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000398ull); 73232812Sjmallett} 74232812Sjmallett#else 75215976Sjmallett#define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull)) 76232812Sjmallett#endif 77232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78232812Sjmallett#define CVMX_POW_ECC_ERR CVMX_POW_ECC_ERR_FUNC() 79232812Sjmallettstatic inline uint64_t CVMX_POW_ECC_ERR_FUNC(void) 80232812Sjmallett{ 81232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 82232812Sjmallett cvmx_warn("CVMX_POW_ECC_ERR not supported on this chip\n"); 83232812Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000218ull); 84232812Sjmallett} 85232812Sjmallett#else 86215976Sjmallett#define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull)) 87232812Sjmallett#endif 88232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89232812Sjmallett#define CVMX_POW_INT_CTL CVMX_POW_INT_CTL_FUNC() 90232812Sjmallettstatic inline uint64_t CVMX_POW_INT_CTL_FUNC(void) 91232812Sjmallett{ 92232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 93232812Sjmallett cvmx_warn("CVMX_POW_INT_CTL not supported on this chip\n"); 94232812Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000220ull); 95232812Sjmallett} 96232812Sjmallett#else 97215976Sjmallett#define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull)) 98232812Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallettstatic inline uint64_t CVMX_POW_IQ_CNTX(unsigned long offset) 101215976Sjmallett{ 102215976Sjmallett if (!( 103215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 104215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 105215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 106215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 107215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 108215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 109215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 110232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 111232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 112232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 113232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 114215976Sjmallett cvmx_warn("CVMX_POW_IQ_CNTX(%lu) is invalid on this chip\n", offset); 115215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8; 116215976Sjmallett} 117215976Sjmallett#else 118215976Sjmallett#define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8) 119215976Sjmallett#endif 120232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 121232812Sjmallett#define CVMX_POW_IQ_COM_CNT CVMX_POW_IQ_COM_CNT_FUNC() 122232812Sjmallettstatic inline uint64_t CVMX_POW_IQ_COM_CNT_FUNC(void) 123232812Sjmallett{ 124232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 125232812Sjmallett cvmx_warn("CVMX_POW_IQ_COM_CNT not supported on this chip\n"); 126232812Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000388ull); 127232812Sjmallett} 128232812Sjmallett#else 129215976Sjmallett#define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull)) 130232812Sjmallett#endif 131215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 132215976Sjmallett#define CVMX_POW_IQ_INT CVMX_POW_IQ_INT_FUNC() 133215976Sjmallettstatic inline uint64_t CVMX_POW_IQ_INT_FUNC(void) 134215976Sjmallett{ 135232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 136215976Sjmallett cvmx_warn("CVMX_POW_IQ_INT not supported on this chip\n"); 137215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000238ull); 138215976Sjmallett} 139215976Sjmallett#else 140215976Sjmallett#define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull)) 141215976Sjmallett#endif 142215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 143215976Sjmallett#define CVMX_POW_IQ_INT_EN CVMX_POW_IQ_INT_EN_FUNC() 144215976Sjmallettstatic inline uint64_t CVMX_POW_IQ_INT_EN_FUNC(void) 145215976Sjmallett{ 146232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 147215976Sjmallett cvmx_warn("CVMX_POW_IQ_INT_EN not supported on this chip\n"); 148215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000240ull); 149215976Sjmallett} 150215976Sjmallett#else 151215976Sjmallett#define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull)) 152215976Sjmallett#endif 153215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 154215976Sjmallettstatic inline uint64_t CVMX_POW_IQ_THRX(unsigned long offset) 155215976Sjmallett{ 156215976Sjmallett if (!( 157215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 158215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 159232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 160232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 161232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 162232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 163215976Sjmallett cvmx_warn("CVMX_POW_IQ_THRX(%lu) is invalid on this chip\n", offset); 164215976Sjmallett return CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8; 165215976Sjmallett} 166215976Sjmallett#else 167215976Sjmallett#define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8) 168215976Sjmallett#endif 169232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 170232812Sjmallett#define CVMX_POW_NOS_CNT CVMX_POW_NOS_CNT_FUNC() 171232812Sjmallettstatic inline uint64_t CVMX_POW_NOS_CNT_FUNC(void) 172232812Sjmallett{ 173232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 174232812Sjmallett cvmx_warn("CVMX_POW_NOS_CNT not supported on this chip\n"); 175232812Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000228ull); 176232812Sjmallett} 177232812Sjmallett#else 178215976Sjmallett#define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull)) 179232812Sjmallett#endif 180232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 181232812Sjmallett#define CVMX_POW_NW_TIM CVMX_POW_NW_TIM_FUNC() 182232812Sjmallettstatic inline uint64_t CVMX_POW_NW_TIM_FUNC(void) 183232812Sjmallett{ 184232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 185232812Sjmallett cvmx_warn("CVMX_POW_NW_TIM not supported on this chip\n"); 186232812Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000210ull); 187232812Sjmallett} 188232812Sjmallett#else 189215976Sjmallett#define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull)) 190232812Sjmallett#endif 191215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 192215976Sjmallett#define CVMX_POW_PF_RST_MSK CVMX_POW_PF_RST_MSK_FUNC() 193215976Sjmallettstatic inline uint64_t CVMX_POW_PF_RST_MSK_FUNC(void) 194215976Sjmallett{ 195232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 196215976Sjmallett cvmx_warn("CVMX_POW_PF_RST_MSK not supported on this chip\n"); 197215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000230ull); 198215976Sjmallett} 199215976Sjmallett#else 200215976Sjmallett#define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull)) 201215976Sjmallett#endif 202215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 203215976Sjmallettstatic inline uint64_t CVMX_POW_PP_GRP_MSKX(unsigned long offset) 204215976Sjmallett{ 205215976Sjmallett if (!( 206215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 207215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 208215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) || 209215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 210215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 211215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 212215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 213232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 214232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) || 215232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) || 216232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 217215976Sjmallett cvmx_warn("CVMX_POW_PP_GRP_MSKX(%lu) is invalid on this chip\n", offset); 218215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8; 219215976Sjmallett} 220215976Sjmallett#else 221215976Sjmallett#define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8) 222215976Sjmallett#endif 223215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 224215976Sjmallettstatic inline uint64_t CVMX_POW_QOS_RNDX(unsigned long offset) 225215976Sjmallett{ 226215976Sjmallett if (!( 227215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 228215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 229215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 230215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 231215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 232215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 233215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 234232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 235232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 236232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 237232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 238215976Sjmallett cvmx_warn("CVMX_POW_QOS_RNDX(%lu) is invalid on this chip\n", offset); 239215976Sjmallett return CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8; 240215976Sjmallett} 241215976Sjmallett#else 242215976Sjmallett#define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8) 243215976Sjmallett#endif 244215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 245215976Sjmallettstatic inline uint64_t CVMX_POW_QOS_THRX(unsigned long offset) 246215976Sjmallett{ 247215976Sjmallett if (!( 248215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 249215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 250215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 251215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 252215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 253215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 254215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 255232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 256232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 257232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 258232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 259215976Sjmallett cvmx_warn("CVMX_POW_QOS_THRX(%lu) is invalid on this chip\n", offset); 260215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8; 261215976Sjmallett} 262215976Sjmallett#else 263215976Sjmallett#define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8) 264215976Sjmallett#endif 265232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 266232812Sjmallett#define CVMX_POW_TS_PC CVMX_POW_TS_PC_FUNC() 267232812Sjmallettstatic inline uint64_t CVMX_POW_TS_PC_FUNC(void) 268232812Sjmallett{ 269232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 270232812Sjmallett cvmx_warn("CVMX_POW_TS_PC not supported on this chip\n"); 271232812Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000390ull); 272232812Sjmallett} 273232812Sjmallett#else 274215976Sjmallett#define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull)) 275232812Sjmallett#endif 276232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 277232812Sjmallett#define CVMX_POW_WA_COM_PC CVMX_POW_WA_COM_PC_FUNC() 278232812Sjmallettstatic inline uint64_t CVMX_POW_WA_COM_PC_FUNC(void) 279232812Sjmallett{ 280232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 281232812Sjmallett cvmx_warn("CVMX_POW_WA_COM_PC not supported on this chip\n"); 282232812Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000380ull); 283232812Sjmallett} 284232812Sjmallett#else 285215976Sjmallett#define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull)) 286232812Sjmallett#endif 287215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 288215976Sjmallettstatic inline uint64_t CVMX_POW_WA_PCX(unsigned long offset) 289215976Sjmallett{ 290215976Sjmallett if (!( 291215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 292215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 293215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 294215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 295215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 296215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 297215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 298232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 299232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 300232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 301232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 302215976Sjmallett cvmx_warn("CVMX_POW_WA_PCX(%lu) is invalid on this chip\n", offset); 303215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8; 304215976Sjmallett} 305215976Sjmallett#else 306215976Sjmallett#define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8) 307215976Sjmallett#endif 308232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309232812Sjmallett#define CVMX_POW_WQ_INT CVMX_POW_WQ_INT_FUNC() 310232812Sjmallettstatic inline uint64_t CVMX_POW_WQ_INT_FUNC(void) 311232812Sjmallett{ 312232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 313232812Sjmallett cvmx_warn("CVMX_POW_WQ_INT not supported on this chip\n"); 314232812Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000200ull); 315232812Sjmallett} 316232812Sjmallett#else 317215976Sjmallett#define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull)) 318232812Sjmallett#endif 319215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 320215976Sjmallettstatic inline uint64_t CVMX_POW_WQ_INT_CNTX(unsigned long offset) 321215976Sjmallett{ 322215976Sjmallett if (!( 323215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) || 324215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) || 325215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) || 326215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) || 327215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) || 328215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) || 329215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 330232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) || 331232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) || 332232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) || 333232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15))))) 334215976Sjmallett cvmx_warn("CVMX_POW_WQ_INT_CNTX(%lu) is invalid on this chip\n", offset); 335215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8; 336215976Sjmallett} 337215976Sjmallett#else 338215976Sjmallett#define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8) 339215976Sjmallett#endif 340232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 341232812Sjmallett#define CVMX_POW_WQ_INT_PC CVMX_POW_WQ_INT_PC_FUNC() 342232812Sjmallettstatic inline uint64_t CVMX_POW_WQ_INT_PC_FUNC(void) 343232812Sjmallett{ 344232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 345232812Sjmallett cvmx_warn("CVMX_POW_WQ_INT_PC not supported on this chip\n"); 346232812Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000208ull); 347232812Sjmallett} 348232812Sjmallett#else 349215976Sjmallett#define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull)) 350232812Sjmallett#endif 351215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 352215976Sjmallettstatic inline uint64_t CVMX_POW_WQ_INT_THRX(unsigned long offset) 353215976Sjmallett{ 354215976Sjmallett if (!( 355215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) || 356215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) || 357215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) || 358215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) || 359215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) || 360215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) || 361215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 362232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) || 363232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) || 364232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) || 365232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15))))) 366215976Sjmallett cvmx_warn("CVMX_POW_WQ_INT_THRX(%lu) is invalid on this chip\n", offset); 367215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8; 368215976Sjmallett} 369215976Sjmallett#else 370215976Sjmallett#define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8) 371215976Sjmallett#endif 372215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 373215976Sjmallettstatic inline uint64_t CVMX_POW_WS_PCX(unsigned long offset) 374215976Sjmallett{ 375215976Sjmallett if (!( 376215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) || 377215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) || 378215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) || 379215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) || 380215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) || 381215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) || 382215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 383232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) || 384232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) || 385232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) || 386232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15))))) 387215976Sjmallett cvmx_warn("CVMX_POW_WS_PCX(%lu) is invalid on this chip\n", offset); 388215976Sjmallett return CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8; 389215976Sjmallett} 390215976Sjmallett#else 391215976Sjmallett#define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8) 392215976Sjmallett#endif 393215976Sjmallett 394215976Sjmallett/** 395215976Sjmallett * cvmx_pow_bist_stat 396215976Sjmallett * 397215976Sjmallett * POW_BIST_STAT = POW BIST Status Register 398215976Sjmallett * 399215976Sjmallett * Contains the BIST status for the POW memories ('0' = pass, '1' = fail). 400215976Sjmallett * 401215976Sjmallett * Also contains the BIST status for the PP's. Each bit in the PP field is the OR of all BIST 402215976Sjmallett * results for the corresponding physical PP ('0' = pass, '1' = fail). 403215976Sjmallett */ 404232812Sjmallettunion cvmx_pow_bist_stat { 405215976Sjmallett uint64_t u64; 406232812Sjmallett struct cvmx_pow_bist_stat_s { 407232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 408215976Sjmallett uint64_t reserved_32_63 : 32; 409215976Sjmallett uint64_t pp : 16; /**< Physical PP BIST status */ 410215976Sjmallett uint64_t reserved_0_15 : 16; 411215976Sjmallett#else 412215976Sjmallett uint64_t reserved_0_15 : 16; 413215976Sjmallett uint64_t pp : 16; 414215976Sjmallett uint64_t reserved_32_63 : 32; 415215976Sjmallett#endif 416215976Sjmallett } s; 417232812Sjmallett struct cvmx_pow_bist_stat_cn30xx { 418232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 419215976Sjmallett uint64_t reserved_17_63 : 47; 420215976Sjmallett uint64_t pp : 1; /**< Physical PP BIST status */ 421215976Sjmallett uint64_t reserved_9_15 : 7; 422215976Sjmallett uint64_t cam : 1; /**< POW CAM BIST status */ 423215976Sjmallett uint64_t nbt1 : 1; /**< NCB transmitter memory 1 BIST status */ 424215976Sjmallett uint64_t nbt0 : 1; /**< NCB transmitter memory 0 BIST status */ 425215976Sjmallett uint64_t index : 1; /**< Index memory BIST status */ 426215976Sjmallett uint64_t fidx : 1; /**< Forward index memory BIST status */ 427215976Sjmallett uint64_t nbr1 : 1; /**< NCB receiver memory 1 BIST status */ 428215976Sjmallett uint64_t nbr0 : 1; /**< NCB receiver memory 0 BIST status */ 429215976Sjmallett uint64_t pend : 1; /**< Pending switch memory BIST status */ 430215976Sjmallett uint64_t adr : 1; /**< Address memory BIST status */ 431215976Sjmallett#else 432215976Sjmallett uint64_t adr : 1; 433215976Sjmallett uint64_t pend : 1; 434215976Sjmallett uint64_t nbr0 : 1; 435215976Sjmallett uint64_t nbr1 : 1; 436215976Sjmallett uint64_t fidx : 1; 437215976Sjmallett uint64_t index : 1; 438215976Sjmallett uint64_t nbt0 : 1; 439215976Sjmallett uint64_t nbt1 : 1; 440215976Sjmallett uint64_t cam : 1; 441215976Sjmallett uint64_t reserved_9_15 : 7; 442215976Sjmallett uint64_t pp : 1; 443215976Sjmallett uint64_t reserved_17_63 : 47; 444215976Sjmallett#endif 445215976Sjmallett } cn30xx; 446232812Sjmallett struct cvmx_pow_bist_stat_cn31xx { 447232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 448215976Sjmallett uint64_t reserved_18_63 : 46; 449215976Sjmallett uint64_t pp : 2; /**< Physical PP BIST status */ 450215976Sjmallett uint64_t reserved_9_15 : 7; 451215976Sjmallett uint64_t cam : 1; /**< POW CAM BIST status */ 452215976Sjmallett uint64_t nbt1 : 1; /**< NCB transmitter memory 1 BIST status */ 453215976Sjmallett uint64_t nbt0 : 1; /**< NCB transmitter memory 0 BIST status */ 454215976Sjmallett uint64_t index : 1; /**< Index memory BIST status */ 455215976Sjmallett uint64_t fidx : 1; /**< Forward index memory BIST status */ 456215976Sjmallett uint64_t nbr1 : 1; /**< NCB receiver memory 1 BIST status */ 457215976Sjmallett uint64_t nbr0 : 1; /**< NCB receiver memory 0 BIST status */ 458215976Sjmallett uint64_t pend : 1; /**< Pending switch memory BIST status */ 459215976Sjmallett uint64_t adr : 1; /**< Address memory BIST status */ 460215976Sjmallett#else 461215976Sjmallett uint64_t adr : 1; 462215976Sjmallett uint64_t pend : 1; 463215976Sjmallett uint64_t nbr0 : 1; 464215976Sjmallett uint64_t nbr1 : 1; 465215976Sjmallett uint64_t fidx : 1; 466215976Sjmallett uint64_t index : 1; 467215976Sjmallett uint64_t nbt0 : 1; 468215976Sjmallett uint64_t nbt1 : 1; 469215976Sjmallett uint64_t cam : 1; 470215976Sjmallett uint64_t reserved_9_15 : 7; 471215976Sjmallett uint64_t pp : 2; 472215976Sjmallett uint64_t reserved_18_63 : 46; 473215976Sjmallett#endif 474215976Sjmallett } cn31xx; 475232812Sjmallett struct cvmx_pow_bist_stat_cn38xx { 476232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 477215976Sjmallett uint64_t reserved_32_63 : 32; 478215976Sjmallett uint64_t pp : 16; /**< Physical PP BIST status */ 479215976Sjmallett uint64_t reserved_10_15 : 6; 480215976Sjmallett uint64_t cam : 1; /**< POW CAM BIST status */ 481215976Sjmallett uint64_t nbt : 1; /**< NCB transmitter memory BIST status */ 482215976Sjmallett uint64_t index : 1; /**< Index memory BIST status */ 483215976Sjmallett uint64_t fidx : 1; /**< Forward index memory BIST status */ 484215976Sjmallett uint64_t nbr1 : 1; /**< NCB receiver memory 1 BIST status */ 485215976Sjmallett uint64_t nbr0 : 1; /**< NCB receiver memory 0 BIST status */ 486215976Sjmallett uint64_t pend1 : 1; /**< Pending switch memory 1 BIST status */ 487215976Sjmallett uint64_t pend0 : 1; /**< Pending switch memory 0 BIST status */ 488215976Sjmallett uint64_t adr1 : 1; /**< Address memory 1 BIST status */ 489215976Sjmallett uint64_t adr0 : 1; /**< Address memory 0 BIST status */ 490215976Sjmallett#else 491215976Sjmallett uint64_t adr0 : 1; 492215976Sjmallett uint64_t adr1 : 1; 493215976Sjmallett uint64_t pend0 : 1; 494215976Sjmallett uint64_t pend1 : 1; 495215976Sjmallett uint64_t nbr0 : 1; 496215976Sjmallett uint64_t nbr1 : 1; 497215976Sjmallett uint64_t fidx : 1; 498215976Sjmallett uint64_t index : 1; 499215976Sjmallett uint64_t nbt : 1; 500215976Sjmallett uint64_t cam : 1; 501215976Sjmallett uint64_t reserved_10_15 : 6; 502215976Sjmallett uint64_t pp : 16; 503215976Sjmallett uint64_t reserved_32_63 : 32; 504215976Sjmallett#endif 505215976Sjmallett } cn38xx; 506215976Sjmallett struct cvmx_pow_bist_stat_cn38xx cn38xxp2; 507215976Sjmallett struct cvmx_pow_bist_stat_cn31xx cn50xx; 508232812Sjmallett struct cvmx_pow_bist_stat_cn52xx { 509232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 510215976Sjmallett uint64_t reserved_20_63 : 44; 511215976Sjmallett uint64_t pp : 4; /**< Physical PP BIST status */ 512215976Sjmallett uint64_t reserved_9_15 : 7; 513215976Sjmallett uint64_t cam : 1; /**< POW CAM BIST status */ 514215976Sjmallett uint64_t nbt1 : 1; /**< NCB transmitter memory 1 BIST status */ 515215976Sjmallett uint64_t nbt0 : 1; /**< NCB transmitter memory 0 BIST status */ 516215976Sjmallett uint64_t index : 1; /**< Index memory BIST status */ 517215976Sjmallett uint64_t fidx : 1; /**< Forward index memory BIST status */ 518215976Sjmallett uint64_t nbr1 : 1; /**< NCB receiver memory 1 BIST status */ 519215976Sjmallett uint64_t nbr0 : 1; /**< NCB receiver memory 0 BIST status */ 520215976Sjmallett uint64_t pend : 1; /**< Pending switch memory BIST status */ 521215976Sjmallett uint64_t adr : 1; /**< Address memory BIST status */ 522215976Sjmallett#else 523215976Sjmallett uint64_t adr : 1; 524215976Sjmallett uint64_t pend : 1; 525215976Sjmallett uint64_t nbr0 : 1; 526215976Sjmallett uint64_t nbr1 : 1; 527215976Sjmallett uint64_t fidx : 1; 528215976Sjmallett uint64_t index : 1; 529215976Sjmallett uint64_t nbt0 : 1; 530215976Sjmallett uint64_t nbt1 : 1; 531215976Sjmallett uint64_t cam : 1; 532215976Sjmallett uint64_t reserved_9_15 : 7; 533215976Sjmallett uint64_t pp : 4; 534215976Sjmallett uint64_t reserved_20_63 : 44; 535215976Sjmallett#endif 536215976Sjmallett } cn52xx; 537215976Sjmallett struct cvmx_pow_bist_stat_cn52xx cn52xxp1; 538232812Sjmallett struct cvmx_pow_bist_stat_cn56xx { 539232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 540215976Sjmallett uint64_t reserved_28_63 : 36; 541215976Sjmallett uint64_t pp : 12; /**< Physical PP BIST status */ 542215976Sjmallett uint64_t reserved_10_15 : 6; 543215976Sjmallett uint64_t cam : 1; /**< POW CAM BIST status */ 544215976Sjmallett uint64_t nbt : 1; /**< NCB transmitter memory BIST status */ 545215976Sjmallett uint64_t index : 1; /**< Index memory BIST status */ 546215976Sjmallett uint64_t fidx : 1; /**< Forward index memory BIST status */ 547215976Sjmallett uint64_t nbr1 : 1; /**< NCB receiver memory 1 BIST status */ 548215976Sjmallett uint64_t nbr0 : 1; /**< NCB receiver memory 0 BIST status */ 549215976Sjmallett uint64_t pend1 : 1; /**< Pending switch memory 1 BIST status */ 550215976Sjmallett uint64_t pend0 : 1; /**< Pending switch memory 0 BIST status */ 551215976Sjmallett uint64_t adr1 : 1; /**< Address memory 1 BIST status */ 552215976Sjmallett uint64_t adr0 : 1; /**< Address memory 0 BIST status */ 553215976Sjmallett#else 554215976Sjmallett uint64_t adr0 : 1; 555215976Sjmallett uint64_t adr1 : 1; 556215976Sjmallett uint64_t pend0 : 1; 557215976Sjmallett uint64_t pend1 : 1; 558215976Sjmallett uint64_t nbr0 : 1; 559215976Sjmallett uint64_t nbr1 : 1; 560215976Sjmallett uint64_t fidx : 1; 561215976Sjmallett uint64_t index : 1; 562215976Sjmallett uint64_t nbt : 1; 563215976Sjmallett uint64_t cam : 1; 564215976Sjmallett uint64_t reserved_10_15 : 6; 565215976Sjmallett uint64_t pp : 12; 566215976Sjmallett uint64_t reserved_28_63 : 36; 567215976Sjmallett#endif 568215976Sjmallett } cn56xx; 569215976Sjmallett struct cvmx_pow_bist_stat_cn56xx cn56xxp1; 570215976Sjmallett struct cvmx_pow_bist_stat_cn38xx cn58xx; 571215976Sjmallett struct cvmx_pow_bist_stat_cn38xx cn58xxp1; 572232812Sjmallett struct cvmx_pow_bist_stat_cn61xx { 573232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 574232812Sjmallett uint64_t reserved_20_63 : 44; 575232812Sjmallett uint64_t pp : 4; /**< Physical PP BIST status */ 576232812Sjmallett uint64_t reserved_12_15 : 4; 577232812Sjmallett uint64_t cam : 1; /**< POW CAM BIST status */ 578232812Sjmallett uint64_t nbr : 3; /**< NCB receiver memory BIST status */ 579232812Sjmallett uint64_t nbt : 4; /**< NCB transmitter memory BIST status */ 580232812Sjmallett uint64_t index : 1; /**< Index memory BIST status */ 581232812Sjmallett uint64_t fidx : 1; /**< Forward index memory BIST status */ 582232812Sjmallett uint64_t pend : 1; /**< Pending switch memory BIST status */ 583232812Sjmallett uint64_t adr : 1; /**< Address memory BIST status */ 584232812Sjmallett#else 585232812Sjmallett uint64_t adr : 1; 586232812Sjmallett uint64_t pend : 1; 587232812Sjmallett uint64_t fidx : 1; 588232812Sjmallett uint64_t index : 1; 589232812Sjmallett uint64_t nbt : 4; 590232812Sjmallett uint64_t nbr : 3; 591232812Sjmallett uint64_t cam : 1; 592232812Sjmallett uint64_t reserved_12_15 : 4; 593232812Sjmallett uint64_t pp : 4; 594232812Sjmallett uint64_t reserved_20_63 : 44; 595232812Sjmallett#endif 596232812Sjmallett } cn61xx; 597232812Sjmallett struct cvmx_pow_bist_stat_cn63xx { 598232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 599215976Sjmallett uint64_t reserved_22_63 : 42; 600215976Sjmallett uint64_t pp : 6; /**< Physical PP BIST status */ 601215976Sjmallett uint64_t reserved_12_15 : 4; 602215976Sjmallett uint64_t cam : 1; /**< POW CAM BIST status */ 603215976Sjmallett uint64_t nbr : 3; /**< NCB receiver memory BIST status */ 604215976Sjmallett uint64_t nbt : 4; /**< NCB transmitter memory BIST status */ 605215976Sjmallett uint64_t index : 1; /**< Index memory BIST status */ 606215976Sjmallett uint64_t fidx : 1; /**< Forward index memory BIST status */ 607215976Sjmallett uint64_t pend : 1; /**< Pending switch memory BIST status */ 608215976Sjmallett uint64_t adr : 1; /**< Address memory BIST status */ 609215976Sjmallett#else 610215976Sjmallett uint64_t adr : 1; 611215976Sjmallett uint64_t pend : 1; 612215976Sjmallett uint64_t fidx : 1; 613215976Sjmallett uint64_t index : 1; 614215976Sjmallett uint64_t nbt : 4; 615215976Sjmallett uint64_t nbr : 3; 616215976Sjmallett uint64_t cam : 1; 617215976Sjmallett uint64_t reserved_12_15 : 4; 618215976Sjmallett uint64_t pp : 6; 619215976Sjmallett uint64_t reserved_22_63 : 42; 620215976Sjmallett#endif 621215976Sjmallett } cn63xx; 622215976Sjmallett struct cvmx_pow_bist_stat_cn63xx cn63xxp1; 623232812Sjmallett struct cvmx_pow_bist_stat_cn66xx { 624232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 625232812Sjmallett uint64_t reserved_26_63 : 38; 626232812Sjmallett uint64_t pp : 10; /**< Physical PP BIST status */ 627232812Sjmallett uint64_t reserved_12_15 : 4; 628232812Sjmallett uint64_t cam : 1; /**< POW CAM BIST status */ 629232812Sjmallett uint64_t nbr : 3; /**< NCB receiver memory BIST status */ 630232812Sjmallett uint64_t nbt : 4; /**< NCB transmitter memory BIST status */ 631232812Sjmallett uint64_t index : 1; /**< Index memory BIST status */ 632232812Sjmallett uint64_t fidx : 1; /**< Forward index memory BIST status */ 633232812Sjmallett uint64_t pend : 1; /**< Pending switch memory BIST status */ 634232812Sjmallett uint64_t adr : 1; /**< Address memory BIST status */ 635232812Sjmallett#else 636232812Sjmallett uint64_t adr : 1; 637232812Sjmallett uint64_t pend : 1; 638232812Sjmallett uint64_t fidx : 1; 639232812Sjmallett uint64_t index : 1; 640232812Sjmallett uint64_t nbt : 4; 641232812Sjmallett uint64_t nbr : 3; 642232812Sjmallett uint64_t cam : 1; 643232812Sjmallett uint64_t reserved_12_15 : 4; 644232812Sjmallett uint64_t pp : 10; 645232812Sjmallett uint64_t reserved_26_63 : 38; 646232812Sjmallett#endif 647232812Sjmallett } cn66xx; 648232812Sjmallett struct cvmx_pow_bist_stat_cn61xx cnf71xx; 649215976Sjmallett}; 650215976Sjmalletttypedef union cvmx_pow_bist_stat cvmx_pow_bist_stat_t; 651215976Sjmallett 652215976Sjmallett/** 653215976Sjmallett * cvmx_pow_ds_pc 654215976Sjmallett * 655215976Sjmallett * POW_DS_PC = POW De-Schedule Performance Counter 656215976Sjmallett * 657215976Sjmallett * Counts the number of de-schedule requests. Write to clear. 658215976Sjmallett */ 659232812Sjmallettunion cvmx_pow_ds_pc { 660215976Sjmallett uint64_t u64; 661232812Sjmallett struct cvmx_pow_ds_pc_s { 662232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 663215976Sjmallett uint64_t reserved_32_63 : 32; 664215976Sjmallett uint64_t ds_pc : 32; /**< De-schedule performance counter */ 665215976Sjmallett#else 666215976Sjmallett uint64_t ds_pc : 32; 667215976Sjmallett uint64_t reserved_32_63 : 32; 668215976Sjmallett#endif 669215976Sjmallett } s; 670215976Sjmallett struct cvmx_pow_ds_pc_s cn30xx; 671215976Sjmallett struct cvmx_pow_ds_pc_s cn31xx; 672215976Sjmallett struct cvmx_pow_ds_pc_s cn38xx; 673215976Sjmallett struct cvmx_pow_ds_pc_s cn38xxp2; 674215976Sjmallett struct cvmx_pow_ds_pc_s cn50xx; 675215976Sjmallett struct cvmx_pow_ds_pc_s cn52xx; 676215976Sjmallett struct cvmx_pow_ds_pc_s cn52xxp1; 677215976Sjmallett struct cvmx_pow_ds_pc_s cn56xx; 678215976Sjmallett struct cvmx_pow_ds_pc_s cn56xxp1; 679215976Sjmallett struct cvmx_pow_ds_pc_s cn58xx; 680215976Sjmallett struct cvmx_pow_ds_pc_s cn58xxp1; 681232812Sjmallett struct cvmx_pow_ds_pc_s cn61xx; 682215976Sjmallett struct cvmx_pow_ds_pc_s cn63xx; 683215976Sjmallett struct cvmx_pow_ds_pc_s cn63xxp1; 684232812Sjmallett struct cvmx_pow_ds_pc_s cn66xx; 685232812Sjmallett struct cvmx_pow_ds_pc_s cnf71xx; 686215976Sjmallett}; 687215976Sjmalletttypedef union cvmx_pow_ds_pc cvmx_pow_ds_pc_t; 688215976Sjmallett 689215976Sjmallett/** 690215976Sjmallett * cvmx_pow_ecc_err 691215976Sjmallett * 692215976Sjmallett * POW_ECC_ERR = POW ECC Error Register 693215976Sjmallett * 694215976Sjmallett * Contains the single and double error bits and the corresponding interrupt enables for the ECC- 695215976Sjmallett * protected POW index memory. Also contains the syndrome value in the event of an ECC error. 696215976Sjmallett * 697215976Sjmallett * Also contains the remote pointer error bit and interrupt enable. RPE is set when the POW detected 698215976Sjmallett * corruption on one or more of the input queue lists in L2/DRAM (POW's local copy of the tail pointer 699215976Sjmallett * for the L2/DRAM input queue did not match the last entry on the the list). This is caused by 700215976Sjmallett * L2/DRAM corruption, and is generally a fatal error because it likely caused POW to load bad work 701215976Sjmallett * queue entries. 702215976Sjmallett * 703215976Sjmallett * This register also contains the illegal operation error bits and the corresponding interrupt 704215976Sjmallett * enables as follows: 705215976Sjmallett * 706215976Sjmallett * <0> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL_NULL state 707215976Sjmallett * <1> Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL state 708215976Sjmallett * <2> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK from PP with pending tag switch to ORDERED or ATOMIC 709215976Sjmallett * <3> Received SWTAG/SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL_NULL 710215976Sjmallett * <4> Received SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL 711215976Sjmallett * <5> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with GET_WORK pending 712215976Sjmallett * <6> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with NULL_RD pending 713215976Sjmallett * <7> Received CLR_NSCHED from PP with SWTAG_DESCH/DESCH/CLR_NSCHED pending 714215976Sjmallett * <8> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with CLR_NSCHED pending 715215976Sjmallett * <9> Received illegal opcode 716215976Sjmallett * <10> Received ADD_WORK with tag specified as NULL_NULL 717215976Sjmallett * <11> Received DBG load from PP with DBG load pending 718215976Sjmallett * <12> Received CSR load from PP with CSR load pending 719215976Sjmallett */ 720232812Sjmallettunion cvmx_pow_ecc_err { 721215976Sjmallett uint64_t u64; 722232812Sjmallett struct cvmx_pow_ecc_err_s { 723232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 724215976Sjmallett uint64_t reserved_45_63 : 19; 725215976Sjmallett uint64_t iop_ie : 13; /**< Illegal operation interrupt enables */ 726215976Sjmallett uint64_t reserved_29_31 : 3; 727215976Sjmallett uint64_t iop : 13; /**< Illegal operation errors */ 728215976Sjmallett uint64_t reserved_14_15 : 2; 729215976Sjmallett uint64_t rpe_ie : 1; /**< Remote pointer error interrupt enable */ 730215976Sjmallett uint64_t rpe : 1; /**< Remote pointer error */ 731215976Sjmallett uint64_t reserved_9_11 : 3; 732215976Sjmallett uint64_t syn : 5; /**< Syndrome value (only valid when DBE or SBE is set) */ 733215976Sjmallett uint64_t dbe_ie : 1; /**< Double bit error interrupt enable */ 734215976Sjmallett uint64_t sbe_ie : 1; /**< Single bit error interrupt enable */ 735215976Sjmallett uint64_t dbe : 1; /**< Double bit error */ 736215976Sjmallett uint64_t sbe : 1; /**< Single bit error */ 737215976Sjmallett#else 738215976Sjmallett uint64_t sbe : 1; 739215976Sjmallett uint64_t dbe : 1; 740215976Sjmallett uint64_t sbe_ie : 1; 741215976Sjmallett uint64_t dbe_ie : 1; 742215976Sjmallett uint64_t syn : 5; 743215976Sjmallett uint64_t reserved_9_11 : 3; 744215976Sjmallett uint64_t rpe : 1; 745215976Sjmallett uint64_t rpe_ie : 1; 746215976Sjmallett uint64_t reserved_14_15 : 2; 747215976Sjmallett uint64_t iop : 13; 748215976Sjmallett uint64_t reserved_29_31 : 3; 749215976Sjmallett uint64_t iop_ie : 13; 750215976Sjmallett uint64_t reserved_45_63 : 19; 751215976Sjmallett#endif 752215976Sjmallett } s; 753215976Sjmallett struct cvmx_pow_ecc_err_s cn30xx; 754232812Sjmallett struct cvmx_pow_ecc_err_cn31xx { 755232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 756215976Sjmallett uint64_t reserved_14_63 : 50; 757215976Sjmallett uint64_t rpe_ie : 1; /**< Remote pointer error interrupt enable */ 758215976Sjmallett uint64_t rpe : 1; /**< Remote pointer error */ 759215976Sjmallett uint64_t reserved_9_11 : 3; 760215976Sjmallett uint64_t syn : 5; /**< Syndrome value (only valid when DBE or SBE is set) */ 761215976Sjmallett uint64_t dbe_ie : 1; /**< Double bit error interrupt enable */ 762215976Sjmallett uint64_t sbe_ie : 1; /**< Single bit error interrupt enable */ 763215976Sjmallett uint64_t dbe : 1; /**< Double bit error */ 764215976Sjmallett uint64_t sbe : 1; /**< Single bit error */ 765215976Sjmallett#else 766215976Sjmallett uint64_t sbe : 1; 767215976Sjmallett uint64_t dbe : 1; 768215976Sjmallett uint64_t sbe_ie : 1; 769215976Sjmallett uint64_t dbe_ie : 1; 770215976Sjmallett uint64_t syn : 5; 771215976Sjmallett uint64_t reserved_9_11 : 3; 772215976Sjmallett uint64_t rpe : 1; 773215976Sjmallett uint64_t rpe_ie : 1; 774215976Sjmallett uint64_t reserved_14_63 : 50; 775215976Sjmallett#endif 776215976Sjmallett } cn31xx; 777215976Sjmallett struct cvmx_pow_ecc_err_s cn38xx; 778215976Sjmallett struct cvmx_pow_ecc_err_cn31xx cn38xxp2; 779215976Sjmallett struct cvmx_pow_ecc_err_s cn50xx; 780215976Sjmallett struct cvmx_pow_ecc_err_s cn52xx; 781215976Sjmallett struct cvmx_pow_ecc_err_s cn52xxp1; 782215976Sjmallett struct cvmx_pow_ecc_err_s cn56xx; 783215976Sjmallett struct cvmx_pow_ecc_err_s cn56xxp1; 784215976Sjmallett struct cvmx_pow_ecc_err_s cn58xx; 785215976Sjmallett struct cvmx_pow_ecc_err_s cn58xxp1; 786232812Sjmallett struct cvmx_pow_ecc_err_s cn61xx; 787215976Sjmallett struct cvmx_pow_ecc_err_s cn63xx; 788215976Sjmallett struct cvmx_pow_ecc_err_s cn63xxp1; 789232812Sjmallett struct cvmx_pow_ecc_err_s cn66xx; 790232812Sjmallett struct cvmx_pow_ecc_err_s cnf71xx; 791215976Sjmallett}; 792215976Sjmalletttypedef union cvmx_pow_ecc_err cvmx_pow_ecc_err_t; 793215976Sjmallett 794215976Sjmallett/** 795215976Sjmallett * cvmx_pow_int_ctl 796215976Sjmallett * 797215976Sjmallett * POW_INT_CTL = POW Internal Control Register 798215976Sjmallett * 799215976Sjmallett * Contains POW internal control values (for internal use, not typically for customer use): 800215976Sjmallett * 801215976Sjmallett * PFR_DIS = Disable high-performance pre-fetch reset mode. 802215976Sjmallett * 803215976Sjmallett * NBR_THR = Assert ncb__busy when the number of remaining coherent bus NBR credits equals is less 804215976Sjmallett * than or equal to this value. 805215976Sjmallett */ 806232812Sjmallettunion cvmx_pow_int_ctl { 807215976Sjmallett uint64_t u64; 808232812Sjmallett struct cvmx_pow_int_ctl_s { 809232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 810215976Sjmallett uint64_t reserved_6_63 : 58; 811215976Sjmallett uint64_t pfr_dis : 1; /**< High-perf pre-fetch reset mode disable */ 812215976Sjmallett uint64_t nbr_thr : 5; /**< NBR busy threshold */ 813215976Sjmallett#else 814215976Sjmallett uint64_t nbr_thr : 5; 815215976Sjmallett uint64_t pfr_dis : 1; 816215976Sjmallett uint64_t reserved_6_63 : 58; 817215976Sjmallett#endif 818215976Sjmallett } s; 819215976Sjmallett struct cvmx_pow_int_ctl_s cn30xx; 820215976Sjmallett struct cvmx_pow_int_ctl_s cn31xx; 821215976Sjmallett struct cvmx_pow_int_ctl_s cn38xx; 822215976Sjmallett struct cvmx_pow_int_ctl_s cn38xxp2; 823215976Sjmallett struct cvmx_pow_int_ctl_s cn50xx; 824215976Sjmallett struct cvmx_pow_int_ctl_s cn52xx; 825215976Sjmallett struct cvmx_pow_int_ctl_s cn52xxp1; 826215976Sjmallett struct cvmx_pow_int_ctl_s cn56xx; 827215976Sjmallett struct cvmx_pow_int_ctl_s cn56xxp1; 828215976Sjmallett struct cvmx_pow_int_ctl_s cn58xx; 829215976Sjmallett struct cvmx_pow_int_ctl_s cn58xxp1; 830232812Sjmallett struct cvmx_pow_int_ctl_s cn61xx; 831215976Sjmallett struct cvmx_pow_int_ctl_s cn63xx; 832215976Sjmallett struct cvmx_pow_int_ctl_s cn63xxp1; 833232812Sjmallett struct cvmx_pow_int_ctl_s cn66xx; 834232812Sjmallett struct cvmx_pow_int_ctl_s cnf71xx; 835215976Sjmallett}; 836215976Sjmalletttypedef union cvmx_pow_int_ctl cvmx_pow_int_ctl_t; 837215976Sjmallett 838215976Sjmallett/** 839215976Sjmallett * cvmx_pow_iq_cnt# 840215976Sjmallett * 841215976Sjmallett * POW_IQ_CNTX = POW Input Queue Count Register (1 per QOS level) 842215976Sjmallett * 843215976Sjmallett * Contains a read-only count of the number of work queue entries for each QOS level. 844215976Sjmallett */ 845232812Sjmallettunion cvmx_pow_iq_cntx { 846215976Sjmallett uint64_t u64; 847232812Sjmallett struct cvmx_pow_iq_cntx_s { 848232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 849215976Sjmallett uint64_t reserved_32_63 : 32; 850215976Sjmallett uint64_t iq_cnt : 32; /**< Input queue count for QOS level X */ 851215976Sjmallett#else 852215976Sjmallett uint64_t iq_cnt : 32; 853215976Sjmallett uint64_t reserved_32_63 : 32; 854215976Sjmallett#endif 855215976Sjmallett } s; 856215976Sjmallett struct cvmx_pow_iq_cntx_s cn30xx; 857215976Sjmallett struct cvmx_pow_iq_cntx_s cn31xx; 858215976Sjmallett struct cvmx_pow_iq_cntx_s cn38xx; 859215976Sjmallett struct cvmx_pow_iq_cntx_s cn38xxp2; 860215976Sjmallett struct cvmx_pow_iq_cntx_s cn50xx; 861215976Sjmallett struct cvmx_pow_iq_cntx_s cn52xx; 862215976Sjmallett struct cvmx_pow_iq_cntx_s cn52xxp1; 863215976Sjmallett struct cvmx_pow_iq_cntx_s cn56xx; 864215976Sjmallett struct cvmx_pow_iq_cntx_s cn56xxp1; 865215976Sjmallett struct cvmx_pow_iq_cntx_s cn58xx; 866215976Sjmallett struct cvmx_pow_iq_cntx_s cn58xxp1; 867232812Sjmallett struct cvmx_pow_iq_cntx_s cn61xx; 868215976Sjmallett struct cvmx_pow_iq_cntx_s cn63xx; 869215976Sjmallett struct cvmx_pow_iq_cntx_s cn63xxp1; 870232812Sjmallett struct cvmx_pow_iq_cntx_s cn66xx; 871232812Sjmallett struct cvmx_pow_iq_cntx_s cnf71xx; 872215976Sjmallett}; 873215976Sjmalletttypedef union cvmx_pow_iq_cntx cvmx_pow_iq_cntx_t; 874215976Sjmallett 875215976Sjmallett/** 876215976Sjmallett * cvmx_pow_iq_com_cnt 877215976Sjmallett * 878215976Sjmallett * POW_IQ_COM_CNT = POW Input Queue Combined Count Register 879215976Sjmallett * 880215976Sjmallett * Contains a read-only count of the total number of work queue entries in all QOS levels. 881215976Sjmallett */ 882232812Sjmallettunion cvmx_pow_iq_com_cnt { 883215976Sjmallett uint64_t u64; 884232812Sjmallett struct cvmx_pow_iq_com_cnt_s { 885232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 886215976Sjmallett uint64_t reserved_32_63 : 32; 887215976Sjmallett uint64_t iq_cnt : 32; /**< Input queue combined count */ 888215976Sjmallett#else 889215976Sjmallett uint64_t iq_cnt : 32; 890215976Sjmallett uint64_t reserved_32_63 : 32; 891215976Sjmallett#endif 892215976Sjmallett } s; 893215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn30xx; 894215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn31xx; 895215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn38xx; 896215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn38xxp2; 897215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn50xx; 898215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn52xx; 899215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn52xxp1; 900215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn56xx; 901215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn56xxp1; 902215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn58xx; 903215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn58xxp1; 904232812Sjmallett struct cvmx_pow_iq_com_cnt_s cn61xx; 905215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn63xx; 906215976Sjmallett struct cvmx_pow_iq_com_cnt_s cn63xxp1; 907232812Sjmallett struct cvmx_pow_iq_com_cnt_s cn66xx; 908232812Sjmallett struct cvmx_pow_iq_com_cnt_s cnf71xx; 909215976Sjmallett}; 910215976Sjmalletttypedef union cvmx_pow_iq_com_cnt cvmx_pow_iq_com_cnt_t; 911215976Sjmallett 912215976Sjmallett/** 913215976Sjmallett * cvmx_pow_iq_int 914215976Sjmallett * 915215976Sjmallett * POW_IQ_INT = POW Input Queue Interrupt Register 916215976Sjmallett * 917215976Sjmallett * Contains the bits (1 per QOS level) that can trigger the input queue interrupt. An IQ_INT bit 918215976Sjmallett * will be set if POW_IQ_CNT#QOS# changes and the resulting value is equal to POW_IQ_THR#QOS#. 919215976Sjmallett */ 920232812Sjmallettunion cvmx_pow_iq_int { 921215976Sjmallett uint64_t u64; 922232812Sjmallett struct cvmx_pow_iq_int_s { 923232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 924215976Sjmallett uint64_t reserved_8_63 : 56; 925215976Sjmallett uint64_t iq_int : 8; /**< Input queue interrupt bits */ 926215976Sjmallett#else 927215976Sjmallett uint64_t iq_int : 8; 928215976Sjmallett uint64_t reserved_8_63 : 56; 929215976Sjmallett#endif 930215976Sjmallett } s; 931215976Sjmallett struct cvmx_pow_iq_int_s cn52xx; 932215976Sjmallett struct cvmx_pow_iq_int_s cn52xxp1; 933215976Sjmallett struct cvmx_pow_iq_int_s cn56xx; 934215976Sjmallett struct cvmx_pow_iq_int_s cn56xxp1; 935232812Sjmallett struct cvmx_pow_iq_int_s cn61xx; 936215976Sjmallett struct cvmx_pow_iq_int_s cn63xx; 937215976Sjmallett struct cvmx_pow_iq_int_s cn63xxp1; 938232812Sjmallett struct cvmx_pow_iq_int_s cn66xx; 939232812Sjmallett struct cvmx_pow_iq_int_s cnf71xx; 940215976Sjmallett}; 941215976Sjmalletttypedef union cvmx_pow_iq_int cvmx_pow_iq_int_t; 942215976Sjmallett 943215976Sjmallett/** 944215976Sjmallett * cvmx_pow_iq_int_en 945215976Sjmallett * 946215976Sjmallett * POW_IQ_INT_EN = POW Input Queue Interrupt Enable Register 947215976Sjmallett * 948215976Sjmallett * Contains the bits (1 per QOS level) that enable the input queue interrupt. 949215976Sjmallett */ 950232812Sjmallettunion cvmx_pow_iq_int_en { 951215976Sjmallett uint64_t u64; 952232812Sjmallett struct cvmx_pow_iq_int_en_s { 953232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 954215976Sjmallett uint64_t reserved_8_63 : 56; 955215976Sjmallett uint64_t int_en : 8; /**< Input queue interrupt enable bits */ 956215976Sjmallett#else 957215976Sjmallett uint64_t int_en : 8; 958215976Sjmallett uint64_t reserved_8_63 : 56; 959215976Sjmallett#endif 960215976Sjmallett } s; 961215976Sjmallett struct cvmx_pow_iq_int_en_s cn52xx; 962215976Sjmallett struct cvmx_pow_iq_int_en_s cn52xxp1; 963215976Sjmallett struct cvmx_pow_iq_int_en_s cn56xx; 964215976Sjmallett struct cvmx_pow_iq_int_en_s cn56xxp1; 965232812Sjmallett struct cvmx_pow_iq_int_en_s cn61xx; 966215976Sjmallett struct cvmx_pow_iq_int_en_s cn63xx; 967215976Sjmallett struct cvmx_pow_iq_int_en_s cn63xxp1; 968232812Sjmallett struct cvmx_pow_iq_int_en_s cn66xx; 969232812Sjmallett struct cvmx_pow_iq_int_en_s cnf71xx; 970215976Sjmallett}; 971215976Sjmalletttypedef union cvmx_pow_iq_int_en cvmx_pow_iq_int_en_t; 972215976Sjmallett 973215976Sjmallett/** 974215976Sjmallett * cvmx_pow_iq_thr# 975215976Sjmallett * 976215976Sjmallett * POW_IQ_THRX = POW Input Queue Threshold Register (1 per QOS level) 977215976Sjmallett * 978215976Sjmallett * Threshold value for triggering input queue interrupts. 979215976Sjmallett */ 980232812Sjmallettunion cvmx_pow_iq_thrx { 981215976Sjmallett uint64_t u64; 982232812Sjmallett struct cvmx_pow_iq_thrx_s { 983232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 984215976Sjmallett uint64_t reserved_32_63 : 32; 985215976Sjmallett uint64_t iq_thr : 32; /**< Input queue threshold for QOS level X */ 986215976Sjmallett#else 987215976Sjmallett uint64_t iq_thr : 32; 988215976Sjmallett uint64_t reserved_32_63 : 32; 989215976Sjmallett#endif 990215976Sjmallett } s; 991215976Sjmallett struct cvmx_pow_iq_thrx_s cn52xx; 992215976Sjmallett struct cvmx_pow_iq_thrx_s cn52xxp1; 993215976Sjmallett struct cvmx_pow_iq_thrx_s cn56xx; 994215976Sjmallett struct cvmx_pow_iq_thrx_s cn56xxp1; 995232812Sjmallett struct cvmx_pow_iq_thrx_s cn61xx; 996215976Sjmallett struct cvmx_pow_iq_thrx_s cn63xx; 997215976Sjmallett struct cvmx_pow_iq_thrx_s cn63xxp1; 998232812Sjmallett struct cvmx_pow_iq_thrx_s cn66xx; 999232812Sjmallett struct cvmx_pow_iq_thrx_s cnf71xx; 1000215976Sjmallett}; 1001215976Sjmalletttypedef union cvmx_pow_iq_thrx cvmx_pow_iq_thrx_t; 1002215976Sjmallett 1003215976Sjmallett/** 1004215976Sjmallett * cvmx_pow_nos_cnt 1005215976Sjmallett * 1006215976Sjmallett * POW_NOS_CNT = POW No-schedule Count Register 1007215976Sjmallett * 1008215976Sjmallett * Contains the number of work queue entries on the no-schedule list. 1009215976Sjmallett */ 1010232812Sjmallettunion cvmx_pow_nos_cnt { 1011215976Sjmallett uint64_t u64; 1012232812Sjmallett struct cvmx_pow_nos_cnt_s { 1013232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1014215976Sjmallett uint64_t reserved_12_63 : 52; 1015215976Sjmallett uint64_t nos_cnt : 12; /**< # of work queue entries on the no-schedule list */ 1016215976Sjmallett#else 1017215976Sjmallett uint64_t nos_cnt : 12; 1018215976Sjmallett uint64_t reserved_12_63 : 52; 1019215976Sjmallett#endif 1020215976Sjmallett } s; 1021232812Sjmallett struct cvmx_pow_nos_cnt_cn30xx { 1022232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1023215976Sjmallett uint64_t reserved_7_63 : 57; 1024215976Sjmallett uint64_t nos_cnt : 7; /**< # of work queue entries on the no-schedule list */ 1025215976Sjmallett#else 1026215976Sjmallett uint64_t nos_cnt : 7; 1027215976Sjmallett uint64_t reserved_7_63 : 57; 1028215976Sjmallett#endif 1029215976Sjmallett } cn30xx; 1030232812Sjmallett struct cvmx_pow_nos_cnt_cn31xx { 1031232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1032215976Sjmallett uint64_t reserved_9_63 : 55; 1033215976Sjmallett uint64_t nos_cnt : 9; /**< # of work queue entries on the no-schedule list */ 1034215976Sjmallett#else 1035215976Sjmallett uint64_t nos_cnt : 9; 1036215976Sjmallett uint64_t reserved_9_63 : 55; 1037215976Sjmallett#endif 1038215976Sjmallett } cn31xx; 1039215976Sjmallett struct cvmx_pow_nos_cnt_s cn38xx; 1040215976Sjmallett struct cvmx_pow_nos_cnt_s cn38xxp2; 1041215976Sjmallett struct cvmx_pow_nos_cnt_cn31xx cn50xx; 1042232812Sjmallett struct cvmx_pow_nos_cnt_cn52xx { 1043232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1044215976Sjmallett uint64_t reserved_10_63 : 54; 1045215976Sjmallett uint64_t nos_cnt : 10; /**< # of work queue entries on the no-schedule list */ 1046215976Sjmallett#else 1047215976Sjmallett uint64_t nos_cnt : 10; 1048215976Sjmallett uint64_t reserved_10_63 : 54; 1049215976Sjmallett#endif 1050215976Sjmallett } cn52xx; 1051215976Sjmallett struct cvmx_pow_nos_cnt_cn52xx cn52xxp1; 1052215976Sjmallett struct cvmx_pow_nos_cnt_s cn56xx; 1053215976Sjmallett struct cvmx_pow_nos_cnt_s cn56xxp1; 1054215976Sjmallett struct cvmx_pow_nos_cnt_s cn58xx; 1055215976Sjmallett struct cvmx_pow_nos_cnt_s cn58xxp1; 1056232812Sjmallett struct cvmx_pow_nos_cnt_cn52xx cn61xx; 1057232812Sjmallett struct cvmx_pow_nos_cnt_cn63xx { 1058232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1059215976Sjmallett uint64_t reserved_11_63 : 53; 1060215976Sjmallett uint64_t nos_cnt : 11; /**< # of work queue entries on the no-schedule list */ 1061215976Sjmallett#else 1062215976Sjmallett uint64_t nos_cnt : 11; 1063215976Sjmallett uint64_t reserved_11_63 : 53; 1064215976Sjmallett#endif 1065215976Sjmallett } cn63xx; 1066215976Sjmallett struct cvmx_pow_nos_cnt_cn63xx cn63xxp1; 1067232812Sjmallett struct cvmx_pow_nos_cnt_cn63xx cn66xx; 1068232812Sjmallett struct cvmx_pow_nos_cnt_cn52xx cnf71xx; 1069215976Sjmallett}; 1070215976Sjmalletttypedef union cvmx_pow_nos_cnt cvmx_pow_nos_cnt_t; 1071215976Sjmallett 1072215976Sjmallett/** 1073215976Sjmallett * cvmx_pow_nw_tim 1074215976Sjmallett * 1075215976Sjmallett * POW_NW_TIM = POW New Work Timer Period Register 1076215976Sjmallett * 1077215976Sjmallett * Sets the minimum period for a new work request timeout. Period is specified in n-1 notation 1078215976Sjmallett * where the increment value is 1024 clock cycles. Thus, a value of 0x0 in this register translates 1079215976Sjmallett * to 1024 cycles, 0x1 translates to 2048 cycles, 0x2 translates to 3072 cycles, etc... Note: the 1080215976Sjmallett * maximum period for a new work request timeout is 2 times the minimum period. Note: the new work 1081215976Sjmallett * request timeout counter is reset when this register is written. 1082215976Sjmallett * 1083215976Sjmallett * There are two new work request timeout cases: 1084215976Sjmallett * 1085215976Sjmallett * - WAIT bit clear. The new work request can timeout if the timer expires before the pre-fetch 1086215976Sjmallett * engine has reached the end of all work queues. This can occur if the executable work queue 1087215976Sjmallett * entry is deep in the queue and the pre-fetch engine is subject to many resets (i.e. high switch, 1088215976Sjmallett * de-schedule, or new work load from other PP's). Thus, it is possible for a PP to receive a work 1089215976Sjmallett * response with the NO_WORK bit set even though there was at least one executable entry in the 1090215976Sjmallett * work queues. The other (and typical) scenario for receiving a NO_WORK response with the WAIT 1091215976Sjmallett * bit clear is that the pre-fetch engine has reached the end of all work queues without finding 1092215976Sjmallett * executable work. 1093215976Sjmallett * 1094215976Sjmallett * - WAIT bit set. The new work request can timeout if the timer expires before the pre-fetch 1095215976Sjmallett * engine has found executable work. In this case, the only scenario where the PP will receive a 1096215976Sjmallett * work response with the NO_WORK bit set is if the timer expires. Note: it is still possible for 1097215976Sjmallett * a PP to receive a NO_WORK response even though there was at least one executable entry in the 1098215976Sjmallett * work queues. 1099215976Sjmallett * 1100215976Sjmallett * In either case, it's important to note that switches and de-schedules are higher priority 1101215976Sjmallett * operations that can cause the pre-fetch engine to reset. Thus in a system with many switches or 1102215976Sjmallett * de-schedules occuring, it's possible for the new work timer to expire (resulting in NO_WORK 1103215976Sjmallett * responses) before the pre-fetch engine is able to get very deep into the work queues. 1104215976Sjmallett */ 1105232812Sjmallettunion cvmx_pow_nw_tim { 1106215976Sjmallett uint64_t u64; 1107232812Sjmallett struct cvmx_pow_nw_tim_s { 1108232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1109215976Sjmallett uint64_t reserved_10_63 : 54; 1110215976Sjmallett uint64_t nw_tim : 10; /**< New work timer period */ 1111215976Sjmallett#else 1112215976Sjmallett uint64_t nw_tim : 10; 1113215976Sjmallett uint64_t reserved_10_63 : 54; 1114215976Sjmallett#endif 1115215976Sjmallett } s; 1116215976Sjmallett struct cvmx_pow_nw_tim_s cn30xx; 1117215976Sjmallett struct cvmx_pow_nw_tim_s cn31xx; 1118215976Sjmallett struct cvmx_pow_nw_tim_s cn38xx; 1119215976Sjmallett struct cvmx_pow_nw_tim_s cn38xxp2; 1120215976Sjmallett struct cvmx_pow_nw_tim_s cn50xx; 1121215976Sjmallett struct cvmx_pow_nw_tim_s cn52xx; 1122215976Sjmallett struct cvmx_pow_nw_tim_s cn52xxp1; 1123215976Sjmallett struct cvmx_pow_nw_tim_s cn56xx; 1124215976Sjmallett struct cvmx_pow_nw_tim_s cn56xxp1; 1125215976Sjmallett struct cvmx_pow_nw_tim_s cn58xx; 1126215976Sjmallett struct cvmx_pow_nw_tim_s cn58xxp1; 1127232812Sjmallett struct cvmx_pow_nw_tim_s cn61xx; 1128215976Sjmallett struct cvmx_pow_nw_tim_s cn63xx; 1129215976Sjmallett struct cvmx_pow_nw_tim_s cn63xxp1; 1130232812Sjmallett struct cvmx_pow_nw_tim_s cn66xx; 1131232812Sjmallett struct cvmx_pow_nw_tim_s cnf71xx; 1132215976Sjmallett}; 1133215976Sjmalletttypedef union cvmx_pow_nw_tim cvmx_pow_nw_tim_t; 1134215976Sjmallett 1135215976Sjmallett/** 1136215976Sjmallett * cvmx_pow_pf_rst_msk 1137215976Sjmallett * 1138215976Sjmallett * POW_PF_RST_MSK = POW Prefetch Reset Mask 1139215976Sjmallett * 1140215976Sjmallett * Resets the work prefetch engine when work is stored in an internal buffer (either when the add 1141215976Sjmallett * work arrives or when the work is reloaded from an external buffer) for an enabled QOS level 1142215976Sjmallett * (1 bit per QOS level). 1143215976Sjmallett */ 1144232812Sjmallettunion cvmx_pow_pf_rst_msk { 1145215976Sjmallett uint64_t u64; 1146232812Sjmallett struct cvmx_pow_pf_rst_msk_s { 1147232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1148215976Sjmallett uint64_t reserved_8_63 : 56; 1149215976Sjmallett uint64_t rst_msk : 8; /**< Prefetch engine reset mask */ 1150215976Sjmallett#else 1151215976Sjmallett uint64_t rst_msk : 8; 1152215976Sjmallett uint64_t reserved_8_63 : 56; 1153215976Sjmallett#endif 1154215976Sjmallett } s; 1155215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn50xx; 1156215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn52xx; 1157215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn52xxp1; 1158215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn56xx; 1159215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn56xxp1; 1160215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn58xx; 1161215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn58xxp1; 1162232812Sjmallett struct cvmx_pow_pf_rst_msk_s cn61xx; 1163215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn63xx; 1164215976Sjmallett struct cvmx_pow_pf_rst_msk_s cn63xxp1; 1165232812Sjmallett struct cvmx_pow_pf_rst_msk_s cn66xx; 1166232812Sjmallett struct cvmx_pow_pf_rst_msk_s cnf71xx; 1167215976Sjmallett}; 1168215976Sjmalletttypedef union cvmx_pow_pf_rst_msk cvmx_pow_pf_rst_msk_t; 1169215976Sjmallett 1170215976Sjmallett/** 1171215976Sjmallett * cvmx_pow_pp_grp_msk# 1172215976Sjmallett * 1173215976Sjmallett * POW_PP_GRP_MSKX = POW PP Group Mask Register (1 per PP) 1174215976Sjmallett * 1175215976Sjmallett * Selects which group(s) a PP belongs to. A '1' in any bit position sets the PP's membership in 1176215976Sjmallett * the corresponding group. A value of 0x0 will prevent the PP from receiving new work. Note: 1177215976Sjmallett * disabled or non-existent PP's should have this field set to 0xffff (the reset value) in order to 1178215976Sjmallett * maximize POW performance. 1179215976Sjmallett * 1180215976Sjmallett * Also contains the QOS level priorities for each PP. 0x0 is highest priority, and 0x7 the lowest. 1181215976Sjmallett * Setting the priority to 0xf will prevent that PP from receiving work from that QOS level. 1182215976Sjmallett * Priority values 0x8 through 0xe are reserved and should not be used. For a given PP, priorities 1183215976Sjmallett * should begin at 0x0 and remain contiguous throughout the range. 1184215976Sjmallett */ 1185232812Sjmallettunion cvmx_pow_pp_grp_mskx { 1186215976Sjmallett uint64_t u64; 1187232812Sjmallett struct cvmx_pow_pp_grp_mskx_s { 1188232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1189215976Sjmallett uint64_t reserved_48_63 : 16; 1190215976Sjmallett uint64_t qos7_pri : 4; /**< PPX priority for QOS level 7 */ 1191215976Sjmallett uint64_t qos6_pri : 4; /**< PPX priority for QOS level 6 */ 1192215976Sjmallett uint64_t qos5_pri : 4; /**< PPX priority for QOS level 5 */ 1193215976Sjmallett uint64_t qos4_pri : 4; /**< PPX priority for QOS level 4 */ 1194215976Sjmallett uint64_t qos3_pri : 4; /**< PPX priority for QOS level 3 */ 1195215976Sjmallett uint64_t qos2_pri : 4; /**< PPX priority for QOS level 2 */ 1196215976Sjmallett uint64_t qos1_pri : 4; /**< PPX priority for QOS level 1 */ 1197215976Sjmallett uint64_t qos0_pri : 4; /**< PPX priority for QOS level 0 */ 1198215976Sjmallett uint64_t grp_msk : 16; /**< PPX group mask */ 1199215976Sjmallett#else 1200215976Sjmallett uint64_t grp_msk : 16; 1201215976Sjmallett uint64_t qos0_pri : 4; 1202215976Sjmallett uint64_t qos1_pri : 4; 1203215976Sjmallett uint64_t qos2_pri : 4; 1204215976Sjmallett uint64_t qos3_pri : 4; 1205215976Sjmallett uint64_t qos4_pri : 4; 1206215976Sjmallett uint64_t qos5_pri : 4; 1207215976Sjmallett uint64_t qos6_pri : 4; 1208215976Sjmallett uint64_t qos7_pri : 4; 1209215976Sjmallett uint64_t reserved_48_63 : 16; 1210215976Sjmallett#endif 1211215976Sjmallett } s; 1212232812Sjmallett struct cvmx_pow_pp_grp_mskx_cn30xx { 1213232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1214215976Sjmallett uint64_t reserved_16_63 : 48; 1215215976Sjmallett uint64_t grp_msk : 16; /**< PPX group mask */ 1216215976Sjmallett#else 1217215976Sjmallett uint64_t grp_msk : 16; 1218215976Sjmallett uint64_t reserved_16_63 : 48; 1219215976Sjmallett#endif 1220215976Sjmallett } cn30xx; 1221215976Sjmallett struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx; 1222215976Sjmallett struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx; 1223215976Sjmallett struct cvmx_pow_pp_grp_mskx_cn30xx cn38xxp2; 1224215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn50xx; 1225215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn52xx; 1226215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn52xxp1; 1227215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn56xx; 1228215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn56xxp1; 1229215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn58xx; 1230215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn58xxp1; 1231232812Sjmallett struct cvmx_pow_pp_grp_mskx_s cn61xx; 1232215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn63xx; 1233215976Sjmallett struct cvmx_pow_pp_grp_mskx_s cn63xxp1; 1234232812Sjmallett struct cvmx_pow_pp_grp_mskx_s cn66xx; 1235232812Sjmallett struct cvmx_pow_pp_grp_mskx_s cnf71xx; 1236215976Sjmallett}; 1237215976Sjmalletttypedef union cvmx_pow_pp_grp_mskx cvmx_pow_pp_grp_mskx_t; 1238215976Sjmallett 1239215976Sjmallett/** 1240215976Sjmallett * cvmx_pow_qos_rnd# 1241215976Sjmallett * 1242215976Sjmallett * POW_QOS_RNDX = POW QOS Issue Round Register (4 rounds per register x 8 registers = 32 rounds) 1243215976Sjmallett * 1244215976Sjmallett * Contains the round definitions for issuing new work. Each round consists of 8 bits with each bit 1245215976Sjmallett * corresponding to a QOS level. There are 4 rounds contained in each register for a total of 32 1246215976Sjmallett * rounds. The issue logic traverses through the rounds sequentially (lowest round to highest round) 1247215976Sjmallett * in an attempt to find new work for each PP. Within each round, the issue logic traverses through 1248215976Sjmallett * the QOS levels sequentially (highest QOS to lowest QOS) skipping over each QOS level with a clear 1249215976Sjmallett * bit in the round mask. Note: setting a QOS level to all zeroes in all issue round registers will 1250215976Sjmallett * prevent work from being issued from that QOS level. 1251215976Sjmallett */ 1252232812Sjmallettunion cvmx_pow_qos_rndx { 1253215976Sjmallett uint64_t u64; 1254232812Sjmallett struct cvmx_pow_qos_rndx_s { 1255232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1256215976Sjmallett uint64_t reserved_32_63 : 32; 1257215976Sjmallett uint64_t rnd_p3 : 8; /**< Round mask for round Xx4+3 */ 1258215976Sjmallett uint64_t rnd_p2 : 8; /**< Round mask for round Xx4+2 */ 1259215976Sjmallett uint64_t rnd_p1 : 8; /**< Round mask for round Xx4+1 */ 1260215976Sjmallett uint64_t rnd : 8; /**< Round mask for round Xx4 */ 1261215976Sjmallett#else 1262215976Sjmallett uint64_t rnd : 8; 1263215976Sjmallett uint64_t rnd_p1 : 8; 1264215976Sjmallett uint64_t rnd_p2 : 8; 1265215976Sjmallett uint64_t rnd_p3 : 8; 1266215976Sjmallett uint64_t reserved_32_63 : 32; 1267215976Sjmallett#endif 1268215976Sjmallett } s; 1269215976Sjmallett struct cvmx_pow_qos_rndx_s cn30xx; 1270215976Sjmallett struct cvmx_pow_qos_rndx_s cn31xx; 1271215976Sjmallett struct cvmx_pow_qos_rndx_s cn38xx; 1272215976Sjmallett struct cvmx_pow_qos_rndx_s cn38xxp2; 1273215976Sjmallett struct cvmx_pow_qos_rndx_s cn50xx; 1274215976Sjmallett struct cvmx_pow_qos_rndx_s cn52xx; 1275215976Sjmallett struct cvmx_pow_qos_rndx_s cn52xxp1; 1276215976Sjmallett struct cvmx_pow_qos_rndx_s cn56xx; 1277215976Sjmallett struct cvmx_pow_qos_rndx_s cn56xxp1; 1278215976Sjmallett struct cvmx_pow_qos_rndx_s cn58xx; 1279215976Sjmallett struct cvmx_pow_qos_rndx_s cn58xxp1; 1280232812Sjmallett struct cvmx_pow_qos_rndx_s cn61xx; 1281215976Sjmallett struct cvmx_pow_qos_rndx_s cn63xx; 1282215976Sjmallett struct cvmx_pow_qos_rndx_s cn63xxp1; 1283232812Sjmallett struct cvmx_pow_qos_rndx_s cn66xx; 1284232812Sjmallett struct cvmx_pow_qos_rndx_s cnf71xx; 1285215976Sjmallett}; 1286215976Sjmalletttypedef union cvmx_pow_qos_rndx cvmx_pow_qos_rndx_t; 1287215976Sjmallett 1288215976Sjmallett/** 1289215976Sjmallett * cvmx_pow_qos_thr# 1290215976Sjmallett * 1291215976Sjmallett * POW_QOS_THRX = POW QOS Threshold Register (1 per QOS level) 1292215976Sjmallett * 1293215976Sjmallett * Contains the thresholds for allocating POW internal storage buffers. If the number of remaining 1294215976Sjmallett * free buffers drops below the minimum threshold (MIN_THR) or the number of allocated buffers for 1295215976Sjmallett * this QOS level rises above the maximum threshold (MAX_THR), future incoming work queue entries 1296215976Sjmallett * will be buffered externally rather than internally. This register also contains a read-only count 1297215976Sjmallett * of the current number of free buffers (FREE_CNT), the number of internal buffers currently 1298215976Sjmallett * allocated to this QOS level (BUF_CNT), and the total number of buffers on the de-schedule list 1299215976Sjmallett * (DES_CNT) (which is not the same as the total number of de-scheduled buffers). 1300215976Sjmallett */ 1301232812Sjmallettunion cvmx_pow_qos_thrx { 1302215976Sjmallett uint64_t u64; 1303232812Sjmallett struct cvmx_pow_qos_thrx_s { 1304232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1305215976Sjmallett uint64_t reserved_60_63 : 4; 1306215976Sjmallett uint64_t des_cnt : 12; /**< # of buffers on de-schedule list */ 1307215976Sjmallett uint64_t buf_cnt : 12; /**< # of internal buffers allocated to QOS level X */ 1308215976Sjmallett uint64_t free_cnt : 12; /**< # of total free buffers */ 1309215976Sjmallett uint64_t reserved_23_23 : 1; 1310215976Sjmallett uint64_t max_thr : 11; /**< Max threshold for QOS level X */ 1311215976Sjmallett uint64_t reserved_11_11 : 1; 1312215976Sjmallett uint64_t min_thr : 11; /**< Min threshold for QOS level X */ 1313215976Sjmallett#else 1314215976Sjmallett uint64_t min_thr : 11; 1315215976Sjmallett uint64_t reserved_11_11 : 1; 1316215976Sjmallett uint64_t max_thr : 11; 1317215976Sjmallett uint64_t reserved_23_23 : 1; 1318215976Sjmallett uint64_t free_cnt : 12; 1319215976Sjmallett uint64_t buf_cnt : 12; 1320215976Sjmallett uint64_t des_cnt : 12; 1321215976Sjmallett uint64_t reserved_60_63 : 4; 1322215976Sjmallett#endif 1323215976Sjmallett } s; 1324232812Sjmallett struct cvmx_pow_qos_thrx_cn30xx { 1325232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1326215976Sjmallett uint64_t reserved_55_63 : 9; 1327215976Sjmallett uint64_t des_cnt : 7; /**< # of buffers on de-schedule list */ 1328215976Sjmallett uint64_t reserved_43_47 : 5; 1329215976Sjmallett uint64_t buf_cnt : 7; /**< # of internal buffers allocated to QOS level X */ 1330215976Sjmallett uint64_t reserved_31_35 : 5; 1331215976Sjmallett uint64_t free_cnt : 7; /**< # of total free buffers */ 1332215976Sjmallett uint64_t reserved_18_23 : 6; 1333215976Sjmallett uint64_t max_thr : 6; /**< Max threshold for QOS level X */ 1334215976Sjmallett uint64_t reserved_6_11 : 6; 1335215976Sjmallett uint64_t min_thr : 6; /**< Min threshold for QOS level X */ 1336215976Sjmallett#else 1337215976Sjmallett uint64_t min_thr : 6; 1338215976Sjmallett uint64_t reserved_6_11 : 6; 1339215976Sjmallett uint64_t max_thr : 6; 1340215976Sjmallett uint64_t reserved_18_23 : 6; 1341215976Sjmallett uint64_t free_cnt : 7; 1342215976Sjmallett uint64_t reserved_31_35 : 5; 1343215976Sjmallett uint64_t buf_cnt : 7; 1344215976Sjmallett uint64_t reserved_43_47 : 5; 1345215976Sjmallett uint64_t des_cnt : 7; 1346215976Sjmallett uint64_t reserved_55_63 : 9; 1347215976Sjmallett#endif 1348215976Sjmallett } cn30xx; 1349232812Sjmallett struct cvmx_pow_qos_thrx_cn31xx { 1350232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1351215976Sjmallett uint64_t reserved_57_63 : 7; 1352215976Sjmallett uint64_t des_cnt : 9; /**< # of buffers on de-schedule list */ 1353215976Sjmallett uint64_t reserved_45_47 : 3; 1354215976Sjmallett uint64_t buf_cnt : 9; /**< # of internal buffers allocated to QOS level X */ 1355215976Sjmallett uint64_t reserved_33_35 : 3; 1356215976Sjmallett uint64_t free_cnt : 9; /**< # of total free buffers */ 1357215976Sjmallett uint64_t reserved_20_23 : 4; 1358215976Sjmallett uint64_t max_thr : 8; /**< Max threshold for QOS level X */ 1359215976Sjmallett uint64_t reserved_8_11 : 4; 1360215976Sjmallett uint64_t min_thr : 8; /**< Min threshold for QOS level X */ 1361215976Sjmallett#else 1362215976Sjmallett uint64_t min_thr : 8; 1363215976Sjmallett uint64_t reserved_8_11 : 4; 1364215976Sjmallett uint64_t max_thr : 8; 1365215976Sjmallett uint64_t reserved_20_23 : 4; 1366215976Sjmallett uint64_t free_cnt : 9; 1367215976Sjmallett uint64_t reserved_33_35 : 3; 1368215976Sjmallett uint64_t buf_cnt : 9; 1369215976Sjmallett uint64_t reserved_45_47 : 3; 1370215976Sjmallett uint64_t des_cnt : 9; 1371215976Sjmallett uint64_t reserved_57_63 : 7; 1372215976Sjmallett#endif 1373215976Sjmallett } cn31xx; 1374215976Sjmallett struct cvmx_pow_qos_thrx_s cn38xx; 1375215976Sjmallett struct cvmx_pow_qos_thrx_s cn38xxp2; 1376215976Sjmallett struct cvmx_pow_qos_thrx_cn31xx cn50xx; 1377232812Sjmallett struct cvmx_pow_qos_thrx_cn52xx { 1378232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1379215976Sjmallett uint64_t reserved_58_63 : 6; 1380215976Sjmallett uint64_t des_cnt : 10; /**< # of buffers on de-schedule list */ 1381215976Sjmallett uint64_t reserved_46_47 : 2; 1382215976Sjmallett uint64_t buf_cnt : 10; /**< # of internal buffers allocated to QOS level X */ 1383215976Sjmallett uint64_t reserved_34_35 : 2; 1384215976Sjmallett uint64_t free_cnt : 10; /**< # of total free buffers */ 1385215976Sjmallett uint64_t reserved_21_23 : 3; 1386215976Sjmallett uint64_t max_thr : 9; /**< Max threshold for QOS level X */ 1387215976Sjmallett uint64_t reserved_9_11 : 3; 1388215976Sjmallett uint64_t min_thr : 9; /**< Min threshold for QOS level X */ 1389215976Sjmallett#else 1390215976Sjmallett uint64_t min_thr : 9; 1391215976Sjmallett uint64_t reserved_9_11 : 3; 1392215976Sjmallett uint64_t max_thr : 9; 1393215976Sjmallett uint64_t reserved_21_23 : 3; 1394215976Sjmallett uint64_t free_cnt : 10; 1395215976Sjmallett uint64_t reserved_34_35 : 2; 1396215976Sjmallett uint64_t buf_cnt : 10; 1397215976Sjmallett uint64_t reserved_46_47 : 2; 1398215976Sjmallett uint64_t des_cnt : 10; 1399215976Sjmallett uint64_t reserved_58_63 : 6; 1400215976Sjmallett#endif 1401215976Sjmallett } cn52xx; 1402215976Sjmallett struct cvmx_pow_qos_thrx_cn52xx cn52xxp1; 1403215976Sjmallett struct cvmx_pow_qos_thrx_s cn56xx; 1404215976Sjmallett struct cvmx_pow_qos_thrx_s cn56xxp1; 1405215976Sjmallett struct cvmx_pow_qos_thrx_s cn58xx; 1406215976Sjmallett struct cvmx_pow_qos_thrx_s cn58xxp1; 1407232812Sjmallett struct cvmx_pow_qos_thrx_cn52xx cn61xx; 1408232812Sjmallett struct cvmx_pow_qos_thrx_cn63xx { 1409232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1410215976Sjmallett uint64_t reserved_59_63 : 5; 1411215976Sjmallett uint64_t des_cnt : 11; /**< # of buffers on de-schedule list */ 1412215976Sjmallett uint64_t reserved_47_47 : 1; 1413215976Sjmallett uint64_t buf_cnt : 11; /**< # of internal buffers allocated to QOS level X */ 1414215976Sjmallett uint64_t reserved_35_35 : 1; 1415215976Sjmallett uint64_t free_cnt : 11; /**< # of total free buffers */ 1416215976Sjmallett uint64_t reserved_22_23 : 2; 1417215976Sjmallett uint64_t max_thr : 10; /**< Max threshold for QOS level X */ 1418215976Sjmallett uint64_t reserved_10_11 : 2; 1419215976Sjmallett uint64_t min_thr : 10; /**< Min threshold for QOS level X */ 1420215976Sjmallett#else 1421215976Sjmallett uint64_t min_thr : 10; 1422215976Sjmallett uint64_t reserved_10_11 : 2; 1423215976Sjmallett uint64_t max_thr : 10; 1424215976Sjmallett uint64_t reserved_22_23 : 2; 1425215976Sjmallett uint64_t free_cnt : 11; 1426215976Sjmallett uint64_t reserved_35_35 : 1; 1427215976Sjmallett uint64_t buf_cnt : 11; 1428215976Sjmallett uint64_t reserved_47_47 : 1; 1429215976Sjmallett uint64_t des_cnt : 11; 1430215976Sjmallett uint64_t reserved_59_63 : 5; 1431215976Sjmallett#endif 1432215976Sjmallett } cn63xx; 1433215976Sjmallett struct cvmx_pow_qos_thrx_cn63xx cn63xxp1; 1434232812Sjmallett struct cvmx_pow_qos_thrx_cn63xx cn66xx; 1435232812Sjmallett struct cvmx_pow_qos_thrx_cn52xx cnf71xx; 1436215976Sjmallett}; 1437215976Sjmalletttypedef union cvmx_pow_qos_thrx cvmx_pow_qos_thrx_t; 1438215976Sjmallett 1439215976Sjmallett/** 1440215976Sjmallett * cvmx_pow_ts_pc 1441215976Sjmallett * 1442215976Sjmallett * POW_TS_PC = POW Tag Switch Performance Counter 1443215976Sjmallett * 1444215976Sjmallett * Counts the number of tag switch requests. Write to clear. 1445215976Sjmallett */ 1446232812Sjmallettunion cvmx_pow_ts_pc { 1447215976Sjmallett uint64_t u64; 1448232812Sjmallett struct cvmx_pow_ts_pc_s { 1449232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1450215976Sjmallett uint64_t reserved_32_63 : 32; 1451215976Sjmallett uint64_t ts_pc : 32; /**< Tag switch performance counter */ 1452215976Sjmallett#else 1453215976Sjmallett uint64_t ts_pc : 32; 1454215976Sjmallett uint64_t reserved_32_63 : 32; 1455215976Sjmallett#endif 1456215976Sjmallett } s; 1457215976Sjmallett struct cvmx_pow_ts_pc_s cn30xx; 1458215976Sjmallett struct cvmx_pow_ts_pc_s cn31xx; 1459215976Sjmallett struct cvmx_pow_ts_pc_s cn38xx; 1460215976Sjmallett struct cvmx_pow_ts_pc_s cn38xxp2; 1461215976Sjmallett struct cvmx_pow_ts_pc_s cn50xx; 1462215976Sjmallett struct cvmx_pow_ts_pc_s cn52xx; 1463215976Sjmallett struct cvmx_pow_ts_pc_s cn52xxp1; 1464215976Sjmallett struct cvmx_pow_ts_pc_s cn56xx; 1465215976Sjmallett struct cvmx_pow_ts_pc_s cn56xxp1; 1466215976Sjmallett struct cvmx_pow_ts_pc_s cn58xx; 1467215976Sjmallett struct cvmx_pow_ts_pc_s cn58xxp1; 1468232812Sjmallett struct cvmx_pow_ts_pc_s cn61xx; 1469215976Sjmallett struct cvmx_pow_ts_pc_s cn63xx; 1470215976Sjmallett struct cvmx_pow_ts_pc_s cn63xxp1; 1471232812Sjmallett struct cvmx_pow_ts_pc_s cn66xx; 1472232812Sjmallett struct cvmx_pow_ts_pc_s cnf71xx; 1473215976Sjmallett}; 1474215976Sjmalletttypedef union cvmx_pow_ts_pc cvmx_pow_ts_pc_t; 1475215976Sjmallett 1476215976Sjmallett/** 1477215976Sjmallett * cvmx_pow_wa_com_pc 1478215976Sjmallett * 1479215976Sjmallett * POW_WA_COM_PC = POW Work Add Combined Performance Counter 1480215976Sjmallett * 1481215976Sjmallett * Counts the number of add new work requests for all QOS levels. Write to clear. 1482215976Sjmallett */ 1483232812Sjmallettunion cvmx_pow_wa_com_pc { 1484215976Sjmallett uint64_t u64; 1485232812Sjmallett struct cvmx_pow_wa_com_pc_s { 1486232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1487215976Sjmallett uint64_t reserved_32_63 : 32; 1488215976Sjmallett uint64_t wa_pc : 32; /**< Work add combined performance counter */ 1489215976Sjmallett#else 1490215976Sjmallett uint64_t wa_pc : 32; 1491215976Sjmallett uint64_t reserved_32_63 : 32; 1492215976Sjmallett#endif 1493215976Sjmallett } s; 1494215976Sjmallett struct cvmx_pow_wa_com_pc_s cn30xx; 1495215976Sjmallett struct cvmx_pow_wa_com_pc_s cn31xx; 1496215976Sjmallett struct cvmx_pow_wa_com_pc_s cn38xx; 1497215976Sjmallett struct cvmx_pow_wa_com_pc_s cn38xxp2; 1498215976Sjmallett struct cvmx_pow_wa_com_pc_s cn50xx; 1499215976Sjmallett struct cvmx_pow_wa_com_pc_s cn52xx; 1500215976Sjmallett struct cvmx_pow_wa_com_pc_s cn52xxp1; 1501215976Sjmallett struct cvmx_pow_wa_com_pc_s cn56xx; 1502215976Sjmallett struct cvmx_pow_wa_com_pc_s cn56xxp1; 1503215976Sjmallett struct cvmx_pow_wa_com_pc_s cn58xx; 1504215976Sjmallett struct cvmx_pow_wa_com_pc_s cn58xxp1; 1505232812Sjmallett struct cvmx_pow_wa_com_pc_s cn61xx; 1506215976Sjmallett struct cvmx_pow_wa_com_pc_s cn63xx; 1507215976Sjmallett struct cvmx_pow_wa_com_pc_s cn63xxp1; 1508232812Sjmallett struct cvmx_pow_wa_com_pc_s cn66xx; 1509232812Sjmallett struct cvmx_pow_wa_com_pc_s cnf71xx; 1510215976Sjmallett}; 1511215976Sjmalletttypedef union cvmx_pow_wa_com_pc cvmx_pow_wa_com_pc_t; 1512215976Sjmallett 1513215976Sjmallett/** 1514215976Sjmallett * cvmx_pow_wa_pc# 1515215976Sjmallett * 1516215976Sjmallett * POW_WA_PCX = POW Work Add Performance Counter (1 per QOS level) 1517215976Sjmallett * 1518215976Sjmallett * Counts the number of add new work requests for each QOS level. Write to clear. 1519215976Sjmallett */ 1520232812Sjmallettunion cvmx_pow_wa_pcx { 1521215976Sjmallett uint64_t u64; 1522232812Sjmallett struct cvmx_pow_wa_pcx_s { 1523232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1524215976Sjmallett uint64_t reserved_32_63 : 32; 1525215976Sjmallett uint64_t wa_pc : 32; /**< Work add performance counter for QOS level X */ 1526215976Sjmallett#else 1527215976Sjmallett uint64_t wa_pc : 32; 1528215976Sjmallett uint64_t reserved_32_63 : 32; 1529215976Sjmallett#endif 1530215976Sjmallett } s; 1531215976Sjmallett struct cvmx_pow_wa_pcx_s cn30xx; 1532215976Sjmallett struct cvmx_pow_wa_pcx_s cn31xx; 1533215976Sjmallett struct cvmx_pow_wa_pcx_s cn38xx; 1534215976Sjmallett struct cvmx_pow_wa_pcx_s cn38xxp2; 1535215976Sjmallett struct cvmx_pow_wa_pcx_s cn50xx; 1536215976Sjmallett struct cvmx_pow_wa_pcx_s cn52xx; 1537215976Sjmallett struct cvmx_pow_wa_pcx_s cn52xxp1; 1538215976Sjmallett struct cvmx_pow_wa_pcx_s cn56xx; 1539215976Sjmallett struct cvmx_pow_wa_pcx_s cn56xxp1; 1540215976Sjmallett struct cvmx_pow_wa_pcx_s cn58xx; 1541215976Sjmallett struct cvmx_pow_wa_pcx_s cn58xxp1; 1542232812Sjmallett struct cvmx_pow_wa_pcx_s cn61xx; 1543215976Sjmallett struct cvmx_pow_wa_pcx_s cn63xx; 1544215976Sjmallett struct cvmx_pow_wa_pcx_s cn63xxp1; 1545232812Sjmallett struct cvmx_pow_wa_pcx_s cn66xx; 1546232812Sjmallett struct cvmx_pow_wa_pcx_s cnf71xx; 1547215976Sjmallett}; 1548215976Sjmalletttypedef union cvmx_pow_wa_pcx cvmx_pow_wa_pcx_t; 1549215976Sjmallett 1550215976Sjmallett/** 1551215976Sjmallett * cvmx_pow_wq_int 1552215976Sjmallett * 1553215976Sjmallett * POW_WQ_INT = POW Work Queue Interrupt Register 1554215976Sjmallett * 1555215976Sjmallett * Contains the bits (1 per group) that set work queue interrupts and are used to clear these 1556215976Sjmallett * interrupts. Also contains the input queue interrupt temporary disable bits (1 per group). For 1557215976Sjmallett * more information regarding this register, see the interrupt section. 1558215976Sjmallett */ 1559232812Sjmallettunion cvmx_pow_wq_int { 1560215976Sjmallett uint64_t u64; 1561232812Sjmallett struct cvmx_pow_wq_int_s { 1562232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1563215976Sjmallett uint64_t reserved_32_63 : 32; 1564215976Sjmallett uint64_t iq_dis : 16; /**< Input queue interrupt temporary disable mask 1565215976Sjmallett Corresponding WQ_INT<*> bit cannot be set due to 1566215976Sjmallett IQ_CNT/IQ_THR check when this bit is set. 1567215976Sjmallett Corresponding IQ_DIS bit is cleared by HW whenever: 1568215976Sjmallett - POW_WQ_INT_CNT*[IQ_CNT] is zero, or 1569215976Sjmallett - POW_WQ_INT_CNT*[TC_CNT]==1 when periodic 1570215976Sjmallett counter POW_WQ_INT_PC[PC]==0 */ 1571215976Sjmallett uint64_t wq_int : 16; /**< Work queue interrupt bits 1572215976Sjmallett Corresponding WQ_INT bit is set by HW whenever: 1573215976Sjmallett - POW_WQ_INT_CNT*[IQ_CNT] >= 1574215976Sjmallett POW_WQ_INT_THR*[IQ_THR] and the threshold 1575215976Sjmallett interrupt is not disabled. 1576215976Sjmallett IQ_DIS<*>==1 disables the interrupt. 1577215976Sjmallett POW_WQ_INT_THR*[IQ_THR]==0 disables the int. 1578215976Sjmallett - POW_WQ_INT_CNT*[DS_CNT] >= 1579215976Sjmallett POW_WQ_INT_THR*[DS_THR] and the threshold 1580215976Sjmallett interrupt is not disabled 1581215976Sjmallett POW_WQ_INT_THR*[DS_THR]==0 disables the int. 1582215976Sjmallett - POW_WQ_INT_CNT*[TC_CNT]==1 when periodic 1583215976Sjmallett counter POW_WQ_INT_PC[PC]==0 and 1584215976Sjmallett POW_WQ_INT_THR*[TC_EN]==1 and at least one of: 1585215976Sjmallett - POW_WQ_INT_CNT*[IQ_CNT] > 0 1586215976Sjmallett - POW_WQ_INT_CNT*[DS_CNT] > 0 */ 1587215976Sjmallett#else 1588215976Sjmallett uint64_t wq_int : 16; 1589215976Sjmallett uint64_t iq_dis : 16; 1590215976Sjmallett uint64_t reserved_32_63 : 32; 1591215976Sjmallett#endif 1592215976Sjmallett } s; 1593215976Sjmallett struct cvmx_pow_wq_int_s cn30xx; 1594215976Sjmallett struct cvmx_pow_wq_int_s cn31xx; 1595215976Sjmallett struct cvmx_pow_wq_int_s cn38xx; 1596215976Sjmallett struct cvmx_pow_wq_int_s cn38xxp2; 1597215976Sjmallett struct cvmx_pow_wq_int_s cn50xx; 1598215976Sjmallett struct cvmx_pow_wq_int_s cn52xx; 1599215976Sjmallett struct cvmx_pow_wq_int_s cn52xxp1; 1600215976Sjmallett struct cvmx_pow_wq_int_s cn56xx; 1601215976Sjmallett struct cvmx_pow_wq_int_s cn56xxp1; 1602215976Sjmallett struct cvmx_pow_wq_int_s cn58xx; 1603215976Sjmallett struct cvmx_pow_wq_int_s cn58xxp1; 1604232812Sjmallett struct cvmx_pow_wq_int_s cn61xx; 1605215976Sjmallett struct cvmx_pow_wq_int_s cn63xx; 1606215976Sjmallett struct cvmx_pow_wq_int_s cn63xxp1; 1607232812Sjmallett struct cvmx_pow_wq_int_s cn66xx; 1608232812Sjmallett struct cvmx_pow_wq_int_s cnf71xx; 1609215976Sjmallett}; 1610215976Sjmalletttypedef union cvmx_pow_wq_int cvmx_pow_wq_int_t; 1611215976Sjmallett 1612215976Sjmallett/** 1613215976Sjmallett * cvmx_pow_wq_int_cnt# 1614215976Sjmallett * 1615215976Sjmallett * POW_WQ_INT_CNTX = POW Work Queue Interrupt Count Register (1 per group) 1616215976Sjmallett * 1617215976Sjmallett * Contains a read-only copy of the counts used to trigger work queue interrupts. For more 1618215976Sjmallett * information regarding this register, see the interrupt section. 1619215976Sjmallett */ 1620232812Sjmallettunion cvmx_pow_wq_int_cntx { 1621215976Sjmallett uint64_t u64; 1622232812Sjmallett struct cvmx_pow_wq_int_cntx_s { 1623232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1624215976Sjmallett uint64_t reserved_28_63 : 36; 1625215976Sjmallett uint64_t tc_cnt : 4; /**< Time counter current value for group X 1626215976Sjmallett HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever: 1627215976Sjmallett - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and 1628215976Sjmallett corresponding POW_WQ_INT_CNT*[DS_CNT]==0 1629215976Sjmallett - corresponding POW_WQ_INT[WQ_INT<*>] is written 1630215976Sjmallett with a 1 by SW 1631215976Sjmallett - corresponding POW_WQ_INT[IQ_DIS<*>] is written 1632215976Sjmallett with a 1 by SW 1633215976Sjmallett - corresponding POW_WQ_INT_THR* is written by SW 1634215976Sjmallett - TC_CNT==1 and periodic counter 1635215976Sjmallett POW_WQ_INT_PC[PC]==0 1636215976Sjmallett Otherwise, HW decrements TC_CNT whenever the 1637215976Sjmallett periodic counter POW_WQ_INT_PC[PC]==0. 1638215976Sjmallett TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */ 1639215976Sjmallett uint64_t ds_cnt : 12; /**< De-schedule executable count for group X */ 1640215976Sjmallett uint64_t iq_cnt : 12; /**< Input queue executable count for group X */ 1641215976Sjmallett#else 1642215976Sjmallett uint64_t iq_cnt : 12; 1643215976Sjmallett uint64_t ds_cnt : 12; 1644215976Sjmallett uint64_t tc_cnt : 4; 1645215976Sjmallett uint64_t reserved_28_63 : 36; 1646215976Sjmallett#endif 1647215976Sjmallett } s; 1648232812Sjmallett struct cvmx_pow_wq_int_cntx_cn30xx { 1649232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1650215976Sjmallett uint64_t reserved_28_63 : 36; 1651215976Sjmallett uint64_t tc_cnt : 4; /**< Time counter current value for group X 1652215976Sjmallett HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever: 1653215976Sjmallett - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and 1654215976Sjmallett corresponding POW_WQ_INT_CNT*[DS_CNT]==0 1655215976Sjmallett - corresponding POW_WQ_INT[WQ_INT<*>] is written 1656215976Sjmallett with a 1 by SW 1657215976Sjmallett - corresponding POW_WQ_INT[IQ_DIS<*>] is written 1658215976Sjmallett with a 1 by SW 1659215976Sjmallett - corresponding POW_WQ_INT_THR* is written by SW 1660215976Sjmallett - TC_CNT==1 and periodic counter 1661215976Sjmallett POW_WQ_INT_PC[PC]==0 1662215976Sjmallett Otherwise, HW decrements TC_CNT whenever the 1663215976Sjmallett periodic counter POW_WQ_INT_PC[PC]==0. 1664215976Sjmallett TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */ 1665215976Sjmallett uint64_t reserved_19_23 : 5; 1666215976Sjmallett uint64_t ds_cnt : 7; /**< De-schedule executable count for group X */ 1667215976Sjmallett uint64_t reserved_7_11 : 5; 1668215976Sjmallett uint64_t iq_cnt : 7; /**< Input queue executable count for group X */ 1669215976Sjmallett#else 1670215976Sjmallett uint64_t iq_cnt : 7; 1671215976Sjmallett uint64_t reserved_7_11 : 5; 1672215976Sjmallett uint64_t ds_cnt : 7; 1673215976Sjmallett uint64_t reserved_19_23 : 5; 1674215976Sjmallett uint64_t tc_cnt : 4; 1675215976Sjmallett uint64_t reserved_28_63 : 36; 1676215976Sjmallett#endif 1677215976Sjmallett } cn30xx; 1678232812Sjmallett struct cvmx_pow_wq_int_cntx_cn31xx { 1679232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1680215976Sjmallett uint64_t reserved_28_63 : 36; 1681215976Sjmallett uint64_t tc_cnt : 4; /**< Time counter current value for group X 1682215976Sjmallett HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever: 1683215976Sjmallett - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and 1684215976Sjmallett corresponding POW_WQ_INT_CNT*[DS_CNT]==0 1685215976Sjmallett - corresponding POW_WQ_INT[WQ_INT<*>] is written 1686215976Sjmallett with a 1 by SW 1687215976Sjmallett - corresponding POW_WQ_INT[IQ_DIS<*>] is written 1688215976Sjmallett with a 1 by SW 1689215976Sjmallett - corresponding POW_WQ_INT_THR* is written by SW 1690215976Sjmallett - TC_CNT==1 and periodic counter 1691215976Sjmallett POW_WQ_INT_PC[PC]==0 1692215976Sjmallett Otherwise, HW decrements TC_CNT whenever the 1693215976Sjmallett periodic counter POW_WQ_INT_PC[PC]==0. 1694215976Sjmallett TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */ 1695215976Sjmallett uint64_t reserved_21_23 : 3; 1696215976Sjmallett uint64_t ds_cnt : 9; /**< De-schedule executable count for group X */ 1697215976Sjmallett uint64_t reserved_9_11 : 3; 1698215976Sjmallett uint64_t iq_cnt : 9; /**< Input queue executable count for group X */ 1699215976Sjmallett#else 1700215976Sjmallett uint64_t iq_cnt : 9; 1701215976Sjmallett uint64_t reserved_9_11 : 3; 1702215976Sjmallett uint64_t ds_cnt : 9; 1703215976Sjmallett uint64_t reserved_21_23 : 3; 1704215976Sjmallett uint64_t tc_cnt : 4; 1705215976Sjmallett uint64_t reserved_28_63 : 36; 1706215976Sjmallett#endif 1707215976Sjmallett } cn31xx; 1708215976Sjmallett struct cvmx_pow_wq_int_cntx_s cn38xx; 1709215976Sjmallett struct cvmx_pow_wq_int_cntx_s cn38xxp2; 1710215976Sjmallett struct cvmx_pow_wq_int_cntx_cn31xx cn50xx; 1711232812Sjmallett struct cvmx_pow_wq_int_cntx_cn52xx { 1712232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1713215976Sjmallett uint64_t reserved_28_63 : 36; 1714215976Sjmallett uint64_t tc_cnt : 4; /**< Time counter current value for group X 1715215976Sjmallett HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever: 1716215976Sjmallett - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and 1717215976Sjmallett corresponding POW_WQ_INT_CNT*[DS_CNT]==0 1718215976Sjmallett - corresponding POW_WQ_INT[WQ_INT<*>] is written 1719215976Sjmallett with a 1 by SW 1720215976Sjmallett - corresponding POW_WQ_INT[IQ_DIS<*>] is written 1721215976Sjmallett with a 1 by SW 1722215976Sjmallett - corresponding POW_WQ_INT_THR* is written by SW 1723215976Sjmallett - TC_CNT==1 and periodic counter 1724215976Sjmallett POW_WQ_INT_PC[PC]==0 1725215976Sjmallett Otherwise, HW decrements TC_CNT whenever the 1726215976Sjmallett periodic counter POW_WQ_INT_PC[PC]==0. 1727215976Sjmallett TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */ 1728215976Sjmallett uint64_t reserved_22_23 : 2; 1729215976Sjmallett uint64_t ds_cnt : 10; /**< De-schedule executable count for group X */ 1730215976Sjmallett uint64_t reserved_10_11 : 2; 1731215976Sjmallett uint64_t iq_cnt : 10; /**< Input queue executable count for group X */ 1732215976Sjmallett#else 1733215976Sjmallett uint64_t iq_cnt : 10; 1734215976Sjmallett uint64_t reserved_10_11 : 2; 1735215976Sjmallett uint64_t ds_cnt : 10; 1736215976Sjmallett uint64_t reserved_22_23 : 2; 1737215976Sjmallett uint64_t tc_cnt : 4; 1738215976Sjmallett uint64_t reserved_28_63 : 36; 1739215976Sjmallett#endif 1740215976Sjmallett } cn52xx; 1741215976Sjmallett struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1; 1742215976Sjmallett struct cvmx_pow_wq_int_cntx_s cn56xx; 1743215976Sjmallett struct cvmx_pow_wq_int_cntx_s cn56xxp1; 1744215976Sjmallett struct cvmx_pow_wq_int_cntx_s cn58xx; 1745215976Sjmallett struct cvmx_pow_wq_int_cntx_s cn58xxp1; 1746232812Sjmallett struct cvmx_pow_wq_int_cntx_cn52xx cn61xx; 1747232812Sjmallett struct cvmx_pow_wq_int_cntx_cn63xx { 1748232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1749215976Sjmallett uint64_t reserved_28_63 : 36; 1750215976Sjmallett uint64_t tc_cnt : 4; /**< Time counter current value for group X 1751215976Sjmallett HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever: 1752215976Sjmallett - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and 1753215976Sjmallett corresponding POW_WQ_INT_CNT*[DS_CNT]==0 1754215976Sjmallett - corresponding POW_WQ_INT[WQ_INT<*>] is written 1755215976Sjmallett with a 1 by SW 1756215976Sjmallett - corresponding POW_WQ_INT[IQ_DIS<*>] is written 1757215976Sjmallett with a 1 by SW 1758215976Sjmallett - corresponding POW_WQ_INT_THR* is written by SW 1759215976Sjmallett - TC_CNT==1 and periodic counter 1760215976Sjmallett POW_WQ_INT_PC[PC]==0 1761215976Sjmallett Otherwise, HW decrements TC_CNT whenever the 1762215976Sjmallett periodic counter POW_WQ_INT_PC[PC]==0. 1763215976Sjmallett TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */ 1764215976Sjmallett uint64_t reserved_23_23 : 1; 1765215976Sjmallett uint64_t ds_cnt : 11; /**< De-schedule executable count for group X */ 1766215976Sjmallett uint64_t reserved_11_11 : 1; 1767215976Sjmallett uint64_t iq_cnt : 11; /**< Input queue executable count for group X */ 1768215976Sjmallett#else 1769215976Sjmallett uint64_t iq_cnt : 11; 1770215976Sjmallett uint64_t reserved_11_11 : 1; 1771215976Sjmallett uint64_t ds_cnt : 11; 1772215976Sjmallett uint64_t reserved_23_23 : 1; 1773215976Sjmallett uint64_t tc_cnt : 4; 1774215976Sjmallett uint64_t reserved_28_63 : 36; 1775215976Sjmallett#endif 1776215976Sjmallett } cn63xx; 1777215976Sjmallett struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1; 1778232812Sjmallett struct cvmx_pow_wq_int_cntx_cn63xx cn66xx; 1779232812Sjmallett struct cvmx_pow_wq_int_cntx_cn52xx cnf71xx; 1780215976Sjmallett}; 1781215976Sjmalletttypedef union cvmx_pow_wq_int_cntx cvmx_pow_wq_int_cntx_t; 1782215976Sjmallett 1783215976Sjmallett/** 1784215976Sjmallett * cvmx_pow_wq_int_pc 1785215976Sjmallett * 1786215976Sjmallett * POW_WQ_INT_PC = POW Work Queue Interrupt Periodic Counter Register 1787215976Sjmallett * 1788215976Sjmallett * Contains the threshold value for the work queue interrupt periodic counter and also a read-only 1789215976Sjmallett * copy of the periodic counter. For more information regarding this register, see the interrupt 1790215976Sjmallett * section. 1791215976Sjmallett */ 1792232812Sjmallettunion cvmx_pow_wq_int_pc { 1793215976Sjmallett uint64_t u64; 1794232812Sjmallett struct cvmx_pow_wq_int_pc_s { 1795232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1796215976Sjmallett uint64_t reserved_60_63 : 4; 1797215976Sjmallett uint64_t pc : 28; /**< Work queue interrupt periodic counter */ 1798215976Sjmallett uint64_t reserved_28_31 : 4; 1799215976Sjmallett uint64_t pc_thr : 20; /**< Work queue interrupt periodic counter threshold */ 1800215976Sjmallett uint64_t reserved_0_7 : 8; 1801215976Sjmallett#else 1802215976Sjmallett uint64_t reserved_0_7 : 8; 1803215976Sjmallett uint64_t pc_thr : 20; 1804215976Sjmallett uint64_t reserved_28_31 : 4; 1805215976Sjmallett uint64_t pc : 28; 1806215976Sjmallett uint64_t reserved_60_63 : 4; 1807215976Sjmallett#endif 1808215976Sjmallett } s; 1809215976Sjmallett struct cvmx_pow_wq_int_pc_s cn30xx; 1810215976Sjmallett struct cvmx_pow_wq_int_pc_s cn31xx; 1811215976Sjmallett struct cvmx_pow_wq_int_pc_s cn38xx; 1812215976Sjmallett struct cvmx_pow_wq_int_pc_s cn38xxp2; 1813215976Sjmallett struct cvmx_pow_wq_int_pc_s cn50xx; 1814215976Sjmallett struct cvmx_pow_wq_int_pc_s cn52xx; 1815215976Sjmallett struct cvmx_pow_wq_int_pc_s cn52xxp1; 1816215976Sjmallett struct cvmx_pow_wq_int_pc_s cn56xx; 1817215976Sjmallett struct cvmx_pow_wq_int_pc_s cn56xxp1; 1818215976Sjmallett struct cvmx_pow_wq_int_pc_s cn58xx; 1819215976Sjmallett struct cvmx_pow_wq_int_pc_s cn58xxp1; 1820232812Sjmallett struct cvmx_pow_wq_int_pc_s cn61xx; 1821215976Sjmallett struct cvmx_pow_wq_int_pc_s cn63xx; 1822215976Sjmallett struct cvmx_pow_wq_int_pc_s cn63xxp1; 1823232812Sjmallett struct cvmx_pow_wq_int_pc_s cn66xx; 1824232812Sjmallett struct cvmx_pow_wq_int_pc_s cnf71xx; 1825215976Sjmallett}; 1826215976Sjmalletttypedef union cvmx_pow_wq_int_pc cvmx_pow_wq_int_pc_t; 1827215976Sjmallett 1828215976Sjmallett/** 1829215976Sjmallett * cvmx_pow_wq_int_thr# 1830215976Sjmallett * 1831215976Sjmallett * POW_WQ_INT_THRX = POW Work Queue Interrupt Threshold Register (1 per group) 1832215976Sjmallett * 1833215976Sjmallett * Contains the thresholds for enabling and setting work queue interrupts. For more information 1834215976Sjmallett * regarding this register, see the interrupt section. 1835215976Sjmallett * 1836232812Sjmallett * Note: Up to 4 of the POW's internal storage buffers can be allocated for hardware use and are 1837215976Sjmallett * therefore not available for incoming work queue entries. Additionally, any PP that is not in the 1838232812Sjmallett * NULL_NULL state consumes a buffer. Thus in a 4 PP system, it is not advisable to set either 1839232812Sjmallett * IQ_THR or DS_THR to greater than 512 - 4 - 4 = 504. Doing so may prevent the interrupt from 1840215976Sjmallett * ever triggering. 1841215976Sjmallett */ 1842232812Sjmallettunion cvmx_pow_wq_int_thrx { 1843215976Sjmallett uint64_t u64; 1844232812Sjmallett struct cvmx_pow_wq_int_thrx_s { 1845232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1846215976Sjmallett uint64_t reserved_29_63 : 35; 1847215976Sjmallett uint64_t tc_en : 1; /**< Time counter interrupt enable for group X 1848215976Sjmallett TC_EN must be zero when TC_THR==0 */ 1849215976Sjmallett uint64_t tc_thr : 4; /**< Time counter interrupt threshold for group X 1850215976Sjmallett When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */ 1851215976Sjmallett uint64_t reserved_23_23 : 1; 1852215976Sjmallett uint64_t ds_thr : 11; /**< De-schedule count threshold for group X 1853215976Sjmallett DS_THR==0 disables the threshold interrupt */ 1854215976Sjmallett uint64_t reserved_11_11 : 1; 1855215976Sjmallett uint64_t iq_thr : 11; /**< Input queue count threshold for group X 1856215976Sjmallett IQ_THR==0 disables the threshold interrupt */ 1857215976Sjmallett#else 1858215976Sjmallett uint64_t iq_thr : 11; 1859215976Sjmallett uint64_t reserved_11_11 : 1; 1860215976Sjmallett uint64_t ds_thr : 11; 1861215976Sjmallett uint64_t reserved_23_23 : 1; 1862215976Sjmallett uint64_t tc_thr : 4; 1863215976Sjmallett uint64_t tc_en : 1; 1864215976Sjmallett uint64_t reserved_29_63 : 35; 1865215976Sjmallett#endif 1866215976Sjmallett } s; 1867232812Sjmallett struct cvmx_pow_wq_int_thrx_cn30xx { 1868232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1869215976Sjmallett uint64_t reserved_29_63 : 35; 1870215976Sjmallett uint64_t tc_en : 1; /**< Time counter interrupt enable for group X 1871215976Sjmallett TC_EN must be zero when TC_THR==0 */ 1872215976Sjmallett uint64_t tc_thr : 4; /**< Time counter interrupt threshold for group X 1873215976Sjmallett When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */ 1874215976Sjmallett uint64_t reserved_18_23 : 6; 1875215976Sjmallett uint64_t ds_thr : 6; /**< De-schedule count threshold for group X 1876215976Sjmallett DS_THR==0 disables the threshold interrupt */ 1877215976Sjmallett uint64_t reserved_6_11 : 6; 1878215976Sjmallett uint64_t iq_thr : 6; /**< Input queue count threshold for group X 1879215976Sjmallett IQ_THR==0 disables the threshold interrupt */ 1880215976Sjmallett#else 1881215976Sjmallett uint64_t iq_thr : 6; 1882215976Sjmallett uint64_t reserved_6_11 : 6; 1883215976Sjmallett uint64_t ds_thr : 6; 1884215976Sjmallett uint64_t reserved_18_23 : 6; 1885215976Sjmallett uint64_t tc_thr : 4; 1886215976Sjmallett uint64_t tc_en : 1; 1887215976Sjmallett uint64_t reserved_29_63 : 35; 1888215976Sjmallett#endif 1889215976Sjmallett } cn30xx; 1890232812Sjmallett struct cvmx_pow_wq_int_thrx_cn31xx { 1891232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1892215976Sjmallett uint64_t reserved_29_63 : 35; 1893215976Sjmallett uint64_t tc_en : 1; /**< Time counter interrupt enable for group X 1894215976Sjmallett TC_EN must be zero when TC_THR==0 */ 1895215976Sjmallett uint64_t tc_thr : 4; /**< Time counter interrupt threshold for group X 1896215976Sjmallett When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */ 1897215976Sjmallett uint64_t reserved_20_23 : 4; 1898215976Sjmallett uint64_t ds_thr : 8; /**< De-schedule count threshold for group X 1899215976Sjmallett DS_THR==0 disables the threshold interrupt */ 1900215976Sjmallett uint64_t reserved_8_11 : 4; 1901215976Sjmallett uint64_t iq_thr : 8; /**< Input queue count threshold for group X 1902215976Sjmallett IQ_THR==0 disables the threshold interrupt */ 1903215976Sjmallett#else 1904215976Sjmallett uint64_t iq_thr : 8; 1905215976Sjmallett uint64_t reserved_8_11 : 4; 1906215976Sjmallett uint64_t ds_thr : 8; 1907215976Sjmallett uint64_t reserved_20_23 : 4; 1908215976Sjmallett uint64_t tc_thr : 4; 1909215976Sjmallett uint64_t tc_en : 1; 1910215976Sjmallett uint64_t reserved_29_63 : 35; 1911215976Sjmallett#endif 1912215976Sjmallett } cn31xx; 1913215976Sjmallett struct cvmx_pow_wq_int_thrx_s cn38xx; 1914215976Sjmallett struct cvmx_pow_wq_int_thrx_s cn38xxp2; 1915215976Sjmallett struct cvmx_pow_wq_int_thrx_cn31xx cn50xx; 1916232812Sjmallett struct cvmx_pow_wq_int_thrx_cn52xx { 1917232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1918215976Sjmallett uint64_t reserved_29_63 : 35; 1919215976Sjmallett uint64_t tc_en : 1; /**< Time counter interrupt enable for group X 1920215976Sjmallett TC_EN must be zero when TC_THR==0 */ 1921215976Sjmallett uint64_t tc_thr : 4; /**< Time counter interrupt threshold for group X 1922215976Sjmallett When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */ 1923215976Sjmallett uint64_t reserved_21_23 : 3; 1924215976Sjmallett uint64_t ds_thr : 9; /**< De-schedule count threshold for group X 1925215976Sjmallett DS_THR==0 disables the threshold interrupt */ 1926215976Sjmallett uint64_t reserved_9_11 : 3; 1927215976Sjmallett uint64_t iq_thr : 9; /**< Input queue count threshold for group X 1928215976Sjmallett IQ_THR==0 disables the threshold interrupt */ 1929215976Sjmallett#else 1930215976Sjmallett uint64_t iq_thr : 9; 1931215976Sjmallett uint64_t reserved_9_11 : 3; 1932215976Sjmallett uint64_t ds_thr : 9; 1933215976Sjmallett uint64_t reserved_21_23 : 3; 1934215976Sjmallett uint64_t tc_thr : 4; 1935215976Sjmallett uint64_t tc_en : 1; 1936215976Sjmallett uint64_t reserved_29_63 : 35; 1937215976Sjmallett#endif 1938215976Sjmallett } cn52xx; 1939215976Sjmallett struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1; 1940215976Sjmallett struct cvmx_pow_wq_int_thrx_s cn56xx; 1941215976Sjmallett struct cvmx_pow_wq_int_thrx_s cn56xxp1; 1942215976Sjmallett struct cvmx_pow_wq_int_thrx_s cn58xx; 1943215976Sjmallett struct cvmx_pow_wq_int_thrx_s cn58xxp1; 1944232812Sjmallett struct cvmx_pow_wq_int_thrx_cn52xx cn61xx; 1945232812Sjmallett struct cvmx_pow_wq_int_thrx_cn63xx { 1946232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1947215976Sjmallett uint64_t reserved_29_63 : 35; 1948215976Sjmallett uint64_t tc_en : 1; /**< Time counter interrupt enable for group X 1949215976Sjmallett TC_EN must be zero when TC_THR==0 */ 1950215976Sjmallett uint64_t tc_thr : 4; /**< Time counter interrupt threshold for group X 1951215976Sjmallett When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */ 1952215976Sjmallett uint64_t reserved_22_23 : 2; 1953215976Sjmallett uint64_t ds_thr : 10; /**< De-schedule count threshold for group X 1954215976Sjmallett DS_THR==0 disables the threshold interrupt */ 1955215976Sjmallett uint64_t reserved_10_11 : 2; 1956215976Sjmallett uint64_t iq_thr : 10; /**< Input queue count threshold for group X 1957215976Sjmallett IQ_THR==0 disables the threshold interrupt */ 1958215976Sjmallett#else 1959215976Sjmallett uint64_t iq_thr : 10; 1960215976Sjmallett uint64_t reserved_10_11 : 2; 1961215976Sjmallett uint64_t ds_thr : 10; 1962215976Sjmallett uint64_t reserved_22_23 : 2; 1963215976Sjmallett uint64_t tc_thr : 4; 1964215976Sjmallett uint64_t tc_en : 1; 1965215976Sjmallett uint64_t reserved_29_63 : 35; 1966215976Sjmallett#endif 1967215976Sjmallett } cn63xx; 1968215976Sjmallett struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1; 1969232812Sjmallett struct cvmx_pow_wq_int_thrx_cn63xx cn66xx; 1970232812Sjmallett struct cvmx_pow_wq_int_thrx_cn52xx cnf71xx; 1971215976Sjmallett}; 1972215976Sjmalletttypedef union cvmx_pow_wq_int_thrx cvmx_pow_wq_int_thrx_t; 1973215976Sjmallett 1974215976Sjmallett/** 1975215976Sjmallett * cvmx_pow_ws_pc# 1976215976Sjmallett * 1977215976Sjmallett * POW_WS_PCX = POW Work Schedule Performance Counter (1 per group) 1978215976Sjmallett * 1979215976Sjmallett * Counts the number of work schedules for each group. Write to clear. 1980215976Sjmallett */ 1981232812Sjmallettunion cvmx_pow_ws_pcx { 1982215976Sjmallett uint64_t u64; 1983232812Sjmallett struct cvmx_pow_ws_pcx_s { 1984232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1985215976Sjmallett uint64_t reserved_32_63 : 32; 1986215976Sjmallett uint64_t ws_pc : 32; /**< Work schedule performance counter for group X */ 1987215976Sjmallett#else 1988215976Sjmallett uint64_t ws_pc : 32; 1989215976Sjmallett uint64_t reserved_32_63 : 32; 1990215976Sjmallett#endif 1991215976Sjmallett } s; 1992215976Sjmallett struct cvmx_pow_ws_pcx_s cn30xx; 1993215976Sjmallett struct cvmx_pow_ws_pcx_s cn31xx; 1994215976Sjmallett struct cvmx_pow_ws_pcx_s cn38xx; 1995215976Sjmallett struct cvmx_pow_ws_pcx_s cn38xxp2; 1996215976Sjmallett struct cvmx_pow_ws_pcx_s cn50xx; 1997215976Sjmallett struct cvmx_pow_ws_pcx_s cn52xx; 1998215976Sjmallett struct cvmx_pow_ws_pcx_s cn52xxp1; 1999215976Sjmallett struct cvmx_pow_ws_pcx_s cn56xx; 2000215976Sjmallett struct cvmx_pow_ws_pcx_s cn56xxp1; 2001215976Sjmallett struct cvmx_pow_ws_pcx_s cn58xx; 2002215976Sjmallett struct cvmx_pow_ws_pcx_s cn58xxp1; 2003232812Sjmallett struct cvmx_pow_ws_pcx_s cn61xx; 2004215976Sjmallett struct cvmx_pow_ws_pcx_s cn63xx; 2005215976Sjmallett struct cvmx_pow_ws_pcx_s cn63xxp1; 2006232812Sjmallett struct cvmx_pow_ws_pcx_s cn66xx; 2007232812Sjmallett struct cvmx_pow_ws_pcx_s cnf71xx; 2008215976Sjmallett}; 2009215976Sjmalletttypedef union cvmx_pow_ws_pcx cvmx_pow_ws_pcx_t; 2010215976Sjmallett 2011215976Sjmallett#endif 2012