1210284Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17210284Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22210284Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27210284Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215990Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett/** 42210284Sjmallett * @file 43210284Sjmallett * 44210284Sjmallett * Interface to the hardware Packet Input Processing unit. 45210284Sjmallett * 46232812Sjmallett * <hr>$Revision: 70030 $<hr> 47210284Sjmallett */ 48210284Sjmallett 49210284Sjmallett 50210284Sjmallett#ifndef __CVMX_PIP_H__ 51210284Sjmallett#define __CVMX_PIP_H__ 52210284Sjmallett 53210284Sjmallett#include "cvmx-wqe.h" 54210284Sjmallett#include "cvmx-fpa.h" 55215990Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 56215990Sjmallett#include "cvmx-pip-defs.h" 57215990Sjmallett#else 58210284Sjmallett#ifndef CVMX_DONT_INCLUDE_CONFIG 59210284Sjmallett#include "executive-config.h" 60210284Sjmallett#endif 61215990Sjmallett#endif 62210284Sjmallett 63232812Sjmallett#include "cvmx-helper.h" 64232812Sjmallett#include "cvmx-helper-util.h" 65215990Sjmallett 66232812Sjmallett 67210284Sjmallett#ifdef __cplusplus 68210284Sjmallettextern "C" { 69210284Sjmallett#endif 70210284Sjmallett 71232812Sjmallett#define CVMX_PIP_NUM_INPUT_PORTS 46 72210284Sjmallett 73215990Sjmallett/* 74215990Sjmallett * Encodes the different error and exception codes 75215990Sjmallett */ 76210284Sjmalletttypedef enum 77210284Sjmallett{ 78210284Sjmallett CVMX_PIP_L4_NO_ERR = 0ull, 79215990Sjmallett /* 1 = TCP (UDP) packet not long enough to cover TCP (UDP) header */ 80210284Sjmallett CVMX_PIP_L4_MAL_ERR = 1ull, 81215990Sjmallett /* 2 = TCP/UDP checksum failure */ 82210284Sjmallett CVMX_PIP_CHK_ERR = 2ull, 83215990Sjmallett /* 3 = TCP/UDP length check (TCP/UDP length does not match IP length) */ 84210284Sjmallett CVMX_PIP_L4_LENGTH_ERR = 3ull, 85215990Sjmallett /* 4 = illegal TCP/UDP port (either source or dest port is zero) */ 86210284Sjmallett CVMX_PIP_BAD_PRT_ERR = 4ull, 87215990Sjmallett /* 8 = TCP flags = FIN only */ 88210284Sjmallett CVMX_PIP_TCP_FLG8_ERR = 8ull, 89215990Sjmallett /* 9 = TCP flags = 0 */ 90210284Sjmallett CVMX_PIP_TCP_FLG9_ERR = 9ull, 91215990Sjmallett /* 10 = TCP flags = FIN+RST+* */ 92210284Sjmallett CVMX_PIP_TCP_FLG10_ERR = 10ull, 93215990Sjmallett /* 11 = TCP flags = SYN+URG+* */ 94210284Sjmallett CVMX_PIP_TCP_FLG11_ERR = 11ull, 95215990Sjmallett /* 12 = TCP flags = SYN+RST+* */ 96210284Sjmallett CVMX_PIP_TCP_FLG12_ERR = 12ull, 97215990Sjmallett /* 13 = TCP flags = SYN+FIN+* */ 98210284Sjmallett CVMX_PIP_TCP_FLG13_ERR = 13ull 99210284Sjmallett} cvmx_pip_l4_err_t; 100210284Sjmallett 101210284Sjmalletttypedef enum 102210284Sjmallett{ 103210284Sjmallett 104210284Sjmallett CVMX_PIP_IP_NO_ERR = 0ull, 105215990Sjmallett /* 1 = not IPv4 or IPv6 */ 106210284Sjmallett CVMX_PIP_NOT_IP = 1ull, 107215990Sjmallett /* 2 = IPv4 header checksum violation */ 108210284Sjmallett CVMX_PIP_IPV4_HDR_CHK = 2ull, 109215990Sjmallett /* 3 = malformed (packet not long enough to cover IP hdr) */ 110210284Sjmallett CVMX_PIP_IP_MAL_HDR = 3ull, 111215990Sjmallett /* 4 = malformed (packet not long enough to cover len in IP hdr) */ 112210284Sjmallett CVMX_PIP_IP_MAL_PKT = 4ull, 113215990Sjmallett /* 5 = TTL / hop count equal zero */ 114210284Sjmallett CVMX_PIP_TTL_HOP = 5ull, 115215990Sjmallett /* 6 = IPv4 options / IPv6 early extension headers */ 116210284Sjmallett CVMX_PIP_OPTS = 6ull 117210284Sjmallett} cvmx_pip_ip_exc_t; 118210284Sjmallett 119210284Sjmallett 120210284Sjmallett/** 121210284Sjmallett * NOTES 122210284Sjmallett * late collision (data received before collision) 123210284Sjmallett * late collisions cannot be detected by the receiver 124210284Sjmallett * they would appear as JAM bits which would appear as bad FCS 125210284Sjmallett * or carrier extend error which is CVMX_PIP_EXTEND_ERR 126210284Sjmallett */ 127210284Sjmalletttypedef enum 128210284Sjmallett{ 129210284Sjmallett /** 130210284Sjmallett * No error 131210284Sjmallett */ 132210284Sjmallett CVMX_PIP_RX_NO_ERR = 0ull, 133210284Sjmallett 134215990Sjmallett CVMX_PIP_PARTIAL_ERR = 1ull, /* RGM+SPI 1 = partially received packet (buffering/bandwidth not adequate) */ 135215990Sjmallett CVMX_PIP_JABBER_ERR = 2ull, /* RGM+SPI 2 = receive packet too large and truncated */ 136215990Sjmallett CVMX_PIP_OVER_FCS_ERR = 3ull, /* RGM 3 = max frame error (pkt len > max frame len) (with FCS error) */ 137215990Sjmallett CVMX_PIP_OVER_ERR = 4ull, /* RGM+SPI 4 = max frame error (pkt len > max frame len) */ 138215990Sjmallett CVMX_PIP_ALIGN_ERR = 5ull, /* RGM 5 = nibble error (data not byte multiple - 100M and 10M only) */ 139215990Sjmallett CVMX_PIP_UNDER_FCS_ERR = 6ull, /* RGM 6 = min frame error (pkt len < min frame len) (with FCS error) */ 140215990Sjmallett CVMX_PIP_GMX_FCS_ERR = 7ull, /* RGM 7 = FCS error */ 141215990Sjmallett CVMX_PIP_UNDER_ERR = 8ull, /* RGM+SPI 8 = min frame error (pkt len < min frame len) */ 142215990Sjmallett CVMX_PIP_EXTEND_ERR = 9ull, /* RGM 9 = Frame carrier extend error */ 143215990Sjmallett CVMX_PIP_TERMINATE_ERR = 9ull, /* XAUI 9 = Packet was terminated with an idle cycle */ 144215990Sjmallett CVMX_PIP_LENGTH_ERR = 10ull, /* RGM 10 = length mismatch (len did not match len in L2 length/type) */ 145215990Sjmallett CVMX_PIP_DAT_ERR = 11ull, /* RGM 11 = Frame error (some or all data bits marked err) */ 146215990Sjmallett CVMX_PIP_DIP_ERR = 11ull, /* SPI 11 = DIP4 error */ 147215990Sjmallett CVMX_PIP_SKIP_ERR = 12ull, /* RGM 12 = packet was not large enough to pass the skipper - no inspection could occur */ 148215990Sjmallett CVMX_PIP_NIBBLE_ERR = 13ull, /* RGM 13 = studder error (data not repeated - 100M and 10M only) */ 149215990Sjmallett CVMX_PIP_PIP_FCS = 16L, /* RGM+SPI 16 = FCS error */ 150215990Sjmallett CVMX_PIP_PIP_SKIP_ERR = 17L, /* RGM+SPI+PCI 17 = packet was not large enough to pass the skipper - no inspection could occur */ 151215990Sjmallett CVMX_PIP_PIP_L2_MAL_HDR= 18L, /* RGM+SPI+PCI 18 = malformed l2 (packet not long enough to cover L2 hdr) */ 152215990Sjmallett CVMX_PIP_PUNY_ERR = 47L /* SGMII 47 = PUNY error (packet was 4B or less when FCS stripping is enabled) */ 153215990Sjmallett /* NOTES 154215990Sjmallett * xx = late collision (data received before collision) 155215990Sjmallett * late collisions cannot be detected by the receiver 156215990Sjmallett * they would appear as JAM bits which would appear as bad FCS 157215990Sjmallett * or carrier extend error which is CVMX_PIP_EXTEND_ERR 158215990Sjmallett */ 159210284Sjmallett} cvmx_pip_rcv_err_t; 160210284Sjmallett 161210284Sjmallett/** 162210284Sjmallett * This defines the err_code field errors in the work Q entry 163210284Sjmallett */ 164210284Sjmalletttypedef union 165210284Sjmallett{ 166210284Sjmallett cvmx_pip_l4_err_t l4_err; 167210284Sjmallett cvmx_pip_ip_exc_t ip_exc; 168210284Sjmallett cvmx_pip_rcv_err_t rcv_err; 169210284Sjmallett} cvmx_pip_err_t; 170210284Sjmallett 171210284Sjmallett 172210284Sjmallett/** 173210284Sjmallett * Status statistics for a port 174210284Sjmallett */ 175210284Sjmalletttypedef struct 176210284Sjmallett{ 177210284Sjmallett uint32_t dropped_octets; /**< Inbound octets marked to be dropped by the IPD */ 178210284Sjmallett uint32_t dropped_packets; /**< Inbound packets marked to be dropped by the IPD */ 179210284Sjmallett uint32_t pci_raw_packets; /**< RAW PCI Packets received by PIP per port */ 180210284Sjmallett uint32_t octets; /**< Number of octets processed by PIP */ 181210284Sjmallett uint32_t packets; /**< Number of packets processed by PIP */ 182210284Sjmallett uint32_t multicast_packets; /**< Number of indentified L2 multicast packets. 183210284Sjmallett Does not include broadcast packets. 184210284Sjmallett Only includes packets whose parse mode is 185210284Sjmallett SKIP_TO_L2 */ 186210284Sjmallett uint32_t broadcast_packets; /**< Number of indentified L2 broadcast packets. 187210284Sjmallett Does not include multicast packets. 188210284Sjmallett Only includes packets whose parse mode is 189210284Sjmallett SKIP_TO_L2 */ 190210284Sjmallett uint32_t len_64_packets; /**< Number of 64B packets */ 191210284Sjmallett uint32_t len_65_127_packets; /**< Number of 65-127B packets */ 192210284Sjmallett uint32_t len_128_255_packets; /**< Number of 128-255B packets */ 193210284Sjmallett uint32_t len_256_511_packets; /**< Number of 256-511B packets */ 194210284Sjmallett uint32_t len_512_1023_packets; /**< Number of 512-1023B packets */ 195210284Sjmallett uint32_t len_1024_1518_packets; /**< Number of 1024-1518B packets */ 196210284Sjmallett uint32_t len_1519_max_packets; /**< Number of 1519-max packets */ 197210284Sjmallett uint32_t fcs_align_err_packets; /**< Number of packets with FCS or Align opcode errors */ 198210284Sjmallett uint32_t runt_packets; /**< Number of packets with length < min */ 199210284Sjmallett uint32_t runt_crc_packets; /**< Number of packets with length < min and FCS error */ 200210284Sjmallett uint32_t oversize_packets; /**< Number of packets with length > max */ 201210284Sjmallett uint32_t oversize_crc_packets; /**< Number of packets with length > max and FCS error */ 202210284Sjmallett uint32_t inb_packets; /**< Number of packets without GMX/SPX/PCI errors received by PIP */ 203210284Sjmallett uint64_t inb_octets; /**< Total number of octets from all packets received by PIP, including CRC */ 204210284Sjmallett uint16_t inb_errors; /**< Number of packets with GMX/SPX/PCI errors received by PIP */ 205232812Sjmallett uint32_t mcast_l2_red_packets; /**< Number of packets with L2 Multicast DMAC 206232812Sjmallett that were dropped due to RED. 207232812Sjmallett The HW will consider a packet to be an L2 208232812Sjmallett multicast packet when the least-significant bit 209232812Sjmallett of the first byte of the DMAC is set and the 210232812Sjmallett packet is not an L2 broadcast packet. 211232812Sjmallett Only applies when the parse mode for the packets 212232812Sjmallett is SKIP-TO-L2 */ 213232812Sjmallett uint32_t bcast_l2_red_packets; /**< Number of packets with L2 Broadcast DMAC 214232812Sjmallett that were dropped due to RED. 215232812Sjmallett The HW will consider a packet to be an L2 216232812Sjmallett broadcast packet when the 48-bit DMAC is all 1's. 217232812Sjmallett Only applies when the parse mode for the packets 218232812Sjmallett is SKIP-TO-L2 */ 219232812Sjmallett uint32_t mcast_l3_red_packets; /**< Number of packets with L3 Multicast Dest Address 220232812Sjmallett that were dropped due to RED. 221232812Sjmallett The HW considers an IPv4 packet to be multicast 222232812Sjmallett when the most-significant nibble of the 32-bit 223232812Sjmallett destination address is 0xE (i.e it is a class D 224232812Sjmallett address). The HW considers an IPv6 packet to be 225232812Sjmallett multicast when the most-significant byte of the 226232812Sjmallett 128-bit destination address is all 1's. 227232812Sjmallett Only applies when the parse mode for the packets 228232812Sjmallett is SKIP-TO-L2 and the packet is IP or the parse 229232812Sjmallett mode for the packet is SKIP-TO-IP */ 230232812Sjmallett uint32_t bcast_l3_red_packets; /**< Number of packets with L3 Broadcast Dest Address 231232812Sjmallett that were dropped due to RED. 232232812Sjmallett The HW considers an IPv4 packet to be broadcast 233232812Sjmallett when all bits are set in the MSB of the 234232812Sjmallett destination address. IPv6 does not have the 235232812Sjmallett concept of a broadcast packets. 236232812Sjmallett Only applies when the parse mode for the packet 237232812Sjmallett is SKIP-TO-L2 and the packet is IP or the parse 238232812Sjmallett mode for the packet is SKIP-TO-IP */ 239210284Sjmallett} cvmx_pip_port_status_t; 240210284Sjmallett 241210284Sjmallett 242210284Sjmallett/** 243210284Sjmallett * Definition of the PIP custom header that can be prepended 244210284Sjmallett * to a packet by external hardware. 245210284Sjmallett */ 246210284Sjmalletttypedef union 247210284Sjmallett{ 248210284Sjmallett uint64_t u64; 249210284Sjmallett struct 250210284Sjmallett { 251210284Sjmallett uint64_t rawfull : 1; /**< Documented as R - Set if the Packet is RAWFULL. If set, 252210284Sjmallett this header must be the full 8 bytes */ 253210284Sjmallett uint64_t reserved0 : 5; /**< Must be zero */ 254210284Sjmallett cvmx_pip_port_parse_mode_t parse_mode : 2; /**< PIP parse mode for this packet */ 255210284Sjmallett uint64_t reserved1 : 1; /**< Must be zero */ 256210284Sjmallett uint64_t skip_len : 7; /**< Skip amount, including this header, to the beginning of the packet */ 257232812Sjmallett uint64_t grpext : 2; /**< These bits get concatenated with the 258232812Sjmallett PKT_INST_HDR[GRP] bits, creating a 6-bit 259232812Sjmallett GRP field. Added in pass2. */ 260215990Sjmallett uint64_t nqos : 1; /**< Must be 0 when PKT_INST_HDR[R] = 0. 261215990Sjmallett When set to 1, NQOS prevents PIP from directly using 262215990Sjmallett PKT_INST_HDR[QOS] for the QOS value in WQE. 263215990Sjmallett When PIP_GBL_CTL[IHMSK_DIS] = 1, Octeon2 does not use NQOS */ 264215990Sjmallett uint64_t ngrp : 1; /**< Must be 0 when PKT_INST_HDR[R] = 0. 265215990Sjmallett When set to 1, NGPR prevents PIP from directly using 266215990Sjmallett PKT_INST_HDR[GPR] for the GPR value in WQE. 267215990Sjmallett When PIP_GBL_CTL[IHMSK_DIS] = 1, Octeon2 does not use NGRP */ 268215990Sjmallett uint64_t ntt : 1; /**< Must be 0 when PKT_INST_HDR[R] = 0. 269215990Sjmallett When set to 1, NTT prevents PIP from directly using 270215990Sjmallett PKT_INST_HDR[TT] for the TT value in WQE. 271215990Sjmallett When PIP_GBL_CTL[IHMSK_DIS] = 1, Octeon2 does not use NTT */ 272215990Sjmallett uint64_t ntag : 1; /**< Must be 0 when PKT_INST_HDR[R] = 0. 273215990Sjmallett When set to 1, NTAG prevents PIP from directly using 274215990Sjmallett PKT_INST_HDR[TAG] for the TAG value in WQE. 275215990Sjmallett When PIP_GBL_CTL[IHMSK_DIS] = 1, Octeon2 does not use NTAG */ 276210284Sjmallett uint64_t qos : 3; /**< POW input queue for this packet */ 277210284Sjmallett uint64_t grp : 4; /**< POW input group for this packet */ 278210284Sjmallett uint64_t rs : 1; /**< Flag to store this packet in the work queue entry, if possible */ 279210284Sjmallett cvmx_pow_tag_type_t tag_type : 2; /**< POW input tag type */ 280210284Sjmallett uint64_t tag : 32; /**< POW input tag */ 281210284Sjmallett } s; 282210284Sjmallett} cvmx_pip_pkt_inst_hdr_t; 283210284Sjmallett 284215990Sjmallett/* CSR typedefs have been moved to cvmx-pip-defs.h */ 285210284Sjmallett 286210284Sjmallett/** 287210284Sjmallett * Configure an ethernet input port 288210284Sjmallett * 289210284Sjmallett * @param port_num Port number to configure 290210284Sjmallett * @param port_cfg Port hardware configuration 291210284Sjmallett * @param port_tag_cfg 292210284Sjmallett * Port POW tagging configuration 293210284Sjmallett */ 294210284Sjmallettstatic inline void cvmx_pip_config_port(uint64_t port_num, 295215990Sjmallett cvmx_pip_prt_cfgx_t port_cfg, 296215990Sjmallett cvmx_pip_prt_tagx_t port_tag_cfg) 297210284Sjmallett{ 298210284Sjmallett 299232812Sjmallett if (octeon_has_feature(OCTEON_FEATURE_PKND)) 300232812Sjmallett { 301232812Sjmallett int interface, index, pknd; 302210284Sjmallett 303232812Sjmallett interface = cvmx_helper_get_interface_num(port_num); 304232812Sjmallett index = cvmx_helper_get_interface_index_num(port_num); 305232812Sjmallett pknd = cvmx_helper_get_pknd(interface, index); 306210284Sjmallett 307232812Sjmallett port_num = pknd; /* overload port_num with pknd */ 308232812Sjmallett } 309210284Sjmallett 310232812Sjmallett cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64); 311232812Sjmallett cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64); 312210284Sjmallett} 313210284Sjmallett 314210284Sjmallett 315210284Sjmallett/** 316210284Sjmallett * Configure the VLAN priority to QoS queue mapping. 317210284Sjmallett * 318210284Sjmallett * @param vlan_priority 319210284Sjmallett * VLAN priority (0-7) 320210284Sjmallett * @param qos QoS queue for packets matching this watcher 321210284Sjmallett */ 322210284Sjmallettstatic inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority, uint64_t qos) 323210284Sjmallett{ 324232812Sjmallett if (octeon_has_feature(OCTEON_FEATURE_PKND)) 325232812Sjmallett { 326232812Sjmallett /* FIXME for 68xx. */ 327232812Sjmallett } 328232812Sjmallett else 329232812Sjmallett { 330232812Sjmallett cvmx_pip_qos_vlanx_t pip_qos_vlanx; 331232812Sjmallett pip_qos_vlanx.u64 = 0; 332232812Sjmallett pip_qos_vlanx.s.qos = qos; 333232812Sjmallett cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64); 334232812Sjmallett } 335210284Sjmallett} 336210284Sjmallett 337210284Sjmallett 338210284Sjmallett/** 339210284Sjmallett * Configure the Diffserv to QoS queue mapping. 340210284Sjmallett * 341210284Sjmallett * @param diffserv Diffserv field value (0-63) 342210284Sjmallett * @param qos QoS queue for packets matching this watcher 343210284Sjmallett */ 344210284Sjmallettstatic inline void cvmx_pip_config_diffserv_qos(uint64_t diffserv, uint64_t qos) 345210284Sjmallett{ 346232812Sjmallett if (octeon_has_feature(OCTEON_FEATURE_PKND)) 347232812Sjmallett { 348232812Sjmallett /* FIXME for 68xx. */ 349232812Sjmallett } 350232812Sjmallett else 351232812Sjmallett { 352232812Sjmallett cvmx_pip_qos_diffx_t pip_qos_diffx; 353232812Sjmallett pip_qos_diffx.u64 = 0; 354232812Sjmallett pip_qos_diffx.s.qos = qos; 355232812Sjmallett cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64); 356232812Sjmallett } 357210284Sjmallett} 358210284Sjmallett 359210284Sjmallett 360210284Sjmallett/** 361210284Sjmallett * Get the status counters for a port. 362210284Sjmallett * 363232812Sjmallett * @param port_num Port number (ipd_port) to get statistics for. 364210284Sjmallett * @param clear Set to 1 to clear the counters after they are read 365210284Sjmallett * @param status Where to put the results. 366210284Sjmallett */ 367210284Sjmallettstatic inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear, cvmx_pip_port_status_t *status) 368210284Sjmallett{ 369210284Sjmallett cvmx_pip_stat_ctl_t pip_stat_ctl; 370210284Sjmallett cvmx_pip_stat0_prtx_t stat0; 371210284Sjmallett cvmx_pip_stat1_prtx_t stat1; 372210284Sjmallett cvmx_pip_stat2_prtx_t stat2; 373210284Sjmallett cvmx_pip_stat3_prtx_t stat3; 374210284Sjmallett cvmx_pip_stat4_prtx_t stat4; 375210284Sjmallett cvmx_pip_stat5_prtx_t stat5; 376210284Sjmallett cvmx_pip_stat6_prtx_t stat6; 377210284Sjmallett cvmx_pip_stat7_prtx_t stat7; 378210284Sjmallett cvmx_pip_stat8_prtx_t stat8; 379210284Sjmallett cvmx_pip_stat9_prtx_t stat9; 380232812Sjmallett cvmx_pip_stat10_x_t stat10; 381232812Sjmallett cvmx_pip_stat11_x_t stat11; 382210284Sjmallett cvmx_pip_stat_inb_pktsx_t pip_stat_inb_pktsx; 383210284Sjmallett cvmx_pip_stat_inb_octsx_t pip_stat_inb_octsx; 384210284Sjmallett cvmx_pip_stat_inb_errsx_t pip_stat_inb_errsx; 385232812Sjmallett int interface = cvmx_helper_get_interface_num(port_num); 386232812Sjmallett int index = cvmx_helper_get_interface_index_num(port_num); 387210284Sjmallett 388210284Sjmallett pip_stat_ctl.u64 = 0; 389210284Sjmallett pip_stat_ctl.s.rdclr = clear; 390210284Sjmallett cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64); 391210284Sjmallett 392232812Sjmallett if (octeon_has_feature(OCTEON_FEATURE_PKND)) 393215990Sjmallett { 394232812Sjmallett int pknd = cvmx_helper_get_pknd(interface, index); 395232812Sjmallett /* 396232812Sjmallett * PIP_STAT_CTL[MODE] 0 means pkind. 397232812Sjmallett */ 398232812Sjmallett stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_X(pknd)); 399232812Sjmallett stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_X(pknd)); 400232812Sjmallett stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_X(pknd)); 401232812Sjmallett stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_X(pknd)); 402232812Sjmallett stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_X(pknd)); 403232812Sjmallett stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_X(pknd)); 404232812Sjmallett stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_X(pknd)); 405232812Sjmallett stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_X(pknd)); 406232812Sjmallett stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_X(pknd)); 407232812Sjmallett stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_X(pknd)); 408232812Sjmallett stat10.u64 = cvmx_read_csr(CVMX_PIP_STAT10_X(pknd)); 409232812Sjmallett stat11.u64 = cvmx_read_csr(CVMX_PIP_STAT11_X(pknd)); 410215990Sjmallett } 411232812Sjmallett else 412232812Sjmallett { 413232812Sjmallett if (port_num >= 40) 414232812Sjmallett { 415232812Sjmallett stat0.u64 = cvmx_read_csr(CVMX_PIP_XSTAT0_PRTX(port_num)); 416232812Sjmallett stat1.u64 = cvmx_read_csr(CVMX_PIP_XSTAT1_PRTX(port_num)); 417232812Sjmallett stat2.u64 = cvmx_read_csr(CVMX_PIP_XSTAT2_PRTX(port_num)); 418232812Sjmallett stat3.u64 = cvmx_read_csr(CVMX_PIP_XSTAT3_PRTX(port_num)); 419232812Sjmallett stat4.u64 = cvmx_read_csr(CVMX_PIP_XSTAT4_PRTX(port_num)); 420232812Sjmallett stat5.u64 = cvmx_read_csr(CVMX_PIP_XSTAT5_PRTX(port_num)); 421232812Sjmallett stat6.u64 = cvmx_read_csr(CVMX_PIP_XSTAT6_PRTX(port_num)); 422232812Sjmallett stat7.u64 = cvmx_read_csr(CVMX_PIP_XSTAT7_PRTX(port_num)); 423232812Sjmallett stat8.u64 = cvmx_read_csr(CVMX_PIP_XSTAT8_PRTX(port_num)); 424232812Sjmallett stat9.u64 = cvmx_read_csr(CVMX_PIP_XSTAT9_PRTX(port_num)); 425232812Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) 426232812Sjmallett { 427232812Sjmallett stat10.u64 = cvmx_read_csr(CVMX_PIP_XSTAT10_PRTX(port_num)); 428232812Sjmallett stat11.u64 = cvmx_read_csr(CVMX_PIP_XSTAT11_PRTX(port_num)); 429232812Sjmallett } 430232812Sjmallett } 431232812Sjmallett else 432232812Sjmallett { 433232812Sjmallett stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num)); 434232812Sjmallett stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num)); 435232812Sjmallett stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num)); 436232812Sjmallett stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num)); 437232812Sjmallett stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num)); 438232812Sjmallett stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num)); 439232812Sjmallett stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num)); 440232812Sjmallett stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num)); 441232812Sjmallett stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num)); 442232812Sjmallett stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num)); 443232812Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN52XX) 444232812Sjmallett || OCTEON_IS_MODEL(OCTEON_CN56XX) 445232812Sjmallett || OCTEON_IS_MODEL(OCTEON_CN6XXX) 446232812Sjmallett || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) 447232812Sjmallett { 448232812Sjmallett stat10.u64 = cvmx_read_csr(CVMX_PIP_STAT10_PRTX(port_num)); 449232812Sjmallett stat11.u64 = cvmx_read_csr(CVMX_PIP_STAT11_PRTX(port_num)); 450232812Sjmallett } 451232812Sjmallett } 452232812Sjmallett } 453232812Sjmallett if (octeon_has_feature(OCTEON_FEATURE_PKND)) 454232812Sjmallett { 455232812Sjmallett int pknd = cvmx_helper_get_pknd(interface, index); 456232812Sjmallett 457232812Sjmallett pip_stat_inb_pktsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_PKTS_PKNDX(pknd)); 458232812Sjmallett pip_stat_inb_octsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_OCTS_PKNDX(pknd)); 459232812Sjmallett pip_stat_inb_errsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_ERRS_PKNDX(pknd)); 460232812Sjmallett } 461215990Sjmallett else 462215990Sjmallett { 463232812Sjmallett pip_stat_inb_pktsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num)); 464232812Sjmallett pip_stat_inb_octsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num)); 465232812Sjmallett pip_stat_inb_errsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num)); 466215990Sjmallett } 467210284Sjmallett 468210284Sjmallett status->dropped_octets = stat0.s.drp_octs; 469210284Sjmallett status->dropped_packets = stat0.s.drp_pkts; 470210284Sjmallett status->octets = stat1.s.octs; 471210284Sjmallett status->pci_raw_packets = stat2.s.raw; 472210284Sjmallett status->packets = stat2.s.pkts; 473210284Sjmallett status->multicast_packets = stat3.s.mcst; 474210284Sjmallett status->broadcast_packets = stat3.s.bcst; 475210284Sjmallett status->len_64_packets = stat4.s.h64; 476210284Sjmallett status->len_65_127_packets = stat4.s.h65to127; 477210284Sjmallett status->len_128_255_packets = stat5.s.h128to255; 478210284Sjmallett status->len_256_511_packets = stat5.s.h256to511; 479210284Sjmallett status->len_512_1023_packets = stat6.s.h512to1023; 480210284Sjmallett status->len_1024_1518_packets = stat6.s.h1024to1518; 481210284Sjmallett status->len_1519_max_packets = stat7.s.h1519; 482210284Sjmallett status->fcs_align_err_packets = stat7.s.fcs; 483210284Sjmallett status->runt_packets = stat8.s.undersz; 484210284Sjmallett status->runt_crc_packets = stat8.s.frag; 485210284Sjmallett status->oversize_packets = stat9.s.oversz; 486210284Sjmallett status->oversize_crc_packets = stat9.s.jabber; 487232812Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN52XX) 488232812Sjmallett || OCTEON_IS_MODEL(OCTEON_CN56XX) 489232812Sjmallett || OCTEON_IS_MODEL(OCTEON_CN6XXX) 490232812Sjmallett || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) 491232812Sjmallett { 492232812Sjmallett status->mcast_l2_red_packets = stat10.s.mcast; 493232812Sjmallett status->bcast_l2_red_packets = stat10.s.bcast; 494232812Sjmallett status->mcast_l3_red_packets = stat11.s.mcast; 495232812Sjmallett status->bcast_l3_red_packets = stat11.s.bcast; 496232812Sjmallett } 497210284Sjmallett status->inb_packets = pip_stat_inb_pktsx.s.pkts; 498210284Sjmallett status->inb_octets = pip_stat_inb_octsx.s.octs; 499210284Sjmallett status->inb_errors = pip_stat_inb_errsx.s.errs; 500210284Sjmallett} 501210284Sjmallett 502210284Sjmallett 503210284Sjmallett/** 504210284Sjmallett * Configure the hardware CRC engine 505210284Sjmallett * 506210284Sjmallett * @param interface Interface to configure (0 or 1) 507210284Sjmallett * @param invert_result 508210284Sjmallett * Invert the result of the CRC 509210284Sjmallett * @param reflect Reflect 510210284Sjmallett * @param initialization_vector 511210284Sjmallett * CRC initialization vector 512210284Sjmallett */ 513210284Sjmallettstatic inline void cvmx_pip_config_crc(uint64_t interface, uint64_t invert_result, uint64_t reflect, uint32_t initialization_vector) 514210284Sjmallett{ 515210284Sjmallett if ((OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 516210284Sjmallett { 517210284Sjmallett cvmx_pip_crc_ctlx_t config; 518210284Sjmallett cvmx_pip_crc_ivx_t pip_crc_ivx; 519210284Sjmallett 520210284Sjmallett config.u64 = 0; 521210284Sjmallett config.s.invres = invert_result; 522210284Sjmallett config.s.reflect = reflect; 523210284Sjmallett cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64); 524210284Sjmallett 525210284Sjmallett pip_crc_ivx.u64 = 0; 526210284Sjmallett pip_crc_ivx.s.iv = initialization_vector; 527210284Sjmallett cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64); 528210284Sjmallett } 529210284Sjmallett} 530210284Sjmallett 531210284Sjmallett 532210284Sjmallett/** 533210284Sjmallett * Clear all bits in a tag mask. This should be called on 534210284Sjmallett * startup before any calls to cvmx_pip_tag_mask_set. Each bit 535210284Sjmallett * set in the final mask represent a byte used in the packet for 536210284Sjmallett * tag generation. 537210284Sjmallett * 538210284Sjmallett * @param mask_index Which tag mask to clear (0..3) 539210284Sjmallett */ 540210284Sjmallettstatic inline void cvmx_pip_tag_mask_clear(uint64_t mask_index) 541210284Sjmallett{ 542210284Sjmallett uint64_t index; 543210284Sjmallett cvmx_pip_tag_incx_t pip_tag_incx; 544210284Sjmallett pip_tag_incx.u64 = 0; 545210284Sjmallett pip_tag_incx.s.en = 0; 546210284Sjmallett for (index=mask_index*16; index<(mask_index+1)*16; index++) 547210284Sjmallett cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); 548210284Sjmallett} 549210284Sjmallett 550210284Sjmallett 551210284Sjmallett/** 552210284Sjmallett * Sets a range of bits in the tag mask. The tag mask is used 553210284Sjmallett * when the cvmx_pip_port_tag_cfg_t tag_mode is non zero. 554210284Sjmallett * There are four separate masks that can be configured. 555210284Sjmallett * 556210284Sjmallett * @param mask_index Which tag mask to modify (0..3) 557210284Sjmallett * @param offset Offset into the bitmask to set bits at. Use the GCC macro 558210284Sjmallett * offsetof() to determine the offsets into packet headers. 559210284Sjmallett * For example, offsetof(ethhdr, protocol) returns the offset 560210284Sjmallett * of the ethernet protocol field. The bitmask selects which bytes 561210284Sjmallett * to include the the tag, with bit offset X selecting byte at offset X 562210284Sjmallett * from the beginning of the packet data. 563210284Sjmallett * @param len Number of bytes to include. Usually this is the sizeof() 564210284Sjmallett * the field. 565210284Sjmallett */ 566210284Sjmallettstatic inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset, uint64_t len) 567210284Sjmallett{ 568210284Sjmallett while (len--) 569210284Sjmallett { 570210284Sjmallett cvmx_pip_tag_incx_t pip_tag_incx; 571210284Sjmallett uint64_t index = mask_index*16 + offset/8; 572210284Sjmallett pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index)); 573210284Sjmallett pip_tag_incx.s.en |= 0x80 >> (offset & 0x7); 574210284Sjmallett cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); 575210284Sjmallett offset++; 576210284Sjmallett } 577210284Sjmallett} 578210284Sjmallett 579232812Sjmallett/** 580232812Sjmallett * Initialize Bit Select Extractor config. Their are 8 bit positions and valids 581232812Sjmallett * to be used when using the corresponding extractor. 582232812Sjmallett * 583232812Sjmallett * @param bit Bit Select Extractor to use 584232812Sjmallett * @param pos Which position to update 585232812Sjmallett * @param val The value to update the position with 586232812Sjmallett */ 587232812Sjmallettstatic inline void cvmx_pip_set_bsel_pos(int bit, int pos, int val) 588232812Sjmallett{ 589232812Sjmallett cvmx_pip_bsel_ext_posx_t bsel_pos; 590232812Sjmallett 591232812Sjmallett /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */ 592232812Sjmallett if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR)) 593232812Sjmallett return; 594232812Sjmallett 595232812Sjmallett if (bit < 0 || bit > 3) 596232812Sjmallett { 597232812Sjmallett cvmx_dprintf("ERROR: cvmx_pip_set_bsel_pos: Invalid Bit-Select Extractor (%d) passed\n", bit); 598232812Sjmallett return; 599232812Sjmallett } 600232812Sjmallett 601232812Sjmallett bsel_pos.u64 = cvmx_read_csr(CVMX_PIP_BSEL_EXT_POSX(bit)); 602232812Sjmallett switch(pos) 603232812Sjmallett { 604232812Sjmallett case 0: 605232812Sjmallett bsel_pos.s.pos0_val = 1; 606232812Sjmallett bsel_pos.s.pos0 = val & 0x7f; 607232812Sjmallett break; 608232812Sjmallett case 1: 609232812Sjmallett bsel_pos.s.pos1_val = 1; 610232812Sjmallett bsel_pos.s.pos1 = val & 0x7f; 611232812Sjmallett break; 612232812Sjmallett case 2: 613232812Sjmallett bsel_pos.s.pos2_val = 1; 614232812Sjmallett bsel_pos.s.pos2 = val & 0x7f; 615232812Sjmallett break; 616232812Sjmallett case 3: 617232812Sjmallett bsel_pos.s.pos3_val = 1; 618232812Sjmallett bsel_pos.s.pos3 = val & 0x7f; 619232812Sjmallett break; 620232812Sjmallett case 4: 621232812Sjmallett bsel_pos.s.pos4_val = 1; 622232812Sjmallett bsel_pos.s.pos4 = val & 0x7f; 623232812Sjmallett break; 624232812Sjmallett case 5: 625232812Sjmallett bsel_pos.s.pos5_val = 1; 626232812Sjmallett bsel_pos.s.pos5 = val & 0x7f; 627232812Sjmallett break; 628232812Sjmallett case 6: 629232812Sjmallett bsel_pos.s.pos6_val = 1; 630232812Sjmallett bsel_pos.s.pos6 = val & 0x7f; 631232812Sjmallett break; 632232812Sjmallett case 7: 633232812Sjmallett bsel_pos.s.pos7_val = 1; 634232812Sjmallett bsel_pos.s.pos7 = val & 0x7f; 635232812Sjmallett break; 636232812Sjmallett default: 637232812Sjmallett cvmx_dprintf("Warning: cvmx_pip_set_bsel_pos: Invalid pos(%d)\n", pos); 638232812Sjmallett break; 639232812Sjmallett } 640232812Sjmallett cvmx_write_csr(CVMX_PIP_BSEL_EXT_POSX(bit), bsel_pos.u64); 641232812Sjmallett} 642232812Sjmallett 643232812Sjmallett/** 644232812Sjmallett * Initialize offset and skip values to use by bit select extractor. 645232812Sjmallett 646232812Sjmallett * @param bit Bit Select Extractor to use 647232812Sjmallett * @param offset Offset to add to extractor mem addr to get final address 648232812Sjmallett to lookup table. 649232812Sjmallett * @param skip Number of bytes to skip from start of packet 0-64 650232812Sjmallett */ 651232812Sjmallettstatic inline void cvmx_pip_bsel_config(int bit, int offset, int skip) 652232812Sjmallett{ 653232812Sjmallett cvmx_pip_bsel_ext_cfgx_t bsel_cfg; 654232812Sjmallett 655232812Sjmallett /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */ 656232812Sjmallett if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR)) 657232812Sjmallett return; 658232812Sjmallett 659232812Sjmallett bsel_cfg.u64 = cvmx_read_csr(CVMX_PIP_BSEL_EXT_CFGX(bit)); 660232812Sjmallett bsel_cfg.s.offset = offset; 661232812Sjmallett bsel_cfg.s.skip = skip; 662232812Sjmallett cvmx_write_csr(CVMX_PIP_BSEL_EXT_CFGX(bit), bsel_cfg.u64); 663232812Sjmallett} 664232812Sjmallett 665232812Sjmallett 666232812Sjmallett/** 667232812Sjmallett * Get the entry for the Bit Select Extractor Table. 668232812Sjmallett * @param work pointer to work queue entry 669232812Sjmallett * @return Index of the Bit Select Extractor Table 670232812Sjmallett */ 671232812Sjmallettstatic inline int cvmx_pip_get_bsel_table_index(cvmx_wqe_t *work) 672232812Sjmallett{ 673232812Sjmallett int bit = cvmx_wqe_get_port(work) & 0x3; 674232812Sjmallett /* Get the Bit select table index. */ 675232812Sjmallett int index; 676232812Sjmallett int y; 677232812Sjmallett cvmx_pip_bsel_ext_cfgx_t bsel_cfg; 678232812Sjmallett cvmx_pip_bsel_ext_posx_t bsel_pos; 679232812Sjmallett 680232812Sjmallett /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */ 681232812Sjmallett if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR)) 682232812Sjmallett return -1; 683232812Sjmallett 684232812Sjmallett bsel_cfg.u64 = cvmx_read_csr(CVMX_PIP_BSEL_EXT_CFGX(bit)); 685232812Sjmallett bsel_pos.u64 = cvmx_read_csr(CVMX_PIP_BSEL_EXT_POSX(bit)); 686232812Sjmallett 687232812Sjmallett for (y = 0; y < 8; y++) 688232812Sjmallett { 689232812Sjmallett char *ptr = (char *)cvmx_phys_to_ptr(work->packet_ptr.s.addr); 690232812Sjmallett int bit_loc = 0; 691232812Sjmallett int bit; 692232812Sjmallett 693232812Sjmallett ptr += bsel_cfg.s.skip; 694232812Sjmallett switch(y) 695232812Sjmallett { 696232812Sjmallett case 0: 697232812Sjmallett ptr += (bsel_pos.s.pos0 >> 3); 698232812Sjmallett bit_loc = 7 - (bsel_pos.s.pos0 & 0x3); 699232812Sjmallett break; 700232812Sjmallett case 1: 701232812Sjmallett ptr += (bsel_pos.s.pos1 >> 3); 702232812Sjmallett bit_loc = 7 - (bsel_pos.s.pos1 & 0x3); 703232812Sjmallett break; 704232812Sjmallett case 2: 705232812Sjmallett ptr += (bsel_pos.s.pos2 >> 3); 706232812Sjmallett bit_loc = 7 - (bsel_pos.s.pos2 & 0x3); 707232812Sjmallett break; 708232812Sjmallett case 3: 709232812Sjmallett ptr += (bsel_pos.s.pos3 >> 3); 710232812Sjmallett bit_loc = 7 - (bsel_pos.s.pos3 & 0x3); 711232812Sjmallett break; 712232812Sjmallett case 4: 713232812Sjmallett ptr += (bsel_pos.s.pos4 >> 3); 714232812Sjmallett bit_loc = 7 - (bsel_pos.s.pos4 & 0x3); 715232812Sjmallett break; 716232812Sjmallett case 5: 717232812Sjmallett ptr += (bsel_pos.s.pos5 >> 3); 718232812Sjmallett bit_loc = 7 - (bsel_pos.s.pos5 & 0x3); 719232812Sjmallett break; 720232812Sjmallett case 6: 721232812Sjmallett ptr += (bsel_pos.s.pos6 >> 3); 722232812Sjmallett bit_loc = 7 - (bsel_pos.s.pos6 & 0x3); 723232812Sjmallett break; 724232812Sjmallett case 7: 725232812Sjmallett ptr += (bsel_pos.s.pos7 >> 3); 726232812Sjmallett bit_loc = 7 - (bsel_pos.s.pos7 & 0x3); 727232812Sjmallett break; 728232812Sjmallett } 729232812Sjmallett bit = (*ptr >> bit_loc) & 1; 730232812Sjmallett index |= bit << y; 731232812Sjmallett } 732232812Sjmallett index += bsel_cfg.s.offset; 733232812Sjmallett index &= 0x1ff; 734232812Sjmallett return index; 735232812Sjmallett} 736232812Sjmallett 737232812Sjmallettstatic inline int cvmx_pip_get_bsel_qos(cvmx_wqe_t *work) 738232812Sjmallett{ 739232812Sjmallett int index = cvmx_pip_get_bsel_table_index(work); 740232812Sjmallett cvmx_pip_bsel_tbl_entx_t bsel_tbl; 741232812Sjmallett 742232812Sjmallett /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */ 743232812Sjmallett if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR)) 744232812Sjmallett return -1; 745232812Sjmallett 746232812Sjmallett bsel_tbl.u64 = cvmx_read_csr(CVMX_PIP_BSEL_TBL_ENTX(index)); 747232812Sjmallett 748232812Sjmallett return bsel_tbl.s.qos; 749232812Sjmallett} 750232812Sjmallett 751232812Sjmallettstatic inline int cvmx_pip_get_bsel_grp(cvmx_wqe_t *work) 752232812Sjmallett{ 753232812Sjmallett int index = cvmx_pip_get_bsel_table_index(work); 754232812Sjmallett cvmx_pip_bsel_tbl_entx_t bsel_tbl; 755232812Sjmallett 756232812Sjmallett /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */ 757232812Sjmallett if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR)) 758232812Sjmallett return -1; 759232812Sjmallett 760232812Sjmallett bsel_tbl.u64 = cvmx_read_csr(CVMX_PIP_BSEL_TBL_ENTX(index)); 761232812Sjmallett 762232812Sjmallett return bsel_tbl.s.grp; 763232812Sjmallett} 764232812Sjmallett 765232812Sjmallettstatic inline int cvmx_pip_get_bsel_tt(cvmx_wqe_t *work) 766232812Sjmallett{ 767232812Sjmallett int index = cvmx_pip_get_bsel_table_index(work); 768232812Sjmallett cvmx_pip_bsel_tbl_entx_t bsel_tbl; 769232812Sjmallett 770232812Sjmallett /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */ 771232812Sjmallett if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR)) 772232812Sjmallett return -1; 773232812Sjmallett 774232812Sjmallett bsel_tbl.u64 = cvmx_read_csr(CVMX_PIP_BSEL_TBL_ENTX(index)); 775232812Sjmallett 776232812Sjmallett return bsel_tbl.s.tt; 777232812Sjmallett} 778232812Sjmallett 779232812Sjmallettstatic inline int cvmx_pip_get_bsel_tag(cvmx_wqe_t *work) 780232812Sjmallett{ 781232812Sjmallett int index = cvmx_pip_get_bsel_table_index(work); 782232812Sjmallett int port = cvmx_wqe_get_port(work); 783232812Sjmallett int bit = port & 0x3; 784232812Sjmallett int upper_tag = 0; 785232812Sjmallett cvmx_pip_bsel_tbl_entx_t bsel_tbl; 786232812Sjmallett cvmx_pip_bsel_ext_cfgx_t bsel_cfg; 787232812Sjmallett cvmx_pip_prt_tagx_t prt_tag; 788232812Sjmallett 789232812Sjmallett /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */ 790232812Sjmallett if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR)) 791232812Sjmallett return -1; 792232812Sjmallett 793232812Sjmallett bsel_tbl.u64 = cvmx_read_csr(CVMX_PIP_BSEL_TBL_ENTX(index)); 794232812Sjmallett bsel_cfg.u64 = cvmx_read_csr(CVMX_PIP_BSEL_EXT_CFGX(bit)); 795232812Sjmallett 796232812Sjmallett prt_tag.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(port)); 797232812Sjmallett if (prt_tag.s.inc_prt_flag == 0) 798232812Sjmallett upper_tag = bsel_cfg.s.upper_tag; 799232812Sjmallett return (bsel_tbl.s.tag | ((bsel_cfg.s.tag << 8) & 0xff00) | ((upper_tag << 16) & 0xffff0000)); 800232812Sjmallett} 801232812Sjmallett 802210284Sjmallett#ifdef __cplusplus 803210284Sjmallett} 804210284Sjmallett#endif 805210284Sjmallett 806210284Sjmallett#endif /* __CVMX_PIP_H__ */ 807