cvmx-pcsxx-defs.h revision 215990
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-pcsxx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon pcsxx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_PCSXX_TYPEDEFS_H__ 53#define __CVMX_PCSXX_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 60 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 61 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 62 cvmx_warn("CVMX_PCSXX_10GBX_STATUS_REG(%lu) is invalid on this chip\n", block_id); 63 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 1) * 0x8000000ull; 64} 65#else 66#define CVMX_PCSXX_10GBX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 1) * 0x8000000ull) 67#endif 68#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id) 70{ 71 if (!( 72 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 73 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 74 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 75 cvmx_warn("CVMX_PCSXX_BIST_STATUS_REG(%lu) is invalid on this chip\n", block_id); 76 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 1) * 0x8000000ull; 77} 78#else 79#define CVMX_PCSXX_BIST_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 1) * 0x8000000ull) 80#endif 81#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id) 83{ 84 if (!( 85 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 86 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 87 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 88 cvmx_warn("CVMX_PCSXX_BIT_LOCK_STATUS_REG(%lu) is invalid on this chip\n", block_id); 89 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 1) * 0x8000000ull; 90} 91#else 92#define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 1) * 0x8000000ull) 93#endif 94#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 95static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id) 96{ 97 if (!( 98 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 99 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 100 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 101 cvmx_warn("CVMX_PCSXX_CONTROL1_REG(%lu) is invalid on this chip\n", block_id); 102 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 1) * 0x8000000ull; 103} 104#else 105#define CVMX_PCSXX_CONTROL1_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 1) * 0x8000000ull) 106#endif 107#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 108static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id) 109{ 110 if (!( 111 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 112 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 113 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 114 cvmx_warn("CVMX_PCSXX_CONTROL2_REG(%lu) is invalid on this chip\n", block_id); 115 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 1) * 0x8000000ull; 116} 117#else 118#define CVMX_PCSXX_CONTROL2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 1) * 0x8000000ull) 119#endif 120#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 121static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id) 122{ 123 if (!( 124 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 125 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 126 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 127 cvmx_warn("CVMX_PCSXX_INT_EN_REG(%lu) is invalid on this chip\n", block_id); 128 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 1) * 0x8000000ull; 129} 130#else 131#define CVMX_PCSXX_INT_EN_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 1) * 0x8000000ull) 132#endif 133#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 134static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id) 135{ 136 if (!( 137 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 138 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 139 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 140 cvmx_warn("CVMX_PCSXX_INT_REG(%lu) is invalid on this chip\n", block_id); 141 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 1) * 0x8000000ull; 142} 143#else 144#define CVMX_PCSXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 1) * 0x8000000ull) 145#endif 146#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 147static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id) 148{ 149 if (!( 150 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 151 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 152 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 153 cvmx_warn("CVMX_PCSXX_LOG_ANL_REG(%lu) is invalid on this chip\n", block_id); 154 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 1) * 0x8000000ull; 155} 156#else 157#define CVMX_PCSXX_LOG_ANL_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 1) * 0x8000000ull) 158#endif 159#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 160static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id) 161{ 162 if (!( 163 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 164 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 165 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 166 cvmx_warn("CVMX_PCSXX_MISC_CTL_REG(%lu) is invalid on this chip\n", block_id); 167 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 1) * 0x8000000ull; 168} 169#else 170#define CVMX_PCSXX_MISC_CTL_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 1) * 0x8000000ull) 171#endif 172#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 173static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id) 174{ 175 if (!( 176 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 177 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 178 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 179 cvmx_warn("CVMX_PCSXX_RX_SYNC_STATES_REG(%lu) is invalid on this chip\n", block_id); 180 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 1) * 0x8000000ull; 181} 182#else 183#define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 1) * 0x8000000ull) 184#endif 185#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 186static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id) 187{ 188 if (!( 189 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 190 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 191 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 192 cvmx_warn("CVMX_PCSXX_SPD_ABIL_REG(%lu) is invalid on this chip\n", block_id); 193 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 1) * 0x8000000ull; 194} 195#else 196#define CVMX_PCSXX_SPD_ABIL_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 1) * 0x8000000ull) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id) 200{ 201 if (!( 202 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 203 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 204 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 205 cvmx_warn("CVMX_PCSXX_STATUS1_REG(%lu) is invalid on this chip\n", block_id); 206 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 1) * 0x8000000ull; 207} 208#else 209#define CVMX_PCSXX_STATUS1_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 1) * 0x8000000ull) 210#endif 211#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id) 213{ 214 if (!( 215 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 216 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 217 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 218 cvmx_warn("CVMX_PCSXX_STATUS2_REG(%lu) is invalid on this chip\n", block_id); 219 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 1) * 0x8000000ull; 220} 221#else 222#define CVMX_PCSXX_STATUS2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 1) * 0x8000000ull) 223#endif 224#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 225static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id) 226{ 227 if (!( 228 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 229 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 230 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 231 cvmx_warn("CVMX_PCSXX_TX_RX_POLARITY_REG(%lu) is invalid on this chip\n", block_id); 232 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 1) * 0x8000000ull; 233} 234#else 235#define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 1) * 0x8000000ull) 236#endif 237#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 238static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id) 239{ 240 if (!( 241 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 242 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 243 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))))) 244 cvmx_warn("CVMX_PCSXX_TX_RX_STATES_REG(%lu) is invalid on this chip\n", block_id); 245 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 1) * 0x8000000ull; 246} 247#else 248#define CVMX_PCSXX_TX_RX_STATES_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 1) * 0x8000000ull) 249#endif 250 251/** 252 * cvmx_pcsx#_10gbx_status_reg 253 * 254 * PCSX_10GBX_STATUS_REG = 10gbx_status_reg 255 * 256 */ 257union cvmx_pcsxx_10gbx_status_reg 258{ 259 uint64_t u64; 260 struct cvmx_pcsxx_10gbx_status_reg_s 261 { 262#if __BYTE_ORDER == __BIG_ENDIAN 263 uint64_t reserved_13_63 : 51; 264 uint64_t alignd : 1; /**< 1=Lane alignment achieved, 0=Lanes not aligned */ 265 uint64_t pattst : 1; /**< Always at 0, no pattern testing capability */ 266 uint64_t reserved_4_10 : 7; 267 uint64_t l3sync : 1; /**< 1=Rcv lane 3 code grp synchronized, 0=not sync'ed */ 268 uint64_t l2sync : 1; /**< 1=Rcv lane 2 code grp synchronized, 0=not sync'ed */ 269 uint64_t l1sync : 1; /**< 1=Rcv lane 1 code grp synchronized, 0=not sync'ed */ 270 uint64_t l0sync : 1; /**< 1=Rcv lane 0 code grp synchronized, 0=not sync'ed */ 271#else 272 uint64_t l0sync : 1; 273 uint64_t l1sync : 1; 274 uint64_t l2sync : 1; 275 uint64_t l3sync : 1; 276 uint64_t reserved_4_10 : 7; 277 uint64_t pattst : 1; 278 uint64_t alignd : 1; 279 uint64_t reserved_13_63 : 51; 280#endif 281 } s; 282 struct cvmx_pcsxx_10gbx_status_reg_s cn52xx; 283 struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1; 284 struct cvmx_pcsxx_10gbx_status_reg_s cn56xx; 285 struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1; 286 struct cvmx_pcsxx_10gbx_status_reg_s cn63xx; 287 struct cvmx_pcsxx_10gbx_status_reg_s cn63xxp1; 288}; 289typedef union cvmx_pcsxx_10gbx_status_reg cvmx_pcsxx_10gbx_status_reg_t; 290 291/** 292 * cvmx_pcsx#_bist_status_reg 293 * 294 * NOTE: Logic Analyzer is enabled with LA_EN for xaui only. PKT_SZ is effective only when LA_EN=1 295 * For normal operation(xaui), this bit must be 0. The dropped lane is used to send rxc[3:0]. 296 * See pcs.csr for sgmii/1000Base-X logic analyzer mode. 297 * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt 298 * 299 * 300 * PCSX Bist Status Register 301 */ 302union cvmx_pcsxx_bist_status_reg 303{ 304 uint64_t u64; 305 struct cvmx_pcsxx_bist_status_reg_s 306 { 307#if __BYTE_ORDER == __BIG_ENDIAN 308 uint64_t reserved_1_63 : 63; 309 uint64_t bist_status : 1; /**< 1=bist failure, 0=bisted memory ok or bist in progress 310 pcsx.tx_sm.drf8x36m1_async_bist */ 311#else 312 uint64_t bist_status : 1; 313 uint64_t reserved_1_63 : 63; 314#endif 315 } s; 316 struct cvmx_pcsxx_bist_status_reg_s cn52xx; 317 struct cvmx_pcsxx_bist_status_reg_s cn52xxp1; 318 struct cvmx_pcsxx_bist_status_reg_s cn56xx; 319 struct cvmx_pcsxx_bist_status_reg_s cn56xxp1; 320 struct cvmx_pcsxx_bist_status_reg_s cn63xx; 321 struct cvmx_pcsxx_bist_status_reg_s cn63xxp1; 322}; 323typedef union cvmx_pcsxx_bist_status_reg cvmx_pcsxx_bist_status_reg_t; 324 325/** 326 * cvmx_pcsx#_bit_lock_status_reg 327 * 328 * LN_SWAP for XAUI is to simplify interconnection layout between devices 329 * 330 * 331 * PCSX Bit Lock Status Register 332 */ 333union cvmx_pcsxx_bit_lock_status_reg 334{ 335 uint64_t u64; 336 struct cvmx_pcsxx_bit_lock_status_reg_s 337 { 338#if __BYTE_ORDER == __BIG_ENDIAN 339 uint64_t reserved_4_63 : 60; 340 uint64_t bitlck3 : 1; /**< Receive Lane 3 bit lock status */ 341 uint64_t bitlck2 : 1; /**< Receive Lane 2 bit lock status */ 342 uint64_t bitlck1 : 1; /**< Receive Lane 1 bit lock status */ 343 uint64_t bitlck0 : 1; /**< Receive Lane 0 bit lock status */ 344#else 345 uint64_t bitlck0 : 1; 346 uint64_t bitlck1 : 1; 347 uint64_t bitlck2 : 1; 348 uint64_t bitlck3 : 1; 349 uint64_t reserved_4_63 : 60; 350#endif 351 } s; 352 struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx; 353 struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1; 354 struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx; 355 struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1; 356 struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx; 357 struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1; 358}; 359typedef union cvmx_pcsxx_bit_lock_status_reg cvmx_pcsxx_bit_lock_status_reg_t; 360 361/** 362 * cvmx_pcsx#_control1_reg 363 * 364 * NOTE: Logic Analyzer is enabled with LA_EN for the specified PCS lane only. PKT_SZ is effective only when LA_EN=1 365 * For normal operation(sgmii or 1000Base-X), this bit must be 0. 366 * See pcsx.csr for xaui logic analyzer mode. 367 * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt 368 * 369 * 370 * PCSX regs follow IEEE Std 802.3-2005, Section: 45.2.3 371 * 372 * 373 * PCSX_CONTROL1_REG = Control Register1 374 */ 375union cvmx_pcsxx_control1_reg 376{ 377 uint64_t u64; 378 struct cvmx_pcsxx_control1_reg_s 379 { 380#if __BYTE_ORDER == __BIG_ENDIAN 381 uint64_t reserved_16_63 : 48; 382 uint64_t reset : 1; /**< 1=SW PCSX Reset, the bit will return to 0 after pcs 383 has been reset. Takes 32 eclk cycles to reset pcs 384 0=Normal operation */ 385 uint64_t loopbck1 : 1; /**< 0=normal operation, 1=internal loopback mode 386 xgmii tx data received from gmx tx port is returned 387 back into gmx, xgmii rx port. */ 388 uint64_t spdsel1 : 1; /**< See bit 6 description */ 389 uint64_t reserved_12_12 : 1; 390 uint64_t lo_pwr : 1; /**< 1=Power Down(HW reset), 0=Normal operation */ 391 uint64_t reserved_7_10 : 4; 392 uint64_t spdsel0 : 1; /**< SPDSEL1 and SPDSEL0 are always at 1'b1. Write has 393 no effect. 394 [<6>, <13>]Link Speed selection 395 1 1 Bits 5:2 select speed */ 396 uint64_t spd : 4; /**< Always select 10Gb/s, writes have no effect */ 397 uint64_t reserved_0_1 : 2; 398#else 399 uint64_t reserved_0_1 : 2; 400 uint64_t spd : 4; 401 uint64_t spdsel0 : 1; 402 uint64_t reserved_7_10 : 4; 403 uint64_t lo_pwr : 1; 404 uint64_t reserved_12_12 : 1; 405 uint64_t spdsel1 : 1; 406 uint64_t loopbck1 : 1; 407 uint64_t reset : 1; 408 uint64_t reserved_16_63 : 48; 409#endif 410 } s; 411 struct cvmx_pcsxx_control1_reg_s cn52xx; 412 struct cvmx_pcsxx_control1_reg_s cn52xxp1; 413 struct cvmx_pcsxx_control1_reg_s cn56xx; 414 struct cvmx_pcsxx_control1_reg_s cn56xxp1; 415 struct cvmx_pcsxx_control1_reg_s cn63xx; 416 struct cvmx_pcsxx_control1_reg_s cn63xxp1; 417}; 418typedef union cvmx_pcsxx_control1_reg cvmx_pcsxx_control1_reg_t; 419 420/** 421 * cvmx_pcsx#_control2_reg 422 * 423 * PCSX_CONTROL2_REG = Control Register2 424 * 425 */ 426union cvmx_pcsxx_control2_reg 427{ 428 uint64_t u64; 429 struct cvmx_pcsxx_control2_reg_s 430 { 431#if __BYTE_ORDER == __BIG_ENDIAN 432 uint64_t reserved_2_63 : 62; 433 uint64_t type : 2; /**< Always 2'b01, 10GBASE-X only supported */ 434#else 435 uint64_t type : 2; 436 uint64_t reserved_2_63 : 62; 437#endif 438 } s; 439 struct cvmx_pcsxx_control2_reg_s cn52xx; 440 struct cvmx_pcsxx_control2_reg_s cn52xxp1; 441 struct cvmx_pcsxx_control2_reg_s cn56xx; 442 struct cvmx_pcsxx_control2_reg_s cn56xxp1; 443 struct cvmx_pcsxx_control2_reg_s cn63xx; 444 struct cvmx_pcsxx_control2_reg_s cn63xxp1; 445}; 446typedef union cvmx_pcsxx_control2_reg cvmx_pcsxx_control2_reg_t; 447 448/** 449 * cvmx_pcsx#_int_en_reg 450 * 451 * Note: DBG_SYNC is a edge triggered interrupt. When set it indicates PCS Synchronization state machine in 452 * Figure 48-7 state diagram in IEEE Std 802.3-2005 changes state SYNC_ACQUIRED_1 to SYNC_ACQUIRED_2 453 * indicating an invalid code group was received on one of the 4 receive lanes. 454 * This interrupt should be always disabled and used only for link problem debugging help. 455 * 456 * 457 * PCSX Interrupt Enable Register 458 */ 459union cvmx_pcsxx_int_en_reg 460{ 461 uint64_t u64; 462 struct cvmx_pcsxx_int_en_reg_s 463 { 464#if __BYTE_ORDER == __BIG_ENDIAN 465 uint64_t reserved_7_63 : 57; 466 uint64_t dbg_sync_en : 1; /**< Code Group sync failure debug help */ 467 uint64_t algnlos_en : 1; /**< Enable ALGNLOS interrupt */ 468 uint64_t synlos_en : 1; /**< Enable SYNLOS interrupt */ 469 uint64_t bitlckls_en : 1; /**< Enable BITLCKLS interrupt */ 470 uint64_t rxsynbad_en : 1; /**< Enable RXSYNBAD interrupt */ 471 uint64_t rxbad_en : 1; /**< Enable RXBAD interrupt */ 472 uint64_t txflt_en : 1; /**< Enable TXFLT interrupt */ 473#else 474 uint64_t txflt_en : 1; 475 uint64_t rxbad_en : 1; 476 uint64_t rxsynbad_en : 1; 477 uint64_t bitlckls_en : 1; 478 uint64_t synlos_en : 1; 479 uint64_t algnlos_en : 1; 480 uint64_t dbg_sync_en : 1; 481 uint64_t reserved_7_63 : 57; 482#endif 483 } s; 484 struct cvmx_pcsxx_int_en_reg_cn52xx 485 { 486#if __BYTE_ORDER == __BIG_ENDIAN 487 uint64_t reserved_6_63 : 58; 488 uint64_t algnlos_en : 1; /**< Enable ALGNLOS interrupt */ 489 uint64_t synlos_en : 1; /**< Enable SYNLOS interrupt */ 490 uint64_t bitlckls_en : 1; /**< Enable BITLCKLS interrupt */ 491 uint64_t rxsynbad_en : 1; /**< Enable RXSYNBAD interrupt */ 492 uint64_t rxbad_en : 1; /**< Enable RXBAD interrupt */ 493 uint64_t txflt_en : 1; /**< Enable TXFLT interrupt */ 494#else 495 uint64_t txflt_en : 1; 496 uint64_t rxbad_en : 1; 497 uint64_t rxsynbad_en : 1; 498 uint64_t bitlckls_en : 1; 499 uint64_t synlos_en : 1; 500 uint64_t algnlos_en : 1; 501 uint64_t reserved_6_63 : 58; 502#endif 503 } cn52xx; 504 struct cvmx_pcsxx_int_en_reg_cn52xx cn52xxp1; 505 struct cvmx_pcsxx_int_en_reg_cn52xx cn56xx; 506 struct cvmx_pcsxx_int_en_reg_cn52xx cn56xxp1; 507 struct cvmx_pcsxx_int_en_reg_s cn63xx; 508 struct cvmx_pcsxx_int_en_reg_s cn63xxp1; 509}; 510typedef union cvmx_pcsxx_int_en_reg cvmx_pcsxx_int_en_reg_t; 511 512/** 513 * cvmx_pcsx#_int_reg 514 * 515 * PCSX Interrupt Register 516 * 517 */ 518union cvmx_pcsxx_int_reg 519{ 520 uint64_t u64; 521 struct cvmx_pcsxx_int_reg_s 522 { 523#if __BYTE_ORDER == __BIG_ENDIAN 524 uint64_t reserved_7_63 : 57; 525 uint64_t dbg_sync : 1; /**< Code Group sync failure debug help, see Note below */ 526 uint64_t algnlos : 1; /**< Set when XAUI lanes lose alignment */ 527 uint64_t synlos : 1; /**< Set when Code group sync lost on 1 or more lanes */ 528 uint64_t bitlckls : 1; /**< Set when Bit lock lost on 1 or more xaui lanes */ 529 uint64_t rxsynbad : 1; /**< Set when RX code grp sync st machine in bad state 530 in one of the 4 xaui lanes */ 531 uint64_t rxbad : 1; /**< Set when RX state machine in bad state */ 532 uint64_t txflt : 1; /**< None defined at this time, always 0x0 */ 533#else 534 uint64_t txflt : 1; 535 uint64_t rxbad : 1; 536 uint64_t rxsynbad : 1; 537 uint64_t bitlckls : 1; 538 uint64_t synlos : 1; 539 uint64_t algnlos : 1; 540 uint64_t dbg_sync : 1; 541 uint64_t reserved_7_63 : 57; 542#endif 543 } s; 544 struct cvmx_pcsxx_int_reg_cn52xx 545 { 546#if __BYTE_ORDER == __BIG_ENDIAN 547 uint64_t reserved_6_63 : 58; 548 uint64_t algnlos : 1; /**< Set when XAUI lanes lose alignment */ 549 uint64_t synlos : 1; /**< Set when Code group sync lost on 1 or more lanes */ 550 uint64_t bitlckls : 1; /**< Set when Bit lock lost on 1 or more xaui lanes */ 551 uint64_t rxsynbad : 1; /**< Set when RX code grp sync st machine in bad state 552 in one of the 4 xaui lanes */ 553 uint64_t rxbad : 1; /**< Set when RX state machine in bad state */ 554 uint64_t txflt : 1; /**< None defined at this time, always 0x0 */ 555#else 556 uint64_t txflt : 1; 557 uint64_t rxbad : 1; 558 uint64_t rxsynbad : 1; 559 uint64_t bitlckls : 1; 560 uint64_t synlos : 1; 561 uint64_t algnlos : 1; 562 uint64_t reserved_6_63 : 58; 563#endif 564 } cn52xx; 565 struct cvmx_pcsxx_int_reg_cn52xx cn52xxp1; 566 struct cvmx_pcsxx_int_reg_cn52xx cn56xx; 567 struct cvmx_pcsxx_int_reg_cn52xx cn56xxp1; 568 struct cvmx_pcsxx_int_reg_s cn63xx; 569 struct cvmx_pcsxx_int_reg_s cn63xxp1; 570}; 571typedef union cvmx_pcsxx_int_reg cvmx_pcsxx_int_reg_t; 572 573/** 574 * cvmx_pcsx#_log_anl_reg 575 * 576 * PCSX Logic Analyzer Register 577 * 578 */ 579union cvmx_pcsxx_log_anl_reg 580{ 581 uint64_t u64; 582 struct cvmx_pcsxx_log_anl_reg_s 583 { 584#if __BYTE_ORDER == __BIG_ENDIAN 585 uint64_t reserved_7_63 : 57; 586 uint64_t enc_mode : 1; /**< 1=send xaui encoded data, 0=send xaui raw data to GMX 587 See .../rtl/pcs/readme_logic_analyzer.txt for details */ 588 uint64_t drop_ln : 2; /**< xaui lane# to drop from logic analyzer packets 589 [<5>, <4>] Drop lane \# 590 0 0 Drop lane 0 data 591 0 1 Drop lane 1 data 592 1 0 Drop lane 2 data 593 1 1 Drop lane 3 data */ 594 uint64_t lafifovfl : 1; /**< 1=logic analyser fif overflowed one or more times 595 during packetization. 596 Write 1 to clear this bit */ 597 uint64_t la_en : 1; /**< 1= Logic Analyzer enabled, 0=Logic Analyzer disabled */ 598 uint64_t pkt_sz : 2; /**< [<1>, <0>] Logic Analyzer Packet Size 599 0 0 Packet size 1k bytes 600 0 1 Packet size 4k bytes 601 1 0 Packet size 8k bytes 602 1 1 Packet size 16k bytes */ 603#else 604 uint64_t pkt_sz : 2; 605 uint64_t la_en : 1; 606 uint64_t lafifovfl : 1; 607 uint64_t drop_ln : 2; 608 uint64_t enc_mode : 1; 609 uint64_t reserved_7_63 : 57; 610#endif 611 } s; 612 struct cvmx_pcsxx_log_anl_reg_s cn52xx; 613 struct cvmx_pcsxx_log_anl_reg_s cn52xxp1; 614 struct cvmx_pcsxx_log_anl_reg_s cn56xx; 615 struct cvmx_pcsxx_log_anl_reg_s cn56xxp1; 616 struct cvmx_pcsxx_log_anl_reg_s cn63xx; 617 struct cvmx_pcsxx_log_anl_reg_s cn63xxp1; 618}; 619typedef union cvmx_pcsxx_log_anl_reg cvmx_pcsxx_log_anl_reg_t; 620 621/** 622 * cvmx_pcsx#_misc_ctl_reg 623 * 624 * RX lane polarity vector [3:0] = XOR_RXPLRT<9:6> ^ [4[RXPLRT<1>]]; 625 * 626 * TX lane polarity vector [3:0] = XOR_TXPLRT<5:2> ^ [4[TXPLRT<0>]]; 627 * 628 * In short keep <1:0> to 2'b00, and use <5:2> and <9:6> fields to define per lane polarities 629 * 630 * 631 * 632 * PCSX Misc Control Register 633 */ 634union cvmx_pcsxx_misc_ctl_reg 635{ 636 uint64_t u64; 637 struct cvmx_pcsxx_misc_ctl_reg_s 638 { 639#if __BYTE_ORDER == __BIG_ENDIAN 640 uint64_t reserved_4_63 : 60; 641 uint64_t tx_swap : 1; /**< 0=do not swap xaui lanes going out to qlm's 642 1=swap lanes 3 <-> 0 and 2 <-> 1 */ 643 uint64_t rx_swap : 1; /**< 0=do not swap xaui lanes coming in from qlm's 644 1=swap lanes 3 <-> 0 and 2 <-> 1 */ 645 uint64_t xaui : 1; /**< 1=XAUI mode selected, 0=not XAUI mode selected 646 This bit represents pi_qlm1/3_cfg[1:0] pin status */ 647 uint64_t gmxeno : 1; /**< GMX port enable override, GMX en/dis status is held 648 during data packet reception. */ 649#else 650 uint64_t gmxeno : 1; 651 uint64_t xaui : 1; 652 uint64_t rx_swap : 1; 653 uint64_t tx_swap : 1; 654 uint64_t reserved_4_63 : 60; 655#endif 656 } s; 657 struct cvmx_pcsxx_misc_ctl_reg_s cn52xx; 658 struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1; 659 struct cvmx_pcsxx_misc_ctl_reg_s cn56xx; 660 struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1; 661 struct cvmx_pcsxx_misc_ctl_reg_s cn63xx; 662 struct cvmx_pcsxx_misc_ctl_reg_s cn63xxp1; 663}; 664typedef union cvmx_pcsxx_misc_ctl_reg cvmx_pcsxx_misc_ctl_reg_t; 665 666/** 667 * cvmx_pcsx#_rx_sync_states_reg 668 * 669 * PCSX_RX_SYNC_STATES_REG = Receive Sync States Register 670 * 671 */ 672union cvmx_pcsxx_rx_sync_states_reg 673{ 674 uint64_t u64; 675 struct cvmx_pcsxx_rx_sync_states_reg_s 676 { 677#if __BYTE_ORDER == __BIG_ENDIAN 678 uint64_t reserved_16_63 : 48; 679 uint64_t sync3st : 4; /**< Receive lane 3 code grp sync state machine state */ 680 uint64_t sync2st : 4; /**< Receive lane 2 code grp sync state machine state */ 681 uint64_t sync1st : 4; /**< Receive lane 1 code grp sync state machine state */ 682 uint64_t sync0st : 4; /**< Receive lane 0 code grp sync state machine state */ 683#else 684 uint64_t sync0st : 4; 685 uint64_t sync1st : 4; 686 uint64_t sync2st : 4; 687 uint64_t sync3st : 4; 688 uint64_t reserved_16_63 : 48; 689#endif 690 } s; 691 struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx; 692 struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1; 693 struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx; 694 struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1; 695 struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx; 696 struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1; 697}; 698typedef union cvmx_pcsxx_rx_sync_states_reg cvmx_pcsxx_rx_sync_states_reg_t; 699 700/** 701 * cvmx_pcsx#_spd_abil_reg 702 * 703 * PCSX_SPD_ABIL_REG = Speed ability register 704 * 705 */ 706union cvmx_pcsxx_spd_abil_reg 707{ 708 uint64_t u64; 709 struct cvmx_pcsxx_spd_abil_reg_s 710 { 711#if __BYTE_ORDER == __BIG_ENDIAN 712 uint64_t reserved_2_63 : 62; 713 uint64_t tenpasst : 1; /**< Always 0, no 10PASS-TS/2BASE-TL capability support */ 714 uint64_t tengb : 1; /**< Always 1, 10Gb/s supported */ 715#else 716 uint64_t tengb : 1; 717 uint64_t tenpasst : 1; 718 uint64_t reserved_2_63 : 62; 719#endif 720 } s; 721 struct cvmx_pcsxx_spd_abil_reg_s cn52xx; 722 struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1; 723 struct cvmx_pcsxx_spd_abil_reg_s cn56xx; 724 struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1; 725 struct cvmx_pcsxx_spd_abil_reg_s cn63xx; 726 struct cvmx_pcsxx_spd_abil_reg_s cn63xxp1; 727}; 728typedef union cvmx_pcsxx_spd_abil_reg cvmx_pcsxx_spd_abil_reg_t; 729 730/** 731 * cvmx_pcsx#_status1_reg 732 * 733 * PCSX_STATUS1_REG = Status Register1 734 * 735 */ 736union cvmx_pcsxx_status1_reg 737{ 738 uint64_t u64; 739 struct cvmx_pcsxx_status1_reg_s 740 { 741#if __BYTE_ORDER == __BIG_ENDIAN 742 uint64_t reserved_8_63 : 56; 743 uint64_t flt : 1; /**< 1=Fault condition detected, 0=No fault condition 744 This bit is a logical OR of Status2 reg bits 11,10 */ 745 uint64_t reserved_3_6 : 4; 746 uint64_t rcv_lnk : 1; /**< 1=Receive Link up, 0=Receive Link down 747 Latching Low version of r_10gbx_status_reg[12], 748 Link down status continues until SW read. */ 749 uint64_t lpable : 1; /**< Always set to 1 for Low Power ablility indication */ 750 uint64_t reserved_0_0 : 1; 751#else 752 uint64_t reserved_0_0 : 1; 753 uint64_t lpable : 1; 754 uint64_t rcv_lnk : 1; 755 uint64_t reserved_3_6 : 4; 756 uint64_t flt : 1; 757 uint64_t reserved_8_63 : 56; 758#endif 759 } s; 760 struct cvmx_pcsxx_status1_reg_s cn52xx; 761 struct cvmx_pcsxx_status1_reg_s cn52xxp1; 762 struct cvmx_pcsxx_status1_reg_s cn56xx; 763 struct cvmx_pcsxx_status1_reg_s cn56xxp1; 764 struct cvmx_pcsxx_status1_reg_s cn63xx; 765 struct cvmx_pcsxx_status1_reg_s cn63xxp1; 766}; 767typedef union cvmx_pcsxx_status1_reg cvmx_pcsxx_status1_reg_t; 768 769/** 770 * cvmx_pcsx#_status2_reg 771 * 772 * PCSX_STATUS2_REG = Status Register2 773 * 774 */ 775union cvmx_pcsxx_status2_reg 776{ 777 uint64_t u64; 778 struct cvmx_pcsxx_status2_reg_s 779 { 780#if __BYTE_ORDER == __BIG_ENDIAN 781 uint64_t reserved_16_63 : 48; 782 uint64_t dev : 2; /**< Always at 2'b10, means a Device present at the addr */ 783 uint64_t reserved_12_13 : 2; 784 uint64_t xmtflt : 1; /**< 0=No xmit fault, 1=xmit fault. Implements latching 785 High function until SW read. */ 786 uint64_t rcvflt : 1; /**< 0=No rcv fault, 1=rcv fault. Implements latching 787 High function until SW read */ 788 uint64_t reserved_3_9 : 7; 789 uint64_t tengb_w : 1; /**< Always 0, no 10GBASE-W capability */ 790 uint64_t tengb_x : 1; /**< Always 1, 10GBASE-X capable */ 791 uint64_t tengb_r : 1; /**< Always 0, no 10GBASE-R capability */ 792#else 793 uint64_t tengb_r : 1; 794 uint64_t tengb_x : 1; 795 uint64_t tengb_w : 1; 796 uint64_t reserved_3_9 : 7; 797 uint64_t rcvflt : 1; 798 uint64_t xmtflt : 1; 799 uint64_t reserved_12_13 : 2; 800 uint64_t dev : 2; 801 uint64_t reserved_16_63 : 48; 802#endif 803 } s; 804 struct cvmx_pcsxx_status2_reg_s cn52xx; 805 struct cvmx_pcsxx_status2_reg_s cn52xxp1; 806 struct cvmx_pcsxx_status2_reg_s cn56xx; 807 struct cvmx_pcsxx_status2_reg_s cn56xxp1; 808 struct cvmx_pcsxx_status2_reg_s cn63xx; 809 struct cvmx_pcsxx_status2_reg_s cn63xxp1; 810}; 811typedef union cvmx_pcsxx_status2_reg cvmx_pcsxx_status2_reg_t; 812 813/** 814 * cvmx_pcsx#_tx_rx_polarity_reg 815 * 816 * PCSX_POLARITY_REG = TX_RX polarity reg 817 * 818 */ 819union cvmx_pcsxx_tx_rx_polarity_reg 820{ 821 uint64_t u64; 822 struct cvmx_pcsxx_tx_rx_polarity_reg_s 823 { 824#if __BYTE_ORDER == __BIG_ENDIAN 825 uint64_t reserved_10_63 : 54; 826 uint64_t xor_rxplrt : 4; /**< Per lane RX polarity control */ 827 uint64_t xor_txplrt : 4; /**< Per lane TX polarity control */ 828 uint64_t rxplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */ 829 uint64_t txplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */ 830#else 831 uint64_t txplrt : 1; 832 uint64_t rxplrt : 1; 833 uint64_t xor_txplrt : 4; 834 uint64_t xor_rxplrt : 4; 835 uint64_t reserved_10_63 : 54; 836#endif 837 } s; 838 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx; 839 struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 840 { 841#if __BYTE_ORDER == __BIG_ENDIAN 842 uint64_t reserved_2_63 : 62; 843 uint64_t rxplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */ 844 uint64_t txplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */ 845#else 846 uint64_t txplrt : 1; 847 uint64_t rxplrt : 1; 848 uint64_t reserved_2_63 : 62; 849#endif 850 } cn52xxp1; 851 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx; 852 struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1; 853 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx; 854 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1; 855}; 856typedef union cvmx_pcsxx_tx_rx_polarity_reg cvmx_pcsxx_tx_rx_polarity_reg_t; 857 858/** 859 * cvmx_pcsx#_tx_rx_states_reg 860 * 861 * PCSX_TX_RX_STATES_REG = Transmit Receive States Register 862 * 863 */ 864union cvmx_pcsxx_tx_rx_states_reg 865{ 866 uint64_t u64; 867 struct cvmx_pcsxx_tx_rx_states_reg_s 868 { 869#if __BYTE_ORDER == __BIG_ENDIAN 870 uint64_t reserved_14_63 : 50; 871 uint64_t term_err : 1; /**< 1=Check end function detected error in packet 872 terminate ||T|| column or the one after it */ 873 uint64_t syn3bad : 1; /**< 1=lane 3 code grp sync state machine in bad state */ 874 uint64_t syn2bad : 1; /**< 1=lane 2 code grp sync state machine in bad state */ 875 uint64_t syn1bad : 1; /**< 1=lane 1 code grp sync state machine in bad state */ 876 uint64_t syn0bad : 1; /**< 1=lane 0 code grp sync state machine in bad state */ 877 uint64_t rxbad : 1; /**< 1=Rcv state machine in a bad state, HW malfunction */ 878 uint64_t algn_st : 3; /**< Lane alignment state machine state state */ 879 uint64_t rx_st : 2; /**< Receive state machine state state */ 880 uint64_t tx_st : 3; /**< Transmit state machine state state */ 881#else 882 uint64_t tx_st : 3; 883 uint64_t rx_st : 2; 884 uint64_t algn_st : 3; 885 uint64_t rxbad : 1; 886 uint64_t syn0bad : 1; 887 uint64_t syn1bad : 1; 888 uint64_t syn2bad : 1; 889 uint64_t syn3bad : 1; 890 uint64_t term_err : 1; 891 uint64_t reserved_14_63 : 50; 892#endif 893 } s; 894 struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx; 895 struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 896 { 897#if __BYTE_ORDER == __BIG_ENDIAN 898 uint64_t reserved_13_63 : 51; 899 uint64_t syn3bad : 1; /**< 1=lane 3 code grp sync state machine in bad state */ 900 uint64_t syn2bad : 1; /**< 1=lane 2 code grp sync state machine in bad state */ 901 uint64_t syn1bad : 1; /**< 1=lane 1 code grp sync state machine in bad state */ 902 uint64_t syn0bad : 1; /**< 1=lane 0 code grp sync state machine in bad state */ 903 uint64_t rxbad : 1; /**< 1=Rcv state machine in a bad state, HW malfunction */ 904 uint64_t algn_st : 3; /**< Lane alignment state machine state state */ 905 uint64_t rx_st : 2; /**< Receive state machine state state */ 906 uint64_t tx_st : 3; /**< Transmit state machine state state */ 907#else 908 uint64_t tx_st : 3; 909 uint64_t rx_st : 2; 910 uint64_t algn_st : 3; 911 uint64_t rxbad : 1; 912 uint64_t syn0bad : 1; 913 uint64_t syn1bad : 1; 914 uint64_t syn2bad : 1; 915 uint64_t syn3bad : 1; 916 uint64_t reserved_13_63 : 51; 917#endif 918 } cn52xxp1; 919 struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx; 920 struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1; 921 struct cvmx_pcsxx_tx_rx_states_reg_s cn63xx; 922 struct cvmx_pcsxx_tx_rx_states_reg_s cn63xxp1; 923}; 924typedef union cvmx_pcsxx_tx_rx_states_reg cvmx_pcsxx_tx_rx_states_reg_t; 925 926#endif 927