cvmx-pcmx-defs.h revision 232812
1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pcmx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon pcmx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_PCMX_DEFS_H__ 53232812Sjmallett#define __CVMX_PCMX_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_PCMX_DMA_CFG(unsigned long offset) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 61232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 62232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 63232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 64215976Sjmallett cvmx_warn("CVMX_PCMX_DMA_CFG(%lu) is invalid on this chip\n", offset); 65215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384; 66215976Sjmallett} 67215976Sjmallett#else 68215976Sjmallett#define CVMX_PCMX_DMA_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384) 69215976Sjmallett#endif 70215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71215976Sjmallettstatic inline uint64_t CVMX_PCMX_INT_ENA(unsigned long offset) 72215976Sjmallett{ 73215976Sjmallett if (!( 74215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 75215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 76232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 77232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 78232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 79215976Sjmallett cvmx_warn("CVMX_PCMX_INT_ENA(%lu) is invalid on this chip\n", offset); 80215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384; 81215976Sjmallett} 82215976Sjmallett#else 83215976Sjmallett#define CVMX_PCMX_INT_ENA(offset) (CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384) 84215976Sjmallett#endif 85215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 86215976Sjmallettstatic inline uint64_t CVMX_PCMX_INT_SUM(unsigned long offset) 87215976Sjmallett{ 88215976Sjmallett if (!( 89215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 90215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 91232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 92232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 93232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 94215976Sjmallett cvmx_warn("CVMX_PCMX_INT_SUM(%lu) is invalid on this chip\n", offset); 95215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384; 96215976Sjmallett} 97215976Sjmallett#else 98215976Sjmallett#define CVMX_PCMX_INT_SUM(offset) (CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384) 99215976Sjmallett#endif 100215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 101215976Sjmallettstatic inline uint64_t CVMX_PCMX_RXADDR(unsigned long offset) 102215976Sjmallett{ 103215976Sjmallett if (!( 104215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 105215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 106232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 107232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 108232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 109215976Sjmallett cvmx_warn("CVMX_PCMX_RXADDR(%lu) is invalid on this chip\n", offset); 110215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384; 111215976Sjmallett} 112215976Sjmallett#else 113215976Sjmallett#define CVMX_PCMX_RXADDR(offset) (CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384) 114215976Sjmallett#endif 115215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116215976Sjmallettstatic inline uint64_t CVMX_PCMX_RXCNT(unsigned long offset) 117215976Sjmallett{ 118215976Sjmallett if (!( 119215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 120215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 121232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 122232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 123232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 124215976Sjmallett cvmx_warn("CVMX_PCMX_RXCNT(%lu) is invalid on this chip\n", offset); 125215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010060ull) + ((offset) & 3) * 16384; 126215976Sjmallett} 127215976Sjmallett#else 128215976Sjmallett#define CVMX_PCMX_RXCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000010060ull) + ((offset) & 3) * 16384) 129215976Sjmallett#endif 130215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 131215976Sjmallettstatic inline uint64_t CVMX_PCMX_RXMSK0(unsigned long offset) 132215976Sjmallett{ 133215976Sjmallett if (!( 134215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 135215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 136232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 137232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 138232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 139215976Sjmallett cvmx_warn("CVMX_PCMX_RXMSK0(%lu) is invalid on this chip\n", offset); 140215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000100C0ull) + ((offset) & 3) * 16384; 141215976Sjmallett} 142215976Sjmallett#else 143215976Sjmallett#define CVMX_PCMX_RXMSK0(offset) (CVMX_ADD_IO_SEG(0x00010700000100C0ull) + ((offset) & 3) * 16384) 144215976Sjmallett#endif 145215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 146215976Sjmallettstatic inline uint64_t CVMX_PCMX_RXMSK1(unsigned long offset) 147215976Sjmallett{ 148215976Sjmallett if (!( 149215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 150215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 151232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 152232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 153232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 154215976Sjmallett cvmx_warn("CVMX_PCMX_RXMSK1(%lu) is invalid on this chip\n", offset); 155215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000100C8ull) + ((offset) & 3) * 16384; 156215976Sjmallett} 157215976Sjmallett#else 158215976Sjmallett#define CVMX_PCMX_RXMSK1(offset) (CVMX_ADD_IO_SEG(0x00010700000100C8ull) + ((offset) & 3) * 16384) 159215976Sjmallett#endif 160215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 161215976Sjmallettstatic inline uint64_t CVMX_PCMX_RXMSK2(unsigned long offset) 162215976Sjmallett{ 163215976Sjmallett if (!( 164215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 165215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 166232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 167232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 168232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 169215976Sjmallett cvmx_warn("CVMX_PCMX_RXMSK2(%lu) is invalid on this chip\n", offset); 170215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000100D0ull) + ((offset) & 3) * 16384; 171215976Sjmallett} 172215976Sjmallett#else 173215976Sjmallett#define CVMX_PCMX_RXMSK2(offset) (CVMX_ADD_IO_SEG(0x00010700000100D0ull) + ((offset) & 3) * 16384) 174215976Sjmallett#endif 175215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176215976Sjmallettstatic inline uint64_t CVMX_PCMX_RXMSK3(unsigned long offset) 177215976Sjmallett{ 178215976Sjmallett if (!( 179215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 180215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 181232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 182232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 183232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 184215976Sjmallett cvmx_warn("CVMX_PCMX_RXMSK3(%lu) is invalid on this chip\n", offset); 185215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000100D8ull) + ((offset) & 3) * 16384; 186215976Sjmallett} 187215976Sjmallett#else 188215976Sjmallett#define CVMX_PCMX_RXMSK3(offset) (CVMX_ADD_IO_SEG(0x00010700000100D8ull) + ((offset) & 3) * 16384) 189215976Sjmallett#endif 190215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 191215976Sjmallettstatic inline uint64_t CVMX_PCMX_RXMSK4(unsigned long offset) 192215976Sjmallett{ 193215976Sjmallett if (!( 194215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 195215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 196232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 197232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 198232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 199215976Sjmallett cvmx_warn("CVMX_PCMX_RXMSK4(%lu) is invalid on this chip\n", offset); 200215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000100E0ull) + ((offset) & 3) * 16384; 201215976Sjmallett} 202215976Sjmallett#else 203215976Sjmallett#define CVMX_PCMX_RXMSK4(offset) (CVMX_ADD_IO_SEG(0x00010700000100E0ull) + ((offset) & 3) * 16384) 204215976Sjmallett#endif 205215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 206215976Sjmallettstatic inline uint64_t CVMX_PCMX_RXMSK5(unsigned long offset) 207215976Sjmallett{ 208215976Sjmallett if (!( 209215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 210215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 211232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 212232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 213232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 214215976Sjmallett cvmx_warn("CVMX_PCMX_RXMSK5(%lu) is invalid on this chip\n", offset); 215215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000100E8ull) + ((offset) & 3) * 16384; 216215976Sjmallett} 217215976Sjmallett#else 218215976Sjmallett#define CVMX_PCMX_RXMSK5(offset) (CVMX_ADD_IO_SEG(0x00010700000100E8ull) + ((offset) & 3) * 16384) 219215976Sjmallett#endif 220215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221215976Sjmallettstatic inline uint64_t CVMX_PCMX_RXMSK6(unsigned long offset) 222215976Sjmallett{ 223215976Sjmallett if (!( 224215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 225215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 226232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 227232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 228232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 229215976Sjmallett cvmx_warn("CVMX_PCMX_RXMSK6(%lu) is invalid on this chip\n", offset); 230215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000100F0ull) + ((offset) & 3) * 16384; 231215976Sjmallett} 232215976Sjmallett#else 233215976Sjmallett#define CVMX_PCMX_RXMSK6(offset) (CVMX_ADD_IO_SEG(0x00010700000100F0ull) + ((offset) & 3) * 16384) 234215976Sjmallett#endif 235215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236215976Sjmallettstatic inline uint64_t CVMX_PCMX_RXMSK7(unsigned long offset) 237215976Sjmallett{ 238215976Sjmallett if (!( 239215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 240215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 241232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 242232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 243232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 244215976Sjmallett cvmx_warn("CVMX_PCMX_RXMSK7(%lu) is invalid on this chip\n", offset); 245215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000100F8ull) + ((offset) & 3) * 16384; 246215976Sjmallett} 247215976Sjmallett#else 248215976Sjmallett#define CVMX_PCMX_RXMSK7(offset) (CVMX_ADD_IO_SEG(0x00010700000100F8ull) + ((offset) & 3) * 16384) 249215976Sjmallett#endif 250215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 251215976Sjmallettstatic inline uint64_t CVMX_PCMX_RXSTART(unsigned long offset) 252215976Sjmallett{ 253215976Sjmallett if (!( 254215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 255215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 256232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 257232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 258232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 259215976Sjmallett cvmx_warn("CVMX_PCMX_RXSTART(%lu) is invalid on this chip\n", offset); 260215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010058ull) + ((offset) & 3) * 16384; 261215976Sjmallett} 262215976Sjmallett#else 263215976Sjmallett#define CVMX_PCMX_RXSTART(offset) (CVMX_ADD_IO_SEG(0x0001070000010058ull) + ((offset) & 3) * 16384) 264215976Sjmallett#endif 265215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 266215976Sjmallettstatic inline uint64_t CVMX_PCMX_TDM_CFG(unsigned long offset) 267215976Sjmallett{ 268215976Sjmallett if (!( 269215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 270215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 271232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 272232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 273232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 274215976Sjmallett cvmx_warn("CVMX_PCMX_TDM_CFG(%lu) is invalid on this chip\n", offset); 275215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010010ull) + ((offset) & 3) * 16384; 276215976Sjmallett} 277215976Sjmallett#else 278215976Sjmallett#define CVMX_PCMX_TDM_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010010ull) + ((offset) & 3) * 16384) 279215976Sjmallett#endif 280215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 281215976Sjmallettstatic inline uint64_t CVMX_PCMX_TDM_DBG(unsigned long offset) 282215976Sjmallett{ 283215976Sjmallett if (!( 284215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 285215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 286232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 287232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 288232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 289215976Sjmallett cvmx_warn("CVMX_PCMX_TDM_DBG(%lu) is invalid on this chip\n", offset); 290215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010030ull) + ((offset) & 3) * 16384; 291215976Sjmallett} 292215976Sjmallett#else 293215976Sjmallett#define CVMX_PCMX_TDM_DBG(offset) (CVMX_ADD_IO_SEG(0x0001070000010030ull) + ((offset) & 3) * 16384) 294215976Sjmallett#endif 295215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 296215976Sjmallettstatic inline uint64_t CVMX_PCMX_TXADDR(unsigned long offset) 297215976Sjmallett{ 298215976Sjmallett if (!( 299215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 300215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 301232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 302232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 303232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 304215976Sjmallett cvmx_warn("CVMX_PCMX_TXADDR(%lu) is invalid on this chip\n", offset); 305215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010050ull) + ((offset) & 3) * 16384; 306215976Sjmallett} 307215976Sjmallett#else 308215976Sjmallett#define CVMX_PCMX_TXADDR(offset) (CVMX_ADD_IO_SEG(0x0001070000010050ull) + ((offset) & 3) * 16384) 309215976Sjmallett#endif 310215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 311215976Sjmallettstatic inline uint64_t CVMX_PCMX_TXCNT(unsigned long offset) 312215976Sjmallett{ 313215976Sjmallett if (!( 314215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 315215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 316232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 317232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 318232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 319215976Sjmallett cvmx_warn("CVMX_PCMX_TXCNT(%lu) is invalid on this chip\n", offset); 320215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010048ull) + ((offset) & 3) * 16384; 321215976Sjmallett} 322215976Sjmallett#else 323215976Sjmallett#define CVMX_PCMX_TXCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000010048ull) + ((offset) & 3) * 16384) 324215976Sjmallett#endif 325215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 326215976Sjmallettstatic inline uint64_t CVMX_PCMX_TXMSK0(unsigned long offset) 327215976Sjmallett{ 328215976Sjmallett if (!( 329215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 330215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 331232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 332232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 333232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 334215976Sjmallett cvmx_warn("CVMX_PCMX_TXMSK0(%lu) is invalid on this chip\n", offset); 335215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010080ull) + ((offset) & 3) * 16384; 336215976Sjmallett} 337215976Sjmallett#else 338215976Sjmallett#define CVMX_PCMX_TXMSK0(offset) (CVMX_ADD_IO_SEG(0x0001070000010080ull) + ((offset) & 3) * 16384) 339215976Sjmallett#endif 340215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 341215976Sjmallettstatic inline uint64_t CVMX_PCMX_TXMSK1(unsigned long offset) 342215976Sjmallett{ 343215976Sjmallett if (!( 344215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 345215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 346232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 347232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 348232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 349215976Sjmallett cvmx_warn("CVMX_PCMX_TXMSK1(%lu) is invalid on this chip\n", offset); 350215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010088ull) + ((offset) & 3) * 16384; 351215976Sjmallett} 352215976Sjmallett#else 353215976Sjmallett#define CVMX_PCMX_TXMSK1(offset) (CVMX_ADD_IO_SEG(0x0001070000010088ull) + ((offset) & 3) * 16384) 354215976Sjmallett#endif 355215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 356215976Sjmallettstatic inline uint64_t CVMX_PCMX_TXMSK2(unsigned long offset) 357215976Sjmallett{ 358215976Sjmallett if (!( 359215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 360215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 361232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 362232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 363232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 364215976Sjmallett cvmx_warn("CVMX_PCMX_TXMSK2(%lu) is invalid on this chip\n", offset); 365215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010090ull) + ((offset) & 3) * 16384; 366215976Sjmallett} 367215976Sjmallett#else 368215976Sjmallett#define CVMX_PCMX_TXMSK2(offset) (CVMX_ADD_IO_SEG(0x0001070000010090ull) + ((offset) & 3) * 16384) 369215976Sjmallett#endif 370215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 371215976Sjmallettstatic inline uint64_t CVMX_PCMX_TXMSK3(unsigned long offset) 372215976Sjmallett{ 373215976Sjmallett if (!( 374215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 375215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 376232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 377232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 378232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 379215976Sjmallett cvmx_warn("CVMX_PCMX_TXMSK3(%lu) is invalid on this chip\n", offset); 380215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010098ull) + ((offset) & 3) * 16384; 381215976Sjmallett} 382215976Sjmallett#else 383215976Sjmallett#define CVMX_PCMX_TXMSK3(offset) (CVMX_ADD_IO_SEG(0x0001070000010098ull) + ((offset) & 3) * 16384) 384215976Sjmallett#endif 385215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386215976Sjmallettstatic inline uint64_t CVMX_PCMX_TXMSK4(unsigned long offset) 387215976Sjmallett{ 388215976Sjmallett if (!( 389215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 390215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 391232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 392232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 393232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 394215976Sjmallett cvmx_warn("CVMX_PCMX_TXMSK4(%lu) is invalid on this chip\n", offset); 395215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000100A0ull) + ((offset) & 3) * 16384; 396215976Sjmallett} 397215976Sjmallett#else 398215976Sjmallett#define CVMX_PCMX_TXMSK4(offset) (CVMX_ADD_IO_SEG(0x00010700000100A0ull) + ((offset) & 3) * 16384) 399215976Sjmallett#endif 400215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 401215976Sjmallettstatic inline uint64_t CVMX_PCMX_TXMSK5(unsigned long offset) 402215976Sjmallett{ 403215976Sjmallett if (!( 404215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 405215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 406232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 407232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 408232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 409215976Sjmallett cvmx_warn("CVMX_PCMX_TXMSK5(%lu) is invalid on this chip\n", offset); 410215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000100A8ull) + ((offset) & 3) * 16384; 411215976Sjmallett} 412215976Sjmallett#else 413215976Sjmallett#define CVMX_PCMX_TXMSK5(offset) (CVMX_ADD_IO_SEG(0x00010700000100A8ull) + ((offset) & 3) * 16384) 414215976Sjmallett#endif 415215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 416215976Sjmallettstatic inline uint64_t CVMX_PCMX_TXMSK6(unsigned long offset) 417215976Sjmallett{ 418215976Sjmallett if (!( 419215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 420215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 421232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 422232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 423232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 424215976Sjmallett cvmx_warn("CVMX_PCMX_TXMSK6(%lu) is invalid on this chip\n", offset); 425215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000100B0ull) + ((offset) & 3) * 16384; 426215976Sjmallett} 427215976Sjmallett#else 428215976Sjmallett#define CVMX_PCMX_TXMSK6(offset) (CVMX_ADD_IO_SEG(0x00010700000100B0ull) + ((offset) & 3) * 16384) 429215976Sjmallett#endif 430215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 431215976Sjmallettstatic inline uint64_t CVMX_PCMX_TXMSK7(unsigned long offset) 432215976Sjmallett{ 433215976Sjmallett if (!( 434215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 435215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 436232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 437232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 438232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 439215976Sjmallett cvmx_warn("CVMX_PCMX_TXMSK7(%lu) is invalid on this chip\n", offset); 440215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000100B8ull) + ((offset) & 3) * 16384; 441215976Sjmallett} 442215976Sjmallett#else 443215976Sjmallett#define CVMX_PCMX_TXMSK7(offset) (CVMX_ADD_IO_SEG(0x00010700000100B8ull) + ((offset) & 3) * 16384) 444215976Sjmallett#endif 445215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 446215976Sjmallettstatic inline uint64_t CVMX_PCMX_TXSTART(unsigned long offset) 447215976Sjmallett{ 448215976Sjmallett if (!( 449215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 450215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 451232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 452232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 453232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 454215976Sjmallett cvmx_warn("CVMX_PCMX_TXSTART(%lu) is invalid on this chip\n", offset); 455215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010040ull) + ((offset) & 3) * 16384; 456215976Sjmallett} 457215976Sjmallett#else 458215976Sjmallett#define CVMX_PCMX_TXSTART(offset) (CVMX_ADD_IO_SEG(0x0001070000010040ull) + ((offset) & 3) * 16384) 459215976Sjmallett#endif 460215976Sjmallett 461215976Sjmallett/** 462215976Sjmallett * cvmx_pcm#_dma_cfg 463215976Sjmallett */ 464232812Sjmallettunion cvmx_pcmx_dma_cfg { 465215976Sjmallett uint64_t u64; 466232812Sjmallett struct cvmx_pcmx_dma_cfg_s { 467232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 468232812Sjmallett uint64_t rdpend : 1; /**< If 0, no L2C read responses pending | NS 469215976Sjmallett 1, L2C read responses are outstanding 470215976Sjmallett NOTE: When restarting after stopping a running TDM 471215976Sjmallett engine, software must wait for RDPEND to read 0 472215976Sjmallett before writing PCMn_TDM_CFG[ENABLE] to a 1 */ 473215976Sjmallett uint64_t reserved_54_62 : 9; 474232812Sjmallett uint64_t rxslots : 10; /**< Number of 8-bit slots to receive per frame | NS 475215976Sjmallett (number of slots in a receive superframe) */ 476215976Sjmallett uint64_t reserved_42_43 : 2; 477232812Sjmallett uint64_t txslots : 10; /**< Number of 8-bit slots to transmit per frame | NS 478215976Sjmallett (number of slots in a transmit superframe) */ 479215976Sjmallett uint64_t reserved_30_31 : 2; 480232812Sjmallett uint64_t rxst : 10; /**< Number of frame writes for interrupt | NS */ 481215976Sjmallett uint64_t reserved_19_19 : 1; 482232812Sjmallett uint64_t useldt : 1; /**< If 0, use LDI command to read from L2C | NS 483215976Sjmallett 1, use LDT command to read from L2C */ 484232812Sjmallett uint64_t txrd : 10; /**< Number of frame reads for interrupt | NS */ 485232812Sjmallett uint64_t fetchsiz : 4; /**< FETCHSIZ+1 timeslots are read when threshold is | NS 486215976Sjmallett reached. */ 487232812Sjmallett uint64_t thresh : 4; /**< If number of bytes remaining in the DMA fifo is <=| NS 488215976Sjmallett THRESH, initiate a fetch of timeslot data from the 489215976Sjmallett transmit memory region. 490215976Sjmallett NOTE: there are only 16B of buffer for each engine 491215976Sjmallett so the seetings for FETCHSIZ and THRESH must be 492215976Sjmallett such that the buffer will not be overrun: 493215976Sjmallett 494215976Sjmallett THRESH + min(FETCHSIZ + 1,TXSLOTS) MUST BE <= 16 */ 495215976Sjmallett#else 496215976Sjmallett uint64_t thresh : 4; 497215976Sjmallett uint64_t fetchsiz : 4; 498215976Sjmallett uint64_t txrd : 10; 499215976Sjmallett uint64_t useldt : 1; 500215976Sjmallett uint64_t reserved_19_19 : 1; 501215976Sjmallett uint64_t rxst : 10; 502215976Sjmallett uint64_t reserved_30_31 : 2; 503215976Sjmallett uint64_t txslots : 10; 504215976Sjmallett uint64_t reserved_42_43 : 2; 505215976Sjmallett uint64_t rxslots : 10; 506215976Sjmallett uint64_t reserved_54_62 : 9; 507215976Sjmallett uint64_t rdpend : 1; 508215976Sjmallett#endif 509215976Sjmallett } s; 510215976Sjmallett struct cvmx_pcmx_dma_cfg_s cn30xx; 511215976Sjmallett struct cvmx_pcmx_dma_cfg_s cn31xx; 512215976Sjmallett struct cvmx_pcmx_dma_cfg_s cn50xx; 513232812Sjmallett struct cvmx_pcmx_dma_cfg_s cn61xx; 514232812Sjmallett struct cvmx_pcmx_dma_cfg_s cnf71xx; 515215976Sjmallett}; 516215976Sjmalletttypedef union cvmx_pcmx_dma_cfg cvmx_pcmx_dma_cfg_t; 517215976Sjmallett 518215976Sjmallett/** 519215976Sjmallett * cvmx_pcm#_int_ena 520215976Sjmallett */ 521232812Sjmallettunion cvmx_pcmx_int_ena { 522215976Sjmallett uint64_t u64; 523232812Sjmallett struct cvmx_pcmx_int_ena_s { 524232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 525215976Sjmallett uint64_t reserved_8_63 : 56; 526232812Sjmallett uint64_t rxovf : 1; /**< Enable interrupt if RX byte overflows | NS */ 527232812Sjmallett uint64_t txempty : 1; /**< Enable interrupt on TX byte empty | NS */ 528232812Sjmallett uint64_t txrd : 1; /**< Enable DMA engine frame read interrupts | NS */ 529232812Sjmallett uint64_t txwrap : 1; /**< Enable TX region wrap interrupts | NS */ 530232812Sjmallett uint64_t rxst : 1; /**< Enable DMA engine frame store interrupts | NS */ 531232812Sjmallett uint64_t rxwrap : 1; /**< Enable RX region wrap interrupts | NS */ 532232812Sjmallett uint64_t fsyncextra : 1; /**< Enable FSYNC extra interrupts | NS 533215976Sjmallett NOTE: FSYNCEXTRA errors are defined as an FSYNC 534215976Sjmallett found in the "wrong" spot of a frame given the 535215976Sjmallett programming of PCMn_CLK_CFG[NUMSLOTS] and 536215976Sjmallett PCMn_CLK_CFG[EXTRABIT]. */ 537232812Sjmallett uint64_t fsyncmissed : 1; /**< Enable FSYNC missed interrupts | NS 538215976Sjmallett NOTE: FSYNCMISSED errors are defined as an FSYNC 539215976Sjmallett missing from the correct spot in a frame given 540215976Sjmallett the programming of PCMn_CLK_CFG[NUMSLOTS] and 541215976Sjmallett PCMn_CLK_CFG[EXTRABIT]. */ 542215976Sjmallett#else 543215976Sjmallett uint64_t fsyncmissed : 1; 544215976Sjmallett uint64_t fsyncextra : 1; 545215976Sjmallett uint64_t rxwrap : 1; 546215976Sjmallett uint64_t rxst : 1; 547215976Sjmallett uint64_t txwrap : 1; 548215976Sjmallett uint64_t txrd : 1; 549215976Sjmallett uint64_t txempty : 1; 550215976Sjmallett uint64_t rxovf : 1; 551215976Sjmallett uint64_t reserved_8_63 : 56; 552215976Sjmallett#endif 553215976Sjmallett } s; 554215976Sjmallett struct cvmx_pcmx_int_ena_s cn30xx; 555215976Sjmallett struct cvmx_pcmx_int_ena_s cn31xx; 556215976Sjmallett struct cvmx_pcmx_int_ena_s cn50xx; 557232812Sjmallett struct cvmx_pcmx_int_ena_s cn61xx; 558232812Sjmallett struct cvmx_pcmx_int_ena_s cnf71xx; 559215976Sjmallett}; 560215976Sjmalletttypedef union cvmx_pcmx_int_ena cvmx_pcmx_int_ena_t; 561215976Sjmallett 562215976Sjmallett/** 563215976Sjmallett * cvmx_pcm#_int_sum 564215976Sjmallett */ 565232812Sjmallettunion cvmx_pcmx_int_sum { 566215976Sjmallett uint64_t u64; 567232812Sjmallett struct cvmx_pcmx_int_sum_s { 568232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 569215976Sjmallett uint64_t reserved_8_63 : 56; 570232812Sjmallett uint64_t rxovf : 1; /**< RX byte overflowed | NS */ 571232812Sjmallett uint64_t txempty : 1; /**< TX byte was empty when sampled | NS */ 572232812Sjmallett uint64_t txrd : 1; /**< DMA engine frame read interrupt occurred | NS */ 573232812Sjmallett uint64_t txwrap : 1; /**< TX region wrap interrupt occurred | NS */ 574232812Sjmallett uint64_t rxst : 1; /**< DMA engine frame store interrupt occurred | NS */ 575232812Sjmallett uint64_t rxwrap : 1; /**< RX region wrap interrupt occurred | NS */ 576232812Sjmallett uint64_t fsyncextra : 1; /**< FSYNC extra interrupt occurred | NS */ 577232812Sjmallett uint64_t fsyncmissed : 1; /**< FSYNC missed interrupt occurred | NS */ 578215976Sjmallett#else 579215976Sjmallett uint64_t fsyncmissed : 1; 580215976Sjmallett uint64_t fsyncextra : 1; 581215976Sjmallett uint64_t rxwrap : 1; 582215976Sjmallett uint64_t rxst : 1; 583215976Sjmallett uint64_t txwrap : 1; 584215976Sjmallett uint64_t txrd : 1; 585215976Sjmallett uint64_t txempty : 1; 586215976Sjmallett uint64_t rxovf : 1; 587215976Sjmallett uint64_t reserved_8_63 : 56; 588215976Sjmallett#endif 589215976Sjmallett } s; 590215976Sjmallett struct cvmx_pcmx_int_sum_s cn30xx; 591215976Sjmallett struct cvmx_pcmx_int_sum_s cn31xx; 592215976Sjmallett struct cvmx_pcmx_int_sum_s cn50xx; 593232812Sjmallett struct cvmx_pcmx_int_sum_s cn61xx; 594232812Sjmallett struct cvmx_pcmx_int_sum_s cnf71xx; 595215976Sjmallett}; 596215976Sjmalletttypedef union cvmx_pcmx_int_sum cvmx_pcmx_int_sum_t; 597215976Sjmallett 598215976Sjmallett/** 599215976Sjmallett * cvmx_pcm#_rxaddr 600215976Sjmallett */ 601232812Sjmallettunion cvmx_pcmx_rxaddr { 602215976Sjmallett uint64_t u64; 603232812Sjmallett struct cvmx_pcmx_rxaddr_s { 604232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 605215976Sjmallett uint64_t reserved_36_63 : 28; 606232812Sjmallett uint64_t addr : 36; /**< Address of the next write to the receive memory | NS 607215976Sjmallett region */ 608215976Sjmallett#else 609215976Sjmallett uint64_t addr : 36; 610215976Sjmallett uint64_t reserved_36_63 : 28; 611215976Sjmallett#endif 612215976Sjmallett } s; 613215976Sjmallett struct cvmx_pcmx_rxaddr_s cn30xx; 614215976Sjmallett struct cvmx_pcmx_rxaddr_s cn31xx; 615215976Sjmallett struct cvmx_pcmx_rxaddr_s cn50xx; 616232812Sjmallett struct cvmx_pcmx_rxaddr_s cn61xx; 617232812Sjmallett struct cvmx_pcmx_rxaddr_s cnf71xx; 618215976Sjmallett}; 619215976Sjmalletttypedef union cvmx_pcmx_rxaddr cvmx_pcmx_rxaddr_t; 620215976Sjmallett 621215976Sjmallett/** 622215976Sjmallett * cvmx_pcm#_rxcnt 623215976Sjmallett */ 624232812Sjmallettunion cvmx_pcmx_rxcnt { 625215976Sjmallett uint64_t u64; 626232812Sjmallett struct cvmx_pcmx_rxcnt_s { 627232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 628215976Sjmallett uint64_t reserved_16_63 : 48; 629232812Sjmallett uint64_t cnt : 16; /**< Number of superframes in receive memory region | NS */ 630215976Sjmallett#else 631215976Sjmallett uint64_t cnt : 16; 632215976Sjmallett uint64_t reserved_16_63 : 48; 633215976Sjmallett#endif 634215976Sjmallett } s; 635215976Sjmallett struct cvmx_pcmx_rxcnt_s cn30xx; 636215976Sjmallett struct cvmx_pcmx_rxcnt_s cn31xx; 637215976Sjmallett struct cvmx_pcmx_rxcnt_s cn50xx; 638232812Sjmallett struct cvmx_pcmx_rxcnt_s cn61xx; 639232812Sjmallett struct cvmx_pcmx_rxcnt_s cnf71xx; 640215976Sjmallett}; 641215976Sjmalletttypedef union cvmx_pcmx_rxcnt cvmx_pcmx_rxcnt_t; 642215976Sjmallett 643215976Sjmallett/** 644215976Sjmallett * cvmx_pcm#_rxmsk0 645215976Sjmallett */ 646232812Sjmallettunion cvmx_pcmx_rxmsk0 { 647215976Sjmallett uint64_t u64; 648232812Sjmallett struct cvmx_pcmx_rxmsk0_s { 649232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 650232812Sjmallett uint64_t mask : 64; /**< Receive mask bits for slots 63 to 0 | NS 651215976Sjmallett (1 means transmit, 0 means don't transmit) */ 652215976Sjmallett#else 653215976Sjmallett uint64_t mask : 64; 654215976Sjmallett#endif 655215976Sjmallett } s; 656215976Sjmallett struct cvmx_pcmx_rxmsk0_s cn30xx; 657215976Sjmallett struct cvmx_pcmx_rxmsk0_s cn31xx; 658215976Sjmallett struct cvmx_pcmx_rxmsk0_s cn50xx; 659232812Sjmallett struct cvmx_pcmx_rxmsk0_s cn61xx; 660232812Sjmallett struct cvmx_pcmx_rxmsk0_s cnf71xx; 661215976Sjmallett}; 662215976Sjmalletttypedef union cvmx_pcmx_rxmsk0 cvmx_pcmx_rxmsk0_t; 663215976Sjmallett 664215976Sjmallett/** 665215976Sjmallett * cvmx_pcm#_rxmsk1 666215976Sjmallett */ 667232812Sjmallettunion cvmx_pcmx_rxmsk1 { 668215976Sjmallett uint64_t u64; 669232812Sjmallett struct cvmx_pcmx_rxmsk1_s { 670232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 671232812Sjmallett uint64_t mask : 64; /**< Receive mask bits for slots 127 to 64 | NS 672215976Sjmallett (1 means transmit, 0 means don't transmit) */ 673215976Sjmallett#else 674215976Sjmallett uint64_t mask : 64; 675215976Sjmallett#endif 676215976Sjmallett } s; 677215976Sjmallett struct cvmx_pcmx_rxmsk1_s cn30xx; 678215976Sjmallett struct cvmx_pcmx_rxmsk1_s cn31xx; 679215976Sjmallett struct cvmx_pcmx_rxmsk1_s cn50xx; 680232812Sjmallett struct cvmx_pcmx_rxmsk1_s cn61xx; 681232812Sjmallett struct cvmx_pcmx_rxmsk1_s cnf71xx; 682215976Sjmallett}; 683215976Sjmalletttypedef union cvmx_pcmx_rxmsk1 cvmx_pcmx_rxmsk1_t; 684215976Sjmallett 685215976Sjmallett/** 686215976Sjmallett * cvmx_pcm#_rxmsk2 687215976Sjmallett */ 688232812Sjmallettunion cvmx_pcmx_rxmsk2 { 689215976Sjmallett uint64_t u64; 690232812Sjmallett struct cvmx_pcmx_rxmsk2_s { 691232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 692232812Sjmallett uint64_t mask : 64; /**< Receive mask bits for slots 191 to 128 | NS 693215976Sjmallett (1 means transmit, 0 means don't transmit) */ 694215976Sjmallett#else 695215976Sjmallett uint64_t mask : 64; 696215976Sjmallett#endif 697215976Sjmallett } s; 698215976Sjmallett struct cvmx_pcmx_rxmsk2_s cn30xx; 699215976Sjmallett struct cvmx_pcmx_rxmsk2_s cn31xx; 700215976Sjmallett struct cvmx_pcmx_rxmsk2_s cn50xx; 701232812Sjmallett struct cvmx_pcmx_rxmsk2_s cn61xx; 702232812Sjmallett struct cvmx_pcmx_rxmsk2_s cnf71xx; 703215976Sjmallett}; 704215976Sjmalletttypedef union cvmx_pcmx_rxmsk2 cvmx_pcmx_rxmsk2_t; 705215976Sjmallett 706215976Sjmallett/** 707215976Sjmallett * cvmx_pcm#_rxmsk3 708215976Sjmallett */ 709232812Sjmallettunion cvmx_pcmx_rxmsk3 { 710215976Sjmallett uint64_t u64; 711232812Sjmallett struct cvmx_pcmx_rxmsk3_s { 712232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 713232812Sjmallett uint64_t mask : 64; /**< Receive mask bits for slots 255 to 192 | NS 714215976Sjmallett (1 means transmit, 0 means don't transmit) */ 715215976Sjmallett#else 716215976Sjmallett uint64_t mask : 64; 717215976Sjmallett#endif 718215976Sjmallett } s; 719215976Sjmallett struct cvmx_pcmx_rxmsk3_s cn30xx; 720215976Sjmallett struct cvmx_pcmx_rxmsk3_s cn31xx; 721215976Sjmallett struct cvmx_pcmx_rxmsk3_s cn50xx; 722232812Sjmallett struct cvmx_pcmx_rxmsk3_s cn61xx; 723232812Sjmallett struct cvmx_pcmx_rxmsk3_s cnf71xx; 724215976Sjmallett}; 725215976Sjmalletttypedef union cvmx_pcmx_rxmsk3 cvmx_pcmx_rxmsk3_t; 726215976Sjmallett 727215976Sjmallett/** 728215976Sjmallett * cvmx_pcm#_rxmsk4 729215976Sjmallett */ 730232812Sjmallettunion cvmx_pcmx_rxmsk4 { 731215976Sjmallett uint64_t u64; 732232812Sjmallett struct cvmx_pcmx_rxmsk4_s { 733232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 734232812Sjmallett uint64_t mask : 64; /**< Receive mask bits for slots 319 to 256 | NS 735215976Sjmallett (1 means transmit, 0 means don't transmit) */ 736215976Sjmallett#else 737215976Sjmallett uint64_t mask : 64; 738215976Sjmallett#endif 739215976Sjmallett } s; 740215976Sjmallett struct cvmx_pcmx_rxmsk4_s cn30xx; 741215976Sjmallett struct cvmx_pcmx_rxmsk4_s cn31xx; 742215976Sjmallett struct cvmx_pcmx_rxmsk4_s cn50xx; 743232812Sjmallett struct cvmx_pcmx_rxmsk4_s cn61xx; 744232812Sjmallett struct cvmx_pcmx_rxmsk4_s cnf71xx; 745215976Sjmallett}; 746215976Sjmalletttypedef union cvmx_pcmx_rxmsk4 cvmx_pcmx_rxmsk4_t; 747215976Sjmallett 748215976Sjmallett/** 749215976Sjmallett * cvmx_pcm#_rxmsk5 750215976Sjmallett */ 751232812Sjmallettunion cvmx_pcmx_rxmsk5 { 752215976Sjmallett uint64_t u64; 753232812Sjmallett struct cvmx_pcmx_rxmsk5_s { 754232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 755232812Sjmallett uint64_t mask : 64; /**< Receive mask bits for slots 383 to 320 | NS 756215976Sjmallett (1 means transmit, 0 means don't transmit) */ 757215976Sjmallett#else 758215976Sjmallett uint64_t mask : 64; 759215976Sjmallett#endif 760215976Sjmallett } s; 761215976Sjmallett struct cvmx_pcmx_rxmsk5_s cn30xx; 762215976Sjmallett struct cvmx_pcmx_rxmsk5_s cn31xx; 763215976Sjmallett struct cvmx_pcmx_rxmsk5_s cn50xx; 764232812Sjmallett struct cvmx_pcmx_rxmsk5_s cn61xx; 765232812Sjmallett struct cvmx_pcmx_rxmsk5_s cnf71xx; 766215976Sjmallett}; 767215976Sjmalletttypedef union cvmx_pcmx_rxmsk5 cvmx_pcmx_rxmsk5_t; 768215976Sjmallett 769215976Sjmallett/** 770215976Sjmallett * cvmx_pcm#_rxmsk6 771215976Sjmallett */ 772232812Sjmallettunion cvmx_pcmx_rxmsk6 { 773215976Sjmallett uint64_t u64; 774232812Sjmallett struct cvmx_pcmx_rxmsk6_s { 775232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 776232812Sjmallett uint64_t mask : 64; /**< Receive mask bits for slots 447 to 384 | NS 777215976Sjmallett (1 means transmit, 0 means don't transmit) */ 778215976Sjmallett#else 779215976Sjmallett uint64_t mask : 64; 780215976Sjmallett#endif 781215976Sjmallett } s; 782215976Sjmallett struct cvmx_pcmx_rxmsk6_s cn30xx; 783215976Sjmallett struct cvmx_pcmx_rxmsk6_s cn31xx; 784215976Sjmallett struct cvmx_pcmx_rxmsk6_s cn50xx; 785232812Sjmallett struct cvmx_pcmx_rxmsk6_s cn61xx; 786232812Sjmallett struct cvmx_pcmx_rxmsk6_s cnf71xx; 787215976Sjmallett}; 788215976Sjmalletttypedef union cvmx_pcmx_rxmsk6 cvmx_pcmx_rxmsk6_t; 789215976Sjmallett 790215976Sjmallett/** 791215976Sjmallett * cvmx_pcm#_rxmsk7 792215976Sjmallett */ 793232812Sjmallettunion cvmx_pcmx_rxmsk7 { 794215976Sjmallett uint64_t u64; 795232812Sjmallett struct cvmx_pcmx_rxmsk7_s { 796232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 797232812Sjmallett uint64_t mask : 64; /**< Receive mask bits for slots 511 to 448 | NS 798215976Sjmallett (1 means transmit, 0 means don't transmit) */ 799215976Sjmallett#else 800215976Sjmallett uint64_t mask : 64; 801215976Sjmallett#endif 802215976Sjmallett } s; 803215976Sjmallett struct cvmx_pcmx_rxmsk7_s cn30xx; 804215976Sjmallett struct cvmx_pcmx_rxmsk7_s cn31xx; 805215976Sjmallett struct cvmx_pcmx_rxmsk7_s cn50xx; 806232812Sjmallett struct cvmx_pcmx_rxmsk7_s cn61xx; 807232812Sjmallett struct cvmx_pcmx_rxmsk7_s cnf71xx; 808215976Sjmallett}; 809215976Sjmalletttypedef union cvmx_pcmx_rxmsk7 cvmx_pcmx_rxmsk7_t; 810215976Sjmallett 811215976Sjmallett/** 812215976Sjmallett * cvmx_pcm#_rxstart 813215976Sjmallett */ 814232812Sjmallettunion cvmx_pcmx_rxstart { 815215976Sjmallett uint64_t u64; 816232812Sjmallett struct cvmx_pcmx_rxstart_s { 817232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 818215976Sjmallett uint64_t reserved_36_63 : 28; 819232812Sjmallett uint64_t addr : 33; /**< Starting address for the receive memory region | NS */ 820215976Sjmallett uint64_t reserved_0_2 : 3; 821215976Sjmallett#else 822215976Sjmallett uint64_t reserved_0_2 : 3; 823215976Sjmallett uint64_t addr : 33; 824215976Sjmallett uint64_t reserved_36_63 : 28; 825215976Sjmallett#endif 826215976Sjmallett } s; 827215976Sjmallett struct cvmx_pcmx_rxstart_s cn30xx; 828215976Sjmallett struct cvmx_pcmx_rxstart_s cn31xx; 829215976Sjmallett struct cvmx_pcmx_rxstart_s cn50xx; 830232812Sjmallett struct cvmx_pcmx_rxstart_s cn61xx; 831232812Sjmallett struct cvmx_pcmx_rxstart_s cnf71xx; 832215976Sjmallett}; 833215976Sjmalletttypedef union cvmx_pcmx_rxstart cvmx_pcmx_rxstart_t; 834215976Sjmallett 835215976Sjmallett/** 836215976Sjmallett * cvmx_pcm#_tdm_cfg 837215976Sjmallett */ 838232812Sjmallettunion cvmx_pcmx_tdm_cfg { 839215976Sjmallett uint64_t u64; 840232812Sjmallett struct cvmx_pcmx_tdm_cfg_s { 841232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 842232812Sjmallett uint64_t drvtim : 16; /**< Number of ECLKs from start of bit time to stop | NS 843215976Sjmallett driving last bit of timeslot (if not driving next 844215976Sjmallett timeslot) */ 845232812Sjmallett uint64_t samppt : 16; /**< Number of ECLKs from start of bit time to sample | NS 846215976Sjmallett data bit. */ 847215976Sjmallett uint64_t reserved_3_31 : 29; 848232812Sjmallett uint64_t lsbfirst : 1; /**< If 0, shift/receive MSB first | NS 849215976Sjmallett 1, shift/receive LSB first */ 850232812Sjmallett uint64_t useclk1 : 1; /**< If 0, this PCM is based on BCLK/FSYNC0 | NS 851215976Sjmallett 1, this PCM is based on BCLK/FSYNC1 */ 852232812Sjmallett uint64_t enable : 1; /**< If 1, PCM is enabled, otherwise pins are GPIOs | NS 853215976Sjmallett NOTE: when TDM is disabled by detection of an 854215976Sjmallett FSYNC error all transmission and reception is 855215976Sjmallett halted. In addition, PCMn_TX/RXADDR are updated 856215976Sjmallett to point to the position at which the error was 857215976Sjmallett detected. */ 858215976Sjmallett#else 859215976Sjmallett uint64_t enable : 1; 860215976Sjmallett uint64_t useclk1 : 1; 861215976Sjmallett uint64_t lsbfirst : 1; 862215976Sjmallett uint64_t reserved_3_31 : 29; 863215976Sjmallett uint64_t samppt : 16; 864215976Sjmallett uint64_t drvtim : 16; 865215976Sjmallett#endif 866215976Sjmallett } s; 867215976Sjmallett struct cvmx_pcmx_tdm_cfg_s cn30xx; 868215976Sjmallett struct cvmx_pcmx_tdm_cfg_s cn31xx; 869215976Sjmallett struct cvmx_pcmx_tdm_cfg_s cn50xx; 870232812Sjmallett struct cvmx_pcmx_tdm_cfg_s cn61xx; 871232812Sjmallett struct cvmx_pcmx_tdm_cfg_s cnf71xx; 872215976Sjmallett}; 873215976Sjmalletttypedef union cvmx_pcmx_tdm_cfg cvmx_pcmx_tdm_cfg_t; 874215976Sjmallett 875215976Sjmallett/** 876215976Sjmallett * cvmx_pcm#_tdm_dbg 877215976Sjmallett */ 878232812Sjmallettunion cvmx_pcmx_tdm_dbg { 879215976Sjmallett uint64_t u64; 880232812Sjmallett struct cvmx_pcmx_tdm_dbg_s { 881232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 882232812Sjmallett uint64_t debuginfo : 64; /**< Miscellaneous debug information | NS */ 883215976Sjmallett#else 884215976Sjmallett uint64_t debuginfo : 64; 885215976Sjmallett#endif 886215976Sjmallett } s; 887215976Sjmallett struct cvmx_pcmx_tdm_dbg_s cn30xx; 888215976Sjmallett struct cvmx_pcmx_tdm_dbg_s cn31xx; 889215976Sjmallett struct cvmx_pcmx_tdm_dbg_s cn50xx; 890232812Sjmallett struct cvmx_pcmx_tdm_dbg_s cn61xx; 891232812Sjmallett struct cvmx_pcmx_tdm_dbg_s cnf71xx; 892215976Sjmallett}; 893215976Sjmalletttypedef union cvmx_pcmx_tdm_dbg cvmx_pcmx_tdm_dbg_t; 894215976Sjmallett 895215976Sjmallett/** 896215976Sjmallett * cvmx_pcm#_txaddr 897215976Sjmallett */ 898232812Sjmallettunion cvmx_pcmx_txaddr { 899215976Sjmallett uint64_t u64; 900232812Sjmallett struct cvmx_pcmx_txaddr_s { 901232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 902215976Sjmallett uint64_t reserved_36_63 : 28; 903232812Sjmallett uint64_t addr : 33; /**< Address of the next read from the transmit memory | NS 904215976Sjmallett region */ 905232812Sjmallett uint64_t fram : 3; /**< Frame offset | NS 906215976Sjmallett NOTE: this is used to extract the correct byte from 907215976Sjmallett each 64b word read from the transmit memory region */ 908215976Sjmallett#else 909215976Sjmallett uint64_t fram : 3; 910215976Sjmallett uint64_t addr : 33; 911215976Sjmallett uint64_t reserved_36_63 : 28; 912215976Sjmallett#endif 913215976Sjmallett } s; 914215976Sjmallett struct cvmx_pcmx_txaddr_s cn30xx; 915215976Sjmallett struct cvmx_pcmx_txaddr_s cn31xx; 916215976Sjmallett struct cvmx_pcmx_txaddr_s cn50xx; 917232812Sjmallett struct cvmx_pcmx_txaddr_s cn61xx; 918232812Sjmallett struct cvmx_pcmx_txaddr_s cnf71xx; 919215976Sjmallett}; 920215976Sjmalletttypedef union cvmx_pcmx_txaddr cvmx_pcmx_txaddr_t; 921215976Sjmallett 922215976Sjmallett/** 923215976Sjmallett * cvmx_pcm#_txcnt 924215976Sjmallett */ 925232812Sjmallettunion cvmx_pcmx_txcnt { 926215976Sjmallett uint64_t u64; 927232812Sjmallett struct cvmx_pcmx_txcnt_s { 928232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 929215976Sjmallett uint64_t reserved_16_63 : 48; 930232812Sjmallett uint64_t cnt : 16; /**< Number of superframes in transmit memory region | NS */ 931215976Sjmallett#else 932215976Sjmallett uint64_t cnt : 16; 933215976Sjmallett uint64_t reserved_16_63 : 48; 934215976Sjmallett#endif 935215976Sjmallett } s; 936215976Sjmallett struct cvmx_pcmx_txcnt_s cn30xx; 937215976Sjmallett struct cvmx_pcmx_txcnt_s cn31xx; 938215976Sjmallett struct cvmx_pcmx_txcnt_s cn50xx; 939232812Sjmallett struct cvmx_pcmx_txcnt_s cn61xx; 940232812Sjmallett struct cvmx_pcmx_txcnt_s cnf71xx; 941215976Sjmallett}; 942215976Sjmalletttypedef union cvmx_pcmx_txcnt cvmx_pcmx_txcnt_t; 943215976Sjmallett 944215976Sjmallett/** 945215976Sjmallett * cvmx_pcm#_txmsk0 946215976Sjmallett */ 947232812Sjmallettunion cvmx_pcmx_txmsk0 { 948215976Sjmallett uint64_t u64; 949232812Sjmallett struct cvmx_pcmx_txmsk0_s { 950232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 951232812Sjmallett uint64_t mask : 64; /**< Transmit mask bits for slots 63 to 0 | NS 952215976Sjmallett (1 means transmit, 0 means don't transmit) */ 953215976Sjmallett#else 954215976Sjmallett uint64_t mask : 64; 955215976Sjmallett#endif 956215976Sjmallett } s; 957215976Sjmallett struct cvmx_pcmx_txmsk0_s cn30xx; 958215976Sjmallett struct cvmx_pcmx_txmsk0_s cn31xx; 959215976Sjmallett struct cvmx_pcmx_txmsk0_s cn50xx; 960232812Sjmallett struct cvmx_pcmx_txmsk0_s cn61xx; 961232812Sjmallett struct cvmx_pcmx_txmsk0_s cnf71xx; 962215976Sjmallett}; 963215976Sjmalletttypedef union cvmx_pcmx_txmsk0 cvmx_pcmx_txmsk0_t; 964215976Sjmallett 965215976Sjmallett/** 966215976Sjmallett * cvmx_pcm#_txmsk1 967215976Sjmallett */ 968232812Sjmallettunion cvmx_pcmx_txmsk1 { 969215976Sjmallett uint64_t u64; 970232812Sjmallett struct cvmx_pcmx_txmsk1_s { 971232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 972232812Sjmallett uint64_t mask : 64; /**< Transmit mask bits for slots 127 to 64 | NS 973215976Sjmallett (1 means transmit, 0 means don't transmit) */ 974215976Sjmallett#else 975215976Sjmallett uint64_t mask : 64; 976215976Sjmallett#endif 977215976Sjmallett } s; 978215976Sjmallett struct cvmx_pcmx_txmsk1_s cn30xx; 979215976Sjmallett struct cvmx_pcmx_txmsk1_s cn31xx; 980215976Sjmallett struct cvmx_pcmx_txmsk1_s cn50xx; 981232812Sjmallett struct cvmx_pcmx_txmsk1_s cn61xx; 982232812Sjmallett struct cvmx_pcmx_txmsk1_s cnf71xx; 983215976Sjmallett}; 984215976Sjmalletttypedef union cvmx_pcmx_txmsk1 cvmx_pcmx_txmsk1_t; 985215976Sjmallett 986215976Sjmallett/** 987215976Sjmallett * cvmx_pcm#_txmsk2 988215976Sjmallett */ 989232812Sjmallettunion cvmx_pcmx_txmsk2 { 990215976Sjmallett uint64_t u64; 991232812Sjmallett struct cvmx_pcmx_txmsk2_s { 992232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 993232812Sjmallett uint64_t mask : 64; /**< Transmit mask bits for slots 191 to 128 | NS 994215976Sjmallett (1 means transmit, 0 means don't transmit) */ 995215976Sjmallett#else 996215976Sjmallett uint64_t mask : 64; 997215976Sjmallett#endif 998215976Sjmallett } s; 999215976Sjmallett struct cvmx_pcmx_txmsk2_s cn30xx; 1000215976Sjmallett struct cvmx_pcmx_txmsk2_s cn31xx; 1001215976Sjmallett struct cvmx_pcmx_txmsk2_s cn50xx; 1002232812Sjmallett struct cvmx_pcmx_txmsk2_s cn61xx; 1003232812Sjmallett struct cvmx_pcmx_txmsk2_s cnf71xx; 1004215976Sjmallett}; 1005215976Sjmalletttypedef union cvmx_pcmx_txmsk2 cvmx_pcmx_txmsk2_t; 1006215976Sjmallett 1007215976Sjmallett/** 1008215976Sjmallett * cvmx_pcm#_txmsk3 1009215976Sjmallett */ 1010232812Sjmallettunion cvmx_pcmx_txmsk3 { 1011215976Sjmallett uint64_t u64; 1012232812Sjmallett struct cvmx_pcmx_txmsk3_s { 1013232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1014232812Sjmallett uint64_t mask : 64; /**< Transmit mask bits for slots 255 to 192 | NS 1015215976Sjmallett (1 means transmit, 0 means don't transmit) */ 1016215976Sjmallett#else 1017215976Sjmallett uint64_t mask : 64; 1018215976Sjmallett#endif 1019215976Sjmallett } s; 1020215976Sjmallett struct cvmx_pcmx_txmsk3_s cn30xx; 1021215976Sjmallett struct cvmx_pcmx_txmsk3_s cn31xx; 1022215976Sjmallett struct cvmx_pcmx_txmsk3_s cn50xx; 1023232812Sjmallett struct cvmx_pcmx_txmsk3_s cn61xx; 1024232812Sjmallett struct cvmx_pcmx_txmsk3_s cnf71xx; 1025215976Sjmallett}; 1026215976Sjmalletttypedef union cvmx_pcmx_txmsk3 cvmx_pcmx_txmsk3_t; 1027215976Sjmallett 1028215976Sjmallett/** 1029215976Sjmallett * cvmx_pcm#_txmsk4 1030215976Sjmallett */ 1031232812Sjmallettunion cvmx_pcmx_txmsk4 { 1032215976Sjmallett uint64_t u64; 1033232812Sjmallett struct cvmx_pcmx_txmsk4_s { 1034232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1035232812Sjmallett uint64_t mask : 64; /**< Transmit mask bits for slots 319 to 256 | NS 1036215976Sjmallett (1 means transmit, 0 means don't transmit) */ 1037215976Sjmallett#else 1038215976Sjmallett uint64_t mask : 64; 1039215976Sjmallett#endif 1040215976Sjmallett } s; 1041215976Sjmallett struct cvmx_pcmx_txmsk4_s cn30xx; 1042215976Sjmallett struct cvmx_pcmx_txmsk4_s cn31xx; 1043215976Sjmallett struct cvmx_pcmx_txmsk4_s cn50xx; 1044232812Sjmallett struct cvmx_pcmx_txmsk4_s cn61xx; 1045232812Sjmallett struct cvmx_pcmx_txmsk4_s cnf71xx; 1046215976Sjmallett}; 1047215976Sjmalletttypedef union cvmx_pcmx_txmsk4 cvmx_pcmx_txmsk4_t; 1048215976Sjmallett 1049215976Sjmallett/** 1050215976Sjmallett * cvmx_pcm#_txmsk5 1051215976Sjmallett */ 1052232812Sjmallettunion cvmx_pcmx_txmsk5 { 1053215976Sjmallett uint64_t u64; 1054232812Sjmallett struct cvmx_pcmx_txmsk5_s { 1055232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1056232812Sjmallett uint64_t mask : 64; /**< Transmit mask bits for slots 383 to 320 | NS 1057215976Sjmallett (1 means transmit, 0 means don't transmit) */ 1058215976Sjmallett#else 1059215976Sjmallett uint64_t mask : 64; 1060215976Sjmallett#endif 1061215976Sjmallett } s; 1062215976Sjmallett struct cvmx_pcmx_txmsk5_s cn30xx; 1063215976Sjmallett struct cvmx_pcmx_txmsk5_s cn31xx; 1064215976Sjmallett struct cvmx_pcmx_txmsk5_s cn50xx; 1065232812Sjmallett struct cvmx_pcmx_txmsk5_s cn61xx; 1066232812Sjmallett struct cvmx_pcmx_txmsk5_s cnf71xx; 1067215976Sjmallett}; 1068215976Sjmalletttypedef union cvmx_pcmx_txmsk5 cvmx_pcmx_txmsk5_t; 1069215976Sjmallett 1070215976Sjmallett/** 1071215976Sjmallett * cvmx_pcm#_txmsk6 1072215976Sjmallett */ 1073232812Sjmallettunion cvmx_pcmx_txmsk6 { 1074215976Sjmallett uint64_t u64; 1075232812Sjmallett struct cvmx_pcmx_txmsk6_s { 1076232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1077232812Sjmallett uint64_t mask : 64; /**< Transmit mask bits for slots 447 to 384 | NS 1078215976Sjmallett (1 means transmit, 0 means don't transmit) */ 1079215976Sjmallett#else 1080215976Sjmallett uint64_t mask : 64; 1081215976Sjmallett#endif 1082215976Sjmallett } s; 1083215976Sjmallett struct cvmx_pcmx_txmsk6_s cn30xx; 1084215976Sjmallett struct cvmx_pcmx_txmsk6_s cn31xx; 1085215976Sjmallett struct cvmx_pcmx_txmsk6_s cn50xx; 1086232812Sjmallett struct cvmx_pcmx_txmsk6_s cn61xx; 1087232812Sjmallett struct cvmx_pcmx_txmsk6_s cnf71xx; 1088215976Sjmallett}; 1089215976Sjmalletttypedef union cvmx_pcmx_txmsk6 cvmx_pcmx_txmsk6_t; 1090215976Sjmallett 1091215976Sjmallett/** 1092215976Sjmallett * cvmx_pcm#_txmsk7 1093215976Sjmallett */ 1094232812Sjmallettunion cvmx_pcmx_txmsk7 { 1095215976Sjmallett uint64_t u64; 1096232812Sjmallett struct cvmx_pcmx_txmsk7_s { 1097232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1098232812Sjmallett uint64_t mask : 64; /**< Transmit mask bits for slots 511 to 448 | NS 1099215976Sjmallett (1 means transmit, 0 means don't transmit) */ 1100215976Sjmallett#else 1101215976Sjmallett uint64_t mask : 64; 1102215976Sjmallett#endif 1103215976Sjmallett } s; 1104215976Sjmallett struct cvmx_pcmx_txmsk7_s cn30xx; 1105215976Sjmallett struct cvmx_pcmx_txmsk7_s cn31xx; 1106215976Sjmallett struct cvmx_pcmx_txmsk7_s cn50xx; 1107232812Sjmallett struct cvmx_pcmx_txmsk7_s cn61xx; 1108232812Sjmallett struct cvmx_pcmx_txmsk7_s cnf71xx; 1109215976Sjmallett}; 1110215976Sjmalletttypedef union cvmx_pcmx_txmsk7 cvmx_pcmx_txmsk7_t; 1111215976Sjmallett 1112215976Sjmallett/** 1113215976Sjmallett * cvmx_pcm#_txstart 1114215976Sjmallett */ 1115232812Sjmallettunion cvmx_pcmx_txstart { 1116215976Sjmallett uint64_t u64; 1117232812Sjmallett struct cvmx_pcmx_txstart_s { 1118232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1119215976Sjmallett uint64_t reserved_36_63 : 28; 1120232812Sjmallett uint64_t addr : 33; /**< Starting address for the transmit memory region | NS */ 1121215976Sjmallett uint64_t reserved_0_2 : 3; 1122215976Sjmallett#else 1123215976Sjmallett uint64_t reserved_0_2 : 3; 1124215976Sjmallett uint64_t addr : 33; 1125215976Sjmallett uint64_t reserved_36_63 : 28; 1126215976Sjmallett#endif 1127215976Sjmallett } s; 1128215976Sjmallett struct cvmx_pcmx_txstart_s cn30xx; 1129215976Sjmallett struct cvmx_pcmx_txstart_s cn31xx; 1130215976Sjmallett struct cvmx_pcmx_txstart_s cn50xx; 1131232812Sjmallett struct cvmx_pcmx_txstart_s cn61xx; 1132232812Sjmallett struct cvmx_pcmx_txstart_s cnf71xx; 1133215976Sjmallett}; 1134215976Sjmalletttypedef union cvmx_pcmx_txstart cvmx_pcmx_txstart_t; 1135215976Sjmallett 1136215976Sjmallett#endif 1137