cvmx-pcie.h revision 210284
1210284Sjmallett/***********************license start*************** 2210284Sjmallett * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3210284Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6210284Sjmallett * Redistribution and use in source and binary forms, with or without 7210284Sjmallett * modification, are permitted provided that the following conditions are 8210284Sjmallett * met: 9210284Sjmallett * 10210284Sjmallett * * Redistributions of source code must retain the above copyright 11210284Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13210284Sjmallett * * Redistributions in binary form must reproduce the above 14210284Sjmallett * copyright notice, this list of conditions and the following 15210284Sjmallett * disclaimer in the documentation and/or other materials provided 16210284Sjmallett * with the distribution. 17210284Sjmallett * 18210284Sjmallett * * Neither the name of Cavium Networks nor the names of 19210284Sjmallett * its contributors may be used to endorse or promote products 20210284Sjmallett * derived from this software without specific prior written 21210284Sjmallett * permission. 22210284Sjmallett * 23210284Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24210284Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25210284Sjmallett * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26210284Sjmallett * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27210284Sjmallett * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28210284Sjmallett * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29210284Sjmallett * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30210284Sjmallett * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31210284Sjmallett * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32210284Sjmallett * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33210284Sjmallett * 34210284Sjmallett * 35210284Sjmallett * For any questions regarding licensing please contact marketing@caviumnetworks.com 36210284Sjmallett * 37210284Sjmallett ***********************license end**************************************/ 38210284Sjmallett 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett/** 45210284Sjmallett * @file 46210284Sjmallett * 47210284Sjmallett * Interface to PCIe as a host(RC) or target(EP) 48210284Sjmallett * 49210284Sjmallett * <hr>$Revision: 41586 $<hr> 50210284Sjmallett */ 51210284Sjmallett 52210284Sjmallett#ifndef __CVMX_PCIE_H__ 53210284Sjmallett#define __CVMX_PCIE_H__ 54210284Sjmallett 55210284Sjmallett#ifdef __cplusplus 56210284Sjmallettextern "C" { 57210284Sjmallett#endif 58210284Sjmallett 59210284Sjmalletttypedef union 60210284Sjmallett{ 61210284Sjmallett uint64_t u64; 62210284Sjmallett struct 63210284Sjmallett { 64210284Sjmallett uint64_t upper : 2; /* Normally 2 for XKPHYS */ 65210284Sjmallett uint64_t reserved_49_61 : 13; /* Must be zero */ 66210284Sjmallett uint64_t io : 1; /* 1 for IO space access */ 67210284Sjmallett uint64_t did : 5; /* PCIe DID = 3 */ 68210284Sjmallett uint64_t subdid : 3; /* PCIe SubDID = 1 */ 69210284Sjmallett uint64_t reserved_36_39 : 4; /* Must be zero */ 70210284Sjmallett uint64_t es : 2; /* Endian swap = 1 */ 71210284Sjmallett uint64_t port : 2; /* PCIe port 0,1 */ 72210284Sjmallett uint64_t reserved_29_31 : 3; /* Must be zero */ 73210284Sjmallett uint64_t ty : 1; /* Selects the type of the configuration request (0 = type 0, 1 = type 1). */ 74210284Sjmallett uint64_t bus : 8; /* Target bus number sent in the ID in the request. */ 75210284Sjmallett uint64_t dev : 5; /* Target device number sent in the ID in the request. Note that Dev must be 76210284Sjmallett zero for type 0 configuration requests. */ 77210284Sjmallett uint64_t func : 3; /* Target function number sent in the ID in the request. */ 78210284Sjmallett uint64_t reg : 12; /* Selects a register in the configuration space of the target. */ 79210284Sjmallett } config; 80210284Sjmallett struct 81210284Sjmallett { 82210284Sjmallett uint64_t upper : 2; /* Normally 2 for XKPHYS */ 83210284Sjmallett uint64_t reserved_49_61 : 13; /* Must be zero */ 84210284Sjmallett uint64_t io : 1; /* 1 for IO space access */ 85210284Sjmallett uint64_t did : 5; /* PCIe DID = 3 */ 86210284Sjmallett uint64_t subdid : 3; /* PCIe SubDID = 2 */ 87210284Sjmallett uint64_t reserved_36_39 : 4; /* Must be zero */ 88210284Sjmallett uint64_t es : 2; /* Endian swap = 1 */ 89210284Sjmallett uint64_t port : 2; /* PCIe port 0,1 */ 90210284Sjmallett uint64_t address : 32; /* PCIe IO address */ 91210284Sjmallett } io; 92210284Sjmallett struct 93210284Sjmallett { 94210284Sjmallett uint64_t upper : 2; /* Normally 2 for XKPHYS */ 95210284Sjmallett uint64_t reserved_49_61 : 13; /* Must be zero */ 96210284Sjmallett uint64_t io : 1; /* 1 for IO space access */ 97210284Sjmallett uint64_t did : 5; /* PCIe DID = 3 */ 98210284Sjmallett uint64_t subdid : 3; /* PCIe SubDID = 3-6 */ 99210284Sjmallett uint64_t reserved_36_39 : 4; /* Must be zero */ 100210284Sjmallett uint64_t address : 36; /* PCIe Mem address */ 101210284Sjmallett } mem; 102210284Sjmallett} cvmx_pcie_address_t; 103210284Sjmallett 104210284Sjmallett 105210284Sjmallett/** 106210284Sjmallett * Return the Core virtual base address for PCIe IO access. IOs are 107210284Sjmallett * read/written as an offset from this address. 108210284Sjmallett * 109210284Sjmallett * @param pcie_port PCIe port the IO is for 110210284Sjmallett * 111210284Sjmallett * @return 64bit Octeon IO base address for read/write 112210284Sjmallett */ 113210284Sjmallettuint64_t cvmx_pcie_get_io_base_address(int pcie_port); 114210284Sjmallett 115210284Sjmallett/** 116210284Sjmallett * Size of the IO address region returned at address 117210284Sjmallett * cvmx_pcie_get_io_base_address() 118210284Sjmallett * 119210284Sjmallett * @param pcie_port PCIe port the IO is for 120210284Sjmallett * 121210284Sjmallett * @return Size of the IO window 122210284Sjmallett */ 123210284Sjmallettuint64_t cvmx_pcie_get_io_size(int pcie_port); 124210284Sjmallett 125210284Sjmallett/** 126210284Sjmallett * Return the Core virtual base address for PCIe MEM access. Memory is 127210284Sjmallett * read/written as an offset from this address. 128210284Sjmallett * 129210284Sjmallett * @param pcie_port PCIe port the IO is for 130210284Sjmallett * 131210284Sjmallett * @return 64bit Octeon IO base address for read/write 132210284Sjmallett */ 133210284Sjmallettuint64_t cvmx_pcie_get_mem_base_address(int pcie_port); 134210284Sjmallett 135210284Sjmallett/** 136210284Sjmallett * Size of the Mem address region returned at address 137210284Sjmallett * cvmx_pcie_get_mem_base_address() 138210284Sjmallett * 139210284Sjmallett * @param pcie_port PCIe port the IO is for 140210284Sjmallett * 141210284Sjmallett * @return Size of the Mem window 142210284Sjmallett */ 143210284Sjmallettuint64_t cvmx_pcie_get_mem_size(int pcie_port); 144210284Sjmallett 145210284Sjmallett/** 146210284Sjmallett * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus. 147210284Sjmallett * 148210284Sjmallett * @param pcie_port PCIe port to initialize 149210284Sjmallett * 150210284Sjmallett * @return Zero on success 151210284Sjmallett */ 152210284Sjmallettint cvmx_pcie_rc_initialize(int pcie_port); 153210284Sjmallett 154210284Sjmallett/** 155210284Sjmallett * Shutdown a PCIe port and put it in reset 156210284Sjmallett * 157210284Sjmallett * @param pcie_port PCIe port to shutdown 158210284Sjmallett * 159210284Sjmallett * @return Zero on success 160210284Sjmallett */ 161210284Sjmallettint cvmx_pcie_rc_shutdown(int pcie_port); 162210284Sjmallett 163210284Sjmallett/** 164210284Sjmallett * Read 8bits from a Device's config space 165210284Sjmallett * 166210284Sjmallett * @param pcie_port PCIe port the device is on 167210284Sjmallett * @param bus Sub bus 168210284Sjmallett * @param dev Device ID 169210284Sjmallett * @param fn Device sub function 170210284Sjmallett * @param reg Register to access 171210284Sjmallett * 172210284Sjmallett * @return Result of the read 173210284Sjmallett */ 174210284Sjmallettuint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev, int fn, int reg); 175210284Sjmallett 176210284Sjmallett/** 177210284Sjmallett * Read 16bits from a Device's config space 178210284Sjmallett * 179210284Sjmallett * @param pcie_port PCIe port the device is on 180210284Sjmallett * @param bus Sub bus 181210284Sjmallett * @param dev Device ID 182210284Sjmallett * @param fn Device sub function 183210284Sjmallett * @param reg Register to access 184210284Sjmallett * 185210284Sjmallett * @return Result of the read 186210284Sjmallett */ 187210284Sjmallettuint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev, int fn, int reg); 188210284Sjmallett 189210284Sjmallett/** 190210284Sjmallett * Read 32bits from a Device's config space 191210284Sjmallett * 192210284Sjmallett * @param pcie_port PCIe port the device is on 193210284Sjmallett * @param bus Sub bus 194210284Sjmallett * @param dev Device ID 195210284Sjmallett * @param fn Device sub function 196210284Sjmallett * @param reg Register to access 197210284Sjmallett * 198210284Sjmallett * @return Result of the read 199210284Sjmallett */ 200210284Sjmallettuint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, int fn, int reg); 201210284Sjmallett 202210284Sjmallett/** 203210284Sjmallett * Write 8bits to a Device's config space 204210284Sjmallett * 205210284Sjmallett * @param pcie_port PCIe port the device is on 206210284Sjmallett * @param bus Sub bus 207210284Sjmallett * @param dev Device ID 208210284Sjmallett * @param fn Device sub function 209210284Sjmallett * @param reg Register to access 210210284Sjmallett * @param val Value to write 211210284Sjmallett */ 212210284Sjmallettvoid cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn, int reg, uint8_t val); 213210284Sjmallett 214210284Sjmallett/** 215210284Sjmallett * Write 16bits to a Device's config space 216210284Sjmallett * 217210284Sjmallett * @param pcie_port PCIe port the device is on 218210284Sjmallett * @param bus Sub bus 219210284Sjmallett * @param dev Device ID 220210284Sjmallett * @param fn Device sub function 221210284Sjmallett * @param reg Register to access 222210284Sjmallett * @param val Value to write 223210284Sjmallett */ 224210284Sjmallettvoid cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn, int reg, uint16_t val); 225210284Sjmallett 226210284Sjmallett/** 227210284Sjmallett * Write 32bits to a Device's config space 228210284Sjmallett * 229210284Sjmallett * @param pcie_port PCIe port the device is on 230210284Sjmallett * @param bus Sub bus 231210284Sjmallett * @param dev Device ID 232210284Sjmallett * @param fn Device sub function 233210284Sjmallett * @param reg Register to access 234210284Sjmallett * @param val Value to write 235210284Sjmallett */ 236210284Sjmallettvoid cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn, int reg, uint32_t val); 237210284Sjmallett 238210284Sjmallett/** 239210284Sjmallett * Read a PCIe config space register indirectly. This is used for 240210284Sjmallett * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???. 241210284Sjmallett * 242210284Sjmallett * @param pcie_port PCIe port to read from 243210284Sjmallett * @param cfg_offset Address to read 244210284Sjmallett * 245210284Sjmallett * @return Value read 246210284Sjmallett */ 247210284Sjmallettuint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset); 248210284Sjmallett 249210284Sjmallett/** 250210284Sjmallett * Write a PCIe config space register indirectly. This is used for 251210284Sjmallett * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???. 252210284Sjmallett * 253210284Sjmallett * @param pcie_port PCIe port to write to 254210284Sjmallett * @param cfg_offset Address to write 255210284Sjmallett * @param val Value to write 256210284Sjmallett */ 257210284Sjmallettvoid cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, uint32_t val); 258210284Sjmallett 259210284Sjmallett/** 260210284Sjmallett * Write a 32bit value to the Octeon NPEI register space 261210284Sjmallett * 262210284Sjmallett * @param address Address to write to 263210284Sjmallett * @param val Value to write 264210284Sjmallett */ 265210284Sjmallettstatic inline void cvmx_pcie_npei_write32(uint64_t address, uint32_t val) 266210284Sjmallett{ 267210284Sjmallett cvmx_write64_uint32(address ^ 4, val); 268210284Sjmallett cvmx_read64_uint32(address ^ 4); 269210284Sjmallett} 270210284Sjmallett 271210284Sjmallett/** 272210284Sjmallett * Read a 32bit value from the Octeon NPEI register space 273210284Sjmallett * 274210284Sjmallett * @param address Address to read 275210284Sjmallett * @return The result 276210284Sjmallett */ 277210284Sjmallettstatic inline uint32_t cvmx_pcie_npei_read32(uint64_t address) 278210284Sjmallett{ 279210284Sjmallett return cvmx_read64_uint32(address ^ 4); 280210284Sjmallett} 281210284Sjmallett 282210284Sjmallett/** 283210284Sjmallett * Initialize a PCIe port for use in target(EP) mode. 284210284Sjmallett * 285210284Sjmallett * @return Zero on success 286210284Sjmallett */ 287210284Sjmallettint cvmx_pcie_ep_initialize(void); 288210284Sjmallett 289210284Sjmallett/** 290210284Sjmallett * Wait for posted PCIe read/writes to reach the other side of 291210284Sjmallett * the internal PCIe switch. This will insure that core 292210284Sjmallett * read/writes are posted before anything after this function 293210284Sjmallett * is called. This may be necessary when writing to memory that 294210284Sjmallett * will later be read using the DMA/PKT engines. 295210284Sjmallett * 296210284Sjmallett * @param pcie_port PCIe port to wait for 297210284Sjmallett */ 298210284Sjmallettvoid cvmx_pcie_wait_for_pending(int pcie_port); 299210284Sjmallett 300210284Sjmallett#ifdef __cplusplus 301210284Sjmallett} 302210284Sjmallett#endif 303210284Sjmallett 304210284Sjmallett#endif 305