1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pci-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon pci. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_PCI_DEFS_H__ 53232812Sjmallett#define __CVMX_PCI_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_PCI_BAR1_INDEXX(unsigned long offset) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) || 61215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) || 62215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) || 63215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31))))) 64215976Sjmallett cvmx_warn("CVMX_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset); 65215976Sjmallett return 0x0000000000000100ull + ((offset) & 31) * 4; 66215976Sjmallett} 67215976Sjmallett#else 68215976Sjmallett#define CVMX_PCI_BAR1_INDEXX(offset) (0x0000000000000100ull + ((offset) & 31) * 4) 69215976Sjmallett#endif 70215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71215976Sjmallett#define CVMX_PCI_BIST_REG CVMX_PCI_BIST_REG_FUNC() 72215976Sjmallettstatic inline uint64_t CVMX_PCI_BIST_REG_FUNC(void) 73215976Sjmallett{ 74215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN50XX))) 75215976Sjmallett cvmx_warn("CVMX_PCI_BIST_REG not supported on this chip\n"); 76215976Sjmallett return 0x00000000000001C0ull; 77215976Sjmallett} 78215976Sjmallett#else 79215976Sjmallett#define CVMX_PCI_BIST_REG (0x00000000000001C0ull) 80215976Sjmallett#endif 81215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82215976Sjmallett#define CVMX_PCI_CFG00 CVMX_PCI_CFG00_FUNC() 83215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG00_FUNC(void) 84215976Sjmallett{ 85215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 86215976Sjmallett cvmx_warn("CVMX_PCI_CFG00 not supported on this chip\n"); 87215976Sjmallett return 0x0000000000000000ull; 88215976Sjmallett} 89215976Sjmallett#else 90215976Sjmallett#define CVMX_PCI_CFG00 (0x0000000000000000ull) 91215976Sjmallett#endif 92215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 93215976Sjmallett#define CVMX_PCI_CFG01 CVMX_PCI_CFG01_FUNC() 94215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG01_FUNC(void) 95215976Sjmallett{ 96215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 97215976Sjmallett cvmx_warn("CVMX_PCI_CFG01 not supported on this chip\n"); 98215976Sjmallett return 0x0000000000000004ull; 99215976Sjmallett} 100215976Sjmallett#else 101215976Sjmallett#define CVMX_PCI_CFG01 (0x0000000000000004ull) 102215976Sjmallett#endif 103215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104215976Sjmallett#define CVMX_PCI_CFG02 CVMX_PCI_CFG02_FUNC() 105215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG02_FUNC(void) 106215976Sjmallett{ 107215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 108215976Sjmallett cvmx_warn("CVMX_PCI_CFG02 not supported on this chip\n"); 109215976Sjmallett return 0x0000000000000008ull; 110215976Sjmallett} 111215976Sjmallett#else 112215976Sjmallett#define CVMX_PCI_CFG02 (0x0000000000000008ull) 113215976Sjmallett#endif 114215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 115215976Sjmallett#define CVMX_PCI_CFG03 CVMX_PCI_CFG03_FUNC() 116215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG03_FUNC(void) 117215976Sjmallett{ 118215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 119215976Sjmallett cvmx_warn("CVMX_PCI_CFG03 not supported on this chip\n"); 120215976Sjmallett return 0x000000000000000Cull; 121215976Sjmallett} 122215976Sjmallett#else 123215976Sjmallett#define CVMX_PCI_CFG03 (0x000000000000000Cull) 124215976Sjmallett#endif 125215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 126215976Sjmallett#define CVMX_PCI_CFG04 CVMX_PCI_CFG04_FUNC() 127215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG04_FUNC(void) 128215976Sjmallett{ 129215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 130215976Sjmallett cvmx_warn("CVMX_PCI_CFG04 not supported on this chip\n"); 131215976Sjmallett return 0x0000000000000010ull; 132215976Sjmallett} 133215976Sjmallett#else 134215976Sjmallett#define CVMX_PCI_CFG04 (0x0000000000000010ull) 135215976Sjmallett#endif 136215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 137215976Sjmallett#define CVMX_PCI_CFG05 CVMX_PCI_CFG05_FUNC() 138215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG05_FUNC(void) 139215976Sjmallett{ 140215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 141215976Sjmallett cvmx_warn("CVMX_PCI_CFG05 not supported on this chip\n"); 142215976Sjmallett return 0x0000000000000014ull; 143215976Sjmallett} 144215976Sjmallett#else 145215976Sjmallett#define CVMX_PCI_CFG05 (0x0000000000000014ull) 146215976Sjmallett#endif 147215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 148215976Sjmallett#define CVMX_PCI_CFG06 CVMX_PCI_CFG06_FUNC() 149215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG06_FUNC(void) 150215976Sjmallett{ 151215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 152215976Sjmallett cvmx_warn("CVMX_PCI_CFG06 not supported on this chip\n"); 153215976Sjmallett return 0x0000000000000018ull; 154215976Sjmallett} 155215976Sjmallett#else 156215976Sjmallett#define CVMX_PCI_CFG06 (0x0000000000000018ull) 157215976Sjmallett#endif 158215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 159215976Sjmallett#define CVMX_PCI_CFG07 CVMX_PCI_CFG07_FUNC() 160215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG07_FUNC(void) 161215976Sjmallett{ 162215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 163215976Sjmallett cvmx_warn("CVMX_PCI_CFG07 not supported on this chip\n"); 164215976Sjmallett return 0x000000000000001Cull; 165215976Sjmallett} 166215976Sjmallett#else 167215976Sjmallett#define CVMX_PCI_CFG07 (0x000000000000001Cull) 168215976Sjmallett#endif 169215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 170215976Sjmallett#define CVMX_PCI_CFG08 CVMX_PCI_CFG08_FUNC() 171215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG08_FUNC(void) 172215976Sjmallett{ 173215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 174215976Sjmallett cvmx_warn("CVMX_PCI_CFG08 not supported on this chip\n"); 175215976Sjmallett return 0x0000000000000020ull; 176215976Sjmallett} 177215976Sjmallett#else 178215976Sjmallett#define CVMX_PCI_CFG08 (0x0000000000000020ull) 179215976Sjmallett#endif 180215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 181215976Sjmallett#define CVMX_PCI_CFG09 CVMX_PCI_CFG09_FUNC() 182215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG09_FUNC(void) 183215976Sjmallett{ 184215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 185215976Sjmallett cvmx_warn("CVMX_PCI_CFG09 not supported on this chip\n"); 186215976Sjmallett return 0x0000000000000024ull; 187215976Sjmallett} 188215976Sjmallett#else 189215976Sjmallett#define CVMX_PCI_CFG09 (0x0000000000000024ull) 190215976Sjmallett#endif 191215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 192215976Sjmallett#define CVMX_PCI_CFG10 CVMX_PCI_CFG10_FUNC() 193215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG10_FUNC(void) 194215976Sjmallett{ 195215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 196215976Sjmallett cvmx_warn("CVMX_PCI_CFG10 not supported on this chip\n"); 197215976Sjmallett return 0x0000000000000028ull; 198215976Sjmallett} 199215976Sjmallett#else 200215976Sjmallett#define CVMX_PCI_CFG10 (0x0000000000000028ull) 201215976Sjmallett#endif 202215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 203215976Sjmallett#define CVMX_PCI_CFG11 CVMX_PCI_CFG11_FUNC() 204215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG11_FUNC(void) 205215976Sjmallett{ 206215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 207215976Sjmallett cvmx_warn("CVMX_PCI_CFG11 not supported on this chip\n"); 208215976Sjmallett return 0x000000000000002Cull; 209215976Sjmallett} 210215976Sjmallett#else 211215976Sjmallett#define CVMX_PCI_CFG11 (0x000000000000002Cull) 212215976Sjmallett#endif 213215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 214215976Sjmallett#define CVMX_PCI_CFG12 CVMX_PCI_CFG12_FUNC() 215215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG12_FUNC(void) 216215976Sjmallett{ 217215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 218215976Sjmallett cvmx_warn("CVMX_PCI_CFG12 not supported on this chip\n"); 219215976Sjmallett return 0x0000000000000030ull; 220215976Sjmallett} 221215976Sjmallett#else 222215976Sjmallett#define CVMX_PCI_CFG12 (0x0000000000000030ull) 223215976Sjmallett#endif 224215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 225215976Sjmallett#define CVMX_PCI_CFG13 CVMX_PCI_CFG13_FUNC() 226215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG13_FUNC(void) 227215976Sjmallett{ 228215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 229215976Sjmallett cvmx_warn("CVMX_PCI_CFG13 not supported on this chip\n"); 230215976Sjmallett return 0x0000000000000034ull; 231215976Sjmallett} 232215976Sjmallett#else 233215976Sjmallett#define CVMX_PCI_CFG13 (0x0000000000000034ull) 234215976Sjmallett#endif 235215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236215976Sjmallett#define CVMX_PCI_CFG15 CVMX_PCI_CFG15_FUNC() 237215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG15_FUNC(void) 238215976Sjmallett{ 239215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 240215976Sjmallett cvmx_warn("CVMX_PCI_CFG15 not supported on this chip\n"); 241215976Sjmallett return 0x000000000000003Cull; 242215976Sjmallett} 243215976Sjmallett#else 244215976Sjmallett#define CVMX_PCI_CFG15 (0x000000000000003Cull) 245215976Sjmallett#endif 246215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 247215976Sjmallett#define CVMX_PCI_CFG16 CVMX_PCI_CFG16_FUNC() 248215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG16_FUNC(void) 249215976Sjmallett{ 250215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 251215976Sjmallett cvmx_warn("CVMX_PCI_CFG16 not supported on this chip\n"); 252215976Sjmallett return 0x0000000000000040ull; 253215976Sjmallett} 254215976Sjmallett#else 255215976Sjmallett#define CVMX_PCI_CFG16 (0x0000000000000040ull) 256215976Sjmallett#endif 257215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 258215976Sjmallett#define CVMX_PCI_CFG17 CVMX_PCI_CFG17_FUNC() 259215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG17_FUNC(void) 260215976Sjmallett{ 261215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 262215976Sjmallett cvmx_warn("CVMX_PCI_CFG17 not supported on this chip\n"); 263215976Sjmallett return 0x0000000000000044ull; 264215976Sjmallett} 265215976Sjmallett#else 266215976Sjmallett#define CVMX_PCI_CFG17 (0x0000000000000044ull) 267215976Sjmallett#endif 268215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 269215976Sjmallett#define CVMX_PCI_CFG18 CVMX_PCI_CFG18_FUNC() 270215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG18_FUNC(void) 271215976Sjmallett{ 272215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 273215976Sjmallett cvmx_warn("CVMX_PCI_CFG18 not supported on this chip\n"); 274215976Sjmallett return 0x0000000000000048ull; 275215976Sjmallett} 276215976Sjmallett#else 277215976Sjmallett#define CVMX_PCI_CFG18 (0x0000000000000048ull) 278215976Sjmallett#endif 279215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 280215976Sjmallett#define CVMX_PCI_CFG19 CVMX_PCI_CFG19_FUNC() 281215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG19_FUNC(void) 282215976Sjmallett{ 283215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 284215976Sjmallett cvmx_warn("CVMX_PCI_CFG19 not supported on this chip\n"); 285215976Sjmallett return 0x000000000000004Cull; 286215976Sjmallett} 287215976Sjmallett#else 288215976Sjmallett#define CVMX_PCI_CFG19 (0x000000000000004Cull) 289215976Sjmallett#endif 290215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 291215976Sjmallett#define CVMX_PCI_CFG20 CVMX_PCI_CFG20_FUNC() 292215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG20_FUNC(void) 293215976Sjmallett{ 294215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 295215976Sjmallett cvmx_warn("CVMX_PCI_CFG20 not supported on this chip\n"); 296215976Sjmallett return 0x0000000000000050ull; 297215976Sjmallett} 298215976Sjmallett#else 299215976Sjmallett#define CVMX_PCI_CFG20 (0x0000000000000050ull) 300215976Sjmallett#endif 301215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 302215976Sjmallett#define CVMX_PCI_CFG21 CVMX_PCI_CFG21_FUNC() 303215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG21_FUNC(void) 304215976Sjmallett{ 305215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 306215976Sjmallett cvmx_warn("CVMX_PCI_CFG21 not supported on this chip\n"); 307215976Sjmallett return 0x0000000000000054ull; 308215976Sjmallett} 309215976Sjmallett#else 310215976Sjmallett#define CVMX_PCI_CFG21 (0x0000000000000054ull) 311215976Sjmallett#endif 312215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 313215976Sjmallett#define CVMX_PCI_CFG22 CVMX_PCI_CFG22_FUNC() 314215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG22_FUNC(void) 315215976Sjmallett{ 316215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 317215976Sjmallett cvmx_warn("CVMX_PCI_CFG22 not supported on this chip\n"); 318215976Sjmallett return 0x0000000000000058ull; 319215976Sjmallett} 320215976Sjmallett#else 321215976Sjmallett#define CVMX_PCI_CFG22 (0x0000000000000058ull) 322215976Sjmallett#endif 323215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 324215976Sjmallett#define CVMX_PCI_CFG56 CVMX_PCI_CFG56_FUNC() 325215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG56_FUNC(void) 326215976Sjmallett{ 327215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 328215976Sjmallett cvmx_warn("CVMX_PCI_CFG56 not supported on this chip\n"); 329215976Sjmallett return 0x00000000000000E0ull; 330215976Sjmallett} 331215976Sjmallett#else 332215976Sjmallett#define CVMX_PCI_CFG56 (0x00000000000000E0ull) 333215976Sjmallett#endif 334215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 335215976Sjmallett#define CVMX_PCI_CFG57 CVMX_PCI_CFG57_FUNC() 336215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG57_FUNC(void) 337215976Sjmallett{ 338215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 339215976Sjmallett cvmx_warn("CVMX_PCI_CFG57 not supported on this chip\n"); 340215976Sjmallett return 0x00000000000000E4ull; 341215976Sjmallett} 342215976Sjmallett#else 343215976Sjmallett#define CVMX_PCI_CFG57 (0x00000000000000E4ull) 344215976Sjmallett#endif 345215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 346215976Sjmallett#define CVMX_PCI_CFG58 CVMX_PCI_CFG58_FUNC() 347215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG58_FUNC(void) 348215976Sjmallett{ 349215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 350215976Sjmallett cvmx_warn("CVMX_PCI_CFG58 not supported on this chip\n"); 351215976Sjmallett return 0x00000000000000E8ull; 352215976Sjmallett} 353215976Sjmallett#else 354215976Sjmallett#define CVMX_PCI_CFG58 (0x00000000000000E8ull) 355215976Sjmallett#endif 356215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 357215976Sjmallett#define CVMX_PCI_CFG59 CVMX_PCI_CFG59_FUNC() 358215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG59_FUNC(void) 359215976Sjmallett{ 360215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 361215976Sjmallett cvmx_warn("CVMX_PCI_CFG59 not supported on this chip\n"); 362215976Sjmallett return 0x00000000000000ECull; 363215976Sjmallett} 364215976Sjmallett#else 365215976Sjmallett#define CVMX_PCI_CFG59 (0x00000000000000ECull) 366215976Sjmallett#endif 367215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 368215976Sjmallett#define CVMX_PCI_CFG60 CVMX_PCI_CFG60_FUNC() 369215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG60_FUNC(void) 370215976Sjmallett{ 371215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 372215976Sjmallett cvmx_warn("CVMX_PCI_CFG60 not supported on this chip\n"); 373215976Sjmallett return 0x00000000000000F0ull; 374215976Sjmallett} 375215976Sjmallett#else 376215976Sjmallett#define CVMX_PCI_CFG60 (0x00000000000000F0ull) 377215976Sjmallett#endif 378215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 379215976Sjmallett#define CVMX_PCI_CFG61 CVMX_PCI_CFG61_FUNC() 380215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG61_FUNC(void) 381215976Sjmallett{ 382215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 383215976Sjmallett cvmx_warn("CVMX_PCI_CFG61 not supported on this chip\n"); 384215976Sjmallett return 0x00000000000000F4ull; 385215976Sjmallett} 386215976Sjmallett#else 387215976Sjmallett#define CVMX_PCI_CFG61 (0x00000000000000F4ull) 388215976Sjmallett#endif 389215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 390215976Sjmallett#define CVMX_PCI_CFG62 CVMX_PCI_CFG62_FUNC() 391215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG62_FUNC(void) 392215976Sjmallett{ 393215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 394215976Sjmallett cvmx_warn("CVMX_PCI_CFG62 not supported on this chip\n"); 395215976Sjmallett return 0x00000000000000F8ull; 396215976Sjmallett} 397215976Sjmallett#else 398215976Sjmallett#define CVMX_PCI_CFG62 (0x00000000000000F8ull) 399215976Sjmallett#endif 400215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 401215976Sjmallett#define CVMX_PCI_CFG63 CVMX_PCI_CFG63_FUNC() 402215976Sjmallettstatic inline uint64_t CVMX_PCI_CFG63_FUNC(void) 403215976Sjmallett{ 404215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 405215976Sjmallett cvmx_warn("CVMX_PCI_CFG63 not supported on this chip\n"); 406215976Sjmallett return 0x00000000000000FCull; 407215976Sjmallett} 408215976Sjmallett#else 409215976Sjmallett#define CVMX_PCI_CFG63 (0x00000000000000FCull) 410215976Sjmallett#endif 411215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 412215976Sjmallett#define CVMX_PCI_CNT_REG CVMX_PCI_CNT_REG_FUNC() 413215976Sjmallettstatic inline uint64_t CVMX_PCI_CNT_REG_FUNC(void) 414215976Sjmallett{ 415215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 416215976Sjmallett cvmx_warn("CVMX_PCI_CNT_REG not supported on this chip\n"); 417215976Sjmallett return 0x00000000000001B8ull; 418215976Sjmallett} 419215976Sjmallett#else 420215976Sjmallett#define CVMX_PCI_CNT_REG (0x00000000000001B8ull) 421215976Sjmallett#endif 422215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 423215976Sjmallett#define CVMX_PCI_CTL_STATUS_2 CVMX_PCI_CTL_STATUS_2_FUNC() 424215976Sjmallettstatic inline uint64_t CVMX_PCI_CTL_STATUS_2_FUNC(void) 425215976Sjmallett{ 426215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 427215976Sjmallett cvmx_warn("CVMX_PCI_CTL_STATUS_2 not supported on this chip\n"); 428215976Sjmallett return 0x000000000000018Cull; 429215976Sjmallett} 430215976Sjmallett#else 431215976Sjmallett#define CVMX_PCI_CTL_STATUS_2 (0x000000000000018Cull) 432215976Sjmallett#endif 433215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 434215976Sjmallettstatic inline uint64_t CVMX_PCI_DBELL_X(unsigned long offset) 435215976Sjmallett{ 436215976Sjmallett if (!( 437215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 438215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 439215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 440215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 441215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 442215976Sjmallett cvmx_warn("CVMX_PCI_DBELL_X(%lu) is invalid on this chip\n", offset); 443215976Sjmallett return 0x0000000000000080ull + ((offset) & 3) * 8; 444215976Sjmallett} 445215976Sjmallett#else 446215976Sjmallett#define CVMX_PCI_DBELL_X(offset) (0x0000000000000080ull + ((offset) & 3) * 8) 447215976Sjmallett#endif 448215976Sjmallett#define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0) 449215976Sjmallett#define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1) 450215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 451215976Sjmallettstatic inline uint64_t CVMX_PCI_DMA_CNTX(unsigned long offset) 452215976Sjmallett{ 453215976Sjmallett if (!( 454215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 455215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 456215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 457215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 458215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 459215976Sjmallett cvmx_warn("CVMX_PCI_DMA_CNTX(%lu) is invalid on this chip\n", offset); 460215976Sjmallett return 0x00000000000000A0ull + ((offset) & 1) * 8; 461215976Sjmallett} 462215976Sjmallett#else 463215976Sjmallett#define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8) 464215976Sjmallett#endif 465215976Sjmallett#define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0) 466215976Sjmallett#define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1) 467215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 468215976Sjmallettstatic inline uint64_t CVMX_PCI_DMA_INT_LEVX(unsigned long offset) 469215976Sjmallett{ 470215976Sjmallett if (!( 471215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 472215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 473215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 474215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 475215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 476215976Sjmallett cvmx_warn("CVMX_PCI_DMA_INT_LEVX(%lu) is invalid on this chip\n", offset); 477215976Sjmallett return 0x00000000000000A4ull + ((offset) & 1) * 8; 478215976Sjmallett} 479215976Sjmallett#else 480215976Sjmallett#define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8) 481215976Sjmallett#endif 482215976Sjmallett#define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0) 483215976Sjmallett#define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1) 484215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485215976Sjmallettstatic inline uint64_t CVMX_PCI_DMA_TIMEX(unsigned long offset) 486215976Sjmallett{ 487215976Sjmallett if (!( 488215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 489215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 490215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 491215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 492215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 493215976Sjmallett cvmx_warn("CVMX_PCI_DMA_TIMEX(%lu) is invalid on this chip\n", offset); 494215976Sjmallett return 0x00000000000000B0ull + ((offset) & 1) * 4; 495215976Sjmallett} 496215976Sjmallett#else 497215976Sjmallett#define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4) 498215976Sjmallett#endif 499215976Sjmallett#define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0) 500215976Sjmallett#define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1) 501215976Sjmallett#define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2) 502215976Sjmallett#define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3) 503215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 504215976Sjmallettstatic inline uint64_t CVMX_PCI_INSTR_COUNTX(unsigned long offset) 505215976Sjmallett{ 506215976Sjmallett if (!( 507215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 508215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 509215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 510215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 511215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 512215976Sjmallett cvmx_warn("CVMX_PCI_INSTR_COUNTX(%lu) is invalid on this chip\n", offset); 513215976Sjmallett return 0x0000000000000084ull + ((offset) & 3) * 8; 514215976Sjmallett} 515215976Sjmallett#else 516215976Sjmallett#define CVMX_PCI_INSTR_COUNTX(offset) (0x0000000000000084ull + ((offset) & 3) * 8) 517215976Sjmallett#endif 518215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 519215976Sjmallett#define CVMX_PCI_INT_ENB CVMX_PCI_INT_ENB_FUNC() 520215976Sjmallettstatic inline uint64_t CVMX_PCI_INT_ENB_FUNC(void) 521215976Sjmallett{ 522215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 523215976Sjmallett cvmx_warn("CVMX_PCI_INT_ENB not supported on this chip\n"); 524215976Sjmallett return 0x0000000000000038ull; 525215976Sjmallett} 526215976Sjmallett#else 527215976Sjmallett#define CVMX_PCI_INT_ENB (0x0000000000000038ull) 528215976Sjmallett#endif 529215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 530215976Sjmallett#define CVMX_PCI_INT_ENB2 CVMX_PCI_INT_ENB2_FUNC() 531215976Sjmallettstatic inline uint64_t CVMX_PCI_INT_ENB2_FUNC(void) 532215976Sjmallett{ 533215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 534215976Sjmallett cvmx_warn("CVMX_PCI_INT_ENB2 not supported on this chip\n"); 535215976Sjmallett return 0x00000000000001A0ull; 536215976Sjmallett} 537215976Sjmallett#else 538215976Sjmallett#define CVMX_PCI_INT_ENB2 (0x00000000000001A0ull) 539215976Sjmallett#endif 540215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 541215976Sjmallett#define CVMX_PCI_INT_SUM CVMX_PCI_INT_SUM_FUNC() 542215976Sjmallettstatic inline uint64_t CVMX_PCI_INT_SUM_FUNC(void) 543215976Sjmallett{ 544215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 545215976Sjmallett cvmx_warn("CVMX_PCI_INT_SUM not supported on this chip\n"); 546215976Sjmallett return 0x0000000000000030ull; 547215976Sjmallett} 548215976Sjmallett#else 549215976Sjmallett#define CVMX_PCI_INT_SUM (0x0000000000000030ull) 550215976Sjmallett#endif 551215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 552215976Sjmallett#define CVMX_PCI_INT_SUM2 CVMX_PCI_INT_SUM2_FUNC() 553215976Sjmallettstatic inline uint64_t CVMX_PCI_INT_SUM2_FUNC(void) 554215976Sjmallett{ 555215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 556215976Sjmallett cvmx_warn("CVMX_PCI_INT_SUM2 not supported on this chip\n"); 557215976Sjmallett return 0x0000000000000198ull; 558215976Sjmallett} 559215976Sjmallett#else 560215976Sjmallett#define CVMX_PCI_INT_SUM2 (0x0000000000000198ull) 561215976Sjmallett#endif 562215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 563215976Sjmallett#define CVMX_PCI_MSI_RCV CVMX_PCI_MSI_RCV_FUNC() 564215976Sjmallettstatic inline uint64_t CVMX_PCI_MSI_RCV_FUNC(void) 565215976Sjmallett{ 566215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 567215976Sjmallett cvmx_warn("CVMX_PCI_MSI_RCV not supported on this chip\n"); 568215976Sjmallett return 0x00000000000000F0ull; 569215976Sjmallett} 570215976Sjmallett#else 571215976Sjmallett#define CVMX_PCI_MSI_RCV (0x00000000000000F0ull) 572215976Sjmallett#endif 573215976Sjmallett#define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0) 574215976Sjmallett#define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1) 575215976Sjmallett#define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2) 576215976Sjmallett#define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3) 577215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 578215976Sjmallettstatic inline uint64_t CVMX_PCI_PKTS_SENTX(unsigned long offset) 579215976Sjmallett{ 580215976Sjmallett if (!( 581215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 582215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 583215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 584215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 585215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 586215976Sjmallett cvmx_warn("CVMX_PCI_PKTS_SENTX(%lu) is invalid on this chip\n", offset); 587215976Sjmallett return 0x0000000000000040ull + ((offset) & 3) * 16; 588215976Sjmallett} 589215976Sjmallett#else 590215976Sjmallett#define CVMX_PCI_PKTS_SENTX(offset) (0x0000000000000040ull + ((offset) & 3) * 16) 591215976Sjmallett#endif 592215976Sjmallett#define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0) 593215976Sjmallett#define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1) 594215976Sjmallett#define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2) 595215976Sjmallett#define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3) 596215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 597215976Sjmallettstatic inline uint64_t CVMX_PCI_PKTS_SENT_INT_LEVX(unsigned long offset) 598215976Sjmallett{ 599215976Sjmallett if (!( 600215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 601215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 602215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 603215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 604215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 605215976Sjmallett cvmx_warn("CVMX_PCI_PKTS_SENT_INT_LEVX(%lu) is invalid on this chip\n", offset); 606215976Sjmallett return 0x0000000000000048ull + ((offset) & 3) * 16; 607215976Sjmallett} 608215976Sjmallett#else 609215976Sjmallett#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) (0x0000000000000048ull + ((offset) & 3) * 16) 610215976Sjmallett#endif 611215976Sjmallett#define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0) 612215976Sjmallett#define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1) 613215976Sjmallett#define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2) 614215976Sjmallett#define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3) 615215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 616215976Sjmallettstatic inline uint64_t CVMX_PCI_PKTS_SENT_TIMEX(unsigned long offset) 617215976Sjmallett{ 618215976Sjmallett if (!( 619215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 620215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 621215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 622215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 623215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 624215976Sjmallett cvmx_warn("CVMX_PCI_PKTS_SENT_TIMEX(%lu) is invalid on this chip\n", offset); 625215976Sjmallett return 0x000000000000004Cull + ((offset) & 3) * 16; 626215976Sjmallett} 627215976Sjmallett#else 628215976Sjmallett#define CVMX_PCI_PKTS_SENT_TIMEX(offset) (0x000000000000004Cull + ((offset) & 3) * 16) 629215976Sjmallett#endif 630215976Sjmallett#define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0) 631215976Sjmallett#define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1) 632215976Sjmallett#define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2) 633215976Sjmallett#define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3) 634215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 635215976Sjmallettstatic inline uint64_t CVMX_PCI_PKT_CREDITSX(unsigned long offset) 636215976Sjmallett{ 637215976Sjmallett if (!( 638215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 639215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 640215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 641215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 642215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 643215976Sjmallett cvmx_warn("CVMX_PCI_PKT_CREDITSX(%lu) is invalid on this chip\n", offset); 644215976Sjmallett return 0x0000000000000044ull + ((offset) & 3) * 16; 645215976Sjmallett} 646215976Sjmallett#else 647215976Sjmallett#define CVMX_PCI_PKT_CREDITSX(offset) (0x0000000000000044ull + ((offset) & 3) * 16) 648215976Sjmallett#endif 649215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 650215976Sjmallett#define CVMX_PCI_READ_CMD_6 CVMX_PCI_READ_CMD_6_FUNC() 651215976Sjmallettstatic inline uint64_t CVMX_PCI_READ_CMD_6_FUNC(void) 652215976Sjmallett{ 653215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 654215976Sjmallett cvmx_warn("CVMX_PCI_READ_CMD_6 not supported on this chip\n"); 655215976Sjmallett return 0x0000000000000180ull; 656215976Sjmallett} 657215976Sjmallett#else 658215976Sjmallett#define CVMX_PCI_READ_CMD_6 (0x0000000000000180ull) 659215976Sjmallett#endif 660215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 661215976Sjmallett#define CVMX_PCI_READ_CMD_C CVMX_PCI_READ_CMD_C_FUNC() 662215976Sjmallettstatic inline uint64_t CVMX_PCI_READ_CMD_C_FUNC(void) 663215976Sjmallett{ 664215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 665215976Sjmallett cvmx_warn("CVMX_PCI_READ_CMD_C not supported on this chip\n"); 666215976Sjmallett return 0x0000000000000184ull; 667215976Sjmallett} 668215976Sjmallett#else 669215976Sjmallett#define CVMX_PCI_READ_CMD_C (0x0000000000000184ull) 670215976Sjmallett#endif 671215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 672215976Sjmallett#define CVMX_PCI_READ_CMD_E CVMX_PCI_READ_CMD_E_FUNC() 673215976Sjmallettstatic inline uint64_t CVMX_PCI_READ_CMD_E_FUNC(void) 674215976Sjmallett{ 675215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 676215976Sjmallett cvmx_warn("CVMX_PCI_READ_CMD_E not supported on this chip\n"); 677215976Sjmallett return 0x0000000000000188ull; 678215976Sjmallett} 679215976Sjmallett#else 680215976Sjmallett#define CVMX_PCI_READ_CMD_E (0x0000000000000188ull) 681215976Sjmallett#endif 682215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 683215976Sjmallett#define CVMX_PCI_READ_TIMEOUT CVMX_PCI_READ_TIMEOUT_FUNC() 684215976Sjmallettstatic inline uint64_t CVMX_PCI_READ_TIMEOUT_FUNC(void) 685215976Sjmallett{ 686215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 687215976Sjmallett cvmx_warn("CVMX_PCI_READ_TIMEOUT not supported on this chip\n"); 688215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000000B0ull); 689215976Sjmallett} 690215976Sjmallett#else 691215976Sjmallett#define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull)) 692215976Sjmallett#endif 693215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 694215976Sjmallett#define CVMX_PCI_SCM_REG CVMX_PCI_SCM_REG_FUNC() 695215976Sjmallettstatic inline uint64_t CVMX_PCI_SCM_REG_FUNC(void) 696215976Sjmallett{ 697215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 698215976Sjmallett cvmx_warn("CVMX_PCI_SCM_REG not supported on this chip\n"); 699215976Sjmallett return 0x00000000000001A8ull; 700215976Sjmallett} 701215976Sjmallett#else 702215976Sjmallett#define CVMX_PCI_SCM_REG (0x00000000000001A8ull) 703215976Sjmallett#endif 704215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 705215976Sjmallett#define CVMX_PCI_TSR_REG CVMX_PCI_TSR_REG_FUNC() 706215976Sjmallettstatic inline uint64_t CVMX_PCI_TSR_REG_FUNC(void) 707215976Sjmallett{ 708215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 709215976Sjmallett cvmx_warn("CVMX_PCI_TSR_REG not supported on this chip\n"); 710215976Sjmallett return 0x00000000000001B0ull; 711215976Sjmallett} 712215976Sjmallett#else 713215976Sjmallett#define CVMX_PCI_TSR_REG (0x00000000000001B0ull) 714215976Sjmallett#endif 715215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716215976Sjmallett#define CVMX_PCI_WIN_RD_ADDR CVMX_PCI_WIN_RD_ADDR_FUNC() 717215976Sjmallettstatic inline uint64_t CVMX_PCI_WIN_RD_ADDR_FUNC(void) 718215976Sjmallett{ 719215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 720215976Sjmallett cvmx_warn("CVMX_PCI_WIN_RD_ADDR not supported on this chip\n"); 721215976Sjmallett return 0x0000000000000008ull; 722215976Sjmallett} 723215976Sjmallett#else 724215976Sjmallett#define CVMX_PCI_WIN_RD_ADDR (0x0000000000000008ull) 725215976Sjmallett#endif 726215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 727215976Sjmallett#define CVMX_PCI_WIN_RD_DATA CVMX_PCI_WIN_RD_DATA_FUNC() 728215976Sjmallettstatic inline uint64_t CVMX_PCI_WIN_RD_DATA_FUNC(void) 729215976Sjmallett{ 730215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 731215976Sjmallett cvmx_warn("CVMX_PCI_WIN_RD_DATA not supported on this chip\n"); 732215976Sjmallett return 0x0000000000000020ull; 733215976Sjmallett} 734215976Sjmallett#else 735215976Sjmallett#define CVMX_PCI_WIN_RD_DATA (0x0000000000000020ull) 736215976Sjmallett#endif 737215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 738215976Sjmallett#define CVMX_PCI_WIN_WR_ADDR CVMX_PCI_WIN_WR_ADDR_FUNC() 739215976Sjmallettstatic inline uint64_t CVMX_PCI_WIN_WR_ADDR_FUNC(void) 740215976Sjmallett{ 741215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 742215976Sjmallett cvmx_warn("CVMX_PCI_WIN_WR_ADDR not supported on this chip\n"); 743215976Sjmallett return 0x0000000000000000ull; 744215976Sjmallett} 745215976Sjmallett#else 746215976Sjmallett#define CVMX_PCI_WIN_WR_ADDR (0x0000000000000000ull) 747215976Sjmallett#endif 748215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 749215976Sjmallett#define CVMX_PCI_WIN_WR_DATA CVMX_PCI_WIN_WR_DATA_FUNC() 750215976Sjmallettstatic inline uint64_t CVMX_PCI_WIN_WR_DATA_FUNC(void) 751215976Sjmallett{ 752215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 753215976Sjmallett cvmx_warn("CVMX_PCI_WIN_WR_DATA not supported on this chip\n"); 754215976Sjmallett return 0x0000000000000010ull; 755215976Sjmallett} 756215976Sjmallett#else 757215976Sjmallett#define CVMX_PCI_WIN_WR_DATA (0x0000000000000010ull) 758215976Sjmallett#endif 759215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 760215976Sjmallett#define CVMX_PCI_WIN_WR_MASK CVMX_PCI_WIN_WR_MASK_FUNC() 761215976Sjmallettstatic inline uint64_t CVMX_PCI_WIN_WR_MASK_FUNC(void) 762215976Sjmallett{ 763215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 764215976Sjmallett cvmx_warn("CVMX_PCI_WIN_WR_MASK not supported on this chip\n"); 765215976Sjmallett return 0x0000000000000018ull; 766215976Sjmallett} 767215976Sjmallett#else 768215976Sjmallett#define CVMX_PCI_WIN_WR_MASK (0x0000000000000018ull) 769215976Sjmallett#endif 770215976Sjmallett 771215976Sjmallett/** 772215976Sjmallett * cvmx_pci_bar1_index# 773215976Sjmallett * 774215976Sjmallett * PCI_BAR1_INDEXX = PCI IndexX Register 775215976Sjmallett * 776215976Sjmallett * Contains address index and control bits for access to memory ranges of Bar-1, 777215976Sjmallett * when PCI supplied address-bits [26:22] == X. 778215976Sjmallett */ 779232812Sjmallettunion cvmx_pci_bar1_indexx { 780215976Sjmallett uint32_t u32; 781232812Sjmallett struct cvmx_pci_bar1_indexx_s { 782232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 783215976Sjmallett uint32_t reserved_18_31 : 14; 784215976Sjmallett uint32_t addr_idx : 14; /**< Address bits [35:22] sent to L2C */ 785215976Sjmallett uint32_t ca : 1; /**< Set '1' when access is not to be cached in L2. */ 786215976Sjmallett uint32_t end_swp : 2; /**< Endian Swap Mode */ 787215976Sjmallett uint32_t addr_v : 1; /**< Set '1' when the selected address range is valid. */ 788215976Sjmallett#else 789215976Sjmallett uint32_t addr_v : 1; 790215976Sjmallett uint32_t end_swp : 2; 791215976Sjmallett uint32_t ca : 1; 792215976Sjmallett uint32_t addr_idx : 14; 793215976Sjmallett uint32_t reserved_18_31 : 14; 794215976Sjmallett#endif 795215976Sjmallett } s; 796215976Sjmallett struct cvmx_pci_bar1_indexx_s cn30xx; 797215976Sjmallett struct cvmx_pci_bar1_indexx_s cn31xx; 798215976Sjmallett struct cvmx_pci_bar1_indexx_s cn38xx; 799215976Sjmallett struct cvmx_pci_bar1_indexx_s cn38xxp2; 800215976Sjmallett struct cvmx_pci_bar1_indexx_s cn50xx; 801215976Sjmallett struct cvmx_pci_bar1_indexx_s cn58xx; 802215976Sjmallett struct cvmx_pci_bar1_indexx_s cn58xxp1; 803215976Sjmallett}; 804215976Sjmalletttypedef union cvmx_pci_bar1_indexx cvmx_pci_bar1_indexx_t; 805215976Sjmallett 806215976Sjmallett/** 807215976Sjmallett * cvmx_pci_bist_reg 808215976Sjmallett * 809215976Sjmallett * PCI_BIST_REG = PCI PNI BIST Status Register 810215976Sjmallett * 811215976Sjmallett * Contains the bist results for the PNI memories. 812215976Sjmallett */ 813232812Sjmallettunion cvmx_pci_bist_reg { 814215976Sjmallett uint64_t u64; 815232812Sjmallett struct cvmx_pci_bist_reg_s { 816232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 817215976Sjmallett uint64_t reserved_10_63 : 54; 818215976Sjmallett uint64_t rsp_bs : 1; /**< Bist Status For b12_rsp_fifo_bist 819215976Sjmallett The value of this register is available 100,000 820215976Sjmallett core clocks + 21,000 pclks after: 821215976Sjmallett Host Mode - deassertion of pci_rst_n 822215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 823215976Sjmallett uint64_t dma0_bs : 1; /**< Bist Status For dmao_count 824215976Sjmallett The value of this register is available 100,000 825215976Sjmallett core clocks + 21,000 pclks after: 826215976Sjmallett Host Mode - deassertion of pci_rst_n 827215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 828215976Sjmallett uint64_t cmd0_bs : 1; /**< Bist Status For npi_cmd0_pni_am0 829215976Sjmallett The value of this register is available 100,000 830215976Sjmallett core clocks + 21,000 pclks after: 831215976Sjmallett Host Mode - deassertion of pci_rst_n 832215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 833215976Sjmallett uint64_t cmd_bs : 1; /**< Bist Status For npi_cmd_pni_am1 834215976Sjmallett The value of this register is available 100,000 835215976Sjmallett core clocks + 21,000 pclks after: 836215976Sjmallett Host Mode - deassertion of pci_rst_n 837215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 838215976Sjmallett uint64_t csr2p_bs : 1; /**< Bist Status For npi_csr_2_pni_am 839215976Sjmallett The value of this register is available 100,000 840215976Sjmallett core clocks + 21,000 pclks after: 841215976Sjmallett Host Mode - deassertion of pci_rst_n 842215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 843215976Sjmallett uint64_t csrr_bs : 1; /**< Bist Status For npi_csr_rsp_2_pni_am 844215976Sjmallett The value of this register is available 100,000 845215976Sjmallett core clocks + 21,000 pclks after: 846215976Sjmallett Host Mode - deassertion of pci_rst_n 847215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 848215976Sjmallett uint64_t rsp2p_bs : 1; /**< Bist Status For npi_rsp_2_pni_am 849215976Sjmallett The value of this register is available 100,000 850215976Sjmallett core clocks + 21,000 pclks after: 851215976Sjmallett Host Mode - deassertion of pci_rst_n 852215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 853215976Sjmallett uint64_t csr2n_bs : 1; /**< Bist Status For pni_csr_2_npi_am 854215976Sjmallett The value of this register is available 100,000 855215976Sjmallett core clocks + 21,000 pclks after: 856215976Sjmallett Host Mode - deassertion of pci_rst_n 857215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 858215976Sjmallett uint64_t dat2n_bs : 1; /**< Bist Status For pni_data_2_npi_am 859215976Sjmallett The value of this register is available 100,000 860215976Sjmallett core clocks + 21,000 pclks after: 861215976Sjmallett Host Mode - deassertion of pci_rst_n 862215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 863215976Sjmallett uint64_t dbg2n_bs : 1; /**< Bist Status For pni_dbg_data_2_npi_am 864215976Sjmallett The value of this register is available 100,000 865215976Sjmallett core clocks + 21,000 pclks after: 866215976Sjmallett Host Mode - deassertion of pci_rst_n 867215976Sjmallett Non Host Mode - deassertion of pci_rst_n */ 868215976Sjmallett#else 869215976Sjmallett uint64_t dbg2n_bs : 1; 870215976Sjmallett uint64_t dat2n_bs : 1; 871215976Sjmallett uint64_t csr2n_bs : 1; 872215976Sjmallett uint64_t rsp2p_bs : 1; 873215976Sjmallett uint64_t csrr_bs : 1; 874215976Sjmallett uint64_t csr2p_bs : 1; 875215976Sjmallett uint64_t cmd_bs : 1; 876215976Sjmallett uint64_t cmd0_bs : 1; 877215976Sjmallett uint64_t dma0_bs : 1; 878215976Sjmallett uint64_t rsp_bs : 1; 879215976Sjmallett uint64_t reserved_10_63 : 54; 880215976Sjmallett#endif 881215976Sjmallett } s; 882215976Sjmallett struct cvmx_pci_bist_reg_s cn50xx; 883215976Sjmallett}; 884215976Sjmalletttypedef union cvmx_pci_bist_reg cvmx_pci_bist_reg_t; 885215976Sjmallett 886215976Sjmallett/** 887215976Sjmallett * cvmx_pci_cfg00 888215976Sjmallett * 889215976Sjmallett * Registers at address 0x1000 -> 0x17FF are PNI 890215976Sjmallett * Start at 0x100 into range 891215976Sjmallett * these are shifted by 2 to the left to make address 892215976Sjmallett * Registers at address 0x1800 -> 0x18FF are CFG 893215976Sjmallett * these are shifted by 2 to the left to make address 894215976Sjmallett * 895215976Sjmallett * PCI_CFG00 = First 32-bits of PCI config space (PCI Vendor + Device) 896215976Sjmallett * 897215976Sjmallett * This register contains the first 32-bits of the PCI config space registers 898215976Sjmallett */ 899232812Sjmallettunion cvmx_pci_cfg00 { 900215976Sjmallett uint32_t u32; 901232812Sjmallett struct cvmx_pci_cfg00_s { 902232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 903215976Sjmallett uint32_t devid : 16; /**< This is the device ID for OCTEON (90nm shhrink) */ 904215976Sjmallett uint32_t vendid : 16; /**< This is the Cavium's vendor ID */ 905215976Sjmallett#else 906215976Sjmallett uint32_t vendid : 16; 907215976Sjmallett uint32_t devid : 16; 908215976Sjmallett#endif 909215976Sjmallett } s; 910215976Sjmallett struct cvmx_pci_cfg00_s cn30xx; 911215976Sjmallett struct cvmx_pci_cfg00_s cn31xx; 912215976Sjmallett struct cvmx_pci_cfg00_s cn38xx; 913215976Sjmallett struct cvmx_pci_cfg00_s cn38xxp2; 914215976Sjmallett struct cvmx_pci_cfg00_s cn50xx; 915215976Sjmallett struct cvmx_pci_cfg00_s cn58xx; 916215976Sjmallett struct cvmx_pci_cfg00_s cn58xxp1; 917215976Sjmallett}; 918215976Sjmalletttypedef union cvmx_pci_cfg00 cvmx_pci_cfg00_t; 919215976Sjmallett 920215976Sjmallett/** 921215976Sjmallett * cvmx_pci_cfg01 922215976Sjmallett * 923215976Sjmallett * PCI_CFG01 = Second 32-bits of PCI config space (Command/Status Register) 924215976Sjmallett * 925215976Sjmallett */ 926232812Sjmallettunion cvmx_pci_cfg01 { 927215976Sjmallett uint32_t u32; 928232812Sjmallett struct cvmx_pci_cfg01_s { 929232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 930215976Sjmallett uint32_t dpe : 1; /**< Detected Parity Error */ 931215976Sjmallett uint32_t sse : 1; /**< Signaled System Error */ 932215976Sjmallett uint32_t rma : 1; /**< Received Master Abort */ 933215976Sjmallett uint32_t rta : 1; /**< Received Target Abort */ 934215976Sjmallett uint32_t sta : 1; /**< Signaled Target Abort */ 935215976Sjmallett uint32_t devt : 2; /**< DEVSEL# timing (for PCI only/for PCIX = don't care) */ 936215976Sjmallett uint32_t mdpe : 1; /**< Master Data Parity Error */ 937215976Sjmallett uint32_t fbb : 1; /**< Fast Back-to-Back Transactions Capable 938215976Sjmallett Mode Dependent (1 = PCI Mode / 0 = PCIX Mode) */ 939215976Sjmallett uint32_t reserved_22_22 : 1; 940215976Sjmallett uint32_t m66 : 1; /**< 66MHz Capable */ 941215976Sjmallett uint32_t cle : 1; /**< Capabilities List Enable */ 942215976Sjmallett uint32_t i_stat : 1; /**< When INTx# is asserted by OCTEON this bit will be set. 943215976Sjmallett When deasserted by OCTEON this bit will be cleared. */ 944215976Sjmallett uint32_t reserved_11_18 : 8; 945215976Sjmallett uint32_t i_dis : 1; /**< When asserted '1' disables the generation of INTx# 946215976Sjmallett by OCTEON. When disabled '0' allows assertion of INTx# 947215976Sjmallett by OCTEON. */ 948215976Sjmallett uint32_t fbbe : 1; /**< Fast Back to Back Transaction Enable */ 949215976Sjmallett uint32_t see : 1; /**< System Error Enable */ 950215976Sjmallett uint32_t ads : 1; /**< Address/Data Stepping 951215976Sjmallett NOTE: Octeon does NOT support address/data stepping. */ 952215976Sjmallett uint32_t pee : 1; /**< PERR# Enable */ 953215976Sjmallett uint32_t vps : 1; /**< VGA Palette Snooping */ 954215976Sjmallett uint32_t mwice : 1; /**< Memory Write & Invalidate Command Enable */ 955215976Sjmallett uint32_t scse : 1; /**< Special Cycle Snooping Enable */ 956215976Sjmallett uint32_t me : 1; /**< Master Enable 957215976Sjmallett Must be set for OCTEON to master a PCI/PCI-X 958215976Sjmallett transaction. This should always be set any time 959215976Sjmallett that OCTEON is connected to a PCI/PCI-X bus. */ 960215976Sjmallett uint32_t msae : 1; /**< Memory Space Access Enable 961215976Sjmallett Must be set to recieve a PCI/PCI-X memory space 962215976Sjmallett transaction. This must always be set any time that 963215976Sjmallett OCTEON is connected to a PCI/PCI-X bus. */ 964215976Sjmallett uint32_t isae : 1; /**< I/O Space Access Enable 965215976Sjmallett NOTE: For OCTEON, this bit MUST NEVER be set 966215976Sjmallett (it is read-only and OCTEON does not respond to I/O 967215976Sjmallett Space accesses). */ 968215976Sjmallett#else 969215976Sjmallett uint32_t isae : 1; 970215976Sjmallett uint32_t msae : 1; 971215976Sjmallett uint32_t me : 1; 972215976Sjmallett uint32_t scse : 1; 973215976Sjmallett uint32_t mwice : 1; 974215976Sjmallett uint32_t vps : 1; 975215976Sjmallett uint32_t pee : 1; 976215976Sjmallett uint32_t ads : 1; 977215976Sjmallett uint32_t see : 1; 978215976Sjmallett uint32_t fbbe : 1; 979215976Sjmallett uint32_t i_dis : 1; 980215976Sjmallett uint32_t reserved_11_18 : 8; 981215976Sjmallett uint32_t i_stat : 1; 982215976Sjmallett uint32_t cle : 1; 983215976Sjmallett uint32_t m66 : 1; 984215976Sjmallett uint32_t reserved_22_22 : 1; 985215976Sjmallett uint32_t fbb : 1; 986215976Sjmallett uint32_t mdpe : 1; 987215976Sjmallett uint32_t devt : 2; 988215976Sjmallett uint32_t sta : 1; 989215976Sjmallett uint32_t rta : 1; 990215976Sjmallett uint32_t rma : 1; 991215976Sjmallett uint32_t sse : 1; 992215976Sjmallett uint32_t dpe : 1; 993215976Sjmallett#endif 994215976Sjmallett } s; 995215976Sjmallett struct cvmx_pci_cfg01_s cn30xx; 996215976Sjmallett struct cvmx_pci_cfg01_s cn31xx; 997215976Sjmallett struct cvmx_pci_cfg01_s cn38xx; 998215976Sjmallett struct cvmx_pci_cfg01_s cn38xxp2; 999215976Sjmallett struct cvmx_pci_cfg01_s cn50xx; 1000215976Sjmallett struct cvmx_pci_cfg01_s cn58xx; 1001215976Sjmallett struct cvmx_pci_cfg01_s cn58xxp1; 1002215976Sjmallett}; 1003215976Sjmalletttypedef union cvmx_pci_cfg01 cvmx_pci_cfg01_t; 1004215976Sjmallett 1005215976Sjmallett/** 1006215976Sjmallett * cvmx_pci_cfg02 1007215976Sjmallett * 1008215976Sjmallett * PCI_CFG02 = Third 32-bits of PCI config space (Class Code / Revision ID) 1009215976Sjmallett * 1010215976Sjmallett */ 1011232812Sjmallettunion cvmx_pci_cfg02 { 1012215976Sjmallett uint32_t u32; 1013232812Sjmallett struct cvmx_pci_cfg02_s { 1014232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1015215976Sjmallett uint32_t cc : 24; /**< Class Code (Processor/MIPS) 1016215976Sjmallett (was 0x100000 in pass 1 and pass 2) */ 1017215976Sjmallett uint32_t rid : 8; /**< Revision ID 1018215976Sjmallett (0 in pass 1, 1 in pass 1.1, 8 in pass 2.0) */ 1019215976Sjmallett#else 1020215976Sjmallett uint32_t rid : 8; 1021215976Sjmallett uint32_t cc : 24; 1022215976Sjmallett#endif 1023215976Sjmallett } s; 1024215976Sjmallett struct cvmx_pci_cfg02_s cn30xx; 1025215976Sjmallett struct cvmx_pci_cfg02_s cn31xx; 1026215976Sjmallett struct cvmx_pci_cfg02_s cn38xx; 1027215976Sjmallett struct cvmx_pci_cfg02_s cn38xxp2; 1028215976Sjmallett struct cvmx_pci_cfg02_s cn50xx; 1029215976Sjmallett struct cvmx_pci_cfg02_s cn58xx; 1030215976Sjmallett struct cvmx_pci_cfg02_s cn58xxp1; 1031215976Sjmallett}; 1032215976Sjmalletttypedef union cvmx_pci_cfg02 cvmx_pci_cfg02_t; 1033215976Sjmallett 1034215976Sjmallett/** 1035215976Sjmallett * cvmx_pci_cfg03 1036215976Sjmallett * 1037215976Sjmallett * PCI_CFG03 = Fourth 32-bits of PCI config space (BIST, HEADER Type, Latency timer, line size) 1038215976Sjmallett * 1039215976Sjmallett */ 1040232812Sjmallettunion cvmx_pci_cfg03 { 1041215976Sjmallett uint32_t u32; 1042232812Sjmallett struct cvmx_pci_cfg03_s { 1043232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1044215976Sjmallett uint32_t bcap : 1; /**< BIST Capable */ 1045215976Sjmallett uint32_t brb : 1; /**< BIST Request/busy bit 1046215976Sjmallett Note: OCTEON does not support PCI BIST, therefore 1047215976Sjmallett this bit should remain zero. */ 1048215976Sjmallett uint32_t reserved_28_29 : 2; 1049215976Sjmallett uint32_t bcod : 4; /**< BIST Code */ 1050215976Sjmallett uint32_t ht : 8; /**< Header Type (Type 0) */ 1051215976Sjmallett uint32_t lt : 8; /**< Latency Timer 1052215976Sjmallett (0=PCI) (0=PCI) 1053215976Sjmallett (0x40=PCIX) (0x40=PCIX) */ 1054215976Sjmallett uint32_t cls : 8; /**< Cache Line Size */ 1055215976Sjmallett#else 1056215976Sjmallett uint32_t cls : 8; 1057215976Sjmallett uint32_t lt : 8; 1058215976Sjmallett uint32_t ht : 8; 1059215976Sjmallett uint32_t bcod : 4; 1060215976Sjmallett uint32_t reserved_28_29 : 2; 1061215976Sjmallett uint32_t brb : 1; 1062215976Sjmallett uint32_t bcap : 1; 1063215976Sjmallett#endif 1064215976Sjmallett } s; 1065215976Sjmallett struct cvmx_pci_cfg03_s cn30xx; 1066215976Sjmallett struct cvmx_pci_cfg03_s cn31xx; 1067215976Sjmallett struct cvmx_pci_cfg03_s cn38xx; 1068215976Sjmallett struct cvmx_pci_cfg03_s cn38xxp2; 1069215976Sjmallett struct cvmx_pci_cfg03_s cn50xx; 1070215976Sjmallett struct cvmx_pci_cfg03_s cn58xx; 1071215976Sjmallett struct cvmx_pci_cfg03_s cn58xxp1; 1072215976Sjmallett}; 1073215976Sjmalletttypedef union cvmx_pci_cfg03 cvmx_pci_cfg03_t; 1074215976Sjmallett 1075215976Sjmallett/** 1076215976Sjmallett * cvmx_pci_cfg04 1077215976Sjmallett * 1078215976Sjmallett * PCI_CFG04 = Fifth 32-bits of PCI config space (Base Address Register 0 - Low) 1079215976Sjmallett * 1080215976Sjmallett * Description: BAR0: 4KB 64-bit Prefetchable Memory Space 1081215976Sjmallett * [0]: 0 (Memory Space) 1082215976Sjmallett * [2:1]: 2 (64bit memory decoder) 1083215976Sjmallett * [3]: 1 (Prefetchable) 1084215976Sjmallett * [11:4]: RAZ (to imply 4KB space) 1085215976Sjmallett * [31:12]: RW (User may define base address) 1086215976Sjmallett */ 1087232812Sjmallettunion cvmx_pci_cfg04 { 1088215976Sjmallett uint32_t u32; 1089232812Sjmallett struct cvmx_pci_cfg04_s { 1090232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1091215976Sjmallett uint32_t lbase : 20; /**< Base Address[31:12] 1092215976Sjmallett Base Address[30:12] read as zero if 1093215976Sjmallett PCI_CTL_STATUS_2[BB0] is set (in pass 3+) */ 1094215976Sjmallett uint32_t lbasez : 8; /**< Base Address[11:4] (Read as Zero) */ 1095215976Sjmallett uint32_t pf : 1; /**< Prefetchable Space */ 1096215976Sjmallett uint32_t typ : 2; /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */ 1097215976Sjmallett uint32_t mspc : 1; /**< Memory Space Indicator */ 1098215976Sjmallett#else 1099215976Sjmallett uint32_t mspc : 1; 1100215976Sjmallett uint32_t typ : 2; 1101215976Sjmallett uint32_t pf : 1; 1102215976Sjmallett uint32_t lbasez : 8; 1103215976Sjmallett uint32_t lbase : 20; 1104215976Sjmallett#endif 1105215976Sjmallett } s; 1106215976Sjmallett struct cvmx_pci_cfg04_s cn30xx; 1107215976Sjmallett struct cvmx_pci_cfg04_s cn31xx; 1108215976Sjmallett struct cvmx_pci_cfg04_s cn38xx; 1109215976Sjmallett struct cvmx_pci_cfg04_s cn38xxp2; 1110215976Sjmallett struct cvmx_pci_cfg04_s cn50xx; 1111215976Sjmallett struct cvmx_pci_cfg04_s cn58xx; 1112215976Sjmallett struct cvmx_pci_cfg04_s cn58xxp1; 1113215976Sjmallett}; 1114215976Sjmalletttypedef union cvmx_pci_cfg04 cvmx_pci_cfg04_t; 1115215976Sjmallett 1116215976Sjmallett/** 1117215976Sjmallett * cvmx_pci_cfg05 1118215976Sjmallett * 1119215976Sjmallett * PCI_CFG05 = Sixth 32-bits of PCI config space (Base Address Register 0 - High) 1120215976Sjmallett * 1121215976Sjmallett */ 1122232812Sjmallettunion cvmx_pci_cfg05 { 1123215976Sjmallett uint32_t u32; 1124232812Sjmallett struct cvmx_pci_cfg05_s { 1125232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1126215976Sjmallett uint32_t hbase : 32; /**< Base Address[63:32] */ 1127215976Sjmallett#else 1128215976Sjmallett uint32_t hbase : 32; 1129215976Sjmallett#endif 1130215976Sjmallett } s; 1131215976Sjmallett struct cvmx_pci_cfg05_s cn30xx; 1132215976Sjmallett struct cvmx_pci_cfg05_s cn31xx; 1133215976Sjmallett struct cvmx_pci_cfg05_s cn38xx; 1134215976Sjmallett struct cvmx_pci_cfg05_s cn38xxp2; 1135215976Sjmallett struct cvmx_pci_cfg05_s cn50xx; 1136215976Sjmallett struct cvmx_pci_cfg05_s cn58xx; 1137215976Sjmallett struct cvmx_pci_cfg05_s cn58xxp1; 1138215976Sjmallett}; 1139215976Sjmalletttypedef union cvmx_pci_cfg05 cvmx_pci_cfg05_t; 1140215976Sjmallett 1141215976Sjmallett/** 1142215976Sjmallett * cvmx_pci_cfg06 1143215976Sjmallett * 1144215976Sjmallett * PCI_CFG06 = Seventh 32-bits of PCI config space (Base Address Register 1 - Low) 1145215976Sjmallett * 1146215976Sjmallett * Description: BAR1: 128MB 64-bit Prefetchable Memory Space 1147215976Sjmallett * [0]: 0 (Memory Space) 1148215976Sjmallett * [2:1]: 2 (64bit memory decoder) 1149215976Sjmallett * [3]: 1 (Prefetchable) 1150215976Sjmallett * [26:4]: RAZ (to imply 128MB space) 1151215976Sjmallett * [31:27]: RW (User may define base address) 1152215976Sjmallett */ 1153232812Sjmallettunion cvmx_pci_cfg06 { 1154215976Sjmallett uint32_t u32; 1155232812Sjmallett struct cvmx_pci_cfg06_s { 1156232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1157215976Sjmallett uint32_t lbase : 5; /**< Base Address[31:27] 1158215976Sjmallett In pass 3+: 1159215976Sjmallett Base Address[29:27] read as zero if 1160215976Sjmallett PCI_CTL_STATUS_2[BB1] is set 1161215976Sjmallett Base Address[30] reads as zero if 1162215976Sjmallett PCI_CTL_STATUS_2[BB1] is set and 1163215976Sjmallett PCI_CTL_STATUS_2[BB1_SIZE] is set */ 1164215976Sjmallett uint32_t lbasez : 23; /**< Base Address[26:4] (Read as Zero) */ 1165215976Sjmallett uint32_t pf : 1; /**< Prefetchable Space */ 1166215976Sjmallett uint32_t typ : 2; /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */ 1167215976Sjmallett uint32_t mspc : 1; /**< Memory Space Indicator */ 1168215976Sjmallett#else 1169215976Sjmallett uint32_t mspc : 1; 1170215976Sjmallett uint32_t typ : 2; 1171215976Sjmallett uint32_t pf : 1; 1172215976Sjmallett uint32_t lbasez : 23; 1173215976Sjmallett uint32_t lbase : 5; 1174215976Sjmallett#endif 1175215976Sjmallett } s; 1176215976Sjmallett struct cvmx_pci_cfg06_s cn30xx; 1177215976Sjmallett struct cvmx_pci_cfg06_s cn31xx; 1178215976Sjmallett struct cvmx_pci_cfg06_s cn38xx; 1179215976Sjmallett struct cvmx_pci_cfg06_s cn38xxp2; 1180215976Sjmallett struct cvmx_pci_cfg06_s cn50xx; 1181215976Sjmallett struct cvmx_pci_cfg06_s cn58xx; 1182215976Sjmallett struct cvmx_pci_cfg06_s cn58xxp1; 1183215976Sjmallett}; 1184215976Sjmalletttypedef union cvmx_pci_cfg06 cvmx_pci_cfg06_t; 1185215976Sjmallett 1186215976Sjmallett/** 1187215976Sjmallett * cvmx_pci_cfg07 1188215976Sjmallett * 1189215976Sjmallett * PCI_CFG07 = Eighth 32-bits of PCI config space (Base Address Register 1 - High) 1190215976Sjmallett * 1191215976Sjmallett */ 1192232812Sjmallettunion cvmx_pci_cfg07 { 1193215976Sjmallett uint32_t u32; 1194232812Sjmallett struct cvmx_pci_cfg07_s { 1195232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1196215976Sjmallett uint32_t hbase : 32; /**< Base Address[63:32] */ 1197215976Sjmallett#else 1198215976Sjmallett uint32_t hbase : 32; 1199215976Sjmallett#endif 1200215976Sjmallett } s; 1201215976Sjmallett struct cvmx_pci_cfg07_s cn30xx; 1202215976Sjmallett struct cvmx_pci_cfg07_s cn31xx; 1203215976Sjmallett struct cvmx_pci_cfg07_s cn38xx; 1204215976Sjmallett struct cvmx_pci_cfg07_s cn38xxp2; 1205215976Sjmallett struct cvmx_pci_cfg07_s cn50xx; 1206215976Sjmallett struct cvmx_pci_cfg07_s cn58xx; 1207215976Sjmallett struct cvmx_pci_cfg07_s cn58xxp1; 1208215976Sjmallett}; 1209215976Sjmalletttypedef union cvmx_pci_cfg07 cvmx_pci_cfg07_t; 1210215976Sjmallett 1211215976Sjmallett/** 1212215976Sjmallett * cvmx_pci_cfg08 1213215976Sjmallett * 1214215976Sjmallett * PCI_CFG08 = Ninth 32-bits of PCI config space (Base Address Register 2 - Low) 1215215976Sjmallett * 1216215976Sjmallett * Description: BAR1: 2^39 (512GB) 64-bit Prefetchable Memory Space 1217215976Sjmallett * [0]: 0 (Memory Space) 1218215976Sjmallett * [2:1]: 2 (64bit memory decoder) 1219215976Sjmallett * [3]: 1 (Prefetchable) 1220215976Sjmallett * [31:4]: RAZ 1221215976Sjmallett */ 1222232812Sjmallettunion cvmx_pci_cfg08 { 1223215976Sjmallett uint32_t u32; 1224232812Sjmallett struct cvmx_pci_cfg08_s { 1225232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1226215976Sjmallett uint32_t lbasez : 28; /**< Base Address[31:4] (Read as Zero) */ 1227215976Sjmallett uint32_t pf : 1; /**< Prefetchable Space */ 1228215976Sjmallett uint32_t typ : 2; /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */ 1229215976Sjmallett uint32_t mspc : 1; /**< Memory Space Indicator */ 1230215976Sjmallett#else 1231215976Sjmallett uint32_t mspc : 1; 1232215976Sjmallett uint32_t typ : 2; 1233215976Sjmallett uint32_t pf : 1; 1234215976Sjmallett uint32_t lbasez : 28; 1235215976Sjmallett#endif 1236215976Sjmallett } s; 1237215976Sjmallett struct cvmx_pci_cfg08_s cn30xx; 1238215976Sjmallett struct cvmx_pci_cfg08_s cn31xx; 1239215976Sjmallett struct cvmx_pci_cfg08_s cn38xx; 1240215976Sjmallett struct cvmx_pci_cfg08_s cn38xxp2; 1241215976Sjmallett struct cvmx_pci_cfg08_s cn50xx; 1242215976Sjmallett struct cvmx_pci_cfg08_s cn58xx; 1243215976Sjmallett struct cvmx_pci_cfg08_s cn58xxp1; 1244215976Sjmallett}; 1245215976Sjmalletttypedef union cvmx_pci_cfg08 cvmx_pci_cfg08_t; 1246215976Sjmallett 1247215976Sjmallett/** 1248215976Sjmallett * cvmx_pci_cfg09 1249215976Sjmallett * 1250215976Sjmallett * PCI_CFG09 = Tenth 32-bits of PCI config space (Base Address Register 2 - High) 1251215976Sjmallett * 1252215976Sjmallett */ 1253232812Sjmallettunion cvmx_pci_cfg09 { 1254215976Sjmallett uint32_t u32; 1255232812Sjmallett struct cvmx_pci_cfg09_s { 1256232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1257215976Sjmallett uint32_t hbase : 25; /**< Base Address[63:39] */ 1258215976Sjmallett uint32_t hbasez : 7; /**< Base Address[38:31] (Read as Zero) */ 1259215976Sjmallett#else 1260215976Sjmallett uint32_t hbasez : 7; 1261215976Sjmallett uint32_t hbase : 25; 1262215976Sjmallett#endif 1263215976Sjmallett } s; 1264215976Sjmallett struct cvmx_pci_cfg09_s cn30xx; 1265215976Sjmallett struct cvmx_pci_cfg09_s cn31xx; 1266215976Sjmallett struct cvmx_pci_cfg09_s cn38xx; 1267215976Sjmallett struct cvmx_pci_cfg09_s cn38xxp2; 1268215976Sjmallett struct cvmx_pci_cfg09_s cn50xx; 1269215976Sjmallett struct cvmx_pci_cfg09_s cn58xx; 1270215976Sjmallett struct cvmx_pci_cfg09_s cn58xxp1; 1271215976Sjmallett}; 1272215976Sjmalletttypedef union cvmx_pci_cfg09 cvmx_pci_cfg09_t; 1273215976Sjmallett 1274215976Sjmallett/** 1275215976Sjmallett * cvmx_pci_cfg10 1276215976Sjmallett * 1277215976Sjmallett * PCI_CFG10 = Eleventh 32-bits of PCI config space (Card Bus CIS Pointer) 1278215976Sjmallett * 1279215976Sjmallett */ 1280232812Sjmallettunion cvmx_pci_cfg10 { 1281215976Sjmallett uint32_t u32; 1282232812Sjmallett struct cvmx_pci_cfg10_s { 1283232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1284215976Sjmallett uint32_t cisp : 32; /**< CardBus CIS Pointer (UNUSED) */ 1285215976Sjmallett#else 1286215976Sjmallett uint32_t cisp : 32; 1287215976Sjmallett#endif 1288215976Sjmallett } s; 1289215976Sjmallett struct cvmx_pci_cfg10_s cn30xx; 1290215976Sjmallett struct cvmx_pci_cfg10_s cn31xx; 1291215976Sjmallett struct cvmx_pci_cfg10_s cn38xx; 1292215976Sjmallett struct cvmx_pci_cfg10_s cn38xxp2; 1293215976Sjmallett struct cvmx_pci_cfg10_s cn50xx; 1294215976Sjmallett struct cvmx_pci_cfg10_s cn58xx; 1295215976Sjmallett struct cvmx_pci_cfg10_s cn58xxp1; 1296215976Sjmallett}; 1297215976Sjmalletttypedef union cvmx_pci_cfg10 cvmx_pci_cfg10_t; 1298215976Sjmallett 1299215976Sjmallett/** 1300215976Sjmallett * cvmx_pci_cfg11 1301215976Sjmallett * 1302215976Sjmallett * PCI_CFG11 = Twelfth 32-bits of PCI config space (SubSystem ID/Subsystem Vendor ID Register) 1303215976Sjmallett * 1304215976Sjmallett */ 1305232812Sjmallettunion cvmx_pci_cfg11 { 1306215976Sjmallett uint32_t u32; 1307232812Sjmallett struct cvmx_pci_cfg11_s { 1308232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1309215976Sjmallett uint32_t ssid : 16; /**< SubSystem ID */ 1310215976Sjmallett uint32_t ssvid : 16; /**< Subsystem Vendor ID */ 1311215976Sjmallett#else 1312215976Sjmallett uint32_t ssvid : 16; 1313215976Sjmallett uint32_t ssid : 16; 1314215976Sjmallett#endif 1315215976Sjmallett } s; 1316215976Sjmallett struct cvmx_pci_cfg11_s cn30xx; 1317215976Sjmallett struct cvmx_pci_cfg11_s cn31xx; 1318215976Sjmallett struct cvmx_pci_cfg11_s cn38xx; 1319215976Sjmallett struct cvmx_pci_cfg11_s cn38xxp2; 1320215976Sjmallett struct cvmx_pci_cfg11_s cn50xx; 1321215976Sjmallett struct cvmx_pci_cfg11_s cn58xx; 1322215976Sjmallett struct cvmx_pci_cfg11_s cn58xxp1; 1323215976Sjmallett}; 1324215976Sjmalletttypedef union cvmx_pci_cfg11 cvmx_pci_cfg11_t; 1325215976Sjmallett 1326215976Sjmallett/** 1327215976Sjmallett * cvmx_pci_cfg12 1328215976Sjmallett * 1329215976Sjmallett * PCI_CFG12 = Thirteenth 32-bits of PCI config space (Expansion ROM Base Address Register) 1330215976Sjmallett * 1331215976Sjmallett */ 1332232812Sjmallettunion cvmx_pci_cfg12 { 1333215976Sjmallett uint32_t u32; 1334232812Sjmallett struct cvmx_pci_cfg12_s { 1335232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1336215976Sjmallett uint32_t erbar : 16; /**< Expansion ROM Base Address[31:16] 64KB in size */ 1337215976Sjmallett uint32_t erbarz : 5; /**< Expansion ROM Base Base Address (Read as Zero) */ 1338215976Sjmallett uint32_t reserved_1_10 : 10; 1339215976Sjmallett uint32_t erbar_en : 1; /**< Expansion ROM Address Decode Enable */ 1340215976Sjmallett#else 1341215976Sjmallett uint32_t erbar_en : 1; 1342215976Sjmallett uint32_t reserved_1_10 : 10; 1343215976Sjmallett uint32_t erbarz : 5; 1344215976Sjmallett uint32_t erbar : 16; 1345215976Sjmallett#endif 1346215976Sjmallett } s; 1347215976Sjmallett struct cvmx_pci_cfg12_s cn30xx; 1348215976Sjmallett struct cvmx_pci_cfg12_s cn31xx; 1349215976Sjmallett struct cvmx_pci_cfg12_s cn38xx; 1350215976Sjmallett struct cvmx_pci_cfg12_s cn38xxp2; 1351215976Sjmallett struct cvmx_pci_cfg12_s cn50xx; 1352215976Sjmallett struct cvmx_pci_cfg12_s cn58xx; 1353215976Sjmallett struct cvmx_pci_cfg12_s cn58xxp1; 1354215976Sjmallett}; 1355215976Sjmalletttypedef union cvmx_pci_cfg12 cvmx_pci_cfg12_t; 1356215976Sjmallett 1357215976Sjmallett/** 1358215976Sjmallett * cvmx_pci_cfg13 1359215976Sjmallett * 1360215976Sjmallett * PCI_CFG13 = Fourteenth 32-bits of PCI config space (Capabilities Pointer Register) 1361215976Sjmallett * 1362215976Sjmallett */ 1363232812Sjmallettunion cvmx_pci_cfg13 { 1364215976Sjmallett uint32_t u32; 1365232812Sjmallett struct cvmx_pci_cfg13_s { 1366232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1367215976Sjmallett uint32_t reserved_8_31 : 24; 1368215976Sjmallett uint32_t cp : 8; /**< Capabilities Pointer */ 1369215976Sjmallett#else 1370215976Sjmallett uint32_t cp : 8; 1371215976Sjmallett uint32_t reserved_8_31 : 24; 1372215976Sjmallett#endif 1373215976Sjmallett } s; 1374215976Sjmallett struct cvmx_pci_cfg13_s cn30xx; 1375215976Sjmallett struct cvmx_pci_cfg13_s cn31xx; 1376215976Sjmallett struct cvmx_pci_cfg13_s cn38xx; 1377215976Sjmallett struct cvmx_pci_cfg13_s cn38xxp2; 1378215976Sjmallett struct cvmx_pci_cfg13_s cn50xx; 1379215976Sjmallett struct cvmx_pci_cfg13_s cn58xx; 1380215976Sjmallett struct cvmx_pci_cfg13_s cn58xxp1; 1381215976Sjmallett}; 1382215976Sjmalletttypedef union cvmx_pci_cfg13 cvmx_pci_cfg13_t; 1383215976Sjmallett 1384215976Sjmallett/** 1385215976Sjmallett * cvmx_pci_cfg15 1386215976Sjmallett * 1387215976Sjmallett * PCI_CFG15 = Sixteenth 32-bits of PCI config space (INT/ARB/LATENCY Register) 1388215976Sjmallett * 1389215976Sjmallett */ 1390232812Sjmallettunion cvmx_pci_cfg15 { 1391215976Sjmallett uint32_t u32; 1392232812Sjmallett struct cvmx_pci_cfg15_s { 1393232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1394215976Sjmallett uint32_t ml : 8; /**< Maximum Latency */ 1395215976Sjmallett uint32_t mg : 8; /**< Minimum Grant */ 1396215976Sjmallett uint32_t inta : 8; /**< Interrupt Pin (INTA#) */ 1397215976Sjmallett uint32_t il : 8; /**< Interrupt Line */ 1398215976Sjmallett#else 1399215976Sjmallett uint32_t il : 8; 1400215976Sjmallett uint32_t inta : 8; 1401215976Sjmallett uint32_t mg : 8; 1402215976Sjmallett uint32_t ml : 8; 1403215976Sjmallett#endif 1404215976Sjmallett } s; 1405215976Sjmallett struct cvmx_pci_cfg15_s cn30xx; 1406215976Sjmallett struct cvmx_pci_cfg15_s cn31xx; 1407215976Sjmallett struct cvmx_pci_cfg15_s cn38xx; 1408215976Sjmallett struct cvmx_pci_cfg15_s cn38xxp2; 1409215976Sjmallett struct cvmx_pci_cfg15_s cn50xx; 1410215976Sjmallett struct cvmx_pci_cfg15_s cn58xx; 1411215976Sjmallett struct cvmx_pci_cfg15_s cn58xxp1; 1412215976Sjmallett}; 1413215976Sjmalletttypedef union cvmx_pci_cfg15 cvmx_pci_cfg15_t; 1414215976Sjmallett 1415215976Sjmallett/** 1416215976Sjmallett * cvmx_pci_cfg16 1417215976Sjmallett * 1418215976Sjmallett * PCI_CFG16 = Seventeenth 32-bits of PCI config space (Target Implementation Register) 1419215976Sjmallett * 1420215976Sjmallett */ 1421232812Sjmallettunion cvmx_pci_cfg16 { 1422215976Sjmallett uint32_t u32; 1423232812Sjmallett struct cvmx_pci_cfg16_s { 1424232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1425215976Sjmallett uint32_t trdnpr : 1; /**< Target Read Delayed Transaction for I/O and 1426215976Sjmallett non-prefetchable regions discarded. */ 1427215976Sjmallett uint32_t trdard : 1; /**< Target Read Delayed Transaction for all regions 1428215976Sjmallett discarded. */ 1429215976Sjmallett uint32_t rdsati : 1; /**< Target(I/O and Memory) Read Delayed/Split at 1430215976Sjmallett timeout/immediately (default timeout). 1431215976Sjmallett Note: OCTEON requires that this bit MBZ(must be zero). */ 1432215976Sjmallett uint32_t trdrs : 1; /**< Target(I/O and Memory) Read Delayed/Split or Retry 1433215976Sjmallett select (of the application interface is not ready) 1434215976Sjmallett 0 = Delayed Split Transaction 1435215976Sjmallett 1 = Retry Transaction (always Immediate Retry, no 1436215976Sjmallett AT_REQ to application). */ 1437215976Sjmallett uint32_t trtae : 1; /**< Target(I/O and Memory) Read Target Abort Enable 1438215976Sjmallett (if application interface is not ready at the 1439215976Sjmallett latency timeout). 1440215976Sjmallett Note: OCTEON as target will never target-abort, 1441215976Sjmallett therefore this bit should never be set. */ 1442215976Sjmallett uint32_t twsei : 1; /**< Target(I/O) Write Split Enable (at timeout / 1443215976Sjmallett immediately; default timeout) */ 1444215976Sjmallett uint32_t twsen : 1; /**< T(I/O) write split Enable (if the application 1445215976Sjmallett interface is not ready) */ 1446215976Sjmallett uint32_t twtae : 1; /**< Target(I/O and Memory) Write Target Abort Enable 1447215976Sjmallett (if the application interface is not ready at the 1448215976Sjmallett start of the cycle). 1449215976Sjmallett Note: OCTEON as target will never target-abort, 1450215976Sjmallett therefore this bit should never be set. */ 1451215976Sjmallett uint32_t tmae : 1; /**< Target(Read/Write) Master Abort Enable; check 1452215976Sjmallett at the start of each transaction. 1453215976Sjmallett Note: This bit can be used to force a Master 1454215976Sjmallett Abort when OCTEON is acting as the intended target 1455215976Sjmallett device. */ 1456215976Sjmallett uint32_t tslte : 3; /**< Target Subsequent(2nd-last) Latency Timeout Enable 1457215976Sjmallett Valid range: [1..7] and 0=8. */ 1458215976Sjmallett uint32_t tilt : 4; /**< Target Initial(1st data) Latency Timeout in PCI 1459215976Sjmallett ModeValid range: [8..15] and 0=16. */ 1460215976Sjmallett uint32_t pbe : 12; /**< Programmable Boundary Enable to disconnect/prefetch 1461215976Sjmallett for target burst read cycles to prefetchable 1462215976Sjmallett region in PCI. A value of 1 indicates end of 1463215976Sjmallett boundary (64 KB down to 16 Bytes). */ 1464215976Sjmallett uint32_t dppmr : 1; /**< Disconnect/Prefetch to prefetchable memory 1465215976Sjmallett regions Enable. Prefetchable memory regions 1466215976Sjmallett are always disconnected on a region boundary. 1467215976Sjmallett Non-prefetchable regions for PCI are always 1468215976Sjmallett disconnected on the first transfer. 1469215976Sjmallett Note: OCTEON as target will never target-disconnect, 1470215976Sjmallett therefore this bit should never be set. */ 1471215976Sjmallett uint32_t reserved_2_2 : 1; 1472215976Sjmallett uint32_t tswc : 1; /**< Target Split Write Control 1473215976Sjmallett 0 = Blocks all requests except PMW 1474215976Sjmallett 1 = Blocks all requests including PMW until 1475215976Sjmallett split completion occurs. */ 1476215976Sjmallett uint32_t mltd : 1; /**< Master Latency Timer Disable 1477215976Sjmallett Note: For OCTEON, it is recommended that this bit 1478215976Sjmallett be set(to disable the Master Latency timer). */ 1479215976Sjmallett#else 1480215976Sjmallett uint32_t mltd : 1; 1481215976Sjmallett uint32_t tswc : 1; 1482215976Sjmallett uint32_t reserved_2_2 : 1; 1483215976Sjmallett uint32_t dppmr : 1; 1484215976Sjmallett uint32_t pbe : 12; 1485215976Sjmallett uint32_t tilt : 4; 1486215976Sjmallett uint32_t tslte : 3; 1487215976Sjmallett uint32_t tmae : 1; 1488215976Sjmallett uint32_t twtae : 1; 1489215976Sjmallett uint32_t twsen : 1; 1490215976Sjmallett uint32_t twsei : 1; 1491215976Sjmallett uint32_t trtae : 1; 1492215976Sjmallett uint32_t trdrs : 1; 1493215976Sjmallett uint32_t rdsati : 1; 1494215976Sjmallett uint32_t trdard : 1; 1495215976Sjmallett uint32_t trdnpr : 1; 1496215976Sjmallett#endif 1497215976Sjmallett } s; 1498215976Sjmallett struct cvmx_pci_cfg16_s cn30xx; 1499215976Sjmallett struct cvmx_pci_cfg16_s cn31xx; 1500215976Sjmallett struct cvmx_pci_cfg16_s cn38xx; 1501215976Sjmallett struct cvmx_pci_cfg16_s cn38xxp2; 1502215976Sjmallett struct cvmx_pci_cfg16_s cn50xx; 1503215976Sjmallett struct cvmx_pci_cfg16_s cn58xx; 1504215976Sjmallett struct cvmx_pci_cfg16_s cn58xxp1; 1505215976Sjmallett}; 1506215976Sjmalletttypedef union cvmx_pci_cfg16 cvmx_pci_cfg16_t; 1507215976Sjmallett 1508215976Sjmallett/** 1509215976Sjmallett * cvmx_pci_cfg17 1510215976Sjmallett * 1511215976Sjmallett * PCI_CFG17 = Eighteenth 32-bits of PCI config space (Target Split Completion Message 1512215976Sjmallett * Enable Register) 1513215976Sjmallett */ 1514232812Sjmallettunion cvmx_pci_cfg17 { 1515215976Sjmallett uint32_t u32; 1516232812Sjmallett struct cvmx_pci_cfg17_s { 1517232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1518215976Sjmallett uint32_t tscme : 32; /**< Target Split Completion Message Enable 1519215976Sjmallett [31:30]: 00 1520215976Sjmallett [29]: Split Completion Error Indication 1521215976Sjmallett [28]: 0 1522215976Sjmallett [27:20]: Split Completion Message Index 1523215976Sjmallett [19:0]: 0x00000 1524215976Sjmallett For OCTEON, this register is intended for debug use 1525215976Sjmallett only. (as such, it is recommended NOT to be written 1526215976Sjmallett with anything other than ZEROES). */ 1527215976Sjmallett#else 1528215976Sjmallett uint32_t tscme : 32; 1529215976Sjmallett#endif 1530215976Sjmallett } s; 1531215976Sjmallett struct cvmx_pci_cfg17_s cn30xx; 1532215976Sjmallett struct cvmx_pci_cfg17_s cn31xx; 1533215976Sjmallett struct cvmx_pci_cfg17_s cn38xx; 1534215976Sjmallett struct cvmx_pci_cfg17_s cn38xxp2; 1535215976Sjmallett struct cvmx_pci_cfg17_s cn50xx; 1536215976Sjmallett struct cvmx_pci_cfg17_s cn58xx; 1537215976Sjmallett struct cvmx_pci_cfg17_s cn58xxp1; 1538215976Sjmallett}; 1539215976Sjmalletttypedef union cvmx_pci_cfg17 cvmx_pci_cfg17_t; 1540215976Sjmallett 1541215976Sjmallett/** 1542215976Sjmallett * cvmx_pci_cfg18 1543215976Sjmallett * 1544215976Sjmallett * PCI_CFG18 = Nineteenth 32-bits of PCI config space (Target Delayed/Split Request 1545215976Sjmallett * Pending Sequences) 1546215976Sjmallett */ 1547232812Sjmallettunion cvmx_pci_cfg18 { 1548215976Sjmallett uint32_t u32; 1549232812Sjmallett struct cvmx_pci_cfg18_s { 1550232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1551215976Sjmallett uint32_t tdsrps : 32; /**< Target Delayed/Split Request Pending Sequences 1552215976Sjmallett The application uses this address to remove a 1553215976Sjmallett pending split sequence from the target queue by 1554215976Sjmallett clearing the appropriate bit. Example: Clearing [14] 1555215976Sjmallett clears the pending sequence \#14. An application 1556215976Sjmallett or configuration write to this address can clear this 1557215976Sjmallett register. 1558215976Sjmallett For OCTEON, this register is intended for debug use 1559215976Sjmallett only and MUST NEVER be written with anything other 1560215976Sjmallett than ZEROES. */ 1561215976Sjmallett#else 1562215976Sjmallett uint32_t tdsrps : 32; 1563215976Sjmallett#endif 1564215976Sjmallett } s; 1565215976Sjmallett struct cvmx_pci_cfg18_s cn30xx; 1566215976Sjmallett struct cvmx_pci_cfg18_s cn31xx; 1567215976Sjmallett struct cvmx_pci_cfg18_s cn38xx; 1568215976Sjmallett struct cvmx_pci_cfg18_s cn38xxp2; 1569215976Sjmallett struct cvmx_pci_cfg18_s cn50xx; 1570215976Sjmallett struct cvmx_pci_cfg18_s cn58xx; 1571215976Sjmallett struct cvmx_pci_cfg18_s cn58xxp1; 1572215976Sjmallett}; 1573215976Sjmalletttypedef union cvmx_pci_cfg18 cvmx_pci_cfg18_t; 1574215976Sjmallett 1575215976Sjmallett/** 1576215976Sjmallett * cvmx_pci_cfg19 1577215976Sjmallett * 1578215976Sjmallett * PCI_CFG19 = Twentieth 32-bits of PCI config space (Master/Target Implementation Register) 1579215976Sjmallett * 1580215976Sjmallett */ 1581232812Sjmallettunion cvmx_pci_cfg19 { 1582215976Sjmallett uint32_t u32; 1583232812Sjmallett struct cvmx_pci_cfg19_s { 1584232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1585215976Sjmallett uint32_t mrbcm : 1; /**< Master Request (Memory Read) Byte Count/Byte 1586215976Sjmallett Enable select. 1587215976Sjmallett 0 = Byte Enables valid. In PCI mode, a burst 1588215976Sjmallett transaction cannot be performed using 1589215976Sjmallett Memory Read command=4'h6. 1590215976Sjmallett 1 = DWORD Byte Count valid (default). In PCI 1591215976Sjmallett Mode, the memory read byte enables are 1592215976Sjmallett automatically generated by the core. 1593215976Sjmallett NOTE: For OCTEON, this bit must always be one 1594215976Sjmallett for proper operation. */ 1595215976Sjmallett uint32_t mrbci : 1; /**< Master Request (I/O and CR cycles) byte count/byte 1596215976Sjmallett enable select. 1597215976Sjmallett 0 = Byte Enables valid (default) 1598215976Sjmallett 1 = DWORD byte count valid 1599215976Sjmallett NOTE: For OCTEON, this bit must always be zero 1600215976Sjmallett for proper operation (in support of 1601215976Sjmallett Type0/1 Cfg Space accesses which require byte 1602215976Sjmallett enable generation directly from a read mask). */ 1603215976Sjmallett uint32_t mdwe : 1; /**< Master (Retry) Deferred Write Enable (allow 1604215976Sjmallett read requests to pass). 1605215976Sjmallett NOTE: Applicable to PCI Mode I/O and memory 1606215976Sjmallett transactions only. 1607215976Sjmallett 0 = New read requests are NOT accepted until 1608215976Sjmallett the current write cycle completes. [Reads 1609215976Sjmallett cannot pass writes] 1610215976Sjmallett 1 = New read requests are accepted, even when 1611215976Sjmallett there is a write cycle pending [Reads can 1612215976Sjmallett pass writes]. 1613215976Sjmallett NOTE: For OCTEON, this bit must always be zero 1614215976Sjmallett for proper operation. */ 1615215976Sjmallett uint32_t mdre : 1; /**< Master (Retry) Deferred Read Enable (Allows 1616215976Sjmallett read/write requests to pass). 1617215976Sjmallett NOTE: Applicable to PCI mode I/O and memory 1618215976Sjmallett transactions only. 1619215976Sjmallett 0 = New read/write requests are NOT accepted 1620215976Sjmallett until the current read cycle completes. 1621215976Sjmallett [Read/write requests CANNOT pass reads] 1622215976Sjmallett 1 = New read/write requests are accepted, even 1623215976Sjmallett when there is a read cycle pending. 1624215976Sjmallett [Read/write requests CAN pass reads] 1625215976Sjmallett NOTE: For OCTEON, this bit must always be zero 1626215976Sjmallett for proper operation. */ 1627215976Sjmallett uint32_t mdrimc : 1; /**< Master I/O Deferred/Split Request Outstanding 1628215976Sjmallett Maximum Count 1629215976Sjmallett 0 = MDRRMC[26:24] 1630215976Sjmallett 1 = 1 */ 1631215976Sjmallett uint32_t mdrrmc : 3; /**< Master Deferred Read Request Outstanding Max 1632215976Sjmallett Count (PCI only). 1633215976Sjmallett CR4C[26:24] Max SAC cycles MAX DAC cycles 1634215976Sjmallett 000 8 4 1635215976Sjmallett 001 1 0 1636215976Sjmallett 010 2 1 1637215976Sjmallett 011 3 1 1638215976Sjmallett 100 4 2 1639215976Sjmallett 101 5 2 1640215976Sjmallett 110 6 3 1641215976Sjmallett 111 7 3 1642215976Sjmallett For example, if these bits are programmed to 1643215976Sjmallett 100, the core can support 2 DAC cycles, 4 SAC 1644215976Sjmallett cycles or a combination of 1 DAC and 2 SAC cycles. 1645215976Sjmallett NOTE: For the PCI-X maximum outstanding split 1646215976Sjmallett transactions, refer to CRE0[22:20] */ 1647215976Sjmallett uint32_t tmes : 8; /**< Target/Master Error Sequence \# */ 1648215976Sjmallett uint32_t teci : 1; /**< Target Error Command Indication 1649215976Sjmallett 0 = Delayed/Split 1650215976Sjmallett 1 = Others */ 1651215976Sjmallett uint32_t tmei : 1; /**< Target/Master Error Indication 1652215976Sjmallett 0 = Target 1653215976Sjmallett 1 = Master */ 1654215976Sjmallett uint32_t tmse : 1; /**< Target/Master System Error. This bit is set 1655215976Sjmallett whenever ATM_SERR_O is active. */ 1656215976Sjmallett uint32_t tmdpes : 1; /**< Target/Master Data PERR# error status. This 1657215976Sjmallett bit is set whenever ATM_DATA_PERR_O is active. */ 1658215976Sjmallett uint32_t tmapes : 1; /**< Target/Master Address PERR# error status. This 1659215976Sjmallett bit is set whenever ATM_ADDR_PERR_O is active. */ 1660215976Sjmallett uint32_t reserved_9_10 : 2; 1661215976Sjmallett uint32_t tibcd : 1; /**< Target Illegal I/O DWORD byte combinations detected. */ 1662215976Sjmallett uint32_t tibde : 1; /**< Target Illegal I/O DWORD byte detection enable */ 1663215976Sjmallett uint32_t reserved_6_6 : 1; 1664215976Sjmallett uint32_t tidomc : 1; /**< Target I/O Delayed/Split request outstanding 1665215976Sjmallett maximum count. 1666215976Sjmallett 0 = TDOMC[4:0] 1667215976Sjmallett 1 = 1 */ 1668215976Sjmallett uint32_t tdomc : 5; /**< Target Delayed/Split request outstanding maximum 1669215976Sjmallett count. [1..31] and 0=32. 1670215976Sjmallett NOTE: If the user programs these bits beyond the 1671215976Sjmallett Designed Maximum outstanding count, then the 1672215976Sjmallett designed maximum table depth will be used instead. 1673215976Sjmallett No additional Deferred/Split transactions will be 1674215976Sjmallett accepted if this outstanding maximum count 1675215976Sjmallett is reached. Furthermore, no additional 1676215976Sjmallett deferred/split transactions will be accepted if 1677215976Sjmallett the I/O delay/ I/O Split Request outstanding 1678215976Sjmallett maximum is reached. 1679215976Sjmallett NOTE: For OCTEON in PCI Mode, this field MUST BE 1680215976Sjmallett programmed to 1. (OCTEON can only handle 1 delayed 1681215976Sjmallett read at a time). 1682215976Sjmallett For OCTEON in PCIX Mode, this field can range from 1683215976Sjmallett 1-4. (The designed maximum table depth is 4 1684215976Sjmallett for PCIX mode splits). */ 1685215976Sjmallett#else 1686215976Sjmallett uint32_t tdomc : 5; 1687215976Sjmallett uint32_t tidomc : 1; 1688215976Sjmallett uint32_t reserved_6_6 : 1; 1689215976Sjmallett uint32_t tibde : 1; 1690215976Sjmallett uint32_t tibcd : 1; 1691215976Sjmallett uint32_t reserved_9_10 : 2; 1692215976Sjmallett uint32_t tmapes : 1; 1693215976Sjmallett uint32_t tmdpes : 1; 1694215976Sjmallett uint32_t tmse : 1; 1695215976Sjmallett uint32_t tmei : 1; 1696215976Sjmallett uint32_t teci : 1; 1697215976Sjmallett uint32_t tmes : 8; 1698215976Sjmallett uint32_t mdrrmc : 3; 1699215976Sjmallett uint32_t mdrimc : 1; 1700215976Sjmallett uint32_t mdre : 1; 1701215976Sjmallett uint32_t mdwe : 1; 1702215976Sjmallett uint32_t mrbci : 1; 1703215976Sjmallett uint32_t mrbcm : 1; 1704215976Sjmallett#endif 1705215976Sjmallett } s; 1706215976Sjmallett struct cvmx_pci_cfg19_s cn30xx; 1707215976Sjmallett struct cvmx_pci_cfg19_s cn31xx; 1708215976Sjmallett struct cvmx_pci_cfg19_s cn38xx; 1709215976Sjmallett struct cvmx_pci_cfg19_s cn38xxp2; 1710215976Sjmallett struct cvmx_pci_cfg19_s cn50xx; 1711215976Sjmallett struct cvmx_pci_cfg19_s cn58xx; 1712215976Sjmallett struct cvmx_pci_cfg19_s cn58xxp1; 1713215976Sjmallett}; 1714215976Sjmalletttypedef union cvmx_pci_cfg19 cvmx_pci_cfg19_t; 1715215976Sjmallett 1716215976Sjmallett/** 1717215976Sjmallett * cvmx_pci_cfg20 1718215976Sjmallett * 1719215976Sjmallett * PCI_CFG20 = Twenty-first 32-bits of PCI config space (Master Deferred/Split Sequence Pending) 1720215976Sjmallett * 1721215976Sjmallett */ 1722232812Sjmallettunion cvmx_pci_cfg20 { 1723215976Sjmallett uint32_t u32; 1724232812Sjmallett struct cvmx_pci_cfg20_s { 1725232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1726215976Sjmallett uint32_t mdsp : 32; /**< Master Deferred/Split sequence Pending 1727215976Sjmallett For OCTEON, this register is intended for debug use 1728215976Sjmallett only and MUST NEVER be written with anything other 1729215976Sjmallett than ZEROES. */ 1730215976Sjmallett#else 1731215976Sjmallett uint32_t mdsp : 32; 1732215976Sjmallett#endif 1733215976Sjmallett } s; 1734215976Sjmallett struct cvmx_pci_cfg20_s cn30xx; 1735215976Sjmallett struct cvmx_pci_cfg20_s cn31xx; 1736215976Sjmallett struct cvmx_pci_cfg20_s cn38xx; 1737215976Sjmallett struct cvmx_pci_cfg20_s cn38xxp2; 1738215976Sjmallett struct cvmx_pci_cfg20_s cn50xx; 1739215976Sjmallett struct cvmx_pci_cfg20_s cn58xx; 1740215976Sjmallett struct cvmx_pci_cfg20_s cn58xxp1; 1741215976Sjmallett}; 1742215976Sjmalletttypedef union cvmx_pci_cfg20 cvmx_pci_cfg20_t; 1743215976Sjmallett 1744215976Sjmallett/** 1745215976Sjmallett * cvmx_pci_cfg21 1746215976Sjmallett * 1747215976Sjmallett * PCI_CFG21 = Twenty-second 32-bits of PCI config space (Master Split Completion Message Register) 1748215976Sjmallett * 1749215976Sjmallett */ 1750232812Sjmallettunion cvmx_pci_cfg21 { 1751215976Sjmallett uint32_t u32; 1752232812Sjmallett struct cvmx_pci_cfg21_s { 1753232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1754215976Sjmallett uint32_t scmre : 32; /**< Master Split Completion message received with 1755215976Sjmallett error message. 1756215976Sjmallett For OCTEON, this register is intended for debug use 1757215976Sjmallett only and MUST NEVER be written with anything other 1758215976Sjmallett than ZEROES. */ 1759215976Sjmallett#else 1760215976Sjmallett uint32_t scmre : 32; 1761215976Sjmallett#endif 1762215976Sjmallett } s; 1763215976Sjmallett struct cvmx_pci_cfg21_s cn30xx; 1764215976Sjmallett struct cvmx_pci_cfg21_s cn31xx; 1765215976Sjmallett struct cvmx_pci_cfg21_s cn38xx; 1766215976Sjmallett struct cvmx_pci_cfg21_s cn38xxp2; 1767215976Sjmallett struct cvmx_pci_cfg21_s cn50xx; 1768215976Sjmallett struct cvmx_pci_cfg21_s cn58xx; 1769215976Sjmallett struct cvmx_pci_cfg21_s cn58xxp1; 1770215976Sjmallett}; 1771215976Sjmalletttypedef union cvmx_pci_cfg21 cvmx_pci_cfg21_t; 1772215976Sjmallett 1773215976Sjmallett/** 1774215976Sjmallett * cvmx_pci_cfg22 1775215976Sjmallett * 1776215976Sjmallett * PCI_CFG22 = Twenty-third 32-bits of PCI config space (Master Arbiter Control Register) 1777215976Sjmallett * 1778215976Sjmallett */ 1779232812Sjmallettunion cvmx_pci_cfg22 { 1780215976Sjmallett uint32_t u32; 1781232812Sjmallett struct cvmx_pci_cfg22_s { 1782232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1783215976Sjmallett uint32_t mac : 7; /**< Master Arbiter Control 1784215976Sjmallett [31:26]: Used only in Fixed Priority mode 1785215976Sjmallett (when [25]=1) 1786215976Sjmallett [31:30]: MSI Request 1787215976Sjmallett 00 = Highest Priority 1788215976Sjmallett 01 = Medium Priority 1789215976Sjmallett 10 = Lowest Priority 1790215976Sjmallett 11 = RESERVED 1791215976Sjmallett [29:28]: Target Split Completion 1792215976Sjmallett 00 = Highest Priority 1793215976Sjmallett 01 = Medium Priority 1794215976Sjmallett 10 = Lowest Priority 1795215976Sjmallett 11 = RESERVED 1796215976Sjmallett [27:26]: New Request; Deferred Read,Deferred Write 1797215976Sjmallett 00 = Highest Priority 1798215976Sjmallett 01 = Medium Priority 1799215976Sjmallett 10 = Lowest Priority 1800215976Sjmallett 11 = RESERVED 1801215976Sjmallett [25]: Fixed/Round Robin Priority Selector 1802215976Sjmallett 0 = Round Robin 1803215976Sjmallett 1 = Fixed 1804215976Sjmallett NOTE: When [25]=1(fixed priority), the three levels 1805215976Sjmallett [31:26] MUST BE programmed to have mutually exclusive 1806215976Sjmallett priority levels for proper operation. (Failure to do 1807215976Sjmallett so may result in PCI hangs). */ 1808215976Sjmallett uint32_t reserved_19_24 : 6; 1809215976Sjmallett uint32_t flush : 1; /**< AM_DO_FLUSH_I control 1810215976Sjmallett NOTE: This bit MUST BE ONE for proper OCTEON operation */ 1811215976Sjmallett uint32_t mra : 1; /**< Master Retry Aborted */ 1812215976Sjmallett uint32_t mtta : 1; /**< Master TRDY timeout aborted */ 1813215976Sjmallett uint32_t mrv : 8; /**< Master Retry Value [1..255] and 0=infinite */ 1814215976Sjmallett uint32_t mttv : 8; /**< Master TRDY timeout value [1..255] and 0=disabled 1815215976Sjmallett NOTE: For OCTEON, this bit must always be zero 1816215976Sjmallett for proper operation. (OCTEON does not support 1817215976Sjmallett master TRDY timeout - target is expected to be 1818215976Sjmallett well behaved). */ 1819215976Sjmallett#else 1820215976Sjmallett uint32_t mttv : 8; 1821215976Sjmallett uint32_t mrv : 8; 1822215976Sjmallett uint32_t mtta : 1; 1823215976Sjmallett uint32_t mra : 1; 1824215976Sjmallett uint32_t flush : 1; 1825215976Sjmallett uint32_t reserved_19_24 : 6; 1826215976Sjmallett uint32_t mac : 7; 1827215976Sjmallett#endif 1828215976Sjmallett } s; 1829215976Sjmallett struct cvmx_pci_cfg22_s cn30xx; 1830215976Sjmallett struct cvmx_pci_cfg22_s cn31xx; 1831215976Sjmallett struct cvmx_pci_cfg22_s cn38xx; 1832215976Sjmallett struct cvmx_pci_cfg22_s cn38xxp2; 1833215976Sjmallett struct cvmx_pci_cfg22_s cn50xx; 1834215976Sjmallett struct cvmx_pci_cfg22_s cn58xx; 1835215976Sjmallett struct cvmx_pci_cfg22_s cn58xxp1; 1836215976Sjmallett}; 1837215976Sjmalletttypedef union cvmx_pci_cfg22 cvmx_pci_cfg22_t; 1838215976Sjmallett 1839215976Sjmallett/** 1840215976Sjmallett * cvmx_pci_cfg56 1841215976Sjmallett * 1842215976Sjmallett * PCI_CFG56 = Fifty-seventh 32-bits of PCI config space (PCIX Capabilities Register) 1843215976Sjmallett * 1844215976Sjmallett */ 1845232812Sjmallettunion cvmx_pci_cfg56 { 1846215976Sjmallett uint32_t u32; 1847232812Sjmallett struct cvmx_pci_cfg56_s { 1848232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1849215976Sjmallett uint32_t reserved_23_31 : 9; 1850215976Sjmallett uint32_t most : 3; /**< Maximum outstanding Split transactions 1851215976Sjmallett Encoded Value \#Max outstanding splits 1852215976Sjmallett 000 1 1853215976Sjmallett 001 2 1854215976Sjmallett 010 3 1855215976Sjmallett 011 4 1856215976Sjmallett 100 8 1857215976Sjmallett 101 8(clamped) 1858215976Sjmallett 110 8(clamped) 1859215976Sjmallett 111 8(clamped) 1860215976Sjmallett NOTE: OCTEON only supports upto a MAXIMUM of 8 1861215976Sjmallett outstanding master split transactions. */ 1862215976Sjmallett uint32_t mmbc : 2; /**< Maximum Memory Byte Count 1863215976Sjmallett [0=512B,1=1024B,2=2048B,3=4096B] 1864215976Sjmallett NOTE: OCTEON does not support this field and has 1865215976Sjmallett no effect on limiting the maximum memory byte count. */ 1866215976Sjmallett uint32_t roe : 1; /**< Relaxed Ordering Enable */ 1867215976Sjmallett uint32_t dpere : 1; /**< Data Parity Error Recovery Enable */ 1868215976Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer */ 1869215976Sjmallett uint32_t pxcid : 8; /**< PCI-X Capability ID */ 1870215976Sjmallett#else 1871215976Sjmallett uint32_t pxcid : 8; 1872215976Sjmallett uint32_t ncp : 8; 1873215976Sjmallett uint32_t dpere : 1; 1874215976Sjmallett uint32_t roe : 1; 1875215976Sjmallett uint32_t mmbc : 2; 1876215976Sjmallett uint32_t most : 3; 1877215976Sjmallett uint32_t reserved_23_31 : 9; 1878215976Sjmallett#endif 1879215976Sjmallett } s; 1880215976Sjmallett struct cvmx_pci_cfg56_s cn30xx; 1881215976Sjmallett struct cvmx_pci_cfg56_s cn31xx; 1882215976Sjmallett struct cvmx_pci_cfg56_s cn38xx; 1883215976Sjmallett struct cvmx_pci_cfg56_s cn38xxp2; 1884215976Sjmallett struct cvmx_pci_cfg56_s cn50xx; 1885215976Sjmallett struct cvmx_pci_cfg56_s cn58xx; 1886215976Sjmallett struct cvmx_pci_cfg56_s cn58xxp1; 1887215976Sjmallett}; 1888215976Sjmalletttypedef union cvmx_pci_cfg56 cvmx_pci_cfg56_t; 1889215976Sjmallett 1890215976Sjmallett/** 1891215976Sjmallett * cvmx_pci_cfg57 1892215976Sjmallett * 1893215976Sjmallett * PCI_CFG57 = Fifty-eigth 32-bits of PCI config space (PCIX Status Register) 1894215976Sjmallett * 1895215976Sjmallett */ 1896232812Sjmallettunion cvmx_pci_cfg57 { 1897215976Sjmallett uint32_t u32; 1898232812Sjmallett struct cvmx_pci_cfg57_s { 1899232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1900215976Sjmallett uint32_t reserved_30_31 : 2; 1901215976Sjmallett uint32_t scemr : 1; /**< Split Completion Error Message Received */ 1902215976Sjmallett uint32_t mcrsd : 3; /**< Maximum Cumulative Read Size designed */ 1903215976Sjmallett uint32_t mostd : 3; /**< Maximum Outstanding Split transaction designed */ 1904215976Sjmallett uint32_t mmrbcd : 2; /**< Maximum Memory Read byte count designed */ 1905215976Sjmallett uint32_t dc : 1; /**< Device Complexity 1906215976Sjmallett 0 = Simple Device 1907215976Sjmallett 1 = Bridge Device */ 1908215976Sjmallett uint32_t usc : 1; /**< Unexpected Split Completion */ 1909215976Sjmallett uint32_t scd : 1; /**< Split Completion Discarded */ 1910215976Sjmallett uint32_t m133 : 1; /**< 133MHz Capable */ 1911215976Sjmallett uint32_t w64 : 1; /**< Indicates a 32b(=0) or 64b(=1) device */ 1912215976Sjmallett uint32_t bn : 8; /**< Bus Number. Updated on all configuration write 1913215976Sjmallett (0x11=PCI) cycles. Its value is dependent upon the PCI/X 1914215976Sjmallett (0xFF=PCIX) mode. */ 1915215976Sjmallett uint32_t dn : 5; /**< Device Number. Updated on all configuration 1916215976Sjmallett write cycles. */ 1917215976Sjmallett uint32_t fn : 3; /**< Function Number */ 1918215976Sjmallett#else 1919215976Sjmallett uint32_t fn : 3; 1920215976Sjmallett uint32_t dn : 5; 1921215976Sjmallett uint32_t bn : 8; 1922215976Sjmallett uint32_t w64 : 1; 1923215976Sjmallett uint32_t m133 : 1; 1924215976Sjmallett uint32_t scd : 1; 1925215976Sjmallett uint32_t usc : 1; 1926215976Sjmallett uint32_t dc : 1; 1927215976Sjmallett uint32_t mmrbcd : 2; 1928215976Sjmallett uint32_t mostd : 3; 1929215976Sjmallett uint32_t mcrsd : 3; 1930215976Sjmallett uint32_t scemr : 1; 1931215976Sjmallett uint32_t reserved_30_31 : 2; 1932215976Sjmallett#endif 1933215976Sjmallett } s; 1934215976Sjmallett struct cvmx_pci_cfg57_s cn30xx; 1935215976Sjmallett struct cvmx_pci_cfg57_s cn31xx; 1936215976Sjmallett struct cvmx_pci_cfg57_s cn38xx; 1937215976Sjmallett struct cvmx_pci_cfg57_s cn38xxp2; 1938215976Sjmallett struct cvmx_pci_cfg57_s cn50xx; 1939215976Sjmallett struct cvmx_pci_cfg57_s cn58xx; 1940215976Sjmallett struct cvmx_pci_cfg57_s cn58xxp1; 1941215976Sjmallett}; 1942215976Sjmalletttypedef union cvmx_pci_cfg57 cvmx_pci_cfg57_t; 1943215976Sjmallett 1944215976Sjmallett/** 1945215976Sjmallett * cvmx_pci_cfg58 1946215976Sjmallett * 1947215976Sjmallett * PCI_CFG58 = Fifty-ninth 32-bits of PCI config space (Power Management Capabilities Register) 1948215976Sjmallett * 1949215976Sjmallett */ 1950232812Sjmallettunion cvmx_pci_cfg58 { 1951215976Sjmallett uint32_t u32; 1952232812Sjmallett struct cvmx_pci_cfg58_s { 1953232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1954215976Sjmallett uint32_t pmes : 5; /**< PME Support (D0 to D3cold) */ 1955215976Sjmallett uint32_t d2s : 1; /**< D2_Support */ 1956215976Sjmallett uint32_t d1s : 1; /**< D1_Support */ 1957215976Sjmallett uint32_t auxc : 3; /**< AUX_Current (0..375mA) */ 1958215976Sjmallett uint32_t dsi : 1; /**< Device Specific Initialization */ 1959215976Sjmallett uint32_t reserved_20_20 : 1; 1960215976Sjmallett uint32_t pmec : 1; /**< PME Clock */ 1961215976Sjmallett uint32_t pcimiv : 3; /**< Indicates the version of the PCI 1962215976Sjmallett Management 1963215976Sjmallett Interface Specification with which the core 1964215976Sjmallett complies. 1965215976Sjmallett 010b = Complies with PCI Management Interface 1966215976Sjmallett Specification Revision 1.1 */ 1967215976Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer */ 1968215976Sjmallett uint32_t pmcid : 8; /**< Power Management Capability ID */ 1969215976Sjmallett#else 1970215976Sjmallett uint32_t pmcid : 8; 1971215976Sjmallett uint32_t ncp : 8; 1972215976Sjmallett uint32_t pcimiv : 3; 1973215976Sjmallett uint32_t pmec : 1; 1974215976Sjmallett uint32_t reserved_20_20 : 1; 1975215976Sjmallett uint32_t dsi : 1; 1976215976Sjmallett uint32_t auxc : 3; 1977215976Sjmallett uint32_t d1s : 1; 1978215976Sjmallett uint32_t d2s : 1; 1979215976Sjmallett uint32_t pmes : 5; 1980215976Sjmallett#endif 1981215976Sjmallett } s; 1982215976Sjmallett struct cvmx_pci_cfg58_s cn30xx; 1983215976Sjmallett struct cvmx_pci_cfg58_s cn31xx; 1984215976Sjmallett struct cvmx_pci_cfg58_s cn38xx; 1985215976Sjmallett struct cvmx_pci_cfg58_s cn38xxp2; 1986215976Sjmallett struct cvmx_pci_cfg58_s cn50xx; 1987215976Sjmallett struct cvmx_pci_cfg58_s cn58xx; 1988215976Sjmallett struct cvmx_pci_cfg58_s cn58xxp1; 1989215976Sjmallett}; 1990215976Sjmalletttypedef union cvmx_pci_cfg58 cvmx_pci_cfg58_t; 1991215976Sjmallett 1992215976Sjmallett/** 1993215976Sjmallett * cvmx_pci_cfg59 1994215976Sjmallett * 1995215976Sjmallett * PCI_CFG59 = Sixtieth 32-bits of PCI config space (Power Management Data/PMCSR Register(s)) 1996215976Sjmallett * 1997215976Sjmallett */ 1998232812Sjmallettunion cvmx_pci_cfg59 { 1999215976Sjmallett uint32_t u32; 2000232812Sjmallett struct cvmx_pci_cfg59_s { 2001232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2002215976Sjmallett uint32_t pmdia : 8; /**< Power Management data input from application 2003215976Sjmallett (PME_DATA) */ 2004215976Sjmallett uint32_t bpccen : 1; /**< BPCC_En (bus power/clock control) enable */ 2005215976Sjmallett uint32_t bd3h : 1; /**< B2_B3\#, B2/B3 Support for D3hot */ 2006215976Sjmallett uint32_t reserved_16_21 : 6; 2007215976Sjmallett uint32_t pmess : 1; /**< PME_Status sticky bit */ 2008215976Sjmallett uint32_t pmedsia : 2; /**< PME_Data_Scale input from application 2009215976Sjmallett Device (PME_DATA_SCALE[1:0]) 2010215976Sjmallett Specific */ 2011215976Sjmallett uint32_t pmds : 4; /**< Power Management Data_select */ 2012215976Sjmallett uint32_t pmeens : 1; /**< PME_En sticky bit */ 2013215976Sjmallett uint32_t reserved_2_7 : 6; 2014215976Sjmallett uint32_t ps : 2; /**< Power State (D0 to D3) 2015215976Sjmallett The N2 DOES NOT support D1/D2 Power Management 2016215976Sjmallett states, therefore writing to this register has 2017215976Sjmallett no effect (please refer to the PCI Power 2018215976Sjmallett Management 2019215976Sjmallett Specification v1.1 for further details about 2020215976Sjmallett it?s R/W nature. This is not a conventional 2021215976Sjmallett R/W style register. */ 2022215976Sjmallett#else 2023215976Sjmallett uint32_t ps : 2; 2024215976Sjmallett uint32_t reserved_2_7 : 6; 2025215976Sjmallett uint32_t pmeens : 1; 2026215976Sjmallett uint32_t pmds : 4; 2027215976Sjmallett uint32_t pmedsia : 2; 2028215976Sjmallett uint32_t pmess : 1; 2029215976Sjmallett uint32_t reserved_16_21 : 6; 2030215976Sjmallett uint32_t bd3h : 1; 2031215976Sjmallett uint32_t bpccen : 1; 2032215976Sjmallett uint32_t pmdia : 8; 2033215976Sjmallett#endif 2034215976Sjmallett } s; 2035215976Sjmallett struct cvmx_pci_cfg59_s cn30xx; 2036215976Sjmallett struct cvmx_pci_cfg59_s cn31xx; 2037215976Sjmallett struct cvmx_pci_cfg59_s cn38xx; 2038215976Sjmallett struct cvmx_pci_cfg59_s cn38xxp2; 2039215976Sjmallett struct cvmx_pci_cfg59_s cn50xx; 2040215976Sjmallett struct cvmx_pci_cfg59_s cn58xx; 2041215976Sjmallett struct cvmx_pci_cfg59_s cn58xxp1; 2042215976Sjmallett}; 2043215976Sjmalletttypedef union cvmx_pci_cfg59 cvmx_pci_cfg59_t; 2044215976Sjmallett 2045215976Sjmallett/** 2046215976Sjmallett * cvmx_pci_cfg60 2047215976Sjmallett * 2048215976Sjmallett * PCI_CFG60 = Sixty-first 32-bits of PCI config space (MSI Capabilities Register) 2049215976Sjmallett * 2050215976Sjmallett */ 2051232812Sjmallettunion cvmx_pci_cfg60 { 2052215976Sjmallett uint32_t u32; 2053232812Sjmallett struct cvmx_pci_cfg60_s { 2054232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2055215976Sjmallett uint32_t reserved_24_31 : 8; 2056215976Sjmallett uint32_t m64 : 1; /**< 32/64 b message */ 2057215976Sjmallett uint32_t mme : 3; /**< Multiple Message Enable(1,2,4,8,16,32) */ 2058215976Sjmallett uint32_t mmc : 3; /**< Multiple Message Capable(0=1,1=2,2=4,3=8,4=16,5=32) */ 2059215976Sjmallett uint32_t msien : 1; /**< MSI Enable */ 2060215976Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer */ 2061215976Sjmallett uint32_t msicid : 8; /**< MSI Capability ID */ 2062215976Sjmallett#else 2063215976Sjmallett uint32_t msicid : 8; 2064215976Sjmallett uint32_t ncp : 8; 2065215976Sjmallett uint32_t msien : 1; 2066215976Sjmallett uint32_t mmc : 3; 2067215976Sjmallett uint32_t mme : 3; 2068215976Sjmallett uint32_t m64 : 1; 2069215976Sjmallett uint32_t reserved_24_31 : 8; 2070215976Sjmallett#endif 2071215976Sjmallett } s; 2072215976Sjmallett struct cvmx_pci_cfg60_s cn30xx; 2073215976Sjmallett struct cvmx_pci_cfg60_s cn31xx; 2074215976Sjmallett struct cvmx_pci_cfg60_s cn38xx; 2075215976Sjmallett struct cvmx_pci_cfg60_s cn38xxp2; 2076215976Sjmallett struct cvmx_pci_cfg60_s cn50xx; 2077215976Sjmallett struct cvmx_pci_cfg60_s cn58xx; 2078215976Sjmallett struct cvmx_pci_cfg60_s cn58xxp1; 2079215976Sjmallett}; 2080215976Sjmalletttypedef union cvmx_pci_cfg60 cvmx_pci_cfg60_t; 2081215976Sjmallett 2082215976Sjmallett/** 2083215976Sjmallett * cvmx_pci_cfg61 2084215976Sjmallett * 2085215976Sjmallett * PCI_CFG61 = Sixty-second 32-bits of PCI config space (MSI Lower Address Register) 2086215976Sjmallett * 2087215976Sjmallett */ 2088232812Sjmallettunion cvmx_pci_cfg61 { 2089215976Sjmallett uint32_t u32; 2090232812Sjmallett struct cvmx_pci_cfg61_s { 2091232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2092215976Sjmallett uint32_t msi31t2 : 30; /**< App Specific MSI Address [31:2] */ 2093215976Sjmallett uint32_t reserved_0_1 : 2; 2094215976Sjmallett#else 2095215976Sjmallett uint32_t reserved_0_1 : 2; 2096215976Sjmallett uint32_t msi31t2 : 30; 2097215976Sjmallett#endif 2098215976Sjmallett } s; 2099215976Sjmallett struct cvmx_pci_cfg61_s cn30xx; 2100215976Sjmallett struct cvmx_pci_cfg61_s cn31xx; 2101215976Sjmallett struct cvmx_pci_cfg61_s cn38xx; 2102215976Sjmallett struct cvmx_pci_cfg61_s cn38xxp2; 2103215976Sjmallett struct cvmx_pci_cfg61_s cn50xx; 2104215976Sjmallett struct cvmx_pci_cfg61_s cn58xx; 2105215976Sjmallett struct cvmx_pci_cfg61_s cn58xxp1; 2106215976Sjmallett}; 2107215976Sjmalletttypedef union cvmx_pci_cfg61 cvmx_pci_cfg61_t; 2108215976Sjmallett 2109215976Sjmallett/** 2110215976Sjmallett * cvmx_pci_cfg62 2111215976Sjmallett * 2112215976Sjmallett * PCI_CFG62 = Sixty-third 32-bits of PCI config space (MSI Upper Address Register) 2113215976Sjmallett * 2114215976Sjmallett */ 2115232812Sjmallettunion cvmx_pci_cfg62 { 2116215976Sjmallett uint32_t u32; 2117232812Sjmallett struct cvmx_pci_cfg62_s { 2118232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2119215976Sjmallett uint32_t msi : 32; /**< MSI Address [63:32] */ 2120215976Sjmallett#else 2121215976Sjmallett uint32_t msi : 32; 2122215976Sjmallett#endif 2123215976Sjmallett } s; 2124215976Sjmallett struct cvmx_pci_cfg62_s cn30xx; 2125215976Sjmallett struct cvmx_pci_cfg62_s cn31xx; 2126215976Sjmallett struct cvmx_pci_cfg62_s cn38xx; 2127215976Sjmallett struct cvmx_pci_cfg62_s cn38xxp2; 2128215976Sjmallett struct cvmx_pci_cfg62_s cn50xx; 2129215976Sjmallett struct cvmx_pci_cfg62_s cn58xx; 2130215976Sjmallett struct cvmx_pci_cfg62_s cn58xxp1; 2131215976Sjmallett}; 2132215976Sjmalletttypedef union cvmx_pci_cfg62 cvmx_pci_cfg62_t; 2133215976Sjmallett 2134215976Sjmallett/** 2135215976Sjmallett * cvmx_pci_cfg63 2136215976Sjmallett * 2137215976Sjmallett * PCI_CFG63 = Sixty-fourth 32-bits of PCI config space (MSI Message Data Register) 2138215976Sjmallett * 2139215976Sjmallett */ 2140232812Sjmallettunion cvmx_pci_cfg63 { 2141215976Sjmallett uint32_t u32; 2142232812Sjmallett struct cvmx_pci_cfg63_s { 2143232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2144215976Sjmallett uint32_t reserved_16_31 : 16; 2145215976Sjmallett uint32_t msimd : 16; /**< MSI Message Data */ 2146215976Sjmallett#else 2147215976Sjmallett uint32_t msimd : 16; 2148215976Sjmallett uint32_t reserved_16_31 : 16; 2149215976Sjmallett#endif 2150215976Sjmallett } s; 2151215976Sjmallett struct cvmx_pci_cfg63_s cn30xx; 2152215976Sjmallett struct cvmx_pci_cfg63_s cn31xx; 2153215976Sjmallett struct cvmx_pci_cfg63_s cn38xx; 2154215976Sjmallett struct cvmx_pci_cfg63_s cn38xxp2; 2155215976Sjmallett struct cvmx_pci_cfg63_s cn50xx; 2156215976Sjmallett struct cvmx_pci_cfg63_s cn58xx; 2157215976Sjmallett struct cvmx_pci_cfg63_s cn58xxp1; 2158215976Sjmallett}; 2159215976Sjmalletttypedef union cvmx_pci_cfg63 cvmx_pci_cfg63_t; 2160215976Sjmallett 2161215976Sjmallett/** 2162215976Sjmallett * cvmx_pci_cnt_reg 2163215976Sjmallett * 2164215976Sjmallett * PCI_CNT_REG = PCI Clock Count Register 2165215976Sjmallett * 2166215976Sjmallett * This register is provided to software as a means to determine PCI Bus Type/Speed. 2167215976Sjmallett */ 2168232812Sjmallettunion cvmx_pci_cnt_reg { 2169215976Sjmallett uint64_t u64; 2170232812Sjmallett struct cvmx_pci_cnt_reg_s { 2171232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2172215976Sjmallett uint64_t reserved_38_63 : 26; 2173215976Sjmallett uint64_t hm_pcix : 1; /**< PCI Host Mode Sampled Bus Type (0:PCI/1:PCIX) 2174215976Sjmallett This field represents what OCTEON(in Host mode) 2175215976Sjmallett sampled as the 'intended' PCI Bus Type based on 2176215976Sjmallett the PCI_PCIXCAP pin. (see HM_SPEED Bus Type/Speed 2177215976Sjmallett encoding table). */ 2178215976Sjmallett uint64_t hm_speed : 2; /**< PCI Host Mode Sampled Bus Speed 2179215976Sjmallett This field represents what OCTEON(in Host mode) 2180215976Sjmallett sampled as the 'intended' PCI Bus Speed based on 2181215976Sjmallett the PCI100, PCI_M66EN and PCI_PCIXCAP pins. 2182215976Sjmallett NOTE: This DOES NOT reflect what the actual PCI 2183215976Sjmallett Bus Type/Speed values are. They only indicate what 2184215976Sjmallett OCTEON sampled as the 'intended' values. 2185215976Sjmallett PCI Host Mode Sampled Bus Type/Speed Table: 2186215976Sjmallett M66EN | PCIXCAP | PCI100 | HM_PCIX | HM_SPEED[1:0] 2187215976Sjmallett ---------+---------+---------+----------+------------- 2188215976Sjmallett 0 | 0 | 0 | 0=PCI | 00=33 MHz 2189215976Sjmallett 0 | 0 | 1 | 0=PCI | 00=33 MHz 2190215976Sjmallett 0 | Z | 0 | 0=PCI | 01=66 MHz 2191215976Sjmallett 0 | Z | 1 | 0=PCI | 01=66 MHz 2192215976Sjmallett 1 | 0 | 0 | 0=PCI | 01=66 MHz 2193215976Sjmallett 1 | 0 | 1 | 0=PCI | 01=66 MHz 2194215976Sjmallett 1 | Z | 0 | 0=PCI | 01=66 MHz 2195215976Sjmallett 1 | Z | 1 | 0=PCI | 01=66 MHz 2196215976Sjmallett 0 | 1 | 1 | 1=PCIX | 10=100 MHz 2197215976Sjmallett 1 | 1 | 1 | 1=PCIX | 10=100 MHz 2198215976Sjmallett 0 | 1 | 0 | 1=PCIX | 11=133 MHz 2199215976Sjmallett 1 | 1 | 0 | 1=PCIX | 11=133 MHz 2200215976Sjmallett NOTE: PCIXCAP has tri-level value (0,1,Z). See PCI specification 2201215976Sjmallett for more details on board level hookup to achieve these 2202215976Sjmallett values. 2203215976Sjmallett NOTE: Software can use the NPI_PCI_INT_ARB_CFG[PCI_OVR] 2204215976Sjmallett to override the 'sampled' PCI Bus Type/Speed. 2205215976Sjmallett NOTE: Software can also use the PCI_CNT_REG[PCICNT] to determine 2206215976Sjmallett the exact PCI(X) Bus speed. 2207215976Sjmallett Example: PCI_REF_CLKIN=133MHz 2208215976Sjmallett PCI_HOST_MODE=1 2209215976Sjmallett PCI_M66EN=0 2210215976Sjmallett PCI_PCIXCAP=1 2211215976Sjmallett PCI_PCI100=1 2212215976Sjmallett For this example, OCTEON will generate 2213215976Sjmallett PCI_CLK_OUT=100MHz and drive the proper PCI 2214215976Sjmallett Initialization sequence (DEVSEL#=Deasserted, 2215215976Sjmallett STOP#=Asserted, TRDY#=Asserted) during PCI_RST_N 2216215976Sjmallett deassertion. 2217215976Sjmallett NOTE: The HM_SPEED field is only valid after 2218215976Sjmallett PLL_REF_CLK is active and PLL_DCOK is asserted. 2219215976Sjmallett (see HRM description for power-on/reset sequence). 2220215976Sjmallett NOTE: PCI_REF_CLKIN input must be 133MHz (and is used 2221215976Sjmallett to generate the PCI_CLK_OUT pin in Host Mode). */ 2222215976Sjmallett uint64_t ap_pcix : 1; /**< PCI(X) Bus Type (0:PCI/1:PCIX) 2223215976Sjmallett At PCI_RST_N de-assertion, the PCI Initialization 2224215976Sjmallett pattern(PCI_DEVSEL_N, PCI_STOP_N, PCI_TRDY_N) is 2225215976Sjmallett captured to provide information to software regarding 2226215976Sjmallett the PCI Bus Type(PCI/PCIX) and PCI Bus Speed Range. */ 2227215976Sjmallett uint64_t ap_speed : 2; /**< PCI(X) Bus Speed (0:33/1:66/2:100/3:133) 2228215976Sjmallett At PCI_RST_N de-assertion, the PCI Initialization 2229215976Sjmallett pattern(PCI_DEVSEL_N, PCI_STOP_N, PCI_TRDY_N) is 2230215976Sjmallett captured to provide information to software regarding 2231215976Sjmallett the PCI Bus Type(PCI/PCIX) and PCI Bus Speed Range. 2232215976Sjmallett PCI-X Initialization Pattern(see PCIX Spec): 2233215976Sjmallett PCI_DEVSEL_N PCI_STOP_N PCI_TRDY_N Mode MaxClk(ns) MinClk(ns) MinClk(MHz) MaxClk(MHz) 2234215976Sjmallett -------------+----------+----------+-------+---------+----------+----------+------------------ 2235215976Sjmallett Deasserted Deasserted Deasserted PCI 33 -- 30 0 33 2236215976Sjmallett PCI 66 30 15 33 66 2237215976Sjmallett Deasserted Deasserted Asserted PCI-X 20 15 50 66 2238215976Sjmallett Deasserted Asserted Deasserted PCI-X 15 10 66 100 2239215976Sjmallett Deasserted Asserted Asserted PCI-X 10 7.5 100 133 2240215976Sjmallett Asserted Deasserted Deasserted PCI-X Reserved Reserved Reserved Reserved 2241215976Sjmallett Asserted Deasserted Asserted PCI-X Reserved Reserved Reserved Reserved 2242215976Sjmallett Asserted Asserted Deasserted PCI-X Reserved Reserved Reserved Reserved 2243215976Sjmallett Asserted Asserted Asserted PCI-X Reserved Reserved Reserved Reserved 2244215976Sjmallett NOTE: The PCI Bus speed 'assumed' from the initialization 2245215976Sjmallett pattern is really intended for an operational range. 2246215976Sjmallett For example: If PINIT=100, this indicates PCI-X in the 2247215976Sjmallett 100-133MHz range. The PCI_CNT field can be used to further 2248215976Sjmallett determine a more exacting PCI Bus frequency value if 2249215976Sjmallett required. */ 2250215976Sjmallett uint64_t pcicnt : 32; /**< Free Running PCI Clock counter. 2251215976Sjmallett At PCI Reset, the PCICNT=0, and is auto-incremented 2252215976Sjmallett on every PCI clock and will auto-wrap back to zero 2253215976Sjmallett when saturated. 2254215976Sjmallett NOTE: Writes override the auto-increment to allow 2255215976Sjmallett software to preload any initial value. 2256215976Sjmallett The PCICNT field is provided to software as a means 2257215976Sjmallett to determine the PCI Bus Speed. 2258215976Sjmallett Assuming software has knowledge of the core frequency 2259215976Sjmallett (eclk), this register can be written with a value X, 2260215976Sjmallett wait 'n' core clocks(eclk) and then read later(Y) to 2261215976Sjmallett determine \#PCI clocks(Y-X) have elapsed within 'n' core 2262215976Sjmallett clocks to determine the PCI input Clock frequency. */ 2263215976Sjmallett#else 2264215976Sjmallett uint64_t pcicnt : 32; 2265215976Sjmallett uint64_t ap_speed : 2; 2266215976Sjmallett uint64_t ap_pcix : 1; 2267215976Sjmallett uint64_t hm_speed : 2; 2268215976Sjmallett uint64_t hm_pcix : 1; 2269215976Sjmallett uint64_t reserved_38_63 : 26; 2270215976Sjmallett#endif 2271215976Sjmallett } s; 2272215976Sjmallett struct cvmx_pci_cnt_reg_s cn50xx; 2273215976Sjmallett struct cvmx_pci_cnt_reg_s cn58xx; 2274215976Sjmallett struct cvmx_pci_cnt_reg_s cn58xxp1; 2275215976Sjmallett}; 2276215976Sjmalletttypedef union cvmx_pci_cnt_reg cvmx_pci_cnt_reg_t; 2277215976Sjmallett 2278215976Sjmallett/** 2279215976Sjmallett * cvmx_pci_ctl_status_2 2280215976Sjmallett * 2281215976Sjmallett * PCI_CTL_STATUS_2 = PCI Control Status 2 Register 2282215976Sjmallett * 2283215976Sjmallett * Control status register accessable from both PCI and NCB. 2284215976Sjmallett */ 2285232812Sjmallettunion cvmx_pci_ctl_status_2 { 2286215976Sjmallett uint32_t u32; 2287232812Sjmallett struct cvmx_pci_ctl_status_2_s { 2288232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2289215976Sjmallett uint32_t reserved_29_31 : 3; 2290215976Sjmallett uint32_t bb1_hole : 3; /**< Big BAR 1 Hole 2291215976Sjmallett NOT IN PASS 1 NOR PASS 2 2292215976Sjmallett When PCI_CTL_STATUS_2[BB1]=1, this field defines 2293215976Sjmallett an encoded size of the upper BAR1 region which 2294215976Sjmallett OCTEON will mask out (ie: not respond to). 2295215976Sjmallett (see definition of BB1_HOLE and BB1_SIZ encodings 2296215976Sjmallett in the PCI_CTL_STATUS_2[BB1] definition below). */ 2297215976Sjmallett uint32_t bb1_siz : 1; /**< Big BAR 1 Size 2298215976Sjmallett NOT IN PASS 1 NOR PASS 2 2299215976Sjmallett When PCI_CTL_STATUS_2[BB1]=1, this field defines 2300215976Sjmallett the programmable SIZE of BAR 1. 2301215976Sjmallett - 0: 1GB / 1: 2GB */ 2302215976Sjmallett uint32_t bb_ca : 1; /**< Set to '1' for Big Bar Mode to do STT/LDT L2C 2303215976Sjmallett operations. 2304215976Sjmallett NOT IN PASS 1 NOR PASS 2 */ 2305215976Sjmallett uint32_t bb_es : 2; /**< Big Bar Node Endian Swap Mode 2306215976Sjmallett - 0: No Swizzle 2307215976Sjmallett - 1: Byte Swizzle (per-QW) 2308215976Sjmallett - 2: Byte Swizzle (per-LW) 2309215976Sjmallett - 3: LongWord Swizzle 2310215976Sjmallett NOT IN PASS 1 NOR PASS 2 */ 2311215976Sjmallett uint32_t bb1 : 1; /**< Big Bar 1 Enable 2312215976Sjmallett NOT IN PASS 1 NOR PASS 2 2313215976Sjmallett When PCI_CTL_STATUS_2[BB1] is set, the following differences 2314215976Sjmallett occur: 2315215976Sjmallett - OCTEON's BAR1 becomes somewhere in the range 512-2048 MB rather 2316215976Sjmallett than the default 128MB. 2317215976Sjmallett - The following table indicates the effective size of 2318215976Sjmallett BAR1 when BB1 is set: 2319215976Sjmallett BB1_SIZ BB1_HOLE Effective size Comment 2320215976Sjmallett +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2321215976Sjmallett 0 0 1024 MB Normal 1GB BAR 2322215976Sjmallett 0 1 1008 MB 1 GB, 16 MB hole 2323215976Sjmallett 0 2 992 MB 1 GB, 32 MB hole 2324215976Sjmallett 0 3 960 MB 1 GB, 64 MB hole 2325215976Sjmallett 0 4 896 MB 1 GB,128 MB hole 2326215976Sjmallett 0 5 768 MB 1 GB,256 MB hole 2327215976Sjmallett 0 6 512 MB 1 GB,512 MB hole 2328215976Sjmallett 0 7 Illegal 2329215976Sjmallett 1 0 2048 MB Normal 2GB BAR 2330215976Sjmallett 1 1 2032 MB 2 GB, 16 MB hole 2331215976Sjmallett 1 2 2016 MB 2 GB, 32 MB hole 2332215976Sjmallett 1 3 1984 MB 2 GB, 64 MB hole 2333215976Sjmallett 1 4 1920 MB 2 GB,128 MB hole 2334215976Sjmallett 1 5 1792 MB 2 GB,256 MB hole 2335215976Sjmallett 1 6 1536 MB 2 GB,512 MB hole 2336215976Sjmallett 1 7 Illegal 2337215976Sjmallett - When BB1_SIZ is 0: PCI_CFG06[LBASE<2:0>] reads as zero 2338215976Sjmallett and are ignored on write. BAR1 is an entirely ordinary 2339215976Sjmallett 1 GB (power-of-two) BAR in all aspects when BB1_HOLE is 0. 2340215976Sjmallett When BB1_HOLE is not zero, BAR1 addresses are programmed 2341215976Sjmallett as if the BAR were 1GB, but, OCTEON does not respond 2342215976Sjmallett to addresses in the programmed holes. 2343215976Sjmallett - When BB1_SIZ is 1: PCI_CFG06[LBASE<3:0>] reads as zero 2344215976Sjmallett and are ignored on write. BAR1 is an entirely ordinary 2345215976Sjmallett 2 GB (power-of-two) BAR in all aspects when BB1_HOLE is 0. 2346215976Sjmallett When BB1_HOLE is not zero, BAR1 addresses are programmed 2347215976Sjmallett as if the BAR were 2GB, but, OCTEON does not respond 2348215976Sjmallett to addresses in the programmed holes. 2349215976Sjmallett - Note that the BB1_HOLE value has no effect on the 2350215976Sjmallett PCI_CFG06[LBASE] behavior. BB1_HOLE only affects whether 2351215976Sjmallett OCTEON accepts an address. BB1_SIZ does affect PCI_CFG06[LBASE] 2352215976Sjmallett behavior, however. 2353215976Sjmallett - The first 128MB, i.e. addresses on the PCI bus in the range 2354215976Sjmallett BAR1+0 .. BAR1+0x07FFFFFF 2355215976Sjmallett access OCTEON's DRAM addresses with PCI_BAR1_INDEX CSR's 2356215976Sjmallett as before 2357215976Sjmallett - The remaining address space, i.e. addresses 2358215976Sjmallett on the PCI bus in the range 2359215976Sjmallett BAR1+0x08000000 .. BAR1+size-1, 2360215976Sjmallett where size is the size of BAR1 as selected by the above 2361215976Sjmallett table (based on the BB1_SIZ and BB1_HOLE values), are mapped to 2362215976Sjmallett OCTEON physical DRAM addresses as follows: 2363215976Sjmallett PCI Address Range OCTEON Physical Address Range 2364215976Sjmallett ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2365215976Sjmallett BAR1+0x08000000 .. BAR1+size-1 | 0x88000000 .. 0x7FFFFFFF+size 2366215976Sjmallett and PCI_CTL_STATUS_2[BB_ES] is the endian-swap and 2367215976Sjmallett PCI_CTL_STATUS_2[BB_CA] is the L2 cache allocation bit 2368215976Sjmallett for these references. 2369215976Sjmallett The consequences of any burst that crosses the end of the PCI 2370215976Sjmallett Address Range for BAR1 are unpredicable. 2371215976Sjmallett - The consequences of any burst access that crosses the boundary 2372215976Sjmallett between BAR1+0x07FFFFFF and BAR1+0x08000000 are unpredictable in PCI-X 2373215976Sjmallett mode. OCTEON may disconnect PCI references at this boundary. */ 2374215976Sjmallett uint32_t bb0 : 1; /**< Big Bar 0 Enable 2375215976Sjmallett NOT IN PASS 1 NOR PASS 2 2376215976Sjmallett When PCI_CTL_STATUS_2[BB0] is set, the following 2377215976Sjmallett differences occur: 2378215976Sjmallett - OCTEON's BAR0 becomes 2GB rather than the default 4KB. 2379215976Sjmallett PCI_CFG04[LBASE<18:0>] reads as zero and is ignored on write. 2380215976Sjmallett - OCTEON's BAR0 becomes burstable. (When BB0 is clear, OCTEON 2381215976Sjmallett single-phase disconnects PCI BAR0 reads and PCI/PCI-X BAR0 2382215976Sjmallett writes, and splits (burstably) PCI-X BAR0 reads.) 2383215976Sjmallett - The first 4KB, i.e. addresses on the PCI bus in the range 2384215976Sjmallett BAR0+0 .. BAR0+0xFFF 2385215976Sjmallett access OCTEON's PCI-type CSR's as when BB0 is clear. 2386215976Sjmallett - The remaining address space, i.e. addresses on the PCI bus 2387215976Sjmallett in the range 2388215976Sjmallett BAR0+0x1000 .. BAR0+0x7FFFFFFF 2389215976Sjmallett are mapped to OCTEON physical DRAM addresses as follows: 2390215976Sjmallett PCI Address Range OCTEON Physical Address Range 2391215976Sjmallett ------------------------------------+------------------------------ 2392215976Sjmallett BAR0+0x00001000 .. BAR0+0x0FFFFFFF | 0x000001000 .. 0x00FFFFFFF 2393215976Sjmallett BAR0+0x10000000 .. BAR0+0x1FFFFFFF | 0x410000000 .. 0x41FFFFFFF 2394215976Sjmallett BAR0+0x20000000 .. BAR0+0x7FFFFFFF | 0x020000000 .. 0x07FFFFFFF 2395215976Sjmallett and PCI_CTL_STATUS_2[BB_ES] is the endian-swap and 2396215976Sjmallett PCI_CTL_STATUS_2[BB_CA] is the L2 cache allocation bit 2397215976Sjmallett for these references. 2398215976Sjmallett The consequences of any burst that crosses the end of the PCI 2399215976Sjmallett Address Range for BAR0 are unpredicable. 2400215976Sjmallett - The consequences of any burst access that crosses the boundary 2401215976Sjmallett between BAR0+0xFFF and BAR0+0x1000 are unpredictable in PCI-X 2402215976Sjmallett mode. OCTEON may disconnect PCI references at this boundary. 2403215976Sjmallett - The results of any burst read that crosses the boundary 2404215976Sjmallett between BAR0+0x0FFFFFFF and BAR0+0x10000000 are unpredictable. 2405215976Sjmallett The consequences of any burst write that crosses this same 2406215976Sjmallett boundary are unpredictable. 2407215976Sjmallett - The results of any burst read that crosses the boundary 2408215976Sjmallett between BAR0+0x1FFFFFFF and BAR0+0x20000000 are unpredictable. 2409215976Sjmallett The consequences of any burst write that crosses this same 2410215976Sjmallett boundary are unpredictable. */ 2411215976Sjmallett uint32_t erst_n : 1; /**< Reset active Low. PASS-2 */ 2412215976Sjmallett uint32_t bar2pres : 1; /**< From fuse block. When fuse(MIO_FUS_DAT3[BAR2_EN]) 2413215976Sjmallett is NOT blown the value of this field is '0' after 2414215976Sjmallett reset and BAR2 is NOT present. When the fuse IS 2415215976Sjmallett blown the value of this field is '1' after reset 2416215976Sjmallett and BAR2 is present. Note that SW can change this 2417215976Sjmallett field after reset. This is a PASS-2 field. */ 2418215976Sjmallett uint32_t scmtyp : 1; /**< Split Completion Message CMD Type (0=RD/1=WR) 2419215976Sjmallett When SCM=1, SCMTYP specifies the CMD intent (R/W) */ 2420215976Sjmallett uint32_t scm : 1; /**< Split Completion Message Detected (Read or Write) */ 2421215976Sjmallett uint32_t en_wfilt : 1; /**< When '1' the window-access filter is enabled. 2422215976Sjmallett Unfilter writes are: 2423215976Sjmallett MIO, SubId0 2424215976Sjmallett MIO, SubId7 2425215976Sjmallett NPI, SubId0 2426215976Sjmallett NPI, SubId7 2427215976Sjmallett POW, SubId7 2428215976Sjmallett DFA, SubId7 2429215976Sjmallett IPD, SubId7 2430215976Sjmallett Unfiltered Reads are: 2431215976Sjmallett MIO, SubId0 2432215976Sjmallett MIO, SubId7 2433215976Sjmallett NPI, SubId0 2434215976Sjmallett NPI, SubId7 2435215976Sjmallett POW, SubId1 2436215976Sjmallett POW, SubId2 2437215976Sjmallett POW, SubId3 2438215976Sjmallett POW, SubId7 2439215976Sjmallett DFA, SubId7 2440215976Sjmallett IPD, SubId7 */ 2441215976Sjmallett uint32_t reserved_14_14 : 1; 2442215976Sjmallett uint32_t ap_pcix : 1; /**< PCX Core Mode status (0=PCI Bus/1=PCIX) 2443215976Sjmallett If one or more of PCI_DEVSEL_N, PCI_STOP_N, and 2444215976Sjmallett PCI_TRDY_N are asserted at the rising edge of 2445215976Sjmallett PCI_RST_N, the device enters PCI-X mode. 2446215976Sjmallett Otherwise, the device enters conventional PCI 2447215976Sjmallett mode at the rising edge of RST#. */ 2448215976Sjmallett uint32_t ap_64ad : 1; /**< PCX Core Bus status (0=32b Bus/1=64b Bus) 2449215976Sjmallett When PCI_RST_N pin is de-asserted, the state 2450215976Sjmallett of PCI_REQ64_N(driven by central agent) determines 2451215976Sjmallett the width of the PCI/X bus. */ 2452215976Sjmallett uint32_t b12_bist : 1; /**< Bist Status For Memeory In B12 */ 2453215976Sjmallett uint32_t pmo_amod : 1; /**< PMO-ARB Mode (0=FP[HP=CMD1,LP=CMD0]/1=RR) */ 2454215976Sjmallett uint32_t pmo_fpc : 3; /**< PMO-ARB Fixed Priority Counter 2455215976Sjmallett When PMO_AMOD=0 (FP mode), this field represents 2456215976Sjmallett the \# of CMD1 requests that are issued (at higher 2457215976Sjmallett priority) before a single lower priority CMD0 2458215976Sjmallett is allowed to issue (to ensure foward progress). 2459215976Sjmallett - 0: 1 CMD1 Request issued before CMD0 allowed 2460215976Sjmallett - ... 2461215976Sjmallett - 7: 8 CMD1 Requests issued before CMD0 allowed */ 2462215976Sjmallett uint32_t tsr_hwm : 3; /**< Target Split-Read ADB(allowable disconnect boundary) 2463215976Sjmallett High Water Mark. 2464215976Sjmallett Specifies the number of ADBs(128 Byte aligned chunks) 2465215976Sjmallett that are accumulated(pending) BEFORE the Target Split 2466215976Sjmallett completion is attempted on the PCI bus. 2467215976Sjmallett - 0: RESERVED/ILLEGAL 2468215976Sjmallett - 1: 2 Pending ADBs (129B-256B) 2469215976Sjmallett - 2: 3 Pending ADBs (257B-384B) 2470215976Sjmallett - 3: 4 Pending ADBs (385B-512B) 2471215976Sjmallett - 4: 5 Pending ADBs (513B-640B) 2472215976Sjmallett - 5: 6 Pending ADBs (641B-768B) 2473215976Sjmallett - 6: 7 Pending ADBs (769B-896B) 2474215976Sjmallett - 7: 8 Pending ADBs (897B-1024B) 2475215976Sjmallett Example: Suppose a 1KB target memory request with 2476215976Sjmallett starting byte offset address[6:0]=0x7F is split by 2477215976Sjmallett the OCTEON and the TSR_HWM=1(2 ADBs). 2478215976Sjmallett The OCTEON will start the target split completion 2479215976Sjmallett on the PCI Bus after 1B(1st ADB)+128B(2nd ADB)=129B 2480215976Sjmallett of data have been received from memory (even though 2481215976Sjmallett the remaining 895B has not yet been received). The 2482215976Sjmallett OCTEON will continue the split completion until it 2483215976Sjmallett has consumed all of the pended split data. If the 2484215976Sjmallett full transaction length(1KB) of data was NOT entirely 2485215976Sjmallett transferred, then OCTEON will terminate the split 2486215976Sjmallett completion and again wait for another 2 ADB-aligned data 2487215976Sjmallett chunks(256B) of pended split data to be received from 2488215976Sjmallett memory before starting another split completion request. 2489215976Sjmallett This allows Octeon (as split completer), to send back 2490215976Sjmallett multiple split completions for a given large split 2491215976Sjmallett transaction without having to wait for the entire 2492215976Sjmallett transaction length to be received from memory. 2493215976Sjmallett NOTE: For split transaction sizes 'smaller' than the 2494215976Sjmallett specified TSR_HWM value, the split completion 2495215976Sjmallett is started when the last datum has been received from 2496215976Sjmallett memory. 2497215976Sjmallett NOTE: It is IMPERATIVE that this field NEVER BE 2498215976Sjmallett written to a ZERO value. A value of zero is 2499215976Sjmallett reserved/illegal and can result in PCIX bus hangs). */ 2500215976Sjmallett uint32_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when 2501215976Sjmallett clear '0' BAR2 access will be target-aborted. */ 2502215976Sjmallett uint32_t bar2_esx : 2; /**< Value will be XORed with pci-address[37:36] to 2503215976Sjmallett determine the endian swap mode. */ 2504215976Sjmallett uint32_t bar2_cax : 1; /**< Value will be XORed with pci-address[38] to 2505215976Sjmallett determine the L2 cache attribute. 2506215976Sjmallett When XOR result is 1, not cached in L2 */ 2507215976Sjmallett#else 2508215976Sjmallett uint32_t bar2_cax : 1; 2509215976Sjmallett uint32_t bar2_esx : 2; 2510215976Sjmallett uint32_t bar2_enb : 1; 2511215976Sjmallett uint32_t tsr_hwm : 3; 2512215976Sjmallett uint32_t pmo_fpc : 3; 2513215976Sjmallett uint32_t pmo_amod : 1; 2514215976Sjmallett uint32_t b12_bist : 1; 2515215976Sjmallett uint32_t ap_64ad : 1; 2516215976Sjmallett uint32_t ap_pcix : 1; 2517215976Sjmallett uint32_t reserved_14_14 : 1; 2518215976Sjmallett uint32_t en_wfilt : 1; 2519215976Sjmallett uint32_t scm : 1; 2520215976Sjmallett uint32_t scmtyp : 1; 2521215976Sjmallett uint32_t bar2pres : 1; 2522215976Sjmallett uint32_t erst_n : 1; 2523215976Sjmallett uint32_t bb0 : 1; 2524215976Sjmallett uint32_t bb1 : 1; 2525215976Sjmallett uint32_t bb_es : 2; 2526215976Sjmallett uint32_t bb_ca : 1; 2527215976Sjmallett uint32_t bb1_siz : 1; 2528215976Sjmallett uint32_t bb1_hole : 3; 2529215976Sjmallett uint32_t reserved_29_31 : 3; 2530215976Sjmallett#endif 2531215976Sjmallett } s; 2532215976Sjmallett struct cvmx_pci_ctl_status_2_s cn30xx; 2533232812Sjmallett struct cvmx_pci_ctl_status_2_cn31xx { 2534232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2535215976Sjmallett uint32_t reserved_20_31 : 12; 2536215976Sjmallett uint32_t erst_n : 1; /**< Reset active Low. */ 2537215976Sjmallett uint32_t bar2pres : 1; /**< From fuse block. When fuse(MIO_FUS_DAT3[BAR2_EN]) 2538215976Sjmallett is NOT blown the value of this field is '0' after 2539215976Sjmallett reset and BAR2 is NOT present. When the fuse IS 2540215976Sjmallett blown the value of this field is '1' after reset 2541215976Sjmallett and BAR2 is present. Note that SW can change this 2542215976Sjmallett field after reset. */ 2543215976Sjmallett uint32_t scmtyp : 1; /**< Split Completion Message CMD Type (0=RD/1=WR) 2544215976Sjmallett When SCM=1, SCMTYP specifies the CMD intent (R/W) */ 2545215976Sjmallett uint32_t scm : 1; /**< Split Completion Message Detected (Read or Write) */ 2546215976Sjmallett uint32_t en_wfilt : 1; /**< When '1' the window-access filter is enabled. 2547215976Sjmallett Unfilter writes are: 2548215976Sjmallett MIO, SubId0 2549215976Sjmallett MIO, SubId7 2550215976Sjmallett NPI, SubId0 2551215976Sjmallett NPI, SubId7 2552215976Sjmallett POW, SubId7 2553215976Sjmallett DFA, SubId7 2554215976Sjmallett IPD, SubId7 2555215976Sjmallett USBN, SubId7 2556215976Sjmallett Unfiltered Reads are: 2557215976Sjmallett MIO, SubId0 2558215976Sjmallett MIO, SubId7 2559215976Sjmallett NPI, SubId0 2560215976Sjmallett NPI, SubId7 2561215976Sjmallett POW, SubId1 2562215976Sjmallett POW, SubId2 2563215976Sjmallett POW, SubId3 2564215976Sjmallett POW, SubId7 2565215976Sjmallett DFA, SubId7 2566215976Sjmallett IPD, SubId7 2567215976Sjmallett USBN, SubId7 */ 2568215976Sjmallett uint32_t reserved_14_14 : 1; 2569215976Sjmallett uint32_t ap_pcix : 1; /**< PCX Core Mode status (0=PCI Bus/1=PCIX) */ 2570215976Sjmallett uint32_t ap_64ad : 1; /**< PCX Core Bus status (0=32b Bus/1=64b Bus) */ 2571215976Sjmallett uint32_t b12_bist : 1; /**< Bist Status For Memeory In B12 */ 2572215976Sjmallett uint32_t pmo_amod : 1; /**< PMO-ARB Mode (0=FP[HP=CMD1,LP=CMD0]/1=RR) */ 2573215976Sjmallett uint32_t pmo_fpc : 3; /**< PMO-ARB Fixed Priority Counter 2574215976Sjmallett When PMO_AMOD=0 (FP mode), this field represents 2575215976Sjmallett the \# of CMD1 requests that are issued (at higher 2576215976Sjmallett priority) before a single lower priority CMD0 2577215976Sjmallett is allowed to issue (to ensure foward progress). 2578215976Sjmallett - 0: 1 CMD1 Request issued before CMD0 allowed 2579215976Sjmallett - ... 2580215976Sjmallett - 7: 8 CMD1 Requests issued before CMD0 allowed */ 2581215976Sjmallett uint32_t tsr_hwm : 3; /**< Target Split-Read ADB(allowable disconnect boundary) 2582215976Sjmallett High Water Mark. 2583215976Sjmallett Specifies the number of ADBs(128 Byte aligned chunks) 2584215976Sjmallett that are accumulated(pending) BEFORE the Target Split 2585215976Sjmallett completion is attempted on the PCI bus. 2586215976Sjmallett - 0: RESERVED/ILLEGAL 2587215976Sjmallett - 1: 2 Pending ADBs (129B-256B) 2588215976Sjmallett - 2: 3 Pending ADBs (257B-384B) 2589215976Sjmallett - 3: 4 Pending ADBs (385B-512B) 2590215976Sjmallett - 4: 5 Pending ADBs (513B-640B) 2591215976Sjmallett - 5: 6 Pending ADBs (641B-768B) 2592215976Sjmallett - 6: 7 Pending ADBs (769B-896B) 2593215976Sjmallett - 7: 8 Pending ADBs (897B-1024B) 2594215976Sjmallett Example: Suppose a 1KB target memory request with 2595215976Sjmallett starting byte offset address[6:0]=0x7F is split by 2596215976Sjmallett the OCTEON and the TSR_HWM=1(2 ADBs). 2597215976Sjmallett The OCTEON will start the target split completion 2598215976Sjmallett on the PCI Bus after 1B(1st ADB)+128B(2nd ADB)=129B 2599215976Sjmallett of data have been received from memory (even though 2600215976Sjmallett the remaining 895B has not yet been received). The 2601215976Sjmallett OCTEON will continue the split completion until it 2602215976Sjmallett has consumed all of the pended split data. If the 2603215976Sjmallett full transaction length(1KB) of data was NOT entirely 2604215976Sjmallett transferred, then OCTEON will terminate the split 2605215976Sjmallett completion and again wait for another 2 ADB-aligned data 2606215976Sjmallett chunks(256B) of pended split data to be received from 2607215976Sjmallett memory before starting another split completion request. 2608215976Sjmallett This allows Octeon (as split completer), to send back 2609215976Sjmallett multiple split completions for a given large split 2610215976Sjmallett transaction without having to wait for the entire 2611215976Sjmallett transaction length to be received from memory. 2612215976Sjmallett NOTE: For split transaction sizes 'smaller' than the 2613215976Sjmallett specified TSR_HWM value, the split completion 2614215976Sjmallett is started when the last datum has been received from 2615215976Sjmallett memory. 2616215976Sjmallett NOTE: It is IMPERATIVE that this field NEVER BE 2617215976Sjmallett written to a ZERO value. A value of zero is 2618215976Sjmallett reserved/illegal and can result in PCIX bus hangs). */ 2619215976Sjmallett uint32_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when 2620215976Sjmallett clear '0' BAR2 access will be target-aborted. */ 2621215976Sjmallett uint32_t bar2_esx : 2; /**< Value will be XORed with pci-address[37:36] to 2622215976Sjmallett determine the endian swap mode. */ 2623215976Sjmallett uint32_t bar2_cax : 1; /**< Value will be XORed with pci-address[38] to 2624215976Sjmallett determine the L2 cache attribute. 2625215976Sjmallett When XOR result is 1, not allocated in L2 cache */ 2626215976Sjmallett#else 2627215976Sjmallett uint32_t bar2_cax : 1; 2628215976Sjmallett uint32_t bar2_esx : 2; 2629215976Sjmallett uint32_t bar2_enb : 1; 2630215976Sjmallett uint32_t tsr_hwm : 3; 2631215976Sjmallett uint32_t pmo_fpc : 3; 2632215976Sjmallett uint32_t pmo_amod : 1; 2633215976Sjmallett uint32_t b12_bist : 1; 2634215976Sjmallett uint32_t ap_64ad : 1; 2635215976Sjmallett uint32_t ap_pcix : 1; 2636215976Sjmallett uint32_t reserved_14_14 : 1; 2637215976Sjmallett uint32_t en_wfilt : 1; 2638215976Sjmallett uint32_t scm : 1; 2639215976Sjmallett uint32_t scmtyp : 1; 2640215976Sjmallett uint32_t bar2pres : 1; 2641215976Sjmallett uint32_t erst_n : 1; 2642215976Sjmallett uint32_t reserved_20_31 : 12; 2643215976Sjmallett#endif 2644215976Sjmallett } cn31xx; 2645215976Sjmallett struct cvmx_pci_ctl_status_2_s cn38xx; 2646215976Sjmallett struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2; 2647215976Sjmallett struct cvmx_pci_ctl_status_2_s cn50xx; 2648215976Sjmallett struct cvmx_pci_ctl_status_2_s cn58xx; 2649215976Sjmallett struct cvmx_pci_ctl_status_2_s cn58xxp1; 2650215976Sjmallett}; 2651215976Sjmalletttypedef union cvmx_pci_ctl_status_2 cvmx_pci_ctl_status_2_t; 2652215976Sjmallett 2653215976Sjmallett/** 2654215976Sjmallett * cvmx_pci_dbell# 2655215976Sjmallett * 2656215976Sjmallett * PCI_DBELL0 = PCI Doorbell-0 2657215976Sjmallett * 2658215976Sjmallett * The value to write to the doorbell 0 register. The value in this register is acted upon when the 2659215976Sjmallett * least-significant-byte of this register is written. 2660215976Sjmallett */ 2661232812Sjmallettunion cvmx_pci_dbellx { 2662215976Sjmallett uint32_t u32; 2663232812Sjmallett struct cvmx_pci_dbellx_s { 2664232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2665215976Sjmallett uint32_t reserved_16_31 : 16; 2666215976Sjmallett uint32_t inc_val : 16; /**< Software writes this register with the 2667215976Sjmallett number of new Instructions to be processed 2668215976Sjmallett on the Instruction Queue. When read this 2669215976Sjmallett register contains the last write value. */ 2670215976Sjmallett#else 2671215976Sjmallett uint32_t inc_val : 16; 2672215976Sjmallett uint32_t reserved_16_31 : 16; 2673215976Sjmallett#endif 2674215976Sjmallett } s; 2675215976Sjmallett struct cvmx_pci_dbellx_s cn30xx; 2676215976Sjmallett struct cvmx_pci_dbellx_s cn31xx; 2677215976Sjmallett struct cvmx_pci_dbellx_s cn38xx; 2678215976Sjmallett struct cvmx_pci_dbellx_s cn38xxp2; 2679215976Sjmallett struct cvmx_pci_dbellx_s cn50xx; 2680215976Sjmallett struct cvmx_pci_dbellx_s cn58xx; 2681215976Sjmallett struct cvmx_pci_dbellx_s cn58xxp1; 2682215976Sjmallett}; 2683215976Sjmalletttypedef union cvmx_pci_dbellx cvmx_pci_dbellx_t; 2684215976Sjmallett 2685215976Sjmallett/** 2686215976Sjmallett * cvmx_pci_dma_cnt# 2687215976Sjmallett * 2688215976Sjmallett * PCI_DMA_CNT0 = PCI DMA Count0 2689215976Sjmallett * 2690215976Sjmallett * Keeps track of the number of DMAs or bytes sent by DMAs. The value in this register is acted upon when the 2691215976Sjmallett * least-significant-byte of this register is written. 2692215976Sjmallett */ 2693232812Sjmallettunion cvmx_pci_dma_cntx { 2694215976Sjmallett uint32_t u32; 2695232812Sjmallett struct cvmx_pci_dma_cntx_s { 2696232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2697215976Sjmallett uint32_t dma_cnt : 32; /**< Update with the number of DMAs completed or the 2698215976Sjmallett number of bytes sent for DMA's associated with 2699215976Sjmallett this counter. When this register is written the 2700215976Sjmallett value written to [15:0] will be subtracted from 2701215976Sjmallett the value in this register. */ 2702215976Sjmallett#else 2703215976Sjmallett uint32_t dma_cnt : 32; 2704215976Sjmallett#endif 2705215976Sjmallett } s; 2706215976Sjmallett struct cvmx_pci_dma_cntx_s cn30xx; 2707215976Sjmallett struct cvmx_pci_dma_cntx_s cn31xx; 2708215976Sjmallett struct cvmx_pci_dma_cntx_s cn38xx; 2709215976Sjmallett struct cvmx_pci_dma_cntx_s cn38xxp2; 2710215976Sjmallett struct cvmx_pci_dma_cntx_s cn50xx; 2711215976Sjmallett struct cvmx_pci_dma_cntx_s cn58xx; 2712215976Sjmallett struct cvmx_pci_dma_cntx_s cn58xxp1; 2713215976Sjmallett}; 2714215976Sjmalletttypedef union cvmx_pci_dma_cntx cvmx_pci_dma_cntx_t; 2715215976Sjmallett 2716215976Sjmallett/** 2717215976Sjmallett * cvmx_pci_dma_int_lev# 2718215976Sjmallett * 2719215976Sjmallett * PCI_DMA_INT_LEV0 = PCI DMA Sent Interrupt Level For DMA 0 2720215976Sjmallett * 2721215976Sjmallett * Interrupt when the value in PCI_DMA_CNT0 is equal to or greater than the register value. 2722215976Sjmallett */ 2723232812Sjmallettunion cvmx_pci_dma_int_levx { 2724215976Sjmallett uint32_t u32; 2725232812Sjmallett struct cvmx_pci_dma_int_levx_s { 2726232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2727215976Sjmallett uint32_t pkt_cnt : 32; /**< When PCI_DMA_CNT0 exceeds the value in this 2728215976Sjmallett DCNT0 will be set in PCI_INT_SUM and PCI_INT_SUM2. */ 2729215976Sjmallett#else 2730215976Sjmallett uint32_t pkt_cnt : 32; 2731215976Sjmallett#endif 2732215976Sjmallett } s; 2733215976Sjmallett struct cvmx_pci_dma_int_levx_s cn30xx; 2734215976Sjmallett struct cvmx_pci_dma_int_levx_s cn31xx; 2735215976Sjmallett struct cvmx_pci_dma_int_levx_s cn38xx; 2736215976Sjmallett struct cvmx_pci_dma_int_levx_s cn38xxp2; 2737215976Sjmallett struct cvmx_pci_dma_int_levx_s cn50xx; 2738215976Sjmallett struct cvmx_pci_dma_int_levx_s cn58xx; 2739215976Sjmallett struct cvmx_pci_dma_int_levx_s cn58xxp1; 2740215976Sjmallett}; 2741215976Sjmalletttypedef union cvmx_pci_dma_int_levx cvmx_pci_dma_int_levx_t; 2742215976Sjmallett 2743215976Sjmallett/** 2744215976Sjmallett * cvmx_pci_dma_time# 2745215976Sjmallett * 2746215976Sjmallett * PCI_DMA_TIME0 = PCI DMA Sent Timer For DMA0 2747215976Sjmallett * 2748215976Sjmallett * Time to wait from DMA being sent before issuing an interrupt. 2749215976Sjmallett */ 2750232812Sjmallettunion cvmx_pci_dma_timex { 2751215976Sjmallett uint32_t u32; 2752232812Sjmallett struct cvmx_pci_dma_timex_s { 2753232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2754215976Sjmallett uint32_t dma_time : 32; /**< Number of PCI clock cycle to wait before 2755215976Sjmallett setting DTIME0 in PCI_INT_SUM and PCI_INT_SUM2. 2756215976Sjmallett After PCI_DMA_CNT0 becomes non-zero. 2757215976Sjmallett The timer is reset when the 2758215976Sjmallett PCI_INT_SUM[27] register is cleared. */ 2759215976Sjmallett#else 2760215976Sjmallett uint32_t dma_time : 32; 2761215976Sjmallett#endif 2762215976Sjmallett } s; 2763215976Sjmallett struct cvmx_pci_dma_timex_s cn30xx; 2764215976Sjmallett struct cvmx_pci_dma_timex_s cn31xx; 2765215976Sjmallett struct cvmx_pci_dma_timex_s cn38xx; 2766215976Sjmallett struct cvmx_pci_dma_timex_s cn38xxp2; 2767215976Sjmallett struct cvmx_pci_dma_timex_s cn50xx; 2768215976Sjmallett struct cvmx_pci_dma_timex_s cn58xx; 2769215976Sjmallett struct cvmx_pci_dma_timex_s cn58xxp1; 2770215976Sjmallett}; 2771215976Sjmalletttypedef union cvmx_pci_dma_timex cvmx_pci_dma_timex_t; 2772215976Sjmallett 2773215976Sjmallett/** 2774215976Sjmallett * cvmx_pci_instr_count# 2775215976Sjmallett * 2776215976Sjmallett * PCI_INSTR_COUNT0 = PCI Instructions Outstanding Request Count 2777215976Sjmallett * 2778215976Sjmallett * The number of instructions to be fetched by the Instruction-0 Engine. 2779215976Sjmallett */ 2780232812Sjmallettunion cvmx_pci_instr_countx { 2781215976Sjmallett uint32_t u32; 2782232812Sjmallett struct cvmx_pci_instr_countx_s { 2783232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2784215976Sjmallett uint32_t icnt : 32; /**< Number of Instructions to be fetched by the 2785215976Sjmallett Instruction Engine. 2786215976Sjmallett A write of any non zero value to this register 2787215976Sjmallett will clear the value of this register. */ 2788215976Sjmallett#else 2789215976Sjmallett uint32_t icnt : 32; 2790215976Sjmallett#endif 2791215976Sjmallett } s; 2792215976Sjmallett struct cvmx_pci_instr_countx_s cn30xx; 2793215976Sjmallett struct cvmx_pci_instr_countx_s cn31xx; 2794215976Sjmallett struct cvmx_pci_instr_countx_s cn38xx; 2795215976Sjmallett struct cvmx_pci_instr_countx_s cn38xxp2; 2796215976Sjmallett struct cvmx_pci_instr_countx_s cn50xx; 2797215976Sjmallett struct cvmx_pci_instr_countx_s cn58xx; 2798215976Sjmallett struct cvmx_pci_instr_countx_s cn58xxp1; 2799215976Sjmallett}; 2800215976Sjmalletttypedef union cvmx_pci_instr_countx cvmx_pci_instr_countx_t; 2801215976Sjmallett 2802215976Sjmallett/** 2803215976Sjmallett * cvmx_pci_int_enb 2804215976Sjmallett * 2805215976Sjmallett * PCI_INT_ENB = PCI Interrupt Enable 2806215976Sjmallett * 2807215976Sjmallett * Enables interrupt bits in the PCI_INT_SUM register. 2808215976Sjmallett */ 2809232812Sjmallettunion cvmx_pci_int_enb { 2810215976Sjmallett uint64_t u64; 2811232812Sjmallett struct cvmx_pci_int_enb_s { 2812232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2813215976Sjmallett uint64_t reserved_34_63 : 30; 2814215976Sjmallett uint64_t ill_rd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */ 2815215976Sjmallett uint64_t ill_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */ 2816215976Sjmallett uint64_t win_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */ 2817215976Sjmallett uint64_t dma1_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */ 2818215976Sjmallett uint64_t dma0_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */ 2819215976Sjmallett uint64_t idtime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */ 2820215976Sjmallett uint64_t idtime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */ 2821215976Sjmallett uint64_t idcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */ 2822215976Sjmallett uint64_t idcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */ 2823215976Sjmallett uint64_t iptime3 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[24] */ 2824215976Sjmallett uint64_t iptime2 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[23] */ 2825215976Sjmallett uint64_t iptime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[22] */ 2826215976Sjmallett uint64_t iptime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */ 2827215976Sjmallett uint64_t ipcnt3 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[20] */ 2828215976Sjmallett uint64_t ipcnt2 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[19] */ 2829215976Sjmallett uint64_t ipcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[18] */ 2830215976Sjmallett uint64_t ipcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */ 2831215976Sjmallett uint64_t irsl_int : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */ 2832215976Sjmallett uint64_t ill_rrd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */ 2833215976Sjmallett uint64_t ill_rwr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */ 2834215976Sjmallett uint64_t idperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */ 2835215976Sjmallett uint64_t iaperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */ 2836215976Sjmallett uint64_t iserr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */ 2837215976Sjmallett uint64_t itsr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */ 2838215976Sjmallett uint64_t imsc_msg : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */ 2839215976Sjmallett uint64_t imsi_mabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */ 2840215976Sjmallett uint64_t imsi_tabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */ 2841215976Sjmallett uint64_t imsi_per : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */ 2842215976Sjmallett uint64_t imr_tto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */ 2843215976Sjmallett uint64_t imr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */ 2844215976Sjmallett uint64_t itr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */ 2845215976Sjmallett uint64_t imr_wtto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */ 2846215976Sjmallett uint64_t imr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */ 2847215976Sjmallett uint64_t itr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */ 2848215976Sjmallett#else 2849215976Sjmallett uint64_t itr_wabt : 1; 2850215976Sjmallett uint64_t imr_wabt : 1; 2851215976Sjmallett uint64_t imr_wtto : 1; 2852215976Sjmallett uint64_t itr_abt : 1; 2853215976Sjmallett uint64_t imr_abt : 1; 2854215976Sjmallett uint64_t imr_tto : 1; 2855215976Sjmallett uint64_t imsi_per : 1; 2856215976Sjmallett uint64_t imsi_tabt : 1; 2857215976Sjmallett uint64_t imsi_mabt : 1; 2858215976Sjmallett uint64_t imsc_msg : 1; 2859215976Sjmallett uint64_t itsr_abt : 1; 2860215976Sjmallett uint64_t iserr : 1; 2861215976Sjmallett uint64_t iaperr : 1; 2862215976Sjmallett uint64_t idperr : 1; 2863215976Sjmallett uint64_t ill_rwr : 1; 2864215976Sjmallett uint64_t ill_rrd : 1; 2865215976Sjmallett uint64_t irsl_int : 1; 2866215976Sjmallett uint64_t ipcnt0 : 1; 2867215976Sjmallett uint64_t ipcnt1 : 1; 2868215976Sjmallett uint64_t ipcnt2 : 1; 2869215976Sjmallett uint64_t ipcnt3 : 1; 2870215976Sjmallett uint64_t iptime0 : 1; 2871215976Sjmallett uint64_t iptime1 : 1; 2872215976Sjmallett uint64_t iptime2 : 1; 2873215976Sjmallett uint64_t iptime3 : 1; 2874215976Sjmallett uint64_t idcnt0 : 1; 2875215976Sjmallett uint64_t idcnt1 : 1; 2876215976Sjmallett uint64_t idtime0 : 1; 2877215976Sjmallett uint64_t idtime1 : 1; 2878215976Sjmallett uint64_t dma0_fi : 1; 2879215976Sjmallett uint64_t dma1_fi : 1; 2880215976Sjmallett uint64_t win_wr : 1; 2881215976Sjmallett uint64_t ill_wr : 1; 2882215976Sjmallett uint64_t ill_rd : 1; 2883215976Sjmallett uint64_t reserved_34_63 : 30; 2884215976Sjmallett#endif 2885215976Sjmallett } s; 2886232812Sjmallett struct cvmx_pci_int_enb_cn30xx { 2887232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2888215976Sjmallett uint64_t reserved_34_63 : 30; 2889215976Sjmallett uint64_t ill_rd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */ 2890215976Sjmallett uint64_t ill_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */ 2891215976Sjmallett uint64_t win_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */ 2892215976Sjmallett uint64_t dma1_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */ 2893215976Sjmallett uint64_t dma0_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */ 2894215976Sjmallett uint64_t idtime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */ 2895215976Sjmallett uint64_t idtime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */ 2896215976Sjmallett uint64_t idcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */ 2897215976Sjmallett uint64_t idcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */ 2898215976Sjmallett uint64_t reserved_22_24 : 3; 2899215976Sjmallett uint64_t iptime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */ 2900215976Sjmallett uint64_t reserved_18_20 : 3; 2901215976Sjmallett uint64_t ipcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */ 2902215976Sjmallett uint64_t irsl_int : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */ 2903215976Sjmallett uint64_t ill_rrd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */ 2904215976Sjmallett uint64_t ill_rwr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */ 2905215976Sjmallett uint64_t idperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */ 2906215976Sjmallett uint64_t iaperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */ 2907215976Sjmallett uint64_t iserr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */ 2908215976Sjmallett uint64_t itsr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */ 2909215976Sjmallett uint64_t imsc_msg : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */ 2910215976Sjmallett uint64_t imsi_mabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */ 2911215976Sjmallett uint64_t imsi_tabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */ 2912215976Sjmallett uint64_t imsi_per : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */ 2913215976Sjmallett uint64_t imr_tto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */ 2914215976Sjmallett uint64_t imr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */ 2915215976Sjmallett uint64_t itr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */ 2916215976Sjmallett uint64_t imr_wtto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */ 2917215976Sjmallett uint64_t imr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */ 2918215976Sjmallett uint64_t itr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */ 2919215976Sjmallett#else 2920215976Sjmallett uint64_t itr_wabt : 1; 2921215976Sjmallett uint64_t imr_wabt : 1; 2922215976Sjmallett uint64_t imr_wtto : 1; 2923215976Sjmallett uint64_t itr_abt : 1; 2924215976Sjmallett uint64_t imr_abt : 1; 2925215976Sjmallett uint64_t imr_tto : 1; 2926215976Sjmallett uint64_t imsi_per : 1; 2927215976Sjmallett uint64_t imsi_tabt : 1; 2928215976Sjmallett uint64_t imsi_mabt : 1; 2929215976Sjmallett uint64_t imsc_msg : 1; 2930215976Sjmallett uint64_t itsr_abt : 1; 2931215976Sjmallett uint64_t iserr : 1; 2932215976Sjmallett uint64_t iaperr : 1; 2933215976Sjmallett uint64_t idperr : 1; 2934215976Sjmallett uint64_t ill_rwr : 1; 2935215976Sjmallett uint64_t ill_rrd : 1; 2936215976Sjmallett uint64_t irsl_int : 1; 2937215976Sjmallett uint64_t ipcnt0 : 1; 2938215976Sjmallett uint64_t reserved_18_20 : 3; 2939215976Sjmallett uint64_t iptime0 : 1; 2940215976Sjmallett uint64_t reserved_22_24 : 3; 2941215976Sjmallett uint64_t idcnt0 : 1; 2942215976Sjmallett uint64_t idcnt1 : 1; 2943215976Sjmallett uint64_t idtime0 : 1; 2944215976Sjmallett uint64_t idtime1 : 1; 2945215976Sjmallett uint64_t dma0_fi : 1; 2946215976Sjmallett uint64_t dma1_fi : 1; 2947215976Sjmallett uint64_t win_wr : 1; 2948215976Sjmallett uint64_t ill_wr : 1; 2949215976Sjmallett uint64_t ill_rd : 1; 2950215976Sjmallett uint64_t reserved_34_63 : 30; 2951215976Sjmallett#endif 2952215976Sjmallett } cn30xx; 2953232812Sjmallett struct cvmx_pci_int_enb_cn31xx { 2954232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2955215976Sjmallett uint64_t reserved_34_63 : 30; 2956215976Sjmallett uint64_t ill_rd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */ 2957215976Sjmallett uint64_t ill_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */ 2958215976Sjmallett uint64_t win_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */ 2959215976Sjmallett uint64_t dma1_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */ 2960215976Sjmallett uint64_t dma0_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */ 2961215976Sjmallett uint64_t idtime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */ 2962215976Sjmallett uint64_t idtime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */ 2963215976Sjmallett uint64_t idcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */ 2964215976Sjmallett uint64_t idcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */ 2965215976Sjmallett uint64_t reserved_23_24 : 2; 2966215976Sjmallett uint64_t iptime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[22] */ 2967215976Sjmallett uint64_t iptime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */ 2968215976Sjmallett uint64_t reserved_19_20 : 2; 2969215976Sjmallett uint64_t ipcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[18] */ 2970215976Sjmallett uint64_t ipcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */ 2971215976Sjmallett uint64_t irsl_int : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */ 2972215976Sjmallett uint64_t ill_rrd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */ 2973215976Sjmallett uint64_t ill_rwr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */ 2974215976Sjmallett uint64_t idperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */ 2975215976Sjmallett uint64_t iaperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */ 2976215976Sjmallett uint64_t iserr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */ 2977215976Sjmallett uint64_t itsr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */ 2978215976Sjmallett uint64_t imsc_msg : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */ 2979215976Sjmallett uint64_t imsi_mabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */ 2980215976Sjmallett uint64_t imsi_tabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */ 2981215976Sjmallett uint64_t imsi_per : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */ 2982215976Sjmallett uint64_t imr_tto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */ 2983215976Sjmallett uint64_t imr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */ 2984215976Sjmallett uint64_t itr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */ 2985215976Sjmallett uint64_t imr_wtto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */ 2986215976Sjmallett uint64_t imr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */ 2987215976Sjmallett uint64_t itr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */ 2988215976Sjmallett#else 2989215976Sjmallett uint64_t itr_wabt : 1; 2990215976Sjmallett uint64_t imr_wabt : 1; 2991215976Sjmallett uint64_t imr_wtto : 1; 2992215976Sjmallett uint64_t itr_abt : 1; 2993215976Sjmallett uint64_t imr_abt : 1; 2994215976Sjmallett uint64_t imr_tto : 1; 2995215976Sjmallett uint64_t imsi_per : 1; 2996215976Sjmallett uint64_t imsi_tabt : 1; 2997215976Sjmallett uint64_t imsi_mabt : 1; 2998215976Sjmallett uint64_t imsc_msg : 1; 2999215976Sjmallett uint64_t itsr_abt : 1; 3000215976Sjmallett uint64_t iserr : 1; 3001215976Sjmallett uint64_t iaperr : 1; 3002215976Sjmallett uint64_t idperr : 1; 3003215976Sjmallett uint64_t ill_rwr : 1; 3004215976Sjmallett uint64_t ill_rrd : 1; 3005215976Sjmallett uint64_t irsl_int : 1; 3006215976Sjmallett uint64_t ipcnt0 : 1; 3007215976Sjmallett uint64_t ipcnt1 : 1; 3008215976Sjmallett uint64_t reserved_19_20 : 2; 3009215976Sjmallett uint64_t iptime0 : 1; 3010215976Sjmallett uint64_t iptime1 : 1; 3011215976Sjmallett uint64_t reserved_23_24 : 2; 3012215976Sjmallett uint64_t idcnt0 : 1; 3013215976Sjmallett uint64_t idcnt1 : 1; 3014215976Sjmallett uint64_t idtime0 : 1; 3015215976Sjmallett uint64_t idtime1 : 1; 3016215976Sjmallett uint64_t dma0_fi : 1; 3017215976Sjmallett uint64_t dma1_fi : 1; 3018215976Sjmallett uint64_t win_wr : 1; 3019215976Sjmallett uint64_t ill_wr : 1; 3020215976Sjmallett uint64_t ill_rd : 1; 3021215976Sjmallett uint64_t reserved_34_63 : 30; 3022215976Sjmallett#endif 3023215976Sjmallett } cn31xx; 3024215976Sjmallett struct cvmx_pci_int_enb_s cn38xx; 3025215976Sjmallett struct cvmx_pci_int_enb_s cn38xxp2; 3026215976Sjmallett struct cvmx_pci_int_enb_cn31xx cn50xx; 3027215976Sjmallett struct cvmx_pci_int_enb_s cn58xx; 3028215976Sjmallett struct cvmx_pci_int_enb_s cn58xxp1; 3029215976Sjmallett}; 3030215976Sjmalletttypedef union cvmx_pci_int_enb cvmx_pci_int_enb_t; 3031215976Sjmallett 3032215976Sjmallett/** 3033215976Sjmallett * cvmx_pci_int_enb2 3034215976Sjmallett * 3035215976Sjmallett * PCI_INT_ENB2 = PCI Interrupt Enable2 Register 3036215976Sjmallett * 3037215976Sjmallett * Enables interrupt bits in the PCI_INT_SUM2 register. 3038215976Sjmallett */ 3039232812Sjmallettunion cvmx_pci_int_enb2 { 3040215976Sjmallett uint64_t u64; 3041232812Sjmallett struct cvmx_pci_int_enb2_s { 3042232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3043215976Sjmallett uint64_t reserved_34_63 : 30; 3044215976Sjmallett uint64_t ill_rd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */ 3045215976Sjmallett uint64_t ill_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */ 3046215976Sjmallett uint64_t win_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */ 3047215976Sjmallett uint64_t dma1_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */ 3048215976Sjmallett uint64_t dma0_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */ 3049215976Sjmallett uint64_t rdtime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */ 3050215976Sjmallett uint64_t rdtime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */ 3051215976Sjmallett uint64_t rdcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */ 3052215976Sjmallett uint64_t rdcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */ 3053215976Sjmallett uint64_t rptime3 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[24] */ 3054215976Sjmallett uint64_t rptime2 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[23] */ 3055215976Sjmallett uint64_t rptime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[22] */ 3056215976Sjmallett uint64_t rptime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */ 3057215976Sjmallett uint64_t rpcnt3 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[20] */ 3058215976Sjmallett uint64_t rpcnt2 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[19] */ 3059215976Sjmallett uint64_t rpcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[18] */ 3060215976Sjmallett uint64_t rpcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */ 3061215976Sjmallett uint64_t rrsl_int : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */ 3062215976Sjmallett uint64_t ill_rrd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */ 3063215976Sjmallett uint64_t ill_rwr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */ 3064215976Sjmallett uint64_t rdperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */ 3065215976Sjmallett uint64_t raperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */ 3066215976Sjmallett uint64_t rserr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */ 3067215976Sjmallett uint64_t rtsr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */ 3068215976Sjmallett uint64_t rmsc_msg : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */ 3069215976Sjmallett uint64_t rmsi_mabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */ 3070215976Sjmallett uint64_t rmsi_tabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */ 3071215976Sjmallett uint64_t rmsi_per : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */ 3072215976Sjmallett uint64_t rmr_tto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */ 3073215976Sjmallett uint64_t rmr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */ 3074215976Sjmallett uint64_t rtr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */ 3075215976Sjmallett uint64_t rmr_wtto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */ 3076215976Sjmallett uint64_t rmr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */ 3077215976Sjmallett uint64_t rtr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */ 3078215976Sjmallett#else 3079215976Sjmallett uint64_t rtr_wabt : 1; 3080215976Sjmallett uint64_t rmr_wabt : 1; 3081215976Sjmallett uint64_t rmr_wtto : 1; 3082215976Sjmallett uint64_t rtr_abt : 1; 3083215976Sjmallett uint64_t rmr_abt : 1; 3084215976Sjmallett uint64_t rmr_tto : 1; 3085215976Sjmallett uint64_t rmsi_per : 1; 3086215976Sjmallett uint64_t rmsi_tabt : 1; 3087215976Sjmallett uint64_t rmsi_mabt : 1; 3088215976Sjmallett uint64_t rmsc_msg : 1; 3089215976Sjmallett uint64_t rtsr_abt : 1; 3090215976Sjmallett uint64_t rserr : 1; 3091215976Sjmallett uint64_t raperr : 1; 3092215976Sjmallett uint64_t rdperr : 1; 3093215976Sjmallett uint64_t ill_rwr : 1; 3094215976Sjmallett uint64_t ill_rrd : 1; 3095215976Sjmallett uint64_t rrsl_int : 1; 3096215976Sjmallett uint64_t rpcnt0 : 1; 3097215976Sjmallett uint64_t rpcnt1 : 1; 3098215976Sjmallett uint64_t rpcnt2 : 1; 3099215976Sjmallett uint64_t rpcnt3 : 1; 3100215976Sjmallett uint64_t rptime0 : 1; 3101215976Sjmallett uint64_t rptime1 : 1; 3102215976Sjmallett uint64_t rptime2 : 1; 3103215976Sjmallett uint64_t rptime3 : 1; 3104215976Sjmallett uint64_t rdcnt0 : 1; 3105215976Sjmallett uint64_t rdcnt1 : 1; 3106215976Sjmallett uint64_t rdtime0 : 1; 3107215976Sjmallett uint64_t rdtime1 : 1; 3108215976Sjmallett uint64_t dma0_fi : 1; 3109215976Sjmallett uint64_t dma1_fi : 1; 3110215976Sjmallett uint64_t win_wr : 1; 3111215976Sjmallett uint64_t ill_wr : 1; 3112215976Sjmallett uint64_t ill_rd : 1; 3113215976Sjmallett uint64_t reserved_34_63 : 30; 3114215976Sjmallett#endif 3115215976Sjmallett } s; 3116232812Sjmallett struct cvmx_pci_int_enb2_cn30xx { 3117232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3118215976Sjmallett uint64_t reserved_34_63 : 30; 3119215976Sjmallett uint64_t ill_rd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */ 3120215976Sjmallett uint64_t ill_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */ 3121215976Sjmallett uint64_t win_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */ 3122215976Sjmallett uint64_t dma1_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */ 3123215976Sjmallett uint64_t dma0_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */ 3124215976Sjmallett uint64_t rdtime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */ 3125215976Sjmallett uint64_t rdtime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */ 3126215976Sjmallett uint64_t rdcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */ 3127215976Sjmallett uint64_t rdcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */ 3128215976Sjmallett uint64_t reserved_22_24 : 3; 3129215976Sjmallett uint64_t rptime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */ 3130215976Sjmallett uint64_t reserved_18_20 : 3; 3131215976Sjmallett uint64_t rpcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */ 3132215976Sjmallett uint64_t rrsl_int : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */ 3133215976Sjmallett uint64_t ill_rrd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */ 3134215976Sjmallett uint64_t ill_rwr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */ 3135215976Sjmallett uint64_t rdperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */ 3136215976Sjmallett uint64_t raperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */ 3137215976Sjmallett uint64_t rserr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */ 3138215976Sjmallett uint64_t rtsr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */ 3139215976Sjmallett uint64_t rmsc_msg : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */ 3140215976Sjmallett uint64_t rmsi_mabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */ 3141215976Sjmallett uint64_t rmsi_tabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */ 3142215976Sjmallett uint64_t rmsi_per : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */ 3143215976Sjmallett uint64_t rmr_tto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */ 3144215976Sjmallett uint64_t rmr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */ 3145215976Sjmallett uint64_t rtr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */ 3146215976Sjmallett uint64_t rmr_wtto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */ 3147215976Sjmallett uint64_t rmr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */ 3148215976Sjmallett uint64_t rtr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */ 3149215976Sjmallett#else 3150215976Sjmallett uint64_t rtr_wabt : 1; 3151215976Sjmallett uint64_t rmr_wabt : 1; 3152215976Sjmallett uint64_t rmr_wtto : 1; 3153215976Sjmallett uint64_t rtr_abt : 1; 3154215976Sjmallett uint64_t rmr_abt : 1; 3155215976Sjmallett uint64_t rmr_tto : 1; 3156215976Sjmallett uint64_t rmsi_per : 1; 3157215976Sjmallett uint64_t rmsi_tabt : 1; 3158215976Sjmallett uint64_t rmsi_mabt : 1; 3159215976Sjmallett uint64_t rmsc_msg : 1; 3160215976Sjmallett uint64_t rtsr_abt : 1; 3161215976Sjmallett uint64_t rserr : 1; 3162215976Sjmallett uint64_t raperr : 1; 3163215976Sjmallett uint64_t rdperr : 1; 3164215976Sjmallett uint64_t ill_rwr : 1; 3165215976Sjmallett uint64_t ill_rrd : 1; 3166215976Sjmallett uint64_t rrsl_int : 1; 3167215976Sjmallett uint64_t rpcnt0 : 1; 3168215976Sjmallett uint64_t reserved_18_20 : 3; 3169215976Sjmallett uint64_t rptime0 : 1; 3170215976Sjmallett uint64_t reserved_22_24 : 3; 3171215976Sjmallett uint64_t rdcnt0 : 1; 3172215976Sjmallett uint64_t rdcnt1 : 1; 3173215976Sjmallett uint64_t rdtime0 : 1; 3174215976Sjmallett uint64_t rdtime1 : 1; 3175215976Sjmallett uint64_t dma0_fi : 1; 3176215976Sjmallett uint64_t dma1_fi : 1; 3177215976Sjmallett uint64_t win_wr : 1; 3178215976Sjmallett uint64_t ill_wr : 1; 3179215976Sjmallett uint64_t ill_rd : 1; 3180215976Sjmallett uint64_t reserved_34_63 : 30; 3181215976Sjmallett#endif 3182215976Sjmallett } cn30xx; 3183232812Sjmallett struct cvmx_pci_int_enb2_cn31xx { 3184232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3185215976Sjmallett uint64_t reserved_34_63 : 30; 3186215976Sjmallett uint64_t ill_rd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */ 3187215976Sjmallett uint64_t ill_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */ 3188215976Sjmallett uint64_t win_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */ 3189215976Sjmallett uint64_t dma1_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */ 3190215976Sjmallett uint64_t dma0_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */ 3191215976Sjmallett uint64_t rdtime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */ 3192215976Sjmallett uint64_t rdtime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */ 3193215976Sjmallett uint64_t rdcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */ 3194215976Sjmallett uint64_t rdcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */ 3195215976Sjmallett uint64_t reserved_23_24 : 2; 3196215976Sjmallett uint64_t rptime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[22] */ 3197215976Sjmallett uint64_t rptime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */ 3198215976Sjmallett uint64_t reserved_19_20 : 2; 3199215976Sjmallett uint64_t rpcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[18] */ 3200215976Sjmallett uint64_t rpcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */ 3201215976Sjmallett uint64_t rrsl_int : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */ 3202215976Sjmallett uint64_t ill_rrd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */ 3203215976Sjmallett uint64_t ill_rwr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */ 3204215976Sjmallett uint64_t rdperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */ 3205215976Sjmallett uint64_t raperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */ 3206215976Sjmallett uint64_t rserr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */ 3207215976Sjmallett uint64_t rtsr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */ 3208215976Sjmallett uint64_t rmsc_msg : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */ 3209215976Sjmallett uint64_t rmsi_mabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */ 3210215976Sjmallett uint64_t rmsi_tabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */ 3211215976Sjmallett uint64_t rmsi_per : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */ 3212215976Sjmallett uint64_t rmr_tto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */ 3213215976Sjmallett uint64_t rmr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */ 3214215976Sjmallett uint64_t rtr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */ 3215215976Sjmallett uint64_t rmr_wtto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */ 3216215976Sjmallett uint64_t rmr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */ 3217215976Sjmallett uint64_t rtr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */ 3218215976Sjmallett#else 3219215976Sjmallett uint64_t rtr_wabt : 1; 3220215976Sjmallett uint64_t rmr_wabt : 1; 3221215976Sjmallett uint64_t rmr_wtto : 1; 3222215976Sjmallett uint64_t rtr_abt : 1; 3223215976Sjmallett uint64_t rmr_abt : 1; 3224215976Sjmallett uint64_t rmr_tto : 1; 3225215976Sjmallett uint64_t rmsi_per : 1; 3226215976Sjmallett uint64_t rmsi_tabt : 1; 3227215976Sjmallett uint64_t rmsi_mabt : 1; 3228215976Sjmallett uint64_t rmsc_msg : 1; 3229215976Sjmallett uint64_t rtsr_abt : 1; 3230215976Sjmallett uint64_t rserr : 1; 3231215976Sjmallett uint64_t raperr : 1; 3232215976Sjmallett uint64_t rdperr : 1; 3233215976Sjmallett uint64_t ill_rwr : 1; 3234215976Sjmallett uint64_t ill_rrd : 1; 3235215976Sjmallett uint64_t rrsl_int : 1; 3236215976Sjmallett uint64_t rpcnt0 : 1; 3237215976Sjmallett uint64_t rpcnt1 : 1; 3238215976Sjmallett uint64_t reserved_19_20 : 2; 3239215976Sjmallett uint64_t rptime0 : 1; 3240215976Sjmallett uint64_t rptime1 : 1; 3241215976Sjmallett uint64_t reserved_23_24 : 2; 3242215976Sjmallett uint64_t rdcnt0 : 1; 3243215976Sjmallett uint64_t rdcnt1 : 1; 3244215976Sjmallett uint64_t rdtime0 : 1; 3245215976Sjmallett uint64_t rdtime1 : 1; 3246215976Sjmallett uint64_t dma0_fi : 1; 3247215976Sjmallett uint64_t dma1_fi : 1; 3248215976Sjmallett uint64_t win_wr : 1; 3249215976Sjmallett uint64_t ill_wr : 1; 3250215976Sjmallett uint64_t ill_rd : 1; 3251215976Sjmallett uint64_t reserved_34_63 : 30; 3252215976Sjmallett#endif 3253215976Sjmallett } cn31xx; 3254215976Sjmallett struct cvmx_pci_int_enb2_s cn38xx; 3255215976Sjmallett struct cvmx_pci_int_enb2_s cn38xxp2; 3256215976Sjmallett struct cvmx_pci_int_enb2_cn31xx cn50xx; 3257215976Sjmallett struct cvmx_pci_int_enb2_s cn58xx; 3258215976Sjmallett struct cvmx_pci_int_enb2_s cn58xxp1; 3259215976Sjmallett}; 3260215976Sjmalletttypedef union cvmx_pci_int_enb2 cvmx_pci_int_enb2_t; 3261215976Sjmallett 3262215976Sjmallett/** 3263215976Sjmallett * cvmx_pci_int_sum 3264215976Sjmallett * 3265215976Sjmallett * PCI_INT_SUM = PCI Interrupt Summary 3266215976Sjmallett * 3267215976Sjmallett * The PCI Interrupt Summary Register. 3268215976Sjmallett */ 3269232812Sjmallettunion cvmx_pci_int_sum { 3270215976Sjmallett uint64_t u64; 3271232812Sjmallett struct cvmx_pci_int_sum_s { 3272232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3273215976Sjmallett uint64_t reserved_34_63 : 30; 3274215976Sjmallett uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3275215976Sjmallett when the mem area is disabled. */ 3276215976Sjmallett uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3277215976Sjmallett when the mem area is disabled. */ 3278215976Sjmallett uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3279215976Sjmallett Read-Address Register took place. */ 3280215976Sjmallett uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3281215976Sjmallett required to set the FORCE-INT bit for counter 1. */ 3282215976Sjmallett uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3283215976Sjmallett required to set the FORCE-INT bit for counter 0. */ 3284215976Sjmallett uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3285215976Sjmallett register is not 0 the DMA_CNT1 timer counts. 3286215976Sjmallett When the DMA1_CNT timer has a value greater 3287215976Sjmallett than the PCI_DMA_TIME1 register this 3288215976Sjmallett bit is set. The timer is reset when bit is 3289215976Sjmallett written with a one. */ 3290215976Sjmallett uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3291215976Sjmallett register is not 0 the DMA_CNT0 timer counts. 3292215976Sjmallett When the DMA0_CNT timer has a value greater 3293215976Sjmallett than the PCI_DMA_TIME0 register this 3294215976Sjmallett bit is set. The timer is reset when bit is 3295215976Sjmallett written with a one. */ 3296215976Sjmallett uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3297215976Sjmallett value is greater than the value 3298215976Sjmallett in the PCI_DMA_INT_LEV1 register. */ 3299215976Sjmallett uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3300215976Sjmallett value is greater than the value 3301215976Sjmallett in the PCI_DMA_INT_LEV0 register. */ 3302215976Sjmallett uint64_t ptime3 : 1; /**< When the value in the PCI_PKTS_SENT3 3303215976Sjmallett register is not 0 the Sent-3 timer counts. 3304215976Sjmallett When the Sent-3 timer has a value greater 3305215976Sjmallett than the PCI_PKTS_SENT_TIME3 register this 3306215976Sjmallett bit is set. The timer is reset when bit is 3307215976Sjmallett written with a one. */ 3308215976Sjmallett uint64_t ptime2 : 1; /**< When the value in the PCI_PKTS_SENT2 3309215976Sjmallett register is not 0 the Sent-2 timer counts. 3310215976Sjmallett When the Sent-2 timer has a value greater 3311215976Sjmallett than the PCI_PKTS_SENT_TIME2 register this 3312215976Sjmallett bit is set. The timer is reset when bit is 3313215976Sjmallett written with a one. */ 3314215976Sjmallett uint64_t ptime1 : 1; /**< When the value in the PCI_PKTS_SENT1 3315215976Sjmallett register is not 0 the Sent-1 timer counts. 3316215976Sjmallett When the Sent-1 timer has a value greater 3317215976Sjmallett than the PCI_PKTS_SENT_TIME1 register this 3318215976Sjmallett bit is set. The timer is reset when bit is 3319215976Sjmallett written with a one. */ 3320215976Sjmallett uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3321215976Sjmallett register is not 0 the Sent-0 timer counts. 3322215976Sjmallett When the Sent-0 timer has a value greater 3323215976Sjmallett than the PCI_PKTS_SENT_TIME0 register this 3324215976Sjmallett bit is set. The timer is reset when bit is 3325215976Sjmallett written with a one. */ 3326215976Sjmallett uint64_t pcnt3 : 1; /**< This bit indicates that PCI_PKTS_SENT3 3327215976Sjmallett value is greater than the value 3328215976Sjmallett in the PCI_PKTS_SENT_INT_LEV3 register. */ 3329215976Sjmallett uint64_t pcnt2 : 1; /**< This bit indicates that PCI_PKTS_SENT2 3330215976Sjmallett value is greater than the value 3331215976Sjmallett in the PCI_PKTS_SENT_INT_LEV2 register. */ 3332215976Sjmallett uint64_t pcnt1 : 1; /**< This bit indicates that PCI_PKTS_SENT1 3333215976Sjmallett value is greater than the value 3334215976Sjmallett in the PCI_PKTS_SENT_INT_LEV1 register. */ 3335215976Sjmallett uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3336215976Sjmallett value is greater than the value 3337215976Sjmallett in the PCI_PKTS_SENT_INT_LEV0 register. */ 3338215976Sjmallett uint64_t rsl_int : 1; /**< This bit is set when the mio_pci_inta_dr wire 3339215976Sjmallett is asserted by the MIO. */ 3340215976Sjmallett uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3341215976Sjmallett uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3342215976Sjmallett uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3343215976Sjmallett uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3344215976Sjmallett uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3345215976Sjmallett uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected 3346215976Sjmallett CN58XX (as completer), has encountered an error 3347215976Sjmallett which prevents the split transaction from 3348215976Sjmallett completing. In this event, the CN58XX (as completer), 3349215976Sjmallett sends a SCM (Split Completion Message) to the 3350215976Sjmallett initiator. See: PCIX Spec v1.0a Fig 2-40. 3351215976Sjmallett [31:28]: Message Class = 2(completer error) 3352215976Sjmallett [27:20]: Message Index = 0x80 3353215976Sjmallett [18:12]: Remaining Lower Address 3354215976Sjmallett [11:0]: Remaining Byte Count */ 3355215976Sjmallett uint64_t msc_msg : 1; /**< Master Split Completion Message (SCM) Detected 3356215976Sjmallett for either a Split-Read/Write error case. 3357215976Sjmallett Set if: 3358215976Sjmallett a) A Split-Write SCM is detected with SCE=1. 3359215976Sjmallett b) A Split-Read SCM is detected (regardless 3360215976Sjmallett of SCE status). 3361215976Sjmallett The Split completion message(SCM) 3362215976Sjmallett is also latched into the PCI_SCM_REG[SCM] to 3363215976Sjmallett assist SW with error recovery. */ 3364215976Sjmallett uint64_t msi_mabt : 1; /**< PCI Master Abort on Master MSI */ 3365215976Sjmallett uint64_t msi_tabt : 1; /**< PCI Target-Abort on Master MSI */ 3366215976Sjmallett uint64_t msi_per : 1; /**< PCI Parity Error on Master MSI */ 3367215976Sjmallett uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Master-Read */ 3368215976Sjmallett uint64_t mr_abt : 1; /**< PCI Master Abort On Master-Read */ 3369215976Sjmallett uint64_t tr_abt : 1; /**< PCI Target Abort On Master-Read */ 3370215976Sjmallett uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on Master-write */ 3371215976Sjmallett uint64_t mr_wabt : 1; /**< PCI Master Abort detected on Master-write */ 3372215976Sjmallett uint64_t tr_wabt : 1; /**< PCI Target Abort detected on Master-write */ 3373215976Sjmallett#else 3374215976Sjmallett uint64_t tr_wabt : 1; 3375215976Sjmallett uint64_t mr_wabt : 1; 3376215976Sjmallett uint64_t mr_wtto : 1; 3377215976Sjmallett uint64_t tr_abt : 1; 3378215976Sjmallett uint64_t mr_abt : 1; 3379215976Sjmallett uint64_t mr_tto : 1; 3380215976Sjmallett uint64_t msi_per : 1; 3381215976Sjmallett uint64_t msi_tabt : 1; 3382215976Sjmallett uint64_t msi_mabt : 1; 3383215976Sjmallett uint64_t msc_msg : 1; 3384215976Sjmallett uint64_t tsr_abt : 1; 3385215976Sjmallett uint64_t serr : 1; 3386215976Sjmallett uint64_t aperr : 1; 3387215976Sjmallett uint64_t dperr : 1; 3388215976Sjmallett uint64_t ill_rwr : 1; 3389215976Sjmallett uint64_t ill_rrd : 1; 3390215976Sjmallett uint64_t rsl_int : 1; 3391215976Sjmallett uint64_t pcnt0 : 1; 3392215976Sjmallett uint64_t pcnt1 : 1; 3393215976Sjmallett uint64_t pcnt2 : 1; 3394215976Sjmallett uint64_t pcnt3 : 1; 3395215976Sjmallett uint64_t ptime0 : 1; 3396215976Sjmallett uint64_t ptime1 : 1; 3397215976Sjmallett uint64_t ptime2 : 1; 3398215976Sjmallett uint64_t ptime3 : 1; 3399215976Sjmallett uint64_t dcnt0 : 1; 3400215976Sjmallett uint64_t dcnt1 : 1; 3401215976Sjmallett uint64_t dtime0 : 1; 3402215976Sjmallett uint64_t dtime1 : 1; 3403215976Sjmallett uint64_t dma0_fi : 1; 3404215976Sjmallett uint64_t dma1_fi : 1; 3405215976Sjmallett uint64_t win_wr : 1; 3406215976Sjmallett uint64_t ill_wr : 1; 3407215976Sjmallett uint64_t ill_rd : 1; 3408215976Sjmallett uint64_t reserved_34_63 : 30; 3409215976Sjmallett#endif 3410215976Sjmallett } s; 3411232812Sjmallett struct cvmx_pci_int_sum_cn30xx { 3412232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3413215976Sjmallett uint64_t reserved_34_63 : 30; 3414215976Sjmallett uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3415215976Sjmallett when the mem area is disabled. */ 3416215976Sjmallett uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3417215976Sjmallett when the mem area is disabled. */ 3418215976Sjmallett uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3419215976Sjmallett Read-Address Register took place. */ 3420215976Sjmallett uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3421215976Sjmallett required to set the FORCE-INT bit for counter 1. */ 3422215976Sjmallett uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3423215976Sjmallett required to set the FORCE-INT bit for counter 0. */ 3424215976Sjmallett uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3425215976Sjmallett register is not 0 the DMA_CNT1 timer counts. 3426215976Sjmallett When the DMA1_CNT timer has a value greater 3427215976Sjmallett than the PCI_DMA_TIME1 register this 3428215976Sjmallett bit is set. The timer is reset when bit is 3429215976Sjmallett written with a one. */ 3430215976Sjmallett uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3431215976Sjmallett register is not 0 the DMA_CNT0 timer counts. 3432215976Sjmallett When the DMA0_CNT timer has a value greater 3433215976Sjmallett than the PCI_DMA_TIME0 register this 3434215976Sjmallett bit is set. The timer is reset when bit is 3435215976Sjmallett written with a one. */ 3436215976Sjmallett uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3437215976Sjmallett value is greater than the value 3438215976Sjmallett in the PCI_DMA_INT_LEV1 register. */ 3439215976Sjmallett uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3440215976Sjmallett value is greater than the value 3441215976Sjmallett in the PCI_DMA_INT_LEV0 register. */ 3442215976Sjmallett uint64_t reserved_22_24 : 3; 3443215976Sjmallett uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3444215976Sjmallett register is not 0 the Sent-0 timer counts. 3445215976Sjmallett When the Sent-0 timer has a value greater 3446215976Sjmallett than the PCI_PKTS_SENT_TIME0 register this 3447215976Sjmallett bit is set. The timer is reset when bit is 3448215976Sjmallett written with a one. */ 3449215976Sjmallett uint64_t reserved_18_20 : 3; 3450215976Sjmallett uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3451215976Sjmallett value is greater than the value 3452215976Sjmallett in the PCI_PKTS_SENT_INT_LEV0 register. */ 3453215976Sjmallett uint64_t rsl_int : 1; /**< This bit is set when the mio_pci_inta_dr wire 3454215976Sjmallett is asserted by the MIO */ 3455215976Sjmallett uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3456215976Sjmallett uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3457215976Sjmallett uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3458215976Sjmallett uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3459215976Sjmallett uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3460215976Sjmallett uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected 3461215976Sjmallett N3K (as completer), has encountered an error 3462215976Sjmallett which prevents the split transaction from 3463215976Sjmallett completing. In this event, the N3K (as completer), 3464215976Sjmallett sends a SCM (Split Completion Message) to the 3465215976Sjmallett initiator. See: PCIX Spec v1.0a Fig 2-40. 3466215976Sjmallett [31:28]: Message Class = 2(completer error) 3467215976Sjmallett [27:20]: Message Index = 0x80 3468215976Sjmallett [18:12]: Remaining Lower Address 3469215976Sjmallett [11:0]: Remaining Byte Count */ 3470215976Sjmallett uint64_t msc_msg : 1; /**< Master Split Completion Message (SCM) Detected 3471215976Sjmallett for either a Split-Read/Write error case. 3472215976Sjmallett Set if: 3473215976Sjmallett a) A Split-Write SCM is detected with SCE=1. 3474215976Sjmallett b) A Split-Read SCM is detected (regardless 3475215976Sjmallett of SCE status). 3476215976Sjmallett The Split completion message(SCM) 3477215976Sjmallett is also latched into the PCI_SCM_REG[SCM] to 3478215976Sjmallett assist SW with error recovery. */ 3479215976Sjmallett uint64_t msi_mabt : 1; /**< PCI Master Abort on Master MSI */ 3480215976Sjmallett uint64_t msi_tabt : 1; /**< PCI Target-Abort on Master MSI */ 3481215976Sjmallett uint64_t msi_per : 1; /**< PCI Parity Error on Master MSI */ 3482215976Sjmallett uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Master-Read */ 3483215976Sjmallett uint64_t mr_abt : 1; /**< PCI Master Abort On Master-Read */ 3484215976Sjmallett uint64_t tr_abt : 1; /**< PCI Target Abort On Master-Read */ 3485215976Sjmallett uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on Master-write */ 3486215976Sjmallett uint64_t mr_wabt : 1; /**< PCI Master Abort detected on Master-write */ 3487215976Sjmallett uint64_t tr_wabt : 1; /**< PCI Target Abort detected on Master-write */ 3488215976Sjmallett#else 3489215976Sjmallett uint64_t tr_wabt : 1; 3490215976Sjmallett uint64_t mr_wabt : 1; 3491215976Sjmallett uint64_t mr_wtto : 1; 3492215976Sjmallett uint64_t tr_abt : 1; 3493215976Sjmallett uint64_t mr_abt : 1; 3494215976Sjmallett uint64_t mr_tto : 1; 3495215976Sjmallett uint64_t msi_per : 1; 3496215976Sjmallett uint64_t msi_tabt : 1; 3497215976Sjmallett uint64_t msi_mabt : 1; 3498215976Sjmallett uint64_t msc_msg : 1; 3499215976Sjmallett uint64_t tsr_abt : 1; 3500215976Sjmallett uint64_t serr : 1; 3501215976Sjmallett uint64_t aperr : 1; 3502215976Sjmallett uint64_t dperr : 1; 3503215976Sjmallett uint64_t ill_rwr : 1; 3504215976Sjmallett uint64_t ill_rrd : 1; 3505215976Sjmallett uint64_t rsl_int : 1; 3506215976Sjmallett uint64_t pcnt0 : 1; 3507215976Sjmallett uint64_t reserved_18_20 : 3; 3508215976Sjmallett uint64_t ptime0 : 1; 3509215976Sjmallett uint64_t reserved_22_24 : 3; 3510215976Sjmallett uint64_t dcnt0 : 1; 3511215976Sjmallett uint64_t dcnt1 : 1; 3512215976Sjmallett uint64_t dtime0 : 1; 3513215976Sjmallett uint64_t dtime1 : 1; 3514215976Sjmallett uint64_t dma0_fi : 1; 3515215976Sjmallett uint64_t dma1_fi : 1; 3516215976Sjmallett uint64_t win_wr : 1; 3517215976Sjmallett uint64_t ill_wr : 1; 3518215976Sjmallett uint64_t ill_rd : 1; 3519215976Sjmallett uint64_t reserved_34_63 : 30; 3520215976Sjmallett#endif 3521215976Sjmallett } cn30xx; 3522232812Sjmallett struct cvmx_pci_int_sum_cn31xx { 3523232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3524215976Sjmallett uint64_t reserved_34_63 : 30; 3525215976Sjmallett uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3526215976Sjmallett when the mem area is disabled. */ 3527215976Sjmallett uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3528215976Sjmallett when the mem area is disabled. */ 3529215976Sjmallett uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3530215976Sjmallett Read-Address Register took place. */ 3531215976Sjmallett uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3532215976Sjmallett required to set the FORCE-INT bit for counter 1. */ 3533215976Sjmallett uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3534215976Sjmallett required to set the FORCE-INT bit for counter 0. */ 3535215976Sjmallett uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3536215976Sjmallett register is not 0 the DMA_CNT1 timer counts. 3537215976Sjmallett When the DMA1_CNT timer has a value greater 3538215976Sjmallett than the PCI_DMA_TIME1 register this 3539215976Sjmallett bit is set. The timer is reset when bit is 3540215976Sjmallett written with a one. */ 3541215976Sjmallett uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3542215976Sjmallett register is not 0 the DMA_CNT0 timer counts. 3543215976Sjmallett When the DMA0_CNT timer has a value greater 3544215976Sjmallett than the PCI_DMA_TIME0 register this 3545215976Sjmallett bit is set. The timer is reset when bit is 3546215976Sjmallett written with a one. */ 3547215976Sjmallett uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3548215976Sjmallett value is greater than the value 3549215976Sjmallett in the PCI_DMA_INT_LEV1 register. */ 3550215976Sjmallett uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3551215976Sjmallett value is greater than the value 3552215976Sjmallett in the PCI_DMA_INT_LEV0 register. */ 3553215976Sjmallett uint64_t reserved_23_24 : 2; 3554215976Sjmallett uint64_t ptime1 : 1; /**< When the value in the PCI_PKTS_SENT1 3555215976Sjmallett register is not 0 the Sent-1 timer counts. 3556215976Sjmallett When the Sent-1 timer has a value greater 3557215976Sjmallett than the PCI_PKTS_SENT_TIME1 register this 3558215976Sjmallett bit is set. The timer is reset when bit is 3559215976Sjmallett written with a one. */ 3560215976Sjmallett uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3561215976Sjmallett register is not 0 the Sent-0 timer counts. 3562215976Sjmallett When the Sent-0 timer has a value greater 3563215976Sjmallett than the PCI_PKTS_SENT_TIME0 register this 3564215976Sjmallett bit is set. The timer is reset when bit is 3565215976Sjmallett written with a one. */ 3566215976Sjmallett uint64_t reserved_19_20 : 2; 3567215976Sjmallett uint64_t pcnt1 : 1; /**< This bit indicates that PCI_PKTS_SENT1 3568215976Sjmallett value is greater than the value 3569215976Sjmallett in the PCI_PKTS_SENT_INT_LEV1 register. */ 3570215976Sjmallett uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3571215976Sjmallett value is greater than the value 3572215976Sjmallett in the PCI_PKTS_SENT_INT_LEV0 register. */ 3573215976Sjmallett uint64_t rsl_int : 1; /**< This bit is set when the mio_pci_inta_dr wire 3574215976Sjmallett is asserted by the MIO */ 3575215976Sjmallett uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3576215976Sjmallett uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3577215976Sjmallett uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3578215976Sjmallett uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3579215976Sjmallett uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3580215976Sjmallett uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected 3581215976Sjmallett N3K (as completer), has encountered an error 3582215976Sjmallett which prevents the split transaction from 3583215976Sjmallett completing. In this event, the N3K (as completer), 3584215976Sjmallett sends a SCM (Split Completion Message) to the 3585215976Sjmallett initiator. See: PCIX Spec v1.0a Fig 2-40. 3586215976Sjmallett [31:28]: Message Class = 2(completer error) 3587215976Sjmallett [27:20]: Message Index = 0x80 3588215976Sjmallett [18:12]: Remaining Lower Address 3589215976Sjmallett [11:0]: Remaining Byte Count */ 3590215976Sjmallett uint64_t msc_msg : 1; /**< Master Split Completion Message (SCM) Detected 3591215976Sjmallett for either a Split-Read/Write error case. 3592215976Sjmallett Set if: 3593215976Sjmallett a) A Split-Write SCM is detected with SCE=1. 3594215976Sjmallett b) A Split-Read SCM is detected (regardless 3595215976Sjmallett of SCE status). 3596215976Sjmallett The Split completion message(SCM) 3597215976Sjmallett is also latched into the PCI_SCM_REG[SCM] to 3598215976Sjmallett assist SW with error recovery. */ 3599215976Sjmallett uint64_t msi_mabt : 1; /**< PCI Master Abort on Master MSI */ 3600215976Sjmallett uint64_t msi_tabt : 1; /**< PCI Target-Abort on Master MSI */ 3601215976Sjmallett uint64_t msi_per : 1; /**< PCI Parity Error on Master MSI */ 3602215976Sjmallett uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Master-Read */ 3603215976Sjmallett uint64_t mr_abt : 1; /**< PCI Master Abort On Master-Read */ 3604215976Sjmallett uint64_t tr_abt : 1; /**< PCI Target Abort On Master-Read */ 3605215976Sjmallett uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on Master-write */ 3606215976Sjmallett uint64_t mr_wabt : 1; /**< PCI Master Abort detected on Master-write */ 3607215976Sjmallett uint64_t tr_wabt : 1; /**< PCI Target Abort detected on Master-write */ 3608215976Sjmallett#else 3609215976Sjmallett uint64_t tr_wabt : 1; 3610215976Sjmallett uint64_t mr_wabt : 1; 3611215976Sjmallett uint64_t mr_wtto : 1; 3612215976Sjmallett uint64_t tr_abt : 1; 3613215976Sjmallett uint64_t mr_abt : 1; 3614215976Sjmallett uint64_t mr_tto : 1; 3615215976Sjmallett uint64_t msi_per : 1; 3616215976Sjmallett uint64_t msi_tabt : 1; 3617215976Sjmallett uint64_t msi_mabt : 1; 3618215976Sjmallett uint64_t msc_msg : 1; 3619215976Sjmallett uint64_t tsr_abt : 1; 3620215976Sjmallett uint64_t serr : 1; 3621215976Sjmallett uint64_t aperr : 1; 3622215976Sjmallett uint64_t dperr : 1; 3623215976Sjmallett uint64_t ill_rwr : 1; 3624215976Sjmallett uint64_t ill_rrd : 1; 3625215976Sjmallett uint64_t rsl_int : 1; 3626215976Sjmallett uint64_t pcnt0 : 1; 3627215976Sjmallett uint64_t pcnt1 : 1; 3628215976Sjmallett uint64_t reserved_19_20 : 2; 3629215976Sjmallett uint64_t ptime0 : 1; 3630215976Sjmallett uint64_t ptime1 : 1; 3631215976Sjmallett uint64_t reserved_23_24 : 2; 3632215976Sjmallett uint64_t dcnt0 : 1; 3633215976Sjmallett uint64_t dcnt1 : 1; 3634215976Sjmallett uint64_t dtime0 : 1; 3635215976Sjmallett uint64_t dtime1 : 1; 3636215976Sjmallett uint64_t dma0_fi : 1; 3637215976Sjmallett uint64_t dma1_fi : 1; 3638215976Sjmallett uint64_t win_wr : 1; 3639215976Sjmallett uint64_t ill_wr : 1; 3640215976Sjmallett uint64_t ill_rd : 1; 3641215976Sjmallett uint64_t reserved_34_63 : 30; 3642215976Sjmallett#endif 3643215976Sjmallett } cn31xx; 3644215976Sjmallett struct cvmx_pci_int_sum_s cn38xx; 3645215976Sjmallett struct cvmx_pci_int_sum_s cn38xxp2; 3646215976Sjmallett struct cvmx_pci_int_sum_cn31xx cn50xx; 3647215976Sjmallett struct cvmx_pci_int_sum_s cn58xx; 3648215976Sjmallett struct cvmx_pci_int_sum_s cn58xxp1; 3649215976Sjmallett}; 3650215976Sjmalletttypedef union cvmx_pci_int_sum cvmx_pci_int_sum_t; 3651215976Sjmallett 3652215976Sjmallett/** 3653215976Sjmallett * cvmx_pci_int_sum2 3654215976Sjmallett * 3655215976Sjmallett * PCI_INT_SUM2 = PCI Interrupt Summary2 Register 3656215976Sjmallett * 3657215976Sjmallett * The PCI Interrupt Summary2 Register copy used for RSL interrupts. 3658215976Sjmallett */ 3659232812Sjmallettunion cvmx_pci_int_sum2 { 3660215976Sjmallett uint64_t u64; 3661232812Sjmallett struct cvmx_pci_int_sum2_s { 3662232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3663215976Sjmallett uint64_t reserved_34_63 : 30; 3664215976Sjmallett uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3665215976Sjmallett when the mem area is disabled. */ 3666215976Sjmallett uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3667215976Sjmallett when the mem area is disabled. */ 3668215976Sjmallett uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3669215976Sjmallett Read-Address Register took place. */ 3670215976Sjmallett uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3671215976Sjmallett required to set the FORCE-INT bit for counter 1. */ 3672215976Sjmallett uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3673215976Sjmallett required to set the FORCE-INT bit for counter 0. */ 3674215976Sjmallett uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3675215976Sjmallett register is not 0 the DMA_CNT1 timer counts. 3676215976Sjmallett When the DMA1_CNT timer has a value greater 3677215976Sjmallett than the PCI_DMA_TIME1 register this 3678215976Sjmallett bit is set. The timer is reset when bit is 3679215976Sjmallett written with a one. */ 3680215976Sjmallett uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3681215976Sjmallett register is not 0 the DMA_CNT0 timer counts. 3682215976Sjmallett When the DMA0_CNT timer has a value greater 3683215976Sjmallett than the PCI_DMA_TIME0 register this 3684215976Sjmallett bit is set. The timer is reset when bit is 3685215976Sjmallett written with a one. */ 3686215976Sjmallett uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3687215976Sjmallett value is greater than the value 3688215976Sjmallett in the PCI_DMA_INT_LEV1 register. */ 3689215976Sjmallett uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3690215976Sjmallett value is greater than the value 3691215976Sjmallett in the PCI_DMA_INT_LEV0 register. */ 3692215976Sjmallett uint64_t ptime3 : 1; /**< When the value in the PCI_PKTS_SENT3 3693215976Sjmallett register is not 0 the Sent-3 timer counts. 3694215976Sjmallett When the Sent-3 timer has a value greater 3695215976Sjmallett than the PCI_PKTS_SENT_TIME3 register this 3696215976Sjmallett bit is set. The timer is reset when bit is 3697215976Sjmallett written with a one. */ 3698215976Sjmallett uint64_t ptime2 : 1; /**< When the value in the PCI_PKTS_SENT2 3699215976Sjmallett register is not 0 the Sent-2 timer counts. 3700215976Sjmallett When the Sent-2 timer has a value greater 3701215976Sjmallett than the PCI_PKTS_SENT_TIME2 register this 3702215976Sjmallett bit is set. The timer is reset when bit is 3703215976Sjmallett written with a one. */ 3704215976Sjmallett uint64_t ptime1 : 1; /**< When the value in the PCI_PKTS_SENT1 3705215976Sjmallett register is not 0 the Sent-1 timer counts. 3706215976Sjmallett When the Sent-1 timer has a value greater 3707215976Sjmallett than the PCI_PKTS_SENT_TIME1 register this 3708215976Sjmallett bit is set. The timer is reset when bit is 3709215976Sjmallett written with a one. */ 3710215976Sjmallett uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3711215976Sjmallett register is not 0 the Sent-0 timer counts. 3712215976Sjmallett When the Sent-0 timer has a value greater 3713215976Sjmallett than the PCI_PKTS_SENT_TIME0 register this 3714215976Sjmallett bit is set. The timer is reset when bit is 3715215976Sjmallett written with a one. */ 3716215976Sjmallett uint64_t pcnt3 : 1; /**< This bit indicates that PCI_PKTS_SENT3 3717215976Sjmallett value is greater than the value 3718215976Sjmallett in the PCI_PKTS_SENT_INT_LEV3 register. */ 3719215976Sjmallett uint64_t pcnt2 : 1; /**< This bit indicates that PCI_PKTS_SENT2 3720215976Sjmallett value is greater than the value 3721215976Sjmallett in the PCI_PKTS_SENT_INT_LEV2 register. */ 3722215976Sjmallett uint64_t pcnt1 : 1; /**< This bit indicates that PCI_PKTS_SENT1 3723215976Sjmallett value is greater than the value 3724215976Sjmallett in the PCI_PKTS_SENT_INT_LEV1 register. */ 3725215976Sjmallett uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3726215976Sjmallett value is greater than the value 3727215976Sjmallett in the PCI_PKTS_SENT_INT_LEV0 register. */ 3728215976Sjmallett uint64_t rsl_int : 1; /**< This bit is set when the RSL Chain has 3729215976Sjmallett generated an interrupt. */ 3730215976Sjmallett uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3731215976Sjmallett uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3732215976Sjmallett uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3733215976Sjmallett uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3734215976Sjmallett uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3735215976Sjmallett uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected */ 3736215976Sjmallett uint64_t msc_msg : 1; /**< Master Split Completion Message Detected */ 3737215976Sjmallett uint64_t msi_mabt : 1; /**< PCI MSI Master Abort. */ 3738215976Sjmallett uint64_t msi_tabt : 1; /**< PCI MSI Target Abort. */ 3739215976Sjmallett uint64_t msi_per : 1; /**< PCI MSI Parity Error. */ 3740215976Sjmallett uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Read. */ 3741215976Sjmallett uint64_t mr_abt : 1; /**< PCI Master Abort On Read. */ 3742215976Sjmallett uint64_t tr_abt : 1; /**< PCI Target Abort On Read. */ 3743215976Sjmallett uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on write. */ 3744215976Sjmallett uint64_t mr_wabt : 1; /**< PCI Master Abort detected on write. */ 3745215976Sjmallett uint64_t tr_wabt : 1; /**< PCI Target Abort detected on write. */ 3746215976Sjmallett#else 3747215976Sjmallett uint64_t tr_wabt : 1; 3748215976Sjmallett uint64_t mr_wabt : 1; 3749215976Sjmallett uint64_t mr_wtto : 1; 3750215976Sjmallett uint64_t tr_abt : 1; 3751215976Sjmallett uint64_t mr_abt : 1; 3752215976Sjmallett uint64_t mr_tto : 1; 3753215976Sjmallett uint64_t msi_per : 1; 3754215976Sjmallett uint64_t msi_tabt : 1; 3755215976Sjmallett uint64_t msi_mabt : 1; 3756215976Sjmallett uint64_t msc_msg : 1; 3757215976Sjmallett uint64_t tsr_abt : 1; 3758215976Sjmallett uint64_t serr : 1; 3759215976Sjmallett uint64_t aperr : 1; 3760215976Sjmallett uint64_t dperr : 1; 3761215976Sjmallett uint64_t ill_rwr : 1; 3762215976Sjmallett uint64_t ill_rrd : 1; 3763215976Sjmallett uint64_t rsl_int : 1; 3764215976Sjmallett uint64_t pcnt0 : 1; 3765215976Sjmallett uint64_t pcnt1 : 1; 3766215976Sjmallett uint64_t pcnt2 : 1; 3767215976Sjmallett uint64_t pcnt3 : 1; 3768215976Sjmallett uint64_t ptime0 : 1; 3769215976Sjmallett uint64_t ptime1 : 1; 3770215976Sjmallett uint64_t ptime2 : 1; 3771215976Sjmallett uint64_t ptime3 : 1; 3772215976Sjmallett uint64_t dcnt0 : 1; 3773215976Sjmallett uint64_t dcnt1 : 1; 3774215976Sjmallett uint64_t dtime0 : 1; 3775215976Sjmallett uint64_t dtime1 : 1; 3776215976Sjmallett uint64_t dma0_fi : 1; 3777215976Sjmallett uint64_t dma1_fi : 1; 3778215976Sjmallett uint64_t win_wr : 1; 3779215976Sjmallett uint64_t ill_wr : 1; 3780215976Sjmallett uint64_t ill_rd : 1; 3781215976Sjmallett uint64_t reserved_34_63 : 30; 3782215976Sjmallett#endif 3783215976Sjmallett } s; 3784232812Sjmallett struct cvmx_pci_int_sum2_cn30xx { 3785232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3786215976Sjmallett uint64_t reserved_34_63 : 30; 3787215976Sjmallett uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3788215976Sjmallett when the mem area is disabled. */ 3789215976Sjmallett uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3790215976Sjmallett when the mem area is disabled. */ 3791215976Sjmallett uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3792215976Sjmallett Read-Address Register took place. */ 3793215976Sjmallett uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3794215976Sjmallett required to set the FORCE-INT bit for counter 1. */ 3795215976Sjmallett uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3796215976Sjmallett required to set the FORCE-INT bit for counter 0. */ 3797215976Sjmallett uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3798215976Sjmallett register is not 0 the DMA_CNT1 timer counts. 3799215976Sjmallett When the DMA1_CNT timer has a value greater 3800215976Sjmallett than the PCI_DMA_TIME1 register this 3801215976Sjmallett bit is set. The timer is reset when bit is 3802215976Sjmallett written with a one. */ 3803215976Sjmallett uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3804215976Sjmallett register is not 0 the DMA_CNT0 timer counts. 3805215976Sjmallett When the DMA0_CNT timer has a value greater 3806215976Sjmallett than the PCI_DMA_TIME0 register this 3807215976Sjmallett bit is set. The timer is reset when bit is 3808215976Sjmallett written with a one. */ 3809215976Sjmallett uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3810215976Sjmallett value is greater than the value 3811215976Sjmallett in the PCI_DMA_INT_LEV1 register. */ 3812215976Sjmallett uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3813215976Sjmallett value is greater than the value 3814215976Sjmallett in the PCI_DMA_INT_LEV0 register. */ 3815215976Sjmallett uint64_t reserved_22_24 : 3; 3816215976Sjmallett uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3817215976Sjmallett register is not 0 the Sent-0 timer counts. 3818215976Sjmallett When the Sent-0 timer has a value greater 3819215976Sjmallett than the PCI_PKTS_SENT_TIME0 register this 3820215976Sjmallett bit is set. The timer is reset when bit is 3821215976Sjmallett written with a one. */ 3822215976Sjmallett uint64_t reserved_18_20 : 3; 3823215976Sjmallett uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3824215976Sjmallett value is greater than the value 3825215976Sjmallett in the PCI_PKTS_SENT_INT_LEV0 register. */ 3826215976Sjmallett uint64_t rsl_int : 1; /**< This bit is set when the RSL Chain has 3827215976Sjmallett generated an interrupt. */ 3828215976Sjmallett uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3829215976Sjmallett uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3830215976Sjmallett uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3831215976Sjmallett uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3832215976Sjmallett uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3833215976Sjmallett uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected */ 3834215976Sjmallett uint64_t msc_msg : 1; /**< Master Split Completion Message Detected */ 3835215976Sjmallett uint64_t msi_mabt : 1; /**< PCI MSI Master Abort. */ 3836215976Sjmallett uint64_t msi_tabt : 1; /**< PCI MSI Target Abort. */ 3837215976Sjmallett uint64_t msi_per : 1; /**< PCI MSI Parity Error. */ 3838215976Sjmallett uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Read. */ 3839215976Sjmallett uint64_t mr_abt : 1; /**< PCI Master Abort On Read. */ 3840215976Sjmallett uint64_t tr_abt : 1; /**< PCI Target Abort On Read. */ 3841215976Sjmallett uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on write. */ 3842215976Sjmallett uint64_t mr_wabt : 1; /**< PCI Master Abort detected on write. */ 3843215976Sjmallett uint64_t tr_wabt : 1; /**< PCI Target Abort detected on write. */ 3844215976Sjmallett#else 3845215976Sjmallett uint64_t tr_wabt : 1; 3846215976Sjmallett uint64_t mr_wabt : 1; 3847215976Sjmallett uint64_t mr_wtto : 1; 3848215976Sjmallett uint64_t tr_abt : 1; 3849215976Sjmallett uint64_t mr_abt : 1; 3850215976Sjmallett uint64_t mr_tto : 1; 3851215976Sjmallett uint64_t msi_per : 1; 3852215976Sjmallett uint64_t msi_tabt : 1; 3853215976Sjmallett uint64_t msi_mabt : 1; 3854215976Sjmallett uint64_t msc_msg : 1; 3855215976Sjmallett uint64_t tsr_abt : 1; 3856215976Sjmallett uint64_t serr : 1; 3857215976Sjmallett uint64_t aperr : 1; 3858215976Sjmallett uint64_t dperr : 1; 3859215976Sjmallett uint64_t ill_rwr : 1; 3860215976Sjmallett uint64_t ill_rrd : 1; 3861215976Sjmallett uint64_t rsl_int : 1; 3862215976Sjmallett uint64_t pcnt0 : 1; 3863215976Sjmallett uint64_t reserved_18_20 : 3; 3864215976Sjmallett uint64_t ptime0 : 1; 3865215976Sjmallett uint64_t reserved_22_24 : 3; 3866215976Sjmallett uint64_t dcnt0 : 1; 3867215976Sjmallett uint64_t dcnt1 : 1; 3868215976Sjmallett uint64_t dtime0 : 1; 3869215976Sjmallett uint64_t dtime1 : 1; 3870215976Sjmallett uint64_t dma0_fi : 1; 3871215976Sjmallett uint64_t dma1_fi : 1; 3872215976Sjmallett uint64_t win_wr : 1; 3873215976Sjmallett uint64_t ill_wr : 1; 3874215976Sjmallett uint64_t ill_rd : 1; 3875215976Sjmallett uint64_t reserved_34_63 : 30; 3876215976Sjmallett#endif 3877215976Sjmallett } cn30xx; 3878232812Sjmallett struct cvmx_pci_int_sum2_cn31xx { 3879232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3880215976Sjmallett uint64_t reserved_34_63 : 30; 3881215976Sjmallett uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3882215976Sjmallett when the mem area is disabled. */ 3883215976Sjmallett uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3884215976Sjmallett when the mem area is disabled. */ 3885215976Sjmallett uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3886215976Sjmallett Read-Address Register took place. */ 3887215976Sjmallett uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3888215976Sjmallett required to set the FORCE-INT bit for counter 1. */ 3889215976Sjmallett uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3890215976Sjmallett required to set the FORCE-INT bit for counter 0. */ 3891215976Sjmallett uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3892215976Sjmallett register is not 0 the DMA_CNT1 timer counts. 3893215976Sjmallett When the DMA1_CNT timer has a value greater 3894215976Sjmallett than the PCI_DMA_TIME1 register this 3895215976Sjmallett bit is set. The timer is reset when bit is 3896215976Sjmallett written with a one. */ 3897215976Sjmallett uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3898215976Sjmallett register is not 0 the DMA_CNT0 timer counts. 3899215976Sjmallett When the DMA0_CNT timer has a value greater 3900215976Sjmallett than the PCI_DMA_TIME0 register this 3901215976Sjmallett bit is set. The timer is reset when bit is 3902215976Sjmallett written with a one. */ 3903215976Sjmallett uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3904215976Sjmallett value is greater than the value 3905215976Sjmallett in the PCI_DMA_INT_LEV1 register. */ 3906215976Sjmallett uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3907215976Sjmallett value is greater than the value 3908215976Sjmallett in the PCI_DMA_INT_LEV0 register. */ 3909215976Sjmallett uint64_t reserved_23_24 : 2; 3910215976Sjmallett uint64_t ptime1 : 1; /**< When the value in the PCI_PKTS_SENT1 3911215976Sjmallett register is not 0 the Sent-1 timer counts. 3912215976Sjmallett When the Sent-1 timer has a value greater 3913215976Sjmallett than the PCI_PKTS_SENT_TIME1 register this 3914215976Sjmallett bit is set. The timer is reset when bit is 3915215976Sjmallett written with a one. */ 3916215976Sjmallett uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3917215976Sjmallett register is not 0 the Sent-0 timer counts. 3918215976Sjmallett When the Sent-0 timer has a value greater 3919215976Sjmallett than the PCI_PKTS_SENT_TIME0 register this 3920215976Sjmallett bit is set. The timer is reset when bit is 3921215976Sjmallett written with a one. */ 3922215976Sjmallett uint64_t reserved_19_20 : 2; 3923215976Sjmallett uint64_t pcnt1 : 1; /**< This bit indicates that PCI_PKTS_SENT1 3924215976Sjmallett value is greater than the value 3925215976Sjmallett in the PCI_PKTS_SENT_INT_LEV1 register. */ 3926215976Sjmallett uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3927215976Sjmallett value is greater than the value 3928215976Sjmallett in the PCI_PKTS_SENT_INT_LEV0 register. */ 3929215976Sjmallett uint64_t rsl_int : 1; /**< This bit is set when the RSL Chain has 3930215976Sjmallett generated an interrupt. */ 3931215976Sjmallett uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3932215976Sjmallett uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3933215976Sjmallett uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3934215976Sjmallett uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3935215976Sjmallett uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3936215976Sjmallett uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected */ 3937215976Sjmallett uint64_t msc_msg : 1; /**< Master Split Completion Message Detected */ 3938215976Sjmallett uint64_t msi_mabt : 1; /**< PCI MSI Master Abort. */ 3939215976Sjmallett uint64_t msi_tabt : 1; /**< PCI MSI Target Abort. */ 3940215976Sjmallett uint64_t msi_per : 1; /**< PCI MSI Parity Error. */ 3941215976Sjmallett uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Read. */ 3942215976Sjmallett uint64_t mr_abt : 1; /**< PCI Master Abort On Read. */ 3943215976Sjmallett uint64_t tr_abt : 1; /**< PCI Target Abort On Read. */ 3944215976Sjmallett uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on write. */ 3945215976Sjmallett uint64_t mr_wabt : 1; /**< PCI Master Abort detected on write. */ 3946215976Sjmallett uint64_t tr_wabt : 1; /**< PCI Target Abort detected on write. */ 3947215976Sjmallett#else 3948215976Sjmallett uint64_t tr_wabt : 1; 3949215976Sjmallett uint64_t mr_wabt : 1; 3950215976Sjmallett uint64_t mr_wtto : 1; 3951215976Sjmallett uint64_t tr_abt : 1; 3952215976Sjmallett uint64_t mr_abt : 1; 3953215976Sjmallett uint64_t mr_tto : 1; 3954215976Sjmallett uint64_t msi_per : 1; 3955215976Sjmallett uint64_t msi_tabt : 1; 3956215976Sjmallett uint64_t msi_mabt : 1; 3957215976Sjmallett uint64_t msc_msg : 1; 3958215976Sjmallett uint64_t tsr_abt : 1; 3959215976Sjmallett uint64_t serr : 1; 3960215976Sjmallett uint64_t aperr : 1; 3961215976Sjmallett uint64_t dperr : 1; 3962215976Sjmallett uint64_t ill_rwr : 1; 3963215976Sjmallett uint64_t ill_rrd : 1; 3964215976Sjmallett uint64_t rsl_int : 1; 3965215976Sjmallett uint64_t pcnt0 : 1; 3966215976Sjmallett uint64_t pcnt1 : 1; 3967215976Sjmallett uint64_t reserved_19_20 : 2; 3968215976Sjmallett uint64_t ptime0 : 1; 3969215976Sjmallett uint64_t ptime1 : 1; 3970215976Sjmallett uint64_t reserved_23_24 : 2; 3971215976Sjmallett uint64_t dcnt0 : 1; 3972215976Sjmallett uint64_t dcnt1 : 1; 3973215976Sjmallett uint64_t dtime0 : 1; 3974215976Sjmallett uint64_t dtime1 : 1; 3975215976Sjmallett uint64_t dma0_fi : 1; 3976215976Sjmallett uint64_t dma1_fi : 1; 3977215976Sjmallett uint64_t win_wr : 1; 3978215976Sjmallett uint64_t ill_wr : 1; 3979215976Sjmallett uint64_t ill_rd : 1; 3980215976Sjmallett uint64_t reserved_34_63 : 30; 3981215976Sjmallett#endif 3982215976Sjmallett } cn31xx; 3983215976Sjmallett struct cvmx_pci_int_sum2_s cn38xx; 3984215976Sjmallett struct cvmx_pci_int_sum2_s cn38xxp2; 3985215976Sjmallett struct cvmx_pci_int_sum2_cn31xx cn50xx; 3986215976Sjmallett struct cvmx_pci_int_sum2_s cn58xx; 3987215976Sjmallett struct cvmx_pci_int_sum2_s cn58xxp1; 3988215976Sjmallett}; 3989215976Sjmalletttypedef union cvmx_pci_int_sum2 cvmx_pci_int_sum2_t; 3990215976Sjmallett 3991215976Sjmallett/** 3992215976Sjmallett * cvmx_pci_msi_rcv 3993215976Sjmallett * 3994215976Sjmallett * PCI_MSI_RCV = PCI's MSI Received Vector Register 3995215976Sjmallett * 3996215976Sjmallett * A bit is set in this register relative to the vector received during a MSI. The value in this 3997215976Sjmallett * register is acted upon when the least-significant-byte of this register is written. 3998215976Sjmallett */ 3999232812Sjmallettunion cvmx_pci_msi_rcv { 4000215976Sjmallett uint32_t u32; 4001232812Sjmallett struct cvmx_pci_msi_rcv_s { 4002232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4003215976Sjmallett uint32_t reserved_6_31 : 26; 4004215976Sjmallett uint32_t intr : 6; /**< When an MSI is received on the PCI the bit selected 4005215976Sjmallett by data [5:0] will be set in this register. To 4006215976Sjmallett clear this bit a write must take place to the 4007215976Sjmallett NPI_MSI_RCV register where any bit set to 1 is 4008215976Sjmallett cleared. Reading this address will return an 4009215976Sjmallett unpredicatable value. */ 4010215976Sjmallett#else 4011215976Sjmallett uint32_t intr : 6; 4012215976Sjmallett uint32_t reserved_6_31 : 26; 4013215976Sjmallett#endif 4014215976Sjmallett } s; 4015215976Sjmallett struct cvmx_pci_msi_rcv_s cn30xx; 4016215976Sjmallett struct cvmx_pci_msi_rcv_s cn31xx; 4017215976Sjmallett struct cvmx_pci_msi_rcv_s cn38xx; 4018215976Sjmallett struct cvmx_pci_msi_rcv_s cn38xxp2; 4019215976Sjmallett struct cvmx_pci_msi_rcv_s cn50xx; 4020215976Sjmallett struct cvmx_pci_msi_rcv_s cn58xx; 4021215976Sjmallett struct cvmx_pci_msi_rcv_s cn58xxp1; 4022215976Sjmallett}; 4023215976Sjmalletttypedef union cvmx_pci_msi_rcv cvmx_pci_msi_rcv_t; 4024215976Sjmallett 4025215976Sjmallett/** 4026215976Sjmallett * cvmx_pci_pkt_credits# 4027215976Sjmallett * 4028215976Sjmallett * PCI_PKT_CREDITS0 = PCI Packet Credits For Output 0 4029215976Sjmallett * 4030215976Sjmallett * Used to decrease the number of packets to be processed by the host from Output-0 and return 4031215976Sjmallett * buffer/info pointer pairs to OCTEON Output-0. The value in this register is acted upon when the 4032215976Sjmallett * least-significant-byte of this register is written. 4033215976Sjmallett */ 4034232812Sjmallettunion cvmx_pci_pkt_creditsx { 4035215976Sjmallett uint32_t u32; 4036232812Sjmallett struct cvmx_pci_pkt_creditsx_s { 4037232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4038215976Sjmallett uint32_t pkt_cnt : 16; /**< The value written to this field will be 4039215976Sjmallett subtracted from PCI_PKTS_SENT0[PKT_CNT]. */ 4040215976Sjmallett uint32_t ptr_cnt : 16; /**< This field value is added to the 4041215976Sjmallett NPI's internal Buffer/Info Pointer Pair count. */ 4042215976Sjmallett#else 4043215976Sjmallett uint32_t ptr_cnt : 16; 4044215976Sjmallett uint32_t pkt_cnt : 16; 4045215976Sjmallett#endif 4046215976Sjmallett } s; 4047215976Sjmallett struct cvmx_pci_pkt_creditsx_s cn30xx; 4048215976Sjmallett struct cvmx_pci_pkt_creditsx_s cn31xx; 4049215976Sjmallett struct cvmx_pci_pkt_creditsx_s cn38xx; 4050215976Sjmallett struct cvmx_pci_pkt_creditsx_s cn38xxp2; 4051215976Sjmallett struct cvmx_pci_pkt_creditsx_s cn50xx; 4052215976Sjmallett struct cvmx_pci_pkt_creditsx_s cn58xx; 4053215976Sjmallett struct cvmx_pci_pkt_creditsx_s cn58xxp1; 4054215976Sjmallett}; 4055215976Sjmalletttypedef union cvmx_pci_pkt_creditsx cvmx_pci_pkt_creditsx_t; 4056215976Sjmallett 4057215976Sjmallett/** 4058215976Sjmallett * cvmx_pci_pkts_sent# 4059215976Sjmallett * 4060215976Sjmallett * PCI_PKTS_SENT0 = PCI Packets Sent 0 4061215976Sjmallett * 4062215976Sjmallett * Number of packets sent to the host memory from PCI Output 0 4063215976Sjmallett */ 4064232812Sjmallettunion cvmx_pci_pkts_sentx { 4065215976Sjmallett uint32_t u32; 4066232812Sjmallett struct cvmx_pci_pkts_sentx_s { 4067232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4068215976Sjmallett uint32_t pkt_cnt : 32; /**< Each time a packet is written to the memory via 4069215976Sjmallett PCI from PCI Output 0, this counter is 4070215976Sjmallett incremented by 1 or the byte count of the packet 4071215976Sjmallett as set in NPI_OUTPUT_CONTROL[P0_BMODE]. */ 4072215976Sjmallett#else 4073215976Sjmallett uint32_t pkt_cnt : 32; 4074215976Sjmallett#endif 4075215976Sjmallett } s; 4076215976Sjmallett struct cvmx_pci_pkts_sentx_s cn30xx; 4077215976Sjmallett struct cvmx_pci_pkts_sentx_s cn31xx; 4078215976Sjmallett struct cvmx_pci_pkts_sentx_s cn38xx; 4079215976Sjmallett struct cvmx_pci_pkts_sentx_s cn38xxp2; 4080215976Sjmallett struct cvmx_pci_pkts_sentx_s cn50xx; 4081215976Sjmallett struct cvmx_pci_pkts_sentx_s cn58xx; 4082215976Sjmallett struct cvmx_pci_pkts_sentx_s cn58xxp1; 4083215976Sjmallett}; 4084215976Sjmalletttypedef union cvmx_pci_pkts_sentx cvmx_pci_pkts_sentx_t; 4085215976Sjmallett 4086215976Sjmallett/** 4087215976Sjmallett * cvmx_pci_pkts_sent_int_lev# 4088215976Sjmallett * 4089215976Sjmallett * PCI_PKTS_SENT_INT_LEV0 = PCI Packets Sent Interrupt Level For Output 0 4090215976Sjmallett * 4091215976Sjmallett * Interrupt when number of packets sent is equal to or greater than the register value. 4092215976Sjmallett */ 4093232812Sjmallettunion cvmx_pci_pkts_sent_int_levx { 4094215976Sjmallett uint32_t u32; 4095232812Sjmallett struct cvmx_pci_pkts_sent_int_levx_s { 4096232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4097215976Sjmallett uint32_t pkt_cnt : 32; /**< When corresponding port's PCI_PKTS_SENT0 value 4098215976Sjmallett exceeds the value in this register, PCNT0 of the 4099215976Sjmallett PCI_INT_SUM and PCI_INT_SUM2 will be set. */ 4100215976Sjmallett#else 4101215976Sjmallett uint32_t pkt_cnt : 32; 4102215976Sjmallett#endif 4103215976Sjmallett } s; 4104215976Sjmallett struct cvmx_pci_pkts_sent_int_levx_s cn30xx; 4105215976Sjmallett struct cvmx_pci_pkts_sent_int_levx_s cn31xx; 4106215976Sjmallett struct cvmx_pci_pkts_sent_int_levx_s cn38xx; 4107215976Sjmallett struct cvmx_pci_pkts_sent_int_levx_s cn38xxp2; 4108215976Sjmallett struct cvmx_pci_pkts_sent_int_levx_s cn50xx; 4109215976Sjmallett struct cvmx_pci_pkts_sent_int_levx_s cn58xx; 4110215976Sjmallett struct cvmx_pci_pkts_sent_int_levx_s cn58xxp1; 4111215976Sjmallett}; 4112215976Sjmalletttypedef union cvmx_pci_pkts_sent_int_levx cvmx_pci_pkts_sent_int_levx_t; 4113215976Sjmallett 4114215976Sjmallett/** 4115215976Sjmallett * cvmx_pci_pkts_sent_time# 4116215976Sjmallett * 4117215976Sjmallett * PCI_PKTS_SENT_TIME0 = PCI Packets Sent Timer For Output-0 4118215976Sjmallett * 4119215976Sjmallett * Time to wait from packet being sent to host from Output-0 before issuing an interrupt. 4120215976Sjmallett */ 4121232812Sjmallettunion cvmx_pci_pkts_sent_timex { 4122215976Sjmallett uint32_t u32; 4123232812Sjmallett struct cvmx_pci_pkts_sent_timex_s { 4124232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4125215976Sjmallett uint32_t pkt_time : 32; /**< Number of PCI clock cycle to wait before 4126215976Sjmallett issuing an interrupt to the host when a 4127215976Sjmallett packet from this port has been sent to the 4128215976Sjmallett host. The timer is reset when the 4129215976Sjmallett PCI_INT_SUM[21] register is cleared. */ 4130215976Sjmallett#else 4131215976Sjmallett uint32_t pkt_time : 32; 4132215976Sjmallett#endif 4133215976Sjmallett } s; 4134215976Sjmallett struct cvmx_pci_pkts_sent_timex_s cn30xx; 4135215976Sjmallett struct cvmx_pci_pkts_sent_timex_s cn31xx; 4136215976Sjmallett struct cvmx_pci_pkts_sent_timex_s cn38xx; 4137215976Sjmallett struct cvmx_pci_pkts_sent_timex_s cn38xxp2; 4138215976Sjmallett struct cvmx_pci_pkts_sent_timex_s cn50xx; 4139215976Sjmallett struct cvmx_pci_pkts_sent_timex_s cn58xx; 4140215976Sjmallett struct cvmx_pci_pkts_sent_timex_s cn58xxp1; 4141215976Sjmallett}; 4142215976Sjmalletttypedef union cvmx_pci_pkts_sent_timex cvmx_pci_pkts_sent_timex_t; 4143215976Sjmallett 4144215976Sjmallett/** 4145215976Sjmallett * cvmx_pci_read_cmd_6 4146215976Sjmallett * 4147215976Sjmallett * PCI_READ_CMD_6 = PCI Read Command 6 Register 4148215976Sjmallett * 4149215976Sjmallett * Contains control inforamtion related to a received PCI Command 6. 4150215976Sjmallett */ 4151232812Sjmallettunion cvmx_pci_read_cmd_6 { 4152215976Sjmallett uint32_t u32; 4153232812Sjmallett struct cvmx_pci_read_cmd_6_s { 4154232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4155215976Sjmallett uint32_t reserved_9_31 : 23; 4156215976Sjmallett uint32_t min_data : 6; /**< The number of words to have buffered in the PNI 4157215976Sjmallett before informing the PCIX-Core that we have 4158215976Sjmallett read data available for the outstanding Delayed 4159215976Sjmallett read. 0 is treated as a 64. 4160215976Sjmallett For reads to the expansion this value is not used. */ 4161215976Sjmallett uint32_t prefetch : 3; /**< Control the amount of data to be preteched when 4162215976Sjmallett this type of bhmstREAD command is received. 4163215976Sjmallett 0 = 1 32/64 bit word. 4164215976Sjmallett 1 = From address to end of 128B block. 4165215976Sjmallett 2 = From address to end of 128B block plus 128B. 4166215976Sjmallett 3 = From address to end of 128B block plus 256B. 4167215976Sjmallett 4 = From address to end of 128B block plus 384B. 4168215976Sjmallett For reads to the expansion this value is not used. */ 4169215976Sjmallett#else 4170215976Sjmallett uint32_t prefetch : 3; 4171215976Sjmallett uint32_t min_data : 6; 4172215976Sjmallett uint32_t reserved_9_31 : 23; 4173215976Sjmallett#endif 4174215976Sjmallett } s; 4175215976Sjmallett struct cvmx_pci_read_cmd_6_s cn30xx; 4176215976Sjmallett struct cvmx_pci_read_cmd_6_s cn31xx; 4177215976Sjmallett struct cvmx_pci_read_cmd_6_s cn38xx; 4178215976Sjmallett struct cvmx_pci_read_cmd_6_s cn38xxp2; 4179215976Sjmallett struct cvmx_pci_read_cmd_6_s cn50xx; 4180215976Sjmallett struct cvmx_pci_read_cmd_6_s cn58xx; 4181215976Sjmallett struct cvmx_pci_read_cmd_6_s cn58xxp1; 4182215976Sjmallett}; 4183215976Sjmalletttypedef union cvmx_pci_read_cmd_6 cvmx_pci_read_cmd_6_t; 4184215976Sjmallett 4185215976Sjmallett/** 4186215976Sjmallett * cvmx_pci_read_cmd_c 4187215976Sjmallett * 4188215976Sjmallett * PCI_READ_CMD_C = PCI Read Command C Register 4189215976Sjmallett * 4190215976Sjmallett * Contains control inforamtion related to a received PCI Command C. 4191215976Sjmallett */ 4192232812Sjmallettunion cvmx_pci_read_cmd_c { 4193215976Sjmallett uint32_t u32; 4194232812Sjmallett struct cvmx_pci_read_cmd_c_s { 4195232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4196215976Sjmallett uint32_t reserved_9_31 : 23; 4197215976Sjmallett uint32_t min_data : 6; /**< The number of words to have buffered in the PNI 4198215976Sjmallett before informing the PCIX-Core that we have 4199215976Sjmallett read data available for the outstanding Delayed 4200215976Sjmallett read. 0 is treated as a 64. 4201215976Sjmallett For reads to the expansion this value is not used. */ 4202215976Sjmallett uint32_t prefetch : 3; /**< Control the amount of data to be preteched when 4203215976Sjmallett this type of READ command is received. 4204215976Sjmallett 0 = 1 32/64 bit word. 4205215976Sjmallett 1 = From address to end of 128B block. 4206215976Sjmallett 2 = From address to end of 128B block plus 128B. 4207215976Sjmallett 3 = From address to end of 128B block plus 256B. 4208215976Sjmallett 4 = From address to end of 128B block plus 384B. 4209215976Sjmallett For reads to the expansion this value is not used. */ 4210215976Sjmallett#else 4211215976Sjmallett uint32_t prefetch : 3; 4212215976Sjmallett uint32_t min_data : 6; 4213215976Sjmallett uint32_t reserved_9_31 : 23; 4214215976Sjmallett#endif 4215215976Sjmallett } s; 4216215976Sjmallett struct cvmx_pci_read_cmd_c_s cn30xx; 4217215976Sjmallett struct cvmx_pci_read_cmd_c_s cn31xx; 4218215976Sjmallett struct cvmx_pci_read_cmd_c_s cn38xx; 4219215976Sjmallett struct cvmx_pci_read_cmd_c_s cn38xxp2; 4220215976Sjmallett struct cvmx_pci_read_cmd_c_s cn50xx; 4221215976Sjmallett struct cvmx_pci_read_cmd_c_s cn58xx; 4222215976Sjmallett struct cvmx_pci_read_cmd_c_s cn58xxp1; 4223215976Sjmallett}; 4224215976Sjmalletttypedef union cvmx_pci_read_cmd_c cvmx_pci_read_cmd_c_t; 4225215976Sjmallett 4226215976Sjmallett/** 4227215976Sjmallett * cvmx_pci_read_cmd_e 4228215976Sjmallett * 4229215976Sjmallett * PCI_READ_CMD_E = PCI Read Command E Register 4230215976Sjmallett * 4231215976Sjmallett * Contains control inforamtion related to a received PCI Command 6. 4232215976Sjmallett */ 4233232812Sjmallettunion cvmx_pci_read_cmd_e { 4234215976Sjmallett uint32_t u32; 4235232812Sjmallett struct cvmx_pci_read_cmd_e_s { 4236232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4237215976Sjmallett uint32_t reserved_9_31 : 23; 4238215976Sjmallett uint32_t min_data : 6; /**< The number of words to have buffered in the PNI 4239215976Sjmallett before informaing the PCIX-Core that we have 4240215976Sjmallett read data available for the outstanding Delayed 4241215976Sjmallett read. 0 is treated as a 64. 4242215976Sjmallett For reads to the expansion this value is not used. */ 4243215976Sjmallett uint32_t prefetch : 3; /**< Control the amount of data to be preteched when 4244215976Sjmallett this type of READ command is received. 4245215976Sjmallett 0 = 1 32/64 bit word. 4246215976Sjmallett 1 = From address to end of 128B block. 4247215976Sjmallett 2 = From address to end of 128B block plus 128B. 4248215976Sjmallett 3 = From address to end of 128B block plus 256B. 4249215976Sjmallett 4 = From address to end of 128B block plus 384B. 4250215976Sjmallett For reads to the expansion this value is not used. */ 4251215976Sjmallett#else 4252215976Sjmallett uint32_t prefetch : 3; 4253215976Sjmallett uint32_t min_data : 6; 4254215976Sjmallett uint32_t reserved_9_31 : 23; 4255215976Sjmallett#endif 4256215976Sjmallett } s; 4257215976Sjmallett struct cvmx_pci_read_cmd_e_s cn30xx; 4258215976Sjmallett struct cvmx_pci_read_cmd_e_s cn31xx; 4259215976Sjmallett struct cvmx_pci_read_cmd_e_s cn38xx; 4260215976Sjmallett struct cvmx_pci_read_cmd_e_s cn38xxp2; 4261215976Sjmallett struct cvmx_pci_read_cmd_e_s cn50xx; 4262215976Sjmallett struct cvmx_pci_read_cmd_e_s cn58xx; 4263215976Sjmallett struct cvmx_pci_read_cmd_e_s cn58xxp1; 4264215976Sjmallett}; 4265215976Sjmalletttypedef union cvmx_pci_read_cmd_e cvmx_pci_read_cmd_e_t; 4266215976Sjmallett 4267215976Sjmallett/** 4268215976Sjmallett * cvmx_pci_read_timeout 4269215976Sjmallett * 4270215976Sjmallett * PCI_READ_TIMEOUT = PCI Read Timeour Register 4271215976Sjmallett * 4272215976Sjmallett * The address to start reading Instructions from for Input-3. 4273215976Sjmallett */ 4274232812Sjmallettunion cvmx_pci_read_timeout { 4275215976Sjmallett uint64_t u64; 4276232812Sjmallett struct cvmx_pci_read_timeout_s { 4277232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4278215976Sjmallett uint64_t reserved_32_63 : 32; 4279215976Sjmallett uint64_t enb : 1; /**< Enable the use of the Timeout function. */ 4280215976Sjmallett uint64_t cnt : 31; /**< The number of eclk cycles to wait after issuing 4281215976Sjmallett a read request to the PNI before setting a 4282215976Sjmallett timeout and not expecting the data to return. 4283215976Sjmallett This is considered a fatal condition by the NPI. */ 4284215976Sjmallett#else 4285215976Sjmallett uint64_t cnt : 31; 4286215976Sjmallett uint64_t enb : 1; 4287215976Sjmallett uint64_t reserved_32_63 : 32; 4288215976Sjmallett#endif 4289215976Sjmallett } s; 4290215976Sjmallett struct cvmx_pci_read_timeout_s cn30xx; 4291215976Sjmallett struct cvmx_pci_read_timeout_s cn31xx; 4292215976Sjmallett struct cvmx_pci_read_timeout_s cn38xx; 4293215976Sjmallett struct cvmx_pci_read_timeout_s cn38xxp2; 4294215976Sjmallett struct cvmx_pci_read_timeout_s cn50xx; 4295215976Sjmallett struct cvmx_pci_read_timeout_s cn58xx; 4296215976Sjmallett struct cvmx_pci_read_timeout_s cn58xxp1; 4297215976Sjmallett}; 4298215976Sjmalletttypedef union cvmx_pci_read_timeout cvmx_pci_read_timeout_t; 4299215976Sjmallett 4300215976Sjmallett/** 4301215976Sjmallett * cvmx_pci_scm_reg 4302215976Sjmallett * 4303215976Sjmallett * PCI_SCM_REG = PCI Master Split Completion Message Register 4304215976Sjmallett * 4305215976Sjmallett * This register contains the Master Split Completion Message(SCM) generated when a master split 4306215976Sjmallett * transaction is aborted. 4307215976Sjmallett */ 4308232812Sjmallettunion cvmx_pci_scm_reg { 4309215976Sjmallett uint64_t u64; 4310232812Sjmallett struct cvmx_pci_scm_reg_s { 4311232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4312215976Sjmallett uint64_t reserved_32_63 : 32; 4313215976Sjmallett uint64_t scm : 32; /**< Contains the Split Completion Message (SCM) 4314215976Sjmallett driven when a master-split transaction is aborted. 4315215976Sjmallett [31:28]: Message Class 4316215976Sjmallett [27:20]: Message Index 4317215976Sjmallett [19]: Reserved 4318215976Sjmallett [18:12]: Remaining Lower Address 4319215976Sjmallett [11:8]: Upper Remaining Byte Count 4320215976Sjmallett [7:0]: Lower Remaining Byte Count 4321215976Sjmallett Refer to the PCIX1.0a specification, Fig 2-40 4322215976Sjmallett for additional details for the split completion 4323215976Sjmallett message format. */ 4324215976Sjmallett#else 4325215976Sjmallett uint64_t scm : 32; 4326215976Sjmallett uint64_t reserved_32_63 : 32; 4327215976Sjmallett#endif 4328215976Sjmallett } s; 4329215976Sjmallett struct cvmx_pci_scm_reg_s cn30xx; 4330215976Sjmallett struct cvmx_pci_scm_reg_s cn31xx; 4331215976Sjmallett struct cvmx_pci_scm_reg_s cn38xx; 4332215976Sjmallett struct cvmx_pci_scm_reg_s cn38xxp2; 4333215976Sjmallett struct cvmx_pci_scm_reg_s cn50xx; 4334215976Sjmallett struct cvmx_pci_scm_reg_s cn58xx; 4335215976Sjmallett struct cvmx_pci_scm_reg_s cn58xxp1; 4336215976Sjmallett}; 4337215976Sjmalletttypedef union cvmx_pci_scm_reg cvmx_pci_scm_reg_t; 4338215976Sjmallett 4339215976Sjmallett/** 4340215976Sjmallett * cvmx_pci_tsr_reg 4341215976Sjmallett * 4342215976Sjmallett * PCI_TSR_REG = PCI Target Split Attribute Register 4343215976Sjmallett * 4344215976Sjmallett * This register contains the Attribute field Master Split Completion Message(SCM) generated when a master split 4345215976Sjmallett * transaction is aborted. 4346215976Sjmallett */ 4347232812Sjmallettunion cvmx_pci_tsr_reg { 4348215976Sjmallett uint64_t u64; 4349232812Sjmallett struct cvmx_pci_tsr_reg_s { 4350232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4351215976Sjmallett uint64_t reserved_36_63 : 28; 4352215976Sjmallett uint64_t tsr : 36; /**< Contains the Target Split Attribute field when a 4353215976Sjmallett target-split transaction is aborted. 4354215976Sjmallett [35:32]: Upper Byte Count 4355215976Sjmallett [31]: BCM=Byte Count Modified 4356215976Sjmallett [30]: SCE=Split Completion Error 4357215976Sjmallett [29]: SCM=Split Completion Message 4358215976Sjmallett [28:24]: RESERVED 4359215976Sjmallett [23:16]: Completer Bus Number 4360215976Sjmallett [15:11]: Completer Device Number 4361215976Sjmallett [10:8]: Completer Function Number 4362215976Sjmallett [7:0]: Lower Byte Count 4363215976Sjmallett Refer to the PCIX1.0a specification, Fig 2-39 4364215976Sjmallett for additional details on the completer attribute 4365215976Sjmallett bit assignments. */ 4366215976Sjmallett#else 4367215976Sjmallett uint64_t tsr : 36; 4368215976Sjmallett uint64_t reserved_36_63 : 28; 4369215976Sjmallett#endif 4370215976Sjmallett } s; 4371215976Sjmallett struct cvmx_pci_tsr_reg_s cn30xx; 4372215976Sjmallett struct cvmx_pci_tsr_reg_s cn31xx; 4373215976Sjmallett struct cvmx_pci_tsr_reg_s cn38xx; 4374215976Sjmallett struct cvmx_pci_tsr_reg_s cn38xxp2; 4375215976Sjmallett struct cvmx_pci_tsr_reg_s cn50xx; 4376215976Sjmallett struct cvmx_pci_tsr_reg_s cn58xx; 4377215976Sjmallett struct cvmx_pci_tsr_reg_s cn58xxp1; 4378215976Sjmallett}; 4379215976Sjmalletttypedef union cvmx_pci_tsr_reg cvmx_pci_tsr_reg_t; 4380215976Sjmallett 4381215976Sjmallett/** 4382215976Sjmallett * cvmx_pci_win_rd_addr 4383215976Sjmallett * 4384215976Sjmallett * PCI_WIN_RD_ADDR = PCI Window Read Address Register 4385215976Sjmallett * 4386215976Sjmallett * Writing the least-significant-byte of this register will cause a read operation to take place, 4387215976Sjmallett * UNLESS, a read operation is already taking place. A read is consider to end when the PCI_WIN_RD_DATA 4388215976Sjmallett * register is read. 4389215976Sjmallett */ 4390232812Sjmallettunion cvmx_pci_win_rd_addr { 4391215976Sjmallett uint64_t u64; 4392232812Sjmallett struct cvmx_pci_win_rd_addr_s { 4393232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4394215976Sjmallett uint64_t reserved_49_63 : 15; 4395215976Sjmallett uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4396215976Sjmallett read as '0'. */ 4397215976Sjmallett uint64_t reserved_0_47 : 48; 4398215976Sjmallett#else 4399215976Sjmallett uint64_t reserved_0_47 : 48; 4400215976Sjmallett uint64_t iobit : 1; 4401215976Sjmallett uint64_t reserved_49_63 : 15; 4402215976Sjmallett#endif 4403215976Sjmallett } s; 4404232812Sjmallett struct cvmx_pci_win_rd_addr_cn30xx { 4405232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4406215976Sjmallett uint64_t reserved_49_63 : 15; 4407215976Sjmallett uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4408215976Sjmallett read as '0'. */ 4409215976Sjmallett uint64_t rd_addr : 46; /**< The address to be read from. Whenever the LSB of 4410215976Sjmallett this register is written, the Read Operation will 4411215976Sjmallett take place. 4412215976Sjmallett [47:40] = NCB_ID 4413215976Sjmallett [39:3] = Address 4414215976Sjmallett When [47:43] == NPI & [42:0] == 0 bits [39:0] are: 4415215976Sjmallett [39:32] == x, Not Used 4416215976Sjmallett [31:27] == RSL_ID 4417215976Sjmallett [12:2] == RSL Register Offset 4418215976Sjmallett [1:0] == x, Not Used */ 4419215976Sjmallett uint64_t reserved_0_1 : 2; 4420215976Sjmallett#else 4421215976Sjmallett uint64_t reserved_0_1 : 2; 4422215976Sjmallett uint64_t rd_addr : 46; 4423215976Sjmallett uint64_t iobit : 1; 4424215976Sjmallett uint64_t reserved_49_63 : 15; 4425215976Sjmallett#endif 4426215976Sjmallett } cn30xx; 4427215976Sjmallett struct cvmx_pci_win_rd_addr_cn30xx cn31xx; 4428232812Sjmallett struct cvmx_pci_win_rd_addr_cn38xx { 4429232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4430215976Sjmallett uint64_t reserved_49_63 : 15; 4431215976Sjmallett uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4432215976Sjmallett read as '0'. */ 4433215976Sjmallett uint64_t rd_addr : 45; /**< The address to be read from. Whenever the LSB of 4434215976Sjmallett this register is written, the Read Operation will 4435215976Sjmallett take place. 4436215976Sjmallett [47:40] = NCB_ID 4437215976Sjmallett [39:3] = Address 4438215976Sjmallett When [47:43] == NPI & [42:0] == 0 bits [39:0] are: 4439215976Sjmallett [39:32] == x, Not Used 4440215976Sjmallett [31:27] == RSL_ID 4441215976Sjmallett [12:3] == RSL Register Offset 4442215976Sjmallett [2:0] == x, Not Used */ 4443215976Sjmallett uint64_t reserved_0_2 : 3; 4444215976Sjmallett#else 4445215976Sjmallett uint64_t reserved_0_2 : 3; 4446215976Sjmallett uint64_t rd_addr : 45; 4447215976Sjmallett uint64_t iobit : 1; 4448215976Sjmallett uint64_t reserved_49_63 : 15; 4449215976Sjmallett#endif 4450215976Sjmallett } cn38xx; 4451215976Sjmallett struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2; 4452215976Sjmallett struct cvmx_pci_win_rd_addr_cn30xx cn50xx; 4453215976Sjmallett struct cvmx_pci_win_rd_addr_cn38xx cn58xx; 4454215976Sjmallett struct cvmx_pci_win_rd_addr_cn38xx cn58xxp1; 4455215976Sjmallett}; 4456215976Sjmalletttypedef union cvmx_pci_win_rd_addr cvmx_pci_win_rd_addr_t; 4457215976Sjmallett 4458215976Sjmallett/** 4459215976Sjmallett * cvmx_pci_win_rd_data 4460215976Sjmallett * 4461215976Sjmallett * PCI_WIN_RD_DATA = PCI Window Read Data Register 4462215976Sjmallett * 4463215976Sjmallett * Contains the result from the read operation that took place when the LSB of the PCI_WIN_RD_ADDR 4464215976Sjmallett * register was written. 4465215976Sjmallett */ 4466232812Sjmallettunion cvmx_pci_win_rd_data { 4467215976Sjmallett uint64_t u64; 4468232812Sjmallett struct cvmx_pci_win_rd_data_s { 4469232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4470215976Sjmallett uint64_t rd_data : 64; /**< The read data. */ 4471215976Sjmallett#else 4472215976Sjmallett uint64_t rd_data : 64; 4473215976Sjmallett#endif 4474215976Sjmallett } s; 4475215976Sjmallett struct cvmx_pci_win_rd_data_s cn30xx; 4476215976Sjmallett struct cvmx_pci_win_rd_data_s cn31xx; 4477215976Sjmallett struct cvmx_pci_win_rd_data_s cn38xx; 4478215976Sjmallett struct cvmx_pci_win_rd_data_s cn38xxp2; 4479215976Sjmallett struct cvmx_pci_win_rd_data_s cn50xx; 4480215976Sjmallett struct cvmx_pci_win_rd_data_s cn58xx; 4481215976Sjmallett struct cvmx_pci_win_rd_data_s cn58xxp1; 4482215976Sjmallett}; 4483215976Sjmalletttypedef union cvmx_pci_win_rd_data cvmx_pci_win_rd_data_t; 4484215976Sjmallett 4485215976Sjmallett/** 4486215976Sjmallett * cvmx_pci_win_wr_addr 4487215976Sjmallett * 4488215976Sjmallett * PCI_WIN_WR_ADDR = PCI Window Write Address Register 4489215976Sjmallett * 4490215976Sjmallett * Contains the address to be writen to when a write operation is started by writing the 4491215976Sjmallett * PCI_WIN_WR_DATA register (see below). 4492215976Sjmallett */ 4493232812Sjmallettunion cvmx_pci_win_wr_addr { 4494215976Sjmallett uint64_t u64; 4495232812Sjmallett struct cvmx_pci_win_wr_addr_s { 4496232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4497215976Sjmallett uint64_t reserved_49_63 : 15; 4498215976Sjmallett uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4499215976Sjmallett read as '0'. */ 4500215976Sjmallett uint64_t wr_addr : 45; /**< The address that will be written to when the 4501215976Sjmallett PCI_WIN_WR_DATA register is written. 4502215976Sjmallett [47:40] = NCB_ID 4503215976Sjmallett [39:3] = Address 4504215976Sjmallett When [47:43] == NPI & [42:0] == 0 bits [39:0] are: 4505215976Sjmallett [39:32] == x, Not Used 4506215976Sjmallett [31:27] == RSL_ID 4507215976Sjmallett [12:3] == RSL Register Offset 4508215976Sjmallett [2:0] == x, Not Used */ 4509215976Sjmallett uint64_t reserved_0_2 : 3; 4510215976Sjmallett#else 4511215976Sjmallett uint64_t reserved_0_2 : 3; 4512215976Sjmallett uint64_t wr_addr : 45; 4513215976Sjmallett uint64_t iobit : 1; 4514215976Sjmallett uint64_t reserved_49_63 : 15; 4515215976Sjmallett#endif 4516215976Sjmallett } s; 4517215976Sjmallett struct cvmx_pci_win_wr_addr_s cn30xx; 4518215976Sjmallett struct cvmx_pci_win_wr_addr_s cn31xx; 4519215976Sjmallett struct cvmx_pci_win_wr_addr_s cn38xx; 4520215976Sjmallett struct cvmx_pci_win_wr_addr_s cn38xxp2; 4521215976Sjmallett struct cvmx_pci_win_wr_addr_s cn50xx; 4522215976Sjmallett struct cvmx_pci_win_wr_addr_s cn58xx; 4523215976Sjmallett struct cvmx_pci_win_wr_addr_s cn58xxp1; 4524215976Sjmallett}; 4525215976Sjmalletttypedef union cvmx_pci_win_wr_addr cvmx_pci_win_wr_addr_t; 4526215976Sjmallett 4527215976Sjmallett/** 4528215976Sjmallett * cvmx_pci_win_wr_data 4529215976Sjmallett * 4530215976Sjmallett * PCI_WIN_WR_DATA = PCI Window Write Data Register 4531215976Sjmallett * 4532215976Sjmallett * Contains the data to write to the address located in the PCI_WIN_WR_ADDR Register. 4533215976Sjmallett * Writing the least-significant-byte of this register will cause a write operation to take place. 4534215976Sjmallett */ 4535232812Sjmallettunion cvmx_pci_win_wr_data { 4536215976Sjmallett uint64_t u64; 4537232812Sjmallett struct cvmx_pci_win_wr_data_s { 4538232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4539215976Sjmallett uint64_t wr_data : 64; /**< The data to be written. Whenever the LSB of this 4540215976Sjmallett register is written, the Window Write will take 4541215976Sjmallett place. */ 4542215976Sjmallett#else 4543215976Sjmallett uint64_t wr_data : 64; 4544215976Sjmallett#endif 4545215976Sjmallett } s; 4546215976Sjmallett struct cvmx_pci_win_wr_data_s cn30xx; 4547215976Sjmallett struct cvmx_pci_win_wr_data_s cn31xx; 4548215976Sjmallett struct cvmx_pci_win_wr_data_s cn38xx; 4549215976Sjmallett struct cvmx_pci_win_wr_data_s cn38xxp2; 4550215976Sjmallett struct cvmx_pci_win_wr_data_s cn50xx; 4551215976Sjmallett struct cvmx_pci_win_wr_data_s cn58xx; 4552215976Sjmallett struct cvmx_pci_win_wr_data_s cn58xxp1; 4553215976Sjmallett}; 4554215976Sjmalletttypedef union cvmx_pci_win_wr_data cvmx_pci_win_wr_data_t; 4555215976Sjmallett 4556215976Sjmallett/** 4557215976Sjmallett * cvmx_pci_win_wr_mask 4558215976Sjmallett * 4559215976Sjmallett * PCI_WIN_WR_MASK = PCI Window Write Mask Register 4560215976Sjmallett * 4561215976Sjmallett * Contains the mask for the data in the PCI_WIN_WR_DATA Register. 4562215976Sjmallett */ 4563232812Sjmallettunion cvmx_pci_win_wr_mask { 4564215976Sjmallett uint64_t u64; 4565232812Sjmallett struct cvmx_pci_win_wr_mask_s { 4566232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4567215976Sjmallett uint64_t reserved_8_63 : 56; 4568215976Sjmallett uint64_t wr_mask : 8; /**< The data to be written. When a bit is set '1' 4569215976Sjmallett the corresponding byte will not be written. */ 4570215976Sjmallett#else 4571215976Sjmallett uint64_t wr_mask : 8; 4572215976Sjmallett uint64_t reserved_8_63 : 56; 4573215976Sjmallett#endif 4574215976Sjmallett } s; 4575215976Sjmallett struct cvmx_pci_win_wr_mask_s cn30xx; 4576215976Sjmallett struct cvmx_pci_win_wr_mask_s cn31xx; 4577215976Sjmallett struct cvmx_pci_win_wr_mask_s cn38xx; 4578215976Sjmallett struct cvmx_pci_win_wr_mask_s cn38xxp2; 4579215976Sjmallett struct cvmx_pci_win_wr_mask_s cn50xx; 4580215976Sjmallett struct cvmx_pci_win_wr_mask_s cn58xx; 4581215976Sjmallett struct cvmx_pci_win_wr_mask_s cn58xxp1; 4582215976Sjmallett}; 4583215976Sjmalletttypedef union cvmx_pci_win_wr_mask cvmx_pci_win_wr_mask_t; 4584215976Sjmallett 4585215976Sjmallett#endif 4586