cvmx-npi.h revision 256281 
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39
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44
45
46/**
47 * @file
48 *
49 * PCI / PCIe packet engine related structures.
50 *
51 * <hr>$Revision: 70030 $<hr>
52 */
53
54#ifndef __CVMX_NPI_H__
55#define __CVMX_NPI_H__
56
57#ifdef	__cplusplus
58extern "C" {
59#endif
60
61/**
62 * PCI / PCIe packet instruction header format
63 */
64typedef union
65{
66    uint64_t u64;
67    struct
68    {
69#ifdef __BIG_ENDIAN_BITFIELD
70        uint64_t            r :     1;      /**< Packet is RAW */
71        uint64_t            g :     1;      /**< Gather list is used */
72        uint64_t            dlengsz : 14;   /**< Data length / Gather list size */
73        uint64_t            fsz     : 6;    /**< Front data size */
74        uint64_t            qos     : 3;    /**< POW QoS queue */
75        uint64_t            grp     : 4;    /**< POW Group */
76        uint64_t            rs      : 1;    /**< Real short */
77        cvmx_pow_tag_type_t tt      : 2;    /**< POW Tag type */
78        uint64_t            tag     : 32;   /**< POW 32 bit tag */
79#else
80	uint64_t            tag     : 32;
81	cvmx_pow_tag_type_t tt      : 2;
82	uint64_t            rs      : 1;
83	uint64_t            grp     : 4;
84	uint64_t            qos     : 3;
85	uint64_t            fsz     : 6;
86	uint64_t            dlengsz : 14;
87	uint64_t            g :     1;
88	uint64_t            r :     1;
89#endif
90    } s;
91} cvmx_npi_inst_hdr_t;
92
93/**
94 * PCI / PCIe packet data pointer formats 0-3
95 */
96typedef union
97{
98    uint64_t dptr0;
99    struct
100    {
101#ifdef __BIG_ENDIAN_BITFIELD
102        uint64_t    es      : 2;    /**< Endian swap mode */
103        uint64_t    ns      : 1;    /**< No snoop */
104        uint64_t    ro      : 1;    /**< Relaxed ordering */
105        uint64_t    addr    : 60;   /**< PCI/PCIe address */
106#else
107        uint64_t    addr    : 60;
108        uint64_t    ro      : 1;
109        uint64_t    ns      : 1;
110        uint64_t    es      : 2;
111#endif
112    } dptr1;
113    struct
114    {
115#ifdef __BIG_ENDIAN_BITFIELD
116        uint64_t    pm      : 2;    /**< Parse mode */
117        uint64_t    sl      : 7;    /**< Skip length */
118        uint64_t    addr    : 55;   /**< PCI/PCIe address */
119#else
120        uint64_t    addr    : 55;
121        uint64_t    sl      : 7;
122        uint64_t    pm      : 2;
123#endif
124    } dptr2;
125    struct
126    {
127#ifdef __BIG_ENDIAN_BITFIELD
128        uint64_t    es      : 2;    /**< Endian swap mode */
129        uint64_t    ns      : 1;    /**< No snoop */
130        uint64_t    ro      : 1;    /**< Relaxed ordering */
131        uint64_t    pm      : 2;    /**< Parse mode */
132        uint64_t    sl      : 7;    /**< Skip length */
133        uint64_t    addr    : 51;   /**< PCI/PCIe address */
134#else
135        uint64_t    addr    : 51;
136        uint64_t    sl      : 7;
137        uint64_t    pm      : 2;
138        uint64_t    ro      : 1;
139        uint64_t    ns      : 1;
140        uint64_t    es      : 2;
141#endif
142    } dptr3;
143} cvmx_npi_dptr_t;
144
145#ifdef	__cplusplus
146}
147#endif
148
149#endif  /* __CVMX_NPI_H__ */
150