cvmx-npi-defs.h revision 215976
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-npi-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon npi. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_NPI_TYPEDEFS_H__ 53#define __CVMX_NPI_TYPEDEFS_H__ 54 55#define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0) 56#define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1) 57#define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2) 58#define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3) 59#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 60static inline uint64_t CVMX_NPI_BASE_ADDR_INPUTX(unsigned long offset) 61{ 62 if (!( 63 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 64 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 65 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 66 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 67 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 68 cvmx_warn("CVMX_NPI_BASE_ADDR_INPUTX(%lu) is invalid on this chip\n", offset); 69 return CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16; 70} 71#else 72#define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16) 73#endif 74#define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0) 75#define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1) 76#define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2) 77#define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3) 78#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 79static inline uint64_t CVMX_NPI_BASE_ADDR_OUTPUTX(unsigned long offset) 80{ 81 if (!( 82 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 83 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 84 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 85 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 86 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 87 cvmx_warn("CVMX_NPI_BASE_ADDR_OUTPUTX(%lu) is invalid on this chip\n", offset); 88 return CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8; 89} 90#else 91#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8) 92#endif 93#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 94#define CVMX_NPI_BIST_STATUS CVMX_NPI_BIST_STATUS_FUNC() 95static inline uint64_t CVMX_NPI_BIST_STATUS_FUNC(void) 96{ 97 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 98 cvmx_warn("CVMX_NPI_BIST_STATUS not supported on this chip\n"); 99 return CVMX_ADD_IO_SEG(0x00011F00000003F8ull); 100} 101#else 102#define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull)) 103#endif 104#define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0) 105#define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1) 106#define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2) 107#define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3) 108#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 109static inline uint64_t CVMX_NPI_BUFF_SIZE_OUTPUTX(unsigned long offset) 110{ 111 if (!( 112 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 113 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 114 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 115 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 116 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 117 cvmx_warn("CVMX_NPI_BUFF_SIZE_OUTPUTX(%lu) is invalid on this chip\n", offset); 118 return CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8; 119} 120#else 121#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8) 122#endif 123#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 124#define CVMX_NPI_COMP_CTL CVMX_NPI_COMP_CTL_FUNC() 125static inline uint64_t CVMX_NPI_COMP_CTL_FUNC(void) 126{ 127 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 128 cvmx_warn("CVMX_NPI_COMP_CTL not supported on this chip\n"); 129 return CVMX_ADD_IO_SEG(0x00011F0000000218ull); 130} 131#else 132#define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull)) 133#endif 134#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 135#define CVMX_NPI_CTL_STATUS CVMX_NPI_CTL_STATUS_FUNC() 136static inline uint64_t CVMX_NPI_CTL_STATUS_FUNC(void) 137{ 138 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 139 cvmx_warn("CVMX_NPI_CTL_STATUS not supported on this chip\n"); 140 return CVMX_ADD_IO_SEG(0x00011F0000000010ull); 141} 142#else 143#define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull)) 144#endif 145#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 146#define CVMX_NPI_DBG_SELECT CVMX_NPI_DBG_SELECT_FUNC() 147static inline uint64_t CVMX_NPI_DBG_SELECT_FUNC(void) 148{ 149 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 150 cvmx_warn("CVMX_NPI_DBG_SELECT not supported on this chip\n"); 151 return CVMX_ADD_IO_SEG(0x00011F0000000008ull); 152} 153#else 154#define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull)) 155#endif 156#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 157#define CVMX_NPI_DMA_CONTROL CVMX_NPI_DMA_CONTROL_FUNC() 158static inline uint64_t CVMX_NPI_DMA_CONTROL_FUNC(void) 159{ 160 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 161 cvmx_warn("CVMX_NPI_DMA_CONTROL not supported on this chip\n"); 162 return CVMX_ADD_IO_SEG(0x00011F0000000128ull); 163} 164#else 165#define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull)) 166#endif 167#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 168#define CVMX_NPI_DMA_HIGHP_COUNTS CVMX_NPI_DMA_HIGHP_COUNTS_FUNC() 169static inline uint64_t CVMX_NPI_DMA_HIGHP_COUNTS_FUNC(void) 170{ 171 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 172 cvmx_warn("CVMX_NPI_DMA_HIGHP_COUNTS not supported on this chip\n"); 173 return CVMX_ADD_IO_SEG(0x00011F0000000148ull); 174} 175#else 176#define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull)) 177#endif 178#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 179#define CVMX_NPI_DMA_HIGHP_NADDR CVMX_NPI_DMA_HIGHP_NADDR_FUNC() 180static inline uint64_t CVMX_NPI_DMA_HIGHP_NADDR_FUNC(void) 181{ 182 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 183 cvmx_warn("CVMX_NPI_DMA_HIGHP_NADDR not supported on this chip\n"); 184 return CVMX_ADD_IO_SEG(0x00011F0000000158ull); 185} 186#else 187#define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull)) 188#endif 189#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 190#define CVMX_NPI_DMA_LOWP_COUNTS CVMX_NPI_DMA_LOWP_COUNTS_FUNC() 191static inline uint64_t CVMX_NPI_DMA_LOWP_COUNTS_FUNC(void) 192{ 193 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 194 cvmx_warn("CVMX_NPI_DMA_LOWP_COUNTS not supported on this chip\n"); 195 return CVMX_ADD_IO_SEG(0x00011F0000000140ull); 196} 197#else 198#define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull)) 199#endif 200#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 201#define CVMX_NPI_DMA_LOWP_NADDR CVMX_NPI_DMA_LOWP_NADDR_FUNC() 202static inline uint64_t CVMX_NPI_DMA_LOWP_NADDR_FUNC(void) 203{ 204 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 205 cvmx_warn("CVMX_NPI_DMA_LOWP_NADDR not supported on this chip\n"); 206 return CVMX_ADD_IO_SEG(0x00011F0000000150ull); 207} 208#else 209#define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull)) 210#endif 211#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212#define CVMX_NPI_HIGHP_DBELL CVMX_NPI_HIGHP_DBELL_FUNC() 213static inline uint64_t CVMX_NPI_HIGHP_DBELL_FUNC(void) 214{ 215 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 216 cvmx_warn("CVMX_NPI_HIGHP_DBELL not supported on this chip\n"); 217 return CVMX_ADD_IO_SEG(0x00011F0000000120ull); 218} 219#else 220#define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull)) 221#endif 222#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 223#define CVMX_NPI_HIGHP_IBUFF_SADDR CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC() 224static inline uint64_t CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC(void) 225{ 226 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 227 cvmx_warn("CVMX_NPI_HIGHP_IBUFF_SADDR not supported on this chip\n"); 228 return CVMX_ADD_IO_SEG(0x00011F0000000110ull); 229} 230#else 231#define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull)) 232#endif 233#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 234#define CVMX_NPI_INPUT_CONTROL CVMX_NPI_INPUT_CONTROL_FUNC() 235static inline uint64_t CVMX_NPI_INPUT_CONTROL_FUNC(void) 236{ 237 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 238 cvmx_warn("CVMX_NPI_INPUT_CONTROL not supported on this chip\n"); 239 return CVMX_ADD_IO_SEG(0x00011F0000000138ull); 240} 241#else 242#define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull)) 243#endif 244#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 245#define CVMX_NPI_INT_ENB CVMX_NPI_INT_ENB_FUNC() 246static inline uint64_t CVMX_NPI_INT_ENB_FUNC(void) 247{ 248 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 249 cvmx_warn("CVMX_NPI_INT_ENB not supported on this chip\n"); 250 return CVMX_ADD_IO_SEG(0x00011F0000000020ull); 251} 252#else 253#define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull)) 254#endif 255#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 256#define CVMX_NPI_INT_SUM CVMX_NPI_INT_SUM_FUNC() 257static inline uint64_t CVMX_NPI_INT_SUM_FUNC(void) 258{ 259 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 260 cvmx_warn("CVMX_NPI_INT_SUM not supported on this chip\n"); 261 return CVMX_ADD_IO_SEG(0x00011F0000000018ull); 262} 263#else 264#define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull)) 265#endif 266#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 267#define CVMX_NPI_LOWP_DBELL CVMX_NPI_LOWP_DBELL_FUNC() 268static inline uint64_t CVMX_NPI_LOWP_DBELL_FUNC(void) 269{ 270 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 271 cvmx_warn("CVMX_NPI_LOWP_DBELL not supported on this chip\n"); 272 return CVMX_ADD_IO_SEG(0x00011F0000000118ull); 273} 274#else 275#define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull)) 276#endif 277#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 278#define CVMX_NPI_LOWP_IBUFF_SADDR CVMX_NPI_LOWP_IBUFF_SADDR_FUNC() 279static inline uint64_t CVMX_NPI_LOWP_IBUFF_SADDR_FUNC(void) 280{ 281 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 282 cvmx_warn("CVMX_NPI_LOWP_IBUFF_SADDR not supported on this chip\n"); 283 return CVMX_ADD_IO_SEG(0x00011F0000000108ull); 284} 285#else 286#define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull)) 287#endif 288#define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3) 289#define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4) 290#define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5) 291#define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6) 292#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 293static inline uint64_t CVMX_NPI_MEM_ACCESS_SUBIDX(unsigned long offset) 294{ 295 if (!( 296 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 3) && (offset <= 6)))) || 297 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 3) && (offset <= 6)))) || 298 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 3) && (offset <= 6)))) || 299 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 3) && (offset <= 6)))) || 300 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 3) && (offset <= 6)))))) 301 cvmx_warn("CVMX_NPI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset); 302 return CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3; 303} 304#else 305#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3) 306#endif 307#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 308#define CVMX_NPI_MSI_RCV CVMX_NPI_MSI_RCV_FUNC() 309static inline uint64_t CVMX_NPI_MSI_RCV_FUNC(void) 310{ 311 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 312 cvmx_warn("CVMX_NPI_MSI_RCV not supported on this chip\n"); 313 return 0x0000000000000190ull; 314} 315#else 316#define CVMX_NPI_MSI_RCV (0x0000000000000190ull) 317#endif 318#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 319#define CVMX_NPI_NPI_MSI_RCV CVMX_NPI_NPI_MSI_RCV_FUNC() 320static inline uint64_t CVMX_NPI_NPI_MSI_RCV_FUNC(void) 321{ 322 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 323 cvmx_warn("CVMX_NPI_NPI_MSI_RCV not supported on this chip\n"); 324 return CVMX_ADD_IO_SEG(0x00011F0000001190ull); 325} 326#else 327#define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull)) 328#endif 329#define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0) 330#define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1) 331#define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2) 332#define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3) 333#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 334static inline uint64_t CVMX_NPI_NUM_DESC_OUTPUTX(unsigned long offset) 335{ 336 if (!( 337 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 338 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 339 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 340 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 341 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 342 cvmx_warn("CVMX_NPI_NUM_DESC_OUTPUTX(%lu) is invalid on this chip\n", offset); 343 return CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8; 344} 345#else 346#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8) 347#endif 348#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 349#define CVMX_NPI_OUTPUT_CONTROL CVMX_NPI_OUTPUT_CONTROL_FUNC() 350static inline uint64_t CVMX_NPI_OUTPUT_CONTROL_FUNC(void) 351{ 352 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 353 cvmx_warn("CVMX_NPI_OUTPUT_CONTROL not supported on this chip\n"); 354 return CVMX_ADD_IO_SEG(0x00011F0000000100ull); 355} 356#else 357#define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull)) 358#endif 359#define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0) 360#define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0) 361#define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0) 362#define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0) 363#define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1) 364#define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1) 365#define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1) 366#define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1) 367#define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2) 368#define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2) 369#define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2) 370#define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2) 371#define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3) 372#define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3) 373#define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3) 374#define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3) 375#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 376static inline uint64_t CVMX_NPI_PCI_BAR1_INDEXX(unsigned long offset) 377{ 378 if (!( 379 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) || 380 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) || 381 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) || 382 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) || 383 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31))))) 384 cvmx_warn("CVMX_NPI_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset); 385 return CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4; 386} 387#else 388#define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4) 389#endif 390#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 391#define CVMX_NPI_PCI_BIST_REG CVMX_NPI_PCI_BIST_REG_FUNC() 392static inline uint64_t CVMX_NPI_PCI_BIST_REG_FUNC(void) 393{ 394 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX))) 395 cvmx_warn("CVMX_NPI_PCI_BIST_REG not supported on this chip\n"); 396 return CVMX_ADD_IO_SEG(0x00011F00000011C0ull); 397} 398#else 399#define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull)) 400#endif 401#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 402#define CVMX_NPI_PCI_BURST_SIZE CVMX_NPI_PCI_BURST_SIZE_FUNC() 403static inline uint64_t CVMX_NPI_PCI_BURST_SIZE_FUNC(void) 404{ 405 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 406 cvmx_warn("CVMX_NPI_PCI_BURST_SIZE not supported on this chip\n"); 407 return CVMX_ADD_IO_SEG(0x00011F00000000D8ull); 408} 409#else 410#define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull)) 411#endif 412#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 413#define CVMX_NPI_PCI_CFG00 CVMX_NPI_PCI_CFG00_FUNC() 414static inline uint64_t CVMX_NPI_PCI_CFG00_FUNC(void) 415{ 416 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 417 cvmx_warn("CVMX_NPI_PCI_CFG00 not supported on this chip\n"); 418 return CVMX_ADD_IO_SEG(0x00011F0000001800ull); 419} 420#else 421#define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull)) 422#endif 423#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 424#define CVMX_NPI_PCI_CFG01 CVMX_NPI_PCI_CFG01_FUNC() 425static inline uint64_t CVMX_NPI_PCI_CFG01_FUNC(void) 426{ 427 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 428 cvmx_warn("CVMX_NPI_PCI_CFG01 not supported on this chip\n"); 429 return CVMX_ADD_IO_SEG(0x00011F0000001804ull); 430} 431#else 432#define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull)) 433#endif 434#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 435#define CVMX_NPI_PCI_CFG02 CVMX_NPI_PCI_CFG02_FUNC() 436static inline uint64_t CVMX_NPI_PCI_CFG02_FUNC(void) 437{ 438 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 439 cvmx_warn("CVMX_NPI_PCI_CFG02 not supported on this chip\n"); 440 return CVMX_ADD_IO_SEG(0x00011F0000001808ull); 441} 442#else 443#define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull)) 444#endif 445#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 446#define CVMX_NPI_PCI_CFG03 CVMX_NPI_PCI_CFG03_FUNC() 447static inline uint64_t CVMX_NPI_PCI_CFG03_FUNC(void) 448{ 449 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 450 cvmx_warn("CVMX_NPI_PCI_CFG03 not supported on this chip\n"); 451 return CVMX_ADD_IO_SEG(0x00011F000000180Cull); 452} 453#else 454#define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull)) 455#endif 456#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 457#define CVMX_NPI_PCI_CFG04 CVMX_NPI_PCI_CFG04_FUNC() 458static inline uint64_t CVMX_NPI_PCI_CFG04_FUNC(void) 459{ 460 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 461 cvmx_warn("CVMX_NPI_PCI_CFG04 not supported on this chip\n"); 462 return CVMX_ADD_IO_SEG(0x00011F0000001810ull); 463} 464#else 465#define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull)) 466#endif 467#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 468#define CVMX_NPI_PCI_CFG05 CVMX_NPI_PCI_CFG05_FUNC() 469static inline uint64_t CVMX_NPI_PCI_CFG05_FUNC(void) 470{ 471 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 472 cvmx_warn("CVMX_NPI_PCI_CFG05 not supported on this chip\n"); 473 return CVMX_ADD_IO_SEG(0x00011F0000001814ull); 474} 475#else 476#define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull)) 477#endif 478#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 479#define CVMX_NPI_PCI_CFG06 CVMX_NPI_PCI_CFG06_FUNC() 480static inline uint64_t CVMX_NPI_PCI_CFG06_FUNC(void) 481{ 482 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 483 cvmx_warn("CVMX_NPI_PCI_CFG06 not supported on this chip\n"); 484 return CVMX_ADD_IO_SEG(0x00011F0000001818ull); 485} 486#else 487#define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull)) 488#endif 489#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 490#define CVMX_NPI_PCI_CFG07 CVMX_NPI_PCI_CFG07_FUNC() 491static inline uint64_t CVMX_NPI_PCI_CFG07_FUNC(void) 492{ 493 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 494 cvmx_warn("CVMX_NPI_PCI_CFG07 not supported on this chip\n"); 495 return CVMX_ADD_IO_SEG(0x00011F000000181Cull); 496} 497#else 498#define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull)) 499#endif 500#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 501#define CVMX_NPI_PCI_CFG08 CVMX_NPI_PCI_CFG08_FUNC() 502static inline uint64_t CVMX_NPI_PCI_CFG08_FUNC(void) 503{ 504 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 505 cvmx_warn("CVMX_NPI_PCI_CFG08 not supported on this chip\n"); 506 return CVMX_ADD_IO_SEG(0x00011F0000001820ull); 507} 508#else 509#define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull)) 510#endif 511#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 512#define CVMX_NPI_PCI_CFG09 CVMX_NPI_PCI_CFG09_FUNC() 513static inline uint64_t CVMX_NPI_PCI_CFG09_FUNC(void) 514{ 515 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 516 cvmx_warn("CVMX_NPI_PCI_CFG09 not supported on this chip\n"); 517 return CVMX_ADD_IO_SEG(0x00011F0000001824ull); 518} 519#else 520#define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull)) 521#endif 522#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 523#define CVMX_NPI_PCI_CFG10 CVMX_NPI_PCI_CFG10_FUNC() 524static inline uint64_t CVMX_NPI_PCI_CFG10_FUNC(void) 525{ 526 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 527 cvmx_warn("CVMX_NPI_PCI_CFG10 not supported on this chip\n"); 528 return CVMX_ADD_IO_SEG(0x00011F0000001828ull); 529} 530#else 531#define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull)) 532#endif 533#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 534#define CVMX_NPI_PCI_CFG11 CVMX_NPI_PCI_CFG11_FUNC() 535static inline uint64_t CVMX_NPI_PCI_CFG11_FUNC(void) 536{ 537 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 538 cvmx_warn("CVMX_NPI_PCI_CFG11 not supported on this chip\n"); 539 return CVMX_ADD_IO_SEG(0x00011F000000182Cull); 540} 541#else 542#define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull)) 543#endif 544#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 545#define CVMX_NPI_PCI_CFG12 CVMX_NPI_PCI_CFG12_FUNC() 546static inline uint64_t CVMX_NPI_PCI_CFG12_FUNC(void) 547{ 548 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 549 cvmx_warn("CVMX_NPI_PCI_CFG12 not supported on this chip\n"); 550 return CVMX_ADD_IO_SEG(0x00011F0000001830ull); 551} 552#else 553#define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull)) 554#endif 555#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 556#define CVMX_NPI_PCI_CFG13 CVMX_NPI_PCI_CFG13_FUNC() 557static inline uint64_t CVMX_NPI_PCI_CFG13_FUNC(void) 558{ 559 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 560 cvmx_warn("CVMX_NPI_PCI_CFG13 not supported on this chip\n"); 561 return CVMX_ADD_IO_SEG(0x00011F0000001834ull); 562} 563#else 564#define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull)) 565#endif 566#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 567#define CVMX_NPI_PCI_CFG15 CVMX_NPI_PCI_CFG15_FUNC() 568static inline uint64_t CVMX_NPI_PCI_CFG15_FUNC(void) 569{ 570 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 571 cvmx_warn("CVMX_NPI_PCI_CFG15 not supported on this chip\n"); 572 return CVMX_ADD_IO_SEG(0x00011F000000183Cull); 573} 574#else 575#define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull)) 576#endif 577#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 578#define CVMX_NPI_PCI_CFG16 CVMX_NPI_PCI_CFG16_FUNC() 579static inline uint64_t CVMX_NPI_PCI_CFG16_FUNC(void) 580{ 581 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 582 cvmx_warn("CVMX_NPI_PCI_CFG16 not supported on this chip\n"); 583 return CVMX_ADD_IO_SEG(0x00011F0000001840ull); 584} 585#else 586#define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull)) 587#endif 588#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 589#define CVMX_NPI_PCI_CFG17 CVMX_NPI_PCI_CFG17_FUNC() 590static inline uint64_t CVMX_NPI_PCI_CFG17_FUNC(void) 591{ 592 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 593 cvmx_warn("CVMX_NPI_PCI_CFG17 not supported on this chip\n"); 594 return CVMX_ADD_IO_SEG(0x00011F0000001844ull); 595} 596#else 597#define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull)) 598#endif 599#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 600#define CVMX_NPI_PCI_CFG18 CVMX_NPI_PCI_CFG18_FUNC() 601static inline uint64_t CVMX_NPI_PCI_CFG18_FUNC(void) 602{ 603 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 604 cvmx_warn("CVMX_NPI_PCI_CFG18 not supported on this chip\n"); 605 return CVMX_ADD_IO_SEG(0x00011F0000001848ull); 606} 607#else 608#define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull)) 609#endif 610#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 611#define CVMX_NPI_PCI_CFG19 CVMX_NPI_PCI_CFG19_FUNC() 612static inline uint64_t CVMX_NPI_PCI_CFG19_FUNC(void) 613{ 614 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 615 cvmx_warn("CVMX_NPI_PCI_CFG19 not supported on this chip\n"); 616 return CVMX_ADD_IO_SEG(0x00011F000000184Cull); 617} 618#else 619#define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull)) 620#endif 621#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 622#define CVMX_NPI_PCI_CFG20 CVMX_NPI_PCI_CFG20_FUNC() 623static inline uint64_t CVMX_NPI_PCI_CFG20_FUNC(void) 624{ 625 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 626 cvmx_warn("CVMX_NPI_PCI_CFG20 not supported on this chip\n"); 627 return CVMX_ADD_IO_SEG(0x00011F0000001850ull); 628} 629#else 630#define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull)) 631#endif 632#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 633#define CVMX_NPI_PCI_CFG21 CVMX_NPI_PCI_CFG21_FUNC() 634static inline uint64_t CVMX_NPI_PCI_CFG21_FUNC(void) 635{ 636 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 637 cvmx_warn("CVMX_NPI_PCI_CFG21 not supported on this chip\n"); 638 return CVMX_ADD_IO_SEG(0x00011F0000001854ull); 639} 640#else 641#define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull)) 642#endif 643#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 644#define CVMX_NPI_PCI_CFG22 CVMX_NPI_PCI_CFG22_FUNC() 645static inline uint64_t CVMX_NPI_PCI_CFG22_FUNC(void) 646{ 647 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 648 cvmx_warn("CVMX_NPI_PCI_CFG22 not supported on this chip\n"); 649 return CVMX_ADD_IO_SEG(0x00011F0000001858ull); 650} 651#else 652#define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull)) 653#endif 654#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 655#define CVMX_NPI_PCI_CFG56 CVMX_NPI_PCI_CFG56_FUNC() 656static inline uint64_t CVMX_NPI_PCI_CFG56_FUNC(void) 657{ 658 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 659 cvmx_warn("CVMX_NPI_PCI_CFG56 not supported on this chip\n"); 660 return CVMX_ADD_IO_SEG(0x00011F00000018E0ull); 661} 662#else 663#define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull)) 664#endif 665#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 666#define CVMX_NPI_PCI_CFG57 CVMX_NPI_PCI_CFG57_FUNC() 667static inline uint64_t CVMX_NPI_PCI_CFG57_FUNC(void) 668{ 669 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 670 cvmx_warn("CVMX_NPI_PCI_CFG57 not supported on this chip\n"); 671 return CVMX_ADD_IO_SEG(0x00011F00000018E4ull); 672} 673#else 674#define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull)) 675#endif 676#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 677#define CVMX_NPI_PCI_CFG58 CVMX_NPI_PCI_CFG58_FUNC() 678static inline uint64_t CVMX_NPI_PCI_CFG58_FUNC(void) 679{ 680 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 681 cvmx_warn("CVMX_NPI_PCI_CFG58 not supported on this chip\n"); 682 return CVMX_ADD_IO_SEG(0x00011F00000018E8ull); 683} 684#else 685#define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull)) 686#endif 687#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 688#define CVMX_NPI_PCI_CFG59 CVMX_NPI_PCI_CFG59_FUNC() 689static inline uint64_t CVMX_NPI_PCI_CFG59_FUNC(void) 690{ 691 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 692 cvmx_warn("CVMX_NPI_PCI_CFG59 not supported on this chip\n"); 693 return CVMX_ADD_IO_SEG(0x00011F00000018ECull); 694} 695#else 696#define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull)) 697#endif 698#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 699#define CVMX_NPI_PCI_CFG60 CVMX_NPI_PCI_CFG60_FUNC() 700static inline uint64_t CVMX_NPI_PCI_CFG60_FUNC(void) 701{ 702 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 703 cvmx_warn("CVMX_NPI_PCI_CFG60 not supported on this chip\n"); 704 return CVMX_ADD_IO_SEG(0x00011F00000018F0ull); 705} 706#else 707#define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull)) 708#endif 709#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 710#define CVMX_NPI_PCI_CFG61 CVMX_NPI_PCI_CFG61_FUNC() 711static inline uint64_t CVMX_NPI_PCI_CFG61_FUNC(void) 712{ 713 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 714 cvmx_warn("CVMX_NPI_PCI_CFG61 not supported on this chip\n"); 715 return CVMX_ADD_IO_SEG(0x00011F00000018F4ull); 716} 717#else 718#define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull)) 719#endif 720#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 721#define CVMX_NPI_PCI_CFG62 CVMX_NPI_PCI_CFG62_FUNC() 722static inline uint64_t CVMX_NPI_PCI_CFG62_FUNC(void) 723{ 724 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 725 cvmx_warn("CVMX_NPI_PCI_CFG62 not supported on this chip\n"); 726 return CVMX_ADD_IO_SEG(0x00011F00000018F8ull); 727} 728#else 729#define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull)) 730#endif 731#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 732#define CVMX_NPI_PCI_CFG63 CVMX_NPI_PCI_CFG63_FUNC() 733static inline uint64_t CVMX_NPI_PCI_CFG63_FUNC(void) 734{ 735 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 736 cvmx_warn("CVMX_NPI_PCI_CFG63 not supported on this chip\n"); 737 return CVMX_ADD_IO_SEG(0x00011F00000018FCull); 738} 739#else 740#define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull)) 741#endif 742#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 743#define CVMX_NPI_PCI_CNT_REG CVMX_NPI_PCI_CNT_REG_FUNC() 744static inline uint64_t CVMX_NPI_PCI_CNT_REG_FUNC(void) 745{ 746 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 747 cvmx_warn("CVMX_NPI_PCI_CNT_REG not supported on this chip\n"); 748 return CVMX_ADD_IO_SEG(0x00011F00000011B8ull); 749} 750#else 751#define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull)) 752#endif 753#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 754#define CVMX_NPI_PCI_CTL_STATUS_2 CVMX_NPI_PCI_CTL_STATUS_2_FUNC() 755static inline uint64_t CVMX_NPI_PCI_CTL_STATUS_2_FUNC(void) 756{ 757 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 758 cvmx_warn("CVMX_NPI_PCI_CTL_STATUS_2 not supported on this chip\n"); 759 return CVMX_ADD_IO_SEG(0x00011F000000118Cull); 760} 761#else 762#define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull)) 763#endif 764#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 765#define CVMX_NPI_PCI_INT_ARB_CFG CVMX_NPI_PCI_INT_ARB_CFG_FUNC() 766static inline uint64_t CVMX_NPI_PCI_INT_ARB_CFG_FUNC(void) 767{ 768 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 769 cvmx_warn("CVMX_NPI_PCI_INT_ARB_CFG not supported on this chip\n"); 770 return CVMX_ADD_IO_SEG(0x00011F0000000130ull); 771} 772#else 773#define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull)) 774#endif 775#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 776#define CVMX_NPI_PCI_INT_ENB2 CVMX_NPI_PCI_INT_ENB2_FUNC() 777static inline uint64_t CVMX_NPI_PCI_INT_ENB2_FUNC(void) 778{ 779 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 780 cvmx_warn("CVMX_NPI_PCI_INT_ENB2 not supported on this chip\n"); 781 return CVMX_ADD_IO_SEG(0x00011F00000011A0ull); 782} 783#else 784#define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull)) 785#endif 786#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 787#define CVMX_NPI_PCI_INT_SUM2 CVMX_NPI_PCI_INT_SUM2_FUNC() 788static inline uint64_t CVMX_NPI_PCI_INT_SUM2_FUNC(void) 789{ 790 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 791 cvmx_warn("CVMX_NPI_PCI_INT_SUM2 not supported on this chip\n"); 792 return CVMX_ADD_IO_SEG(0x00011F0000001198ull); 793} 794#else 795#define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull)) 796#endif 797#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 798#define CVMX_NPI_PCI_READ_CMD CVMX_NPI_PCI_READ_CMD_FUNC() 799static inline uint64_t CVMX_NPI_PCI_READ_CMD_FUNC(void) 800{ 801 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 802 cvmx_warn("CVMX_NPI_PCI_READ_CMD not supported on this chip\n"); 803 return CVMX_ADD_IO_SEG(0x00011F0000000048ull); 804} 805#else 806#define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull)) 807#endif 808#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 809#define CVMX_NPI_PCI_READ_CMD_6 CVMX_NPI_PCI_READ_CMD_6_FUNC() 810static inline uint64_t CVMX_NPI_PCI_READ_CMD_6_FUNC(void) 811{ 812 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 813 cvmx_warn("CVMX_NPI_PCI_READ_CMD_6 not supported on this chip\n"); 814 return CVMX_ADD_IO_SEG(0x00011F0000001180ull); 815} 816#else 817#define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull)) 818#endif 819#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 820#define CVMX_NPI_PCI_READ_CMD_C CVMX_NPI_PCI_READ_CMD_C_FUNC() 821static inline uint64_t CVMX_NPI_PCI_READ_CMD_C_FUNC(void) 822{ 823 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 824 cvmx_warn("CVMX_NPI_PCI_READ_CMD_C not supported on this chip\n"); 825 return CVMX_ADD_IO_SEG(0x00011F0000001184ull); 826} 827#else 828#define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull)) 829#endif 830#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 831#define CVMX_NPI_PCI_READ_CMD_E CVMX_NPI_PCI_READ_CMD_E_FUNC() 832static inline uint64_t CVMX_NPI_PCI_READ_CMD_E_FUNC(void) 833{ 834 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 835 cvmx_warn("CVMX_NPI_PCI_READ_CMD_E not supported on this chip\n"); 836 return CVMX_ADD_IO_SEG(0x00011F0000001188ull); 837} 838#else 839#define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull)) 840#endif 841#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 842#define CVMX_NPI_PCI_SCM_REG CVMX_NPI_PCI_SCM_REG_FUNC() 843static inline uint64_t CVMX_NPI_PCI_SCM_REG_FUNC(void) 844{ 845 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 846 cvmx_warn("CVMX_NPI_PCI_SCM_REG not supported on this chip\n"); 847 return CVMX_ADD_IO_SEG(0x00011F00000011A8ull); 848} 849#else 850#define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull)) 851#endif 852#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 853#define CVMX_NPI_PCI_TSR_REG CVMX_NPI_PCI_TSR_REG_FUNC() 854static inline uint64_t CVMX_NPI_PCI_TSR_REG_FUNC(void) 855{ 856 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 857 cvmx_warn("CVMX_NPI_PCI_TSR_REG not supported on this chip\n"); 858 return CVMX_ADD_IO_SEG(0x00011F00000011B0ull); 859} 860#else 861#define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull)) 862#endif 863#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 864#define CVMX_NPI_PORT32_INSTR_HDR CVMX_NPI_PORT32_INSTR_HDR_FUNC() 865static inline uint64_t CVMX_NPI_PORT32_INSTR_HDR_FUNC(void) 866{ 867 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 868 cvmx_warn("CVMX_NPI_PORT32_INSTR_HDR not supported on this chip\n"); 869 return CVMX_ADD_IO_SEG(0x00011F00000001F8ull); 870} 871#else 872#define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull)) 873#endif 874#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 875#define CVMX_NPI_PORT33_INSTR_HDR CVMX_NPI_PORT33_INSTR_HDR_FUNC() 876static inline uint64_t CVMX_NPI_PORT33_INSTR_HDR_FUNC(void) 877{ 878 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 879 cvmx_warn("CVMX_NPI_PORT33_INSTR_HDR not supported on this chip\n"); 880 return CVMX_ADD_IO_SEG(0x00011F0000000200ull); 881} 882#else 883#define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull)) 884#endif 885#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 886#define CVMX_NPI_PORT34_INSTR_HDR CVMX_NPI_PORT34_INSTR_HDR_FUNC() 887static inline uint64_t CVMX_NPI_PORT34_INSTR_HDR_FUNC(void) 888{ 889 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 890 cvmx_warn("CVMX_NPI_PORT34_INSTR_HDR not supported on this chip\n"); 891 return CVMX_ADD_IO_SEG(0x00011F0000000208ull); 892} 893#else 894#define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull)) 895#endif 896#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 897#define CVMX_NPI_PORT35_INSTR_HDR CVMX_NPI_PORT35_INSTR_HDR_FUNC() 898static inline uint64_t CVMX_NPI_PORT35_INSTR_HDR_FUNC(void) 899{ 900 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 901 cvmx_warn("CVMX_NPI_PORT35_INSTR_HDR not supported on this chip\n"); 902 return CVMX_ADD_IO_SEG(0x00011F0000000210ull); 903} 904#else 905#define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull)) 906#endif 907#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 908#define CVMX_NPI_PORT_BP_CONTROL CVMX_NPI_PORT_BP_CONTROL_FUNC() 909static inline uint64_t CVMX_NPI_PORT_BP_CONTROL_FUNC(void) 910{ 911 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 912 cvmx_warn("CVMX_NPI_PORT_BP_CONTROL not supported on this chip\n"); 913 return CVMX_ADD_IO_SEG(0x00011F00000001F0ull); 914} 915#else 916#define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull)) 917#endif 918#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 919static inline uint64_t CVMX_NPI_PX_DBPAIR_ADDR(unsigned long offset) 920{ 921 if (!( 922 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 923 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 924 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 925 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 926 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 927 cvmx_warn("CVMX_NPI_PX_DBPAIR_ADDR(%lu) is invalid on this chip\n", offset); 928 return CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8; 929} 930#else 931#define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8) 932#endif 933#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 934static inline uint64_t CVMX_NPI_PX_INSTR_ADDR(unsigned long offset) 935{ 936 if (!( 937 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 938 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 939 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 940 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 941 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 942 cvmx_warn("CVMX_NPI_PX_INSTR_ADDR(%lu) is invalid on this chip\n", offset); 943 return CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8; 944} 945#else 946#define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8) 947#endif 948#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 949static inline uint64_t CVMX_NPI_PX_INSTR_CNTS(unsigned long offset) 950{ 951 if (!( 952 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 953 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 954 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 955 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 956 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 957 cvmx_warn("CVMX_NPI_PX_INSTR_CNTS(%lu) is invalid on this chip\n", offset); 958 return CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8; 959} 960#else 961#define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8) 962#endif 963#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 964static inline uint64_t CVMX_NPI_PX_PAIR_CNTS(unsigned long offset) 965{ 966 if (!( 967 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 968 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 969 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 970 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 971 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 972 cvmx_warn("CVMX_NPI_PX_PAIR_CNTS(%lu) is invalid on this chip\n", offset); 973 return CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8; 974} 975#else 976#define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8) 977#endif 978#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 979#define CVMX_NPI_RSL_INT_BLOCKS CVMX_NPI_RSL_INT_BLOCKS_FUNC() 980static inline uint64_t CVMX_NPI_RSL_INT_BLOCKS_FUNC(void) 981{ 982 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 983 cvmx_warn("CVMX_NPI_RSL_INT_BLOCKS not supported on this chip\n"); 984 return CVMX_ADD_IO_SEG(0x00011F0000000000ull); 985} 986#else 987#define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull)) 988#endif 989#define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0) 990#define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1) 991#define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2) 992#define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3) 993#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 994static inline uint64_t CVMX_NPI_SIZE_INPUTX(unsigned long offset) 995{ 996 if (!( 997 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 998 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 999 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 1000 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1001 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 1002 cvmx_warn("CVMX_NPI_SIZE_INPUTX(%lu) is invalid on this chip\n", offset); 1003 return CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16; 1004} 1005#else 1006#define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16) 1007#endif 1008#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1009#define CVMX_NPI_WIN_READ_TO CVMX_NPI_WIN_READ_TO_FUNC() 1010static inline uint64_t CVMX_NPI_WIN_READ_TO_FUNC(void) 1011{ 1012 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 1013 cvmx_warn("CVMX_NPI_WIN_READ_TO not supported on this chip\n"); 1014 return CVMX_ADD_IO_SEG(0x00011F00000001E0ull); 1015} 1016#else 1017#define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull)) 1018#endif 1019 1020/** 1021 * cvmx_npi_base_addr_input# 1022 * 1023 * NPI_BASE_ADDR_INPUT0 = NPI's Base Address Input 0 Register 1024 * 1025 * The address to start reading Instructions from for Input-0. 1026 */ 1027union cvmx_npi_base_addr_inputx 1028{ 1029 uint64_t u64; 1030 struct cvmx_npi_base_addr_inputx_s 1031 { 1032#if __BYTE_ORDER == __BIG_ENDIAN 1033 uint64_t baddr : 61; /**< The address to read Instruction from for output 0. 1034 This address is 8-byte aligned, for this reason 1035 address bits [2:0] will always be zero. */ 1036 uint64_t reserved_0_2 : 3; 1037#else 1038 uint64_t reserved_0_2 : 3; 1039 uint64_t baddr : 61; 1040#endif 1041 } s; 1042 struct cvmx_npi_base_addr_inputx_s cn30xx; 1043 struct cvmx_npi_base_addr_inputx_s cn31xx; 1044 struct cvmx_npi_base_addr_inputx_s cn38xx; 1045 struct cvmx_npi_base_addr_inputx_s cn38xxp2; 1046 struct cvmx_npi_base_addr_inputx_s cn50xx; 1047 struct cvmx_npi_base_addr_inputx_s cn58xx; 1048 struct cvmx_npi_base_addr_inputx_s cn58xxp1; 1049}; 1050typedef union cvmx_npi_base_addr_inputx cvmx_npi_base_addr_inputx_t; 1051 1052/** 1053 * cvmx_npi_base_addr_output# 1054 * 1055 * NPI_BASE_ADDR_OUTPUT0 = NPI's Base Address Output 0 Register 1056 * 1057 * The address to start reading Instructions from for Output-0. 1058 */ 1059union cvmx_npi_base_addr_outputx 1060{ 1061 uint64_t u64; 1062 struct cvmx_npi_base_addr_outputx_s 1063 { 1064#if __BYTE_ORDER == __BIG_ENDIAN 1065 uint64_t baddr : 61; /**< The address to read Instruction from for output 0. 1066 This address is 8-byte aligned, for this reason 1067 address bits [2:0] will always be zero. */ 1068 uint64_t reserved_0_2 : 3; 1069#else 1070 uint64_t reserved_0_2 : 3; 1071 uint64_t baddr : 61; 1072#endif 1073 } s; 1074 struct cvmx_npi_base_addr_outputx_s cn30xx; 1075 struct cvmx_npi_base_addr_outputx_s cn31xx; 1076 struct cvmx_npi_base_addr_outputx_s cn38xx; 1077 struct cvmx_npi_base_addr_outputx_s cn38xxp2; 1078 struct cvmx_npi_base_addr_outputx_s cn50xx; 1079 struct cvmx_npi_base_addr_outputx_s cn58xx; 1080 struct cvmx_npi_base_addr_outputx_s cn58xxp1; 1081}; 1082typedef union cvmx_npi_base_addr_outputx cvmx_npi_base_addr_outputx_t; 1083 1084/** 1085 * cvmx_npi_bist_status 1086 * 1087 * NPI_BIST_STATUS = NPI's BIST Status Register 1088 * 1089 * Results from BIST runs of NPI's memories. 1090 */ 1091union cvmx_npi_bist_status 1092{ 1093 uint64_t u64; 1094 struct cvmx_npi_bist_status_s 1095 { 1096#if __BYTE_ORDER == __BIG_ENDIAN 1097 uint64_t reserved_20_63 : 44; 1098 uint64_t csr_bs : 1; /**< BIST Status for the csr_fifo */ 1099 uint64_t dif_bs : 1; /**< BIST Status for the dif_fifo */ 1100 uint64_t rdp_bs : 1; /**< BIST Status for the rdp_fifo */ 1101 uint64_t pcnc_bs : 1; /**< BIST Status for the pcn_cnt_fifo */ 1102 uint64_t pcn_bs : 1; /**< BIST Status for the pcn_fifo */ 1103 uint64_t rdn_bs : 1; /**< BIST Status for the rdn_fifo */ 1104 uint64_t pcac_bs : 1; /**< BIST Status for the pca_cmd_fifo */ 1105 uint64_t pcad_bs : 1; /**< BIST Status for the pca_data_fifo */ 1106 uint64_t rdnl_bs : 1; /**< BIST Status for the rdn_length_fifo */ 1107 uint64_t pgf_bs : 1; /**< BIST Status for the pgf_fifo */ 1108 uint64_t pig_bs : 1; /**< BIST Status for the pig_fifo */ 1109 uint64_t pof0_bs : 1; /**< BIST Status for the pof0_fifo */ 1110 uint64_t pof1_bs : 1; /**< BIST Status for the pof1_fifo */ 1111 uint64_t pof2_bs : 1; /**< BIST Status for the pof2_fifo */ 1112 uint64_t pof3_bs : 1; /**< BIST Status for the pof3_fifo */ 1113 uint64_t pos_bs : 1; /**< BIST Status for the pos_fifo */ 1114 uint64_t nus_bs : 1; /**< BIST Status for the nus_fifo */ 1115 uint64_t dob_bs : 1; /**< BIST Status for the dob_fifo */ 1116 uint64_t pdf_bs : 1; /**< BIST Status for the pdf_fifo */ 1117 uint64_t dpi_bs : 1; /**< BIST Status for the dpi_fifo */ 1118#else 1119 uint64_t dpi_bs : 1; 1120 uint64_t pdf_bs : 1; 1121 uint64_t dob_bs : 1; 1122 uint64_t nus_bs : 1; 1123 uint64_t pos_bs : 1; 1124 uint64_t pof3_bs : 1; 1125 uint64_t pof2_bs : 1; 1126 uint64_t pof1_bs : 1; 1127 uint64_t pof0_bs : 1; 1128 uint64_t pig_bs : 1; 1129 uint64_t pgf_bs : 1; 1130 uint64_t rdnl_bs : 1; 1131 uint64_t pcad_bs : 1; 1132 uint64_t pcac_bs : 1; 1133 uint64_t rdn_bs : 1; 1134 uint64_t pcn_bs : 1; 1135 uint64_t pcnc_bs : 1; 1136 uint64_t rdp_bs : 1; 1137 uint64_t dif_bs : 1; 1138 uint64_t csr_bs : 1; 1139 uint64_t reserved_20_63 : 44; 1140#endif 1141 } s; 1142 struct cvmx_npi_bist_status_cn30xx 1143 { 1144#if __BYTE_ORDER == __BIG_ENDIAN 1145 uint64_t reserved_20_63 : 44; 1146 uint64_t csr_bs : 1; /**< BIST Status for the csr_fifo */ 1147 uint64_t dif_bs : 1; /**< BIST Status for the dif_fifo */ 1148 uint64_t rdp_bs : 1; /**< BIST Status for the rdp_fifo */ 1149 uint64_t pcnc_bs : 1; /**< BIST Status for the pcn_cnt_fifo */ 1150 uint64_t pcn_bs : 1; /**< BIST Status for the pcn_fifo */ 1151 uint64_t rdn_bs : 1; /**< BIST Status for the rdn_fifo */ 1152 uint64_t pcac_bs : 1; /**< BIST Status for the pca_cmd_fifo */ 1153 uint64_t pcad_bs : 1; /**< BIST Status for the pca_data_fifo */ 1154 uint64_t rdnl_bs : 1; /**< BIST Status for the rdn_length_fifo */ 1155 uint64_t pgf_bs : 1; /**< BIST Status for the pgf_fifo */ 1156 uint64_t pig_bs : 1; /**< BIST Status for the pig_fifo */ 1157 uint64_t pof0_bs : 1; /**< BIST Status for the pof0_fifo */ 1158 uint64_t reserved_5_7 : 3; 1159 uint64_t pos_bs : 1; /**< BIST Status for the pos_fifo */ 1160 uint64_t nus_bs : 1; /**< BIST Status for the nus_fifo */ 1161 uint64_t dob_bs : 1; /**< BIST Status for the dob_fifo */ 1162 uint64_t pdf_bs : 1; /**< BIST Status for the pdf_fifo */ 1163 uint64_t dpi_bs : 1; /**< BIST Status for the dpi_fifo */ 1164#else 1165 uint64_t dpi_bs : 1; 1166 uint64_t pdf_bs : 1; 1167 uint64_t dob_bs : 1; 1168 uint64_t nus_bs : 1; 1169 uint64_t pos_bs : 1; 1170 uint64_t reserved_5_7 : 3; 1171 uint64_t pof0_bs : 1; 1172 uint64_t pig_bs : 1; 1173 uint64_t pgf_bs : 1; 1174 uint64_t rdnl_bs : 1; 1175 uint64_t pcad_bs : 1; 1176 uint64_t pcac_bs : 1; 1177 uint64_t rdn_bs : 1; 1178 uint64_t pcn_bs : 1; 1179 uint64_t pcnc_bs : 1; 1180 uint64_t rdp_bs : 1; 1181 uint64_t dif_bs : 1; 1182 uint64_t csr_bs : 1; 1183 uint64_t reserved_20_63 : 44; 1184#endif 1185 } cn30xx; 1186 struct cvmx_npi_bist_status_s cn31xx; 1187 struct cvmx_npi_bist_status_s cn38xx; 1188 struct cvmx_npi_bist_status_s cn38xxp2; 1189 struct cvmx_npi_bist_status_cn50xx 1190 { 1191#if __BYTE_ORDER == __BIG_ENDIAN 1192 uint64_t reserved_20_63 : 44; 1193 uint64_t csr_bs : 1; /**< BIST Status for the csr_fifo */ 1194 uint64_t dif_bs : 1; /**< BIST Status for the dif_fifo */ 1195 uint64_t rdp_bs : 1; /**< BIST Status for the rdp_fifo */ 1196 uint64_t pcnc_bs : 1; /**< BIST Status for the pcn_cnt_fifo */ 1197 uint64_t pcn_bs : 1; /**< BIST Status for the pcn_fifo */ 1198 uint64_t rdn_bs : 1; /**< BIST Status for the rdn_fifo */ 1199 uint64_t pcac_bs : 1; /**< BIST Status for the pca_cmd_fifo */ 1200 uint64_t pcad_bs : 1; /**< BIST Status for the pca_data_fifo */ 1201 uint64_t rdnl_bs : 1; /**< BIST Status for the rdn_length_fifo */ 1202 uint64_t pgf_bs : 1; /**< BIST Status for the pgf_fifo */ 1203 uint64_t pig_bs : 1; /**< BIST Status for the pig_fifo */ 1204 uint64_t pof0_bs : 1; /**< BIST Status for the pof0_fifo */ 1205 uint64_t pof1_bs : 1; /**< BIST Status for the pof1_fifo */ 1206 uint64_t reserved_5_6 : 2; 1207 uint64_t pos_bs : 1; /**< BIST Status for the pos_fifo */ 1208 uint64_t nus_bs : 1; /**< BIST Status for the nus_fifo */ 1209 uint64_t dob_bs : 1; /**< BIST Status for the dob_fifo */ 1210 uint64_t pdf_bs : 1; /**< BIST Status for the pdf_fifo */ 1211 uint64_t dpi_bs : 1; /**< BIST Status for the dpi_fifo */ 1212#else 1213 uint64_t dpi_bs : 1; 1214 uint64_t pdf_bs : 1; 1215 uint64_t dob_bs : 1; 1216 uint64_t nus_bs : 1; 1217 uint64_t pos_bs : 1; 1218 uint64_t reserved_5_6 : 2; 1219 uint64_t pof1_bs : 1; 1220 uint64_t pof0_bs : 1; 1221 uint64_t pig_bs : 1; 1222 uint64_t pgf_bs : 1; 1223 uint64_t rdnl_bs : 1; 1224 uint64_t pcad_bs : 1; 1225 uint64_t pcac_bs : 1; 1226 uint64_t rdn_bs : 1; 1227 uint64_t pcn_bs : 1; 1228 uint64_t pcnc_bs : 1; 1229 uint64_t rdp_bs : 1; 1230 uint64_t dif_bs : 1; 1231 uint64_t csr_bs : 1; 1232 uint64_t reserved_20_63 : 44; 1233#endif 1234 } cn50xx; 1235 struct cvmx_npi_bist_status_s cn58xx; 1236 struct cvmx_npi_bist_status_s cn58xxp1; 1237}; 1238typedef union cvmx_npi_bist_status cvmx_npi_bist_status_t; 1239 1240/** 1241 * cvmx_npi_buff_size_output# 1242 * 1243 * NPI_BUFF_SIZE_OUTPUT0 = NPI's D/I Buffer Sizes For Output 0 1244 * 1245 * The size in bytes of the Data Bufffer and Information Buffer for output 0. 1246 */ 1247union cvmx_npi_buff_size_outputx 1248{ 1249 uint64_t u64; 1250 struct cvmx_npi_buff_size_outputx_s 1251 { 1252#if __BYTE_ORDER == __BIG_ENDIAN 1253 uint64_t reserved_23_63 : 41; 1254 uint64_t isize : 7; /**< The number of bytes to move to the Info-Pointer 1255 from the front of the packet. 1256 Legal values are 0-120. */ 1257 uint64_t bsize : 16; /**< The size in bytes of the area pointed to by 1258 buffer pointer for output packet data. */ 1259#else 1260 uint64_t bsize : 16; 1261 uint64_t isize : 7; 1262 uint64_t reserved_23_63 : 41; 1263#endif 1264 } s; 1265 struct cvmx_npi_buff_size_outputx_s cn30xx; 1266 struct cvmx_npi_buff_size_outputx_s cn31xx; 1267 struct cvmx_npi_buff_size_outputx_s cn38xx; 1268 struct cvmx_npi_buff_size_outputx_s cn38xxp2; 1269 struct cvmx_npi_buff_size_outputx_s cn50xx; 1270 struct cvmx_npi_buff_size_outputx_s cn58xx; 1271 struct cvmx_npi_buff_size_outputx_s cn58xxp1; 1272}; 1273typedef union cvmx_npi_buff_size_outputx cvmx_npi_buff_size_outputx_t; 1274 1275/** 1276 * cvmx_npi_comp_ctl 1277 * 1278 * NPI_COMP_CTL = PCI Compensation Control 1279 * 1280 * PCI Compensation Control 1281 */ 1282union cvmx_npi_comp_ctl 1283{ 1284 uint64_t u64; 1285 struct cvmx_npi_comp_ctl_s 1286 { 1287#if __BYTE_ORDER == __BIG_ENDIAN 1288 uint64_t reserved_10_63 : 54; 1289 uint64_t pctl : 5; /**< Bypass value for PCTL */ 1290 uint64_t nctl : 5; /**< Bypass value for NCTL */ 1291#else 1292 uint64_t nctl : 5; 1293 uint64_t pctl : 5; 1294 uint64_t reserved_10_63 : 54; 1295#endif 1296 } s; 1297 struct cvmx_npi_comp_ctl_s cn50xx; 1298 struct cvmx_npi_comp_ctl_s cn58xx; 1299 struct cvmx_npi_comp_ctl_s cn58xxp1; 1300}; 1301typedef union cvmx_npi_comp_ctl cvmx_npi_comp_ctl_t; 1302 1303/** 1304 * cvmx_npi_ctl_status 1305 * 1306 * NPI_CTL_STATUS = NPI's Control Status Register 1307 * 1308 * Contains control ans status for NPI. 1309 * Writes to this register are not ordered with writes/reads to the PCI Memory space. 1310 * To ensure that a write has completed the user must read the register before 1311 * making an access(i.e. PCI memory space) that requires the value of this register to be updated. 1312 */ 1313union cvmx_npi_ctl_status 1314{ 1315 uint64_t u64; 1316 struct cvmx_npi_ctl_status_s 1317 { 1318#if __BYTE_ORDER == __BIG_ENDIAN 1319 uint64_t reserved_63_63 : 1; 1320 uint64_t chip_rev : 8; /**< The revision of the N3. */ 1321 uint64_t dis_pniw : 1; /**< When asserted '1' access from the PNI Window 1322 Registers are disabled. */ 1323 uint64_t out3_enb : 1; /**< When asserted '1' the output3 engine is enabled. 1324 After enabling the values of the associated 1325 Address and Size Register should not be changed. */ 1326 uint64_t out2_enb : 1; /**< When asserted '1' the output2 engine is enabled. 1327 After enabling the values of the associated 1328 Address and Size Register should not be changed. */ 1329 uint64_t out1_enb : 1; /**< When asserted '1' the output1 engine is enabled. 1330 After enabling the values of the associated 1331 Address and Size Register should not be changed. */ 1332 uint64_t out0_enb : 1; /**< When asserted '1' the output0 engine is enabled. 1333 After enabling the values of the associated 1334 Address and Size Register should not be changed. */ 1335 uint64_t ins3_enb : 1; /**< When asserted '1' the gather3 engine is enabled. 1336 After enabling the values of the associated 1337 Address and Size Register should not be changed. */ 1338 uint64_t ins2_enb : 1; /**< When asserted '1' the gather2 engine is enabled. 1339 After enabling the values of the associated 1340 Address and Size Register should not be changed. */ 1341 uint64_t ins1_enb : 1; /**< When asserted '1' the gather1 engine is enabled. 1342 After enabling the values of the associated 1343 Address and Size Register should not be changed. */ 1344 uint64_t ins0_enb : 1; /**< When asserted '1' the gather0 engine is enabled. 1345 After enabling the values of the associated 1346 Address and Size Register should not be changed. */ 1347 uint64_t ins3_64b : 1; /**< When asserted '1' the instructions read by the 1348 gather3 engine are 64-Byte instructions, when 1349 de-asserted '0' instructions are 32-byte. */ 1350 uint64_t ins2_64b : 1; /**< When asserted '1' the instructions read by the 1351 gather2 engine are 64-Byte instructions, when 1352 de-asserted '0' instructions are 32-byte. */ 1353 uint64_t ins1_64b : 1; /**< When asserted '1' the instructions read by the 1354 gather1 engine are 64-Byte instructions, when 1355 de-asserted '0' instructions are 32-byte. */ 1356 uint64_t ins0_64b : 1; /**< When asserted '1' the instructions read by the 1357 gather0 engine are 64-Byte instructions, when 1358 de-asserted '0' instructions are 32-byte. */ 1359 uint64_t pci_wdis : 1; /**< When set '1' disables access to registers in 1360 PNI address range 0x1000 - 0x17FF from the PCI. */ 1361 uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit 1362 from the L2C before sending additional access to 1363 the L2C from the PCI. */ 1364 uint64_t reserved_37_39 : 3; 1365 uint64_t max_word : 5; /**< The maximum number of words to merge into a single 1366 write operation from the PPs to the PCI. Legal 1367 values are 1 to 32, where a '0' is treated as 32. */ 1368 uint64_t reserved_10_31 : 22; 1369 uint64_t timer : 10; /**< When the NPI starts a PP to PCI write it will wait 1370 no longer than the value of TIMER in eclks to 1371 merge additional writes from the PPs into 1 1372 large write. The values for this field is 1 to 1373 1024 where a value of '0' is treated as 1024. */ 1374#else 1375 uint64_t timer : 10; 1376 uint64_t reserved_10_31 : 22; 1377 uint64_t max_word : 5; 1378 uint64_t reserved_37_39 : 3; 1379 uint64_t wait_com : 1; 1380 uint64_t pci_wdis : 1; 1381 uint64_t ins0_64b : 1; 1382 uint64_t ins1_64b : 1; 1383 uint64_t ins2_64b : 1; 1384 uint64_t ins3_64b : 1; 1385 uint64_t ins0_enb : 1; 1386 uint64_t ins1_enb : 1; 1387 uint64_t ins2_enb : 1; 1388 uint64_t ins3_enb : 1; 1389 uint64_t out0_enb : 1; 1390 uint64_t out1_enb : 1; 1391 uint64_t out2_enb : 1; 1392 uint64_t out3_enb : 1; 1393 uint64_t dis_pniw : 1; 1394 uint64_t chip_rev : 8; 1395 uint64_t reserved_63_63 : 1; 1396#endif 1397 } s; 1398 struct cvmx_npi_ctl_status_cn30xx 1399 { 1400#if __BYTE_ORDER == __BIG_ENDIAN 1401 uint64_t reserved_63_63 : 1; 1402 uint64_t chip_rev : 8; /**< The revision of the N3. */ 1403 uint64_t dis_pniw : 1; /**< When asserted '1' access from the PNI Window 1404 Registers are disabled. */ 1405 uint64_t reserved_51_53 : 3; 1406 uint64_t out0_enb : 1; /**< When asserted '1' the output0 engine is enabled. 1407 After enabling the values of the associated 1408 Address and Size Register should not be changed. */ 1409 uint64_t reserved_47_49 : 3; 1410 uint64_t ins0_enb : 1; /**< When asserted '1' the gather0 engine is enabled. 1411 After enabling the values of the associated 1412 Address and Size Register should not be changed. */ 1413 uint64_t reserved_43_45 : 3; 1414 uint64_t ins0_64b : 1; /**< When asserted '1' the instructions read by the 1415 gather0 engine are 64-Byte instructions, when 1416 de-asserted '0' instructions are 32-byte. */ 1417 uint64_t pci_wdis : 1; /**< When set '1' disables access to registers in 1418 PNI address range 0x1000 - 0x17FF from the PCI. */ 1419 uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit 1420 from the L2C before sending additional access to 1421 the L2C from the PCI. */ 1422 uint64_t reserved_37_39 : 3; 1423 uint64_t max_word : 5; /**< The maximum number of words to merge into a single 1424 write operation from the PPs to the PCI. Legal 1425 values are 1 to 32, where a '0' is treated as 32. */ 1426 uint64_t reserved_10_31 : 22; 1427 uint64_t timer : 10; /**< When the NPI starts a PP to PCI write it will wait 1428 no longer than the value of TIMER in eclks to 1429 merge additional writes from the PPs into 1 1430 large write. The values for this field is 1 to 1431 1024 where a value of '0' is treated as 1024. */ 1432#else 1433 uint64_t timer : 10; 1434 uint64_t reserved_10_31 : 22; 1435 uint64_t max_word : 5; 1436 uint64_t reserved_37_39 : 3; 1437 uint64_t wait_com : 1; 1438 uint64_t pci_wdis : 1; 1439 uint64_t ins0_64b : 1; 1440 uint64_t reserved_43_45 : 3; 1441 uint64_t ins0_enb : 1; 1442 uint64_t reserved_47_49 : 3; 1443 uint64_t out0_enb : 1; 1444 uint64_t reserved_51_53 : 3; 1445 uint64_t dis_pniw : 1; 1446 uint64_t chip_rev : 8; 1447 uint64_t reserved_63_63 : 1; 1448#endif 1449 } cn30xx; 1450 struct cvmx_npi_ctl_status_cn31xx 1451 { 1452#if __BYTE_ORDER == __BIG_ENDIAN 1453 uint64_t reserved_63_63 : 1; 1454 uint64_t chip_rev : 8; /**< The revision of the N3. 1455 0 => pass1.x, 1 => 2.0 */ 1456 uint64_t dis_pniw : 1; /**< When asserted '1' access from the PNI Window 1457 Registers are disabled. */ 1458 uint64_t reserved_52_53 : 2; 1459 uint64_t out1_enb : 1; /**< When asserted '1' the output1 engine is enabled. 1460 After enabling the values of the associated 1461 Address and Size Register should not be changed. */ 1462 uint64_t out0_enb : 1; /**< When asserted '1' the output0 engine is enabled. 1463 After enabling the values of the associated 1464 Address and Size Register should not be changed. */ 1465 uint64_t reserved_48_49 : 2; 1466 uint64_t ins1_enb : 1; /**< When asserted '1' the gather1 engine is enabled. 1467 After enabling the values of the associated 1468 Address and Size Register should not be changed. */ 1469 uint64_t ins0_enb : 1; /**< When asserted '1' the gather0 engine is enabled. 1470 After enabling the values of the associated 1471 Address and Size Register should not be changed. */ 1472 uint64_t reserved_44_45 : 2; 1473 uint64_t ins1_64b : 1; /**< When asserted '1' the instructions read by the 1474 gather1 engine are 64-Byte instructions, when 1475 de-asserted '0' instructions are 32-byte. */ 1476 uint64_t ins0_64b : 1; /**< When asserted '1' the instructions read by the 1477 gather0 engine are 64-Byte instructions, when 1478 de-asserted '0' instructions are 32-byte. */ 1479 uint64_t pci_wdis : 1; /**< When set '1' disables access to registers in 1480 PNI address range 0x1000 - 0x17FF from the PCI. */ 1481 uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit 1482 from the L2C before sending additional access to 1483 the L2C from the PCI. */ 1484 uint64_t reserved_37_39 : 3; 1485 uint64_t max_word : 5; /**< The maximum number of words to merge into a single 1486 write operation from the PPs to the PCI. Legal 1487 values are 1 to 32, where a '0' is treated as 32. */ 1488 uint64_t reserved_10_31 : 22; 1489 uint64_t timer : 10; /**< When the NPI starts a PP to PCI write it will wait 1490 no longer than the value of TIMER in eclks to 1491 merge additional writes from the PPs into 1 1492 large write. The values for this field is 1 to 1493 1024 where a value of '0' is treated as 1024. */ 1494#else 1495 uint64_t timer : 10; 1496 uint64_t reserved_10_31 : 22; 1497 uint64_t max_word : 5; 1498 uint64_t reserved_37_39 : 3; 1499 uint64_t wait_com : 1; 1500 uint64_t pci_wdis : 1; 1501 uint64_t ins0_64b : 1; 1502 uint64_t ins1_64b : 1; 1503 uint64_t reserved_44_45 : 2; 1504 uint64_t ins0_enb : 1; 1505 uint64_t ins1_enb : 1; 1506 uint64_t reserved_48_49 : 2; 1507 uint64_t out0_enb : 1; 1508 uint64_t out1_enb : 1; 1509 uint64_t reserved_52_53 : 2; 1510 uint64_t dis_pniw : 1; 1511 uint64_t chip_rev : 8; 1512 uint64_t reserved_63_63 : 1; 1513#endif 1514 } cn31xx; 1515 struct cvmx_npi_ctl_status_s cn38xx; 1516 struct cvmx_npi_ctl_status_s cn38xxp2; 1517 struct cvmx_npi_ctl_status_cn31xx cn50xx; 1518 struct cvmx_npi_ctl_status_s cn58xx; 1519 struct cvmx_npi_ctl_status_s cn58xxp1; 1520}; 1521typedef union cvmx_npi_ctl_status cvmx_npi_ctl_status_t; 1522 1523/** 1524 * cvmx_npi_dbg_select 1525 * 1526 * NPI_DBG_SELECT = Debug Select Register 1527 * 1528 * Contains the debug select value in last written to the RSLs. 1529 */ 1530union cvmx_npi_dbg_select 1531{ 1532 uint64_t u64; 1533 struct cvmx_npi_dbg_select_s 1534 { 1535#if __BYTE_ORDER == __BIG_ENDIAN 1536 uint64_t reserved_16_63 : 48; 1537 uint64_t dbg_sel : 16; /**< When this register is written its value is sent to 1538 all RSLs. */ 1539#else 1540 uint64_t dbg_sel : 16; 1541 uint64_t reserved_16_63 : 48; 1542#endif 1543 } s; 1544 struct cvmx_npi_dbg_select_s cn30xx; 1545 struct cvmx_npi_dbg_select_s cn31xx; 1546 struct cvmx_npi_dbg_select_s cn38xx; 1547 struct cvmx_npi_dbg_select_s cn38xxp2; 1548 struct cvmx_npi_dbg_select_s cn50xx; 1549 struct cvmx_npi_dbg_select_s cn58xx; 1550 struct cvmx_npi_dbg_select_s cn58xxp1; 1551}; 1552typedef union cvmx_npi_dbg_select cvmx_npi_dbg_select_t; 1553 1554/** 1555 * cvmx_npi_dma_control 1556 * 1557 * NPI_DMA_CONTROL = DMA Control Register 1558 * 1559 * Controls operation of the DMA IN/OUT of the NPI. 1560 */ 1561union cvmx_npi_dma_control 1562{ 1563 uint64_t u64; 1564 struct cvmx_npi_dma_control_s 1565 { 1566#if __BYTE_ORDER == __BIG_ENDIAN 1567 uint64_t reserved_36_63 : 28; 1568 uint64_t b0_lend : 1; /**< When set '1' and the NPI is in the mode to write 1569 0 to L2C memory when a DMA is done, the address 1570 to be written to will be treated as a Little 1571 Endian address. This field is new to PASS-2. */ 1572 uint64_t dwb_denb : 1; /**< When set '1' the NPI will send a value in the DWB 1573 field for a free page operation for the memory 1574 that contained the data in N3. */ 1575 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are freed 1576 this value is used for the DWB field of the 1577 operation. */ 1578 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will 1579 be returned to when used. */ 1580 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters, 1581 if '0' then the number of bytes in the dma transfer 1582 will be added to the count register. */ 1583 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */ 1584 uint64_t o_ns : 1; /**< Nosnoop For DMA. */ 1585 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */ 1586 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used. 1587 '1' use pointer values for address and register 1588 values for RO, ES, and NS, '0' use register 1589 values for address and pointer values for 1590 RO, ES, and NS. */ 1591 uint64_t hp_enb : 1; /**< Enables the High Priority DMA. 1592 While this bit is disabled '0' then the value 1593 in the NPI_HIGHP_IBUFF_SADDR is re-loaded to the 1594 starting address of the High Priority DMA engine. 1595 CSIZE field will be reloaded, for the High Priority 1596 DMA Engine. */ 1597 uint64_t lp_enb : 1; /**< Enables the Low Priority DMA. 1598 While this bit is disabled '0' then the value 1599 in the NPI_LOWP_IBUFF_SADDR is re-loaded to the 1600 starting address of the Low Priority DMA engine. 1601 PASS-2: When this bit is '0' the value in the 1602 CSIZE field will be reloaded, for the Low Priority 1603 DMA Engine. */ 1604 uint64_t csize : 14; /**< The size in words of the DMA Instruction Chunk. 1605 This value should only be written once. After 1606 writing this value a new value will not be 1607 recognized until the end of the DMA I-Chunk is 1608 reached. */ 1609#else 1610 uint64_t csize : 14; 1611 uint64_t lp_enb : 1; 1612 uint64_t hp_enb : 1; 1613 uint64_t o_mode : 1; 1614 uint64_t o_es : 2; 1615 uint64_t o_ns : 1; 1616 uint64_t o_ro : 1; 1617 uint64_t o_add1 : 1; 1618 uint64_t fpa_que : 3; 1619 uint64_t dwb_ichk : 9; 1620 uint64_t dwb_denb : 1; 1621 uint64_t b0_lend : 1; 1622 uint64_t reserved_36_63 : 28; 1623#endif 1624 } s; 1625 struct cvmx_npi_dma_control_s cn30xx; 1626 struct cvmx_npi_dma_control_s cn31xx; 1627 struct cvmx_npi_dma_control_s cn38xx; 1628 struct cvmx_npi_dma_control_s cn38xxp2; 1629 struct cvmx_npi_dma_control_s cn50xx; 1630 struct cvmx_npi_dma_control_s cn58xx; 1631 struct cvmx_npi_dma_control_s cn58xxp1; 1632}; 1633typedef union cvmx_npi_dma_control cvmx_npi_dma_control_t; 1634 1635/** 1636 * cvmx_npi_dma_highp_counts 1637 * 1638 * NPI_DMA_HIGHP_COUNTS = NPI's High Priority DMA Counts 1639 * 1640 * Values for determing the number of instructions for High Priority DMA in the NPI. 1641 */ 1642union cvmx_npi_dma_highp_counts 1643{ 1644 uint64_t u64; 1645 struct cvmx_npi_dma_highp_counts_s 1646 { 1647#if __BYTE_ORDER == __BIG_ENDIAN 1648 uint64_t reserved_39_63 : 25; 1649 uint64_t fcnt : 7; /**< Number of words in the Instruction FIFO. */ 1650 uint64_t dbell : 32; /**< Number of available words of Instructions to read. */ 1651#else 1652 uint64_t dbell : 32; 1653 uint64_t fcnt : 7; 1654 uint64_t reserved_39_63 : 25; 1655#endif 1656 } s; 1657 struct cvmx_npi_dma_highp_counts_s cn30xx; 1658 struct cvmx_npi_dma_highp_counts_s cn31xx; 1659 struct cvmx_npi_dma_highp_counts_s cn38xx; 1660 struct cvmx_npi_dma_highp_counts_s cn38xxp2; 1661 struct cvmx_npi_dma_highp_counts_s cn50xx; 1662 struct cvmx_npi_dma_highp_counts_s cn58xx; 1663 struct cvmx_npi_dma_highp_counts_s cn58xxp1; 1664}; 1665typedef union cvmx_npi_dma_highp_counts cvmx_npi_dma_highp_counts_t; 1666 1667/** 1668 * cvmx_npi_dma_highp_naddr 1669 * 1670 * NPI_DMA_HIGHP_NADDR = NPI's High Priority DMA Next Ichunk Address 1671 * 1672 * Place NPI will read the next Ichunk data from. This is valid when state is 0 1673 */ 1674union cvmx_npi_dma_highp_naddr 1675{ 1676 uint64_t u64; 1677 struct cvmx_npi_dma_highp_naddr_s 1678 { 1679#if __BYTE_ORDER == __BIG_ENDIAN 1680 uint64_t reserved_40_63 : 24; 1681 uint64_t state : 4; /**< The DMA instruction engine state vector. 1682 Typical value is 0 (IDLE). */ 1683 uint64_t addr : 36; /**< The next L2C address to read DMA instructions 1684 from for the High Priority DMA engine. */ 1685#else 1686 uint64_t addr : 36; 1687 uint64_t state : 4; 1688 uint64_t reserved_40_63 : 24; 1689#endif 1690 } s; 1691 struct cvmx_npi_dma_highp_naddr_s cn30xx; 1692 struct cvmx_npi_dma_highp_naddr_s cn31xx; 1693 struct cvmx_npi_dma_highp_naddr_s cn38xx; 1694 struct cvmx_npi_dma_highp_naddr_s cn38xxp2; 1695 struct cvmx_npi_dma_highp_naddr_s cn50xx; 1696 struct cvmx_npi_dma_highp_naddr_s cn58xx; 1697 struct cvmx_npi_dma_highp_naddr_s cn58xxp1; 1698}; 1699typedef union cvmx_npi_dma_highp_naddr cvmx_npi_dma_highp_naddr_t; 1700 1701/** 1702 * cvmx_npi_dma_lowp_counts 1703 * 1704 * NPI_DMA_LOWP_COUNTS = NPI's Low Priority DMA Counts 1705 * 1706 * Values for determing the number of instructions for Low Priority DMA in the NPI. 1707 */ 1708union cvmx_npi_dma_lowp_counts 1709{ 1710 uint64_t u64; 1711 struct cvmx_npi_dma_lowp_counts_s 1712 { 1713#if __BYTE_ORDER == __BIG_ENDIAN 1714 uint64_t reserved_39_63 : 25; 1715 uint64_t fcnt : 7; /**< Number of words in the Instruction FIFO. */ 1716 uint64_t dbell : 32; /**< Number of available words of Instructions to read. */ 1717#else 1718 uint64_t dbell : 32; 1719 uint64_t fcnt : 7; 1720 uint64_t reserved_39_63 : 25; 1721#endif 1722 } s; 1723 struct cvmx_npi_dma_lowp_counts_s cn30xx; 1724 struct cvmx_npi_dma_lowp_counts_s cn31xx; 1725 struct cvmx_npi_dma_lowp_counts_s cn38xx; 1726 struct cvmx_npi_dma_lowp_counts_s cn38xxp2; 1727 struct cvmx_npi_dma_lowp_counts_s cn50xx; 1728 struct cvmx_npi_dma_lowp_counts_s cn58xx; 1729 struct cvmx_npi_dma_lowp_counts_s cn58xxp1; 1730}; 1731typedef union cvmx_npi_dma_lowp_counts cvmx_npi_dma_lowp_counts_t; 1732 1733/** 1734 * cvmx_npi_dma_lowp_naddr 1735 * 1736 * NPI_DMA_LOWP_NADDR = NPI's Low Priority DMA Next Ichunk Address 1737 * 1738 * Place NPI will read the next Ichunk data from. This is valid when state is 0 1739 */ 1740union cvmx_npi_dma_lowp_naddr 1741{ 1742 uint64_t u64; 1743 struct cvmx_npi_dma_lowp_naddr_s 1744 { 1745#if __BYTE_ORDER == __BIG_ENDIAN 1746 uint64_t reserved_40_63 : 24; 1747 uint64_t state : 4; /**< The DMA instruction engine state vector. 1748 Typical value is 0 (IDLE). */ 1749 uint64_t addr : 36; /**< The next L2C address to read DMA instructions 1750 from for the Low Priority DMA engine. */ 1751#else 1752 uint64_t addr : 36; 1753 uint64_t state : 4; 1754 uint64_t reserved_40_63 : 24; 1755#endif 1756 } s; 1757 struct cvmx_npi_dma_lowp_naddr_s cn30xx; 1758 struct cvmx_npi_dma_lowp_naddr_s cn31xx; 1759 struct cvmx_npi_dma_lowp_naddr_s cn38xx; 1760 struct cvmx_npi_dma_lowp_naddr_s cn38xxp2; 1761 struct cvmx_npi_dma_lowp_naddr_s cn50xx; 1762 struct cvmx_npi_dma_lowp_naddr_s cn58xx; 1763 struct cvmx_npi_dma_lowp_naddr_s cn58xxp1; 1764}; 1765typedef union cvmx_npi_dma_lowp_naddr cvmx_npi_dma_lowp_naddr_t; 1766 1767/** 1768 * cvmx_npi_highp_dbell 1769 * 1770 * NPI_HIGHP_DBELL = High Priority Door Bell 1771 * 1772 * The door bell register for the high priority DMA queue. 1773 */ 1774union cvmx_npi_highp_dbell 1775{ 1776 uint64_t u64; 1777 struct cvmx_npi_highp_dbell_s 1778 { 1779#if __BYTE_ORDER == __BIG_ENDIAN 1780 uint64_t reserved_16_63 : 48; 1781 uint64_t dbell : 16; /**< The value written to this register is added to the 1782 number of 8byte words to be read and processes for 1783 the high priority dma queue. */ 1784#else 1785 uint64_t dbell : 16; 1786 uint64_t reserved_16_63 : 48; 1787#endif 1788 } s; 1789 struct cvmx_npi_highp_dbell_s cn30xx; 1790 struct cvmx_npi_highp_dbell_s cn31xx; 1791 struct cvmx_npi_highp_dbell_s cn38xx; 1792 struct cvmx_npi_highp_dbell_s cn38xxp2; 1793 struct cvmx_npi_highp_dbell_s cn50xx; 1794 struct cvmx_npi_highp_dbell_s cn58xx; 1795 struct cvmx_npi_highp_dbell_s cn58xxp1; 1796}; 1797typedef union cvmx_npi_highp_dbell cvmx_npi_highp_dbell_t; 1798 1799/** 1800 * cvmx_npi_highp_ibuff_saddr 1801 * 1802 * NPI_HIGHP_IBUFF_SADDR = DMA High Priority Instruction Buffer Starting Address 1803 * 1804 * The address to start reading Instructions from for HIGHP. 1805 */ 1806union cvmx_npi_highp_ibuff_saddr 1807{ 1808 uint64_t u64; 1809 struct cvmx_npi_highp_ibuff_saddr_s 1810 { 1811#if __BYTE_ORDER == __BIG_ENDIAN 1812 uint64_t reserved_36_63 : 28; 1813 uint64_t saddr : 36; /**< The starting address to read the first instruction. */ 1814#else 1815 uint64_t saddr : 36; 1816 uint64_t reserved_36_63 : 28; 1817#endif 1818 } s; 1819 struct cvmx_npi_highp_ibuff_saddr_s cn30xx; 1820 struct cvmx_npi_highp_ibuff_saddr_s cn31xx; 1821 struct cvmx_npi_highp_ibuff_saddr_s cn38xx; 1822 struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2; 1823 struct cvmx_npi_highp_ibuff_saddr_s cn50xx; 1824 struct cvmx_npi_highp_ibuff_saddr_s cn58xx; 1825 struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1; 1826}; 1827typedef union cvmx_npi_highp_ibuff_saddr cvmx_npi_highp_ibuff_saddr_t; 1828 1829/** 1830 * cvmx_npi_input_control 1831 * 1832 * NPI_INPUT_CONTROL = NPI's Input Control Register 1833 * 1834 * Control for reads for gather list and instructions. 1835 */ 1836union cvmx_npi_input_control 1837{ 1838 uint64_t u64; 1839 struct cvmx_npi_input_control_s 1840 { 1841#if __BYTE_ORDER == __BIG_ENDIAN 1842 uint64_t reserved_23_63 : 41; 1843 uint64_t pkt_rr : 1; /**< When set '1' the input packet selection will be 1844 made with a Round Robin arbitration. When '0' 1845 the input packet port is fixed in priority, 1846 where the lower port number has higher priority. 1847 PASS3 Field */ 1848 uint64_t pbp_dhi : 13; /**< Field when in [PBP] is set to be used in 1849 calculating a DPTR. */ 1850 uint64_t d_nsr : 1; /**< Enables '1' NoSnoop for reading of 1851 gather data. */ 1852 uint64_t d_esr : 2; /**< The Endian-Swap-Mode for reading of 1853 gather data. */ 1854 uint64_t d_ror : 1; /**< Enables '1' Relaxed Ordering for reading of 1855 gather data. */ 1856 uint64_t use_csr : 1; /**< When set '1' the csr value will be used for 1857 ROR, ESR, and NSR. When clear '0' the value in 1858 DPTR will be used. In turn the bits not used for 1859 ROR, ESR, and NSR, will be used for bits [63:60] 1860 of the address used to fetch packet data. */ 1861 uint64_t nsr : 1; /**< Enables '1' NoSnoop for reading of 1862 gather list and gather instruction. */ 1863 uint64_t esr : 2; /**< The Endian-Swap-Mode for reading of 1864 gather list and gather instruction. */ 1865 uint64_t ror : 1; /**< Enables '1' Relaxed Ordering for reading of 1866 gather list and gather instruction. */ 1867#else 1868 uint64_t ror : 1; 1869 uint64_t esr : 2; 1870 uint64_t nsr : 1; 1871 uint64_t use_csr : 1; 1872 uint64_t d_ror : 1; 1873 uint64_t d_esr : 2; 1874 uint64_t d_nsr : 1; 1875 uint64_t pbp_dhi : 13; 1876 uint64_t pkt_rr : 1; 1877 uint64_t reserved_23_63 : 41; 1878#endif 1879 } s; 1880 struct cvmx_npi_input_control_cn30xx 1881 { 1882#if __BYTE_ORDER == __BIG_ENDIAN 1883 uint64_t reserved_22_63 : 42; 1884 uint64_t pbp_dhi : 13; /**< Field when in [PBP] is set to be used in 1885 calculating a DPTR. */ 1886 uint64_t d_nsr : 1; /**< Enables '1' NoSnoop for reading of 1887 gather data. */ 1888 uint64_t d_esr : 2; /**< The Endian-Swap-Mode for reading of 1889 gather data. */ 1890 uint64_t d_ror : 1; /**< Enables '1' Relaxed Ordering for reading of 1891 gather data. */ 1892 uint64_t use_csr : 1; /**< When set '1' the csr value will be used for 1893 ROR, ESR, and NSR. When clear '0' the value in 1894 DPTR will be used. In turn the bits not used for 1895 ROR, ESR, and NSR, will be used for bits [63:60] 1896 of the address used to fetch packet data. */ 1897 uint64_t nsr : 1; /**< Enables '1' NoSnoop for reading of 1898 gather list and gather instruction. */ 1899 uint64_t esr : 2; /**< The Endian-Swap-Mode for reading of 1900 gather list and gather instruction. */ 1901 uint64_t ror : 1; /**< Enables '1' Relaxed Ordering for reading of 1902 gather list and gather instruction. */ 1903#else 1904 uint64_t ror : 1; 1905 uint64_t esr : 2; 1906 uint64_t nsr : 1; 1907 uint64_t use_csr : 1; 1908 uint64_t d_ror : 1; 1909 uint64_t d_esr : 2; 1910 uint64_t d_nsr : 1; 1911 uint64_t pbp_dhi : 13; 1912 uint64_t reserved_22_63 : 42; 1913#endif 1914 } cn30xx; 1915 struct cvmx_npi_input_control_cn30xx cn31xx; 1916 struct cvmx_npi_input_control_s cn38xx; 1917 struct cvmx_npi_input_control_cn30xx cn38xxp2; 1918 struct cvmx_npi_input_control_s cn50xx; 1919 struct cvmx_npi_input_control_s cn58xx; 1920 struct cvmx_npi_input_control_s cn58xxp1; 1921}; 1922typedef union cvmx_npi_input_control cvmx_npi_input_control_t; 1923 1924/** 1925 * cvmx_npi_int_enb 1926 * 1927 * NPI_INTERRUPT_ENB = NPI's Interrupt Enable Register 1928 * 1929 * Used to enable the various interrupting conditions of NPI 1930 */ 1931union cvmx_npi_int_enb 1932{ 1933 uint64_t u64; 1934 struct cvmx_npi_int_enb_s 1935 { 1936#if __BYTE_ORDER == __BIG_ENDIAN 1937 uint64_t reserved_62_63 : 2; 1938 uint64_t q1_a_f : 1; /**< Enables NPI_INT_SUM[Q1_A_F] to generate an 1939 interrupt. */ 1940 uint64_t q1_s_e : 1; /**< Enables NPI_INT_SUM[Q1_S_E] to generate an 1941 interrupt. */ 1942 uint64_t pdf_p_f : 1; /**< Enables NPI_INT_SUM[PDF_P_F] to generate an 1943 interrupt. */ 1944 uint64_t pdf_p_e : 1; /**< Enables NPI_INT_SUM[PDF_P_E] to generate an 1945 interrupt. */ 1946 uint64_t pcf_p_f : 1; /**< Enables NPI_INT_SUM[PCF_P_F] to generate an 1947 interrupt. */ 1948 uint64_t pcf_p_e : 1; /**< Enables NPI_INT_SUM[PCF_P_E] to generate an 1949 interrupt. */ 1950 uint64_t rdx_s_e : 1; /**< Enables NPI_INT_SUM[RDX_S_E] to generate an 1951 interrupt. */ 1952 uint64_t rwx_s_e : 1; /**< Enables NPI_INT_SUM[RWX_S_E] to generate an 1953 interrupt. */ 1954 uint64_t pnc_a_f : 1; /**< Enables NPI_INT_SUM[PNC_A_F] to generate an 1955 interrupt. */ 1956 uint64_t pnc_s_e : 1; /**< Enables NPI_INT_SUM[PNC_S_E] to generate an 1957 interrupt. */ 1958 uint64_t com_a_f : 1; /**< Enables NPI_INT_SUM[COM_A_F] to generate an 1959 interrupt. */ 1960 uint64_t com_s_e : 1; /**< Enables NPI_INT_SUM[COM_S_E] to generate an 1961 interrupt. */ 1962 uint64_t q3_a_f : 1; /**< Enables NPI_INT_SUM[Q3_A_F] to generate an 1963 interrupt. */ 1964 uint64_t q3_s_e : 1; /**< Enables NPI_INT_SUM[Q3_S_E] to generate an 1965 interrupt. */ 1966 uint64_t q2_a_f : 1; /**< Enables NPI_INT_SUM[Q2_A_F] to generate an 1967 interrupt. */ 1968 uint64_t q2_s_e : 1; /**< Enables NPI_INT_SUM[Q2_S_E] to generate an 1969 interrupt. */ 1970 uint64_t pcr_a_f : 1; /**< Enables NPI_INT_SUM[PCR_A_F] to generate an 1971 interrupt. */ 1972 uint64_t pcr_s_e : 1; /**< Enables NPI_INT_SUM[PCR_S_E] to generate an 1973 interrupt. */ 1974 uint64_t fcr_a_f : 1; /**< Enables NPI_INT_SUM[FCR_A_F] to generate an 1975 interrupt. */ 1976 uint64_t fcr_s_e : 1; /**< Enables NPI_INT_SUM[FCR_S_E] to generate an 1977 interrupt. */ 1978 uint64_t iobdma : 1; /**< Enables NPI_INT_SUM[IOBDMA] to generate an 1979 interrupt. */ 1980 uint64_t p_dperr : 1; /**< Enables NPI_INT_SUM[P_DPERR] to generate an 1981 interrupt. */ 1982 uint64_t win_rto : 1; /**< Enables NPI_INT_SUM[WIN_RTO] to generate an 1983 interrupt. */ 1984 uint64_t i3_pperr : 1; /**< Enables NPI_INT_SUM[I3_PPERR] to generate an 1985 interrupt. */ 1986 uint64_t i2_pperr : 1; /**< Enables NPI_INT_SUM[I2_PPERR] to generate an 1987 interrupt. */ 1988 uint64_t i1_pperr : 1; /**< Enables NPI_INT_SUM[I1_PPERR] to generate an 1989 interrupt. */ 1990 uint64_t i0_pperr : 1; /**< Enables NPI_INT_SUM[I0_PPERR] to generate an 1991 interrupt. */ 1992 uint64_t p3_ptout : 1; /**< Enables NPI_INT_SUM[P3_PTOUT] to generate an 1993 interrupt. */ 1994 uint64_t p2_ptout : 1; /**< Enables NPI_INT_SUM[P2_PTOUT] to generate an 1995 interrupt. */ 1996 uint64_t p1_ptout : 1; /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an 1997 interrupt. */ 1998 uint64_t p0_ptout : 1; /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an 1999 interrupt. */ 2000 uint64_t p3_pperr : 1; /**< Enables NPI_INT_SUM[P3_PPERR] to generate an 2001 interrupt. */ 2002 uint64_t p2_pperr : 1; /**< Enables NPI_INT_SUM[P2_PPERR] to generate an 2003 interrupt. */ 2004 uint64_t p1_pperr : 1; /**< Enables NPI_INT_SUM[P1_PPERR] to generate an 2005 interrupt. */ 2006 uint64_t p0_pperr : 1; /**< Enables NPI_INT_SUM[P0_PPERR] to generate an 2007 interrupt. */ 2008 uint64_t g3_rtout : 1; /**< Enables NPI_INT_SUM[G3_RTOUT] to generate an 2009 interrupt. */ 2010 uint64_t g2_rtout : 1; /**< Enables NPI_INT_SUM[G2_RTOUT] to generate an 2011 interrupt. */ 2012 uint64_t g1_rtout : 1; /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an 2013 interrupt. */ 2014 uint64_t g0_rtout : 1; /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an 2015 interrupt. */ 2016 uint64_t p3_perr : 1; /**< Enables NPI_INT_SUM[P3_PERR] to generate an 2017 interrupt. */ 2018 uint64_t p2_perr : 1; /**< Enables NPI_INT_SUM[P2_PERR] to generate an 2019 interrupt. */ 2020 uint64_t p1_perr : 1; /**< Enables NPI_INT_SUM[P1_PERR] to generate an 2021 interrupt. */ 2022 uint64_t p0_perr : 1; /**< Enables NPI_INT_SUM[P0_PERR] to generate an 2023 interrupt. */ 2024 uint64_t p3_rtout : 1; /**< Enables NPI_INT_SUM[P3_RTOUT] to generate an 2025 interrupt. */ 2026 uint64_t p2_rtout : 1; /**< Enables NPI_INT_SUM[P2_RTOUT] to generate an 2027 interrupt. */ 2028 uint64_t p1_rtout : 1; /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an 2029 interrupt. */ 2030 uint64_t p0_rtout : 1; /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an 2031 interrupt. */ 2032 uint64_t i3_overf : 1; /**< Enables NPI_INT_SUM[I3_OVERF] to generate an 2033 interrupt. */ 2034 uint64_t i2_overf : 1; /**< Enables NPI_INT_SUM[I2_OVERF] to generate an 2035 interrupt. */ 2036 uint64_t i1_overf : 1; /**< Enables NPI_INT_SUM[I1_OVERF] to generate an 2037 interrupt. */ 2038 uint64_t i0_overf : 1; /**< Enables NPI_INT_SUM[I0_OVERF] to generate an 2039 interrupt. */ 2040 uint64_t i3_rtout : 1; /**< Enables NPI_INT_SUM[I3_RTOUT] to generate an 2041 interrupt. */ 2042 uint64_t i2_rtout : 1; /**< Enables NPI_INT_SUM[I2_RTOUT] to generate an 2043 interrupt. */ 2044 uint64_t i1_rtout : 1; /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an 2045 interrupt. */ 2046 uint64_t i0_rtout : 1; /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an 2047 interrupt. */ 2048 uint64_t po3_2sml : 1; /**< Enables NPI_INT_SUM[PO3_2SML] to generate an 2049 interrupt. */ 2050 uint64_t po2_2sml : 1; /**< Enables NPI_INT_SUM[PO2_2SML] to generate an 2051 interrupt. */ 2052 uint64_t po1_2sml : 1; /**< Enables NPI_INT_SUM[PO1_2SML] to generate an 2053 interrupt. */ 2054 uint64_t po0_2sml : 1; /**< Enables NPI_INT_SUM[PO0_2SML] to generate an 2055 interrupt. */ 2056 uint64_t pci_rsl : 1; /**< Enables NPI_INT_SUM[PCI_RSL] to generate an 2057 interrupt. */ 2058 uint64_t rml_wto : 1; /**< Enables NPI_INT_SUM[RML_WTO] to generate an 2059 interrupt. */ 2060 uint64_t rml_rto : 1; /**< Enables NPI_INT_SUM[RML_RTO] to generate an 2061 interrupt. */ 2062#else 2063 uint64_t rml_rto : 1; 2064 uint64_t rml_wto : 1; 2065 uint64_t pci_rsl : 1; 2066 uint64_t po0_2sml : 1; 2067 uint64_t po1_2sml : 1; 2068 uint64_t po2_2sml : 1; 2069 uint64_t po3_2sml : 1; 2070 uint64_t i0_rtout : 1; 2071 uint64_t i1_rtout : 1; 2072 uint64_t i2_rtout : 1; 2073 uint64_t i3_rtout : 1; 2074 uint64_t i0_overf : 1; 2075 uint64_t i1_overf : 1; 2076 uint64_t i2_overf : 1; 2077 uint64_t i3_overf : 1; 2078 uint64_t p0_rtout : 1; 2079 uint64_t p1_rtout : 1; 2080 uint64_t p2_rtout : 1; 2081 uint64_t p3_rtout : 1; 2082 uint64_t p0_perr : 1; 2083 uint64_t p1_perr : 1; 2084 uint64_t p2_perr : 1; 2085 uint64_t p3_perr : 1; 2086 uint64_t g0_rtout : 1; 2087 uint64_t g1_rtout : 1; 2088 uint64_t g2_rtout : 1; 2089 uint64_t g3_rtout : 1; 2090 uint64_t p0_pperr : 1; 2091 uint64_t p1_pperr : 1; 2092 uint64_t p2_pperr : 1; 2093 uint64_t p3_pperr : 1; 2094 uint64_t p0_ptout : 1; 2095 uint64_t p1_ptout : 1; 2096 uint64_t p2_ptout : 1; 2097 uint64_t p3_ptout : 1; 2098 uint64_t i0_pperr : 1; 2099 uint64_t i1_pperr : 1; 2100 uint64_t i2_pperr : 1; 2101 uint64_t i3_pperr : 1; 2102 uint64_t win_rto : 1; 2103 uint64_t p_dperr : 1; 2104 uint64_t iobdma : 1; 2105 uint64_t fcr_s_e : 1; 2106 uint64_t fcr_a_f : 1; 2107 uint64_t pcr_s_e : 1; 2108 uint64_t pcr_a_f : 1; 2109 uint64_t q2_s_e : 1; 2110 uint64_t q2_a_f : 1; 2111 uint64_t q3_s_e : 1; 2112 uint64_t q3_a_f : 1; 2113 uint64_t com_s_e : 1; 2114 uint64_t com_a_f : 1; 2115 uint64_t pnc_s_e : 1; 2116 uint64_t pnc_a_f : 1; 2117 uint64_t rwx_s_e : 1; 2118 uint64_t rdx_s_e : 1; 2119 uint64_t pcf_p_e : 1; 2120 uint64_t pcf_p_f : 1; 2121 uint64_t pdf_p_e : 1; 2122 uint64_t pdf_p_f : 1; 2123 uint64_t q1_s_e : 1; 2124 uint64_t q1_a_f : 1; 2125 uint64_t reserved_62_63 : 2; 2126#endif 2127 } s; 2128 struct cvmx_npi_int_enb_cn30xx 2129 { 2130#if __BYTE_ORDER == __BIG_ENDIAN 2131 uint64_t reserved_62_63 : 2; 2132 uint64_t q1_a_f : 1; /**< Enables NPI_INT_SUM[Q1_A_F] to generate an 2133 interrupt. */ 2134 uint64_t q1_s_e : 1; /**< Enables NPI_INT_SUM[Q1_S_E] to generate an 2135 interrupt. */ 2136 uint64_t pdf_p_f : 1; /**< Enables NPI_INT_SUM[PDF_P_F] to generate an 2137 interrupt. */ 2138 uint64_t pdf_p_e : 1; /**< Enables NPI_INT_SUM[PDF_P_E] to generate an 2139 interrupt. */ 2140 uint64_t pcf_p_f : 1; /**< Enables NPI_INT_SUM[PCF_P_F] to generate an 2141 interrupt. */ 2142 uint64_t pcf_p_e : 1; /**< Enables NPI_INT_SUM[PCF_P_E] to generate an 2143 interrupt. */ 2144 uint64_t rdx_s_e : 1; /**< Enables NPI_INT_SUM[RDX_S_E] to generate an 2145 interrupt. */ 2146 uint64_t rwx_s_e : 1; /**< Enables NPI_INT_SUM[RWX_S_E] to generate an 2147 interrupt. */ 2148 uint64_t pnc_a_f : 1; /**< Enables NPI_INT_SUM[PNC_A_F] to generate an 2149 interrupt. */ 2150 uint64_t pnc_s_e : 1; /**< Enables NPI_INT_SUM[PNC_S_E] to generate an 2151 interrupt. */ 2152 uint64_t com_a_f : 1; /**< Enables NPI_INT_SUM[COM_A_F] to generate an 2153 interrupt. */ 2154 uint64_t com_s_e : 1; /**< Enables NPI_INT_SUM[COM_S_E] to generate an 2155 interrupt. */ 2156 uint64_t q3_a_f : 1; /**< Enables NPI_INT_SUM[Q3_A_F] to generate an 2157 interrupt. */ 2158 uint64_t q3_s_e : 1; /**< Enables NPI_INT_SUM[Q3_S_E] to generate an 2159 interrupt. */ 2160 uint64_t q2_a_f : 1; /**< Enables NPI_INT_SUM[Q2_A_F] to generate an 2161 interrupt. */ 2162 uint64_t q2_s_e : 1; /**< Enables NPI_INT_SUM[Q2_S_E] to generate an 2163 interrupt. */ 2164 uint64_t pcr_a_f : 1; /**< Enables NPI_INT_SUM[PCR_A_F] to generate an 2165 interrupt. */ 2166 uint64_t pcr_s_e : 1; /**< Enables NPI_INT_SUM[PCR_S_E] to generate an 2167 interrupt. */ 2168 uint64_t fcr_a_f : 1; /**< Enables NPI_INT_SUM[FCR_A_F] to generate an 2169 interrupt. */ 2170 uint64_t fcr_s_e : 1; /**< Enables NPI_INT_SUM[FCR_S_E] to generate an 2171 interrupt. */ 2172 uint64_t iobdma : 1; /**< Enables NPI_INT_SUM[IOBDMA] to generate an 2173 interrupt. */ 2174 uint64_t p_dperr : 1; /**< Enables NPI_INT_SUM[P_DPERR] to generate an 2175 interrupt. */ 2176 uint64_t win_rto : 1; /**< Enables NPI_INT_SUM[WIN_RTO] to generate an 2177 interrupt. */ 2178 uint64_t reserved_36_38 : 3; 2179 uint64_t i0_pperr : 1; /**< Enables NPI_INT_SUM[I0_PPERR] to generate an 2180 interrupt. */ 2181 uint64_t reserved_32_34 : 3; 2182 uint64_t p0_ptout : 1; /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an 2183 interrupt. */ 2184 uint64_t reserved_28_30 : 3; 2185 uint64_t p0_pperr : 1; /**< Enables NPI_INT_SUM[P0_PPERR] to generate an 2186 interrupt. */ 2187 uint64_t reserved_24_26 : 3; 2188 uint64_t g0_rtout : 1; /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an 2189 interrupt. */ 2190 uint64_t reserved_20_22 : 3; 2191 uint64_t p0_perr : 1; /**< Enables NPI_INT_SUM[P0_PERR] to generate an 2192 interrupt. */ 2193 uint64_t reserved_16_18 : 3; 2194 uint64_t p0_rtout : 1; /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an 2195 interrupt. */ 2196 uint64_t reserved_12_14 : 3; 2197 uint64_t i0_overf : 1; /**< Enables NPI_INT_SUM[I0_OVERF] to generate an 2198 interrupt. */ 2199 uint64_t reserved_8_10 : 3; 2200 uint64_t i0_rtout : 1; /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an 2201 interrupt. */ 2202 uint64_t reserved_4_6 : 3; 2203 uint64_t po0_2sml : 1; /**< Enables NPI_INT_SUM[PO0_2SML] to generate an 2204 interrupt. */ 2205 uint64_t pci_rsl : 1; /**< Enables NPI_INT_SUM[PCI_RSL] to generate an 2206 interrupt. */ 2207 uint64_t rml_wto : 1; /**< Enables NPI_INT_SUM[RML_WTO] to generate an 2208 interrupt. */ 2209 uint64_t rml_rto : 1; /**< Enables NPI_INT_SUM[RML_RTO] to generate an 2210 interrupt. */ 2211#else 2212 uint64_t rml_rto : 1; 2213 uint64_t rml_wto : 1; 2214 uint64_t pci_rsl : 1; 2215 uint64_t po0_2sml : 1; 2216 uint64_t reserved_4_6 : 3; 2217 uint64_t i0_rtout : 1; 2218 uint64_t reserved_8_10 : 3; 2219 uint64_t i0_overf : 1; 2220 uint64_t reserved_12_14 : 3; 2221 uint64_t p0_rtout : 1; 2222 uint64_t reserved_16_18 : 3; 2223 uint64_t p0_perr : 1; 2224 uint64_t reserved_20_22 : 3; 2225 uint64_t g0_rtout : 1; 2226 uint64_t reserved_24_26 : 3; 2227 uint64_t p0_pperr : 1; 2228 uint64_t reserved_28_30 : 3; 2229 uint64_t p0_ptout : 1; 2230 uint64_t reserved_32_34 : 3; 2231 uint64_t i0_pperr : 1; 2232 uint64_t reserved_36_38 : 3; 2233 uint64_t win_rto : 1; 2234 uint64_t p_dperr : 1; 2235 uint64_t iobdma : 1; 2236 uint64_t fcr_s_e : 1; 2237 uint64_t fcr_a_f : 1; 2238 uint64_t pcr_s_e : 1; 2239 uint64_t pcr_a_f : 1; 2240 uint64_t q2_s_e : 1; 2241 uint64_t q2_a_f : 1; 2242 uint64_t q3_s_e : 1; 2243 uint64_t q3_a_f : 1; 2244 uint64_t com_s_e : 1; 2245 uint64_t com_a_f : 1; 2246 uint64_t pnc_s_e : 1; 2247 uint64_t pnc_a_f : 1; 2248 uint64_t rwx_s_e : 1; 2249 uint64_t rdx_s_e : 1; 2250 uint64_t pcf_p_e : 1; 2251 uint64_t pcf_p_f : 1; 2252 uint64_t pdf_p_e : 1; 2253 uint64_t pdf_p_f : 1; 2254 uint64_t q1_s_e : 1; 2255 uint64_t q1_a_f : 1; 2256 uint64_t reserved_62_63 : 2; 2257#endif 2258 } cn30xx; 2259 struct cvmx_npi_int_enb_cn31xx 2260 { 2261#if __BYTE_ORDER == __BIG_ENDIAN 2262 uint64_t reserved_62_63 : 2; 2263 uint64_t q1_a_f : 1; /**< Enables NPI_INT_SUM[Q1_A_F] to generate an 2264 interrupt. */ 2265 uint64_t q1_s_e : 1; /**< Enables NPI_INT_SUM[Q1_S_E] to generate an 2266 interrupt. */ 2267 uint64_t pdf_p_f : 1; /**< Enables NPI_INT_SUM[PDF_P_F] to generate an 2268 interrupt. */ 2269 uint64_t pdf_p_e : 1; /**< Enables NPI_INT_SUM[PDF_P_E] to generate an 2270 interrupt. */ 2271 uint64_t pcf_p_f : 1; /**< Enables NPI_INT_SUM[PCF_P_F] to generate an 2272 interrupt. */ 2273 uint64_t pcf_p_e : 1; /**< Enables NPI_INT_SUM[PCF_P_E] to generate an 2274 interrupt. */ 2275 uint64_t rdx_s_e : 1; /**< Enables NPI_INT_SUM[RDX_S_E] to generate an 2276 interrupt. */ 2277 uint64_t rwx_s_e : 1; /**< Enables NPI_INT_SUM[RWX_S_E] to generate an 2278 interrupt. */ 2279 uint64_t pnc_a_f : 1; /**< Enables NPI_INT_SUM[PNC_A_F] to generate an 2280 interrupt. */ 2281 uint64_t pnc_s_e : 1; /**< Enables NPI_INT_SUM[PNC_S_E] to generate an 2282 interrupt. */ 2283 uint64_t com_a_f : 1; /**< Enables NPI_INT_SUM[COM_A_F] to generate an 2284 interrupt. */ 2285 uint64_t com_s_e : 1; /**< Enables NPI_INT_SUM[COM_S_E] to generate an 2286 interrupt. */ 2287 uint64_t q3_a_f : 1; /**< Enables NPI_INT_SUM[Q3_A_F] to generate an 2288 interrupt. */ 2289 uint64_t q3_s_e : 1; /**< Enables NPI_INT_SUM[Q3_S_E] to generate an 2290 interrupt. */ 2291 uint64_t q2_a_f : 1; /**< Enables NPI_INT_SUM[Q2_A_F] to generate an 2292 interrupt. */ 2293 uint64_t q2_s_e : 1; /**< Enables NPI_INT_SUM[Q2_S_E] to generate an 2294 interrupt. */ 2295 uint64_t pcr_a_f : 1; /**< Enables NPI_INT_SUM[PCR_A_F] to generate an 2296 interrupt. */ 2297 uint64_t pcr_s_e : 1; /**< Enables NPI_INT_SUM[PCR_S_E] to generate an 2298 interrupt. */ 2299 uint64_t fcr_a_f : 1; /**< Enables NPI_INT_SUM[FCR_A_F] to generate an 2300 interrupt. */ 2301 uint64_t fcr_s_e : 1; /**< Enables NPI_INT_SUM[FCR_S_E] to generate an 2302 interrupt. */ 2303 uint64_t iobdma : 1; /**< Enables NPI_INT_SUM[IOBDMA] to generate an 2304 interrupt. */ 2305 uint64_t p_dperr : 1; /**< Enables NPI_INT_SUM[P_DPERR] to generate an 2306 interrupt. */ 2307 uint64_t win_rto : 1; /**< Enables NPI_INT_SUM[WIN_RTO] to generate an 2308 interrupt. */ 2309 uint64_t reserved_37_38 : 2; 2310 uint64_t i1_pperr : 1; /**< Enables NPI_INT_SUM[I1_PPERR] to generate an 2311 interrupt. */ 2312 uint64_t i0_pperr : 1; /**< Enables NPI_INT_SUM[I0_PPERR] to generate an 2313 interrupt. */ 2314 uint64_t reserved_33_34 : 2; 2315 uint64_t p1_ptout : 1; /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an 2316 interrupt. */ 2317 uint64_t p0_ptout : 1; /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an 2318 interrupt. */ 2319 uint64_t reserved_29_30 : 2; 2320 uint64_t p1_pperr : 1; /**< Enables NPI_INT_SUM[P1_PPERR] to generate an 2321 interrupt. */ 2322 uint64_t p0_pperr : 1; /**< Enables NPI_INT_SUM[P0_PPERR] to generate an 2323 interrupt. */ 2324 uint64_t reserved_25_26 : 2; 2325 uint64_t g1_rtout : 1; /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an 2326 interrupt. */ 2327 uint64_t g0_rtout : 1; /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an 2328 interrupt. */ 2329 uint64_t reserved_21_22 : 2; 2330 uint64_t p1_perr : 1; /**< Enables NPI_INT_SUM[P1_PERR] to generate an 2331 interrupt. */ 2332 uint64_t p0_perr : 1; /**< Enables NPI_INT_SUM[P0_PERR] to generate an 2333 interrupt. */ 2334 uint64_t reserved_17_18 : 2; 2335 uint64_t p1_rtout : 1; /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an 2336 interrupt. */ 2337 uint64_t p0_rtout : 1; /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an 2338 interrupt. */ 2339 uint64_t reserved_13_14 : 2; 2340 uint64_t i1_overf : 1; /**< Enables NPI_INT_SUM[I1_OVERF] to generate an 2341 interrupt. */ 2342 uint64_t i0_overf : 1; /**< Enables NPI_INT_SUM[I0_OVERF] to generate an 2343 interrupt. */ 2344 uint64_t reserved_9_10 : 2; 2345 uint64_t i1_rtout : 1; /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an 2346 interrupt. */ 2347 uint64_t i0_rtout : 1; /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an 2348 interrupt. */ 2349 uint64_t reserved_5_6 : 2; 2350 uint64_t po1_2sml : 1; /**< Enables NPI_INT_SUM[PO1_2SML] to generate an 2351 interrupt. */ 2352 uint64_t po0_2sml : 1; /**< Enables NPI_INT_SUM[PO0_2SML] to generate an 2353 interrupt. */ 2354 uint64_t pci_rsl : 1; /**< Enables NPI_INT_SUM[PCI_RSL] to generate an 2355 interrupt. */ 2356 uint64_t rml_wto : 1; /**< Enables NPI_INT_SUM[RML_WTO] to generate an 2357 interrupt. */ 2358 uint64_t rml_rto : 1; /**< Enables NPI_INT_SUM[RML_RTO] to generate an 2359 interrupt. */ 2360#else 2361 uint64_t rml_rto : 1; 2362 uint64_t rml_wto : 1; 2363 uint64_t pci_rsl : 1; 2364 uint64_t po0_2sml : 1; 2365 uint64_t po1_2sml : 1; 2366 uint64_t reserved_5_6 : 2; 2367 uint64_t i0_rtout : 1; 2368 uint64_t i1_rtout : 1; 2369 uint64_t reserved_9_10 : 2; 2370 uint64_t i0_overf : 1; 2371 uint64_t i1_overf : 1; 2372 uint64_t reserved_13_14 : 2; 2373 uint64_t p0_rtout : 1; 2374 uint64_t p1_rtout : 1; 2375 uint64_t reserved_17_18 : 2; 2376 uint64_t p0_perr : 1; 2377 uint64_t p1_perr : 1; 2378 uint64_t reserved_21_22 : 2; 2379 uint64_t g0_rtout : 1; 2380 uint64_t g1_rtout : 1; 2381 uint64_t reserved_25_26 : 2; 2382 uint64_t p0_pperr : 1; 2383 uint64_t p1_pperr : 1; 2384 uint64_t reserved_29_30 : 2; 2385 uint64_t p0_ptout : 1; 2386 uint64_t p1_ptout : 1; 2387 uint64_t reserved_33_34 : 2; 2388 uint64_t i0_pperr : 1; 2389 uint64_t i1_pperr : 1; 2390 uint64_t reserved_37_38 : 2; 2391 uint64_t win_rto : 1; 2392 uint64_t p_dperr : 1; 2393 uint64_t iobdma : 1; 2394 uint64_t fcr_s_e : 1; 2395 uint64_t fcr_a_f : 1; 2396 uint64_t pcr_s_e : 1; 2397 uint64_t pcr_a_f : 1; 2398 uint64_t q2_s_e : 1; 2399 uint64_t q2_a_f : 1; 2400 uint64_t q3_s_e : 1; 2401 uint64_t q3_a_f : 1; 2402 uint64_t com_s_e : 1; 2403 uint64_t com_a_f : 1; 2404 uint64_t pnc_s_e : 1; 2405 uint64_t pnc_a_f : 1; 2406 uint64_t rwx_s_e : 1; 2407 uint64_t rdx_s_e : 1; 2408 uint64_t pcf_p_e : 1; 2409 uint64_t pcf_p_f : 1; 2410 uint64_t pdf_p_e : 1; 2411 uint64_t pdf_p_f : 1; 2412 uint64_t q1_s_e : 1; 2413 uint64_t q1_a_f : 1; 2414 uint64_t reserved_62_63 : 2; 2415#endif 2416 } cn31xx; 2417 struct cvmx_npi_int_enb_s cn38xx; 2418 struct cvmx_npi_int_enb_cn38xxp2 2419 { 2420#if __BYTE_ORDER == __BIG_ENDIAN 2421 uint64_t reserved_42_63 : 22; 2422 uint64_t iobdma : 1; /**< Enables NPI_INT_SUM[IOBDMA] to generate an 2423 interrupt. */ 2424 uint64_t p_dperr : 1; /**< Enables NPI_INT_SUM[P_DPERR] to generate an 2425 interrupt. */ 2426 uint64_t win_rto : 1; /**< Enables NPI_INT_SUM[WIN_RTO] to generate an 2427 interrupt. */ 2428 uint64_t i3_pperr : 1; /**< Enables NPI_INT_SUM[I3_PPERR] to generate an 2429 interrupt. */ 2430 uint64_t i2_pperr : 1; /**< Enables NPI_INT_SUM[I2_PPERR] to generate an 2431 interrupt. */ 2432 uint64_t i1_pperr : 1; /**< Enables NPI_INT_SUM[I1_PPERR] to generate an 2433 interrupt. */ 2434 uint64_t i0_pperr : 1; /**< Enables NPI_INT_SUM[I0_PPERR] to generate an 2435 interrupt. */ 2436 uint64_t p3_ptout : 1; /**< Enables NPI_INT_SUM[P3_PTOUT] to generate an 2437 interrupt. */ 2438 uint64_t p2_ptout : 1; /**< Enables NPI_INT_SUM[P2_PTOUT] to generate an 2439 interrupt. */ 2440 uint64_t p1_ptout : 1; /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an 2441 interrupt. */ 2442 uint64_t p0_ptout : 1; /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an 2443 interrupt. */ 2444 uint64_t p3_pperr : 1; /**< Enables NPI_INT_SUM[P3_PPERR] to generate an 2445 interrupt. */ 2446 uint64_t p2_pperr : 1; /**< Enables NPI_INT_SUM[P2_PPERR] to generate an 2447 interrupt. */ 2448 uint64_t p1_pperr : 1; /**< Enables NPI_INT_SUM[P1_PPERR] to generate an 2449 interrupt. */ 2450 uint64_t p0_pperr : 1; /**< Enables NPI_INT_SUM[P0_PPERR] to generate an 2451 interrupt. */ 2452 uint64_t g3_rtout : 1; /**< Enables NPI_INT_SUM[G3_RTOUT] to generate an 2453 interrupt. */ 2454 uint64_t g2_rtout : 1; /**< Enables NPI_INT_SUM[G2_RTOUT] to generate an 2455 interrupt. */ 2456 uint64_t g1_rtout : 1; /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an 2457 interrupt. */ 2458 uint64_t g0_rtout : 1; /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an 2459 interrupt. */ 2460 uint64_t p3_perr : 1; /**< Enables NPI_INT_SUM[P3_PERR] to generate an 2461 interrupt. */ 2462 uint64_t p2_perr : 1; /**< Enables NPI_INT_SUM[P2_PERR] to generate an 2463 interrupt. */ 2464 uint64_t p1_perr : 1; /**< Enables NPI_INT_SUM[P1_PERR] to generate an 2465 interrupt. */ 2466 uint64_t p0_perr : 1; /**< Enables NPI_INT_SUM[P0_PERR] to generate an 2467 interrupt. */ 2468 uint64_t p3_rtout : 1; /**< Enables NPI_INT_SUM[P3_RTOUT] to generate an 2469 interrupt. */ 2470 uint64_t p2_rtout : 1; /**< Enables NPI_INT_SUM[P2_RTOUT] to generate an 2471 interrupt. */ 2472 uint64_t p1_rtout : 1; /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an 2473 interrupt. */ 2474 uint64_t p0_rtout : 1; /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an 2475 interrupt. */ 2476 uint64_t i3_overf : 1; /**< Enables NPI_INT_SUM[I3_OVERF] to generate an 2477 interrupt. */ 2478 uint64_t i2_overf : 1; /**< Enables NPI_INT_SUM[I2_OVERF] to generate an 2479 interrupt. */ 2480 uint64_t i1_overf : 1; /**< Enables NPI_INT_SUM[I1_OVERF] to generate an 2481 interrupt. */ 2482 uint64_t i0_overf : 1; /**< Enables NPI_INT_SUM[I0_OVERF] to generate an 2483 interrupt. */ 2484 uint64_t i3_rtout : 1; /**< Enables NPI_INT_SUM[I3_RTOUT] to generate an 2485 interrupt. */ 2486 uint64_t i2_rtout : 1; /**< Enables NPI_INT_SUM[I2_RTOUT] to generate an 2487 interrupt. */ 2488 uint64_t i1_rtout : 1; /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an 2489 interrupt. */ 2490 uint64_t i0_rtout : 1; /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an 2491 interrupt. */ 2492 uint64_t po3_2sml : 1; /**< Enables NPI_INT_SUM[PO3_2SML] to generate an 2493 interrupt. */ 2494 uint64_t po2_2sml : 1; /**< Enables NPI_INT_SUM[PO2_2SML] to generate an 2495 interrupt. */ 2496 uint64_t po1_2sml : 1; /**< Enables NPI_INT_SUM[PO1_2SML] to generate an 2497 interrupt. */ 2498 uint64_t po0_2sml : 1; /**< Enables NPI_INT_SUM[PO0_2SML] to generate an 2499 interrupt. */ 2500 uint64_t pci_rsl : 1; /**< Enables NPI_INT_SUM[PCI_RSL] to generate an 2501 interrupt. */ 2502 uint64_t rml_wto : 1; /**< Enables NPI_INT_SUM[RML_WTO] to generate an 2503 interrupt. */ 2504 uint64_t rml_rto : 1; /**< Enables NPI_INT_SUM[RML_RTO] to generate an 2505 interrupt. */ 2506#else 2507 uint64_t rml_rto : 1; 2508 uint64_t rml_wto : 1; 2509 uint64_t pci_rsl : 1; 2510 uint64_t po0_2sml : 1; 2511 uint64_t po1_2sml : 1; 2512 uint64_t po2_2sml : 1; 2513 uint64_t po3_2sml : 1; 2514 uint64_t i0_rtout : 1; 2515 uint64_t i1_rtout : 1; 2516 uint64_t i2_rtout : 1; 2517 uint64_t i3_rtout : 1; 2518 uint64_t i0_overf : 1; 2519 uint64_t i1_overf : 1; 2520 uint64_t i2_overf : 1; 2521 uint64_t i3_overf : 1; 2522 uint64_t p0_rtout : 1; 2523 uint64_t p1_rtout : 1; 2524 uint64_t p2_rtout : 1; 2525 uint64_t p3_rtout : 1; 2526 uint64_t p0_perr : 1; 2527 uint64_t p1_perr : 1; 2528 uint64_t p2_perr : 1; 2529 uint64_t p3_perr : 1; 2530 uint64_t g0_rtout : 1; 2531 uint64_t g1_rtout : 1; 2532 uint64_t g2_rtout : 1; 2533 uint64_t g3_rtout : 1; 2534 uint64_t p0_pperr : 1; 2535 uint64_t p1_pperr : 1; 2536 uint64_t p2_pperr : 1; 2537 uint64_t p3_pperr : 1; 2538 uint64_t p0_ptout : 1; 2539 uint64_t p1_ptout : 1; 2540 uint64_t p2_ptout : 1; 2541 uint64_t p3_ptout : 1; 2542 uint64_t i0_pperr : 1; 2543 uint64_t i1_pperr : 1; 2544 uint64_t i2_pperr : 1; 2545 uint64_t i3_pperr : 1; 2546 uint64_t win_rto : 1; 2547 uint64_t p_dperr : 1; 2548 uint64_t iobdma : 1; 2549 uint64_t reserved_42_63 : 22; 2550#endif 2551 } cn38xxp2; 2552 struct cvmx_npi_int_enb_cn31xx cn50xx; 2553 struct cvmx_npi_int_enb_s cn58xx; 2554 struct cvmx_npi_int_enb_s cn58xxp1; 2555}; 2556typedef union cvmx_npi_int_enb cvmx_npi_int_enb_t; 2557 2558/** 2559 * cvmx_npi_int_sum 2560 * 2561 * NPI_INTERRUPT_SUM = NPI Interrupt Summary Register 2562 * 2563 * Set when an interrupt condition occurs, write '1' to clear. 2564 */ 2565union cvmx_npi_int_sum 2566{ 2567 uint64_t u64; 2568 struct cvmx_npi_int_sum_s 2569 { 2570#if __BYTE_ORDER == __BIG_ENDIAN 2571 uint64_t reserved_62_63 : 2; 2572 uint64_t q1_a_f : 1; /**< Attempted to add when Queue-1 FIFO is full. 2573 PASS3 Field. */ 2574 uint64_t q1_s_e : 1; /**< Attempted to subtract when Queue-1 FIFO is empty. 2575 PASS3 Field. */ 2576 uint64_t pdf_p_f : 1; /**< Attempted to push a full PCN-DATA-FIFO. 2577 PASS3 Field. */ 2578 uint64_t pdf_p_e : 1; /**< Attempted to pop an empty PCN-DATA-FIFO. 2579 PASS3 Field. */ 2580 uint64_t pcf_p_f : 1; /**< Attempted to push a full PCN-CNT-FIFO. 2581 PASS3 Field. */ 2582 uint64_t pcf_p_e : 1; /**< Attempted to pop an empty PCN-CNT-FIFO. 2583 PASS3 Field. */ 2584 uint64_t rdx_s_e : 1; /**< Attempted to subtract when DPI-XFR-Wait count is 0. 2585 PASS3 Field. */ 2586 uint64_t rwx_s_e : 1; /**< Attempted to subtract when RDN-XFR-Wait count is 0. 2587 PASS3 Field. */ 2588 uint64_t pnc_a_f : 1; /**< Attempted to add when PNI-NPI Credits are max. 2589 PASS3 Field. */ 2590 uint64_t pnc_s_e : 1; /**< Attempted to subtract when PNI-NPI Credits are 0. 2591 PASS3 Field. */ 2592 uint64_t com_a_f : 1; /**< Attempted to add when PCN-Commit Counter is max. 2593 PASS3 Field. */ 2594 uint64_t com_s_e : 1; /**< Attempted to subtract when PCN-Commit Counter is 0. 2595 PASS3 Field. */ 2596 uint64_t q3_a_f : 1; /**< Attempted to add when Queue-3 FIFO is full. 2597 PASS3 Field. */ 2598 uint64_t q3_s_e : 1; /**< Attempted to subtract when Queue-3 FIFO is empty. 2599 PASS3 Field. */ 2600 uint64_t q2_a_f : 1; /**< Attempted to add when Queue-2 FIFO is full. 2601 PASS3 Field. */ 2602 uint64_t q2_s_e : 1; /**< Attempted to subtract when Queue-2 FIFO is empty. 2603 PASS3 Field. */ 2604 uint64_t pcr_a_f : 1; /**< Attempted to add when POW Credits is full. 2605 PASS3 Field. */ 2606 uint64_t pcr_s_e : 1; /**< Attempted to subtract when POW Credits is empty. 2607 PASS3 Field. */ 2608 uint64_t fcr_a_f : 1; /**< Attempted to add when FPA Credits is full. 2609 PASS3 Field. */ 2610 uint64_t fcr_s_e : 1; /**< Attempted to subtract when FPA Credits is empty. 2611 PASS3 Field. */ 2612 uint64_t iobdma : 1; /**< Requested IOBDMA read size exceeded 128 words. */ 2613 uint64_t p_dperr : 1; /**< If a parity error occured on data written to L2C 2614 from the PCI this bit may be set. */ 2615 uint64_t win_rto : 1; /**< Windowed Load Timed Out. */ 2616 uint64_t i3_pperr : 1; /**< If a parity error occured on the port's instruction 2617 this bit may be set. */ 2618 uint64_t i2_pperr : 1; /**< If a parity error occured on the port's instruction 2619 this bit may be set. */ 2620 uint64_t i1_pperr : 1; /**< If a parity error occured on the port's instruction 2621 this bit may be set. */ 2622 uint64_t i0_pperr : 1; /**< If a parity error occured on the port's instruction 2623 this bit may be set. */ 2624 uint64_t p3_ptout : 1; /**< Port-3 output had a read timeout on a DATA/INFO 2625 pair. */ 2626 uint64_t p2_ptout : 1; /**< Port-2 output had a read timeout on a DATA/INFO 2627 pair. */ 2628 uint64_t p1_ptout : 1; /**< Port-1 output had a read timeout on a DATA/INFO 2629 pair. */ 2630 uint64_t p0_ptout : 1; /**< Port-0 output had a read timeout on a DATA/INFO 2631 pair. */ 2632 uint64_t p3_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2633 pointer-pair, this bit may be set. */ 2634 uint64_t p2_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2635 pointer-pair, this bit may be set. */ 2636 uint64_t p1_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2637 pointer-pair, this bit may be set. */ 2638 uint64_t p0_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2639 pointer-pair, this bit may be set. */ 2640 uint64_t g3_rtout : 1; /**< Port-3 had a read timeout while attempting to 2641 read a gather list. */ 2642 uint64_t g2_rtout : 1; /**< Port-2 had a read timeout while attempting to 2643 read a gather list. */ 2644 uint64_t g1_rtout : 1; /**< Port-1 had a read timeout while attempting to 2645 read a gather list. */ 2646 uint64_t g0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2647 read a gather list. */ 2648 uint64_t p3_perr : 1; /**< If a parity error occured on the port's packet 2649 data this bit may be set. */ 2650 uint64_t p2_perr : 1; /**< If a parity error occured on the port's packet 2651 data this bit may be set. */ 2652 uint64_t p1_perr : 1; /**< If a parity error occured on the port's packet 2653 data this bit may be set. */ 2654 uint64_t p0_perr : 1; /**< If a parity error occured on the port's packet 2655 data this bit may be set. */ 2656 uint64_t p3_rtout : 1; /**< Port-3 had a read timeout while attempting to 2657 read packet data. */ 2658 uint64_t p2_rtout : 1; /**< Port-2 had a read timeout while attempting to 2659 read packet data. */ 2660 uint64_t p1_rtout : 1; /**< Port-1 had a read timeout while attempting to 2661 read packet data. */ 2662 uint64_t p0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2663 read packet data. */ 2664 uint64_t i3_overf : 1; /**< Port-3 had a doorbell overflow. Bit[31] of the 2665 doorbell count was set. */ 2666 uint64_t i2_overf : 1; /**< Port-2 had a doorbell overflow. Bit[31] of the 2667 doorbell count was set. */ 2668 uint64_t i1_overf : 1; /**< Port-1 had a doorbell overflow. Bit[31] of the 2669 doorbell count was set. */ 2670 uint64_t i0_overf : 1; /**< Port-0 had a doorbell overflow. Bit[31] of the 2671 doorbell count was set. */ 2672 uint64_t i3_rtout : 1; /**< Port-3 had a read timeout while attempting to 2673 read instructions. */ 2674 uint64_t i2_rtout : 1; /**< Port-2 had a read timeout while attempting to 2675 read instructions. */ 2676 uint64_t i1_rtout : 1; /**< Port-1 had a read timeout while attempting to 2677 read instructions. */ 2678 uint64_t i0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2679 read instructions. */ 2680 uint64_t po3_2sml : 1; /**< The packet being sent out on Port3 is smaller 2681 than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field. */ 2682 uint64_t po2_2sml : 1; /**< The packet being sent out on Port2 is smaller 2683 than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field. */ 2684 uint64_t po1_2sml : 1; /**< The packet being sent out on Port1 is smaller 2685 than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */ 2686 uint64_t po0_2sml : 1; /**< The packet being sent out on Port0 is smaller 2687 than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */ 2688 uint64_t pci_rsl : 1; /**< This '1' when a bit in PCI_INT_SUM2 is SET and the 2689 corresponding bit in the PCI_INT_ENB2 is SET. */ 2690 uint64_t rml_wto : 1; /**< Set '1' when the RML does not receive a commit 2691 back from a RSL after sending a write command to 2692 a RSL. */ 2693 uint64_t rml_rto : 1; /**< Set '1' when the RML does not receive read data 2694 back from a RSL after sending a read command to 2695 a RSL. */ 2696#else 2697 uint64_t rml_rto : 1; 2698 uint64_t rml_wto : 1; 2699 uint64_t pci_rsl : 1; 2700 uint64_t po0_2sml : 1; 2701 uint64_t po1_2sml : 1; 2702 uint64_t po2_2sml : 1; 2703 uint64_t po3_2sml : 1; 2704 uint64_t i0_rtout : 1; 2705 uint64_t i1_rtout : 1; 2706 uint64_t i2_rtout : 1; 2707 uint64_t i3_rtout : 1; 2708 uint64_t i0_overf : 1; 2709 uint64_t i1_overf : 1; 2710 uint64_t i2_overf : 1; 2711 uint64_t i3_overf : 1; 2712 uint64_t p0_rtout : 1; 2713 uint64_t p1_rtout : 1; 2714 uint64_t p2_rtout : 1; 2715 uint64_t p3_rtout : 1; 2716 uint64_t p0_perr : 1; 2717 uint64_t p1_perr : 1; 2718 uint64_t p2_perr : 1; 2719 uint64_t p3_perr : 1; 2720 uint64_t g0_rtout : 1; 2721 uint64_t g1_rtout : 1; 2722 uint64_t g2_rtout : 1; 2723 uint64_t g3_rtout : 1; 2724 uint64_t p0_pperr : 1; 2725 uint64_t p1_pperr : 1; 2726 uint64_t p2_pperr : 1; 2727 uint64_t p3_pperr : 1; 2728 uint64_t p0_ptout : 1; 2729 uint64_t p1_ptout : 1; 2730 uint64_t p2_ptout : 1; 2731 uint64_t p3_ptout : 1; 2732 uint64_t i0_pperr : 1; 2733 uint64_t i1_pperr : 1; 2734 uint64_t i2_pperr : 1; 2735 uint64_t i3_pperr : 1; 2736 uint64_t win_rto : 1; 2737 uint64_t p_dperr : 1; 2738 uint64_t iobdma : 1; 2739 uint64_t fcr_s_e : 1; 2740 uint64_t fcr_a_f : 1; 2741 uint64_t pcr_s_e : 1; 2742 uint64_t pcr_a_f : 1; 2743 uint64_t q2_s_e : 1; 2744 uint64_t q2_a_f : 1; 2745 uint64_t q3_s_e : 1; 2746 uint64_t q3_a_f : 1; 2747 uint64_t com_s_e : 1; 2748 uint64_t com_a_f : 1; 2749 uint64_t pnc_s_e : 1; 2750 uint64_t pnc_a_f : 1; 2751 uint64_t rwx_s_e : 1; 2752 uint64_t rdx_s_e : 1; 2753 uint64_t pcf_p_e : 1; 2754 uint64_t pcf_p_f : 1; 2755 uint64_t pdf_p_e : 1; 2756 uint64_t pdf_p_f : 1; 2757 uint64_t q1_s_e : 1; 2758 uint64_t q1_a_f : 1; 2759 uint64_t reserved_62_63 : 2; 2760#endif 2761 } s; 2762 struct cvmx_npi_int_sum_cn30xx 2763 { 2764#if __BYTE_ORDER == __BIG_ENDIAN 2765 uint64_t reserved_62_63 : 2; 2766 uint64_t q1_a_f : 1; /**< Attempted to add when Queue-1 FIFO is full. */ 2767 uint64_t q1_s_e : 1; /**< Attempted to subtract when Queue-1 FIFO is empty. */ 2768 uint64_t pdf_p_f : 1; /**< Attempted to push a full PCN-DATA-FIFO. */ 2769 uint64_t pdf_p_e : 1; /**< Attempted to pop an empty PCN-DATA-FIFO. */ 2770 uint64_t pcf_p_f : 1; /**< Attempted to push a full PCN-CNT-FIFO. */ 2771 uint64_t pcf_p_e : 1; /**< Attempted to pop an empty PCN-CNT-FIFO. */ 2772 uint64_t rdx_s_e : 1; /**< Attempted to subtract when DPI-XFR-Wait count is 0. */ 2773 uint64_t rwx_s_e : 1; /**< Attempted to subtract when RDN-XFR-Wait count is 0. */ 2774 uint64_t pnc_a_f : 1; /**< Attempted to add when PNI-NPI Credits are max. */ 2775 uint64_t pnc_s_e : 1; /**< Attempted to subtract when PNI-NPI Credits are 0. */ 2776 uint64_t com_a_f : 1; /**< Attempted to add when PCN-Commit Counter is max. */ 2777 uint64_t com_s_e : 1; /**< Attempted to subtract when PCN-Commit Counter is 0. */ 2778 uint64_t q3_a_f : 1; /**< Attempted to add when Queue-3 FIFO is full. */ 2779 uint64_t q3_s_e : 1; /**< Attempted to subtract when Queue-3 FIFO is empty. */ 2780 uint64_t q2_a_f : 1; /**< Attempted to add when Queue-2 FIFO is full. */ 2781 uint64_t q2_s_e : 1; /**< Attempted to subtract when Queue-2 FIFO is empty. */ 2782 uint64_t pcr_a_f : 1; /**< Attempted to add when POW Credits is full. */ 2783 uint64_t pcr_s_e : 1; /**< Attempted to subtract when POW Credits is empty. */ 2784 uint64_t fcr_a_f : 1; /**< Attempted to add when FPA Credits is full. */ 2785 uint64_t fcr_s_e : 1; /**< Attempted to subtract when FPA Credits is empty. */ 2786 uint64_t iobdma : 1; /**< Requested IOBDMA read size exceeded 128 words. */ 2787 uint64_t p_dperr : 1; /**< If a parity error occured on data written to L2C 2788 from the PCI this bit may be set. */ 2789 uint64_t win_rto : 1; /**< Windowed Load Timed Out. */ 2790 uint64_t reserved_36_38 : 3; 2791 uint64_t i0_pperr : 1; /**< If a parity error occured on the port's instruction 2792 this bit may be set. */ 2793 uint64_t reserved_32_34 : 3; 2794 uint64_t p0_ptout : 1; /**< Port-0 output had a read timeout on a DATA/INFO 2795 pair. */ 2796 uint64_t reserved_28_30 : 3; 2797 uint64_t p0_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2798 pointer-pair, this bit may be set. */ 2799 uint64_t reserved_24_26 : 3; 2800 uint64_t g0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2801 read a gather list. */ 2802 uint64_t reserved_20_22 : 3; 2803 uint64_t p0_perr : 1; /**< If a parity error occured on the port's packet 2804 data this bit may be set. */ 2805 uint64_t reserved_16_18 : 3; 2806 uint64_t p0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2807 read packet data. */ 2808 uint64_t reserved_12_14 : 3; 2809 uint64_t i0_overf : 1; /**< Port-0 had a doorbell overflow. Bit[31] of the 2810 doorbell count was set. */ 2811 uint64_t reserved_8_10 : 3; 2812 uint64_t i0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2813 read instructions. */ 2814 uint64_t reserved_4_6 : 3; 2815 uint64_t po0_2sml : 1; /**< The packet being sent out on Port0 is smaller 2816 than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */ 2817 uint64_t pci_rsl : 1; /**< This '1' when a bit in PCI_INT_SUM2 is SET and the 2818 corresponding bit in the PCI_INT_ENB2 is SET. */ 2819 uint64_t rml_wto : 1; /**< Set '1' when the RML does not receive a commit 2820 back from a RSL after sending a write command to 2821 a RSL. */ 2822 uint64_t rml_rto : 1; /**< Set '1' when the RML does not receive read data 2823 back from a RSL after sending a read command to 2824 a RSL. */ 2825#else 2826 uint64_t rml_rto : 1; 2827 uint64_t rml_wto : 1; 2828 uint64_t pci_rsl : 1; 2829 uint64_t po0_2sml : 1; 2830 uint64_t reserved_4_6 : 3; 2831 uint64_t i0_rtout : 1; 2832 uint64_t reserved_8_10 : 3; 2833 uint64_t i0_overf : 1; 2834 uint64_t reserved_12_14 : 3; 2835 uint64_t p0_rtout : 1; 2836 uint64_t reserved_16_18 : 3; 2837 uint64_t p0_perr : 1; 2838 uint64_t reserved_20_22 : 3; 2839 uint64_t g0_rtout : 1; 2840 uint64_t reserved_24_26 : 3; 2841 uint64_t p0_pperr : 1; 2842 uint64_t reserved_28_30 : 3; 2843 uint64_t p0_ptout : 1; 2844 uint64_t reserved_32_34 : 3; 2845 uint64_t i0_pperr : 1; 2846 uint64_t reserved_36_38 : 3; 2847 uint64_t win_rto : 1; 2848 uint64_t p_dperr : 1; 2849 uint64_t iobdma : 1; 2850 uint64_t fcr_s_e : 1; 2851 uint64_t fcr_a_f : 1; 2852 uint64_t pcr_s_e : 1; 2853 uint64_t pcr_a_f : 1; 2854 uint64_t q2_s_e : 1; 2855 uint64_t q2_a_f : 1; 2856 uint64_t q3_s_e : 1; 2857 uint64_t q3_a_f : 1; 2858 uint64_t com_s_e : 1; 2859 uint64_t com_a_f : 1; 2860 uint64_t pnc_s_e : 1; 2861 uint64_t pnc_a_f : 1; 2862 uint64_t rwx_s_e : 1; 2863 uint64_t rdx_s_e : 1; 2864 uint64_t pcf_p_e : 1; 2865 uint64_t pcf_p_f : 1; 2866 uint64_t pdf_p_e : 1; 2867 uint64_t pdf_p_f : 1; 2868 uint64_t q1_s_e : 1; 2869 uint64_t q1_a_f : 1; 2870 uint64_t reserved_62_63 : 2; 2871#endif 2872 } cn30xx; 2873 struct cvmx_npi_int_sum_cn31xx 2874 { 2875#if __BYTE_ORDER == __BIG_ENDIAN 2876 uint64_t reserved_62_63 : 2; 2877 uint64_t q1_a_f : 1; /**< Attempted to add when Queue-1 FIFO is full. */ 2878 uint64_t q1_s_e : 1; /**< Attempted to subtract when Queue-1 FIFO is empty. */ 2879 uint64_t pdf_p_f : 1; /**< Attempted to push a full PCN-DATA-FIFO. */ 2880 uint64_t pdf_p_e : 1; /**< Attempted to pop an empty PCN-DATA-FIFO. */ 2881 uint64_t pcf_p_f : 1; /**< Attempted to push a full PCN-CNT-FIFO. */ 2882 uint64_t pcf_p_e : 1; /**< Attempted to pop an empty PCN-CNT-FIFO. */ 2883 uint64_t rdx_s_e : 1; /**< Attempted to subtract when DPI-XFR-Wait count is 0. */ 2884 uint64_t rwx_s_e : 1; /**< Attempted to subtract when RDN-XFR-Wait count is 0. */ 2885 uint64_t pnc_a_f : 1; /**< Attempted to add when PNI-NPI Credits are max. */ 2886 uint64_t pnc_s_e : 1; /**< Attempted to subtract when PNI-NPI Credits are 0. */ 2887 uint64_t com_a_f : 1; /**< Attempted to add when PCN-Commit Counter is max. */ 2888 uint64_t com_s_e : 1; /**< Attempted to subtract when PCN-Commit Counter is 0. */ 2889 uint64_t q3_a_f : 1; /**< Attempted to add when Queue-3 FIFO is full. */ 2890 uint64_t q3_s_e : 1; /**< Attempted to subtract when Queue-3 FIFO is empty. */ 2891 uint64_t q2_a_f : 1; /**< Attempted to add when Queue-2 FIFO is full. */ 2892 uint64_t q2_s_e : 1; /**< Attempted to subtract when Queue-2 FIFO is empty. */ 2893 uint64_t pcr_a_f : 1; /**< Attempted to add when POW Credits is full. */ 2894 uint64_t pcr_s_e : 1; /**< Attempted to subtract when POW Credits is empty. */ 2895 uint64_t fcr_a_f : 1; /**< Attempted to add when FPA Credits is full. */ 2896 uint64_t fcr_s_e : 1; /**< Attempted to subtract when FPA Credits is empty. */ 2897 uint64_t iobdma : 1; /**< Requested IOBDMA read size exceeded 128 words. */ 2898 uint64_t p_dperr : 1; /**< If a parity error occured on data written to L2C 2899 from the PCI this bit may be set. */ 2900 uint64_t win_rto : 1; /**< Windowed Load Timed Out. */ 2901 uint64_t reserved_37_38 : 2; 2902 uint64_t i1_pperr : 1; /**< If a parity error occured on the port's instruction 2903 this bit may be set. */ 2904 uint64_t i0_pperr : 1; /**< If a parity error occured on the port's instruction 2905 this bit may be set. */ 2906 uint64_t reserved_33_34 : 2; 2907 uint64_t p1_ptout : 1; /**< Port-1 output had a read timeout on a DATA/INFO 2908 pair. */ 2909 uint64_t p0_ptout : 1; /**< Port-0 output had a read timeout on a DATA/INFO 2910 pair. */ 2911 uint64_t reserved_29_30 : 2; 2912 uint64_t p1_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2913 pointer-pair, this bit may be set. */ 2914 uint64_t p0_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2915 pointer-pair, this bit may be set. */ 2916 uint64_t reserved_25_26 : 2; 2917 uint64_t g1_rtout : 1; /**< Port-1 had a read timeout while attempting to 2918 read a gather list. */ 2919 uint64_t g0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2920 read a gather list. */ 2921 uint64_t reserved_21_22 : 2; 2922 uint64_t p1_perr : 1; /**< If a parity error occured on the port's packet 2923 data this bit may be set. */ 2924 uint64_t p0_perr : 1; /**< If a parity error occured on the port's packet 2925 data this bit may be set. */ 2926 uint64_t reserved_17_18 : 2; 2927 uint64_t p1_rtout : 1; /**< Port-1 had a read timeout while attempting to 2928 read packet data. */ 2929 uint64_t p0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2930 read packet data. */ 2931 uint64_t reserved_13_14 : 2; 2932 uint64_t i1_overf : 1; /**< Port-1 had a doorbell overflow. Bit[31] of the 2933 doorbell count was set. */ 2934 uint64_t i0_overf : 1; /**< Port-0 had a doorbell overflow. Bit[31] of the 2935 doorbell count was set. */ 2936 uint64_t reserved_9_10 : 2; 2937 uint64_t i1_rtout : 1; /**< Port-1 had a read timeout while attempting to 2938 read instructions. */ 2939 uint64_t i0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2940 read instructions. */ 2941 uint64_t reserved_5_6 : 2; 2942 uint64_t po1_2sml : 1; /**< The packet being sent out on Port1 is smaller 2943 than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */ 2944 uint64_t po0_2sml : 1; /**< The packet being sent out on Port0 is smaller 2945 than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */ 2946 uint64_t pci_rsl : 1; /**< This '1' when a bit in PCI_INT_SUM2 is SET and the 2947 corresponding bit in the PCI_INT_ENB2 is SET. */ 2948 uint64_t rml_wto : 1; /**< Set '1' when the RML does not receive a commit 2949 back from a RSL after sending a write command to 2950 a RSL. */ 2951 uint64_t rml_rto : 1; /**< Set '1' when the RML does not receive read data 2952 back from a RSL after sending a read command to 2953 a RSL. */ 2954#else 2955 uint64_t rml_rto : 1; 2956 uint64_t rml_wto : 1; 2957 uint64_t pci_rsl : 1; 2958 uint64_t po0_2sml : 1; 2959 uint64_t po1_2sml : 1; 2960 uint64_t reserved_5_6 : 2; 2961 uint64_t i0_rtout : 1; 2962 uint64_t i1_rtout : 1; 2963 uint64_t reserved_9_10 : 2; 2964 uint64_t i0_overf : 1; 2965 uint64_t i1_overf : 1; 2966 uint64_t reserved_13_14 : 2; 2967 uint64_t p0_rtout : 1; 2968 uint64_t p1_rtout : 1; 2969 uint64_t reserved_17_18 : 2; 2970 uint64_t p0_perr : 1; 2971 uint64_t p1_perr : 1; 2972 uint64_t reserved_21_22 : 2; 2973 uint64_t g0_rtout : 1; 2974 uint64_t g1_rtout : 1; 2975 uint64_t reserved_25_26 : 2; 2976 uint64_t p0_pperr : 1; 2977 uint64_t p1_pperr : 1; 2978 uint64_t reserved_29_30 : 2; 2979 uint64_t p0_ptout : 1; 2980 uint64_t p1_ptout : 1; 2981 uint64_t reserved_33_34 : 2; 2982 uint64_t i0_pperr : 1; 2983 uint64_t i1_pperr : 1; 2984 uint64_t reserved_37_38 : 2; 2985 uint64_t win_rto : 1; 2986 uint64_t p_dperr : 1; 2987 uint64_t iobdma : 1; 2988 uint64_t fcr_s_e : 1; 2989 uint64_t fcr_a_f : 1; 2990 uint64_t pcr_s_e : 1; 2991 uint64_t pcr_a_f : 1; 2992 uint64_t q2_s_e : 1; 2993 uint64_t q2_a_f : 1; 2994 uint64_t q3_s_e : 1; 2995 uint64_t q3_a_f : 1; 2996 uint64_t com_s_e : 1; 2997 uint64_t com_a_f : 1; 2998 uint64_t pnc_s_e : 1; 2999 uint64_t pnc_a_f : 1; 3000 uint64_t rwx_s_e : 1; 3001 uint64_t rdx_s_e : 1; 3002 uint64_t pcf_p_e : 1; 3003 uint64_t pcf_p_f : 1; 3004 uint64_t pdf_p_e : 1; 3005 uint64_t pdf_p_f : 1; 3006 uint64_t q1_s_e : 1; 3007 uint64_t q1_a_f : 1; 3008 uint64_t reserved_62_63 : 2; 3009#endif 3010 } cn31xx; 3011 struct cvmx_npi_int_sum_s cn38xx; 3012 struct cvmx_npi_int_sum_cn38xxp2 3013 { 3014#if __BYTE_ORDER == __BIG_ENDIAN 3015 uint64_t reserved_42_63 : 22; 3016 uint64_t iobdma : 1; /**< Requested IOBDMA read size exceeded 128 words. */ 3017 uint64_t p_dperr : 1; /**< If a parity error occured on data written to L2C 3018 from the PCI this bit may be set. */ 3019 uint64_t win_rto : 1; /**< Windowed Load Timed Out. */ 3020 uint64_t i3_pperr : 1; /**< If a parity error occured on the port's instruction 3021 this bit may be set. */ 3022 uint64_t i2_pperr : 1; /**< If a parity error occured on the port's instruction 3023 this bit may be set. */ 3024 uint64_t i1_pperr : 1; /**< If a parity error occured on the port's instruction 3025 this bit may be set. */ 3026 uint64_t i0_pperr : 1; /**< If a parity error occured on the port's instruction 3027 this bit may be set. */ 3028 uint64_t p3_ptout : 1; /**< Port-3 output had a read timeout on a DATA/INFO 3029 pair. */ 3030 uint64_t p2_ptout : 1; /**< Port-2 output had a read timeout on a DATA/INFO 3031 pair. */ 3032 uint64_t p1_ptout : 1; /**< Port-1 output had a read timeout on a DATA/INFO 3033 pair. */ 3034 uint64_t p0_ptout : 1; /**< Port-0 output had a read timeout on a DATA/INFO 3035 pair. */ 3036 uint64_t p3_pperr : 1; /**< If a parity error occured on the port DATA/INFO 3037 pointer-pair, this bit may be set. */ 3038 uint64_t p2_pperr : 1; /**< If a parity error occured on the port DATA/INFO 3039 pointer-pair, this bit may be set. */ 3040 uint64_t p1_pperr : 1; /**< If a parity error occured on the port DATA/INFO 3041 pointer-pair, this bit may be set. */ 3042 uint64_t p0_pperr : 1; /**< If a parity error occured on the port DATA/INFO 3043 pointer-pair, this bit may be set. */ 3044 uint64_t g3_rtout : 1; /**< Port-3 had a read timeout while attempting to 3045 read a gather list. */ 3046 uint64_t g2_rtout : 1; /**< Port-2 had a read timeout while attempting to 3047 read a gather list. */ 3048 uint64_t g1_rtout : 1; /**< Port-1 had a read timeout while attempting to 3049 read a gather list. */ 3050 uint64_t g0_rtout : 1; /**< Port-0 had a read timeout while attempting to 3051 read a gather list. */ 3052 uint64_t p3_perr : 1; /**< If a parity error occured on the port's packet 3053 data this bit may be set. */ 3054 uint64_t p2_perr : 1; /**< If a parity error occured on the port's packet 3055 data this bit may be set. */ 3056 uint64_t p1_perr : 1; /**< If a parity error occured on the port's packet 3057 data this bit may be set. */ 3058 uint64_t p0_perr : 1; /**< If a parity error occured on the port's packet 3059 data this bit may be set. */ 3060 uint64_t p3_rtout : 1; /**< Port-3 had a read timeout while attempting to 3061 read packet data. */ 3062 uint64_t p2_rtout : 1; /**< Port-2 had a read timeout while attempting to 3063 read packet data. */ 3064 uint64_t p1_rtout : 1; /**< Port-1 had a read timeout while attempting to 3065 read packet data. */ 3066 uint64_t p0_rtout : 1; /**< Port-0 had a read timeout while attempting to 3067 read packet data. */ 3068 uint64_t i3_overf : 1; /**< Port-3 had a doorbell overflow. Bit[31] of the 3069 doorbell count was set. */ 3070 uint64_t i2_overf : 1; /**< Port-2 had a doorbell overflow. Bit[31] of the 3071 doorbell count was set. */ 3072 uint64_t i1_overf : 1; /**< Port-1 had a doorbell overflow. Bit[31] of the 3073 doorbell count was set. */ 3074 uint64_t i0_overf : 1; /**< Port-0 had a doorbell overflow. Bit[31] of the 3075 doorbell count was set. */ 3076 uint64_t i3_rtout : 1; /**< Port-3 had a read timeout while attempting to 3077 read instructions. */ 3078 uint64_t i2_rtout : 1; /**< Port-2 had a read timeout while attempting to 3079 read instructions. */ 3080 uint64_t i1_rtout : 1; /**< Port-1 had a read timeout while attempting to 3081 read instructions. */ 3082 uint64_t i0_rtout : 1; /**< Port-0 had a read timeout while attempting to 3083 read instructions. */ 3084 uint64_t po3_2sml : 1; /**< The packet being sent out on Port3 is smaller 3085 than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field. */ 3086 uint64_t po2_2sml : 1; /**< The packet being sent out on Port2 is smaller 3087 than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field. */ 3088 uint64_t po1_2sml : 1; /**< The packet being sent out on Port1 is smaller 3089 than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */ 3090 uint64_t po0_2sml : 1; /**< The packet being sent out on Port0 is smaller 3091 than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */ 3092 uint64_t pci_rsl : 1; /**< This '1' when a bit in PCI_INT_SUM2 is SET and the 3093 corresponding bit in the PCI_INT_ENB2 is SET. */ 3094 uint64_t rml_wto : 1; /**< Set '1' when the RML does not receive a commit 3095 back from a RSL after sending a write command to 3096 a RSL. */ 3097 uint64_t rml_rto : 1; /**< Set '1' when the RML does not receive read data 3098 back from a RSL after sending a read command to 3099 a RSL. */ 3100#else 3101 uint64_t rml_rto : 1; 3102 uint64_t rml_wto : 1; 3103 uint64_t pci_rsl : 1; 3104 uint64_t po0_2sml : 1; 3105 uint64_t po1_2sml : 1; 3106 uint64_t po2_2sml : 1; 3107 uint64_t po3_2sml : 1; 3108 uint64_t i0_rtout : 1; 3109 uint64_t i1_rtout : 1; 3110 uint64_t i2_rtout : 1; 3111 uint64_t i3_rtout : 1; 3112 uint64_t i0_overf : 1; 3113 uint64_t i1_overf : 1; 3114 uint64_t i2_overf : 1; 3115 uint64_t i3_overf : 1; 3116 uint64_t p0_rtout : 1; 3117 uint64_t p1_rtout : 1; 3118 uint64_t p2_rtout : 1; 3119 uint64_t p3_rtout : 1; 3120 uint64_t p0_perr : 1; 3121 uint64_t p1_perr : 1; 3122 uint64_t p2_perr : 1; 3123 uint64_t p3_perr : 1; 3124 uint64_t g0_rtout : 1; 3125 uint64_t g1_rtout : 1; 3126 uint64_t g2_rtout : 1; 3127 uint64_t g3_rtout : 1; 3128 uint64_t p0_pperr : 1; 3129 uint64_t p1_pperr : 1; 3130 uint64_t p2_pperr : 1; 3131 uint64_t p3_pperr : 1; 3132 uint64_t p0_ptout : 1; 3133 uint64_t p1_ptout : 1; 3134 uint64_t p2_ptout : 1; 3135 uint64_t p3_ptout : 1; 3136 uint64_t i0_pperr : 1; 3137 uint64_t i1_pperr : 1; 3138 uint64_t i2_pperr : 1; 3139 uint64_t i3_pperr : 1; 3140 uint64_t win_rto : 1; 3141 uint64_t p_dperr : 1; 3142 uint64_t iobdma : 1; 3143 uint64_t reserved_42_63 : 22; 3144#endif 3145 } cn38xxp2; 3146 struct cvmx_npi_int_sum_cn31xx cn50xx; 3147 struct cvmx_npi_int_sum_s cn58xx; 3148 struct cvmx_npi_int_sum_s cn58xxp1; 3149}; 3150typedef union cvmx_npi_int_sum cvmx_npi_int_sum_t; 3151 3152/** 3153 * cvmx_npi_lowp_dbell 3154 * 3155 * NPI_LOWP_DBELL = Low Priority Door Bell 3156 * 3157 * The door bell register for the low priority DMA queue. 3158 */ 3159union cvmx_npi_lowp_dbell 3160{ 3161 uint64_t u64; 3162 struct cvmx_npi_lowp_dbell_s 3163 { 3164#if __BYTE_ORDER == __BIG_ENDIAN 3165 uint64_t reserved_16_63 : 48; 3166 uint64_t dbell : 16; /**< The value written to this register is added to the 3167 number of 8byte words to be read and processes for 3168 the low priority dma queue. */ 3169#else 3170 uint64_t dbell : 16; 3171 uint64_t reserved_16_63 : 48; 3172#endif 3173 } s; 3174 struct cvmx_npi_lowp_dbell_s cn30xx; 3175 struct cvmx_npi_lowp_dbell_s cn31xx; 3176 struct cvmx_npi_lowp_dbell_s cn38xx; 3177 struct cvmx_npi_lowp_dbell_s cn38xxp2; 3178 struct cvmx_npi_lowp_dbell_s cn50xx; 3179 struct cvmx_npi_lowp_dbell_s cn58xx; 3180 struct cvmx_npi_lowp_dbell_s cn58xxp1; 3181}; 3182typedef union cvmx_npi_lowp_dbell cvmx_npi_lowp_dbell_t; 3183 3184/** 3185 * cvmx_npi_lowp_ibuff_saddr 3186 * 3187 * NPI_LOWP_IBUFF_SADDR = DMA Low Priority's Instruction Buffer Starting Address 3188 * 3189 * The address to start reading Instructions from for LOWP. 3190 */ 3191union cvmx_npi_lowp_ibuff_saddr 3192{ 3193 uint64_t u64; 3194 struct cvmx_npi_lowp_ibuff_saddr_s 3195 { 3196#if __BYTE_ORDER == __BIG_ENDIAN 3197 uint64_t reserved_36_63 : 28; 3198 uint64_t saddr : 36; /**< The starting address to read the first instruction. */ 3199#else 3200 uint64_t saddr : 36; 3201 uint64_t reserved_36_63 : 28; 3202#endif 3203 } s; 3204 struct cvmx_npi_lowp_ibuff_saddr_s cn30xx; 3205 struct cvmx_npi_lowp_ibuff_saddr_s cn31xx; 3206 struct cvmx_npi_lowp_ibuff_saddr_s cn38xx; 3207 struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2; 3208 struct cvmx_npi_lowp_ibuff_saddr_s cn50xx; 3209 struct cvmx_npi_lowp_ibuff_saddr_s cn58xx; 3210 struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1; 3211}; 3212typedef union cvmx_npi_lowp_ibuff_saddr cvmx_npi_lowp_ibuff_saddr_t; 3213 3214/** 3215 * cvmx_npi_mem_access_subid# 3216 * 3217 * NPI_MEM_ACCESS_SUBID3 = Memory Access SubId 3Register 3218 * 3219 * Carries Read/Write parameters for PP access to PCI memory that use NPI SubId3. 3220 * Writes to this register are not ordered with writes/reads to the PCI Memory space. 3221 * To ensure that a write has completed the user must read the register before 3222 * making an access(i.e. PCI memory space) that requires the value of this register to be updated. 3223 */ 3224union cvmx_npi_mem_access_subidx 3225{ 3226 uint64_t u64; 3227 struct cvmx_npi_mem_access_subidx_s 3228 { 3229#if __BYTE_ORDER == __BIG_ENDIAN 3230 uint64_t reserved_38_63 : 26; 3231 uint64_t shortl : 1; /**< Generate CMD-6 on PCI(x) when '1'. 3232 Loads from the cores to the corresponding subid 3233 that are 32-bits or smaller: 3234 - Will generate the PCI-X "Memory Read DWORD" 3235 command in PCI-X mode. (Note that "Memory 3236 Read DWORD" appears much like an IO read on 3237 the PCI-X bus.) 3238 - Will generate the PCI "Memory Read" command 3239 in PCI-X mode, irrespective of the 3240 NPI_PCI_READ_CMD[CMD_SIZE] value. 3241 NOT IN PASS 1 NOR PASS 2 */ 3242 uint64_t nmerge : 1; /**< No Merge. (NOT IN PASS 1 NOR PASS 2) */ 3243 uint64_t esr : 2; /**< Endian-Swap on read. */ 3244 uint64_t esw : 2; /**< Endian-Swap on write. */ 3245 uint64_t nsr : 1; /**< No-Snoop on read. */ 3246 uint64_t nsw : 1; /**< No-Snoop on write. */ 3247 uint64_t ror : 1; /**< Relax Read on read. */ 3248 uint64_t row : 1; /**< Relax Order on write. */ 3249 uint64_t ba : 28; /**< PCI Address bits [63:36]. */ 3250#else 3251 uint64_t ba : 28; 3252 uint64_t row : 1; 3253 uint64_t ror : 1; 3254 uint64_t nsw : 1; 3255 uint64_t nsr : 1; 3256 uint64_t esw : 2; 3257 uint64_t esr : 2; 3258 uint64_t nmerge : 1; 3259 uint64_t shortl : 1; 3260 uint64_t reserved_38_63 : 26; 3261#endif 3262 } s; 3263 struct cvmx_npi_mem_access_subidx_s cn30xx; 3264 struct cvmx_npi_mem_access_subidx_cn31xx 3265 { 3266#if __BYTE_ORDER == __BIG_ENDIAN 3267 uint64_t reserved_36_63 : 28; 3268 uint64_t esr : 2; /**< Endian-Swap on read. */ 3269 uint64_t esw : 2; /**< Endian-Swap on write. */ 3270 uint64_t nsr : 1; /**< No-Snoop on read. */ 3271 uint64_t nsw : 1; /**< No-Snoop on write. */ 3272 uint64_t ror : 1; /**< Relax Read on read. */ 3273 uint64_t row : 1; /**< Relax Order on write. */ 3274 uint64_t ba : 28; /**< PCI Address bits [63:36]. */ 3275#else 3276 uint64_t ba : 28; 3277 uint64_t row : 1; 3278 uint64_t ror : 1; 3279 uint64_t nsw : 1; 3280 uint64_t nsr : 1; 3281 uint64_t esw : 2; 3282 uint64_t esr : 2; 3283 uint64_t reserved_36_63 : 28; 3284#endif 3285 } cn31xx; 3286 struct cvmx_npi_mem_access_subidx_s cn38xx; 3287 struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2; 3288 struct cvmx_npi_mem_access_subidx_s cn50xx; 3289 struct cvmx_npi_mem_access_subidx_s cn58xx; 3290 struct cvmx_npi_mem_access_subidx_s cn58xxp1; 3291}; 3292typedef union cvmx_npi_mem_access_subidx cvmx_npi_mem_access_subidx_t; 3293 3294/** 3295 * cvmx_npi_msi_rcv 3296 * 3297 * NPI_MSI_RCV = NPI MSI Receive Vector Register 3298 * 3299 * A bit is set in this register relative to the vector received during a MSI. And cleared by a W1 to the register. 3300 */ 3301union cvmx_npi_msi_rcv 3302{ 3303 uint64_t u64; 3304 struct cvmx_npi_msi_rcv_s 3305 { 3306#if __BYTE_ORDER == __BIG_ENDIAN 3307 uint64_t int_vec : 64; /**< Refer to PCI_MSI_RCV */ 3308#else 3309 uint64_t int_vec : 64; 3310#endif 3311 } s; 3312 struct cvmx_npi_msi_rcv_s cn30xx; 3313 struct cvmx_npi_msi_rcv_s cn31xx; 3314 struct cvmx_npi_msi_rcv_s cn38xx; 3315 struct cvmx_npi_msi_rcv_s cn38xxp2; 3316 struct cvmx_npi_msi_rcv_s cn50xx; 3317 struct cvmx_npi_msi_rcv_s cn58xx; 3318 struct cvmx_npi_msi_rcv_s cn58xxp1; 3319}; 3320typedef union cvmx_npi_msi_rcv cvmx_npi_msi_rcv_t; 3321 3322/** 3323 * cvmx_npi_num_desc_output# 3324 * 3325 * NUM_DESC_OUTPUT0 = Number Of Descriptors Available For Output 0 3326 * 3327 * The size of the Buffer/Info Pointer Pair ring for Output-0. 3328 */ 3329union cvmx_npi_num_desc_outputx 3330{ 3331 uint64_t u64; 3332 struct cvmx_npi_num_desc_outputx_s 3333 { 3334#if __BYTE_ORDER == __BIG_ENDIAN 3335 uint64_t reserved_32_63 : 32; 3336 uint64_t size : 32; /**< The size of the Buffer/Info Pointer Pair ring. */ 3337#else 3338 uint64_t size : 32; 3339 uint64_t reserved_32_63 : 32; 3340#endif 3341 } s; 3342 struct cvmx_npi_num_desc_outputx_s cn30xx; 3343 struct cvmx_npi_num_desc_outputx_s cn31xx; 3344 struct cvmx_npi_num_desc_outputx_s cn38xx; 3345 struct cvmx_npi_num_desc_outputx_s cn38xxp2; 3346 struct cvmx_npi_num_desc_outputx_s cn50xx; 3347 struct cvmx_npi_num_desc_outputx_s cn58xx; 3348 struct cvmx_npi_num_desc_outputx_s cn58xxp1; 3349}; 3350typedef union cvmx_npi_num_desc_outputx cvmx_npi_num_desc_outputx_t; 3351 3352/** 3353 * cvmx_npi_output_control 3354 * 3355 * NPI_OUTPUT_CONTROL = NPI's Output Control Register 3356 * 3357 * The address to start reading Instructions from for Output-3. 3358 */ 3359union cvmx_npi_output_control 3360{ 3361 uint64_t u64; 3362 struct cvmx_npi_output_control_s 3363 { 3364#if __BYTE_ORDER == __BIG_ENDIAN 3365 uint64_t reserved_49_63 : 15; 3366 uint64_t pkt_rr : 1; /**< When set '1' the output packet selection will be 3367 made with a Round Robin arbitration. When '0' 3368 the output packet port is fixed in priority, 3369 where the lower port number has higher priority. 3370 PASS3 Field */ 3371 uint64_t p3_bmode : 1; /**< When set '1' PCI_PKTS_SENT3 register will be 3372 updated with the number of bytes in the packet 3373 sent, when '0' the register will have a value 3374 of '1' added. */ 3375 uint64_t p2_bmode : 1; /**< When set '1' PCI_PKTS_SENT2 register will be 3376 updated with the number of bytes in the packet 3377 sent, when '0' the register will have a value 3378 of '1' added. */ 3379 uint64_t p1_bmode : 1; /**< When set '1' PCI_PKTS_SENT1 register will be 3380 updated with the number of bytes in the packet 3381 sent, when '0' the register will have a value 3382 of '1' added. */ 3383 uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be 3384 updated with the number of bytes in the packet 3385 sent, when '0' the register will have a value 3386 of '1' added. */ 3387 uint64_t o3_es : 2; /**< Endian Swap for Output3 Data. */ 3388 uint64_t o3_ns : 1; /**< NoSnoop Enable for Output3 Data. */ 3389 uint64_t o3_ro : 1; /**< Relaxed Ordering Enable for Output3 Data. */ 3390 uint64_t o2_es : 2; /**< Endian Swap for Output2 Data. */ 3391 uint64_t o2_ns : 1; /**< NoSnoop Enable for Output2 Data. */ 3392 uint64_t o2_ro : 1; /**< Relaxed Ordering Enable for Output2 Data. */ 3393 uint64_t o1_es : 2; /**< Endian Swap for Output1 Data. */ 3394 uint64_t o1_ns : 1; /**< NoSnoop Enable for Output1 Data. */ 3395 uint64_t o1_ro : 1; /**< Relaxed Ordering Enable for Output1 Data. */ 3396 uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */ 3397 uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */ 3398 uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */ 3399 uint64_t o3_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3400 comes from the DPTR[63:60] in the scatter-list pair, 3401 and the RO, NS, ES values come from the O3_ES, 3402 O3_NS, O3_RO. When '0' the RO == DPTR[60], 3403 NS == DPTR[61], ES == DPTR[63:62], the address the 3404 packet will be written to is ADDR[63:60] == 3405 O3_ES[1:0], O3_NS, O3_RO. For Output Port-3. */ 3406 uint64_t o2_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3407 comes from the DPTR[63:60] in the scatter-list pair, 3408 and the RO, NS, ES values come from the O2_ES, 3409 O2_NS, O2_RO. When '0' the RO == DPTR[60], 3410 NS == DPTR[61], ES == DPTR[63:62], the address the 3411 packet will be written to is ADDR[63:60] == 3412 O2_ES[1:0], O2_NS, O2_RO. For Output Port-2. */ 3413 uint64_t o1_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3414 comes from the DPTR[63:60] in the scatter-list pair, 3415 and the RO, NS, ES values come from the O1_ES, 3416 O1_NS, O1_RO. When '0' the RO == DPTR[60], 3417 NS == DPTR[61], ES == DPTR[63:62], the address the 3418 packet will be written to is ADDR[63:60] == 3419 O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */ 3420 uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3421 comes from the DPTR[63:60] in the scatter-list pair, 3422 and the RO, NS, ES values come from the O0_ES, 3423 O0_NS, O0_RO. When '0' the RO == DPTR[60], 3424 NS == DPTR[61], ES == DPTR[63:62], the address the 3425 packet will be written to is ADDR[63:60] == 3426 O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */ 3427 uint64_t reserved_20_23 : 4; 3428 uint64_t iptr_o3 : 1; /**< Uses the Info-Pointer to store length and data 3429 for output-3. */ 3430 uint64_t iptr_o2 : 1; /**< Uses the Info-Pointer to store length and data 3431 for output-2. */ 3432 uint64_t iptr_o1 : 1; /**< Uses the Info-Pointer to store length and data 3433 for output-1. */ 3434 uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data 3435 for output-0. */ 3436 uint64_t esr_sl3 : 2; /**< The Endian-Swap-Mode for Slist3 reads. */ 3437 uint64_t nsr_sl3 : 1; /**< Enables '1' NoSnoop for Slist3 reads. */ 3438 uint64_t ror_sl3 : 1; /**< Enables '1' Relaxed Ordering for Slist3 reads. */ 3439 uint64_t esr_sl2 : 2; /**< The Endian-Swap-Mode for Slist2 reads. */ 3440 uint64_t nsr_sl2 : 1; /**< Enables '1' NoSnoop for Slist2 reads. */ 3441 uint64_t ror_sl2 : 1; /**< Enables '1' Relaxed Ordering for Slist2 reads. */ 3442 uint64_t esr_sl1 : 2; /**< The Endian-Swap-Mode for Slist1 reads. */ 3443 uint64_t nsr_sl1 : 1; /**< Enables '1' NoSnoop for Slist1 reads. */ 3444 uint64_t ror_sl1 : 1; /**< Enables '1' Relaxed Ordering for Slist1 reads. */ 3445 uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */ 3446 uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */ 3447 uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */ 3448#else 3449 uint64_t ror_sl0 : 1; 3450 uint64_t nsr_sl0 : 1; 3451 uint64_t esr_sl0 : 2; 3452 uint64_t ror_sl1 : 1; 3453 uint64_t nsr_sl1 : 1; 3454 uint64_t esr_sl1 : 2; 3455 uint64_t ror_sl2 : 1; 3456 uint64_t nsr_sl2 : 1; 3457 uint64_t esr_sl2 : 2; 3458 uint64_t ror_sl3 : 1; 3459 uint64_t nsr_sl3 : 1; 3460 uint64_t esr_sl3 : 2; 3461 uint64_t iptr_o0 : 1; 3462 uint64_t iptr_o1 : 1; 3463 uint64_t iptr_o2 : 1; 3464 uint64_t iptr_o3 : 1; 3465 uint64_t reserved_20_23 : 4; 3466 uint64_t o0_csrm : 1; 3467 uint64_t o1_csrm : 1; 3468 uint64_t o2_csrm : 1; 3469 uint64_t o3_csrm : 1; 3470 uint64_t o0_ro : 1; 3471 uint64_t o0_ns : 1; 3472 uint64_t o0_es : 2; 3473 uint64_t o1_ro : 1; 3474 uint64_t o1_ns : 1; 3475 uint64_t o1_es : 2; 3476 uint64_t o2_ro : 1; 3477 uint64_t o2_ns : 1; 3478 uint64_t o2_es : 2; 3479 uint64_t o3_ro : 1; 3480 uint64_t o3_ns : 1; 3481 uint64_t o3_es : 2; 3482 uint64_t p0_bmode : 1; 3483 uint64_t p1_bmode : 1; 3484 uint64_t p2_bmode : 1; 3485 uint64_t p3_bmode : 1; 3486 uint64_t pkt_rr : 1; 3487 uint64_t reserved_49_63 : 15; 3488#endif 3489 } s; 3490 struct cvmx_npi_output_control_cn30xx 3491 { 3492#if __BYTE_ORDER == __BIG_ENDIAN 3493 uint64_t reserved_45_63 : 19; 3494 uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be 3495 updated with the number of bytes in the packet 3496 sent, when '0' the register will have a value 3497 of '1' added. */ 3498 uint64_t reserved_32_43 : 12; 3499 uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */ 3500 uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */ 3501 uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */ 3502 uint64_t reserved_25_27 : 3; 3503 uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3504 comes from the DPTR[63:60] in the scatter-list pair, 3505 and the RO, NS, ES values come from the O0_ES, 3506 O0_NS, O0_RO. When '0' the RO == DPTR[60], 3507 NS == DPTR[61], ES == DPTR[63:62], the address the 3508 packet will be written to is ADDR[63:60] == 3509 O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */ 3510 uint64_t reserved_17_23 : 7; 3511 uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data 3512 for output-0. */ 3513 uint64_t reserved_4_15 : 12; 3514 uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */ 3515 uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */ 3516 uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */ 3517#else 3518 uint64_t ror_sl0 : 1; 3519 uint64_t nsr_sl0 : 1; 3520 uint64_t esr_sl0 : 2; 3521 uint64_t reserved_4_15 : 12; 3522 uint64_t iptr_o0 : 1; 3523 uint64_t reserved_17_23 : 7; 3524 uint64_t o0_csrm : 1; 3525 uint64_t reserved_25_27 : 3; 3526 uint64_t o0_ro : 1; 3527 uint64_t o0_ns : 1; 3528 uint64_t o0_es : 2; 3529 uint64_t reserved_32_43 : 12; 3530 uint64_t p0_bmode : 1; 3531 uint64_t reserved_45_63 : 19; 3532#endif 3533 } cn30xx; 3534 struct cvmx_npi_output_control_cn31xx 3535 { 3536#if __BYTE_ORDER == __BIG_ENDIAN 3537 uint64_t reserved_46_63 : 18; 3538 uint64_t p1_bmode : 1; /**< When set '1' PCI_PKTS_SENT1 register will be 3539 updated with the number of bytes in the packet 3540 sent, when '0' the register will have a value 3541 of '1' added. */ 3542 uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be 3543 updated with the number of bytes in the packet 3544 sent, when '0' the register will have a value 3545 of '1' added. */ 3546 uint64_t reserved_36_43 : 8; 3547 uint64_t o1_es : 2; /**< Endian Swap for Output1 Data. */ 3548 uint64_t o1_ns : 1; /**< NoSnoop Enable for Output1 Data. */ 3549 uint64_t o1_ro : 1; /**< Relaxed Ordering Enable for Output1 Data. */ 3550 uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */ 3551 uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */ 3552 uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */ 3553 uint64_t reserved_26_27 : 2; 3554 uint64_t o1_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3555 comes from the DPTR[63:60] in the scatter-list pair, 3556 and the RO, NS, ES values come from the O1_ES, 3557 O1_NS, O1_RO. When '0' the RO == DPTR[60], 3558 NS == DPTR[61], ES == DPTR[63:62], the address the 3559 packet will be written to is ADDR[63:60] == 3560 O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */ 3561 uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3562 comes from the DPTR[63:60] in the scatter-list pair, 3563 and the RO, NS, ES values come from the O0_ES, 3564 O0_NS, O0_RO. When '0' the RO == DPTR[60], 3565 NS == DPTR[61], ES == DPTR[63:62], the address the 3566 packet will be written to is ADDR[63:60] == 3567 O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */ 3568 uint64_t reserved_18_23 : 6; 3569 uint64_t iptr_o1 : 1; /**< Uses the Info-Pointer to store length and data 3570 for output-1. */ 3571 uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data 3572 for output-0. */ 3573 uint64_t reserved_8_15 : 8; 3574 uint64_t esr_sl1 : 2; /**< The Endian-Swap-Mode for Slist1 reads. */ 3575 uint64_t nsr_sl1 : 1; /**< Enables '1' NoSnoop for Slist1 reads. */ 3576 uint64_t ror_sl1 : 1; /**< Enables '1' Relaxed Ordering for Slist1 reads. */ 3577 uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */ 3578 uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */ 3579 uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */ 3580#else 3581 uint64_t ror_sl0 : 1; 3582 uint64_t nsr_sl0 : 1; 3583 uint64_t esr_sl0 : 2; 3584 uint64_t ror_sl1 : 1; 3585 uint64_t nsr_sl1 : 1; 3586 uint64_t esr_sl1 : 2; 3587 uint64_t reserved_8_15 : 8; 3588 uint64_t iptr_o0 : 1; 3589 uint64_t iptr_o1 : 1; 3590 uint64_t reserved_18_23 : 6; 3591 uint64_t o0_csrm : 1; 3592 uint64_t o1_csrm : 1; 3593 uint64_t reserved_26_27 : 2; 3594 uint64_t o0_ro : 1; 3595 uint64_t o0_ns : 1; 3596 uint64_t o0_es : 2; 3597 uint64_t o1_ro : 1; 3598 uint64_t o1_ns : 1; 3599 uint64_t o1_es : 2; 3600 uint64_t reserved_36_43 : 8; 3601 uint64_t p0_bmode : 1; 3602 uint64_t p1_bmode : 1; 3603 uint64_t reserved_46_63 : 18; 3604#endif 3605 } cn31xx; 3606 struct cvmx_npi_output_control_s cn38xx; 3607 struct cvmx_npi_output_control_cn38xxp2 3608 { 3609#if __BYTE_ORDER == __BIG_ENDIAN 3610 uint64_t reserved_48_63 : 16; 3611 uint64_t p3_bmode : 1; /**< When set '1' PCI_PKTS_SENT3 register will be 3612 updated with the number of bytes in the packet 3613 sent, when '0' the register will have a value 3614 of '1' added. */ 3615 uint64_t p2_bmode : 1; /**< When set '1' PCI_PKTS_SENT2 register will be 3616 updated with the number of bytes in the packet 3617 sent, when '0' the register will have a value 3618 of '1' added. */ 3619 uint64_t p1_bmode : 1; /**< When set '1' PCI_PKTS_SENT1 register will be 3620 updated with the number of bytes in the packet 3621 sent, when '0' the register will have a value 3622 of '1' added. */ 3623 uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be 3624 updated with the number of bytes in the packet 3625 sent, when '0' the register will have a value 3626 of '1' added. */ 3627 uint64_t o3_es : 2; /**< Endian Swap for Output3 Data. */ 3628 uint64_t o3_ns : 1; /**< NoSnoop Enable for Output3 Data. */ 3629 uint64_t o3_ro : 1; /**< Relaxed Ordering Enable for Output3 Data. */ 3630 uint64_t o2_es : 2; /**< Endian Swap for Output2 Data. */ 3631 uint64_t o2_ns : 1; /**< NoSnoop Enable for Output2 Data. */ 3632 uint64_t o2_ro : 1; /**< Relaxed Ordering Enable for Output2 Data. */ 3633 uint64_t o1_es : 2; /**< Endian Swap for Output1 Data. */ 3634 uint64_t o1_ns : 1; /**< NoSnoop Enable for Output1 Data. */ 3635 uint64_t o1_ro : 1; /**< Relaxed Ordering Enable for Output1 Data. */ 3636 uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */ 3637 uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */ 3638 uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */ 3639 uint64_t o3_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3640 comes from the DPTR[63:60] in the scatter-list pair, 3641 and the RO, NS, ES values come from the O3_ES, 3642 O3_NS, O3_RO. When '0' the RO == DPTR[60], 3643 NS == DPTR[61], ES == DPTR[63:62], the address the 3644 packet will be written to is ADDR[63:60] == 3645 O3_ES[1:0], O3_NS, O3_RO. For Output Port-3. */ 3646 uint64_t o2_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3647 comes from the DPTR[63:60] in the scatter-list pair, 3648 and the RO, NS, ES values come from the O2_ES, 3649 O2_NS, O2_RO. When '0' the RO == DPTR[60], 3650 NS == DPTR[61], ES == DPTR[63:62], the address the 3651 packet will be written to is ADDR[63:60] == 3652 O2_ES[1:0], O2_NS, O2_RO. For Output Port-2. */ 3653 uint64_t o1_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3654 comes from the DPTR[63:60] in the scatter-list pair, 3655 and the RO, NS, ES values come from the O1_ES, 3656 O1_NS, O1_RO. When '0' the RO == DPTR[60], 3657 NS == DPTR[61], ES == DPTR[63:62], the address the 3658 packet will be written to is ADDR[63:60] == 3659 O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */ 3660 uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3661 comes from the DPTR[63:60] in the scatter-list pair, 3662 and the RO, NS, ES values come from the O0_ES, 3663 O0_NS, O0_RO. When '0' the RO == DPTR[60], 3664 NS == DPTR[61], ES == DPTR[63:62], the address the 3665 packet will be written to is ADDR[63:60] == 3666 O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */ 3667 uint64_t reserved_20_23 : 4; 3668 uint64_t iptr_o3 : 1; /**< Uses the Info-Pointer to store length and data 3669 for output-3. */ 3670 uint64_t iptr_o2 : 1; /**< Uses the Info-Pointer to store length and data 3671 for output-2. */ 3672 uint64_t iptr_o1 : 1; /**< Uses the Info-Pointer to store length and data 3673 for output-1. */ 3674 uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data 3675 for output-0. */ 3676 uint64_t esr_sl3 : 2; /**< The Endian-Swap-Mode for Slist3 reads. */ 3677 uint64_t nsr_sl3 : 1; /**< Enables '1' NoSnoop for Slist3 reads. */ 3678 uint64_t ror_sl3 : 1; /**< Enables '1' Relaxed Ordering for Slist3 reads. */ 3679 uint64_t esr_sl2 : 2; /**< The Endian-Swap-Mode for Slist2 reads. */ 3680 uint64_t nsr_sl2 : 1; /**< Enables '1' NoSnoop for Slist2 reads. */ 3681 uint64_t ror_sl2 : 1; /**< Enables '1' Relaxed Ordering for Slist2 reads. */ 3682 uint64_t esr_sl1 : 2; /**< The Endian-Swap-Mode for Slist1 reads. */ 3683 uint64_t nsr_sl1 : 1; /**< Enables '1' NoSnoop for Slist1 reads. */ 3684 uint64_t ror_sl1 : 1; /**< Enables '1' Relaxed Ordering for Slist1 reads. */ 3685 uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */ 3686 uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */ 3687 uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */ 3688#else 3689 uint64_t ror_sl0 : 1; 3690 uint64_t nsr_sl0 : 1; 3691 uint64_t esr_sl0 : 2; 3692 uint64_t ror_sl1 : 1; 3693 uint64_t nsr_sl1 : 1; 3694 uint64_t esr_sl1 : 2; 3695 uint64_t ror_sl2 : 1; 3696 uint64_t nsr_sl2 : 1; 3697 uint64_t esr_sl2 : 2; 3698 uint64_t ror_sl3 : 1; 3699 uint64_t nsr_sl3 : 1; 3700 uint64_t esr_sl3 : 2; 3701 uint64_t iptr_o0 : 1; 3702 uint64_t iptr_o1 : 1; 3703 uint64_t iptr_o2 : 1; 3704 uint64_t iptr_o3 : 1; 3705 uint64_t reserved_20_23 : 4; 3706 uint64_t o0_csrm : 1; 3707 uint64_t o1_csrm : 1; 3708 uint64_t o2_csrm : 1; 3709 uint64_t o3_csrm : 1; 3710 uint64_t o0_ro : 1; 3711 uint64_t o0_ns : 1; 3712 uint64_t o0_es : 2; 3713 uint64_t o1_ro : 1; 3714 uint64_t o1_ns : 1; 3715 uint64_t o1_es : 2; 3716 uint64_t o2_ro : 1; 3717 uint64_t o2_ns : 1; 3718 uint64_t o2_es : 2; 3719 uint64_t o3_ro : 1; 3720 uint64_t o3_ns : 1; 3721 uint64_t o3_es : 2; 3722 uint64_t p0_bmode : 1; 3723 uint64_t p1_bmode : 1; 3724 uint64_t p2_bmode : 1; 3725 uint64_t p3_bmode : 1; 3726 uint64_t reserved_48_63 : 16; 3727#endif 3728 } cn38xxp2; 3729 struct cvmx_npi_output_control_cn50xx 3730 { 3731#if __BYTE_ORDER == __BIG_ENDIAN 3732 uint64_t reserved_49_63 : 15; 3733 uint64_t pkt_rr : 1; /**< When set '1' the output packet selection will be 3734 made with a Round Robin arbitration. When '0' 3735 the output packet port is fixed in priority, 3736 where the lower port number has higher priority. 3737 PASS2 Field */ 3738 uint64_t reserved_46_47 : 2; 3739 uint64_t p1_bmode : 1; /**< When set '1' PCI_PKTS_SENT1 register will be 3740 updated with the number of bytes in the packet 3741 sent, when '0' the register will have a value 3742 of '1' added. */ 3743 uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be 3744 updated with the number of bytes in the packet 3745 sent, when '0' the register will have a value 3746 of '1' added. */ 3747 uint64_t reserved_36_43 : 8; 3748 uint64_t o1_es : 2; /**< Endian Swap for Output1 Data. */ 3749 uint64_t o1_ns : 1; /**< NoSnoop Enable for Output1 Data. */ 3750 uint64_t o1_ro : 1; /**< Relaxed Ordering Enable for Output1 Data. */ 3751 uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */ 3752 uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */ 3753 uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */ 3754 uint64_t reserved_26_27 : 2; 3755 uint64_t o1_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3756 comes from the DPTR[63:60] in the scatter-list pair, 3757 and the RO, NS, ES values come from the O1_ES, 3758 O1_NS, O1_RO. When '0' the RO == DPTR[60], 3759 NS == DPTR[61], ES == DPTR[63:62], the address the 3760 packet will be written to is ADDR[63:60] == 3761 O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */ 3762 uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3763 comes from the DPTR[63:60] in the scatter-list pair, 3764 and the RO, NS, ES values come from the O0_ES, 3765 O0_NS, O0_RO. When '0' the RO == DPTR[60], 3766 NS == DPTR[61], ES == DPTR[63:62], the address the 3767 packet will be written to is ADDR[63:60] == 3768 O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */ 3769 uint64_t reserved_18_23 : 6; 3770 uint64_t iptr_o1 : 1; /**< Uses the Info-Pointer to store length and data 3771 for output-1. */ 3772 uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data 3773 for output-0. */ 3774 uint64_t reserved_8_15 : 8; 3775 uint64_t esr_sl1 : 2; /**< The Endian-Swap-Mode for Slist1 reads. */ 3776 uint64_t nsr_sl1 : 1; /**< Enables '1' NoSnoop for Slist1 reads. */ 3777 uint64_t ror_sl1 : 1; /**< Enables '1' Relaxed Ordering for Slist1 reads. */ 3778 uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */ 3779 uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */ 3780 uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */ 3781#else 3782 uint64_t ror_sl0 : 1; 3783 uint64_t nsr_sl0 : 1; 3784 uint64_t esr_sl0 : 2; 3785 uint64_t ror_sl1 : 1; 3786 uint64_t nsr_sl1 : 1; 3787 uint64_t esr_sl1 : 2; 3788 uint64_t reserved_8_15 : 8; 3789 uint64_t iptr_o0 : 1; 3790 uint64_t iptr_o1 : 1; 3791 uint64_t reserved_18_23 : 6; 3792 uint64_t o0_csrm : 1; 3793 uint64_t o1_csrm : 1; 3794 uint64_t reserved_26_27 : 2; 3795 uint64_t o0_ro : 1; 3796 uint64_t o0_ns : 1; 3797 uint64_t o0_es : 2; 3798 uint64_t o1_ro : 1; 3799 uint64_t o1_ns : 1; 3800 uint64_t o1_es : 2; 3801 uint64_t reserved_36_43 : 8; 3802 uint64_t p0_bmode : 1; 3803 uint64_t p1_bmode : 1; 3804 uint64_t reserved_46_47 : 2; 3805 uint64_t pkt_rr : 1; 3806 uint64_t reserved_49_63 : 15; 3807#endif 3808 } cn50xx; 3809 struct cvmx_npi_output_control_s cn58xx; 3810 struct cvmx_npi_output_control_s cn58xxp1; 3811}; 3812typedef union cvmx_npi_output_control cvmx_npi_output_control_t; 3813 3814/** 3815 * cvmx_npi_p#_dbpair_addr 3816 * 3817 * NPI_P0_DBPAIR_ADDR = NPI's Port-0 DATA-BUFFER Pair Next Read Address. 3818 * 3819 * Contains the next address to read for Port's-0 Data/Buffer Pair. 3820 */ 3821union cvmx_npi_px_dbpair_addr 3822{ 3823 uint64_t u64; 3824 struct cvmx_npi_px_dbpair_addr_s 3825 { 3826#if __BYTE_ORDER == __BIG_ENDIAN 3827 uint64_t reserved_63_63 : 1; 3828 uint64_t state : 2; /**< POS state machine vector. Used to tell when NADDR 3829 is valid (when STATE == 0). */ 3830 uint64_t naddr : 61; /**< Bits [63:3] of the next Data-Info Pair to read. 3831 Value is only valid when STATE == 0. */ 3832#else 3833 uint64_t naddr : 61; 3834 uint64_t state : 2; 3835 uint64_t reserved_63_63 : 1; 3836#endif 3837 } s; 3838 struct cvmx_npi_px_dbpair_addr_s cn30xx; 3839 struct cvmx_npi_px_dbpair_addr_s cn31xx; 3840 struct cvmx_npi_px_dbpair_addr_s cn38xx; 3841 struct cvmx_npi_px_dbpair_addr_s cn38xxp2; 3842 struct cvmx_npi_px_dbpair_addr_s cn50xx; 3843 struct cvmx_npi_px_dbpair_addr_s cn58xx; 3844 struct cvmx_npi_px_dbpair_addr_s cn58xxp1; 3845}; 3846typedef union cvmx_npi_px_dbpair_addr cvmx_npi_px_dbpair_addr_t; 3847 3848/** 3849 * cvmx_npi_p#_instr_addr 3850 * 3851 * NPI_P0_INSTR_ADDR = NPI's Port-0 Instruction Next Read Address. 3852 * 3853 * Contains the next address to read for Port's-0 Instructions. 3854 */ 3855union cvmx_npi_px_instr_addr 3856{ 3857 uint64_t u64; 3858 struct cvmx_npi_px_instr_addr_s 3859 { 3860#if __BYTE_ORDER == __BIG_ENDIAN 3861 uint64_t state : 3; /**< Gather engine state vector. Used to tell when 3862 NADDR is valid (when STATE == 0). */ 3863 uint64_t naddr : 61; /**< Bits [63:3] of the next Instruction to read. 3864 Value is only valid when STATE == 0. */ 3865#else 3866 uint64_t naddr : 61; 3867 uint64_t state : 3; 3868#endif 3869 } s; 3870 struct cvmx_npi_px_instr_addr_s cn30xx; 3871 struct cvmx_npi_px_instr_addr_s cn31xx; 3872 struct cvmx_npi_px_instr_addr_s cn38xx; 3873 struct cvmx_npi_px_instr_addr_s cn38xxp2; 3874 struct cvmx_npi_px_instr_addr_s cn50xx; 3875 struct cvmx_npi_px_instr_addr_s cn58xx; 3876 struct cvmx_npi_px_instr_addr_s cn58xxp1; 3877}; 3878typedef union cvmx_npi_px_instr_addr cvmx_npi_px_instr_addr_t; 3879 3880/** 3881 * cvmx_npi_p#_instr_cnts 3882 * 3883 * NPI_P0_INSTR_CNTS = NPI's Port-0 Instruction Counts For Packets In. 3884 * 3885 * Used to determine the number of instruction in the NPI and to be fetched for Input-Packets. 3886 */ 3887union cvmx_npi_px_instr_cnts 3888{ 3889 uint64_t u64; 3890 struct cvmx_npi_px_instr_cnts_s 3891 { 3892#if __BYTE_ORDER == __BIG_ENDIAN 3893 uint64_t reserved_38_63 : 26; 3894 uint64_t fcnt : 6; /**< Number entries in the Instruction FIFO. */ 3895 uint64_t avail : 32; /**< Doorbell count to be read. */ 3896#else 3897 uint64_t avail : 32; 3898 uint64_t fcnt : 6; 3899 uint64_t reserved_38_63 : 26; 3900#endif 3901 } s; 3902 struct cvmx_npi_px_instr_cnts_s cn30xx; 3903 struct cvmx_npi_px_instr_cnts_s cn31xx; 3904 struct cvmx_npi_px_instr_cnts_s cn38xx; 3905 struct cvmx_npi_px_instr_cnts_s cn38xxp2; 3906 struct cvmx_npi_px_instr_cnts_s cn50xx; 3907 struct cvmx_npi_px_instr_cnts_s cn58xx; 3908 struct cvmx_npi_px_instr_cnts_s cn58xxp1; 3909}; 3910typedef union cvmx_npi_px_instr_cnts cvmx_npi_px_instr_cnts_t; 3911 3912/** 3913 * cvmx_npi_p#_pair_cnts 3914 * 3915 * NPI_P0_PAIR_CNTS = NPI's Port-0 Instruction Counts For Packets Out. 3916 * 3917 * Used to determine the number of instruction in the NPI and to be fetched for Output-Packets. 3918 */ 3919union cvmx_npi_px_pair_cnts 3920{ 3921 uint64_t u64; 3922 struct cvmx_npi_px_pair_cnts_s 3923 { 3924#if __BYTE_ORDER == __BIG_ENDIAN 3925 uint64_t reserved_37_63 : 27; 3926 uint64_t fcnt : 5; /**< 16 - number entries in the D/I Pair FIFO. */ 3927 uint64_t avail : 32; /**< Doorbell count to be read. */ 3928#else 3929 uint64_t avail : 32; 3930 uint64_t fcnt : 5; 3931 uint64_t reserved_37_63 : 27; 3932#endif 3933 } s; 3934 struct cvmx_npi_px_pair_cnts_s cn30xx; 3935 struct cvmx_npi_px_pair_cnts_s cn31xx; 3936 struct cvmx_npi_px_pair_cnts_s cn38xx; 3937 struct cvmx_npi_px_pair_cnts_s cn38xxp2; 3938 struct cvmx_npi_px_pair_cnts_s cn50xx; 3939 struct cvmx_npi_px_pair_cnts_s cn58xx; 3940 struct cvmx_npi_px_pair_cnts_s cn58xxp1; 3941}; 3942typedef union cvmx_npi_px_pair_cnts cvmx_npi_px_pair_cnts_t; 3943 3944/** 3945 * cvmx_npi_pci_burst_size 3946 * 3947 * NPI_PCI_BURST_SIZE = NPI PCI Burst Size Register 3948 * 3949 * Control the number of words the NPI will attempt to read / write to/from the PCI. 3950 */ 3951union cvmx_npi_pci_burst_size 3952{ 3953 uint64_t u64; 3954 struct cvmx_npi_pci_burst_size_s 3955 { 3956#if __BYTE_ORDER == __BIG_ENDIAN 3957 uint64_t reserved_14_63 : 50; 3958 uint64_t wr_brst : 7; /**< The number of 8B words to write to PCI in any one 3959 write operation. A zero is equal to 128. This 3960 value is used the packet reads and is clamped at 3961 a max of 112 for dma writes. */ 3962 uint64_t rd_brst : 7; /**< Number of 8B words to read from PCI in any one 3963 read operation. Legal values are 1 to 127, where 3964 a 0 will be treated as a 1. 3965 "For reading of packet data value is limited to 64 3966 in PASS-2." 3967 This value does not control the size of a read 3968 caused by an IOBDMA from a PP. */ 3969#else 3970 uint64_t rd_brst : 7; 3971 uint64_t wr_brst : 7; 3972 uint64_t reserved_14_63 : 50; 3973#endif 3974 } s; 3975 struct cvmx_npi_pci_burst_size_s cn30xx; 3976 struct cvmx_npi_pci_burst_size_s cn31xx; 3977 struct cvmx_npi_pci_burst_size_s cn38xx; 3978 struct cvmx_npi_pci_burst_size_s cn38xxp2; 3979 struct cvmx_npi_pci_burst_size_s cn50xx; 3980 struct cvmx_npi_pci_burst_size_s cn58xx; 3981 struct cvmx_npi_pci_burst_size_s cn58xxp1; 3982}; 3983typedef union cvmx_npi_pci_burst_size cvmx_npi_pci_burst_size_t; 3984 3985/** 3986 * cvmx_npi_pci_int_arb_cfg 3987 * 3988 * NPI_PCI_INT_ARB_CFG = Configuration For PCI Arbiter 3989 * 3990 * Controls operation of the Internal PCI Arbiter. This register should 3991 * only be written when PRST# is asserted. NPI_PCI_INT_ARB_CFG[EN] should 3992 * only be set when Octane is a host. 3993 */ 3994union cvmx_npi_pci_int_arb_cfg 3995{ 3996 uint64_t u64; 3997 struct cvmx_npi_pci_int_arb_cfg_s 3998 { 3999#if __BYTE_ORDER == __BIG_ENDIAN 4000 uint64_t reserved_13_63 : 51; 4001 uint64_t hostmode : 1; /**< PCI Host Mode Pin (sampled for use by software). 4002 This bit reflects the sampled PCI_HOSTMODE pin. 4003 In HOST Mode, OCTEON drives the PCI_CLK_OUT and 4004 PCI initialization pattern during PCI_RST_N deassertion). */ 4005 uint64_t pci_ovr : 4; /**< PCI Host Mode Bus Speed/Type Override 4006 When in Host Mode(PCI_HOSTMODE pin =1), OCTEON acting 4007 as the PCI Central Agent, samples the PCI_PCI100, 4008 PCI_M66EN and PCI_PCIXCAP pins to determine the 4009 'sampled' PCI Bus speed and Bus Type (PCI or PCIX). 4010 (see: PCI_CNT_REG[HM_SPEED,HM_PCIX]) 4011 However, in some cases, SW may want to override the 4012 the 'sampled' PCI Bus Type/Speed, and use some 4013 SLOWER Bus frequency. 4014 The PCI_OVR field encoding represents the 'override' 4015 PCI Bus Type/Speed which will be used to generate the 4016 PCI_CLK_OUT and determines the PCI initialization pattern 4017 driven during PCI_RST_N deassertion. 4018 PCI_OVR[3]: OVERRIDE (0:DISABLE/1:ENABLE) 4019 PCI_OVR[2]: BUS TYPE(0:PCI/1:PCIX) 4020 PCI_OVR[1:0]: BUS SPEED(0:33/1:66/2:100/3:133) 4021 OVERRIDE TYPE SPEED | Override Configuration 4022 [3] [2] [1:0] | TYPE SPEED 4023 ------------------+------------------------------- 4024 0 x xx | No override(uses 'sampled' 4025 | Bus Speed(HM_SPEED) and Bus Type(HM_PCIX) 4026 1 0 00 | PCI Mode 33MHz 4027 1 0 01 | PCI Mode 66MHz 4028 1 0 10 | RESERVED (DO NOT USE) 4029 1 0 11 | RESERVED (DO NOT USE) 4030 1 1 00 | RESERVED (DO NOT USE) 4031 1 1 01 | PCIX Mode 66MHz 4032 1 1 10 | PCIX Mode 100MHz 4033 1 1 11 | PCIX Mode 133MHz 4034 NOTES: 4035 - NPI_PCI_INT_ARB_CFG[PCI_OVR] has NO EFFECT on 4036 PCI_CNT_REG[HM_SPEED,HM_PCIX] (ie: the sampled PCI Bus 4037 Type/Speed), but WILL EFFECT PCI_CTL_STATUS_2[AP_PCIX] 4038 which reflects the actual PCI Bus Type(0:PCI/1:PCIX). 4039 - Software should never 'up' configure the recommended values. 4040 In other words, if the 'sampled' Bus Type=PCI(HM_PCIX=0), 4041 then SW should NOT attempt to set TYPE[2]=1 for PCIX Mode. 4042 Likewise, if the sampled Bus Speed=66MHz(HM_SPEED=01), 4043 then SW should NOT attempt to 'speed up' the bus [ie: 4044 SPEED[1:0]=10(100MHz)]. 4045 - If PCI_OVR<3> is set prior to PCI reset de-assertion 4046 in host mode, NPI_PCI_INT_ARB_CFG[PCI_OVR] 4047 indicates the Bus Type/Speed that OCTEON drove on the 4048 DEVSEL/STOP/TRDY pins during reset de-assertion. (user 4049 should then ignore the 'sampled' Bus Type/Speed 4050 contained in the PCI_CNT_REG[HM_PCIX, HM_SPEED]) fields. 4051 - If PCI_OVR<3> is clear prior to PCI reset de-assertion 4052 in host mode, PCI_CNT_REG[HM_PCIX,HM_SPEED]) 4053 indicates the Bus Type/Speed that OCTEON drove on the 4054 DEVSEL/STOP/TRDY pins during reset de-assertion. */ 4055 uint64_t reserved_5_7 : 3; 4056 uint64_t en : 1; /**< Internal arbiter enable. */ 4057 uint64_t park_mod : 1; /**< Bus park mode. 0=park on last, 1=park on device. */ 4058 uint64_t park_dev : 3; /**< Bus park device. 0-3 External device, 4 = Octane. */ 4059#else 4060 uint64_t park_dev : 3; 4061 uint64_t park_mod : 1; 4062 uint64_t en : 1; 4063 uint64_t reserved_5_7 : 3; 4064 uint64_t pci_ovr : 4; 4065 uint64_t hostmode : 1; 4066 uint64_t reserved_13_63 : 51; 4067#endif 4068 } s; 4069 struct cvmx_npi_pci_int_arb_cfg_cn30xx 4070 { 4071#if __BYTE_ORDER == __BIG_ENDIAN 4072 uint64_t reserved_5_63 : 59; 4073 uint64_t en : 1; /**< Internal arbiter enable. */ 4074 uint64_t park_mod : 1; /**< Bus park mode. 0=park on last, 1=park on device. */ 4075 uint64_t park_dev : 3; /**< Bus park device. 0-3 External device, 4 = Octane. */ 4076#else 4077 uint64_t park_dev : 3; 4078 uint64_t park_mod : 1; 4079 uint64_t en : 1; 4080 uint64_t reserved_5_63 : 59; 4081#endif 4082 } cn30xx; 4083 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx; 4084 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx; 4085 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2; 4086 struct cvmx_npi_pci_int_arb_cfg_s cn50xx; 4087 struct cvmx_npi_pci_int_arb_cfg_s cn58xx; 4088 struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1; 4089}; 4090typedef union cvmx_npi_pci_int_arb_cfg cvmx_npi_pci_int_arb_cfg_t; 4091 4092/** 4093 * cvmx_npi_pci_read_cmd 4094 * 4095 * NPI_PCI_READ_CMD = NPI PCI Read Command Register 4096 * 4097 * Controls the type of read command sent. 4098 * Writes to this register are not ordered with writes/reads to the PCI Memory space. 4099 * To ensure that a write has completed the user must read the register before 4100 * making an access(i.e. PCI memory space) that requires the value of this register to be updated. 4101 * Also any previously issued reads/writes to PCI memory space, still stored in the outbound 4102 * FIFO will use the value of this register after it has been updated. 4103 */ 4104union cvmx_npi_pci_read_cmd 4105{ 4106 uint64_t u64; 4107 struct cvmx_npi_pci_read_cmd_s 4108 { 4109#if __BYTE_ORDER == __BIG_ENDIAN 4110 uint64_t reserved_11_63 : 53; 4111 uint64_t cmd_size : 11; /**< Number bytes to be read is equal to or exceeds this 4112 size will cause the PCI in PCI mode to use a 4113 Memory-Read-Multiple. This register has a value 4114 from 8 to 2048. A value of 0-7 will be treated as 4115 a value of 2048. */ 4116#else 4117 uint64_t cmd_size : 11; 4118 uint64_t reserved_11_63 : 53; 4119#endif 4120 } s; 4121 struct cvmx_npi_pci_read_cmd_s cn30xx; 4122 struct cvmx_npi_pci_read_cmd_s cn31xx; 4123 struct cvmx_npi_pci_read_cmd_s cn38xx; 4124 struct cvmx_npi_pci_read_cmd_s cn38xxp2; 4125 struct cvmx_npi_pci_read_cmd_s cn50xx; 4126 struct cvmx_npi_pci_read_cmd_s cn58xx; 4127 struct cvmx_npi_pci_read_cmd_s cn58xxp1; 4128}; 4129typedef union cvmx_npi_pci_read_cmd cvmx_npi_pci_read_cmd_t; 4130 4131/** 4132 * cvmx_npi_port32_instr_hdr 4133 * 4134 * NPI_PORT32_INSTR_HDR = NPI Port 32 Instruction Header 4135 * 4136 * Contains bits [62:42] of the Instruction Header for port 32. 4137 */ 4138union cvmx_npi_port32_instr_hdr 4139{ 4140 uint64_t u64; 4141 struct cvmx_npi_port32_instr_hdr_s 4142 { 4143#if __BYTE_ORDER == __BIG_ENDIAN 4144 uint64_t reserved_44_63 : 20; 4145 uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */ 4146 uint64_t rsv_f : 5; /**< Reserved */ 4147 uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */ 4148 uint64_t rsv_e : 1; /**< Reserved */ 4149 uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */ 4150 uint64_t rsv_d : 6; /**< Reserved */ 4151 uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent 4152 as part of the packet data, regardless of the 4153 value of bit [63] of the instruction header. 4154 USE_IHDR must be set whenever PBP is set. */ 4155 uint64_t rsv_c : 5; /**< Reserved */ 4156 uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet 4157 is not raw and PBP is not set. */ 4158 uint64_t rsv_b : 1; /**< Reserved 4159 instruction header sent to IPD. */ 4160 uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet 4161 is not raw and PBP is not set. */ 4162 uint64_t rsv_a : 6; /**< Reserved */ 4163#else 4164 uint64_t rsv_a : 6; 4165 uint64_t skp_len : 7; 4166 uint64_t rsv_b : 1; 4167 uint64_t par_mode : 2; 4168 uint64_t rsv_c : 5; 4169 uint64_t use_ihdr : 1; 4170 uint64_t rsv_d : 6; 4171 uint64_t rskp_len : 7; 4172 uint64_t rsv_e : 1; 4173 uint64_t rparmode : 2; 4174 uint64_t rsv_f : 5; 4175 uint64_t pbp : 1; 4176 uint64_t reserved_44_63 : 20; 4177#endif 4178 } s; 4179 struct cvmx_npi_port32_instr_hdr_s cn30xx; 4180 struct cvmx_npi_port32_instr_hdr_s cn31xx; 4181 struct cvmx_npi_port32_instr_hdr_s cn38xx; 4182 struct cvmx_npi_port32_instr_hdr_s cn38xxp2; 4183 struct cvmx_npi_port32_instr_hdr_s cn50xx; 4184 struct cvmx_npi_port32_instr_hdr_s cn58xx; 4185 struct cvmx_npi_port32_instr_hdr_s cn58xxp1; 4186}; 4187typedef union cvmx_npi_port32_instr_hdr cvmx_npi_port32_instr_hdr_t; 4188 4189/** 4190 * cvmx_npi_port33_instr_hdr 4191 * 4192 * NPI_PORT33_INSTR_HDR = NPI Port 33 Instruction Header 4193 * 4194 * Contains bits [62:42] of the Instruction Header for port 33. 4195 */ 4196union cvmx_npi_port33_instr_hdr 4197{ 4198 uint64_t u64; 4199 struct cvmx_npi_port33_instr_hdr_s 4200 { 4201#if __BYTE_ORDER == __BIG_ENDIAN 4202 uint64_t reserved_44_63 : 20; 4203 uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */ 4204 uint64_t rsv_f : 5; /**< Reserved */ 4205 uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */ 4206 uint64_t rsv_e : 1; /**< Reserved */ 4207 uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */ 4208 uint64_t rsv_d : 6; /**< Reserved */ 4209 uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent 4210 as part of the packet data, regardless of the 4211 value of bit [63] of the instruction header. 4212 USE_IHDR must be set whenever PBP is set. */ 4213 uint64_t rsv_c : 5; /**< Reserved */ 4214 uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet 4215 is not raw and PBP is not set. */ 4216 uint64_t rsv_b : 1; /**< Reserved 4217 instruction header sent to IPD. */ 4218 uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet 4219 is not raw and PBP is not set. */ 4220 uint64_t rsv_a : 6; /**< Reserved */ 4221#else 4222 uint64_t rsv_a : 6; 4223 uint64_t skp_len : 7; 4224 uint64_t rsv_b : 1; 4225 uint64_t par_mode : 2; 4226 uint64_t rsv_c : 5; 4227 uint64_t use_ihdr : 1; 4228 uint64_t rsv_d : 6; 4229 uint64_t rskp_len : 7; 4230 uint64_t rsv_e : 1; 4231 uint64_t rparmode : 2; 4232 uint64_t rsv_f : 5; 4233 uint64_t pbp : 1; 4234 uint64_t reserved_44_63 : 20; 4235#endif 4236 } s; 4237 struct cvmx_npi_port33_instr_hdr_s cn31xx; 4238 struct cvmx_npi_port33_instr_hdr_s cn38xx; 4239 struct cvmx_npi_port33_instr_hdr_s cn38xxp2; 4240 struct cvmx_npi_port33_instr_hdr_s cn50xx; 4241 struct cvmx_npi_port33_instr_hdr_s cn58xx; 4242 struct cvmx_npi_port33_instr_hdr_s cn58xxp1; 4243}; 4244typedef union cvmx_npi_port33_instr_hdr cvmx_npi_port33_instr_hdr_t; 4245 4246/** 4247 * cvmx_npi_port34_instr_hdr 4248 * 4249 * NPI_PORT34_INSTR_HDR = NPI Port 34 Instruction Header 4250 * 4251 * Contains bits [62:42] of the Instruction Header for port 34. Added for PASS-2. 4252 */ 4253union cvmx_npi_port34_instr_hdr 4254{ 4255 uint64_t u64; 4256 struct cvmx_npi_port34_instr_hdr_s 4257 { 4258#if __BYTE_ORDER == __BIG_ENDIAN 4259 uint64_t reserved_44_63 : 20; 4260 uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */ 4261 uint64_t rsv_f : 5; /**< Reserved */ 4262 uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */ 4263 uint64_t rsv_e : 1; /**< Reserved */ 4264 uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */ 4265 uint64_t rsv_d : 6; /**< Reserved */ 4266 uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent 4267 as part of the packet data, regardless of the 4268 value of bit [63] of the instruction header. 4269 USE_IHDR must be set whenever PBP is set. */ 4270 uint64_t rsv_c : 5; /**< Reserved */ 4271 uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet 4272 is not raw and PBP is not set. */ 4273 uint64_t rsv_b : 1; /**< Reserved 4274 instruction header sent to IPD. */ 4275 uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet 4276 is not raw and PBP is not set. */ 4277 uint64_t rsv_a : 6; /**< Reserved */ 4278#else 4279 uint64_t rsv_a : 6; 4280 uint64_t skp_len : 7; 4281 uint64_t rsv_b : 1; 4282 uint64_t par_mode : 2; 4283 uint64_t rsv_c : 5; 4284 uint64_t use_ihdr : 1; 4285 uint64_t rsv_d : 6; 4286 uint64_t rskp_len : 7; 4287 uint64_t rsv_e : 1; 4288 uint64_t rparmode : 2; 4289 uint64_t rsv_f : 5; 4290 uint64_t pbp : 1; 4291 uint64_t reserved_44_63 : 20; 4292#endif 4293 } s; 4294 struct cvmx_npi_port34_instr_hdr_s cn38xx; 4295 struct cvmx_npi_port34_instr_hdr_s cn38xxp2; 4296 struct cvmx_npi_port34_instr_hdr_s cn58xx; 4297 struct cvmx_npi_port34_instr_hdr_s cn58xxp1; 4298}; 4299typedef union cvmx_npi_port34_instr_hdr cvmx_npi_port34_instr_hdr_t; 4300 4301/** 4302 * cvmx_npi_port35_instr_hdr 4303 * 4304 * NPI_PORT35_INSTR_HDR = NPI Port 35 Instruction Header 4305 * 4306 * Contains bits [62:42] of the Instruction Header for port 35. Added for PASS-2. 4307 */ 4308union cvmx_npi_port35_instr_hdr 4309{ 4310 uint64_t u64; 4311 struct cvmx_npi_port35_instr_hdr_s 4312 { 4313#if __BYTE_ORDER == __BIG_ENDIAN 4314 uint64_t reserved_44_63 : 20; 4315 uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */ 4316 uint64_t rsv_f : 5; /**< Reserved */ 4317 uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */ 4318 uint64_t rsv_e : 1; /**< Reserved */ 4319 uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */ 4320 uint64_t rsv_d : 6; /**< Reserved */ 4321 uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent 4322 as part of the packet data, regardless of the 4323 value of bit [63] of the instruction header. 4324 USE_IHDR must be set whenever PBP is set. */ 4325 uint64_t rsv_c : 5; /**< Reserved */ 4326 uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet 4327 is not raw and PBP is not set. */ 4328 uint64_t rsv_b : 1; /**< Reserved 4329 instruction header sent to IPD. */ 4330 uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet 4331 is not raw and PBP is not set. */ 4332 uint64_t rsv_a : 6; /**< Reserved */ 4333#else 4334 uint64_t rsv_a : 6; 4335 uint64_t skp_len : 7; 4336 uint64_t rsv_b : 1; 4337 uint64_t par_mode : 2; 4338 uint64_t rsv_c : 5; 4339 uint64_t use_ihdr : 1; 4340 uint64_t rsv_d : 6; 4341 uint64_t rskp_len : 7; 4342 uint64_t rsv_e : 1; 4343 uint64_t rparmode : 2; 4344 uint64_t rsv_f : 5; 4345 uint64_t pbp : 1; 4346 uint64_t reserved_44_63 : 20; 4347#endif 4348 } s; 4349 struct cvmx_npi_port35_instr_hdr_s cn38xx; 4350 struct cvmx_npi_port35_instr_hdr_s cn38xxp2; 4351 struct cvmx_npi_port35_instr_hdr_s cn58xx; 4352 struct cvmx_npi_port35_instr_hdr_s cn58xxp1; 4353}; 4354typedef union cvmx_npi_port35_instr_hdr cvmx_npi_port35_instr_hdr_t; 4355 4356/** 4357 * cvmx_npi_port_bp_control 4358 * 4359 * NPI_PORT_BP_CONTROL = Port Backpressure Control 4360 * 4361 * Enables Port Level Backpressure 4362 */ 4363union cvmx_npi_port_bp_control 4364{ 4365 uint64_t u64; 4366 struct cvmx_npi_port_bp_control_s 4367 { 4368#if __BYTE_ORDER == __BIG_ENDIAN 4369 uint64_t reserved_8_63 : 56; 4370 uint64_t bp_on : 4; /**< Port 35-32 port level backpressure applied. */ 4371 uint64_t enb : 4; /**< Enables port level backpressure from the IPD. */ 4372#else 4373 uint64_t enb : 4; 4374 uint64_t bp_on : 4; 4375 uint64_t reserved_8_63 : 56; 4376#endif 4377 } s; 4378 struct cvmx_npi_port_bp_control_s cn30xx; 4379 struct cvmx_npi_port_bp_control_s cn31xx; 4380 struct cvmx_npi_port_bp_control_s cn38xx; 4381 struct cvmx_npi_port_bp_control_s cn38xxp2; 4382 struct cvmx_npi_port_bp_control_s cn50xx; 4383 struct cvmx_npi_port_bp_control_s cn58xx; 4384 struct cvmx_npi_port_bp_control_s cn58xxp1; 4385}; 4386typedef union cvmx_npi_port_bp_control cvmx_npi_port_bp_control_t; 4387 4388/** 4389 * cvmx_npi_rsl_int_blocks 4390 * 4391 * RSL_INT_BLOCKS = RSL Interrupt Blocks Register 4392 * 4393 * Reading this register will return a vector with a bit set '1' for a corresponding RSL block 4394 * that presently has an interrupt pending. The Field Description below supplies the name of the 4395 * register that software should read to find out why that intterupt bit is set. 4396 */ 4397union cvmx_npi_rsl_int_blocks 4398{ 4399 uint64_t u64; 4400 struct cvmx_npi_rsl_int_blocks_s 4401 { 4402#if __BYTE_ORDER == __BIG_ENDIAN 4403 uint64_t reserved_32_63 : 32; 4404 uint64_t rint_31 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4405 uint64_t iob : 1; /**< IOB_INT_SUM */ 4406 uint64_t reserved_28_29 : 2; 4407 uint64_t rint_27 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4408 uint64_t rint_26 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4409 uint64_t rint_25 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4410 uint64_t rint_24 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4411 uint64_t asx1 : 1; /**< ASX1_INT_REG */ 4412 uint64_t asx0 : 1; /**< ASX0_INT_REG */ 4413 uint64_t rint_21 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4414 uint64_t pip : 1; /**< PIP_INT_REG. */ 4415 uint64_t spx1 : 1; /**< SPX1_INT_REG & STX1_INT_REG */ 4416 uint64_t spx0 : 1; /**< SPX0_INT_REG & STX0_INT_REG */ 4417 uint64_t lmc : 1; /**< LMC_MEM_CFG0 */ 4418 uint64_t l2c : 1; /**< L2T_ERR & L2D_ERR */ 4419 uint64_t rint_15 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4420 uint64_t reserved_13_14 : 2; 4421 uint64_t pow : 1; /**< POW_ECC_ERR */ 4422 uint64_t tim : 1; /**< TIM_REG_ERROR */ 4423 uint64_t pko : 1; /**< PKO_REG_ERROR */ 4424 uint64_t ipd : 1; /**< IPD_INT_SUM */ 4425 uint64_t rint_8 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4426 uint64_t zip : 1; /**< ZIP_ERROR */ 4427 uint64_t dfa : 1; /**< DFA_ERR */ 4428 uint64_t fpa : 1; /**< FPA_INT_SUM */ 4429 uint64_t key : 1; /**< KEY_INT_SUM */ 4430 uint64_t npi : 1; /**< NPI_INT_SUM */ 4431 uint64_t gmx1 : 1; /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */ 4432 uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */ 4433 uint64_t mio : 1; /**< MIO_BOOT_ERR */ 4434#else 4435 uint64_t mio : 1; 4436 uint64_t gmx0 : 1; 4437 uint64_t gmx1 : 1; 4438 uint64_t npi : 1; 4439 uint64_t key : 1; 4440 uint64_t fpa : 1; 4441 uint64_t dfa : 1; 4442 uint64_t zip : 1; 4443 uint64_t rint_8 : 1; 4444 uint64_t ipd : 1; 4445 uint64_t pko : 1; 4446 uint64_t tim : 1; 4447 uint64_t pow : 1; 4448 uint64_t reserved_13_14 : 2; 4449 uint64_t rint_15 : 1; 4450 uint64_t l2c : 1; 4451 uint64_t lmc : 1; 4452 uint64_t spx0 : 1; 4453 uint64_t spx1 : 1; 4454 uint64_t pip : 1; 4455 uint64_t rint_21 : 1; 4456 uint64_t asx0 : 1; 4457 uint64_t asx1 : 1; 4458 uint64_t rint_24 : 1; 4459 uint64_t rint_25 : 1; 4460 uint64_t rint_26 : 1; 4461 uint64_t rint_27 : 1; 4462 uint64_t reserved_28_29 : 2; 4463 uint64_t iob : 1; 4464 uint64_t rint_31 : 1; 4465 uint64_t reserved_32_63 : 32; 4466#endif 4467 } s; 4468 struct cvmx_npi_rsl_int_blocks_cn30xx 4469 { 4470#if __BYTE_ORDER == __BIG_ENDIAN 4471 uint64_t reserved_32_63 : 32; 4472 uint64_t rint_31 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4473 uint64_t iob : 1; /**< IOB_INT_SUM */ 4474 uint64_t rint_29 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4475 uint64_t rint_28 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4476 uint64_t rint_27 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4477 uint64_t rint_26 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4478 uint64_t rint_25 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4479 uint64_t rint_24 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4480 uint64_t asx1 : 1; /**< ASX1_INT_REG */ 4481 uint64_t asx0 : 1; /**< ASX0_INT_REG */ 4482 uint64_t rint_21 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4483 uint64_t pip : 1; /**< PIP_INT_REG. */ 4484 uint64_t spx1 : 1; /**< SPX1_INT_REG & STX1_INT_REG */ 4485 uint64_t spx0 : 1; /**< SPX0_INT_REG & STX0_INT_REG */ 4486 uint64_t lmc : 1; /**< LMC_MEM_CFG0 */ 4487 uint64_t l2c : 1; /**< L2T_ERR & L2D_ERR */ 4488 uint64_t rint_15 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4489 uint64_t rint_14 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4490 uint64_t usb : 1; /**< USBN_INT_SUM */ 4491 uint64_t pow : 1; /**< POW_ECC_ERR */ 4492 uint64_t tim : 1; /**< TIM_REG_ERROR */ 4493 uint64_t pko : 1; /**< PKO_REG_ERROR */ 4494 uint64_t ipd : 1; /**< IPD_INT_SUM */ 4495 uint64_t rint_8 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4496 uint64_t zip : 1; /**< ZIP_ERROR */ 4497 uint64_t dfa : 1; /**< DFA_ERR */ 4498 uint64_t fpa : 1; /**< FPA_INT_SUM */ 4499 uint64_t key : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4500 uint64_t npi : 1; /**< NPI_INT_SUM */ 4501 uint64_t gmx1 : 1; /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */ 4502 uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */ 4503 uint64_t mio : 1; /**< MIO_BOOT_ERR */ 4504#else 4505 uint64_t mio : 1; 4506 uint64_t gmx0 : 1; 4507 uint64_t gmx1 : 1; 4508 uint64_t npi : 1; 4509 uint64_t key : 1; 4510 uint64_t fpa : 1; 4511 uint64_t dfa : 1; 4512 uint64_t zip : 1; 4513 uint64_t rint_8 : 1; 4514 uint64_t ipd : 1; 4515 uint64_t pko : 1; 4516 uint64_t tim : 1; 4517 uint64_t pow : 1; 4518 uint64_t usb : 1; 4519 uint64_t rint_14 : 1; 4520 uint64_t rint_15 : 1; 4521 uint64_t l2c : 1; 4522 uint64_t lmc : 1; 4523 uint64_t spx0 : 1; 4524 uint64_t spx1 : 1; 4525 uint64_t pip : 1; 4526 uint64_t rint_21 : 1; 4527 uint64_t asx0 : 1; 4528 uint64_t asx1 : 1; 4529 uint64_t rint_24 : 1; 4530 uint64_t rint_25 : 1; 4531 uint64_t rint_26 : 1; 4532 uint64_t rint_27 : 1; 4533 uint64_t rint_28 : 1; 4534 uint64_t rint_29 : 1; 4535 uint64_t iob : 1; 4536 uint64_t rint_31 : 1; 4537 uint64_t reserved_32_63 : 32; 4538#endif 4539 } cn30xx; 4540 struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx; 4541 struct cvmx_npi_rsl_int_blocks_cn38xx 4542 { 4543#if __BYTE_ORDER == __BIG_ENDIAN 4544 uint64_t reserved_32_63 : 32; 4545 uint64_t rint_31 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4546 uint64_t iob : 1; /**< IOB_INT_SUM */ 4547 uint64_t rint_29 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4548 uint64_t rint_28 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4549 uint64_t rint_27 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4550 uint64_t rint_26 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4551 uint64_t rint_25 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4552 uint64_t rint_24 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4553 uint64_t asx1 : 1; /**< ASX1_INT_REG */ 4554 uint64_t asx0 : 1; /**< ASX0_INT_REG */ 4555 uint64_t rint_21 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4556 uint64_t pip : 1; /**< PIP_INT_REG. */ 4557 uint64_t spx1 : 1; /**< SPX1_INT_REG & STX1_INT_REG */ 4558 uint64_t spx0 : 1; /**< SPX0_INT_REG & STX0_INT_REG */ 4559 uint64_t lmc : 1; /**< LMC_MEM_CFG0 */ 4560 uint64_t l2c : 1; /**< L2T_ERR & L2D_ERR */ 4561 uint64_t rint_15 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4562 uint64_t rint_14 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4563 uint64_t rint_13 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4564 uint64_t pow : 1; /**< POW_ECC_ERR */ 4565 uint64_t tim : 1; /**< TIM_REG_ERROR */ 4566 uint64_t pko : 1; /**< PKO_REG_ERROR */ 4567 uint64_t ipd : 1; /**< IPD_INT_SUM */ 4568 uint64_t rint_8 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4569 uint64_t zip : 1; /**< ZIP_ERROR */ 4570 uint64_t dfa : 1; /**< DFA_ERR */ 4571 uint64_t fpa : 1; /**< FPA_INT_SUM */ 4572 uint64_t key : 1; /**< KEY_INT_SUM */ 4573 uint64_t npi : 1; /**< NPI_INT_SUM */ 4574 uint64_t gmx1 : 1; /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */ 4575 uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */ 4576 uint64_t mio : 1; /**< MIO_BOOT_ERR */ 4577#else 4578 uint64_t mio : 1; 4579 uint64_t gmx0 : 1; 4580 uint64_t gmx1 : 1; 4581 uint64_t npi : 1; 4582 uint64_t key : 1; 4583 uint64_t fpa : 1; 4584 uint64_t dfa : 1; 4585 uint64_t zip : 1; 4586 uint64_t rint_8 : 1; 4587 uint64_t ipd : 1; 4588 uint64_t pko : 1; 4589 uint64_t tim : 1; 4590 uint64_t pow : 1; 4591 uint64_t rint_13 : 1; 4592 uint64_t rint_14 : 1; 4593 uint64_t rint_15 : 1; 4594 uint64_t l2c : 1; 4595 uint64_t lmc : 1; 4596 uint64_t spx0 : 1; 4597 uint64_t spx1 : 1; 4598 uint64_t pip : 1; 4599 uint64_t rint_21 : 1; 4600 uint64_t asx0 : 1; 4601 uint64_t asx1 : 1; 4602 uint64_t rint_24 : 1; 4603 uint64_t rint_25 : 1; 4604 uint64_t rint_26 : 1; 4605 uint64_t rint_27 : 1; 4606 uint64_t rint_28 : 1; 4607 uint64_t rint_29 : 1; 4608 uint64_t iob : 1; 4609 uint64_t rint_31 : 1; 4610 uint64_t reserved_32_63 : 32; 4611#endif 4612 } cn38xx; 4613 struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2; 4614 struct cvmx_npi_rsl_int_blocks_cn50xx 4615 { 4616#if __BYTE_ORDER == __BIG_ENDIAN 4617 uint64_t reserved_31_63 : 33; 4618 uint64_t iob : 1; /**< IOB_INT_SUM */ 4619 uint64_t lmc1 : 1; /**< Always reads as zero */ 4620 uint64_t agl : 1; /**< Always reads as zero */ 4621 uint64_t reserved_24_27 : 4; 4622 uint64_t asx1 : 1; /**< Always reads as zero */ 4623 uint64_t asx0 : 1; /**< ASX0_INT_REG */ 4624 uint64_t reserved_21_21 : 1; 4625 uint64_t pip : 1; /**< PIP_INT_REG. */ 4626 uint64_t spx1 : 1; /**< Always reads as zero */ 4627 uint64_t spx0 : 1; /**< Always reads as zero */ 4628 uint64_t lmc : 1; /**< LMC_MEM_CFG0 */ 4629 uint64_t l2c : 1; /**< L2T_ERR & L2D_ERR */ 4630 uint64_t reserved_15_15 : 1; 4631 uint64_t rad : 1; /**< Always reads as zero */ 4632 uint64_t usb : 1; /**< USBN_INT_SUM */ 4633 uint64_t pow : 1; /**< POW_ECC_ERR */ 4634 uint64_t tim : 1; /**< TIM_REG_ERROR */ 4635 uint64_t pko : 1; /**< PKO_REG_ERROR */ 4636 uint64_t ipd : 1; /**< IPD_INT_SUM */ 4637 uint64_t reserved_8_8 : 1; 4638 uint64_t zip : 1; /**< Always reads as zero */ 4639 uint64_t dfa : 1; /**< Always reads as zero */ 4640 uint64_t fpa : 1; /**< FPA_INT_SUM */ 4641 uint64_t key : 1; /**< Always reads as zero */ 4642 uint64_t npi : 1; /**< NPI_INT_SUM */ 4643 uint64_t gmx1 : 1; /**< Always reads as zero */ 4644 uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */ 4645 uint64_t mio : 1; /**< MIO_BOOT_ERR */ 4646#else 4647 uint64_t mio : 1; 4648 uint64_t gmx0 : 1; 4649 uint64_t gmx1 : 1; 4650 uint64_t npi : 1; 4651 uint64_t key : 1; 4652 uint64_t fpa : 1; 4653 uint64_t dfa : 1; 4654 uint64_t zip : 1; 4655 uint64_t reserved_8_8 : 1; 4656 uint64_t ipd : 1; 4657 uint64_t pko : 1; 4658 uint64_t tim : 1; 4659 uint64_t pow : 1; 4660 uint64_t usb : 1; 4661 uint64_t rad : 1; 4662 uint64_t reserved_15_15 : 1; 4663 uint64_t l2c : 1; 4664 uint64_t lmc : 1; 4665 uint64_t spx0 : 1; 4666 uint64_t spx1 : 1; 4667 uint64_t pip : 1; 4668 uint64_t reserved_21_21 : 1; 4669 uint64_t asx0 : 1; 4670 uint64_t asx1 : 1; 4671 uint64_t reserved_24_27 : 4; 4672 uint64_t agl : 1; 4673 uint64_t lmc1 : 1; 4674 uint64_t iob : 1; 4675 uint64_t reserved_31_63 : 33; 4676#endif 4677 } cn50xx; 4678 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx; 4679 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1; 4680}; 4681typedef union cvmx_npi_rsl_int_blocks cvmx_npi_rsl_int_blocks_t; 4682 4683/** 4684 * cvmx_npi_size_input# 4685 * 4686 * NPI_SIZE_INPUT0 = NPI's Size for Input 0 Register 4687 * 4688 * The size (in instructions) of Instruction Queue-0. 4689 */ 4690union cvmx_npi_size_inputx 4691{ 4692 uint64_t u64; 4693 struct cvmx_npi_size_inputx_s 4694 { 4695#if __BYTE_ORDER == __BIG_ENDIAN 4696 uint64_t reserved_32_63 : 32; 4697 uint64_t size : 32; /**< The size of the Instruction Queue used by Octane. 4698 The value [SIZE] is in Instructions. 4699 A value of 0 in this field is illegal. */ 4700#else 4701 uint64_t size : 32; 4702 uint64_t reserved_32_63 : 32; 4703#endif 4704 } s; 4705 struct cvmx_npi_size_inputx_s cn30xx; 4706 struct cvmx_npi_size_inputx_s cn31xx; 4707 struct cvmx_npi_size_inputx_s cn38xx; 4708 struct cvmx_npi_size_inputx_s cn38xxp2; 4709 struct cvmx_npi_size_inputx_s cn50xx; 4710 struct cvmx_npi_size_inputx_s cn58xx; 4711 struct cvmx_npi_size_inputx_s cn58xxp1; 4712}; 4713typedef union cvmx_npi_size_inputx cvmx_npi_size_inputx_t; 4714 4715/** 4716 * cvmx_npi_win_read_to 4717 * 4718 * NPI_WIN_READ_TO = NPI WINDOW READ Timeout Register 4719 * 4720 * Number of core clocks to wait before timing out on a WINDOW-READ to the NCB. 4721 */ 4722union cvmx_npi_win_read_to 4723{ 4724 uint64_t u64; 4725 struct cvmx_npi_win_read_to_s 4726 { 4727#if __BYTE_ORDER == __BIG_ENDIAN 4728 uint64_t reserved_32_63 : 32; 4729 uint64_t time : 32; /**< Time to wait in core clocks. A value of 0 will 4730 cause no timeouts. */ 4731#else 4732 uint64_t time : 32; 4733 uint64_t reserved_32_63 : 32; 4734#endif 4735 } s; 4736 struct cvmx_npi_win_read_to_s cn30xx; 4737 struct cvmx_npi_win_read_to_s cn31xx; 4738 struct cvmx_npi_win_read_to_s cn38xx; 4739 struct cvmx_npi_win_read_to_s cn38xxp2; 4740 struct cvmx_npi_win_read_to_s cn50xx; 4741 struct cvmx_npi_win_read_to_s cn58xx; 4742 struct cvmx_npi_win_read_to_s cn58xxp1; 4743}; 4744typedef union cvmx_npi_win_read_to cvmx_npi_win_read_to_t; 4745 4746#endif 4747