cvmx-npei-defs.h revision 215976
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-npei-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon npei. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_NPEI_TYPEDEFS_H__ 53#define __CVMX_NPEI_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_NPEI_BAR1_INDEXX(unsigned long offset) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 60 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 61 cvmx_warn("CVMX_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset); 62 return 0x0000000000000000ull + ((offset) & 31) * 16; 63} 64#else 65#define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16) 66#endif 67#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68#define CVMX_NPEI_BIST_STATUS CVMX_NPEI_BIST_STATUS_FUNC() 69static inline uint64_t CVMX_NPEI_BIST_STATUS_FUNC(void) 70{ 71 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 72 cvmx_warn("CVMX_NPEI_BIST_STATUS not supported on this chip\n"); 73 return 0x0000000000000580ull; 74} 75#else 76#define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull) 77#endif 78#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 79#define CVMX_NPEI_BIST_STATUS2 CVMX_NPEI_BIST_STATUS2_FUNC() 80static inline uint64_t CVMX_NPEI_BIST_STATUS2_FUNC(void) 81{ 82 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 83 cvmx_warn("CVMX_NPEI_BIST_STATUS2 not supported on this chip\n"); 84 return 0x0000000000000680ull; 85} 86#else 87#define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull) 88#endif 89#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 90#define CVMX_NPEI_CTL_PORT0 CVMX_NPEI_CTL_PORT0_FUNC() 91static inline uint64_t CVMX_NPEI_CTL_PORT0_FUNC(void) 92{ 93 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 94 cvmx_warn("CVMX_NPEI_CTL_PORT0 not supported on this chip\n"); 95 return 0x0000000000000250ull; 96} 97#else 98#define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull) 99#endif 100#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 101#define CVMX_NPEI_CTL_PORT1 CVMX_NPEI_CTL_PORT1_FUNC() 102static inline uint64_t CVMX_NPEI_CTL_PORT1_FUNC(void) 103{ 104 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 105 cvmx_warn("CVMX_NPEI_CTL_PORT1 not supported on this chip\n"); 106 return 0x0000000000000260ull; 107} 108#else 109#define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull) 110#endif 111#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 112#define CVMX_NPEI_CTL_STATUS CVMX_NPEI_CTL_STATUS_FUNC() 113static inline uint64_t CVMX_NPEI_CTL_STATUS_FUNC(void) 114{ 115 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 116 cvmx_warn("CVMX_NPEI_CTL_STATUS not supported on this chip\n"); 117 return 0x0000000000000570ull; 118} 119#else 120#define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull) 121#endif 122#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 123#define CVMX_NPEI_CTL_STATUS2 CVMX_NPEI_CTL_STATUS2_FUNC() 124static inline uint64_t CVMX_NPEI_CTL_STATUS2_FUNC(void) 125{ 126 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 127 cvmx_warn("CVMX_NPEI_CTL_STATUS2 not supported on this chip\n"); 128 return 0x0000000000003C00ull; 129} 130#else 131#define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull) 132#endif 133#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 134#define CVMX_NPEI_DATA_OUT_CNT CVMX_NPEI_DATA_OUT_CNT_FUNC() 135static inline uint64_t CVMX_NPEI_DATA_OUT_CNT_FUNC(void) 136{ 137 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 138 cvmx_warn("CVMX_NPEI_DATA_OUT_CNT not supported on this chip\n"); 139 return 0x00000000000005F0ull; 140} 141#else 142#define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull) 143#endif 144#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 145#define CVMX_NPEI_DBG_DATA CVMX_NPEI_DBG_DATA_FUNC() 146static inline uint64_t CVMX_NPEI_DBG_DATA_FUNC(void) 147{ 148 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 149 cvmx_warn("CVMX_NPEI_DBG_DATA not supported on this chip\n"); 150 return 0x0000000000000510ull; 151} 152#else 153#define CVMX_NPEI_DBG_DATA (0x0000000000000510ull) 154#endif 155#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 156#define CVMX_NPEI_DBG_SELECT CVMX_NPEI_DBG_SELECT_FUNC() 157static inline uint64_t CVMX_NPEI_DBG_SELECT_FUNC(void) 158{ 159 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 160 cvmx_warn("CVMX_NPEI_DBG_SELECT not supported on this chip\n"); 161 return 0x0000000000000500ull; 162} 163#else 164#define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull) 165#endif 166#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 167#define CVMX_NPEI_DMA0_INT_LEVEL CVMX_NPEI_DMA0_INT_LEVEL_FUNC() 168static inline uint64_t CVMX_NPEI_DMA0_INT_LEVEL_FUNC(void) 169{ 170 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 171 cvmx_warn("CVMX_NPEI_DMA0_INT_LEVEL not supported on this chip\n"); 172 return 0x00000000000005C0ull; 173} 174#else 175#define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull) 176#endif 177#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 178#define CVMX_NPEI_DMA1_INT_LEVEL CVMX_NPEI_DMA1_INT_LEVEL_FUNC() 179static inline uint64_t CVMX_NPEI_DMA1_INT_LEVEL_FUNC(void) 180{ 181 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 182 cvmx_warn("CVMX_NPEI_DMA1_INT_LEVEL not supported on this chip\n"); 183 return 0x00000000000005D0ull; 184} 185#else 186#define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull) 187#endif 188#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 189static inline uint64_t CVMX_NPEI_DMAX_COUNTS(unsigned long offset) 190{ 191 if (!( 192 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) || 193 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))))) 194 cvmx_warn("CVMX_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset); 195 return 0x0000000000000450ull + ((offset) & 7) * 16; 196} 197#else 198#define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16) 199#endif 200#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 201static inline uint64_t CVMX_NPEI_DMAX_DBELL(unsigned long offset) 202{ 203 if (!( 204 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) || 205 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))))) 206 cvmx_warn("CVMX_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset); 207 return 0x00000000000003B0ull + ((offset) & 7) * 16; 208} 209#else 210#define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16) 211#endif 212#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 213static inline uint64_t CVMX_NPEI_DMAX_IBUFF_SADDR(unsigned long offset) 214{ 215 if (!( 216 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) || 217 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))))) 218 cvmx_warn("CVMX_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset); 219 return 0x0000000000000400ull + ((offset) & 7) * 16; 220} 221#else 222#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16) 223#endif 224#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 225static inline uint64_t CVMX_NPEI_DMAX_NADDR(unsigned long offset) 226{ 227 if (!( 228 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) || 229 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))))) 230 cvmx_warn("CVMX_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset); 231 return 0x00000000000004A0ull + ((offset) & 7) * 16; 232} 233#else 234#define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16) 235#endif 236#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 237#define CVMX_NPEI_DMA_CNTS CVMX_NPEI_DMA_CNTS_FUNC() 238static inline uint64_t CVMX_NPEI_DMA_CNTS_FUNC(void) 239{ 240 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 241 cvmx_warn("CVMX_NPEI_DMA_CNTS not supported on this chip\n"); 242 return 0x00000000000005E0ull; 243} 244#else 245#define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull) 246#endif 247#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 248#define CVMX_NPEI_DMA_CONTROL CVMX_NPEI_DMA_CONTROL_FUNC() 249static inline uint64_t CVMX_NPEI_DMA_CONTROL_FUNC(void) 250{ 251 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 252 cvmx_warn("CVMX_NPEI_DMA_CONTROL not supported on this chip\n"); 253 return 0x00000000000003A0ull; 254} 255#else 256#define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull) 257#endif 258#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 259#define CVMX_NPEI_DMA_PCIE_REQ_NUM CVMX_NPEI_DMA_PCIE_REQ_NUM_FUNC() 260static inline uint64_t CVMX_NPEI_DMA_PCIE_REQ_NUM_FUNC(void) 261{ 262 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 263 cvmx_warn("CVMX_NPEI_DMA_PCIE_REQ_NUM not supported on this chip\n"); 264 return 0x00000000000005B0ull; 265} 266#else 267#define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull) 268#endif 269#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 270#define CVMX_NPEI_DMA_STATE1 CVMX_NPEI_DMA_STATE1_FUNC() 271static inline uint64_t CVMX_NPEI_DMA_STATE1_FUNC(void) 272{ 273 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 274 cvmx_warn("CVMX_NPEI_DMA_STATE1 not supported on this chip\n"); 275 return 0x00000000000006C0ull; 276} 277#else 278#define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull) 279#endif 280#define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull) 281#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 282#define CVMX_NPEI_DMA_STATE2 CVMX_NPEI_DMA_STATE2_FUNC() 283static inline uint64_t CVMX_NPEI_DMA_STATE2_FUNC(void) 284{ 285 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 286 cvmx_warn("CVMX_NPEI_DMA_STATE2 not supported on this chip\n"); 287 return 0x00000000000006D0ull; 288} 289#else 290#define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull) 291#endif 292#define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull) 293#define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull) 294#define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull) 295#define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull) 296#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 297#define CVMX_NPEI_INT_A_ENB CVMX_NPEI_INT_A_ENB_FUNC() 298static inline uint64_t CVMX_NPEI_INT_A_ENB_FUNC(void) 299{ 300 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 301 cvmx_warn("CVMX_NPEI_INT_A_ENB not supported on this chip\n"); 302 return 0x0000000000000560ull; 303} 304#else 305#define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull) 306#endif 307#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 308#define CVMX_NPEI_INT_A_ENB2 CVMX_NPEI_INT_A_ENB2_FUNC() 309static inline uint64_t CVMX_NPEI_INT_A_ENB2_FUNC(void) 310{ 311 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 312 cvmx_warn("CVMX_NPEI_INT_A_ENB2 not supported on this chip\n"); 313 return 0x0000000000003CE0ull; 314} 315#else 316#define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull) 317#endif 318#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 319#define CVMX_NPEI_INT_A_SUM CVMX_NPEI_INT_A_SUM_FUNC() 320static inline uint64_t CVMX_NPEI_INT_A_SUM_FUNC(void) 321{ 322 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 323 cvmx_warn("CVMX_NPEI_INT_A_SUM not supported on this chip\n"); 324 return 0x0000000000000550ull; 325} 326#else 327#define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull) 328#endif 329#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 330#define CVMX_NPEI_INT_ENB CVMX_NPEI_INT_ENB_FUNC() 331static inline uint64_t CVMX_NPEI_INT_ENB_FUNC(void) 332{ 333 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 334 cvmx_warn("CVMX_NPEI_INT_ENB not supported on this chip\n"); 335 return 0x0000000000000540ull; 336} 337#else 338#define CVMX_NPEI_INT_ENB (0x0000000000000540ull) 339#endif 340#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 341#define CVMX_NPEI_INT_ENB2 CVMX_NPEI_INT_ENB2_FUNC() 342static inline uint64_t CVMX_NPEI_INT_ENB2_FUNC(void) 343{ 344 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 345 cvmx_warn("CVMX_NPEI_INT_ENB2 not supported on this chip\n"); 346 return 0x0000000000003CD0ull; 347} 348#else 349#define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull) 350#endif 351#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 352#define CVMX_NPEI_INT_INFO CVMX_NPEI_INT_INFO_FUNC() 353static inline uint64_t CVMX_NPEI_INT_INFO_FUNC(void) 354{ 355 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 356 cvmx_warn("CVMX_NPEI_INT_INFO not supported on this chip\n"); 357 return 0x0000000000000590ull; 358} 359#else 360#define CVMX_NPEI_INT_INFO (0x0000000000000590ull) 361#endif 362#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 363#define CVMX_NPEI_INT_SUM CVMX_NPEI_INT_SUM_FUNC() 364static inline uint64_t CVMX_NPEI_INT_SUM_FUNC(void) 365{ 366 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 367 cvmx_warn("CVMX_NPEI_INT_SUM not supported on this chip\n"); 368 return 0x0000000000000530ull; 369} 370#else 371#define CVMX_NPEI_INT_SUM (0x0000000000000530ull) 372#endif 373#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 374#define CVMX_NPEI_INT_SUM2 CVMX_NPEI_INT_SUM2_FUNC() 375static inline uint64_t CVMX_NPEI_INT_SUM2_FUNC(void) 376{ 377 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 378 cvmx_warn("CVMX_NPEI_INT_SUM2 not supported on this chip\n"); 379 return 0x0000000000003CC0ull; 380} 381#else 382#define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull) 383#endif 384#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 385#define CVMX_NPEI_LAST_WIN_RDATA0 CVMX_NPEI_LAST_WIN_RDATA0_FUNC() 386static inline uint64_t CVMX_NPEI_LAST_WIN_RDATA0_FUNC(void) 387{ 388 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 389 cvmx_warn("CVMX_NPEI_LAST_WIN_RDATA0 not supported on this chip\n"); 390 return 0x0000000000000600ull; 391} 392#else 393#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull) 394#endif 395#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 396#define CVMX_NPEI_LAST_WIN_RDATA1 CVMX_NPEI_LAST_WIN_RDATA1_FUNC() 397static inline uint64_t CVMX_NPEI_LAST_WIN_RDATA1_FUNC(void) 398{ 399 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 400 cvmx_warn("CVMX_NPEI_LAST_WIN_RDATA1 not supported on this chip\n"); 401 return 0x0000000000000610ull; 402} 403#else 404#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull) 405#endif 406#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 407#define CVMX_NPEI_MEM_ACCESS_CTL CVMX_NPEI_MEM_ACCESS_CTL_FUNC() 408static inline uint64_t CVMX_NPEI_MEM_ACCESS_CTL_FUNC(void) 409{ 410 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 411 cvmx_warn("CVMX_NPEI_MEM_ACCESS_CTL not supported on this chip\n"); 412 return 0x00000000000004F0ull; 413} 414#else 415#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull) 416#endif 417#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 418static inline uint64_t CVMX_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset) 419{ 420 if (!( 421 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27)))) || 422 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27)))))) 423 cvmx_warn("CVMX_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset); 424 return 0x0000000000000340ull + ((offset) & 31) * 16 - 16*12; 425} 426#else 427#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12) 428#endif 429#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430#define CVMX_NPEI_MSI_ENB0 CVMX_NPEI_MSI_ENB0_FUNC() 431static inline uint64_t CVMX_NPEI_MSI_ENB0_FUNC(void) 432{ 433 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 434 cvmx_warn("CVMX_NPEI_MSI_ENB0 not supported on this chip\n"); 435 return 0x0000000000003C50ull; 436} 437#else 438#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull) 439#endif 440#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 441#define CVMX_NPEI_MSI_ENB1 CVMX_NPEI_MSI_ENB1_FUNC() 442static inline uint64_t CVMX_NPEI_MSI_ENB1_FUNC(void) 443{ 444 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 445 cvmx_warn("CVMX_NPEI_MSI_ENB1 not supported on this chip\n"); 446 return 0x0000000000003C60ull; 447} 448#else 449#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull) 450#endif 451#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452#define CVMX_NPEI_MSI_ENB2 CVMX_NPEI_MSI_ENB2_FUNC() 453static inline uint64_t CVMX_NPEI_MSI_ENB2_FUNC(void) 454{ 455 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 456 cvmx_warn("CVMX_NPEI_MSI_ENB2 not supported on this chip\n"); 457 return 0x0000000000003C70ull; 458} 459#else 460#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull) 461#endif 462#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 463#define CVMX_NPEI_MSI_ENB3 CVMX_NPEI_MSI_ENB3_FUNC() 464static inline uint64_t CVMX_NPEI_MSI_ENB3_FUNC(void) 465{ 466 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 467 cvmx_warn("CVMX_NPEI_MSI_ENB3 not supported on this chip\n"); 468 return 0x0000000000003C80ull; 469} 470#else 471#define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull) 472#endif 473#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 474#define CVMX_NPEI_MSI_RCV0 CVMX_NPEI_MSI_RCV0_FUNC() 475static inline uint64_t CVMX_NPEI_MSI_RCV0_FUNC(void) 476{ 477 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 478 cvmx_warn("CVMX_NPEI_MSI_RCV0 not supported on this chip\n"); 479 return 0x0000000000003C10ull; 480} 481#else 482#define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull) 483#endif 484#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485#define CVMX_NPEI_MSI_RCV1 CVMX_NPEI_MSI_RCV1_FUNC() 486static inline uint64_t CVMX_NPEI_MSI_RCV1_FUNC(void) 487{ 488 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 489 cvmx_warn("CVMX_NPEI_MSI_RCV1 not supported on this chip\n"); 490 return 0x0000000000003C20ull; 491} 492#else 493#define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull) 494#endif 495#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 496#define CVMX_NPEI_MSI_RCV2 CVMX_NPEI_MSI_RCV2_FUNC() 497static inline uint64_t CVMX_NPEI_MSI_RCV2_FUNC(void) 498{ 499 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 500 cvmx_warn("CVMX_NPEI_MSI_RCV2 not supported on this chip\n"); 501 return 0x0000000000003C30ull; 502} 503#else 504#define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull) 505#endif 506#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 507#define CVMX_NPEI_MSI_RCV3 CVMX_NPEI_MSI_RCV3_FUNC() 508static inline uint64_t CVMX_NPEI_MSI_RCV3_FUNC(void) 509{ 510 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 511 cvmx_warn("CVMX_NPEI_MSI_RCV3 not supported on this chip\n"); 512 return 0x0000000000003C40ull; 513} 514#else 515#define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull) 516#endif 517#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 518#define CVMX_NPEI_MSI_RD_MAP CVMX_NPEI_MSI_RD_MAP_FUNC() 519static inline uint64_t CVMX_NPEI_MSI_RD_MAP_FUNC(void) 520{ 521 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 522 cvmx_warn("CVMX_NPEI_MSI_RD_MAP not supported on this chip\n"); 523 return 0x0000000000003CA0ull; 524} 525#else 526#define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull) 527#endif 528#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 529#define CVMX_NPEI_MSI_W1C_ENB0 CVMX_NPEI_MSI_W1C_ENB0_FUNC() 530static inline uint64_t CVMX_NPEI_MSI_W1C_ENB0_FUNC(void) 531{ 532 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 533 cvmx_warn("CVMX_NPEI_MSI_W1C_ENB0 not supported on this chip\n"); 534 return 0x0000000000003CF0ull; 535} 536#else 537#define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull) 538#endif 539#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 540#define CVMX_NPEI_MSI_W1C_ENB1 CVMX_NPEI_MSI_W1C_ENB1_FUNC() 541static inline uint64_t CVMX_NPEI_MSI_W1C_ENB1_FUNC(void) 542{ 543 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 544 cvmx_warn("CVMX_NPEI_MSI_W1C_ENB1 not supported on this chip\n"); 545 return 0x0000000000003D00ull; 546} 547#else 548#define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull) 549#endif 550#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551#define CVMX_NPEI_MSI_W1C_ENB2 CVMX_NPEI_MSI_W1C_ENB2_FUNC() 552static inline uint64_t CVMX_NPEI_MSI_W1C_ENB2_FUNC(void) 553{ 554 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 555 cvmx_warn("CVMX_NPEI_MSI_W1C_ENB2 not supported on this chip\n"); 556 return 0x0000000000003D10ull; 557} 558#else 559#define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull) 560#endif 561#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 562#define CVMX_NPEI_MSI_W1C_ENB3 CVMX_NPEI_MSI_W1C_ENB3_FUNC() 563static inline uint64_t CVMX_NPEI_MSI_W1C_ENB3_FUNC(void) 564{ 565 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 566 cvmx_warn("CVMX_NPEI_MSI_W1C_ENB3 not supported on this chip\n"); 567 return 0x0000000000003D20ull; 568} 569#else 570#define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull) 571#endif 572#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 573#define CVMX_NPEI_MSI_W1S_ENB0 CVMX_NPEI_MSI_W1S_ENB0_FUNC() 574static inline uint64_t CVMX_NPEI_MSI_W1S_ENB0_FUNC(void) 575{ 576 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 577 cvmx_warn("CVMX_NPEI_MSI_W1S_ENB0 not supported on this chip\n"); 578 return 0x0000000000003D30ull; 579} 580#else 581#define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull) 582#endif 583#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 584#define CVMX_NPEI_MSI_W1S_ENB1 CVMX_NPEI_MSI_W1S_ENB1_FUNC() 585static inline uint64_t CVMX_NPEI_MSI_W1S_ENB1_FUNC(void) 586{ 587 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 588 cvmx_warn("CVMX_NPEI_MSI_W1S_ENB1 not supported on this chip\n"); 589 return 0x0000000000003D40ull; 590} 591#else 592#define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull) 593#endif 594#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 595#define CVMX_NPEI_MSI_W1S_ENB2 CVMX_NPEI_MSI_W1S_ENB2_FUNC() 596static inline uint64_t CVMX_NPEI_MSI_W1S_ENB2_FUNC(void) 597{ 598 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 599 cvmx_warn("CVMX_NPEI_MSI_W1S_ENB2 not supported on this chip\n"); 600 return 0x0000000000003D50ull; 601} 602#else 603#define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull) 604#endif 605#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 606#define CVMX_NPEI_MSI_W1S_ENB3 CVMX_NPEI_MSI_W1S_ENB3_FUNC() 607static inline uint64_t CVMX_NPEI_MSI_W1S_ENB3_FUNC(void) 608{ 609 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 610 cvmx_warn("CVMX_NPEI_MSI_W1S_ENB3 not supported on this chip\n"); 611 return 0x0000000000003D60ull; 612} 613#else 614#define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull) 615#endif 616#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 617#define CVMX_NPEI_MSI_WR_MAP CVMX_NPEI_MSI_WR_MAP_FUNC() 618static inline uint64_t CVMX_NPEI_MSI_WR_MAP_FUNC(void) 619{ 620 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 621 cvmx_warn("CVMX_NPEI_MSI_WR_MAP not supported on this chip\n"); 622 return 0x0000000000003C90ull; 623} 624#else 625#define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull) 626#endif 627#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 628#define CVMX_NPEI_PCIE_CREDIT_CNT CVMX_NPEI_PCIE_CREDIT_CNT_FUNC() 629static inline uint64_t CVMX_NPEI_PCIE_CREDIT_CNT_FUNC(void) 630{ 631 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 632 cvmx_warn("CVMX_NPEI_PCIE_CREDIT_CNT not supported on this chip\n"); 633 return 0x0000000000003D70ull; 634} 635#else 636#define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull) 637#endif 638#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 639#define CVMX_NPEI_PCIE_MSI_RCV CVMX_NPEI_PCIE_MSI_RCV_FUNC() 640static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_FUNC(void) 641{ 642 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 643 cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV not supported on this chip\n"); 644 return 0x0000000000003CB0ull; 645} 646#else 647#define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull) 648#endif 649#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 650#define CVMX_NPEI_PCIE_MSI_RCV_B1 CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC() 651static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC(void) 652{ 653 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 654 cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n"); 655 return 0x0000000000000650ull; 656} 657#else 658#define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull) 659#endif 660#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 661#define CVMX_NPEI_PCIE_MSI_RCV_B2 CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC() 662static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC(void) 663{ 664 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 665 cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n"); 666 return 0x0000000000000660ull; 667} 668#else 669#define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull) 670#endif 671#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 672#define CVMX_NPEI_PCIE_MSI_RCV_B3 CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC() 673static inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC(void) 674{ 675 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 676 cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n"); 677 return 0x0000000000000670ull; 678} 679#else 680#define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull) 681#endif 682#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 683static inline uint64_t CVMX_NPEI_PKTX_CNTS(unsigned long offset) 684{ 685 if (!( 686 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 687 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 688 cvmx_warn("CVMX_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset); 689 return 0x0000000000002400ull + ((offset) & 31) * 16; 690} 691#else 692#define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16) 693#endif 694#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 695static inline uint64_t CVMX_NPEI_PKTX_INSTR_BADDR(unsigned long offset) 696{ 697 if (!( 698 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 699 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 700 cvmx_warn("CVMX_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset); 701 return 0x0000000000002800ull + ((offset) & 31) * 16; 702} 703#else 704#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16) 705#endif 706#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 707static inline uint64_t CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset) 708{ 709 if (!( 710 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 711 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 712 cvmx_warn("CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset); 713 return 0x0000000000002C00ull + ((offset) & 31) * 16; 714} 715#else 716#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16) 717#endif 718#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 719static inline uint64_t CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset) 720{ 721 if (!( 722 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 723 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 724 cvmx_warn("CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset); 725 return 0x0000000000003000ull + ((offset) & 31) * 16; 726} 727#else 728#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16) 729#endif 730#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 731static inline uint64_t CVMX_NPEI_PKTX_INSTR_HEADER(unsigned long offset) 732{ 733 if (!( 734 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 735 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 736 cvmx_warn("CVMX_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset); 737 return 0x0000000000003400ull + ((offset) & 31) * 16; 738} 739#else 740#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16) 741#endif 742#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 743static inline uint64_t CVMX_NPEI_PKTX_IN_BP(unsigned long offset) 744{ 745 if (!( 746 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 747 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 748 cvmx_warn("CVMX_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset); 749 return 0x0000000000003800ull + ((offset) & 31) * 16; 750} 751#else 752#define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16) 753#endif 754#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 755static inline uint64_t CVMX_NPEI_PKTX_SLIST_BADDR(unsigned long offset) 756{ 757 if (!( 758 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 759 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 760 cvmx_warn("CVMX_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset); 761 return 0x0000000000001400ull + ((offset) & 31) * 16; 762} 763#else 764#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16) 765#endif 766#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 767static inline uint64_t CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset) 768{ 769 if (!( 770 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 771 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 772 cvmx_warn("CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset); 773 return 0x0000000000001800ull + ((offset) & 31) * 16; 774} 775#else 776#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16) 777#endif 778#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 779static inline uint64_t CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset) 780{ 781 if (!( 782 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 783 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 784 cvmx_warn("CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset); 785 return 0x0000000000001C00ull + ((offset) & 31) * 16; 786} 787#else 788#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16) 789#endif 790#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 791#define CVMX_NPEI_PKT_CNT_INT CVMX_NPEI_PKT_CNT_INT_FUNC() 792static inline uint64_t CVMX_NPEI_PKT_CNT_INT_FUNC(void) 793{ 794 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 795 cvmx_warn("CVMX_NPEI_PKT_CNT_INT not supported on this chip\n"); 796 return 0x0000000000001110ull; 797} 798#else 799#define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull) 800#endif 801#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 802#define CVMX_NPEI_PKT_CNT_INT_ENB CVMX_NPEI_PKT_CNT_INT_ENB_FUNC() 803static inline uint64_t CVMX_NPEI_PKT_CNT_INT_ENB_FUNC(void) 804{ 805 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 806 cvmx_warn("CVMX_NPEI_PKT_CNT_INT_ENB not supported on this chip\n"); 807 return 0x0000000000001130ull; 808} 809#else 810#define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull) 811#endif 812#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 813#define CVMX_NPEI_PKT_DATA_OUT_ES CVMX_NPEI_PKT_DATA_OUT_ES_FUNC() 814static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ES_FUNC(void) 815{ 816 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 817 cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_ES not supported on this chip\n"); 818 return 0x00000000000010B0ull; 819} 820#else 821#define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull) 822#endif 823#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 824#define CVMX_NPEI_PKT_DATA_OUT_NS CVMX_NPEI_PKT_DATA_OUT_NS_FUNC() 825static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_NS_FUNC(void) 826{ 827 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 828 cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_NS not supported on this chip\n"); 829 return 0x00000000000010A0ull; 830} 831#else 832#define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull) 833#endif 834#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 835#define CVMX_NPEI_PKT_DATA_OUT_ROR CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC() 836static inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC(void) 837{ 838 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 839 cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n"); 840 return 0x0000000000001090ull; 841} 842#else 843#define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull) 844#endif 845#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 846#define CVMX_NPEI_PKT_DPADDR CVMX_NPEI_PKT_DPADDR_FUNC() 847static inline uint64_t CVMX_NPEI_PKT_DPADDR_FUNC(void) 848{ 849 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 850 cvmx_warn("CVMX_NPEI_PKT_DPADDR not supported on this chip\n"); 851 return 0x0000000000001080ull; 852} 853#else 854#define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull) 855#endif 856#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 857#define CVMX_NPEI_PKT_INPUT_CONTROL CVMX_NPEI_PKT_INPUT_CONTROL_FUNC() 858static inline uint64_t CVMX_NPEI_PKT_INPUT_CONTROL_FUNC(void) 859{ 860 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 861 cvmx_warn("CVMX_NPEI_PKT_INPUT_CONTROL not supported on this chip\n"); 862 return 0x0000000000001150ull; 863} 864#else 865#define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull) 866#endif 867#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 868#define CVMX_NPEI_PKT_INSTR_ENB CVMX_NPEI_PKT_INSTR_ENB_FUNC() 869static inline uint64_t CVMX_NPEI_PKT_INSTR_ENB_FUNC(void) 870{ 871 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 872 cvmx_warn("CVMX_NPEI_PKT_INSTR_ENB not supported on this chip\n"); 873 return 0x0000000000001000ull; 874} 875#else 876#define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull) 877#endif 878#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 879#define CVMX_NPEI_PKT_INSTR_RD_SIZE CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC() 880static inline uint64_t CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC(void) 881{ 882 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 883 cvmx_warn("CVMX_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n"); 884 return 0x0000000000001190ull; 885} 886#else 887#define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull) 888#endif 889#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 890#define CVMX_NPEI_PKT_INSTR_SIZE CVMX_NPEI_PKT_INSTR_SIZE_FUNC() 891static inline uint64_t CVMX_NPEI_PKT_INSTR_SIZE_FUNC(void) 892{ 893 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 894 cvmx_warn("CVMX_NPEI_PKT_INSTR_SIZE not supported on this chip\n"); 895 return 0x0000000000001020ull; 896} 897#else 898#define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull) 899#endif 900#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 901#define CVMX_NPEI_PKT_INT_LEVELS CVMX_NPEI_PKT_INT_LEVELS_FUNC() 902static inline uint64_t CVMX_NPEI_PKT_INT_LEVELS_FUNC(void) 903{ 904 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 905 cvmx_warn("CVMX_NPEI_PKT_INT_LEVELS not supported on this chip\n"); 906 return 0x0000000000001100ull; 907} 908#else 909#define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull) 910#endif 911#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 912#define CVMX_NPEI_PKT_IN_BP CVMX_NPEI_PKT_IN_BP_FUNC() 913static inline uint64_t CVMX_NPEI_PKT_IN_BP_FUNC(void) 914{ 915 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 916 cvmx_warn("CVMX_NPEI_PKT_IN_BP not supported on this chip\n"); 917 return 0x00000000000006B0ull; 918} 919#else 920#define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull) 921#endif 922#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 923static inline uint64_t CVMX_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset) 924{ 925 if (!( 926 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 927 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 928 cvmx_warn("CVMX_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset); 929 return 0x0000000000002000ull + ((offset) & 31) * 16; 930} 931#else 932#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16) 933#endif 934#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 935#define CVMX_NPEI_PKT_IN_INSTR_COUNTS CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC() 936static inline uint64_t CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void) 937{ 938 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 939 cvmx_warn("CVMX_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n"); 940 return 0x00000000000006A0ull; 941} 942#else 943#define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull) 944#endif 945#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 946#define CVMX_NPEI_PKT_IN_PCIE_PORT CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC() 947static inline uint64_t CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC(void) 948{ 949 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 950 cvmx_warn("CVMX_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n"); 951 return 0x00000000000011A0ull; 952} 953#else 954#define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull) 955#endif 956#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 957#define CVMX_NPEI_PKT_IPTR CVMX_NPEI_PKT_IPTR_FUNC() 958static inline uint64_t CVMX_NPEI_PKT_IPTR_FUNC(void) 959{ 960 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 961 cvmx_warn("CVMX_NPEI_PKT_IPTR not supported on this chip\n"); 962 return 0x0000000000001070ull; 963} 964#else 965#define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull) 966#endif 967#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 968#define CVMX_NPEI_PKT_OUTPUT_WMARK CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC() 969static inline uint64_t CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC(void) 970{ 971 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 972 cvmx_warn("CVMX_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n"); 973 return 0x0000000000001160ull; 974} 975#else 976#define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull) 977#endif 978#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 979#define CVMX_NPEI_PKT_OUT_BMODE CVMX_NPEI_PKT_OUT_BMODE_FUNC() 980static inline uint64_t CVMX_NPEI_PKT_OUT_BMODE_FUNC(void) 981{ 982 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 983 cvmx_warn("CVMX_NPEI_PKT_OUT_BMODE not supported on this chip\n"); 984 return 0x00000000000010D0ull; 985} 986#else 987#define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull) 988#endif 989#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 990#define CVMX_NPEI_PKT_OUT_ENB CVMX_NPEI_PKT_OUT_ENB_FUNC() 991static inline uint64_t CVMX_NPEI_PKT_OUT_ENB_FUNC(void) 992{ 993 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 994 cvmx_warn("CVMX_NPEI_PKT_OUT_ENB not supported on this chip\n"); 995 return 0x0000000000001010ull; 996} 997#else 998#define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull) 999#endif 1000#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1001#define CVMX_NPEI_PKT_PCIE_PORT CVMX_NPEI_PKT_PCIE_PORT_FUNC() 1002static inline uint64_t CVMX_NPEI_PKT_PCIE_PORT_FUNC(void) 1003{ 1004 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1005 cvmx_warn("CVMX_NPEI_PKT_PCIE_PORT not supported on this chip\n"); 1006 return 0x00000000000010E0ull; 1007} 1008#else 1009#define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull) 1010#endif 1011#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1012#define CVMX_NPEI_PKT_PORT_IN_RST CVMX_NPEI_PKT_PORT_IN_RST_FUNC() 1013static inline uint64_t CVMX_NPEI_PKT_PORT_IN_RST_FUNC(void) 1014{ 1015 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1016 cvmx_warn("CVMX_NPEI_PKT_PORT_IN_RST not supported on this chip\n"); 1017 return 0x0000000000000690ull; 1018} 1019#else 1020#define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull) 1021#endif 1022#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1023#define CVMX_NPEI_PKT_SLIST_ES CVMX_NPEI_PKT_SLIST_ES_FUNC() 1024static inline uint64_t CVMX_NPEI_PKT_SLIST_ES_FUNC(void) 1025{ 1026 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1027 cvmx_warn("CVMX_NPEI_PKT_SLIST_ES not supported on this chip\n"); 1028 return 0x0000000000001050ull; 1029} 1030#else 1031#define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull) 1032#endif 1033#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1034#define CVMX_NPEI_PKT_SLIST_ID_SIZE CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC() 1035static inline uint64_t CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC(void) 1036{ 1037 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1038 cvmx_warn("CVMX_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n"); 1039 return 0x0000000000001180ull; 1040} 1041#else 1042#define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull) 1043#endif 1044#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1045#define CVMX_NPEI_PKT_SLIST_NS CVMX_NPEI_PKT_SLIST_NS_FUNC() 1046static inline uint64_t CVMX_NPEI_PKT_SLIST_NS_FUNC(void) 1047{ 1048 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1049 cvmx_warn("CVMX_NPEI_PKT_SLIST_NS not supported on this chip\n"); 1050 return 0x0000000000001040ull; 1051} 1052#else 1053#define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull) 1054#endif 1055#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1056#define CVMX_NPEI_PKT_SLIST_ROR CVMX_NPEI_PKT_SLIST_ROR_FUNC() 1057static inline uint64_t CVMX_NPEI_PKT_SLIST_ROR_FUNC(void) 1058{ 1059 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1060 cvmx_warn("CVMX_NPEI_PKT_SLIST_ROR not supported on this chip\n"); 1061 return 0x0000000000001030ull; 1062} 1063#else 1064#define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull) 1065#endif 1066#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1067#define CVMX_NPEI_PKT_TIME_INT CVMX_NPEI_PKT_TIME_INT_FUNC() 1068static inline uint64_t CVMX_NPEI_PKT_TIME_INT_FUNC(void) 1069{ 1070 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1071 cvmx_warn("CVMX_NPEI_PKT_TIME_INT not supported on this chip\n"); 1072 return 0x0000000000001120ull; 1073} 1074#else 1075#define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull) 1076#endif 1077#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1078#define CVMX_NPEI_PKT_TIME_INT_ENB CVMX_NPEI_PKT_TIME_INT_ENB_FUNC() 1079static inline uint64_t CVMX_NPEI_PKT_TIME_INT_ENB_FUNC(void) 1080{ 1081 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1082 cvmx_warn("CVMX_NPEI_PKT_TIME_INT_ENB not supported on this chip\n"); 1083 return 0x0000000000001140ull; 1084} 1085#else 1086#define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull) 1087#endif 1088#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1089#define CVMX_NPEI_RSL_INT_BLOCKS CVMX_NPEI_RSL_INT_BLOCKS_FUNC() 1090static inline uint64_t CVMX_NPEI_RSL_INT_BLOCKS_FUNC(void) 1091{ 1092 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1093 cvmx_warn("CVMX_NPEI_RSL_INT_BLOCKS not supported on this chip\n"); 1094 return 0x0000000000000520ull; 1095} 1096#else 1097#define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull) 1098#endif 1099#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1100#define CVMX_NPEI_SCRATCH_1 CVMX_NPEI_SCRATCH_1_FUNC() 1101static inline uint64_t CVMX_NPEI_SCRATCH_1_FUNC(void) 1102{ 1103 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1104 cvmx_warn("CVMX_NPEI_SCRATCH_1 not supported on this chip\n"); 1105 return 0x0000000000000270ull; 1106} 1107#else 1108#define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull) 1109#endif 1110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1111#define CVMX_NPEI_STATE1 CVMX_NPEI_STATE1_FUNC() 1112static inline uint64_t CVMX_NPEI_STATE1_FUNC(void) 1113{ 1114 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1115 cvmx_warn("CVMX_NPEI_STATE1 not supported on this chip\n"); 1116 return 0x0000000000000620ull; 1117} 1118#else 1119#define CVMX_NPEI_STATE1 (0x0000000000000620ull) 1120#endif 1121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1122#define CVMX_NPEI_STATE2 CVMX_NPEI_STATE2_FUNC() 1123static inline uint64_t CVMX_NPEI_STATE2_FUNC(void) 1124{ 1125 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1126 cvmx_warn("CVMX_NPEI_STATE2 not supported on this chip\n"); 1127 return 0x0000000000000630ull; 1128} 1129#else 1130#define CVMX_NPEI_STATE2 (0x0000000000000630ull) 1131#endif 1132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1133#define CVMX_NPEI_STATE3 CVMX_NPEI_STATE3_FUNC() 1134static inline uint64_t CVMX_NPEI_STATE3_FUNC(void) 1135{ 1136 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1137 cvmx_warn("CVMX_NPEI_STATE3 not supported on this chip\n"); 1138 return 0x0000000000000640ull; 1139} 1140#else 1141#define CVMX_NPEI_STATE3 (0x0000000000000640ull) 1142#endif 1143#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1144#define CVMX_NPEI_WINDOW_CTL CVMX_NPEI_WINDOW_CTL_FUNC() 1145static inline uint64_t CVMX_NPEI_WINDOW_CTL_FUNC(void) 1146{ 1147 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1148 cvmx_warn("CVMX_NPEI_WINDOW_CTL not supported on this chip\n"); 1149 return 0x0000000000000380ull; 1150} 1151#else 1152#define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull) 1153#endif 1154#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1155#define CVMX_NPEI_WIN_RD_ADDR CVMX_NPEI_WIN_RD_ADDR_FUNC() 1156static inline uint64_t CVMX_NPEI_WIN_RD_ADDR_FUNC(void) 1157{ 1158 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1159 cvmx_warn("CVMX_NPEI_WIN_RD_ADDR not supported on this chip\n"); 1160 return 0x0000000000000210ull; 1161} 1162#else 1163#define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull) 1164#endif 1165#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1166#define CVMX_NPEI_WIN_RD_DATA CVMX_NPEI_WIN_RD_DATA_FUNC() 1167static inline uint64_t CVMX_NPEI_WIN_RD_DATA_FUNC(void) 1168{ 1169 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1170 cvmx_warn("CVMX_NPEI_WIN_RD_DATA not supported on this chip\n"); 1171 return 0x0000000000000240ull; 1172} 1173#else 1174#define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull) 1175#endif 1176#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1177#define CVMX_NPEI_WIN_WR_ADDR CVMX_NPEI_WIN_WR_ADDR_FUNC() 1178static inline uint64_t CVMX_NPEI_WIN_WR_ADDR_FUNC(void) 1179{ 1180 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1181 cvmx_warn("CVMX_NPEI_WIN_WR_ADDR not supported on this chip\n"); 1182 return 0x0000000000000200ull; 1183} 1184#else 1185#define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull) 1186#endif 1187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1188#define CVMX_NPEI_WIN_WR_DATA CVMX_NPEI_WIN_WR_DATA_FUNC() 1189static inline uint64_t CVMX_NPEI_WIN_WR_DATA_FUNC(void) 1190{ 1191 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1192 cvmx_warn("CVMX_NPEI_WIN_WR_DATA not supported on this chip\n"); 1193 return 0x0000000000000220ull; 1194} 1195#else 1196#define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull) 1197#endif 1198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1199#define CVMX_NPEI_WIN_WR_MASK CVMX_NPEI_WIN_WR_MASK_FUNC() 1200static inline uint64_t CVMX_NPEI_WIN_WR_MASK_FUNC(void) 1201{ 1202 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1203 cvmx_warn("CVMX_NPEI_WIN_WR_MASK not supported on this chip\n"); 1204 return 0x0000000000000230ull; 1205} 1206#else 1207#define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull) 1208#endif 1209 1210/** 1211 * cvmx_npei_bar1_index# 1212 * 1213 * Total Address is 16Kb; 0x0000 - 0x3fff, 0x000 - 0x7fe(Reg, every other 8B) 1214 * 1215 * General 5kb; 0x0000 - 0x13ff, 0x000 - 0x27e(Reg-General) 1216 * PktMem 10Kb; 0x1400 - 0x3bff, 0x280 - 0x77e(Reg-General-Packet) 1217 * Rsvd 1Kb; 0x3c00 - 0x3fff, 0x780 - 0x7fe(Reg-NCB Only Mode) 1218 * == NPEI_PKT_CNT_INT_ENB[PORT] 1219 * == NPEI_PKT_TIME_INT_ENB[PORT] 1220 * == NPEI_PKT_CNT_INT[PORT] 1221 * == NPEI_PKT_TIME_INT[PORT] 1222 * == NPEI_PKT_PCIE_PORT[PP] 1223 * == NPEI_PKT_SLIST_ROR[ROR] 1224 * == NPEI_PKT_SLIST_ROR[NSR] ? 1225 * == NPEI_PKT_SLIST_ES[ES] 1226 * == NPEI_PKTn_SLIST_BAOFF_DBELL[AOFF] 1227 * == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL] 1228 * == NPEI_PKTn_CNTS[CNT] 1229 * NPEI_CTL_STATUS[OUTn_ENB] == NPEI_PKT_OUT_ENB[ENB] 1230 * NPEI_BASE_ADDRESS_OUTPUTn[BADDR] == NPEI_PKTn_SLIST_BADDR[ADDR] 1231 * NPEI_DESC_OUTPUTn[SIZE] == NPEI_PKTn_SLIST_FIFO_RSIZE[RSIZE] 1232 * NPEI_Pn_DBPAIR_ADDR[NADDR] == NPEI_PKTn_SLIST_BADDR[ADDR] + NPEI_PKTn_SLIST_BAOFF_DBELL[AOFF] 1233 * NPEI_PKT_CREDITSn[PTR_CNT] == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL] 1234 * NPEI_P0_PAIR_CNTS[AVAIL] == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL] 1235 * NPEI_P0_PAIR_CNTS[FCNT] == 1236 * NPEI_PKTS_SENTn[PKT_CNT] == NPEI_PKTn_CNTS[CNT] 1237 * NPEI_OUTPUT_CONTROL[Pn_BMODE] == NPEI_PKT_OUT_BMODE[BMODE] 1238 * NPEI_PKT_CREDITSn[PKT_CNT] == NPEI_PKTn_CNTS[CNT] 1239 * NPEI_BUFF_SIZE_OUTPUTn[BSIZE] == NPEI_PKT_SLIST_ID_SIZE[BSIZE] 1240 * NPEI_BUFF_SIZE_OUTPUTn[ISIZE] == NPEI_PKT_SLIST_ID_SIZE[ISIZE] 1241 * NPEI_OUTPUT_CONTROL[On_CSRM] == NPEI_PKT_DPADDR[DPTR] & NPEI_PKT_OUT_USE_IPTR[PORT] 1242 * NPEI_OUTPUT_CONTROL[On_ES] == NPEI_PKT_DATA_OUT_ES[ES] 1243 * NPEI_OUTPUT_CONTROL[On_NS] == NPEI_PKT_DATA_OUT_NS[NSR] ? 1244 * NPEI_OUTPUT_CONTROL[On_RO] == NPEI_PKT_DATA_OUT_ROR[ROR] 1245 * NPEI_PKTS_SENT_INT_LEVn[PKT_CNT] == NPEI_PKT_INT_LEVELS[CNT] 1246 * NPEI_PKTS_SENT_TIMEn[PKT_TIME] == NPEI_PKT_INT_LEVELS[TIME] 1247 * NPEI_OUTPUT_CONTROL[IPTR_On] == NPEI_PKT_IPTR[IPTR] 1248 * NPEI_PCIE_PORT_OUTPUT[] == NPEI_PKT_PCIE_PORT[PP] 1249 * 1250 * NPEI_BAR1_INDEXX = NPEI BAR1 IndexX Register 1251 * 1252 * Contains address index and control bits for access to memory ranges of BAR-1. Index is build from supplied address [25:22]. 1253 * NPEI_BAR1_INDEX0 through NPEI_BAR1_INDEX15 is used for transactions orginating with PCIE-PORT0 and NPEI_BAR1_INDEX16 1254 * through NPEI_BAR1_INDEX31 is used for transactions originating with PCIE-PORT1. 1255 */ 1256union cvmx_npei_bar1_indexx 1257{ 1258 uint32_t u32; 1259 struct cvmx_npei_bar1_indexx_s 1260 { 1261#if __BYTE_ORDER == __BIG_ENDIAN 1262 uint32_t reserved_18_31 : 14; 1263 uint32_t addr_idx : 14; /**< Address bits [35:22] sent to L2C */ 1264 uint32_t ca : 1; /**< Set '1' when access is not to be cached in L2. */ 1265 uint32_t end_swp : 2; /**< Endian Swap Mode */ 1266 uint32_t addr_v : 1; /**< Set '1' when the selected address range is valid. */ 1267#else 1268 uint32_t addr_v : 1; 1269 uint32_t end_swp : 2; 1270 uint32_t ca : 1; 1271 uint32_t addr_idx : 14; 1272 uint32_t reserved_18_31 : 14; 1273#endif 1274 } s; 1275 struct cvmx_npei_bar1_indexx_s cn52xx; 1276 struct cvmx_npei_bar1_indexx_s cn52xxp1; 1277 struct cvmx_npei_bar1_indexx_s cn56xx; 1278 struct cvmx_npei_bar1_indexx_s cn56xxp1; 1279}; 1280typedef union cvmx_npei_bar1_indexx cvmx_npei_bar1_indexx_t; 1281 1282/** 1283 * cvmx_npei_bist_status 1284 * 1285 * NPEI_BIST_STATUS = NPI's BIST Status Register 1286 * 1287 * Results from BIST runs of NPEI's memories. 1288 */ 1289union cvmx_npei_bist_status 1290{ 1291 uint64_t u64; 1292 struct cvmx_npei_bist_status_s 1293 { 1294#if __BYTE_ORDER == __BIG_ENDIAN 1295 uint64_t pkt_rdf : 1; /**< BIST Status for PKT Read FIFO */ 1296 uint64_t reserved_60_62 : 3; 1297 uint64_t pcr_gim : 1; /**< BIST Status for PKT Gather Instr MEM */ 1298 uint64_t pkt_pif : 1; /**< BIST Status for PKT INB FIFO */ 1299 uint64_t pcsr_int : 1; /**< BIST Status for PKT pout_int_bstatus */ 1300 uint64_t pcsr_im : 1; /**< BIST Status for PKT pcsr_instr_mem_bstatus */ 1301 uint64_t pcsr_cnt : 1; /**< BIST Status for PKT pin_cnt_bstatus */ 1302 uint64_t pcsr_id : 1; /**< BIST Status for PKT pcsr_in_done_bstatus */ 1303 uint64_t pcsr_sl : 1; /**< BIST Status for PKT pcsr_slist_bstatus */ 1304 uint64_t reserved_50_52 : 3; 1305 uint64_t pkt_ind : 1; /**< BIST Status for PKT Instruction Done MEM */ 1306 uint64_t pkt_slm : 1; /**< BIST Status for PKT SList MEM */ 1307 uint64_t reserved_36_47 : 12; 1308 uint64_t d0_pst : 1; /**< BIST Status for DMA0 Pcie Store */ 1309 uint64_t d1_pst : 1; /**< BIST Status for DMA1 Pcie Store */ 1310 uint64_t d2_pst : 1; /**< BIST Status for DMA2 Pcie Store */ 1311 uint64_t d3_pst : 1; /**< BIST Status for DMA3 Pcie Store */ 1312 uint64_t reserved_31_31 : 1; 1313 uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */ 1314 uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */ 1315 uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */ 1316 uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */ 1317 uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */ 1318 uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */ 1319 uint64_t p2n1_po : 1; /**< BIST Status for P2N Port1 P Order */ 1320 uint64_t p2n1_no : 1; /**< BIST Status for P2N Port1 N Order */ 1321 uint64_t p2n1_co : 1; /**< BIST Status for P2N Port1 C Order */ 1322 uint64_t p2n0_po : 1; /**< BIST Status for P2N Port0 P Order */ 1323 uint64_t p2n0_no : 1; /**< BIST Status for P2N Port0 N Order */ 1324 uint64_t p2n0_co : 1; /**< BIST Status for P2N Port0 C Order */ 1325 uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */ 1326 uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */ 1327 uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */ 1328 uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */ 1329 uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */ 1330 uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */ 1331 uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */ 1332 uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */ 1333 uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */ 1334 uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */ 1335 uint64_t csm0 : 1; /**< BIST Status for CSM0 */ 1336 uint64_t csm1 : 1; /**< BIST Status for CSM1 */ 1337 uint64_t dif0 : 1; /**< BIST Status for DMA Instr0 */ 1338 uint64_t dif1 : 1; /**< BIST Status for DMA Instr0 */ 1339 uint64_t dif2 : 1; /**< BIST Status for DMA Instr0 */ 1340 uint64_t dif3 : 1; /**< BIST Status for DMA Instr0 */ 1341 uint64_t reserved_2_2 : 1; 1342 uint64_t msi : 1; /**< BIST Status for MSI Memory Map */ 1343 uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */ 1344#else 1345 uint64_t ncb_cmd : 1; 1346 uint64_t msi : 1; 1347 uint64_t reserved_2_2 : 1; 1348 uint64_t dif3 : 1; 1349 uint64_t dif2 : 1; 1350 uint64_t dif1 : 1; 1351 uint64_t dif0 : 1; 1352 uint64_t csm1 : 1; 1353 uint64_t csm0 : 1; 1354 uint64_t p2n1_p1 : 1; 1355 uint64_t p2n1_p0 : 1; 1356 uint64_t p2n1_n : 1; 1357 uint64_t p2n1_c1 : 1; 1358 uint64_t p2n1_c0 : 1; 1359 uint64_t p2n0_p1 : 1; 1360 uint64_t p2n0_p0 : 1; 1361 uint64_t p2n0_n : 1; 1362 uint64_t p2n0_c1 : 1; 1363 uint64_t p2n0_c0 : 1; 1364 uint64_t p2n0_co : 1; 1365 uint64_t p2n0_no : 1; 1366 uint64_t p2n0_po : 1; 1367 uint64_t p2n1_co : 1; 1368 uint64_t p2n1_no : 1; 1369 uint64_t p2n1_po : 1; 1370 uint64_t cpl_p1 : 1; 1371 uint64_t cpl_p0 : 1; 1372 uint64_t n2p1_o : 1; 1373 uint64_t n2p1_c : 1; 1374 uint64_t n2p0_o : 1; 1375 uint64_t n2p0_c : 1; 1376 uint64_t reserved_31_31 : 1; 1377 uint64_t d3_pst : 1; 1378 uint64_t d2_pst : 1; 1379 uint64_t d1_pst : 1; 1380 uint64_t d0_pst : 1; 1381 uint64_t reserved_36_47 : 12; 1382 uint64_t pkt_slm : 1; 1383 uint64_t pkt_ind : 1; 1384 uint64_t reserved_50_52 : 3; 1385 uint64_t pcsr_sl : 1; 1386 uint64_t pcsr_id : 1; 1387 uint64_t pcsr_cnt : 1; 1388 uint64_t pcsr_im : 1; 1389 uint64_t pcsr_int : 1; 1390 uint64_t pkt_pif : 1; 1391 uint64_t pcr_gim : 1; 1392 uint64_t reserved_60_62 : 3; 1393 uint64_t pkt_rdf : 1; 1394#endif 1395 } s; 1396 struct cvmx_npei_bist_status_cn52xx 1397 { 1398#if __BYTE_ORDER == __BIG_ENDIAN 1399 uint64_t pkt_rdf : 1; /**< BIST Status for PKT Read FIFO */ 1400 uint64_t reserved_60_62 : 3; 1401 uint64_t pcr_gim : 1; /**< BIST Status for PKT Gather Instr MEM */ 1402 uint64_t pkt_pif : 1; /**< BIST Status for PKT INB FIFO */ 1403 uint64_t pcsr_int : 1; /**< BIST Status for PKT OUTB Interrupt MEM */ 1404 uint64_t pcsr_im : 1; /**< BIST Status for PKT CSR Instr MEM */ 1405 uint64_t pcsr_cnt : 1; /**< BIST Status for PKT INB Count MEM */ 1406 uint64_t pcsr_id : 1; /**< BIST Status for PKT INB Instr Done MEM */ 1407 uint64_t pcsr_sl : 1; /**< BIST Status for PKT OUTB SLIST MEM */ 1408 uint64_t pkt_imem : 1; /**< BIST Status for PKT OUTB IFIFO */ 1409 uint64_t pkt_pfm : 1; /**< BIST Status for PKT Front MEM */ 1410 uint64_t pkt_pof : 1; /**< BIST Status for PKT OUTB FIFO */ 1411 uint64_t reserved_48_49 : 2; 1412 uint64_t pkt_pop0 : 1; /**< BIST Status for PKT OUTB Slist0 */ 1413 uint64_t pkt_pop1 : 1; /**< BIST Status for PKT OUTB Slist1 */ 1414 uint64_t d0_mem : 1; /**< BIST Status for DMA MEM 0 */ 1415 uint64_t d1_mem : 1; /**< BIST Status for DMA MEM 1 */ 1416 uint64_t d2_mem : 1; /**< BIST Status for DMA MEM 2 */ 1417 uint64_t d3_mem : 1; /**< BIST Status for DMA MEM 3 */ 1418 uint64_t d4_mem : 1; /**< BIST Status for DMA MEM 4 */ 1419 uint64_t ds_mem : 1; /**< BIST Status for DMA Memory */ 1420 uint64_t reserved_36_39 : 4; 1421 uint64_t d0_pst : 1; /**< BIST Status for DMA0 Pcie Store */ 1422 uint64_t d1_pst : 1; /**< BIST Status for DMA1 Pcie Store */ 1423 uint64_t d2_pst : 1; /**< BIST Status for DMA2 Pcie Store */ 1424 uint64_t d3_pst : 1; /**< BIST Status for DMA3 Pcie Store */ 1425 uint64_t d4_pst : 1; /**< BIST Status for DMA4 Pcie Store */ 1426 uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */ 1427 uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */ 1428 uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */ 1429 uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */ 1430 uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */ 1431 uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */ 1432 uint64_t p2n1_po : 1; /**< BIST Status for P2N Port1 P Order */ 1433 uint64_t p2n1_no : 1; /**< BIST Status for P2N Port1 N Order */ 1434 uint64_t p2n1_co : 1; /**< BIST Status for P2N Port1 C Order */ 1435 uint64_t p2n0_po : 1; /**< BIST Status for P2N Port0 P Order */ 1436 uint64_t p2n0_no : 1; /**< BIST Status for P2N Port0 N Order */ 1437 uint64_t p2n0_co : 1; /**< BIST Status for P2N Port0 C Order */ 1438 uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */ 1439 uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */ 1440 uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */ 1441 uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */ 1442 uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */ 1443 uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */ 1444 uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */ 1445 uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */ 1446 uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */ 1447 uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */ 1448 uint64_t csm0 : 1; /**< BIST Status for CSM0 */ 1449 uint64_t csm1 : 1; /**< BIST Status for CSM1 */ 1450 uint64_t dif0 : 1; /**< BIST Status for DMA Instr0 */ 1451 uint64_t dif1 : 1; /**< BIST Status for DMA Instr0 */ 1452 uint64_t dif2 : 1; /**< BIST Status for DMA Instr0 */ 1453 uint64_t dif3 : 1; /**< BIST Status for DMA Instr0 */ 1454 uint64_t dif4 : 1; /**< BIST Status for DMA Instr0 */ 1455 uint64_t msi : 1; /**< BIST Status for MSI Memory Map */ 1456 uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */ 1457#else 1458 uint64_t ncb_cmd : 1; 1459 uint64_t msi : 1; 1460 uint64_t dif4 : 1; 1461 uint64_t dif3 : 1; 1462 uint64_t dif2 : 1; 1463 uint64_t dif1 : 1; 1464 uint64_t dif0 : 1; 1465 uint64_t csm1 : 1; 1466 uint64_t csm0 : 1; 1467 uint64_t p2n1_p1 : 1; 1468 uint64_t p2n1_p0 : 1; 1469 uint64_t p2n1_n : 1; 1470 uint64_t p2n1_c1 : 1; 1471 uint64_t p2n1_c0 : 1; 1472 uint64_t p2n0_p1 : 1; 1473 uint64_t p2n0_p0 : 1; 1474 uint64_t p2n0_n : 1; 1475 uint64_t p2n0_c1 : 1; 1476 uint64_t p2n0_c0 : 1; 1477 uint64_t p2n0_co : 1; 1478 uint64_t p2n0_no : 1; 1479 uint64_t p2n0_po : 1; 1480 uint64_t p2n1_co : 1; 1481 uint64_t p2n1_no : 1; 1482 uint64_t p2n1_po : 1; 1483 uint64_t cpl_p1 : 1; 1484 uint64_t cpl_p0 : 1; 1485 uint64_t n2p1_o : 1; 1486 uint64_t n2p1_c : 1; 1487 uint64_t n2p0_o : 1; 1488 uint64_t n2p0_c : 1; 1489 uint64_t d4_pst : 1; 1490 uint64_t d3_pst : 1; 1491 uint64_t d2_pst : 1; 1492 uint64_t d1_pst : 1; 1493 uint64_t d0_pst : 1; 1494 uint64_t reserved_36_39 : 4; 1495 uint64_t ds_mem : 1; 1496 uint64_t d4_mem : 1; 1497 uint64_t d3_mem : 1; 1498 uint64_t d2_mem : 1; 1499 uint64_t d1_mem : 1; 1500 uint64_t d0_mem : 1; 1501 uint64_t pkt_pop1 : 1; 1502 uint64_t pkt_pop0 : 1; 1503 uint64_t reserved_48_49 : 2; 1504 uint64_t pkt_pof : 1; 1505 uint64_t pkt_pfm : 1; 1506 uint64_t pkt_imem : 1; 1507 uint64_t pcsr_sl : 1; 1508 uint64_t pcsr_id : 1; 1509 uint64_t pcsr_cnt : 1; 1510 uint64_t pcsr_im : 1; 1511 uint64_t pcsr_int : 1; 1512 uint64_t pkt_pif : 1; 1513 uint64_t pcr_gim : 1; 1514 uint64_t reserved_60_62 : 3; 1515 uint64_t pkt_rdf : 1; 1516#endif 1517 } cn52xx; 1518 struct cvmx_npei_bist_status_cn52xxp1 1519 { 1520#if __BYTE_ORDER == __BIG_ENDIAN 1521 uint64_t reserved_46_63 : 18; 1522 uint64_t d0_mem0 : 1; /**< BIST Status for DMA0 Memory */ 1523 uint64_t d1_mem1 : 1; /**< BIST Status for DMA1 Memory */ 1524 uint64_t d2_mem2 : 1; /**< BIST Status for DMA2 Memory */ 1525 uint64_t d3_mem3 : 1; /**< BIST Status for DMA3 Memory */ 1526 uint64_t dr0_mem : 1; /**< BIST Status for DMA0 Store */ 1527 uint64_t d0_mem : 1; /**< BIST Status for DMA0 Memory */ 1528 uint64_t d1_mem : 1; /**< BIST Status for DMA1 Memory */ 1529 uint64_t d2_mem : 1; /**< BIST Status for DMA2 Memory */ 1530 uint64_t d3_mem : 1; /**< BIST Status for DMA3 Memory */ 1531 uint64_t dr1_mem : 1; /**< BIST Status for DMA1 Store */ 1532 uint64_t d0_pst : 1; /**< BIST Status for DMA0 Pcie Store */ 1533 uint64_t d1_pst : 1; /**< BIST Status for DMA1 Pcie Store */ 1534 uint64_t d2_pst : 1; /**< BIST Status for DMA2 Pcie Store */ 1535 uint64_t d3_pst : 1; /**< BIST Status for DMA3 Pcie Store */ 1536 uint64_t dr2_mem : 1; /**< BIST Status for DMA2 Store */ 1537 uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */ 1538 uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */ 1539 uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */ 1540 uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */ 1541 uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */ 1542 uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */ 1543 uint64_t p2n1_po : 1; /**< BIST Status for P2N Port1 P Order */ 1544 uint64_t p2n1_no : 1; /**< BIST Status for P2N Port1 N Order */ 1545 uint64_t p2n1_co : 1; /**< BIST Status for P2N Port1 C Order */ 1546 uint64_t p2n0_po : 1; /**< BIST Status for P2N Port0 P Order */ 1547 uint64_t p2n0_no : 1; /**< BIST Status for P2N Port0 N Order */ 1548 uint64_t p2n0_co : 1; /**< BIST Status for P2N Port0 C Order */ 1549 uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */ 1550 uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */ 1551 uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */ 1552 uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */ 1553 uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */ 1554 uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */ 1555 uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */ 1556 uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */ 1557 uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */ 1558 uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */ 1559 uint64_t csm0 : 1; /**< BIST Status for CSM0 */ 1560 uint64_t csm1 : 1; /**< BIST Status for CSM1 */ 1561 uint64_t dif0 : 1; /**< BIST Status for DMA Instr0 */ 1562 uint64_t dif1 : 1; /**< BIST Status for DMA Instr0 */ 1563 uint64_t dif2 : 1; /**< BIST Status for DMA Instr0 */ 1564 uint64_t dif3 : 1; /**< BIST Status for DMA Instr0 */ 1565 uint64_t dr3_mem : 1; /**< BIST Status for DMA3 Store */ 1566 uint64_t msi : 1; /**< BIST Status for MSI Memory Map */ 1567 uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */ 1568#else 1569 uint64_t ncb_cmd : 1; 1570 uint64_t msi : 1; 1571 uint64_t dr3_mem : 1; 1572 uint64_t dif3 : 1; 1573 uint64_t dif2 : 1; 1574 uint64_t dif1 : 1; 1575 uint64_t dif0 : 1; 1576 uint64_t csm1 : 1; 1577 uint64_t csm0 : 1; 1578 uint64_t p2n1_p1 : 1; 1579 uint64_t p2n1_p0 : 1; 1580 uint64_t p2n1_n : 1; 1581 uint64_t p2n1_c1 : 1; 1582 uint64_t p2n1_c0 : 1; 1583 uint64_t p2n0_p1 : 1; 1584 uint64_t p2n0_p0 : 1; 1585 uint64_t p2n0_n : 1; 1586 uint64_t p2n0_c1 : 1; 1587 uint64_t p2n0_c0 : 1; 1588 uint64_t p2n0_co : 1; 1589 uint64_t p2n0_no : 1; 1590 uint64_t p2n0_po : 1; 1591 uint64_t p2n1_co : 1; 1592 uint64_t p2n1_no : 1; 1593 uint64_t p2n1_po : 1; 1594 uint64_t cpl_p1 : 1; 1595 uint64_t cpl_p0 : 1; 1596 uint64_t n2p1_o : 1; 1597 uint64_t n2p1_c : 1; 1598 uint64_t n2p0_o : 1; 1599 uint64_t n2p0_c : 1; 1600 uint64_t dr2_mem : 1; 1601 uint64_t d3_pst : 1; 1602 uint64_t d2_pst : 1; 1603 uint64_t d1_pst : 1; 1604 uint64_t d0_pst : 1; 1605 uint64_t dr1_mem : 1; 1606 uint64_t d3_mem : 1; 1607 uint64_t d2_mem : 1; 1608 uint64_t d1_mem : 1; 1609 uint64_t d0_mem : 1; 1610 uint64_t dr0_mem : 1; 1611 uint64_t d3_mem3 : 1; 1612 uint64_t d2_mem2 : 1; 1613 uint64_t d1_mem1 : 1; 1614 uint64_t d0_mem0 : 1; 1615 uint64_t reserved_46_63 : 18; 1616#endif 1617 } cn52xxp1; 1618 struct cvmx_npei_bist_status_cn52xx cn56xx; 1619 struct cvmx_npei_bist_status_cn56xxp1 1620 { 1621#if __BYTE_ORDER == __BIG_ENDIAN 1622 uint64_t reserved_58_63 : 6; 1623 uint64_t pcsr_int : 1; /**< BIST Status for PKT pout_int_bstatus */ 1624 uint64_t pcsr_im : 1; /**< BIST Status for PKT pcsr_instr_mem_bstatus */ 1625 uint64_t pcsr_cnt : 1; /**< BIST Status for PKT pin_cnt_bstatus */ 1626 uint64_t pcsr_id : 1; /**< BIST Status for PKT pcsr_in_done_bstatus */ 1627 uint64_t pcsr_sl : 1; /**< BIST Status for PKT pcsr_slist_bstatus */ 1628 uint64_t pkt_pout : 1; /**< BIST Status for PKT OUT Count MEM */ 1629 uint64_t pkt_imem : 1; /**< BIST Status for PKT Instruction MEM */ 1630 uint64_t pkt_cntm : 1; /**< BIST Status for PKT Count MEM */ 1631 uint64_t pkt_ind : 1; /**< BIST Status for PKT Instruction Done MEM */ 1632 uint64_t pkt_slm : 1; /**< BIST Status for PKT SList MEM */ 1633 uint64_t pkt_odf : 1; /**< BIST Status for PKT Output Data FIFO */ 1634 uint64_t pkt_oif : 1; /**< BIST Status for PKT Output INFO FIFO */ 1635 uint64_t pkt_out : 1; /**< BIST Status for PKT Output FIFO */ 1636 uint64_t pkt_i0 : 1; /**< BIST Status for PKT Instr0 */ 1637 uint64_t pkt_i1 : 1; /**< BIST Status for PKT Instr1 */ 1638 uint64_t pkt_s0 : 1; /**< BIST Status for PKT Slist0 */ 1639 uint64_t pkt_s1 : 1; /**< BIST Status for PKT Slist1 */ 1640 uint64_t d0_mem : 1; /**< BIST Status for DMA0 Memory */ 1641 uint64_t d1_mem : 1; /**< BIST Status for DMA1 Memory */ 1642 uint64_t d2_mem : 1; /**< BIST Status for DMA2 Memory */ 1643 uint64_t d3_mem : 1; /**< BIST Status for DMA3 Memory */ 1644 uint64_t d4_mem : 1; /**< BIST Status for DMA4 Memory */ 1645 uint64_t d0_pst : 1; /**< BIST Status for DMA0 Pcie Store */ 1646 uint64_t d1_pst : 1; /**< BIST Status for DMA1 Pcie Store */ 1647 uint64_t d2_pst : 1; /**< BIST Status for DMA2 Pcie Store */ 1648 uint64_t d3_pst : 1; /**< BIST Status for DMA3 Pcie Store */ 1649 uint64_t d4_pst : 1; /**< BIST Status for DMA4 Pcie Store */ 1650 uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */ 1651 uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */ 1652 uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */ 1653 uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */ 1654 uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */ 1655 uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */ 1656 uint64_t p2n1_po : 1; /**< BIST Status for P2N Port1 P Order */ 1657 uint64_t p2n1_no : 1; /**< BIST Status for P2N Port1 N Order */ 1658 uint64_t p2n1_co : 1; /**< BIST Status for P2N Port1 C Order */ 1659 uint64_t p2n0_po : 1; /**< BIST Status for P2N Port0 P Order */ 1660 uint64_t p2n0_no : 1; /**< BIST Status for P2N Port0 N Order */ 1661 uint64_t p2n0_co : 1; /**< BIST Status for P2N Port0 C Order */ 1662 uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */ 1663 uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */ 1664 uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */ 1665 uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */ 1666 uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */ 1667 uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */ 1668 uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */ 1669 uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */ 1670 uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */ 1671 uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */ 1672 uint64_t csm0 : 1; /**< BIST Status for CSM0 */ 1673 uint64_t csm1 : 1; /**< BIST Status for CSM1 */ 1674 uint64_t dif0 : 1; /**< BIST Status for DMA Instr0 */ 1675 uint64_t dif1 : 1; /**< BIST Status for DMA Instr0 */ 1676 uint64_t dif2 : 1; /**< BIST Status for DMA Instr0 */ 1677 uint64_t dif3 : 1; /**< BIST Status for DMA Instr0 */ 1678 uint64_t dif4 : 1; /**< BIST Status for DMA Instr0 */ 1679 uint64_t msi : 1; /**< BIST Status for MSI Memory Map */ 1680 uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */ 1681#else 1682 uint64_t ncb_cmd : 1; 1683 uint64_t msi : 1; 1684 uint64_t dif4 : 1; 1685 uint64_t dif3 : 1; 1686 uint64_t dif2 : 1; 1687 uint64_t dif1 : 1; 1688 uint64_t dif0 : 1; 1689 uint64_t csm1 : 1; 1690 uint64_t csm0 : 1; 1691 uint64_t p2n1_p1 : 1; 1692 uint64_t p2n1_p0 : 1; 1693 uint64_t p2n1_n : 1; 1694 uint64_t p2n1_c1 : 1; 1695 uint64_t p2n1_c0 : 1; 1696 uint64_t p2n0_p1 : 1; 1697 uint64_t p2n0_p0 : 1; 1698 uint64_t p2n0_n : 1; 1699 uint64_t p2n0_c1 : 1; 1700 uint64_t p2n0_c0 : 1; 1701 uint64_t p2n0_co : 1; 1702 uint64_t p2n0_no : 1; 1703 uint64_t p2n0_po : 1; 1704 uint64_t p2n1_co : 1; 1705 uint64_t p2n1_no : 1; 1706 uint64_t p2n1_po : 1; 1707 uint64_t cpl_p1 : 1; 1708 uint64_t cpl_p0 : 1; 1709 uint64_t n2p1_o : 1; 1710 uint64_t n2p1_c : 1; 1711 uint64_t n2p0_o : 1; 1712 uint64_t n2p0_c : 1; 1713 uint64_t d4_pst : 1; 1714 uint64_t d3_pst : 1; 1715 uint64_t d2_pst : 1; 1716 uint64_t d1_pst : 1; 1717 uint64_t d0_pst : 1; 1718 uint64_t d4_mem : 1; 1719 uint64_t d3_mem : 1; 1720 uint64_t d2_mem : 1; 1721 uint64_t d1_mem : 1; 1722 uint64_t d0_mem : 1; 1723 uint64_t pkt_s1 : 1; 1724 uint64_t pkt_s0 : 1; 1725 uint64_t pkt_i1 : 1; 1726 uint64_t pkt_i0 : 1; 1727 uint64_t pkt_out : 1; 1728 uint64_t pkt_oif : 1; 1729 uint64_t pkt_odf : 1; 1730 uint64_t pkt_slm : 1; 1731 uint64_t pkt_ind : 1; 1732 uint64_t pkt_cntm : 1; 1733 uint64_t pkt_imem : 1; 1734 uint64_t pkt_pout : 1; 1735 uint64_t pcsr_sl : 1; 1736 uint64_t pcsr_id : 1; 1737 uint64_t pcsr_cnt : 1; 1738 uint64_t pcsr_im : 1; 1739 uint64_t pcsr_int : 1; 1740 uint64_t reserved_58_63 : 6; 1741#endif 1742 } cn56xxp1; 1743}; 1744typedef union cvmx_npei_bist_status cvmx_npei_bist_status_t; 1745 1746/** 1747 * cvmx_npei_bist_status2 1748 * 1749 * NPEI_BIST_STATUS2 = NPI's BIST Status Register2 1750 * 1751 * Results from BIST runs of NPEI's memories. 1752 */ 1753union cvmx_npei_bist_status2 1754{ 1755 uint64_t u64; 1756 struct cvmx_npei_bist_status2_s 1757 { 1758#if __BYTE_ORDER == __BIG_ENDIAN 1759 uint64_t reserved_14_63 : 50; 1760 uint64_t prd_tag : 1; /**< BIST Status for DMA PCIE RD Tag MEM */ 1761 uint64_t prd_st0 : 1; /**< BIST Status for DMA PCIE RD state MEM 0 */ 1762 uint64_t prd_st1 : 1; /**< BIST Status for DMA PCIE RD state MEM 1 */ 1763 uint64_t prd_err : 1; /**< BIST Status for DMA PCIE RD ERR state MEM */ 1764 uint64_t nrd_st : 1; /**< BIST Status for DMA L2C RD state MEM */ 1765 uint64_t nwe_st : 1; /**< BIST Status for DMA L2C WR state MEM */ 1766 uint64_t nwe_wr0 : 1; /**< BIST Status for DMA L2C WR MEM 0 */ 1767 uint64_t nwe_wr1 : 1; /**< BIST Status for DMA L2C WR MEM 1 */ 1768 uint64_t pkt_rd : 1; /**< BIST Status for Inbound PKT MEM */ 1769 uint64_t psc_p0 : 1; /**< BIST Status for PSC TLP 0 MEM */ 1770 uint64_t psc_p1 : 1; /**< BIST Status for PSC TLP 1 MEM */ 1771 uint64_t pkt_gd : 1; /**< BIST Status for PKT OUTB Gather Data FIFO */ 1772 uint64_t pkt_gl : 1; /**< BIST Status for PKT_OUTB Gather List FIFO */ 1773 uint64_t pkt_blk : 1; /**< BIST Status for PKT OUTB Blocked FIFO */ 1774#else 1775 uint64_t pkt_blk : 1; 1776 uint64_t pkt_gl : 1; 1777 uint64_t pkt_gd : 1; 1778 uint64_t psc_p1 : 1; 1779 uint64_t psc_p0 : 1; 1780 uint64_t pkt_rd : 1; 1781 uint64_t nwe_wr1 : 1; 1782 uint64_t nwe_wr0 : 1; 1783 uint64_t nwe_st : 1; 1784 uint64_t nrd_st : 1; 1785 uint64_t prd_err : 1; 1786 uint64_t prd_st1 : 1; 1787 uint64_t prd_st0 : 1; 1788 uint64_t prd_tag : 1; 1789 uint64_t reserved_14_63 : 50; 1790#endif 1791 } s; 1792 struct cvmx_npei_bist_status2_s cn52xx; 1793 struct cvmx_npei_bist_status2_s cn56xx; 1794}; 1795typedef union cvmx_npei_bist_status2 cvmx_npei_bist_status2_t; 1796 1797/** 1798 * cvmx_npei_ctl_port0 1799 * 1800 * NPEI_CTL_PORT0 = NPEI's Control Port 0 1801 * 1802 * Contains control for access for Port0 1803 */ 1804union cvmx_npei_ctl_port0 1805{ 1806 uint64_t u64; 1807 struct cvmx_npei_ctl_port0_s 1808 { 1809#if __BYTE_ORDER == __BIG_ENDIAN 1810 uint64_t reserved_21_63 : 43; 1811 uint64_t waitl_com : 1; /**< When set '1' casues the NPI to wait for a commit 1812 from the L2C before sending additional completions 1813 to the L2C from the PCIe. 1814 Set this for more conservative behavior. Clear 1815 this for more aggressive, higher-performance 1816 behavior */ 1817 uint64_t intd : 1; /**< When '0' Intd wire asserted. Before mapping. */ 1818 uint64_t intc : 1; /**< When '0' Intc wire asserted. Before mapping. */ 1819 uint64_t intb : 1; /**< When '0' Intb wire asserted. Before mapping. */ 1820 uint64_t inta : 1; /**< When '0' Inta wire asserted. Before mapping. */ 1821 uint64_t intd_map : 2; /**< Maps INTD to INTA(00), INTB(01), INTC(10) or 1822 INTD (11). */ 1823 uint64_t intc_map : 2; /**< Maps INTC to INTA(00), INTB(01), INTC(10) or 1824 INTD (11). */ 1825 uint64_t intb_map : 2; /**< Maps INTB to INTA(00), INTB(01), INTC(10) or 1826 INTD (11). */ 1827 uint64_t inta_map : 2; /**< Maps INTA to INTA(00), INTB(01), INTC(10) or 1828 INTD (11). */ 1829 uint64_t ctlp_ro : 1; /**< Relaxed ordering enable for Completion TLPS. */ 1830 uint64_t reserved_6_6 : 1; 1831 uint64_t ptlp_ro : 1; /**< Relaxed ordering enable for Posted TLPS. */ 1832 uint64_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when 1833 clear '0' BAR2 access will cause UR responses. */ 1834 uint64_t bar2_esx : 2; /**< Value will be XORed with pci-address[37:36] to 1835 determine the endian swap mode. */ 1836 uint64_t bar2_cax : 1; /**< Value will be XORed with pcie-address[38] to 1837 determine the L2 cache attribute. 1838 Not cached in L2 if XOR result is 1 */ 1839 uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit 1840 from the L2C before sending additional stores to 1841 the L2C from the PCIe. 1842 Most applications will not notice a difference, so 1843 should not set this bit. Setting the bit is more 1844 conservative on ordering, lower performance */ 1845#else 1846 uint64_t wait_com : 1; 1847 uint64_t bar2_cax : 1; 1848 uint64_t bar2_esx : 2; 1849 uint64_t bar2_enb : 1; 1850 uint64_t ptlp_ro : 1; 1851 uint64_t reserved_6_6 : 1; 1852 uint64_t ctlp_ro : 1; 1853 uint64_t inta_map : 2; 1854 uint64_t intb_map : 2; 1855 uint64_t intc_map : 2; 1856 uint64_t intd_map : 2; 1857 uint64_t inta : 1; 1858 uint64_t intb : 1; 1859 uint64_t intc : 1; 1860 uint64_t intd : 1; 1861 uint64_t waitl_com : 1; 1862 uint64_t reserved_21_63 : 43; 1863#endif 1864 } s; 1865 struct cvmx_npei_ctl_port0_s cn52xx; 1866 struct cvmx_npei_ctl_port0_s cn52xxp1; 1867 struct cvmx_npei_ctl_port0_s cn56xx; 1868 struct cvmx_npei_ctl_port0_s cn56xxp1; 1869}; 1870typedef union cvmx_npei_ctl_port0 cvmx_npei_ctl_port0_t; 1871 1872/** 1873 * cvmx_npei_ctl_port1 1874 * 1875 * NPEI_CTL_PORT1 = NPEI's Control Port1 1876 * 1877 * Contains control for access for Port1 1878 */ 1879union cvmx_npei_ctl_port1 1880{ 1881 uint64_t u64; 1882 struct cvmx_npei_ctl_port1_s 1883 { 1884#if __BYTE_ORDER == __BIG_ENDIAN 1885 uint64_t reserved_21_63 : 43; 1886 uint64_t waitl_com : 1; /**< When set '1' casues the NPI to wait for a commit 1887 from the L2C before sending additional completions 1888 to the L2C from the PCIe. 1889 Set this for more conservative behavior. Clear 1890 this for more aggressive, higher-performance */ 1891 uint64_t intd : 1; /**< When '0' Intd wire asserted. Before mapping. */ 1892 uint64_t intc : 1; /**< When '0' Intc wire asserted. Before mapping. */ 1893 uint64_t intb : 1; /**< When '0' Intv wire asserted. Before mapping. */ 1894 uint64_t inta : 1; /**< When '0' Inta wire asserted. Before mapping. */ 1895 uint64_t intd_map : 2; /**< Maps INTD to INTA(00), INTB(01), INTC(10) or 1896 INTD (11). */ 1897 uint64_t intc_map : 2; /**< Maps INTC to INTA(00), INTB(01), INTC(10) or 1898 INTD (11). */ 1899 uint64_t intb_map : 2; /**< Maps INTB to INTA(00), INTB(01), INTC(10) or 1900 INTD (11). */ 1901 uint64_t inta_map : 2; /**< Maps INTA to INTA(00), INTB(01), INTC(10) or 1902 INTD (11). */ 1903 uint64_t ctlp_ro : 1; /**< Relaxed ordering enable for Completion TLPS. */ 1904 uint64_t reserved_6_6 : 1; 1905 uint64_t ptlp_ro : 1; /**< Relaxed ordering enable for Posted TLPS. */ 1906 uint64_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when 1907 clear '0' BAR2 access will cause UR responses. */ 1908 uint64_t bar2_esx : 2; /**< Value will be XORed with pci-address[37:36] to 1909 determine the endian swap mode. */ 1910 uint64_t bar2_cax : 1; /**< Value will be XORed with pcie-address[38] to 1911 determine the L2 cache attribute. 1912 Not cached in L2 if XOR result is 1 */ 1913 uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit 1914 from the L2C before sending additional stores to 1915 the L2C from the PCIe. 1916 Most applications will not notice a difference, so 1917 should not set this bit. Setting the bit is more 1918 conservative on ordering, lower performance */ 1919#else 1920 uint64_t wait_com : 1; 1921 uint64_t bar2_cax : 1; 1922 uint64_t bar2_esx : 2; 1923 uint64_t bar2_enb : 1; 1924 uint64_t ptlp_ro : 1; 1925 uint64_t reserved_6_6 : 1; 1926 uint64_t ctlp_ro : 1; 1927 uint64_t inta_map : 2; 1928 uint64_t intb_map : 2; 1929 uint64_t intc_map : 2; 1930 uint64_t intd_map : 2; 1931 uint64_t inta : 1; 1932 uint64_t intb : 1; 1933 uint64_t intc : 1; 1934 uint64_t intd : 1; 1935 uint64_t waitl_com : 1; 1936 uint64_t reserved_21_63 : 43; 1937#endif 1938 } s; 1939 struct cvmx_npei_ctl_port1_s cn52xx; 1940 struct cvmx_npei_ctl_port1_s cn52xxp1; 1941 struct cvmx_npei_ctl_port1_s cn56xx; 1942 struct cvmx_npei_ctl_port1_s cn56xxp1; 1943}; 1944typedef union cvmx_npei_ctl_port1 cvmx_npei_ctl_port1_t; 1945 1946/** 1947 * cvmx_npei_ctl_status 1948 * 1949 * NPEI_CTL_STATUS = NPEI Control Status Register 1950 * 1951 * Contains control and status for NPEI. Writes to this register are not oSrdered with writes/reads to the PCIe Memory space. 1952 * To ensure that a write has completed the user must read the register before making an access(i.e. PCIe memory space) 1953 * that requires the value of this register to be updated. 1954 */ 1955union cvmx_npei_ctl_status 1956{ 1957 uint64_t u64; 1958 struct cvmx_npei_ctl_status_s 1959 { 1960#if __BYTE_ORDER == __BIG_ENDIAN 1961 uint64_t reserved_44_63 : 20; 1962 uint64_t p1_ntags : 6; /**< Number of tags avaiable for PCIe Port1. 1963 In RC mode 1 tag is needed for each outbound TLP 1964 that requires a CPL TLP. In Endpoint mode the 1965 number of tags required for a TLP request is 1966 1 per 64-bytes of CPL data + 1. 1967 This field should only be written as part of 1968 reset sequence, before issuing any reads, CFGs, or 1969 IO transactions from the core(s). */ 1970 uint64_t p0_ntags : 6; /**< Number of tags avaiable for PCIe Port0. 1971 In RC mode 1 tag is needed for each outbound TLP 1972 that requires a CPL TLP. In Endpoint mode the 1973 number of tags required for a TLP request is 1974 1 per 64-bytes of CPL data + 1. 1975 This field should only be written as part of 1976 reset sequence, before issuing any reads, CFGs, or 1977 IO transactions from the core(s). */ 1978 uint64_t cfg_rtry : 16; /**< The time x 0x10000 in core clocks to wait for a 1979 CPL to a CFG RD that does not carry a Retry Status. 1980 Until such time that the timeout occurs and Retry 1981 Status is received for a CFG RD, the Read CFG Read 1982 will be resent. A value of 0 disables retries and 1983 treats a CPL Retry as a CPL UR. */ 1984 uint64_t ring_en : 1; /**< When '0' forces "relative Q position" received 1985 from PKO to be zero, and replicates the back- 1986 pressure indication for the first ring attached 1987 to a PKO port across all the rings attached to a 1988 PKO port. When '1' backpressure is on a per 1989 port/ring. */ 1990 uint64_t lnk_rst : 1; /**< Set when PCIe Core 0 request a link reset due to 1991 link down state. This bit is only reset on raw 1992 reset so it can be read for state to determine if 1993 a reset occured. Bit is cleared when a '1' is 1994 written to this field. */ 1995 uint64_t arb : 1; /**< PCIe switch arbitration mode. '0' == fixed priority 1996 NPEI, PCIe0, then PCIe1. '1' == round robin. */ 1997 uint64_t pkt_bp : 4; /**< Unused */ 1998 uint64_t host_mode : 1; /**< Host mode */ 1999 uint64_t chip_rev : 8; /**< The chip revision. */ 2000#else 2001 uint64_t chip_rev : 8; 2002 uint64_t host_mode : 1; 2003 uint64_t pkt_bp : 4; 2004 uint64_t arb : 1; 2005 uint64_t lnk_rst : 1; 2006 uint64_t ring_en : 1; 2007 uint64_t cfg_rtry : 16; 2008 uint64_t p0_ntags : 6; 2009 uint64_t p1_ntags : 6; 2010 uint64_t reserved_44_63 : 20; 2011#endif 2012 } s; 2013 struct cvmx_npei_ctl_status_s cn52xx; 2014 struct cvmx_npei_ctl_status_cn52xxp1 2015 { 2016#if __BYTE_ORDER == __BIG_ENDIAN 2017 uint64_t reserved_44_63 : 20; 2018 uint64_t p1_ntags : 6; /**< Number of tags avaiable for PCIe Port1. 2019 In RC mode 1 tag is needed for each outbound TLP 2020 that requires a CPL TLP. In Endpoint mode the 2021 number of tags required for a TLP request is 2022 1 per 64-bytes of CPL data + 1. 2023 This field should only be written as part of 2024 reset sequence, before issuing any reads, CFGs, or 2025 IO transactions from the core(s). */ 2026 uint64_t p0_ntags : 6; /**< Number of tags avaiable for PCIe Port0. 2027 In RC mode 1 tag is needed for each outbound TLP 2028 that requires a CPL TLP. In Endpoint mode the 2029 number of tags required for a TLP request is 2030 1 per 64-bytes of CPL data + 1. 2031 This field should only be written as part of 2032 reset sequence, before issuing any reads, CFGs, or 2033 IO transactions from the core(s). */ 2034 uint64_t cfg_rtry : 16; /**< The time x 0x10000 in core clocks to wait for a 2035 CPL to a CFG RD that does not carry a Retry Status. 2036 Until such time that the timeout occurs and Retry 2037 Status is received for a CFG RD, the Read CFG Read 2038 will be resent. A value of 0 disables retries and 2039 treats a CPL Retry as a CPL UR. */ 2040 uint64_t reserved_15_15 : 1; 2041 uint64_t lnk_rst : 1; /**< Set when PCIe Core 0 request a link reset due to 2042 link down state. This bit is only reset on raw 2043 reset so it can be read for state to determine if 2044 a reset occured. Bit is cleared when a '1' is 2045 written to this field. */ 2046 uint64_t arb : 1; /**< PCIe switch arbitration mode. '0' == fixed priority 2047 NPEI, PCIe0, then PCIe1. '1' == round robin. */ 2048 uint64_t reserved_9_12 : 4; 2049 uint64_t host_mode : 1; /**< Host mode */ 2050 uint64_t chip_rev : 8; /**< The chip revision. */ 2051#else 2052 uint64_t chip_rev : 8; 2053 uint64_t host_mode : 1; 2054 uint64_t reserved_9_12 : 4; 2055 uint64_t arb : 1; 2056 uint64_t lnk_rst : 1; 2057 uint64_t reserved_15_15 : 1; 2058 uint64_t cfg_rtry : 16; 2059 uint64_t p0_ntags : 6; 2060 uint64_t p1_ntags : 6; 2061 uint64_t reserved_44_63 : 20; 2062#endif 2063 } cn52xxp1; 2064 struct cvmx_npei_ctl_status_s cn56xx; 2065 struct cvmx_npei_ctl_status_cn56xxp1 2066 { 2067#if __BYTE_ORDER == __BIG_ENDIAN 2068 uint64_t reserved_15_63 : 49; 2069 uint64_t lnk_rst : 1; /**< Set when PCIe Core 0 request a link reset due to 2070 link down state. This bit is only reset on raw 2071 reset so it can be read for state to determine if 2072 a reset occured. Bit is cleared when a '1' is 2073 written to this field. */ 2074 uint64_t arb : 1; /**< PCIe switch arbitration mode. '0' == fixed priority 2075 NPEI, PCIe0, then PCIe1. '1' == round robin. */ 2076 uint64_t pkt_bp : 4; /**< Unused */ 2077 uint64_t host_mode : 1; /**< Host mode */ 2078 uint64_t chip_rev : 8; /**< The chip revision. */ 2079#else 2080 uint64_t chip_rev : 8; 2081 uint64_t host_mode : 1; 2082 uint64_t pkt_bp : 4; 2083 uint64_t arb : 1; 2084 uint64_t lnk_rst : 1; 2085 uint64_t reserved_15_63 : 49; 2086#endif 2087 } cn56xxp1; 2088}; 2089typedef union cvmx_npei_ctl_status cvmx_npei_ctl_status_t; 2090 2091/** 2092 * cvmx_npei_ctl_status2 2093 * 2094 * NPEI_CTL_STATUS2 = NPEI's Control Status2 Register 2095 * 2096 * Contains control and status for NPEI. 2097 * Writes to this register are not ordered with writes/reads to the PCI Memory space. 2098 * To ensure that a write has completed the user must read the register before 2099 * making an access(i.e. PCI memory space) that requires the value of this register to be updated. 2100 */ 2101union cvmx_npei_ctl_status2 2102{ 2103 uint64_t u64; 2104 struct cvmx_npei_ctl_status2_s 2105 { 2106#if __BYTE_ORDER == __BIG_ENDIAN 2107 uint64_t reserved_16_63 : 48; 2108 uint64_t mps : 1; /**< Max Payload Size 2109 0 = 128B 2110 1 = 256B 2111 Note: PCIE*_CFG030[MPS] must be set to the same 2112 value for proper function. */ 2113 uint64_t mrrs : 3; /**< Max Read Request Size 2114 0 = 128B 2115 1 = 256B 2116 2 = 512B 2117 3 = 1024B 2118 4 = 2048B 2119 5 = 4096B 2120 Note: This field must not exceed the desired 2121 max read request size. This means this field 2122 should not exceed PCIE*_CFG030[MRRS]. */ 2123 uint64_t c1_w_flt : 1; /**< When '1' enables the window filter for reads and 2124 writes using the window registers. 2125 PCIE-Port1. 2126 Unfilter writes are: 2127 MIO, SubId0 2128 MIO, SubId7 2129 NPEI, SubId0 2130 NPEI, SubId7 2131 POW, SubId7 2132 IPD, SubId7 2133 USBN0, SubId7 2134 Unfiltered Reads are: 2135 MIO, SubId0 2136 MIO, SubId7 2137 NPEI, SubId0 2138 NPEI, SubId7 2139 POW, SubId1 2140 POW, SubId2 2141 POW, SubId3 2142 POW, SubId7 2143 IPD, SubId7 2144 USBN0, SubId7 */ 2145 uint64_t c0_w_flt : 1; /**< When '1' enables the window filter for reads and 2146 writes using the window registers. 2147 PCIE-Port0. 2148 Unfilter writes are: 2149 MIO, SubId0 2150 MIO, SubId7 2151 NPEI, SubId0 2152 NPEI, SubId7 2153 POW, SubId7 2154 IPD, SubId7 2155 USBN0, SubId7 2156 Unfiltered Reads are: 2157 MIO, SubId0 2158 MIO, SubId7 2159 NPEI, SubId0 2160 NPEI, SubId7 2161 POW, SubId1 2162 POW, SubId2 2163 POW, SubId3 2164 POW, SubId7 2165 IPD, SubId7 2166 USBN0, SubId7 */ 2167 uint64_t c1_b1_s : 3; /**< Pcie-Port1, Bar1 Size. 1 == 64MB, 2 == 128MB, 2168 3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB, 2169 0 and 7 are reserved. */ 2170 uint64_t c0_b1_s : 3; /**< Pcie-Port0, Bar1 Size. 1 == 64MB, 2 == 128MB, 2171 3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB, 2172 0 and 7 are reserved. */ 2173 uint64_t c1_wi_d : 1; /**< When set '1' disables access to the Window 2174 Registers from the PCIe-Port1. */ 2175 uint64_t c1_b0_d : 1; /**< When set '1' disables access from PCIe-Port1 to 2176 BAR-0 address offsets: Less Than 0x270, 2177 Greater than 0x270 AND less than 0x0520, 0x3BC0, 2178 0x3CD0. */ 2179 uint64_t c0_wi_d : 1; /**< When set '1' disables access to the Window 2180 Registers from the PCIe-Port0. */ 2181 uint64_t c0_b0_d : 1; /**< When set '1' disables access from PCIe-Port0 to 2182 BAR-0 address offsets: Less Than 0x270, 2183 Greater than 0x270 AND less than 0x0520, 0x3BC0, 2184 0x3CD0. */ 2185#else 2186 uint64_t c0_b0_d : 1; 2187 uint64_t c0_wi_d : 1; 2188 uint64_t c1_b0_d : 1; 2189 uint64_t c1_wi_d : 1; 2190 uint64_t c0_b1_s : 3; 2191 uint64_t c1_b1_s : 3; 2192 uint64_t c0_w_flt : 1; 2193 uint64_t c1_w_flt : 1; 2194 uint64_t mrrs : 3; 2195 uint64_t mps : 1; 2196 uint64_t reserved_16_63 : 48; 2197#endif 2198 } s; 2199 struct cvmx_npei_ctl_status2_s cn52xx; 2200 struct cvmx_npei_ctl_status2_s cn52xxp1; 2201 struct cvmx_npei_ctl_status2_s cn56xx; 2202 struct cvmx_npei_ctl_status2_s cn56xxp1; 2203}; 2204typedef union cvmx_npei_ctl_status2 cvmx_npei_ctl_status2_t; 2205 2206/** 2207 * cvmx_npei_data_out_cnt 2208 * 2209 * NPEI_DATA_OUT_CNT = NPEI DATA OUT COUNT 2210 * 2211 * The EXEC data out fifo-count and the data unload counter. 2212 */ 2213union cvmx_npei_data_out_cnt 2214{ 2215 uint64_t u64; 2216 struct cvmx_npei_data_out_cnt_s 2217 { 2218#if __BYTE_ORDER == __BIG_ENDIAN 2219 uint64_t reserved_44_63 : 20; 2220 uint64_t p1_ucnt : 16; /**< PCIE-Port1 Fifo Unload Count. This counter is 2221 incremented by '1' every time a word is removed 2222 from the Data Out FIFO, whose count is shown in 2223 P0_FCNT. */ 2224 uint64_t p1_fcnt : 6; /**< PCIE-Port1 Data Out Fifo Count. Number of address 2225 data words to be sent out the PCIe port presently 2226 buffered in the FIFO. */ 2227 uint64_t p0_ucnt : 16; /**< PCIE-Port0 Fifo Unload Count. This counter is 2228 incremented by '1' every time a word is removed 2229 from the Data Out FIFO, whose count is shown in 2230 P0_FCNT. */ 2231 uint64_t p0_fcnt : 6; /**< PCIE-Port0 Data Out Fifo Count. Number of address 2232 data words to be sent out the PCIe port presently 2233 buffered in the FIFO. */ 2234#else 2235 uint64_t p0_fcnt : 6; 2236 uint64_t p0_ucnt : 16; 2237 uint64_t p1_fcnt : 6; 2238 uint64_t p1_ucnt : 16; 2239 uint64_t reserved_44_63 : 20; 2240#endif 2241 } s; 2242 struct cvmx_npei_data_out_cnt_s cn52xx; 2243 struct cvmx_npei_data_out_cnt_s cn52xxp1; 2244 struct cvmx_npei_data_out_cnt_s cn56xx; 2245 struct cvmx_npei_data_out_cnt_s cn56xxp1; 2246}; 2247typedef union cvmx_npei_data_out_cnt cvmx_npei_data_out_cnt_t; 2248 2249/** 2250 * cvmx_npei_dbg_data 2251 * 2252 * NPEI_DBG_DATA = NPEI Debug Data Register 2253 * 2254 * Value returned on the debug-data lines from the RSLs 2255 */ 2256union cvmx_npei_dbg_data 2257{ 2258 uint64_t u64; 2259 struct cvmx_npei_dbg_data_s 2260 { 2261#if __BYTE_ORDER == __BIG_ENDIAN 2262 uint64_t reserved_28_63 : 36; 2263 uint64_t qlm0_rev_lanes : 1; /**< Lane reversal for PCIe port 0 */ 2264 uint64_t reserved_25_26 : 2; 2265 uint64_t qlm1_spd : 2; /**< Sets the QLM1 frequency 2266 0=1.25 Gbaud 2267 1=2.5 Gbaud 2268 2=3.125 Gbaud 2269 3=3.75 Gbaud */ 2270 uint64_t c_mul : 5; /**< PLL_MUL pins sampled at DCOK assertion 2271 Core frequency = 50MHz*C_MUL */ 2272 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the 2273 debug select value. */ 2274 uint64_t data : 17; /**< Value on the debug data lines. */ 2275#else 2276 uint64_t data : 17; 2277 uint64_t dsel_ext : 1; 2278 uint64_t c_mul : 5; 2279 uint64_t qlm1_spd : 2; 2280 uint64_t reserved_25_26 : 2; 2281 uint64_t qlm0_rev_lanes : 1; 2282 uint64_t reserved_28_63 : 36; 2283#endif 2284 } s; 2285 struct cvmx_npei_dbg_data_cn52xx 2286 { 2287#if __BYTE_ORDER == __BIG_ENDIAN 2288 uint64_t reserved_29_63 : 35; 2289 uint64_t qlm0_link_width : 1; /**< Link width of PCIe port 0 2290 0 = PCIe port 0 is 2 lanes, 2291 2 lane PCIe port 1 exists 2292 1 = PCIe port 0 is 4 lanes, 2293 PCIe port 1 does not exist */ 2294 uint64_t qlm0_rev_lanes : 1; /**< Lane reversal for PCIe port 0 */ 2295 uint64_t qlm1_mode : 2; /**< Sets the QLM1 Mode 2296 0=Reserved 2297 1=XAUI 2298 2=SGMII 2299 3=PICMG */ 2300 uint64_t qlm1_spd : 2; /**< Sets the QLM1 frequency 2301 0=1.25 Gbaud 2302 1=2.5 Gbaud 2303 2=3.125 Gbaud 2304 3=3.75 Gbaud */ 2305 uint64_t c_mul : 5; /**< PLL_MUL pins sampled at DCOK assertion 2306 Core frequency = 50MHz*C_MUL */ 2307 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the 2308 debug select value. */ 2309 uint64_t data : 17; /**< Value on the debug data lines. */ 2310#else 2311 uint64_t data : 17; 2312 uint64_t dsel_ext : 1; 2313 uint64_t c_mul : 5; 2314 uint64_t qlm1_spd : 2; 2315 uint64_t qlm1_mode : 2; 2316 uint64_t qlm0_rev_lanes : 1; 2317 uint64_t qlm0_link_width : 1; 2318 uint64_t reserved_29_63 : 35; 2319#endif 2320 } cn52xx; 2321 struct cvmx_npei_dbg_data_cn52xx cn52xxp1; 2322 struct cvmx_npei_dbg_data_cn56xx 2323 { 2324#if __BYTE_ORDER == __BIG_ENDIAN 2325 uint64_t reserved_29_63 : 35; 2326 uint64_t qlm2_rev_lanes : 1; /**< Lane reversal for PCIe port 1 */ 2327 uint64_t qlm0_rev_lanes : 1; /**< Lane reversal for PCIe port 0 */ 2328 uint64_t qlm3_spd : 2; /**< Sets the QLM3 frequency 2329 0=1.25 Gbaud 2330 1=2.5 Gbaud 2331 2=3.125 Gbaud 2332 3=3.75 Gbaud */ 2333 uint64_t qlm1_spd : 2; /**< Sets the QLM1 frequency 2334 0=1.25 Gbaud 2335 1=2.5 Gbaud 2336 2=3.125 Gbaud 2337 3=3.75 Gbaud */ 2338 uint64_t c_mul : 5; /**< PLL_MUL pins sampled at DCOK assertion 2339 Core frequency = 50MHz*C_MUL */ 2340 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the 2341 debug select value. */ 2342 uint64_t data : 17; /**< Value on the debug data lines. */ 2343#else 2344 uint64_t data : 17; 2345 uint64_t dsel_ext : 1; 2346 uint64_t c_mul : 5; 2347 uint64_t qlm1_spd : 2; 2348 uint64_t qlm3_spd : 2; 2349 uint64_t qlm0_rev_lanes : 1; 2350 uint64_t qlm2_rev_lanes : 1; 2351 uint64_t reserved_29_63 : 35; 2352#endif 2353 } cn56xx; 2354 struct cvmx_npei_dbg_data_cn56xx cn56xxp1; 2355}; 2356typedef union cvmx_npei_dbg_data cvmx_npei_dbg_data_t; 2357 2358/** 2359 * cvmx_npei_dbg_select 2360 * 2361 * NPEI_DBG_SELECT = Debug Select Register 2362 * 2363 * Contains the debug select value last written to the RSLs. 2364 */ 2365union cvmx_npei_dbg_select 2366{ 2367 uint64_t u64; 2368 struct cvmx_npei_dbg_select_s 2369 { 2370#if __BYTE_ORDER == __BIG_ENDIAN 2371 uint64_t reserved_16_63 : 48; 2372 uint64_t dbg_sel : 16; /**< When this register is written its value is sent to 2373 all RSLs. */ 2374#else 2375 uint64_t dbg_sel : 16; 2376 uint64_t reserved_16_63 : 48; 2377#endif 2378 } s; 2379 struct cvmx_npei_dbg_select_s cn52xx; 2380 struct cvmx_npei_dbg_select_s cn52xxp1; 2381 struct cvmx_npei_dbg_select_s cn56xx; 2382 struct cvmx_npei_dbg_select_s cn56xxp1; 2383}; 2384typedef union cvmx_npei_dbg_select cvmx_npei_dbg_select_t; 2385 2386/** 2387 * cvmx_npei_dma#_counts 2388 * 2389 * NPEI_DMA[0..4]_COUNTS = DMA Instruction Counts 2390 * 2391 * Values for determing the number of instructions for DMA[0..4] in the NPEI. 2392 */ 2393union cvmx_npei_dmax_counts 2394{ 2395 uint64_t u64; 2396 struct cvmx_npei_dmax_counts_s 2397 { 2398#if __BYTE_ORDER == __BIG_ENDIAN 2399 uint64_t reserved_39_63 : 25; 2400 uint64_t fcnt : 7; /**< Number of words in the Instruction FIFO. */ 2401 uint64_t dbell : 32; /**< Number of available words of Instructions to read. */ 2402#else 2403 uint64_t dbell : 32; 2404 uint64_t fcnt : 7; 2405 uint64_t reserved_39_63 : 25; 2406#endif 2407 } s; 2408 struct cvmx_npei_dmax_counts_s cn52xx; 2409 struct cvmx_npei_dmax_counts_s cn52xxp1; 2410 struct cvmx_npei_dmax_counts_s cn56xx; 2411 struct cvmx_npei_dmax_counts_s cn56xxp1; 2412}; 2413typedef union cvmx_npei_dmax_counts cvmx_npei_dmax_counts_t; 2414 2415/** 2416 * cvmx_npei_dma#_dbell 2417 * 2418 * NPEI_DMA_DBELL[0..4] = DMA Door Bell 2419 * 2420 * The door bell register for DMA[0..4] queue. 2421 */ 2422union cvmx_npei_dmax_dbell 2423{ 2424 uint32_t u32; 2425 struct cvmx_npei_dmax_dbell_s 2426 { 2427#if __BYTE_ORDER == __BIG_ENDIAN 2428 uint32_t reserved_16_31 : 16; 2429 uint32_t dbell : 16; /**< The value written to this register is added to the 2430 number of 8byte words to be read and processes for 2431 the low priority dma queue. */ 2432#else 2433 uint32_t dbell : 16; 2434 uint32_t reserved_16_31 : 16; 2435#endif 2436 } s; 2437 struct cvmx_npei_dmax_dbell_s cn52xx; 2438 struct cvmx_npei_dmax_dbell_s cn52xxp1; 2439 struct cvmx_npei_dmax_dbell_s cn56xx; 2440 struct cvmx_npei_dmax_dbell_s cn56xxp1; 2441}; 2442typedef union cvmx_npei_dmax_dbell cvmx_npei_dmax_dbell_t; 2443 2444/** 2445 * cvmx_npei_dma#_ibuff_saddr 2446 * 2447 * NPEI_DMA[0..4]_IBUFF_SADDR = DMA Instruction Buffer Starting Address 2448 * 2449 * The address to start reading Instructions from for DMA[0..4]. 2450 */ 2451union cvmx_npei_dmax_ibuff_saddr 2452{ 2453 uint64_t u64; 2454 struct cvmx_npei_dmax_ibuff_saddr_s 2455 { 2456#if __BYTE_ORDER == __BIG_ENDIAN 2457 uint64_t reserved_37_63 : 27; 2458 uint64_t idle : 1; /**< DMA Engine IDLE state */ 2459 uint64_t saddr : 29; /**< The 128 byte aligned starting address to read the 2460 first instruction. SADDR is address bit 35:7 of the 2461 first instructions address. */ 2462 uint64_t reserved_0_6 : 7; 2463#else 2464 uint64_t reserved_0_6 : 7; 2465 uint64_t saddr : 29; 2466 uint64_t idle : 1; 2467 uint64_t reserved_37_63 : 27; 2468#endif 2469 } s; 2470 struct cvmx_npei_dmax_ibuff_saddr_s cn52xx; 2471 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 2472 { 2473#if __BYTE_ORDER == __BIG_ENDIAN 2474 uint64_t reserved_36_63 : 28; 2475 uint64_t saddr : 29; /**< The 128 byte aligned starting address to read the 2476 first instruction. SADDR is address bit 35:7 of the 2477 first instructions address. */ 2478 uint64_t reserved_0_6 : 7; 2479#else 2480 uint64_t reserved_0_6 : 7; 2481 uint64_t saddr : 29; 2482 uint64_t reserved_36_63 : 28; 2483#endif 2484 } cn52xxp1; 2485 struct cvmx_npei_dmax_ibuff_saddr_s cn56xx; 2486 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1; 2487}; 2488typedef union cvmx_npei_dmax_ibuff_saddr cvmx_npei_dmax_ibuff_saddr_t; 2489 2490/** 2491 * cvmx_npei_dma#_naddr 2492 * 2493 * NPEI_DMA[0..4]_NADDR = DMA Next Ichunk Address 2494 * 2495 * Place NPEI will read the next Ichunk data from. This is valid when state is 0 2496 */ 2497union cvmx_npei_dmax_naddr 2498{ 2499 uint64_t u64; 2500 struct cvmx_npei_dmax_naddr_s 2501 { 2502#if __BYTE_ORDER == __BIG_ENDIAN 2503 uint64_t reserved_36_63 : 28; 2504 uint64_t addr : 36; /**< The next L2C address to read DMA# instructions 2505 from. */ 2506#else 2507 uint64_t addr : 36; 2508 uint64_t reserved_36_63 : 28; 2509#endif 2510 } s; 2511 struct cvmx_npei_dmax_naddr_s cn52xx; 2512 struct cvmx_npei_dmax_naddr_s cn52xxp1; 2513 struct cvmx_npei_dmax_naddr_s cn56xx; 2514 struct cvmx_npei_dmax_naddr_s cn56xxp1; 2515}; 2516typedef union cvmx_npei_dmax_naddr cvmx_npei_dmax_naddr_t; 2517 2518/** 2519 * cvmx_npei_dma0_int_level 2520 * 2521 * NPEI_DMA0_INT_LEVEL = NPEI DMA0 Interrupt Level 2522 * 2523 * Thresholds for DMA count and timer interrupts for DMA0. 2524 */ 2525union cvmx_npei_dma0_int_level 2526{ 2527 uint64_t u64; 2528 struct cvmx_npei_dma0_int_level_s 2529 { 2530#if __BYTE_ORDER == __BIG_ENDIAN 2531 uint64_t time : 32; /**< Whenever the DMA_CNT0 timer exceeds 2532 this value, NPEI_INT_SUM[DTIME0] is set. 2533 The DMA_CNT0 timer increments every core clock 2534 whenever NPEI_DMA_CNTS[DMA0]!=0, and is cleared 2535 when NPEI_INT_SUM[DTIME0] is written with one. */ 2536 uint64_t cnt : 32; /**< Whenever NPEI_DMA_CNTS[DMA0] exceeds this value, 2537 NPEI_INT_SUM[DCNT0] is set. */ 2538#else 2539 uint64_t cnt : 32; 2540 uint64_t time : 32; 2541#endif 2542 } s; 2543 struct cvmx_npei_dma0_int_level_s cn52xx; 2544 struct cvmx_npei_dma0_int_level_s cn52xxp1; 2545 struct cvmx_npei_dma0_int_level_s cn56xx; 2546 struct cvmx_npei_dma0_int_level_s cn56xxp1; 2547}; 2548typedef union cvmx_npei_dma0_int_level cvmx_npei_dma0_int_level_t; 2549 2550/** 2551 * cvmx_npei_dma1_int_level 2552 * 2553 * NPEI_DMA1_INT_LEVEL = NPEI DMA1 Interrupt Level 2554 * 2555 * Thresholds for DMA count and timer interrupts for DMA1. 2556 */ 2557union cvmx_npei_dma1_int_level 2558{ 2559 uint64_t u64; 2560 struct cvmx_npei_dma1_int_level_s 2561 { 2562#if __BYTE_ORDER == __BIG_ENDIAN 2563 uint64_t time : 32; /**< Whenever the DMA_CNT1 timer exceeds 2564 this value, NPEI_INT_SUM[DTIME1] is set. 2565 The DMA_CNT1 timer increments every core clock 2566 whenever NPEI_DMA_CNTS[DMA1]!=0, and is cleared 2567 when NPEI_INT_SUM[DTIME1] is written with one. */ 2568 uint64_t cnt : 32; /**< Whenever NPEI_DMA_CNTS[DMA1] exceeds this value, 2569 NPEI_INT_SUM[DCNT1] is set. */ 2570#else 2571 uint64_t cnt : 32; 2572 uint64_t time : 32; 2573#endif 2574 } s; 2575 struct cvmx_npei_dma1_int_level_s cn52xx; 2576 struct cvmx_npei_dma1_int_level_s cn52xxp1; 2577 struct cvmx_npei_dma1_int_level_s cn56xx; 2578 struct cvmx_npei_dma1_int_level_s cn56xxp1; 2579}; 2580typedef union cvmx_npei_dma1_int_level cvmx_npei_dma1_int_level_t; 2581 2582/** 2583 * cvmx_npei_dma_cnts 2584 * 2585 * NPEI_DMA_CNTS = NPEI DMA Count 2586 * 2587 * The DMA Count values for DMA0 and DMA1. 2588 */ 2589union cvmx_npei_dma_cnts 2590{ 2591 uint64_t u64; 2592 struct cvmx_npei_dma_cnts_s 2593 { 2594#if __BYTE_ORDER == __BIG_ENDIAN 2595 uint64_t dma1 : 32; /**< The DMA counter 1. 2596 Writing this field will cause the written value to 2597 be subtracted from DMA1. SW should use a 4-byte 2598 write to access this field so as not to change the 2599 value of other fields in this register. 2600 HW will optionally increment this field after 2601 it completes an OUTBOUND or EXTERNAL-ONLY DMA 2602 instruction. These increments may cause interrupts. 2603 Refer to NPEI_DMA1_INT_LEVEL and 2604 NPEI_INT_SUM[DCNT1,DTIME1]. */ 2605 uint64_t dma0 : 32; /**< The DMA counter 0. 2606 Writing this field will cause the written value to 2607 be subtracted from DMA0. SW should use a 4-byte 2608 write to access this field so as not to change the 2609 value of other fields in this register. 2610 HW will optionally increment this field after 2611 it completes an OUTBOUND or EXTERNAL-ONLY DMA 2612 instruction. These increments may cause interrupts. 2613 Refer to NPEI_DMA0_INT_LEVEL and 2614 NPEI_INT_SUM[DCNT0,DTIME0]. */ 2615#else 2616 uint64_t dma0 : 32; 2617 uint64_t dma1 : 32; 2618#endif 2619 } s; 2620 struct cvmx_npei_dma_cnts_s cn52xx; 2621 struct cvmx_npei_dma_cnts_s cn52xxp1; 2622 struct cvmx_npei_dma_cnts_s cn56xx; 2623 struct cvmx_npei_dma_cnts_s cn56xxp1; 2624}; 2625typedef union cvmx_npei_dma_cnts cvmx_npei_dma_cnts_t; 2626 2627/** 2628 * cvmx_npei_dma_control 2629 * 2630 * NPEI_DMA_CONTROL = DMA Control Register 2631 * 2632 * Controls operation of the DMA IN/OUT. 2633 */ 2634union cvmx_npei_dma_control 2635{ 2636 uint64_t u64; 2637 struct cvmx_npei_dma_control_s 2638 { 2639#if __BYTE_ORDER == __BIG_ENDIAN 2640 uint64_t reserved_40_63 : 24; 2641 uint64_t p_32b_m : 1; /**< DMA PCIE 32-bit word read disable bit 2642 When 0, enable the feature */ 2643 uint64_t dma4_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2644 engine. After being enabled a DMA engine should not 2645 be dis-abled while processing instructions. */ 2646 uint64_t dma3_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2647 engine. After being enabled a DMA engine should not 2648 be dis-abled while processing instructions. */ 2649 uint64_t dma2_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2650 engine. After being enabled a DMA engine should not 2651 be dis-abled while processing instructions. */ 2652 uint64_t dma1_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2653 engine. After being enabled a DMA engine should not 2654 be dis-abled while processing instructions. */ 2655 uint64_t dma0_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2656 engine. After being enabled a DMA engine should not 2657 be dis-abled while processing instructions. */ 2658 uint64_t b0_lend : 1; /**< When set '1' and the NPEI is in the mode to write 2659 0 to L2C memory when a DMA is done, the address 2660 to be written to will be treated as a Little 2661 Endian address. */ 2662 uint64_t dwb_denb : 1; /**< When set '1' the NPEI will send a value in the DWB 2663 field for a free page operation for the memory 2664 that contained the data. */ 2665 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are freed 2666 this value is used for the DWB field of the 2667 operation. */ 2668 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will 2669 be returned to when used. */ 2670 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters, 2671 if '0' then the number of bytes in the dma transfer 2672 will be added to the count register. */ 2673 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */ 2674 uint64_t o_ns : 1; /**< Nosnoop For DMA. */ 2675 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */ 2676 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used. 2677 '1' use pointer values for address and register 2678 values for RO, ES, and NS, '0' use register 2679 values for address and pointer values for 2680 RO, ES, and NS. */ 2681 uint64_t csize : 14; /**< The size in words of the DMA Instruction Chunk. 2682 This value should only be written once. After 2683 writing this value a new value will not be 2684 recognized until the end of the DMA I-Chunk is 2685 reached. */ 2686#else 2687 uint64_t csize : 14; 2688 uint64_t o_mode : 1; 2689 uint64_t o_es : 2; 2690 uint64_t o_ns : 1; 2691 uint64_t o_ro : 1; 2692 uint64_t o_add1 : 1; 2693 uint64_t fpa_que : 3; 2694 uint64_t dwb_ichk : 9; 2695 uint64_t dwb_denb : 1; 2696 uint64_t b0_lend : 1; 2697 uint64_t dma0_enb : 1; 2698 uint64_t dma1_enb : 1; 2699 uint64_t dma2_enb : 1; 2700 uint64_t dma3_enb : 1; 2701 uint64_t dma4_enb : 1; 2702 uint64_t p_32b_m : 1; 2703 uint64_t reserved_40_63 : 24; 2704#endif 2705 } s; 2706 struct cvmx_npei_dma_control_s cn52xx; 2707 struct cvmx_npei_dma_control_cn52xxp1 2708 { 2709#if __BYTE_ORDER == __BIG_ENDIAN 2710 uint64_t reserved_38_63 : 26; 2711 uint64_t dma3_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2712 engine. After being enabled a DMA engine should not 2713 be dis-abled while processing instructions. */ 2714 uint64_t dma2_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2715 engine. After being enabled a DMA engine should not 2716 be dis-abled while processing instructions. */ 2717 uint64_t dma1_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2718 engine. After being enabled a DMA engine should not 2719 be dis-abled while processing instructions. */ 2720 uint64_t dma0_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2721 engine. After being enabled a DMA engine should not 2722 be dis-abled while processing instructions. */ 2723 uint64_t b0_lend : 1; /**< When set '1' and the NPEI is in the mode to write 2724 0 to L2C memory when a DMA is done, the address 2725 to be written to will be treated as a Little 2726 Endian address. */ 2727 uint64_t dwb_denb : 1; /**< When set '1' the NPEI will send a value in the DWB 2728 field for a free page operation for the memory 2729 that contained the data. */ 2730 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are freed 2731 this value is used for the DWB field of the 2732 operation. */ 2733 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will 2734 be returned to when used. */ 2735 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters, 2736 if '0' then the number of bytes in the dma transfer 2737 will be added to the count register. */ 2738 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */ 2739 uint64_t o_ns : 1; /**< Nosnoop For DMA. */ 2740 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */ 2741 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used. 2742 '1' use pointer values for address and register 2743 values for RO, ES, and NS, '0' use register 2744 values for address and pointer values for 2745 RO, ES, and NS. */ 2746 uint64_t csize : 14; /**< The size in words of the DMA Instruction Chunk. 2747 This value should only be written once. After 2748 writing this value a new value will not be 2749 recognized until the end of the DMA I-Chunk is 2750 reached. */ 2751#else 2752 uint64_t csize : 14; 2753 uint64_t o_mode : 1; 2754 uint64_t o_es : 2; 2755 uint64_t o_ns : 1; 2756 uint64_t o_ro : 1; 2757 uint64_t o_add1 : 1; 2758 uint64_t fpa_que : 3; 2759 uint64_t dwb_ichk : 9; 2760 uint64_t dwb_denb : 1; 2761 uint64_t b0_lend : 1; 2762 uint64_t dma0_enb : 1; 2763 uint64_t dma1_enb : 1; 2764 uint64_t dma2_enb : 1; 2765 uint64_t dma3_enb : 1; 2766 uint64_t reserved_38_63 : 26; 2767#endif 2768 } cn52xxp1; 2769 struct cvmx_npei_dma_control_s cn56xx; 2770 struct cvmx_npei_dma_control_cn56xxp1 2771 { 2772#if __BYTE_ORDER == __BIG_ENDIAN 2773 uint64_t reserved_39_63 : 25; 2774 uint64_t dma4_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2775 engine. After being enabled a DMA engine should not 2776 be dis-abled while processing instructions. */ 2777 uint64_t dma3_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2778 engine. After being enabled a DMA engine should not 2779 be dis-abled while processing instructions. */ 2780 uint64_t dma2_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2781 engine. After being enabled a DMA engine should not 2782 be dis-abled while processing instructions. */ 2783 uint64_t dma1_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2784 engine. After being enabled a DMA engine should not 2785 be dis-abled while processing instructions. */ 2786 uint64_t dma0_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2787 engine. After being enabled a DMA engine should not 2788 be dis-abled while processing instructions. */ 2789 uint64_t b0_lend : 1; /**< When set '1' and the NPEI is in the mode to write 2790 0 to L2C memory when a DMA is done, the address 2791 to be written to will be treated as a Little 2792 Endian address. */ 2793 uint64_t dwb_denb : 1; /**< When set '1' the NPEI will send a value in the DWB 2794 field for a free page operation for the memory 2795 that contained the data. */ 2796 uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are freed 2797 this value is used for the DWB field of the 2798 operation. */ 2799 uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will 2800 be returned to when used. */ 2801 uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters, 2802 if '0' then the number of bytes in the dma transfer 2803 will be added to the count register. */ 2804 uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */ 2805 uint64_t o_ns : 1; /**< Nosnoop For DMA. */ 2806 uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */ 2807 uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used. 2808 '1' use pointer values for address and register 2809 values for RO, ES, and NS, '0' use register 2810 values for address and pointer values for 2811 RO, ES, and NS. */ 2812 uint64_t csize : 14; /**< The size in words of the DMA Instruction Chunk. 2813 This value should only be written once. After 2814 writing this value a new value will not be 2815 recognized until the end of the DMA I-Chunk is 2816 reached. */ 2817#else 2818 uint64_t csize : 14; 2819 uint64_t o_mode : 1; 2820 uint64_t o_es : 2; 2821 uint64_t o_ns : 1; 2822 uint64_t o_ro : 1; 2823 uint64_t o_add1 : 1; 2824 uint64_t fpa_que : 3; 2825 uint64_t dwb_ichk : 9; 2826 uint64_t dwb_denb : 1; 2827 uint64_t b0_lend : 1; 2828 uint64_t dma0_enb : 1; 2829 uint64_t dma1_enb : 1; 2830 uint64_t dma2_enb : 1; 2831 uint64_t dma3_enb : 1; 2832 uint64_t dma4_enb : 1; 2833 uint64_t reserved_39_63 : 25; 2834#endif 2835 } cn56xxp1; 2836}; 2837typedef union cvmx_npei_dma_control cvmx_npei_dma_control_t; 2838 2839/** 2840 * cvmx_npei_dma_pcie_req_num 2841 * 2842 * NPEI_DMA_PCIE_REQ_NUM = NPEI DMA PCIE Outstanding Read Request Number 2843 * 2844 * Outstanding PCIE read request number for DMAs and Packet, maximum number is 16 2845 */ 2846union cvmx_npei_dma_pcie_req_num 2847{ 2848 uint64_t u64; 2849 struct cvmx_npei_dma_pcie_req_num_s 2850 { 2851#if __BYTE_ORDER == __BIG_ENDIAN 2852 uint64_t dma_arb : 1; /**< DMA_PKT Read Request Arbitration 2853 - 1: DMA0-4 and PKT are round robin. i.e. 2854 DMA0-DMA1-DMA2-DMA3-DMA4-PKT... 2855 - 0: DMA0-4 are round robin, pkt gets selected 2856 half the time. i.e. 2857 DMA0-PKT-DMA1-PKT-DMA2-PKT-DMA3-PKT-DMA4-PKT... */ 2858 uint64_t reserved_53_62 : 10; 2859 uint64_t pkt_cnt : 5; /**< PKT outstanding PCIE Read Request Number for each 2860 PCIe port 2861 When PKT_CNT=x, for each PCIe port, the number 2862 of outstanding PCIe memory space reads by the PCIe 2863 packet input/output will not exceed x. 2864 Valid Number is between 1 and 16 */ 2865 uint64_t reserved_45_47 : 3; 2866 uint64_t dma4_cnt : 5; /**< DMA4 outstanding PCIE Read Request Number 2867 When DMA4_CNT=x, the number of outstanding PCIe 2868 memory space reads by the PCIe DMA engine 4 2869 will not exceed x. 2870 Valid Number is between 1 and 16 */ 2871 uint64_t reserved_37_39 : 3; 2872 uint64_t dma3_cnt : 5; /**< DMA3 outstanding PCIE Read Request Number 2873 When DMA3_CNT=x, the number of outstanding PCIe 2874 memory space reads by the PCIe DMA engine 3 2875 will not exceed x. 2876 Valid Number is between 1 and 16 */ 2877 uint64_t reserved_29_31 : 3; 2878 uint64_t dma2_cnt : 5; /**< DMA2 outstanding PCIE Read Request Number 2879 When DMA2_CNT=x, the number of outstanding PCIe 2880 memory space reads by the PCIe DMA engine 2 2881 will not exceed x. 2882 Valid Number is between 1 and 16 */ 2883 uint64_t reserved_21_23 : 3; 2884 uint64_t dma1_cnt : 5; /**< DMA1 outstanding PCIE Read Request Number 2885 When DMA1_CNT=x, the number of outstanding PCIe 2886 memory space reads by the PCIe DMA engine 1 2887 will not exceed x. 2888 Valid Number is between 1 and 16 */ 2889 uint64_t reserved_13_15 : 3; 2890 uint64_t dma0_cnt : 5; /**< DMA0 outstanding PCIE Read Request Number 2891 When DMA0_CNT=x, the number of outstanding PCIe 2892 memory space reads by the PCIe DMA engine 0 2893 will not exceed x. 2894 Valid Number is between 1 and 16 */ 2895 uint64_t reserved_5_7 : 3; 2896 uint64_t dma_cnt : 5; /**< Total outstanding PCIE Read Request Number for each 2897 PCIe port 2898 When DMA_CNT=x, for each PCIe port, the total 2899 number of outstanding PCIe memory space reads 2900 by the PCIe DMA engines and packet input/output 2901 will not exceed x. 2902 Valid Number is between 1 and 16 */ 2903#else 2904 uint64_t dma_cnt : 5; 2905 uint64_t reserved_5_7 : 3; 2906 uint64_t dma0_cnt : 5; 2907 uint64_t reserved_13_15 : 3; 2908 uint64_t dma1_cnt : 5; 2909 uint64_t reserved_21_23 : 3; 2910 uint64_t dma2_cnt : 5; 2911 uint64_t reserved_29_31 : 3; 2912 uint64_t dma3_cnt : 5; 2913 uint64_t reserved_37_39 : 3; 2914 uint64_t dma4_cnt : 5; 2915 uint64_t reserved_45_47 : 3; 2916 uint64_t pkt_cnt : 5; 2917 uint64_t reserved_53_62 : 10; 2918 uint64_t dma_arb : 1; 2919#endif 2920 } s; 2921 struct cvmx_npei_dma_pcie_req_num_s cn52xx; 2922 struct cvmx_npei_dma_pcie_req_num_s cn56xx; 2923}; 2924typedef union cvmx_npei_dma_pcie_req_num cvmx_npei_dma_pcie_req_num_t; 2925 2926/** 2927 * cvmx_npei_dma_state1 2928 * 2929 * NPEI_DMA_STATE1 = NPI's DMA State 1 2930 * 2931 * Results from DMA state register 1 2932 */ 2933union cvmx_npei_dma_state1 2934{ 2935 uint64_t u64; 2936 struct cvmx_npei_dma_state1_s 2937 { 2938#if __BYTE_ORDER == __BIG_ENDIAN 2939 uint64_t reserved_40_63 : 24; 2940 uint64_t d4_dwe : 8; /**< DMA4 PICe Write State */ 2941 uint64_t d3_dwe : 8; /**< DMA3 PICe Write State */ 2942 uint64_t d2_dwe : 8; /**< DMA2 PICe Write State */ 2943 uint64_t d1_dwe : 8; /**< DMA1 PICe Write State */ 2944 uint64_t d0_dwe : 8; /**< DMA0 PICe Write State */ 2945#else 2946 uint64_t d0_dwe : 8; 2947 uint64_t d1_dwe : 8; 2948 uint64_t d2_dwe : 8; 2949 uint64_t d3_dwe : 8; 2950 uint64_t d4_dwe : 8; 2951 uint64_t reserved_40_63 : 24; 2952#endif 2953 } s; 2954 struct cvmx_npei_dma_state1_s cn52xx; 2955}; 2956typedef union cvmx_npei_dma_state1 cvmx_npei_dma_state1_t; 2957 2958/** 2959 * cvmx_npei_dma_state1_p1 2960 * 2961 * NPEI_DMA_STATE1_P1 = NPEI DMA Request and Instruction State 2962 * 2963 * DMA engine Debug information. 2964 */ 2965union cvmx_npei_dma_state1_p1 2966{ 2967 uint64_t u64; 2968 struct cvmx_npei_dma_state1_p1_s 2969 { 2970#if __BYTE_ORDER == __BIG_ENDIAN 2971 uint64_t reserved_60_63 : 4; 2972 uint64_t d0_difst : 7; /**< DMA engine 0 dif instruction read state */ 2973 uint64_t d1_difst : 7; /**< DMA engine 1 dif instruction read state */ 2974 uint64_t d2_difst : 7; /**< DMA engine 2 dif instruction read state */ 2975 uint64_t d3_difst : 7; /**< DMA engine 3 dif instruction read state */ 2976 uint64_t d4_difst : 7; /**< DMA engine 4 dif instruction read state */ 2977 uint64_t d0_reqst : 5; /**< DMA engine 0 request data state */ 2978 uint64_t d1_reqst : 5; /**< DMA engine 1 request data state */ 2979 uint64_t d2_reqst : 5; /**< DMA engine 2 request data state */ 2980 uint64_t d3_reqst : 5; /**< DMA engine 3 request data state */ 2981 uint64_t d4_reqst : 5; /**< DMA engine 4 request data state */ 2982#else 2983 uint64_t d4_reqst : 5; 2984 uint64_t d3_reqst : 5; 2985 uint64_t d2_reqst : 5; 2986 uint64_t d1_reqst : 5; 2987 uint64_t d0_reqst : 5; 2988 uint64_t d4_difst : 7; 2989 uint64_t d3_difst : 7; 2990 uint64_t d2_difst : 7; 2991 uint64_t d1_difst : 7; 2992 uint64_t d0_difst : 7; 2993 uint64_t reserved_60_63 : 4; 2994#endif 2995 } s; 2996 struct cvmx_npei_dma_state1_p1_cn52xxp1 2997 { 2998#if __BYTE_ORDER == __BIG_ENDIAN 2999 uint64_t reserved_60_63 : 4; 3000 uint64_t d0_difst : 7; /**< DMA engine 0 dif instruction read state */ 3001 uint64_t d1_difst : 7; /**< DMA engine 1 dif instruction read state */ 3002 uint64_t d2_difst : 7; /**< DMA engine 2 dif instruction read state */ 3003 uint64_t d3_difst : 7; /**< DMA engine 3 dif instruction read state */ 3004 uint64_t reserved_25_31 : 7; 3005 uint64_t d0_reqst : 5; /**< DMA engine 0 request data state */ 3006 uint64_t d1_reqst : 5; /**< DMA engine 1 request data state */ 3007 uint64_t d2_reqst : 5; /**< DMA engine 2 request data state */ 3008 uint64_t d3_reqst : 5; /**< DMA engine 3 request data state */ 3009 uint64_t reserved_0_4 : 5; 3010#else 3011 uint64_t reserved_0_4 : 5; 3012 uint64_t d3_reqst : 5; 3013 uint64_t d2_reqst : 5; 3014 uint64_t d1_reqst : 5; 3015 uint64_t d0_reqst : 5; 3016 uint64_t reserved_25_31 : 7; 3017 uint64_t d3_difst : 7; 3018 uint64_t d2_difst : 7; 3019 uint64_t d1_difst : 7; 3020 uint64_t d0_difst : 7; 3021 uint64_t reserved_60_63 : 4; 3022#endif 3023 } cn52xxp1; 3024 struct cvmx_npei_dma_state1_p1_s cn56xxp1; 3025}; 3026typedef union cvmx_npei_dma_state1_p1 cvmx_npei_dma_state1_p1_t; 3027 3028/** 3029 * cvmx_npei_dma_state2 3030 * 3031 * NPEI_DMA_STATE2 = NPI's DMA State 2 3032 * 3033 * Results from DMA state register 2 3034 */ 3035union cvmx_npei_dma_state2 3036{ 3037 uint64_t u64; 3038 struct cvmx_npei_dma_state2_s 3039 { 3040#if __BYTE_ORDER == __BIG_ENDIAN 3041 uint64_t reserved_28_63 : 36; 3042 uint64_t ndwe : 4; /**< DMA L2C Write State */ 3043 uint64_t reserved_21_23 : 3; 3044 uint64_t ndre : 5; /**< DMA L2C Read State */ 3045 uint64_t reserved_10_15 : 6; 3046 uint64_t prd : 10; /**< DMA PICe Read State */ 3047#else 3048 uint64_t prd : 10; 3049 uint64_t reserved_10_15 : 6; 3050 uint64_t ndre : 5; 3051 uint64_t reserved_21_23 : 3; 3052 uint64_t ndwe : 4; 3053 uint64_t reserved_28_63 : 36; 3054#endif 3055 } s; 3056 struct cvmx_npei_dma_state2_s cn52xx; 3057}; 3058typedef union cvmx_npei_dma_state2 cvmx_npei_dma_state2_t; 3059 3060/** 3061 * cvmx_npei_dma_state2_p1 3062 * 3063 * NPEI_DMA_STATE2_P1 = NPEI DMA Instruction Fetch State 3064 * 3065 * DMA engine Debug information. 3066 */ 3067union cvmx_npei_dma_state2_p1 3068{ 3069 uint64_t u64; 3070 struct cvmx_npei_dma_state2_p1_s 3071 { 3072#if __BYTE_ORDER == __BIG_ENDIAN 3073 uint64_t reserved_45_63 : 19; 3074 uint64_t d0_dffst : 9; /**< DMA engine 0 dif instruction fetch state */ 3075 uint64_t d1_dffst : 9; /**< DMA engine 1 dif instruction fetch state */ 3076 uint64_t d2_dffst : 9; /**< DMA engine 2 dif instruction fetch state */ 3077 uint64_t d3_dffst : 9; /**< DMA engine 3 dif instruction fetch state */ 3078 uint64_t d4_dffst : 9; /**< DMA engine 4 dif instruction fetch state */ 3079#else 3080 uint64_t d4_dffst : 9; 3081 uint64_t d3_dffst : 9; 3082 uint64_t d2_dffst : 9; 3083 uint64_t d1_dffst : 9; 3084 uint64_t d0_dffst : 9; 3085 uint64_t reserved_45_63 : 19; 3086#endif 3087 } s; 3088 struct cvmx_npei_dma_state2_p1_cn52xxp1 3089 { 3090#if __BYTE_ORDER == __BIG_ENDIAN 3091 uint64_t reserved_45_63 : 19; 3092 uint64_t d0_dffst : 9; /**< DMA engine 0 dif instruction fetch state */ 3093 uint64_t d1_dffst : 9; /**< DMA engine 1 dif instruction fetch state */ 3094 uint64_t d2_dffst : 9; /**< DMA engine 2 dif instruction fetch state */ 3095 uint64_t d3_dffst : 9; /**< DMA engine 3 dif instruction fetch state */ 3096 uint64_t reserved_0_8 : 9; 3097#else 3098 uint64_t reserved_0_8 : 9; 3099 uint64_t d3_dffst : 9; 3100 uint64_t d2_dffst : 9; 3101 uint64_t d1_dffst : 9; 3102 uint64_t d0_dffst : 9; 3103 uint64_t reserved_45_63 : 19; 3104#endif 3105 } cn52xxp1; 3106 struct cvmx_npei_dma_state2_p1_s cn56xxp1; 3107}; 3108typedef union cvmx_npei_dma_state2_p1 cvmx_npei_dma_state2_p1_t; 3109 3110/** 3111 * cvmx_npei_dma_state3_p1 3112 * 3113 * NPEI_DMA_STATE3_P1 = NPEI DMA DRE State 3114 * 3115 * DMA engine Debug information. 3116 */ 3117union cvmx_npei_dma_state3_p1 3118{ 3119 uint64_t u64; 3120 struct cvmx_npei_dma_state3_p1_s 3121 { 3122#if __BYTE_ORDER == __BIG_ENDIAN 3123 uint64_t reserved_60_63 : 4; 3124 uint64_t d0_drest : 15; /**< DMA engine 0 dre state */ 3125 uint64_t d1_drest : 15; /**< DMA engine 1 dre state */ 3126 uint64_t d2_drest : 15; /**< DMA engine 2 dre state */ 3127 uint64_t d3_drest : 15; /**< DMA engine 3 dre state */ 3128#else 3129 uint64_t d3_drest : 15; 3130 uint64_t d2_drest : 15; 3131 uint64_t d1_drest : 15; 3132 uint64_t d0_drest : 15; 3133 uint64_t reserved_60_63 : 4; 3134#endif 3135 } s; 3136 struct cvmx_npei_dma_state3_p1_s cn52xxp1; 3137 struct cvmx_npei_dma_state3_p1_s cn56xxp1; 3138}; 3139typedef union cvmx_npei_dma_state3_p1 cvmx_npei_dma_state3_p1_t; 3140 3141/** 3142 * cvmx_npei_dma_state4_p1 3143 * 3144 * NPEI_DMA_STATE4_P1 = NPEI DMA DWE State 3145 * 3146 * DMA engine Debug information. 3147 */ 3148union cvmx_npei_dma_state4_p1 3149{ 3150 uint64_t u64; 3151 struct cvmx_npei_dma_state4_p1_s 3152 { 3153#if __BYTE_ORDER == __BIG_ENDIAN 3154 uint64_t reserved_52_63 : 12; 3155 uint64_t d0_dwest : 13; /**< DMA engine 0 dwe state */ 3156 uint64_t d1_dwest : 13; /**< DMA engine 1 dwe state */ 3157 uint64_t d2_dwest : 13; /**< DMA engine 2 dwe state */ 3158 uint64_t d3_dwest : 13; /**< DMA engine 3 dwe state */ 3159#else 3160 uint64_t d3_dwest : 13; 3161 uint64_t d2_dwest : 13; 3162 uint64_t d1_dwest : 13; 3163 uint64_t d0_dwest : 13; 3164 uint64_t reserved_52_63 : 12; 3165#endif 3166 } s; 3167 struct cvmx_npei_dma_state4_p1_s cn52xxp1; 3168 struct cvmx_npei_dma_state4_p1_s cn56xxp1; 3169}; 3170typedef union cvmx_npei_dma_state4_p1 cvmx_npei_dma_state4_p1_t; 3171 3172/** 3173 * cvmx_npei_dma_state5_p1 3174 * 3175 * NPEI_DMA_STATE5_P1 = NPEI DMA DWE and DRE State 3176 * 3177 * DMA engine Debug information. 3178 */ 3179union cvmx_npei_dma_state5_p1 3180{ 3181 uint64_t u64; 3182 struct cvmx_npei_dma_state5_p1_s 3183 { 3184#if __BYTE_ORDER == __BIG_ENDIAN 3185 uint64_t reserved_28_63 : 36; 3186 uint64_t d4_drest : 15; /**< DMA engine 4 dre state */ 3187 uint64_t d4_dwest : 13; /**< DMA engine 4 dwe state */ 3188#else 3189 uint64_t d4_dwest : 13; 3190 uint64_t d4_drest : 15; 3191 uint64_t reserved_28_63 : 36; 3192#endif 3193 } s; 3194 struct cvmx_npei_dma_state5_p1_s cn56xxp1; 3195}; 3196typedef union cvmx_npei_dma_state5_p1 cvmx_npei_dma_state5_p1_t; 3197 3198/** 3199 * cvmx_npei_int_a_enb 3200 * 3201 * NPEI_INTERRUPT_A_ENB = NPI's Interrupt A Enable Register 3202 * 3203 * Used to allow the generation of interrupts (MSI/INTA) to the PCIe CoresUsed to enable the various interrupting conditions of NPEI 3204 */ 3205union cvmx_npei_int_a_enb 3206{ 3207 uint64_t u64; 3208 struct cvmx_npei_int_a_enb_s 3209 { 3210#if __BYTE_ORDER == __BIG_ENDIAN 3211 uint64_t reserved_10_63 : 54; 3212 uint64_t pout_err : 1; /**< Enables NPEI_INT_A_SUM[9] to generate an 3213 interrupt to the PCIE core for MSI/inta. */ 3214 uint64_t pin_bp : 1; /**< Enables NPEI_INT_A_SUM[8] to generate an 3215 interrupt to the PCIE core for MSI/inta. */ 3216 uint64_t p1_rdlk : 1; /**< Enables NPEI_INT_A_SUM[7] to generate an 3217 interrupt to the PCIE core for MSI/inta. */ 3218 uint64_t p0_rdlk : 1; /**< Enables NPEI_INT_A_SUM[6] to generate an 3219 interrupt to the PCIE core for MSI/inta. */ 3220 uint64_t pgl_err : 1; /**< Enables NPEI_INT_A_SUM[5] to generate an 3221 interrupt to the PCIE core for MSI/inta. */ 3222 uint64_t pdi_err : 1; /**< Enables NPEI_INT_A_SUM[4] to generate an 3223 interrupt to the PCIE core for MSI/inta. */ 3224 uint64_t pop_err : 1; /**< Enables NPEI_INT_A_SUM[3] to generate an 3225 interrupt to the PCIE core for MSI/inta. */ 3226 uint64_t pins_err : 1; /**< Enables NPEI_INT_A_SUM[2] to generate an 3227 interrupt to the PCIE core for MSI/inta. */ 3228 uint64_t dma1_cpl : 1; /**< Enables NPEI_INT_A_SUM[1] to generate an 3229 interrupt to the PCIE core for MSI/inta. */ 3230 uint64_t dma0_cpl : 1; /**< Enables NPEI_INT_A_SUM[0] to generate an 3231 interrupt to the PCIE core for MSI/inta. */ 3232#else 3233 uint64_t dma0_cpl : 1; 3234 uint64_t dma1_cpl : 1; 3235 uint64_t pins_err : 1; 3236 uint64_t pop_err : 1; 3237 uint64_t pdi_err : 1; 3238 uint64_t pgl_err : 1; 3239 uint64_t p0_rdlk : 1; 3240 uint64_t p1_rdlk : 1; 3241 uint64_t pin_bp : 1; 3242 uint64_t pout_err : 1; 3243 uint64_t reserved_10_63 : 54; 3244#endif 3245 } s; 3246 struct cvmx_npei_int_a_enb_s cn52xx; 3247 struct cvmx_npei_int_a_enb_cn52xxp1 3248 { 3249#if __BYTE_ORDER == __BIG_ENDIAN 3250 uint64_t reserved_2_63 : 62; 3251 uint64_t dma1_cpl : 1; /**< Enables NPEI_INT_A_SUM[1] to generate an 3252 interrupt to the PCIE core for MSI/inta. */ 3253 uint64_t dma0_cpl : 1; /**< Enables NPEI_INT_A_SUM[0] to generate an 3254 interrupt to the PCIE core for MSI/inta. */ 3255#else 3256 uint64_t dma0_cpl : 1; 3257 uint64_t dma1_cpl : 1; 3258 uint64_t reserved_2_63 : 62; 3259#endif 3260 } cn52xxp1; 3261 struct cvmx_npei_int_a_enb_s cn56xx; 3262}; 3263typedef union cvmx_npei_int_a_enb cvmx_npei_int_a_enb_t; 3264 3265/** 3266 * cvmx_npei_int_a_enb2 3267 * 3268 * NPEI_INTERRUPT_A_ENB2 = NPEI's Interrupt A Enable2 Register 3269 * 3270 * Used to enable the various interrupting conditions of NPEI 3271 */ 3272union cvmx_npei_int_a_enb2 3273{ 3274 uint64_t u64; 3275 struct cvmx_npei_int_a_enb2_s 3276 { 3277#if __BYTE_ORDER == __BIG_ENDIAN 3278 uint64_t reserved_10_63 : 54; 3279 uint64_t pout_err : 1; /**< Enables NPEI_INT_A_SUM[9] to generate an 3280 interrupt on the RSL. */ 3281 uint64_t pin_bp : 1; /**< Enables NPEI_INT_A_SUM[8] to generate an 3282 interrupt on the RSL. */ 3283 uint64_t p1_rdlk : 1; /**< Enables NPEI_INT_A_SUM[7] to generate an 3284 interrupt on the RSL. */ 3285 uint64_t p0_rdlk : 1; /**< Enables NPEI_INT_A_SUM[6] to generate an 3286 interrupt on the RSL. */ 3287 uint64_t pgl_err : 1; /**< Enables NPEI_INT_A_SUM[5] to generate an 3288 interrupt on the RSL. */ 3289 uint64_t pdi_err : 1; /**< Enables NPEI_INT_A_SUM[4] to generate an 3290 interrupt on the RSL. */ 3291 uint64_t pop_err : 1; /**< Enables NPEI_INT_A_SUM[3] to generate an 3292 interrupt on the RSL. */ 3293 uint64_t pins_err : 1; /**< Enables NPEI_INT_A_SUM[2] to generate an 3294 interrupt on the RSL. */ 3295 uint64_t dma1_cpl : 1; /**< Enables NPEI_INT_A_SUM[1] to generate an 3296 interrupt to the PCIE core for MSI/inta. */ 3297 uint64_t dma0_cpl : 1; /**< Enables NPEI_INT_A_SUM[0] to generate an 3298 interrupt to the PCIE core for MSI/inta. */ 3299#else 3300 uint64_t dma0_cpl : 1; 3301 uint64_t dma1_cpl : 1; 3302 uint64_t pins_err : 1; 3303 uint64_t pop_err : 1; 3304 uint64_t pdi_err : 1; 3305 uint64_t pgl_err : 1; 3306 uint64_t p0_rdlk : 1; 3307 uint64_t p1_rdlk : 1; 3308 uint64_t pin_bp : 1; 3309 uint64_t pout_err : 1; 3310 uint64_t reserved_10_63 : 54; 3311#endif 3312 } s; 3313 struct cvmx_npei_int_a_enb2_s cn52xx; 3314 struct cvmx_npei_int_a_enb2_cn52xxp1 3315 { 3316#if __BYTE_ORDER == __BIG_ENDIAN 3317 uint64_t reserved_2_63 : 62; 3318 uint64_t dma1_cpl : 1; /**< Enables NPEI_INT_A_SUM[1] to generate an 3319 interrupt to the PCIE core for MSI/inta. */ 3320 uint64_t dma0_cpl : 1; /**< Enables NPEI_INT_A_SUM[0] to generate an 3321 interrupt to the PCIE core for MSI/inta. */ 3322#else 3323 uint64_t dma0_cpl : 1; 3324 uint64_t dma1_cpl : 1; 3325 uint64_t reserved_2_63 : 62; 3326#endif 3327 } cn52xxp1; 3328 struct cvmx_npei_int_a_enb2_s cn56xx; 3329}; 3330typedef union cvmx_npei_int_a_enb2 cvmx_npei_int_a_enb2_t; 3331 3332/** 3333 * cvmx_npei_int_a_sum 3334 * 3335 * NPEI_INTERRUPT_A_SUM = NPI Interrupt A Summary Register 3336 * 3337 * Set when an interrupt condition occurs, write '1' to clear. When an interrupt bitin this register is set and 3338 * the cooresponding bit in the NPEI_INT_A_ENB register is set, then NPEI_INT_SUM[61] will be set. 3339 */ 3340union cvmx_npei_int_a_sum 3341{ 3342 uint64_t u64; 3343 struct cvmx_npei_int_a_sum_s 3344 { 3345#if __BYTE_ORDER == __BIG_ENDIAN 3346 uint64_t reserved_10_63 : 54; 3347 uint64_t pout_err : 1; /**< Set when PKO sends packet data with the error bit 3348 set. */ 3349 uint64_t pin_bp : 1; /**< Packet input count has exceeded the WMARK. 3350 See NPEI_PKT_IN_BP */ 3351 uint64_t p1_rdlk : 1; /**< PCIe port 1 received a read lock. */ 3352 uint64_t p0_rdlk : 1; /**< PCIe port 0 received a read lock. */ 3353 uint64_t pgl_err : 1; /**< When a read error occurs on a packet gather list 3354 read this bit is set. */ 3355 uint64_t pdi_err : 1; /**< When a read error occurs on a packet data read 3356 this bit is set. */ 3357 uint64_t pop_err : 1; /**< When a read error occurs on a packet scatter 3358 pointer pair this bit is set. */ 3359 uint64_t pins_err : 1; /**< When a read error occurs on a packet instruction 3360 this bit is set. */ 3361 uint64_t dma1_cpl : 1; /**< Set each time any PCIe DMA engine recieves a UR/CA 3362 response from PCIe Port 1 */ 3363 uint64_t dma0_cpl : 1; /**< Set each time any PCIe DMA engine recieves a UR/CA 3364 response from PCIe Port 0 */ 3365#else 3366 uint64_t dma0_cpl : 1; 3367 uint64_t dma1_cpl : 1; 3368 uint64_t pins_err : 1; 3369 uint64_t pop_err : 1; 3370 uint64_t pdi_err : 1; 3371 uint64_t pgl_err : 1; 3372 uint64_t p0_rdlk : 1; 3373 uint64_t p1_rdlk : 1; 3374 uint64_t pin_bp : 1; 3375 uint64_t pout_err : 1; 3376 uint64_t reserved_10_63 : 54; 3377#endif 3378 } s; 3379 struct cvmx_npei_int_a_sum_s cn52xx; 3380 struct cvmx_npei_int_a_sum_cn52xxp1 3381 { 3382#if __BYTE_ORDER == __BIG_ENDIAN 3383 uint64_t reserved_2_63 : 62; 3384 uint64_t dma1_cpl : 1; /**< Set each time any PCIe DMA engine recieves a UR/CA 3385 response from PCIe Port 1 */ 3386 uint64_t dma0_cpl : 1; /**< Set each time any PCIe DMA engine recieves a UR/CA 3387 response from PCIe Port 0 */ 3388#else 3389 uint64_t dma0_cpl : 1; 3390 uint64_t dma1_cpl : 1; 3391 uint64_t reserved_2_63 : 62; 3392#endif 3393 } cn52xxp1; 3394 struct cvmx_npei_int_a_sum_s cn56xx; 3395}; 3396typedef union cvmx_npei_int_a_sum cvmx_npei_int_a_sum_t; 3397 3398/** 3399 * cvmx_npei_int_enb 3400 * 3401 * NPEI_INTERRUPT_ENB = NPI's Interrupt Enable Register 3402 * 3403 * Used to allow the generation of interrupts (MSI/INTA) to the PCIe CoresUsed to enable the various interrupting conditions of NPI 3404 */ 3405union cvmx_npei_int_enb 3406{ 3407 uint64_t u64; 3408 struct cvmx_npei_int_enb_s 3409 { 3410#if __BYTE_ORDER == __BIG_ENDIAN 3411 uint64_t mio_inta : 1; /**< Enables NPEI_INT_SUM[63] to generate an 3412 interrupt to the PCIE core for MSI/inta. */ 3413 uint64_t reserved_62_62 : 1; 3414 uint64_t int_a : 1; /**< Enables NPEI_INT_SUM[61] to generate an 3415 interrupt to the PCIE core for MSI/inta. */ 3416 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an 3417 interrupt to the PCIE core for MSI/inta. */ 3418 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an 3419 interrupt to the PCIE core for MSI/inta. */ 3420 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an 3421 interrupt to the PCIE core for MSI/inta. */ 3422 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an 3423 interrupt to the PCIE core for MSI/inta. */ 3424 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an 3425 interrupt to the PCIE core for MSI/inta. */ 3426 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an 3427 interrupt to the PCIE core for MSI/inta. */ 3428 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an 3429 interrupt to the PCIE core for MSI/inta. */ 3430 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an 3431 interrupt to the PCIE core for MSI/inta. */ 3432 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an 3433 interrupt to the PCIE core for MSI/inta. */ 3434 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an 3435 interrupt to the PCIE core for MSI/inta. */ 3436 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an 3437 interrupt to the PCIE core for MSI/inta. */ 3438 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an 3439 interrupt to the PCIE core for MSI/inta. */ 3440 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an 3441 interrupt to the PCIE core for MSI/inta. */ 3442 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an 3443 interrupt to the PCIE core for MSI/inta. */ 3444 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an 3445 interrupt to the PCIE core for MSI/inta. */ 3446 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an 3447 interrupt to the PCIE core for MSI/inta. */ 3448 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an 3449 interrupt to the PCIE core for MSI/inta. */ 3450 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an 3451 interrupt to the PCIE core for MSI/inta. */ 3452 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an 3453 interrupt to the PCIE core for MSI/inta. */ 3454 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an 3455 interrupt to the PCIE core for MSI/inta. */ 3456 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an 3457 interrupt to the PCIE core for MSI/inta. */ 3458 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an 3459 interrupt to the PCIE core for MSI/inta. */ 3460 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an 3461 interrupt to the PCIE core for MSI/inta. */ 3462 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an 3463 interrupt to the PCIE core for MSI/inta. */ 3464 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an 3465 interrupt to the PCIE core for MSI/inta. */ 3466 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an 3467 interrupt to the PCIE core for MSI/inta. */ 3468 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an 3469 interrupt to the PCIE core for MSI/inta. */ 3470 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an 3471 interrupt to the PCIE core for MSI/inta. */ 3472 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an 3473 interrupt to the PCIE core for MSI/inta. */ 3474 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an 3475 interrupt to the PCIE core for MSI/inta. */ 3476 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an 3477 interrupt to the PCIE core for MSI/inta. */ 3478 uint64_t crs1_dr : 1; /**< Enables NPEI_INT_SUM[29] to generate an 3479 interrupt to the PCIE core for MSI/inta. */ 3480 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an 3481 interrupt to the PCIE core for MSI/inta. */ 3482 uint64_t crs1_er : 1; /**< Enables NPEI_INT_SUM[27] to generate an 3483 interrupt to the PCIE core for MSI/inta. */ 3484 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an 3485 interrupt to the PCIE core for MSI/inta. */ 3486 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an 3487 interrupt to the PCIE core for MSI/inta. */ 3488 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an 3489 interrupt to the PCIE core for MSI/inta. */ 3490 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an 3491 interrupt to the PCIE core for MSI/inta. */ 3492 uint64_t crs0_dr : 1; /**< Enables NPEI_INT_SUM[22] to generate an 3493 interrupt to the PCIE core for MSI/inta. */ 3494 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an 3495 interrupt to the PCIE core for MSI/inta. */ 3496 uint64_t crs0_er : 1; /**< Enables NPEI_INT_SUM[20] to generate an 3497 interrupt to the PCIE core for MSI/inta. */ 3498 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an 3499 interrupt to the PCIE core for MSI/inta. */ 3500 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an 3501 interrupt to the PCIE core for MSI/inta. */ 3502 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an 3503 interrupt to the PCIE core for MSI/inta. */ 3504 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an 3505 interrupt to the PCIE core for MSI/inta. */ 3506 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an 3507 interrupt to the PCIE core for MSI/inta. */ 3508 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an 3509 interrupt to the PCIE core for MSI/inta. */ 3510 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an 3511 interrupt to the PCIE core for MSI/inta. */ 3512 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an 3513 interrupt to the PCIE core for MSI/inta. */ 3514 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an 3515 interrupt to the PCIE core for MSI/inta. */ 3516 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an 3517 interrupt to the PCIE core for MSI/inta. */ 3518 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an 3519 interrupt to the PCIE core for MSI/inta. */ 3520 uint64_t dma4dbo : 1; /**< Enables NPEI_INT_SUM[8] to generate an 3521 interrupt to the PCIE core for MSI/inta. */ 3522 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an 3523 interrupt to the PCIE core for MSI/inta. */ 3524 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an 3525 interrupt to the PCIE core for MSI/inta. */ 3526 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an 3527 interrupt to the PCIE core for MSI/inta. */ 3528 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an 3529 interrupt to the PCIE core for MSI/inta. */ 3530 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an 3531 interrupt to the PCIE core for MSI/inta. */ 3532 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an 3533 interrupt to the PCIE core for MSI/inta. */ 3534 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an 3535 interrupt to the PCIE core for MSI/inta. */ 3536 uint64_t rml_rto : 1; /**< Enables NPEI_INT_SUM[0] to generate an 3537 interrupt to the PCIE core for MSI/inta. */ 3538#else 3539 uint64_t rml_rto : 1; 3540 uint64_t rml_wto : 1; 3541 uint64_t bar0_to : 1; 3542 uint64_t iob2big : 1; 3543 uint64_t dma0dbo : 1; 3544 uint64_t dma1dbo : 1; 3545 uint64_t dma2dbo : 1; 3546 uint64_t dma3dbo : 1; 3547 uint64_t dma4dbo : 1; 3548 uint64_t dma0fi : 1; 3549 uint64_t dma1fi : 1; 3550 uint64_t dcnt0 : 1; 3551 uint64_t dcnt1 : 1; 3552 uint64_t dtime0 : 1; 3553 uint64_t dtime1 : 1; 3554 uint64_t psldbof : 1; 3555 uint64_t pidbof : 1; 3556 uint64_t pcnt : 1; 3557 uint64_t ptime : 1; 3558 uint64_t c0_aeri : 1; 3559 uint64_t crs0_er : 1; 3560 uint64_t c0_se : 1; 3561 uint64_t crs0_dr : 1; 3562 uint64_t c0_wake : 1; 3563 uint64_t c0_pmei : 1; 3564 uint64_t c0_hpint : 1; 3565 uint64_t c1_aeri : 1; 3566 uint64_t crs1_er : 1; 3567 uint64_t c1_se : 1; 3568 uint64_t crs1_dr : 1; 3569 uint64_t c1_wake : 1; 3570 uint64_t c1_pmei : 1; 3571 uint64_t c1_hpint : 1; 3572 uint64_t c0_up_b0 : 1; 3573 uint64_t c0_up_b1 : 1; 3574 uint64_t c0_up_b2 : 1; 3575 uint64_t c0_up_wi : 1; 3576 uint64_t c0_up_bx : 1; 3577 uint64_t c0_un_b0 : 1; 3578 uint64_t c0_un_b1 : 1; 3579 uint64_t c0_un_b2 : 1; 3580 uint64_t c0_un_wi : 1; 3581 uint64_t c0_un_bx : 1; 3582 uint64_t c1_up_b0 : 1; 3583 uint64_t c1_up_b1 : 1; 3584 uint64_t c1_up_b2 : 1; 3585 uint64_t c1_up_wi : 1; 3586 uint64_t c1_up_bx : 1; 3587 uint64_t c1_un_b0 : 1; 3588 uint64_t c1_un_b1 : 1; 3589 uint64_t c1_un_b2 : 1; 3590 uint64_t c1_un_wi : 1; 3591 uint64_t c1_un_bx : 1; 3592 uint64_t c0_un_wf : 1; 3593 uint64_t c1_un_wf : 1; 3594 uint64_t c0_up_wf : 1; 3595 uint64_t c1_up_wf : 1; 3596 uint64_t c0_exc : 1; 3597 uint64_t c1_exc : 1; 3598 uint64_t c0_ldwn : 1; 3599 uint64_t c1_ldwn : 1; 3600 uint64_t int_a : 1; 3601 uint64_t reserved_62_62 : 1; 3602 uint64_t mio_inta : 1; 3603#endif 3604 } s; 3605 struct cvmx_npei_int_enb_s cn52xx; 3606 struct cvmx_npei_int_enb_cn52xxp1 3607 { 3608#if __BYTE_ORDER == __BIG_ENDIAN 3609 uint64_t mio_inta : 1; /**< Enables NPEI_INT_SUM[63] to generate an 3610 interrupt to the PCIE core for MSI/inta. */ 3611 uint64_t reserved_62_62 : 1; 3612 uint64_t int_a : 1; /**< Enables NPEI_INT_SUM[61] to generate an 3613 interrupt to the PCIE core for MSI/inta. */ 3614 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an 3615 interrupt to the PCIE core for MSI/inta. */ 3616 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an 3617 interrupt to the PCIE core for MSI/inta. */ 3618 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an 3619 interrupt to the PCIE core for MSI/inta. */ 3620 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an 3621 interrupt to the PCIE core for MSI/inta. */ 3622 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an 3623 interrupt to the PCIE core for MSI/inta. */ 3624 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an 3625 interrupt to the PCIE core for MSI/inta. */ 3626 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an 3627 interrupt to the PCIE core for MSI/inta. */ 3628 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an 3629 interrupt to the PCIE core for MSI/inta. */ 3630 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an 3631 interrupt to the PCIE core for MSI/inta. */ 3632 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an 3633 interrupt to the PCIE core for MSI/inta. */ 3634 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an 3635 interrupt to the PCIE core for MSI/inta. */ 3636 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an 3637 interrupt to the PCIE core for MSI/inta. */ 3638 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an 3639 interrupt to the PCIE core for MSI/inta. */ 3640 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an 3641 interrupt to the PCIE core for MSI/inta. */ 3642 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an 3643 interrupt to the PCIE core for MSI/inta. */ 3644 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an 3645 interrupt to the PCIE core for MSI/inta. */ 3646 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an 3647 interrupt to the PCIE core for MSI/inta. */ 3648 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an 3649 interrupt to the PCIE core for MSI/inta. */ 3650 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an 3651 interrupt to the PCIE core for MSI/inta. */ 3652 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an 3653 interrupt to the PCIE core for MSI/inta. */ 3654 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an 3655 interrupt to the PCIE core for MSI/inta. */ 3656 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an 3657 interrupt to the PCIE core for MSI/inta. */ 3658 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an 3659 interrupt to the PCIE core for MSI/inta. */ 3660 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an 3661 interrupt to the PCIE core for MSI/inta. */ 3662 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an 3663 interrupt to the PCIE core for MSI/inta. */ 3664 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an 3665 interrupt to the PCIE core for MSI/inta. */ 3666 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an 3667 interrupt to the PCIE core for MSI/inta. */ 3668 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an 3669 interrupt to the PCIE core for MSI/inta. */ 3670 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an 3671 interrupt to the PCIE core for MSI/inta. */ 3672 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an 3673 interrupt to the PCIE core for MSI/inta. */ 3674 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an 3675 interrupt to the PCIE core for MSI/inta. */ 3676 uint64_t crs1_dr : 1; /**< Enables NPEI_INT_SUM[29] to generate an 3677 interrupt to the PCIE core for MSI/inta. */ 3678 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an 3679 interrupt to the PCIE core for MSI/inta. */ 3680 uint64_t crs1_er : 1; /**< Enables NPEI_INT_SUM[27] to generate an 3681 interrupt to the PCIE core for MSI/inta. */ 3682 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an 3683 interrupt to the PCIE core for MSI/inta. */ 3684 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an 3685 interrupt to the PCIE core for MSI/inta. */ 3686 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an 3687 interrupt to the PCIE core for MSI/inta. */ 3688 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an 3689 interrupt to the PCIE core for MSI/inta. */ 3690 uint64_t crs0_dr : 1; /**< Enables NPEI_INT_SUM[22] to generate an 3691 interrupt to the PCIE core for MSI/inta. */ 3692 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an 3693 interrupt to the PCIE core for MSI/inta. */ 3694 uint64_t crs0_er : 1; /**< Enables NPEI_INT_SUM[20] to generate an 3695 interrupt to the PCIE core for MSI/inta. */ 3696 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an 3697 interrupt to the PCIE core for MSI/inta. */ 3698 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an 3699 interrupt to the PCIE core for MSI/inta. */ 3700 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an 3701 interrupt to the PCIE core for MSI/inta. */ 3702 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an 3703 interrupt to the PCIE core for MSI/inta. */ 3704 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an 3705 interrupt to the PCIE core for MSI/inta. */ 3706 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an 3707 interrupt to the PCIE core for MSI/inta. */ 3708 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an 3709 interrupt to the PCIE core for MSI/inta. */ 3710 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an 3711 interrupt to the PCIE core for MSI/inta. */ 3712 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an 3713 interrupt to the PCIE core for MSI/inta. */ 3714 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an 3715 interrupt to the PCIE core for MSI/inta. */ 3716 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an 3717 interrupt to the PCIE core for MSI/inta. */ 3718 uint64_t reserved_8_8 : 1; 3719 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an 3720 interrupt to the PCIE core for MSI/inta. */ 3721 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an 3722 interrupt to the PCIE core for MSI/inta. */ 3723 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an 3724 interrupt to the PCIE core for MSI/inta. */ 3725 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an 3726 interrupt to the PCIE core for MSI/inta. */ 3727 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an 3728 interrupt to the PCIE core for MSI/inta. */ 3729 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an 3730 interrupt to the PCIE core for MSI/inta. */ 3731 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an 3732 interrupt to the PCIE core for MSI/inta. */ 3733 uint64_t rml_rto : 1; /**< Enables NPEI_INT_SUM[0] to generate an 3734 interrupt to the PCIE core for MSI/inta. */ 3735#else 3736 uint64_t rml_rto : 1; 3737 uint64_t rml_wto : 1; 3738 uint64_t bar0_to : 1; 3739 uint64_t iob2big : 1; 3740 uint64_t dma0dbo : 1; 3741 uint64_t dma1dbo : 1; 3742 uint64_t dma2dbo : 1; 3743 uint64_t dma3dbo : 1; 3744 uint64_t reserved_8_8 : 1; 3745 uint64_t dma0fi : 1; 3746 uint64_t dma1fi : 1; 3747 uint64_t dcnt0 : 1; 3748 uint64_t dcnt1 : 1; 3749 uint64_t dtime0 : 1; 3750 uint64_t dtime1 : 1; 3751 uint64_t psldbof : 1; 3752 uint64_t pidbof : 1; 3753 uint64_t pcnt : 1; 3754 uint64_t ptime : 1; 3755 uint64_t c0_aeri : 1; 3756 uint64_t crs0_er : 1; 3757 uint64_t c0_se : 1; 3758 uint64_t crs0_dr : 1; 3759 uint64_t c0_wake : 1; 3760 uint64_t c0_pmei : 1; 3761 uint64_t c0_hpint : 1; 3762 uint64_t c1_aeri : 1; 3763 uint64_t crs1_er : 1; 3764 uint64_t c1_se : 1; 3765 uint64_t crs1_dr : 1; 3766 uint64_t c1_wake : 1; 3767 uint64_t c1_pmei : 1; 3768 uint64_t c1_hpint : 1; 3769 uint64_t c0_up_b0 : 1; 3770 uint64_t c0_up_b1 : 1; 3771 uint64_t c0_up_b2 : 1; 3772 uint64_t c0_up_wi : 1; 3773 uint64_t c0_up_bx : 1; 3774 uint64_t c0_un_b0 : 1; 3775 uint64_t c0_un_b1 : 1; 3776 uint64_t c0_un_b2 : 1; 3777 uint64_t c0_un_wi : 1; 3778 uint64_t c0_un_bx : 1; 3779 uint64_t c1_up_b0 : 1; 3780 uint64_t c1_up_b1 : 1; 3781 uint64_t c1_up_b2 : 1; 3782 uint64_t c1_up_wi : 1; 3783 uint64_t c1_up_bx : 1; 3784 uint64_t c1_un_b0 : 1; 3785 uint64_t c1_un_b1 : 1; 3786 uint64_t c1_un_b2 : 1; 3787 uint64_t c1_un_wi : 1; 3788 uint64_t c1_un_bx : 1; 3789 uint64_t c0_un_wf : 1; 3790 uint64_t c1_un_wf : 1; 3791 uint64_t c0_up_wf : 1; 3792 uint64_t c1_up_wf : 1; 3793 uint64_t c0_exc : 1; 3794 uint64_t c1_exc : 1; 3795 uint64_t c0_ldwn : 1; 3796 uint64_t c1_ldwn : 1; 3797 uint64_t int_a : 1; 3798 uint64_t reserved_62_62 : 1; 3799 uint64_t mio_inta : 1; 3800#endif 3801 } cn52xxp1; 3802 struct cvmx_npei_int_enb_s cn56xx; 3803 struct cvmx_npei_int_enb_cn56xxp1 3804 { 3805#if __BYTE_ORDER == __BIG_ENDIAN 3806 uint64_t mio_inta : 1; /**< Enables NPEI_INT_SUM[63] to generate an 3807 interrupt to the PCIE core for MSI/inta. */ 3808 uint64_t reserved_61_62 : 2; 3809 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an 3810 interrupt to the PCIE core for MSI/inta. */ 3811 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an 3812 interrupt to the PCIE core for MSI/inta. */ 3813 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an 3814 interrupt to the PCIE core for MSI/inta. */ 3815 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an 3816 interrupt to the PCIE core for MSI/inta. */ 3817 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an 3818 interrupt to the PCIE core for MSI/inta. */ 3819 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an 3820 interrupt to the PCIE core for MSI/inta. */ 3821 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an 3822 interrupt to the PCIE core for MSI/inta. */ 3823 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an 3824 interrupt to the PCIE core for MSI/inta. */ 3825 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an 3826 interrupt to the PCIE core for MSI/inta. */ 3827 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an 3828 interrupt to the PCIE core for MSI/inta. */ 3829 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an 3830 interrupt to the PCIE core for MSI/inta. */ 3831 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an 3832 interrupt to the PCIE core for MSI/inta. */ 3833 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an 3834 interrupt to the PCIE core for MSI/inta. */ 3835 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an 3836 interrupt to the PCIE core for MSI/inta. */ 3837 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an 3838 interrupt to the PCIE core for MSI/inta. */ 3839 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an 3840 interrupt to the PCIE core for MSI/inta. */ 3841 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an 3842 interrupt to the PCIE core for MSI/inta. */ 3843 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an 3844 interrupt to the PCIE core for MSI/inta. */ 3845 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an 3846 interrupt to the PCIE core for MSI/inta. */ 3847 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an 3848 interrupt to the PCIE core for MSI/inta. */ 3849 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an 3850 interrupt to the PCIE core for MSI/inta. */ 3851 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an 3852 interrupt to the PCIE core for MSI/inta. */ 3853 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an 3854 interrupt to the PCIE core for MSI/inta. */ 3855 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an 3856 interrupt to the PCIE core for MSI/inta. */ 3857 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an 3858 interrupt to the PCIE core for MSI/inta. */ 3859 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an 3860 interrupt to the PCIE core for MSI/inta. */ 3861 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an 3862 interrupt to the PCIE core for MSI/inta. */ 3863 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an 3864 interrupt to the PCIE core for MSI/inta. */ 3865 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an 3866 interrupt to the PCIE core for MSI/inta. */ 3867 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an 3868 interrupt to the PCIE core for MSI/inta. */ 3869 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an 3870 interrupt to the PCIE core for MSI/inta. */ 3871 uint64_t reserved_29_29 : 1; 3872 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an 3873 interrupt to the PCIE core for MSI/inta. */ 3874 uint64_t reserved_27_27 : 1; 3875 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an 3876 interrupt to the PCIE core for MSI/inta. */ 3877 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an 3878 interrupt to the PCIE core for MSI/inta. */ 3879 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an 3880 interrupt to the PCIE core for MSI/inta. */ 3881 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an 3882 interrupt to the PCIE core for MSI/inta. */ 3883 uint64_t reserved_22_22 : 1; 3884 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an 3885 interrupt to the PCIE core for MSI/inta. */ 3886 uint64_t reserved_20_20 : 1; 3887 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an 3888 interrupt to the PCIE core for MSI/inta. */ 3889 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an 3890 interrupt to the PCIE core for MSI/inta. */ 3891 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an 3892 interrupt to the PCIE core for MSI/inta. */ 3893 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an 3894 interrupt to the PCIE core for MSI/inta. */ 3895 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an 3896 interrupt to the PCIE core for MSI/inta. */ 3897 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an 3898 interrupt to the PCIE core for MSI/inta. */ 3899 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an 3900 interrupt to the PCIE core for MSI/inta. */ 3901 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an 3902 interrupt to the PCIE core for MSI/inta. */ 3903 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an 3904 interrupt to the PCIE core for MSI/inta. */ 3905 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an 3906 interrupt to the PCIE core for MSI/inta. */ 3907 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an 3908 interrupt to the PCIE core for MSI/inta. */ 3909 uint64_t dma4dbo : 1; /**< Enables NPEI_INT_SUM[8] to generate an 3910 interrupt to the PCIE core for MSI/inta. */ 3911 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an 3912 interrupt to the PCIE core for MSI/inta. */ 3913 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an 3914 interrupt to the PCIE core for MSI/inta. */ 3915 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an 3916 interrupt to the PCIE core for MSI/inta. */ 3917 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an 3918 interrupt to the PCIE core for MSI/inta. */ 3919 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an 3920 interrupt to the PCIE core for MSI/inta. */ 3921 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an 3922 interrupt to the PCIE core for MSI/inta. */ 3923 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an 3924 interrupt to the PCIE core for MSI/inta. */ 3925 uint64_t rml_rto : 1; /**< Enables NPEI_INT_SUM[0] to generate an 3926 interrupt to the PCIE core for MSI/inta. */ 3927#else 3928 uint64_t rml_rto : 1; 3929 uint64_t rml_wto : 1; 3930 uint64_t bar0_to : 1; 3931 uint64_t iob2big : 1; 3932 uint64_t dma0dbo : 1; 3933 uint64_t dma1dbo : 1; 3934 uint64_t dma2dbo : 1; 3935 uint64_t dma3dbo : 1; 3936 uint64_t dma4dbo : 1; 3937 uint64_t dma0fi : 1; 3938 uint64_t dma1fi : 1; 3939 uint64_t dcnt0 : 1; 3940 uint64_t dcnt1 : 1; 3941 uint64_t dtime0 : 1; 3942 uint64_t dtime1 : 1; 3943 uint64_t psldbof : 1; 3944 uint64_t pidbof : 1; 3945 uint64_t pcnt : 1; 3946 uint64_t ptime : 1; 3947 uint64_t c0_aeri : 1; 3948 uint64_t reserved_20_20 : 1; 3949 uint64_t c0_se : 1; 3950 uint64_t reserved_22_22 : 1; 3951 uint64_t c0_wake : 1; 3952 uint64_t c0_pmei : 1; 3953 uint64_t c0_hpint : 1; 3954 uint64_t c1_aeri : 1; 3955 uint64_t reserved_27_27 : 1; 3956 uint64_t c1_se : 1; 3957 uint64_t reserved_29_29 : 1; 3958 uint64_t c1_wake : 1; 3959 uint64_t c1_pmei : 1; 3960 uint64_t c1_hpint : 1; 3961 uint64_t c0_up_b0 : 1; 3962 uint64_t c0_up_b1 : 1; 3963 uint64_t c0_up_b2 : 1; 3964 uint64_t c0_up_wi : 1; 3965 uint64_t c0_up_bx : 1; 3966 uint64_t c0_un_b0 : 1; 3967 uint64_t c0_un_b1 : 1; 3968 uint64_t c0_un_b2 : 1; 3969 uint64_t c0_un_wi : 1; 3970 uint64_t c0_un_bx : 1; 3971 uint64_t c1_up_b0 : 1; 3972 uint64_t c1_up_b1 : 1; 3973 uint64_t c1_up_b2 : 1; 3974 uint64_t c1_up_wi : 1; 3975 uint64_t c1_up_bx : 1; 3976 uint64_t c1_un_b0 : 1; 3977 uint64_t c1_un_b1 : 1; 3978 uint64_t c1_un_b2 : 1; 3979 uint64_t c1_un_wi : 1; 3980 uint64_t c1_un_bx : 1; 3981 uint64_t c0_un_wf : 1; 3982 uint64_t c1_un_wf : 1; 3983 uint64_t c0_up_wf : 1; 3984 uint64_t c1_up_wf : 1; 3985 uint64_t c0_exc : 1; 3986 uint64_t c1_exc : 1; 3987 uint64_t c0_ldwn : 1; 3988 uint64_t c1_ldwn : 1; 3989 uint64_t reserved_61_62 : 2; 3990 uint64_t mio_inta : 1; 3991#endif 3992 } cn56xxp1; 3993}; 3994typedef union cvmx_npei_int_enb cvmx_npei_int_enb_t; 3995 3996/** 3997 * cvmx_npei_int_enb2 3998 * 3999 * NPEI_INTERRUPT_ENB2 = NPI's Interrupt Enable2 Register 4000 * 4001 * Used to enable the various interrupting conditions of NPI 4002 */ 4003union cvmx_npei_int_enb2 4004{ 4005 uint64_t u64; 4006 struct cvmx_npei_int_enb2_s 4007 { 4008#if __BYTE_ORDER == __BIG_ENDIAN 4009 uint64_t reserved_62_63 : 2; 4010 uint64_t int_a : 1; /**< Enables NPEI_INT_SUM2[61] to generate an 4011 interrupt on the RSL. */ 4012 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an 4013 interrupt on the RSL. */ 4014 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an 4015 interrupt on the RSL. */ 4016 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an 4017 interrupt on the RSL. */ 4018 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an 4019 interrupt on the RSL. */ 4020 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an 4021 interrupt on the RSL. */ 4022 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an 4023 interrupt on the RSL. */ 4024 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an 4025 interrupt on the RSL. */ 4026 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an 4027 interrupt on the RSL. */ 4028 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an 4029 interrupt on the RSL. */ 4030 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an 4031 interrupt on the RSL. */ 4032 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an 4033 interrupt on the RSL. */ 4034 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an 4035 interrupt on the RSL. */ 4036 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an 4037 interrupt on the RSL. */ 4038 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an 4039 interrupt on the RSL. */ 4040 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an 4041 interrupt on the RSL. */ 4042 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an 4043 interrupt on the RSL. */ 4044 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an 4045 interrupt on the RSL. */ 4046 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an 4047 interrupt on the RSL. */ 4048 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an 4049 interrupt on the RSL. */ 4050 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an 4051 interrupt on the RSL. */ 4052 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an 4053 interrupt on the RSL. */ 4054 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an 4055 interrupt on the RSL. */ 4056 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an 4057 interrupt on the RSL. */ 4058 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an 4059 interrupt on the RSL. */ 4060 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an 4061 interrupt on the RSL. */ 4062 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an 4063 interrupt on the RSL. */ 4064 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an 4065 interrupt on the RSL. */ 4066 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an 4067 interrupt on the RSL. */ 4068 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an 4069 interrupt on the RSL. */ 4070 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an 4071 interrupt on the RSL. */ 4072 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an 4073 interrupt on the RSL. */ 4074 uint64_t crs1_dr : 1; /**< Enables NPEI_INT_SUM2[29] to generate an 4075 interrupt on the RSL. */ 4076 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an 4077 interrupt on the RSL. */ 4078 uint64_t crs1_er : 1; /**< Enables NPEI_INT_SUM2[27] to generate an 4079 interrupt on the RSL. */ 4080 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an 4081 interrupt on the RSL. */ 4082 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an 4083 interrupt on the RSL. */ 4084 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an 4085 interrupt on the RSL. */ 4086 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an 4087 interrupt on the RSL. */ 4088 uint64_t crs0_dr : 1; /**< Enables NPEI_INT_SUM2[22] to generate an 4089 interrupt on the RSL. */ 4090 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an 4091 interrupt on the RSL. */ 4092 uint64_t crs0_er : 1; /**< Enables NPEI_INT_SUM2[20] to generate an 4093 interrupt on the RSL. */ 4094 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an 4095 interrupt on the RSL. */ 4096 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an 4097 interrupt on the RSL. */ 4098 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an 4099 interrupt on the RSL. */ 4100 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an 4101 interrupt on the RSL. */ 4102 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an 4103 interrupt on the RSL. */ 4104 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an 4105 interrupt on the RSL. */ 4106 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an 4107 interrupt on the RSL. */ 4108 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an 4109 interrupt on the RSL. */ 4110 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an 4111 interrupt on the RSL. */ 4112 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an 4113 interrupt on the RSL. */ 4114 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an 4115 interrupt on the RSL. */ 4116 uint64_t dma4dbo : 1; /**< Enables NPEI_INT_SUM[8] to generate an 4117 interrupt on the RSL. */ 4118 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an 4119 interrupt on the RSL. */ 4120 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an 4121 interrupt on the RSL. */ 4122 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an 4123 interrupt on the RSL. */ 4124 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an 4125 interrupt on the RSL. */ 4126 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an 4127 interrupt on the RSL. */ 4128 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an 4129 interrupt on the RSL. */ 4130 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an 4131 interrupt on the RSL. */ 4132 uint64_t rml_rto : 1; /**< Enables NPEI_INT_UM[0] to generate an 4133 interrupt on the RSL. */ 4134#else 4135 uint64_t rml_rto : 1; 4136 uint64_t rml_wto : 1; 4137 uint64_t bar0_to : 1; 4138 uint64_t iob2big : 1; 4139 uint64_t dma0dbo : 1; 4140 uint64_t dma1dbo : 1; 4141 uint64_t dma2dbo : 1; 4142 uint64_t dma3dbo : 1; 4143 uint64_t dma4dbo : 1; 4144 uint64_t dma0fi : 1; 4145 uint64_t dma1fi : 1; 4146 uint64_t dcnt0 : 1; 4147 uint64_t dcnt1 : 1; 4148 uint64_t dtime0 : 1; 4149 uint64_t dtime1 : 1; 4150 uint64_t psldbof : 1; 4151 uint64_t pidbof : 1; 4152 uint64_t pcnt : 1; 4153 uint64_t ptime : 1; 4154 uint64_t c0_aeri : 1; 4155 uint64_t crs0_er : 1; 4156 uint64_t c0_se : 1; 4157 uint64_t crs0_dr : 1; 4158 uint64_t c0_wake : 1; 4159 uint64_t c0_pmei : 1; 4160 uint64_t c0_hpint : 1; 4161 uint64_t c1_aeri : 1; 4162 uint64_t crs1_er : 1; 4163 uint64_t c1_se : 1; 4164 uint64_t crs1_dr : 1; 4165 uint64_t c1_wake : 1; 4166 uint64_t c1_pmei : 1; 4167 uint64_t c1_hpint : 1; 4168 uint64_t c0_up_b0 : 1; 4169 uint64_t c0_up_b1 : 1; 4170 uint64_t c0_up_b2 : 1; 4171 uint64_t c0_up_wi : 1; 4172 uint64_t c0_up_bx : 1; 4173 uint64_t c0_un_b0 : 1; 4174 uint64_t c0_un_b1 : 1; 4175 uint64_t c0_un_b2 : 1; 4176 uint64_t c0_un_wi : 1; 4177 uint64_t c0_un_bx : 1; 4178 uint64_t c1_up_b0 : 1; 4179 uint64_t c1_up_b1 : 1; 4180 uint64_t c1_up_b2 : 1; 4181 uint64_t c1_up_wi : 1; 4182 uint64_t c1_up_bx : 1; 4183 uint64_t c1_un_b0 : 1; 4184 uint64_t c1_un_b1 : 1; 4185 uint64_t c1_un_b2 : 1; 4186 uint64_t c1_un_wi : 1; 4187 uint64_t c1_un_bx : 1; 4188 uint64_t c0_un_wf : 1; 4189 uint64_t c1_un_wf : 1; 4190 uint64_t c0_up_wf : 1; 4191 uint64_t c1_up_wf : 1; 4192 uint64_t c0_exc : 1; 4193 uint64_t c1_exc : 1; 4194 uint64_t c0_ldwn : 1; 4195 uint64_t c1_ldwn : 1; 4196 uint64_t int_a : 1; 4197 uint64_t reserved_62_63 : 2; 4198#endif 4199 } s; 4200 struct cvmx_npei_int_enb2_s cn52xx; 4201 struct cvmx_npei_int_enb2_cn52xxp1 4202 { 4203#if __BYTE_ORDER == __BIG_ENDIAN 4204 uint64_t reserved_62_63 : 2; 4205 uint64_t int_a : 1; /**< Enables NPEI_INT_SUM2[61] to generate an 4206 interrupt on the RSL. */ 4207 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM2[60] to generate an 4208 interrupt on the RSL. */ 4209 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM2[59] to generate an 4210 interrupt on the RSL. */ 4211 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM2[58] to generate an 4212 interrupt on the RSL. */ 4213 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM2[57] to generate an 4214 interrupt on the RSL. */ 4215 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM2[56] to generate an 4216 interrupt on the RSL. */ 4217 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM2[55] to generate an 4218 interrupt on the RSL. */ 4219 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM2[54] to generate an 4220 interrupt on the RSL. */ 4221 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM2[53] to generate an 4222 interrupt on the RSL. */ 4223 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM2[52] to generate an 4224 interrupt on the RSL. */ 4225 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM2[51] to generate an 4226 interrupt on the RSL. */ 4227 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM2[50] to generate an 4228 interrupt on the RSL. */ 4229 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM2[49] to generate an 4230 interrupt on the RSL. */ 4231 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM2[48] to generate an 4232 interrupt on the RSL. */ 4233 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM2[47] to generate an 4234 interrupt on the RSL. */ 4235 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM2[46] to generate an 4236 interrupt on the RSL. */ 4237 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM2[45] to generate an 4238 interrupt on the RSL. */ 4239 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM2[44] to generate an 4240 interrupt on the RSL. */ 4241 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM2[43] to generate an 4242 interrupt on the RSL. */ 4243 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM2[42] to generate an 4244 interrupt on the RSL. */ 4245 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM2[41] to generate an 4246 interrupt on the RSL. */ 4247 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM2[40] to generate an 4248 interrupt on the RSL. */ 4249 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM2[39] to generate an 4250 interrupt on the RSL. */ 4251 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM2[38] to generate an 4252 interrupt on the RSL. */ 4253 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM2[37] to generate an 4254 interrupt on the RSL. */ 4255 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM2[36] to generate an 4256 interrupt on the RSL. */ 4257 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM2[35] to generate an 4258 interrupt on the RSL. */ 4259 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM2[34] to generate an 4260 interrupt on the RSL. */ 4261 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM2[33] to generate an 4262 interrupt on the RSL. */ 4263 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM2[32] to generate an 4264 interrupt on the RSL. */ 4265 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM2[31] to generate an 4266 interrupt on the RSL. */ 4267 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM2[30] to generate an 4268 interrupt on the RSL. */ 4269 uint64_t crs1_dr : 1; /**< Enables NPEI_INT_SUM2[29] to generate an 4270 interrupt on the RSL. */ 4271 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM2[28] to generate an 4272 interrupt on the RSL. */ 4273 uint64_t crs1_er : 1; /**< Enables NPEI_INT_SUM2[27] to generate an 4274 interrupt on the RSL. */ 4275 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM2[26] to generate an 4276 interrupt on the RSL. */ 4277 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM2[25] to generate an 4278 interrupt on the RSL. */ 4279 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM2[24] to generate an 4280 interrupt on the RSL. */ 4281 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM2[23] to generate an 4282 interrupt on the RSL. */ 4283 uint64_t crs0_dr : 1; /**< Enables NPEI_INT_SUM2[22] to generate an 4284 interrupt on the RSL. */ 4285 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM2[21] to generate an 4286 interrupt on the RSL. */ 4287 uint64_t crs0_er : 1; /**< Enables NPEI_INT_SUM2[20] to generate an 4288 interrupt on the RSL. */ 4289 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM2[19] to generate an 4290 interrupt on the RSL. */ 4291 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM2[18] to generate an 4292 interrupt on the RSL. */ 4293 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM2[17] to generate an 4294 interrupt on the RSL. */ 4295 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM2[16] to generate an 4296 interrupt on the RSL. */ 4297 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM2[15] to generate an 4298 interrupt on the RSL. */ 4299 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM2[14] to generate an 4300 interrupt on the RSL. */ 4301 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM2[13] to generate an 4302 interrupt on the RSL. */ 4303 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM2[12] to generate an 4304 interrupt on the RSL. */ 4305 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM2[11] to generate an 4306 interrupt on the RSL. */ 4307 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM2[10] to generate an 4308 interrupt on the RSL. */ 4309 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM2[9] to generate an 4310 interrupt on the RSL. */ 4311 uint64_t reserved_8_8 : 1; 4312 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM2[7] to generate an 4313 interrupt on the RSL. */ 4314 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM2[6] to generate an 4315 interrupt on the RSL. */ 4316 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM2[5] to generate an 4317 interrupt on the RSL. */ 4318 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM2[4] to generate an 4319 interrupt on the RSL. */ 4320 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM2[3] to generate an 4321 interrupt on the RSL. */ 4322 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM2[2] to generate an 4323 interrupt on the RSL. */ 4324 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM2[1] to generate an 4325 interrupt on the RSL. */ 4326 uint64_t rml_rto : 1; /**< Enables NPEI_INT_SUM2[0] to generate an 4327 interrupt on the RSL. */ 4328#else 4329 uint64_t rml_rto : 1; 4330 uint64_t rml_wto : 1; 4331 uint64_t bar0_to : 1; 4332 uint64_t iob2big : 1; 4333 uint64_t dma0dbo : 1; 4334 uint64_t dma1dbo : 1; 4335 uint64_t dma2dbo : 1; 4336 uint64_t dma3dbo : 1; 4337 uint64_t reserved_8_8 : 1; 4338 uint64_t dma0fi : 1; 4339 uint64_t dma1fi : 1; 4340 uint64_t dcnt0 : 1; 4341 uint64_t dcnt1 : 1; 4342 uint64_t dtime0 : 1; 4343 uint64_t dtime1 : 1; 4344 uint64_t psldbof : 1; 4345 uint64_t pidbof : 1; 4346 uint64_t pcnt : 1; 4347 uint64_t ptime : 1; 4348 uint64_t c0_aeri : 1; 4349 uint64_t crs0_er : 1; 4350 uint64_t c0_se : 1; 4351 uint64_t crs0_dr : 1; 4352 uint64_t c0_wake : 1; 4353 uint64_t c0_pmei : 1; 4354 uint64_t c0_hpint : 1; 4355 uint64_t c1_aeri : 1; 4356 uint64_t crs1_er : 1; 4357 uint64_t c1_se : 1; 4358 uint64_t crs1_dr : 1; 4359 uint64_t c1_wake : 1; 4360 uint64_t c1_pmei : 1; 4361 uint64_t c1_hpint : 1; 4362 uint64_t c0_up_b0 : 1; 4363 uint64_t c0_up_b1 : 1; 4364 uint64_t c0_up_b2 : 1; 4365 uint64_t c0_up_wi : 1; 4366 uint64_t c0_up_bx : 1; 4367 uint64_t c0_un_b0 : 1; 4368 uint64_t c0_un_b1 : 1; 4369 uint64_t c0_un_b2 : 1; 4370 uint64_t c0_un_wi : 1; 4371 uint64_t c0_un_bx : 1; 4372 uint64_t c1_up_b0 : 1; 4373 uint64_t c1_up_b1 : 1; 4374 uint64_t c1_up_b2 : 1; 4375 uint64_t c1_up_wi : 1; 4376 uint64_t c1_up_bx : 1; 4377 uint64_t c1_un_b0 : 1; 4378 uint64_t c1_un_b1 : 1; 4379 uint64_t c1_un_b2 : 1; 4380 uint64_t c1_un_wi : 1; 4381 uint64_t c1_un_bx : 1; 4382 uint64_t c0_un_wf : 1; 4383 uint64_t c1_un_wf : 1; 4384 uint64_t c0_up_wf : 1; 4385 uint64_t c1_up_wf : 1; 4386 uint64_t c0_exc : 1; 4387 uint64_t c1_exc : 1; 4388 uint64_t c0_ldwn : 1; 4389 uint64_t c1_ldwn : 1; 4390 uint64_t int_a : 1; 4391 uint64_t reserved_62_63 : 2; 4392#endif 4393 } cn52xxp1; 4394 struct cvmx_npei_int_enb2_s cn56xx; 4395 struct cvmx_npei_int_enb2_cn56xxp1 4396 { 4397#if __BYTE_ORDER == __BIG_ENDIAN 4398 uint64_t reserved_61_63 : 3; 4399 uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an 4400 interrupt on the RSL. */ 4401 uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an 4402 interrupt on the RSL. */ 4403 uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an 4404 interrupt on the RSL. */ 4405 uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an 4406 interrupt on the RSL. */ 4407 uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an 4408 interrupt on the RSL. */ 4409 uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an 4410 interrupt on the RSL. */ 4411 uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an 4412 interrupt on the RSL. */ 4413 uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an 4414 interrupt on the RSL. */ 4415 uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an 4416 interrupt on the RSL. */ 4417 uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an 4418 interrupt on the RSL. */ 4419 uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an 4420 interrupt on the RSL. */ 4421 uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an 4422 interrupt on the RSL. */ 4423 uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an 4424 interrupt on the RSL. */ 4425 uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an 4426 interrupt on the RSL. */ 4427 uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an 4428 interrupt on the RSL. */ 4429 uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an 4430 interrupt on the RSL. */ 4431 uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an 4432 interrupt on the RSL. */ 4433 uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an 4434 interrupt on the RSL. */ 4435 uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an 4436 interrupt on the RSL. */ 4437 uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an 4438 interrupt on the RSL. */ 4439 uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an 4440 interrupt on the RSL. */ 4441 uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an 4442 interrupt on the RSL. */ 4443 uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an 4444 interrupt on the RSL. */ 4445 uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an 4446 interrupt on the RSL. */ 4447 uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an 4448 interrupt on the RSL. */ 4449 uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an 4450 interrupt on the RSL. */ 4451 uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an 4452 interrupt on the RSL. */ 4453 uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an 4454 interrupt on the RSL. */ 4455 uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an 4456 interrupt on the RSL. */ 4457 uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an 4458 interrupt on the RSL. */ 4459 uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an 4460 interrupt on the RSL. */ 4461 uint64_t reserved_29_29 : 1; 4462 uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an 4463 interrupt on the RSL. */ 4464 uint64_t reserved_27_27 : 1; 4465 uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an 4466 interrupt on the RSL. */ 4467 uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an 4468 interrupt on the RSL. */ 4469 uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an 4470 interrupt on the RSL. */ 4471 uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an 4472 interrupt on the RSL. */ 4473 uint64_t reserved_22_22 : 1; 4474 uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an 4475 interrupt on the RSL. */ 4476 uint64_t reserved_20_20 : 1; 4477 uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an 4478 interrupt on the RSL. */ 4479 uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an 4480 interrupt on the RSL. */ 4481 uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an 4482 interrupt on the RSL. */ 4483 uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an 4484 interrupt on the RSL. */ 4485 uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an 4486 interrupt on the RSL. */ 4487 uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an 4488 interrupt on the RSL. */ 4489 uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an 4490 interrupt on the RSL. */ 4491 uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an 4492 interrupt on the RSL. */ 4493 uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an 4494 interrupt on the RSL. */ 4495 uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an 4496 interrupt on the RSL. */ 4497 uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an 4498 interrupt on the RSL. */ 4499 uint64_t dma4dbo : 1; /**< Enables NPEI_INT_SUM[8] to generate an 4500 interrupt on the RSL. */ 4501 uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an 4502 interrupt on the RSL. */ 4503 uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an 4504 interrupt on the RSL. */ 4505 uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an 4506 interrupt on the RSL. */ 4507 uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an 4508 interrupt on the RSL. */ 4509 uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an 4510 interrupt on the RSL. */ 4511 uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an 4512 interrupt on the RSL. */ 4513 uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an 4514 interrupt on the RSL. */ 4515 uint64_t rml_rto : 1; /**< Enables NPEI_INT_UM[0] to generate an 4516 interrupt on the RSL. */ 4517#else 4518 uint64_t rml_rto : 1; 4519 uint64_t rml_wto : 1; 4520 uint64_t bar0_to : 1; 4521 uint64_t iob2big : 1; 4522 uint64_t dma0dbo : 1; 4523 uint64_t dma1dbo : 1; 4524 uint64_t dma2dbo : 1; 4525 uint64_t dma3dbo : 1; 4526 uint64_t dma4dbo : 1; 4527 uint64_t dma0fi : 1; 4528 uint64_t dma1fi : 1; 4529 uint64_t dcnt0 : 1; 4530 uint64_t dcnt1 : 1; 4531 uint64_t dtime0 : 1; 4532 uint64_t dtime1 : 1; 4533 uint64_t psldbof : 1; 4534 uint64_t pidbof : 1; 4535 uint64_t pcnt : 1; 4536 uint64_t ptime : 1; 4537 uint64_t c0_aeri : 1; 4538 uint64_t reserved_20_20 : 1; 4539 uint64_t c0_se : 1; 4540 uint64_t reserved_22_22 : 1; 4541 uint64_t c0_wake : 1; 4542 uint64_t c0_pmei : 1; 4543 uint64_t c0_hpint : 1; 4544 uint64_t c1_aeri : 1; 4545 uint64_t reserved_27_27 : 1; 4546 uint64_t c1_se : 1; 4547 uint64_t reserved_29_29 : 1; 4548 uint64_t c1_wake : 1; 4549 uint64_t c1_pmei : 1; 4550 uint64_t c1_hpint : 1; 4551 uint64_t c0_up_b0 : 1; 4552 uint64_t c0_up_b1 : 1; 4553 uint64_t c0_up_b2 : 1; 4554 uint64_t c0_up_wi : 1; 4555 uint64_t c0_up_bx : 1; 4556 uint64_t c0_un_b0 : 1; 4557 uint64_t c0_un_b1 : 1; 4558 uint64_t c0_un_b2 : 1; 4559 uint64_t c0_un_wi : 1; 4560 uint64_t c0_un_bx : 1; 4561 uint64_t c1_up_b0 : 1; 4562 uint64_t c1_up_b1 : 1; 4563 uint64_t c1_up_b2 : 1; 4564 uint64_t c1_up_wi : 1; 4565 uint64_t c1_up_bx : 1; 4566 uint64_t c1_un_b0 : 1; 4567 uint64_t c1_un_b1 : 1; 4568 uint64_t c1_un_b2 : 1; 4569 uint64_t c1_un_wi : 1; 4570 uint64_t c1_un_bx : 1; 4571 uint64_t c0_un_wf : 1; 4572 uint64_t c1_un_wf : 1; 4573 uint64_t c0_up_wf : 1; 4574 uint64_t c1_up_wf : 1; 4575 uint64_t c0_exc : 1; 4576 uint64_t c1_exc : 1; 4577 uint64_t c0_ldwn : 1; 4578 uint64_t c1_ldwn : 1; 4579 uint64_t reserved_61_63 : 3; 4580#endif 4581 } cn56xxp1; 4582}; 4583typedef union cvmx_npei_int_enb2 cvmx_npei_int_enb2_t; 4584 4585/** 4586 * cvmx_npei_int_info 4587 * 4588 * NPEI_INT_INFO = NPI Interrupt Information 4589 * 4590 * Contains information about some of the interrupt condition that can occur in the NPEI_INTERRUPT_SUM register. 4591 */ 4592union cvmx_npei_int_info 4593{ 4594 uint64_t u64; 4595 struct cvmx_npei_int_info_s 4596 { 4597#if __BYTE_ORDER == __BIG_ENDIAN 4598 uint64_t reserved_12_63 : 52; 4599 uint64_t pidbof : 6; /**< Field set when the NPEI_INTERRUPT_SUM[PIDBOF] bit 4600 is set. This field when set will not change again 4601 unitl NPEI_INTERRUPT_SUM[PIDBOF] is cleared. */ 4602 uint64_t psldbof : 6; /**< Field set when the NPEI_INTERRUPT_SUM[PSLDBOF] bit 4603 is set. This field when set will not change again 4604 unitl NPEI_INTERRUPT_SUM[PSLDBOF] is cleared. */ 4605#else 4606 uint64_t psldbof : 6; 4607 uint64_t pidbof : 6; 4608 uint64_t reserved_12_63 : 52; 4609#endif 4610 } s; 4611 struct cvmx_npei_int_info_s cn52xx; 4612 struct cvmx_npei_int_info_s cn56xx; 4613 struct cvmx_npei_int_info_s cn56xxp1; 4614}; 4615typedef union cvmx_npei_int_info cvmx_npei_int_info_t; 4616 4617/** 4618 * cvmx_npei_int_sum 4619 * 4620 * NPEI_INTERRUPT_SUM = NPI Interrupt Summary Register 4621 * 4622 * Set when an interrupt condition occurs, write '1' to clear. 4623 * 4624 * HACK: These used to exist, how are TO handled? 4625 * <3> PO0_2SML R/W1C 0x0 0 The packet being sent out on Port0 is smaller $R NS 4626 * than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. 4627 * <7> I0_RTOUT R/W1C 0x0 0 Port-0 had a read timeout while attempting to $R NS 4628 * read instructions. 4629 * <15> P0_RTOUT R/W1C 0x0 0 Port-0 had a read timeout while attempting to $R NS 4630 * read packet data. 4631 * <23> G0_RTOUT R/W1C 0x0 0 Port-0 had a read timeout while attempting to $R NS 4632 * read a gather list. 4633 * <31> P0_PTOUT R/W1C 0x0 0 Port-0 output had a read timeout on a DATA/INFO $R NS 4634 * pair. 4635 */ 4636union cvmx_npei_int_sum 4637{ 4638 uint64_t u64; 4639 struct cvmx_npei_int_sum_s 4640 { 4641#if __BYTE_ORDER == __BIG_ENDIAN 4642 uint64_t mio_inta : 1; /**< Interrupt from MIO. */ 4643 uint64_t reserved_62_62 : 1; 4644 uint64_t int_a : 1; /**< Set when a bit in the NPEI_INT_A_SUM register and 4645 the cooresponding bit in the NPEI_INT_A_ENB 4646 register is set. */ 4647 uint64_t c1_ldwn : 1; /**< Reset request due to link1 down status. */ 4648 uint64_t c0_ldwn : 1; /**< Reset request due to link0 down status. */ 4649 uint64_t c1_exc : 1; /**< Set when the PESC1_DBG_INFO register has a bit 4650 set and its cooresponding PESC1_DBG_INFO_EN bit 4651 is set. */ 4652 uint64_t c0_exc : 1; /**< Set when the PESC0_DBG_INFO register has a bit 4653 set and its cooresponding PESC0_DBG_INFO_EN bit 4654 is set. */ 4655 uint64_t c1_up_wf : 1; /**< Received Unsupported P-TLP for filtered window 4656 register. Core1. */ 4657 uint64_t c0_up_wf : 1; /**< Received Unsupported P-TLP for filtered window 4658 register. Core0. */ 4659 uint64_t c1_un_wf : 1; /**< Received Unsupported N-TLP for filtered window 4660 register. Core1. */ 4661 uint64_t c0_un_wf : 1; /**< Received Unsupported N-TLP for filtered window 4662 register. Core0. */ 4663 uint64_t c1_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar. 4664 Core 1. */ 4665 uint64_t c1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register. 4666 Core 1. */ 4667 uint64_t c1_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2. 4668 Core 1. */ 4669 uint64_t c1_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1. 4670 Core 1. */ 4671 uint64_t c1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0. 4672 Core 1. */ 4673 uint64_t c1_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar. 4674 Core 1. */ 4675 uint64_t c1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register. 4676 Core 1. */ 4677 uint64_t c1_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2. 4678 Core 1. */ 4679 uint64_t c1_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1. 4680 Core 1. */ 4681 uint64_t c1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0. 4682 Core 1. */ 4683 uint64_t c0_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar. 4684 Core 0. */ 4685 uint64_t c0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register. 4686 Core 0. */ 4687 uint64_t c0_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2. 4688 Core 0. */ 4689 uint64_t c0_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1. 4690 Core 0. */ 4691 uint64_t c0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0. 4692 Core 0. */ 4693 uint64_t c0_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar. 4694 Core 0. */ 4695 uint64_t c0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register. 4696 Core 0. */ 4697 uint64_t c0_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2. 4698 Core 0. */ 4699 uint64_t c0_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1. 4700 Core 0. */ 4701 uint64_t c0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0. 4702 Core 0. */ 4703 uint64_t c1_hpint : 1; /**< Hot-Plug Interrupt. 4704 Pcie Core 1 (hp_int). 4705 This interrupt will only be generated when 4706 PCIERC1_CFG034[DLLS_C] is generated. Hot plug is 4707 not supported. */ 4708 uint64_t c1_pmei : 1; /**< PME Interrupt. 4709 Pcie Core 1. (cfg_pme_int) */ 4710 uint64_t c1_wake : 1; /**< Wake up from Power Management Unit. 4711 Pcie Core 1. (wake_n) 4712 Octeon will never generate this interrupt. */ 4713 uint64_t crs1_dr : 1; /**< Had a CRS when Retries were disabled. */ 4714 uint64_t c1_se : 1; /**< System Error, RC Mode Only. 4715 Pcie Core 1. (cfg_sys_err_rc) */ 4716 uint64_t crs1_er : 1; /**< Had a CRS Timeout when Retries were enabled. */ 4717 uint64_t c1_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only. 4718 Pcie Core 1. */ 4719 uint64_t c0_hpint : 1; /**< Hot-Plug Interrupt. 4720 Pcie Core 0 (hp_int). 4721 This interrupt will only be generated when 4722 PCIERC0_CFG034[DLLS_C] is generated. Hot plug is 4723 not supported. */ 4724 uint64_t c0_pmei : 1; /**< PME Interrupt. 4725 Pcie Core 0. (cfg_pme_int) */ 4726 uint64_t c0_wake : 1; /**< Wake up from Power Management Unit. 4727 Pcie Core 0. (wake_n) 4728 Octeon will never generate this interrupt. */ 4729 uint64_t crs0_dr : 1; /**< Had a CRS when Retries were disabled. */ 4730 uint64_t c0_se : 1; /**< System Error, RC Mode Only. 4731 Pcie Core 0. (cfg_sys_err_rc) */ 4732 uint64_t crs0_er : 1; /**< Had a CRS Timeout when Retries were enabled. */ 4733 uint64_t c0_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only. 4734 Pcie Core 0 (cfg_aer_rc_err_int). */ 4735 uint64_t ptime : 1; /**< Packet Timer has an interrupt. Which rings can 4736 be found in NPEI_PKT_TIME_INT. */ 4737 uint64_t pcnt : 1; /**< Packet Counter has an interrupt. Which rings can 4738 be found in NPEI_PKT_CNT_INT. */ 4739 uint64_t pidbof : 1; /**< Packet Instruction Doorbell count overflowed. Which 4740 doorbell can be found in NPEI_INT_INFO[PIDBOF] */ 4741 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell count overflowed. Which 4742 doorbell can be found in NPEI_INT_INFO[PSLDBOF] */ 4743 uint64_t dtime1 : 1; /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the 4744 DMA_CNT1 timer increments every core clock. When 4745 DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME], 4746 this bit is set. Writing a '1' to this bit also 4747 clears the DMA_CNT1 timer. */ 4748 uint64_t dtime0 : 1; /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the 4749 DMA_CNT0 timer increments every core clock. When 4750 DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME], 4751 this bit is set. Writing a '1' to this bit also 4752 clears the DMA_CNT0 timer. */ 4753 uint64_t dcnt1 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is 4754 greater than NPEI_DMA1_INT_LEVEL[CNT]. */ 4755 uint64_t dcnt0 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is 4756 greater than NPEI_DMA0_INT_LEVEL[CNT]. */ 4757 uint64_t dma1fi : 1; /**< DMA0 set Forced Interrupt. */ 4758 uint64_t dma0fi : 1; /**< DMA0 set Forced Interrupt. */ 4759 uint64_t dma4dbo : 1; /**< DMA4 doorbell overflow. 4760 Bit[32] of the doorbell count was set. */ 4761 uint64_t dma3dbo : 1; /**< DMA3 doorbell overflow. 4762 Bit[32] of the doorbell count was set. */ 4763 uint64_t dma2dbo : 1; /**< DMA2 doorbell overflow. 4764 Bit[32] of the doorbell count was set. */ 4765 uint64_t dma1dbo : 1; /**< DMA1 doorbell overflow. 4766 Bit[32] of the doorbell count was set. */ 4767 uint64_t dma0dbo : 1; /**< DMA0 doorbell overflow. 4768 Bit[32] of the doorbell count was set. */ 4769 uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */ 4770 uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive 4771 read-data/commit in 0xffff core clocks. */ 4772 uint64_t rml_wto : 1; /**< RML write did not get commit in 0xffff core clocks. */ 4773 uint64_t rml_rto : 1; /**< RML read did not return data in 0xffff core clocks. */ 4774#else 4775 uint64_t rml_rto : 1; 4776 uint64_t rml_wto : 1; 4777 uint64_t bar0_to : 1; 4778 uint64_t iob2big : 1; 4779 uint64_t dma0dbo : 1; 4780 uint64_t dma1dbo : 1; 4781 uint64_t dma2dbo : 1; 4782 uint64_t dma3dbo : 1; 4783 uint64_t dma4dbo : 1; 4784 uint64_t dma0fi : 1; 4785 uint64_t dma1fi : 1; 4786 uint64_t dcnt0 : 1; 4787 uint64_t dcnt1 : 1; 4788 uint64_t dtime0 : 1; 4789 uint64_t dtime1 : 1; 4790 uint64_t psldbof : 1; 4791 uint64_t pidbof : 1; 4792 uint64_t pcnt : 1; 4793 uint64_t ptime : 1; 4794 uint64_t c0_aeri : 1; 4795 uint64_t crs0_er : 1; 4796 uint64_t c0_se : 1; 4797 uint64_t crs0_dr : 1; 4798 uint64_t c0_wake : 1; 4799 uint64_t c0_pmei : 1; 4800 uint64_t c0_hpint : 1; 4801 uint64_t c1_aeri : 1; 4802 uint64_t crs1_er : 1; 4803 uint64_t c1_se : 1; 4804 uint64_t crs1_dr : 1; 4805 uint64_t c1_wake : 1; 4806 uint64_t c1_pmei : 1; 4807 uint64_t c1_hpint : 1; 4808 uint64_t c0_up_b0 : 1; 4809 uint64_t c0_up_b1 : 1; 4810 uint64_t c0_up_b2 : 1; 4811 uint64_t c0_up_wi : 1; 4812 uint64_t c0_up_bx : 1; 4813 uint64_t c0_un_b0 : 1; 4814 uint64_t c0_un_b1 : 1; 4815 uint64_t c0_un_b2 : 1; 4816 uint64_t c0_un_wi : 1; 4817 uint64_t c0_un_bx : 1; 4818 uint64_t c1_up_b0 : 1; 4819 uint64_t c1_up_b1 : 1; 4820 uint64_t c1_up_b2 : 1; 4821 uint64_t c1_up_wi : 1; 4822 uint64_t c1_up_bx : 1; 4823 uint64_t c1_un_b0 : 1; 4824 uint64_t c1_un_b1 : 1; 4825 uint64_t c1_un_b2 : 1; 4826 uint64_t c1_un_wi : 1; 4827 uint64_t c1_un_bx : 1; 4828 uint64_t c0_un_wf : 1; 4829 uint64_t c1_un_wf : 1; 4830 uint64_t c0_up_wf : 1; 4831 uint64_t c1_up_wf : 1; 4832 uint64_t c0_exc : 1; 4833 uint64_t c1_exc : 1; 4834 uint64_t c0_ldwn : 1; 4835 uint64_t c1_ldwn : 1; 4836 uint64_t int_a : 1; 4837 uint64_t reserved_62_62 : 1; 4838 uint64_t mio_inta : 1; 4839#endif 4840 } s; 4841 struct cvmx_npei_int_sum_s cn52xx; 4842 struct cvmx_npei_int_sum_cn52xxp1 4843 { 4844#if __BYTE_ORDER == __BIG_ENDIAN 4845 uint64_t mio_inta : 1; /**< Interrupt from MIO. */ 4846 uint64_t reserved_62_62 : 1; 4847 uint64_t int_a : 1; /**< Set when a bit in the NPEI_INT_A_SUM register and 4848 the cooresponding bit in the NPEI_INT_A_ENB 4849 register is set. */ 4850 uint64_t c1_ldwn : 1; /**< Reset request due to link1 down status. */ 4851 uint64_t c0_ldwn : 1; /**< Reset request due to link0 down status. */ 4852 uint64_t c1_exc : 1; /**< Set when the PESC1_DBG_INFO register has a bit 4853 set and its cooresponding PESC1_DBG_INFO_EN bit 4854 is set. */ 4855 uint64_t c0_exc : 1; /**< Set when the PESC0_DBG_INFO register has a bit 4856 set and its cooresponding PESC0_DBG_INFO_EN bit 4857 is set. */ 4858 uint64_t c1_up_wf : 1; /**< Received Unsupported P-TLP for filtered window 4859 register. Core1. */ 4860 uint64_t c0_up_wf : 1; /**< Received Unsupported P-TLP for filtered window 4861 register. Core0. */ 4862 uint64_t c1_un_wf : 1; /**< Received Unsupported N-TLP for filtered window 4863 register. Core1. */ 4864 uint64_t c0_un_wf : 1; /**< Received Unsupported N-TLP for filtered window 4865 register. Core0. */ 4866 uint64_t c1_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar. 4867 Core 1. */ 4868 uint64_t c1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register. 4869 Core 1. */ 4870 uint64_t c1_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2. 4871 Core 1. */ 4872 uint64_t c1_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1. 4873 Core 1. */ 4874 uint64_t c1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0. 4875 Core 1. */ 4876 uint64_t c1_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar. 4877 Core 1. */ 4878 uint64_t c1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register. 4879 Core 1. */ 4880 uint64_t c1_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2. 4881 Core 1. */ 4882 uint64_t c1_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1. 4883 Core 1. */ 4884 uint64_t c1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0. 4885 Core 1. */ 4886 uint64_t c0_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar. 4887 Core 0. */ 4888 uint64_t c0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register. 4889 Core 0. */ 4890 uint64_t c0_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2. 4891 Core 0. */ 4892 uint64_t c0_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1. 4893 Core 0. */ 4894 uint64_t c0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0. 4895 Core 0. */ 4896 uint64_t c0_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar. 4897 Core 0. */ 4898 uint64_t c0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register. 4899 Core 0. */ 4900 uint64_t c0_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2. 4901 Core 0. */ 4902 uint64_t c0_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1. 4903 Core 0. */ 4904 uint64_t c0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0. 4905 Core 0. */ 4906 uint64_t c1_hpint : 1; /**< Hot-Plug Interrupt. 4907 Pcie Core 1 (hp_int). 4908 This interrupt will only be generated when 4909 PCIERC1_CFG034[DLLS_C] is generated. Hot plug is 4910 not supported. */ 4911 uint64_t c1_pmei : 1; /**< PME Interrupt. 4912 Pcie Core 1. (cfg_pme_int) */ 4913 uint64_t c1_wake : 1; /**< Wake up from Power Management Unit. 4914 Pcie Core 1. (wake_n) 4915 Octeon will never generate this interrupt. */ 4916 uint64_t crs1_dr : 1; /**< Had a CRS when Retries were disabled. */ 4917 uint64_t c1_se : 1; /**< System Error, RC Mode Only. 4918 Pcie Core 1. (cfg_sys_err_rc) */ 4919 uint64_t crs1_er : 1; /**< Had a CRS Timeout when Retries were enabled. */ 4920 uint64_t c1_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only. 4921 Pcie Core 1. */ 4922 uint64_t c0_hpint : 1; /**< Hot-Plug Interrupt. 4923 Pcie Core 0 (hp_int). 4924 This interrupt will only be generated when 4925 PCIERC0_CFG034[DLLS_C] is generated. Hot plug is 4926 not supported. */ 4927 uint64_t c0_pmei : 1; /**< PME Interrupt. 4928 Pcie Core 0. (cfg_pme_int) */ 4929 uint64_t c0_wake : 1; /**< Wake up from Power Management Unit. 4930 Pcie Core 0. (wake_n) 4931 Octeon will never generate this interrupt. */ 4932 uint64_t crs0_dr : 1; /**< Had a CRS when Retries were disabled. */ 4933 uint64_t c0_se : 1; /**< System Error, RC Mode Only. 4934 Pcie Core 0. (cfg_sys_err_rc) */ 4935 uint64_t crs0_er : 1; /**< Had a CRS Timeout when Retries were enabled. */ 4936 uint64_t c0_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only. 4937 Pcie Core 0 (cfg_aer_rc_err_int). */ 4938 uint64_t reserved_15_18 : 4; 4939 uint64_t dtime1 : 1; /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the 4940 DMA_CNT1 timer increments every core clock. When 4941 DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME], 4942 this bit is set. Writing a '1' to this bit also 4943 clears the DMA_CNT1 timer. */ 4944 uint64_t dtime0 : 1; /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the 4945 DMA_CNT0 timer increments every core clock. When 4946 DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME], 4947 this bit is set. Writing a '1' to this bit also 4948 clears the DMA_CNT0 timer. */ 4949 uint64_t dcnt1 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is 4950 greater than NPEI_DMA1_INT_LEVEL[CNT]. */ 4951 uint64_t dcnt0 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is 4952 greater than NPEI_DMA0_INT_LEVEL[CNT]. */ 4953 uint64_t dma1fi : 1; /**< DMA0 set Forced Interrupt. */ 4954 uint64_t dma0fi : 1; /**< DMA0 set Forced Interrupt. */ 4955 uint64_t reserved_8_8 : 1; 4956 uint64_t dma3dbo : 1; /**< DMA3 doorbell count overflow. 4957 Bit[32] of the doorbell count was set. */ 4958 uint64_t dma2dbo : 1; /**< DMA2 doorbell count overflow. 4959 Bit[32] of the doorbell count was set. */ 4960 uint64_t dma1dbo : 1; /**< DMA1 doorbell count overflow. 4961 Bit[32] of the doorbell count was set. */ 4962 uint64_t dma0dbo : 1; /**< DMA0 doorbell count overflow. 4963 Bit[32] of the doorbell count was set. */ 4964 uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */ 4965 uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive 4966 read-data/commit in 0xffff core clocks. */ 4967 uint64_t rml_wto : 1; /**< RML write did not get commit in 0xffff core clocks. */ 4968 uint64_t rml_rto : 1; /**< RML read did not return data in 0xffff core clocks. */ 4969#else 4970 uint64_t rml_rto : 1; 4971 uint64_t rml_wto : 1; 4972 uint64_t bar0_to : 1; 4973 uint64_t iob2big : 1; 4974 uint64_t dma0dbo : 1; 4975 uint64_t dma1dbo : 1; 4976 uint64_t dma2dbo : 1; 4977 uint64_t dma3dbo : 1; 4978 uint64_t reserved_8_8 : 1; 4979 uint64_t dma0fi : 1; 4980 uint64_t dma1fi : 1; 4981 uint64_t dcnt0 : 1; 4982 uint64_t dcnt1 : 1; 4983 uint64_t dtime0 : 1; 4984 uint64_t dtime1 : 1; 4985 uint64_t reserved_15_18 : 4; 4986 uint64_t c0_aeri : 1; 4987 uint64_t crs0_er : 1; 4988 uint64_t c0_se : 1; 4989 uint64_t crs0_dr : 1; 4990 uint64_t c0_wake : 1; 4991 uint64_t c0_pmei : 1; 4992 uint64_t c0_hpint : 1; 4993 uint64_t c1_aeri : 1; 4994 uint64_t crs1_er : 1; 4995 uint64_t c1_se : 1; 4996 uint64_t crs1_dr : 1; 4997 uint64_t c1_wake : 1; 4998 uint64_t c1_pmei : 1; 4999 uint64_t c1_hpint : 1; 5000 uint64_t c0_up_b0 : 1; 5001 uint64_t c0_up_b1 : 1; 5002 uint64_t c0_up_b2 : 1; 5003 uint64_t c0_up_wi : 1; 5004 uint64_t c0_up_bx : 1; 5005 uint64_t c0_un_b0 : 1; 5006 uint64_t c0_un_b1 : 1; 5007 uint64_t c0_un_b2 : 1; 5008 uint64_t c0_un_wi : 1; 5009 uint64_t c0_un_bx : 1; 5010 uint64_t c1_up_b0 : 1; 5011 uint64_t c1_up_b1 : 1; 5012 uint64_t c1_up_b2 : 1; 5013 uint64_t c1_up_wi : 1; 5014 uint64_t c1_up_bx : 1; 5015 uint64_t c1_un_b0 : 1; 5016 uint64_t c1_un_b1 : 1; 5017 uint64_t c1_un_b2 : 1; 5018 uint64_t c1_un_wi : 1; 5019 uint64_t c1_un_bx : 1; 5020 uint64_t c0_un_wf : 1; 5021 uint64_t c1_un_wf : 1; 5022 uint64_t c0_up_wf : 1; 5023 uint64_t c1_up_wf : 1; 5024 uint64_t c0_exc : 1; 5025 uint64_t c1_exc : 1; 5026 uint64_t c0_ldwn : 1; 5027 uint64_t c1_ldwn : 1; 5028 uint64_t int_a : 1; 5029 uint64_t reserved_62_62 : 1; 5030 uint64_t mio_inta : 1; 5031#endif 5032 } cn52xxp1; 5033 struct cvmx_npei_int_sum_s cn56xx; 5034 struct cvmx_npei_int_sum_cn56xxp1 5035 { 5036#if __BYTE_ORDER == __BIG_ENDIAN 5037 uint64_t mio_inta : 1; /**< Interrupt from MIO. */ 5038 uint64_t reserved_61_62 : 2; 5039 uint64_t c1_ldwn : 1; /**< Reset request due to link1 down status. */ 5040 uint64_t c0_ldwn : 1; /**< Reset request due to link0 down status. */ 5041 uint64_t c1_exc : 1; /**< Set when the PESC1_DBG_INFO register has a bit 5042 set and its cooresponding PESC1_DBG_INFO_EN bit 5043 is set. */ 5044 uint64_t c0_exc : 1; /**< Set when the PESC0_DBG_INFO register has a bit 5045 set and its cooresponding PESC0_DBG_INFO_EN bit 5046 is set. */ 5047 uint64_t c1_up_wf : 1; /**< Received Unsupported P-TLP for filtered window 5048 register. Core1. */ 5049 uint64_t c0_up_wf : 1; /**< Received Unsupported P-TLP for filtered window 5050 register. Core0. */ 5051 uint64_t c1_un_wf : 1; /**< Received Unsupported N-TLP for filtered window 5052 register. Core1. */ 5053 uint64_t c0_un_wf : 1; /**< Received Unsupported N-TLP for filtered window 5054 register. Core0. */ 5055 uint64_t c1_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar. 5056 Core 1. */ 5057 uint64_t c1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register. 5058 Core 1. */ 5059 uint64_t c1_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2. 5060 Core 1. */ 5061 uint64_t c1_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1. 5062 Core 1. */ 5063 uint64_t c1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0. 5064 Core 1. */ 5065 uint64_t c1_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar. 5066 Core 1. */ 5067 uint64_t c1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register. 5068 Core 1. */ 5069 uint64_t c1_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2. 5070 Core 1. */ 5071 uint64_t c1_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1. 5072 Core 1. */ 5073 uint64_t c1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0. 5074 Core 1. */ 5075 uint64_t c0_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar. 5076 Core 0. */ 5077 uint64_t c0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register. 5078 Core 0. */ 5079 uint64_t c0_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2. 5080 Core 0. */ 5081 uint64_t c0_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1. 5082 Core 0. */ 5083 uint64_t c0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0. 5084 Core 0. */ 5085 uint64_t c0_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar. 5086 Core 0. */ 5087 uint64_t c0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register. 5088 Core 0. */ 5089 uint64_t c0_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2. 5090 Core 0. */ 5091 uint64_t c0_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1. 5092 Core 0. */ 5093 uint64_t c0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0. 5094 Core 0. */ 5095 uint64_t c1_hpint : 1; /**< Hot-Plug Interrupt. 5096 Pcie Core 1 (hp_int). 5097 This interrupt will only be generated when 5098 PCIERC1_CFG034[DLLS_C] is generated. Hot plug is 5099 not supported. */ 5100 uint64_t c1_pmei : 1; /**< PME Interrupt. 5101 Pcie Core 1. (cfg_pme_int) */ 5102 uint64_t c1_wake : 1; /**< Wake up from Power Management Unit. 5103 Pcie Core 1. (wake_n) 5104 Octeon will never generate this interrupt. */ 5105 uint64_t reserved_29_29 : 1; 5106 uint64_t c1_se : 1; /**< System Error, RC Mode Only. 5107 Pcie Core 1. (cfg_sys_err_rc) */ 5108 uint64_t reserved_27_27 : 1; 5109 uint64_t c1_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only. 5110 Pcie Core 1. */ 5111 uint64_t c0_hpint : 1; /**< Hot-Plug Interrupt. 5112 Pcie Core 0 (hp_int). 5113 This interrupt will only be generated when 5114 PCIERC0_CFG034[DLLS_C] is generated. Hot plug is 5115 not supported. */ 5116 uint64_t c0_pmei : 1; /**< PME Interrupt. 5117 Pcie Core 0. (cfg_pme_int) */ 5118 uint64_t c0_wake : 1; /**< Wake up from Power Management Unit. 5119 Pcie Core 0. (wake_n) 5120 Octeon will never generate this interrupt. */ 5121 uint64_t reserved_22_22 : 1; 5122 uint64_t c0_se : 1; /**< System Error, RC Mode Only. 5123 Pcie Core 0. (cfg_sys_err_rc) */ 5124 uint64_t reserved_20_20 : 1; 5125 uint64_t c0_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only. 5126 Pcie Core 0 (cfg_aer_rc_err_int). */ 5127 uint64_t reserved_15_18 : 4; 5128 uint64_t dtime1 : 1; /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the 5129 DMA_CNT1 timer increments every core clock. When 5130 DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME], 5131 this bit is set. Writing a '1' to this bit also 5132 clears the DMA_CNT1 timer. */ 5133 uint64_t dtime0 : 1; /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the 5134 DMA_CNT0 timer increments every core clock. When 5135 DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME], 5136 this bit is set. Writing a '1' to this bit also 5137 clears the DMA_CNT0 timer. */ 5138 uint64_t dcnt1 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is 5139 greater than NPEI_DMA1_INT_LEVEL[CNT]. */ 5140 uint64_t dcnt0 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is 5141 greater than NPEI_DMA0_INT_LEVEL[CNT]. */ 5142 uint64_t dma1fi : 1; /**< DMA0 set Forced Interrupt. */ 5143 uint64_t dma0fi : 1; /**< DMA0 set Forced Interrupt. */ 5144 uint64_t dma4dbo : 1; /**< DMA4 doorbell overflow. 5145 Bit[32] of the doorbell count was set. */ 5146 uint64_t dma3dbo : 1; /**< DMA3 doorbell overflow. 5147 Bit[32] of the doorbell count was set. */ 5148 uint64_t dma2dbo : 1; /**< DMA2 doorbell overflow. 5149 Bit[32] of the doorbell count was set. */ 5150 uint64_t dma1dbo : 1; /**< DMA1 doorbell overflow. 5151 Bit[32] of the doorbell count was set. */ 5152 uint64_t dma0dbo : 1; /**< DMA0 doorbell overflow. 5153 Bit[32] of the doorbell count was set. */ 5154 uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */ 5155 uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive 5156 read-data/commit in 0xffff core clocks. */ 5157 uint64_t rml_wto : 1; /**< RML write did not get commit in 0xffff core clocks. */ 5158 uint64_t rml_rto : 1; /**< RML read did not return data in 0xffff core clocks. */ 5159#else 5160 uint64_t rml_rto : 1; 5161 uint64_t rml_wto : 1; 5162 uint64_t bar0_to : 1; 5163 uint64_t iob2big : 1; 5164 uint64_t dma0dbo : 1; 5165 uint64_t dma1dbo : 1; 5166 uint64_t dma2dbo : 1; 5167 uint64_t dma3dbo : 1; 5168 uint64_t dma4dbo : 1; 5169 uint64_t dma0fi : 1; 5170 uint64_t dma1fi : 1; 5171 uint64_t dcnt0 : 1; 5172 uint64_t dcnt1 : 1; 5173 uint64_t dtime0 : 1; 5174 uint64_t dtime1 : 1; 5175 uint64_t reserved_15_18 : 4; 5176 uint64_t c0_aeri : 1; 5177 uint64_t reserved_20_20 : 1; 5178 uint64_t c0_se : 1; 5179 uint64_t reserved_22_22 : 1; 5180 uint64_t c0_wake : 1; 5181 uint64_t c0_pmei : 1; 5182 uint64_t c0_hpint : 1; 5183 uint64_t c1_aeri : 1; 5184 uint64_t reserved_27_27 : 1; 5185 uint64_t c1_se : 1; 5186 uint64_t reserved_29_29 : 1; 5187 uint64_t c1_wake : 1; 5188 uint64_t c1_pmei : 1; 5189 uint64_t c1_hpint : 1; 5190 uint64_t c0_up_b0 : 1; 5191 uint64_t c0_up_b1 : 1; 5192 uint64_t c0_up_b2 : 1; 5193 uint64_t c0_up_wi : 1; 5194 uint64_t c0_up_bx : 1; 5195 uint64_t c0_un_b0 : 1; 5196 uint64_t c0_un_b1 : 1; 5197 uint64_t c0_un_b2 : 1; 5198 uint64_t c0_un_wi : 1; 5199 uint64_t c0_un_bx : 1; 5200 uint64_t c1_up_b0 : 1; 5201 uint64_t c1_up_b1 : 1; 5202 uint64_t c1_up_b2 : 1; 5203 uint64_t c1_up_wi : 1; 5204 uint64_t c1_up_bx : 1; 5205 uint64_t c1_un_b0 : 1; 5206 uint64_t c1_un_b1 : 1; 5207 uint64_t c1_un_b2 : 1; 5208 uint64_t c1_un_wi : 1; 5209 uint64_t c1_un_bx : 1; 5210 uint64_t c0_un_wf : 1; 5211 uint64_t c1_un_wf : 1; 5212 uint64_t c0_up_wf : 1; 5213 uint64_t c1_up_wf : 1; 5214 uint64_t c0_exc : 1; 5215 uint64_t c1_exc : 1; 5216 uint64_t c0_ldwn : 1; 5217 uint64_t c1_ldwn : 1; 5218 uint64_t reserved_61_62 : 2; 5219 uint64_t mio_inta : 1; 5220#endif 5221 } cn56xxp1; 5222}; 5223typedef union cvmx_npei_int_sum cvmx_npei_int_sum_t; 5224 5225/** 5226 * cvmx_npei_int_sum2 5227 * 5228 * NPEI_INTERRUPT_SUM2 = NPI Interrupt Summary2 Register 5229 * 5230 * This is a read only copy of the NPEI_INTERRUPT_SUM register with bit variances. 5231 */ 5232union cvmx_npei_int_sum2 5233{ 5234 uint64_t u64; 5235 struct cvmx_npei_int_sum2_s 5236 { 5237#if __BYTE_ORDER == __BIG_ENDIAN 5238 uint64_t mio_inta : 1; /**< Equal to the cooresponding bit if the 5239 NPEI_INT_SUM register. */ 5240 uint64_t reserved_62_62 : 1; 5241 uint64_t int_a : 1; /**< Set when a bit in the NPEI_INT_A_SUM register and 5242 the cooresponding bit in the NPEI_INT_A_ENB2 5243 register is set. */ 5244 uint64_t c1_ldwn : 1; /**< Equal to the cooresponding bit if the 5245 NPEI_INT_SUM register. */ 5246 uint64_t c0_ldwn : 1; /**< Equal to the cooresponding bit if the 5247 NPEI_INT_SUM register. */ 5248 uint64_t c1_exc : 1; /**< Equal to the cooresponding bit if the 5249 NPEI_INT_SUM register. */ 5250 uint64_t c0_exc : 1; /**< Equal to the cooresponding bit if the 5251 NPEI_INT_SUM register. */ 5252 uint64_t c1_up_wf : 1; /**< Equal to the cooresponding bit if the 5253 NPEI_INT_SUM register. */ 5254 uint64_t c0_up_wf : 1; /**< Equal to the cooresponding bit if the 5255 NPEI_INT_SUM register. */ 5256 uint64_t c1_un_wf : 1; /**< Equal to the cooresponding bit if the 5257 NPEI_INT_SUM register. */ 5258 uint64_t c0_un_wf : 1; /**< Equal to the cooresponding bit if the 5259 NPEI_INT_SUM register. */ 5260 uint64_t c1_un_bx : 1; /**< Equal to the cooresponding bit if the 5261 NPEI_INT_SUM register. */ 5262 uint64_t c1_un_wi : 1; /**< Equal to the cooresponding bit if the 5263 NPEI_INT_SUM register. */ 5264 uint64_t c1_un_b2 : 1; /**< Equal to the cooresponding bit if the 5265 NPEI_INT_SUM register. */ 5266 uint64_t c1_un_b1 : 1; /**< Equal to the cooresponding bit if the 5267 NPEI_INT_SUM register. */ 5268 uint64_t c1_un_b0 : 1; /**< Equal to the cooresponding bit if the 5269 NPEI_INT_SUM register. */ 5270 uint64_t c1_up_bx : 1; /**< Equal to the cooresponding bit if the 5271 NPEI_INT_SUM register. */ 5272 uint64_t c1_up_wi : 1; /**< Equal to the cooresponding bit if the 5273 NPEI_INT_SUM register. */ 5274 uint64_t c1_up_b2 : 1; /**< Equal to the cooresponding bit if the 5275 NPEI_INT_SUM register. */ 5276 uint64_t c1_up_b1 : 1; /**< Equal to the cooresponding bit if the 5277 NPEI_INT_SUM register. */ 5278 uint64_t c1_up_b0 : 1; /**< Equal to the cooresponding bit if the 5279 NPEI_INT_SUM register. */ 5280 uint64_t c0_un_bx : 1; /**< Equal to the cooresponding bit if the 5281 NPEI_INT_SUM register. */ 5282 uint64_t c0_un_wi : 1; /**< Equal to the cooresponding bit if the 5283 NPEI_INT_SUM register. */ 5284 uint64_t c0_un_b2 : 1; /**< Equal to the cooresponding bit if the 5285 NPEI_INT_SUM register. */ 5286 uint64_t c0_un_b1 : 1; /**< Equal to the cooresponding bit if the 5287 NPEI_INT_SUM register. */ 5288 uint64_t c0_un_b0 : 1; /**< Equal to the cooresponding bit if the 5289 NPEI_INT_SUM register. */ 5290 uint64_t c0_up_bx : 1; /**< Equal to the cooresponding bit if the 5291 NPEI_INT_SUM register. */ 5292 uint64_t c0_up_wi : 1; /**< Equal to the cooresponding bit if the 5293 NPEI_INT_SUM register. */ 5294 uint64_t c0_up_b2 : 1; /**< Equal to the cooresponding bit if the 5295 NPEI_INT_SUM register. */ 5296 uint64_t c0_up_b1 : 1; /**< Equal to the cooresponding bit if the 5297 NPEI_INT_SUM register. */ 5298 uint64_t c0_up_b0 : 1; /**< Equal to the cooresponding bit if the 5299 NPEI_INT_SUM register. */ 5300 uint64_t c1_hpint : 1; /**< Equal to the cooresponding bit if the 5301 NPEI_INT_SUM register. */ 5302 uint64_t c1_pmei : 1; /**< Equal to the cooresponding bit if the 5303 NPEI_INT_SUM register. */ 5304 uint64_t c1_wake : 1; /**< Equal to the cooresponding bit if the 5305 NPEI_INT_SUM register. */ 5306 uint64_t crs1_dr : 1; /**< Equal to the cooresponding bit if the 5307 NPEI_INT_SUM register. */ 5308 uint64_t c1_se : 1; /**< Equal to the cooresponding bit if the 5309 NPEI_INT_SUM register. */ 5310 uint64_t crs1_er : 1; /**< Equal to the cooresponding bit if the 5311 NPEI_INT_SUM register. */ 5312 uint64_t c1_aeri : 1; /**< Equal to the cooresponding bit if the 5313 NPEI_INT_SUM register. */ 5314 uint64_t c0_hpint : 1; /**< Equal to the cooresponding bit if the 5315 NPEI_INT_SUM register. */ 5316 uint64_t c0_pmei : 1; /**< Equal to the cooresponding bit if the 5317 NPEI_INT_SUM register. */ 5318 uint64_t c0_wake : 1; /**< Equal to the cooresponding bit if the 5319 NPEI_INT_SUM register. */ 5320 uint64_t crs0_dr : 1; /**< Equal to the cooresponding bit if the 5321 NPEI_INT_SUM register. */ 5322 uint64_t c0_se : 1; /**< Equal to the cooresponding bit if the 5323 NPEI_INT_SUM register. */ 5324 uint64_t crs0_er : 1; /**< Equal to the cooresponding bit if the 5325 NPEI_INT_SUM register. */ 5326 uint64_t c0_aeri : 1; /**< Equal to the cooresponding bit if the 5327 NPEI_INT_SUM register. */ 5328 uint64_t reserved_15_18 : 4; 5329 uint64_t dtime1 : 1; /**< Equal to the cooresponding bit if the 5330 NPEI_INT_SUM register. */ 5331 uint64_t dtime0 : 1; /**< Equal to the cooresponding bit if the 5332 NPEI_INT_SUM register. */ 5333 uint64_t dcnt1 : 1; /**< Equal to the cooresponding bit if the 5334 NPEI_INT_SUM register. */ 5335 uint64_t dcnt0 : 1; /**< Equal to the cooresponding bit if the 5336 NPEI_INT_SUM register. */ 5337 uint64_t dma1fi : 1; /**< Equal to the cooresponding bit if the 5338 NPEI_INT_SUM register. */ 5339 uint64_t dma0fi : 1; /**< Equal to the cooresponding bit if the 5340 NPEI_INT_SUM register. */ 5341 uint64_t reserved_8_8 : 1; 5342 uint64_t dma3dbo : 1; /**< Equal to the cooresponding bit if the 5343 NPEI_INT_SUM register. */ 5344 uint64_t dma2dbo : 1; /**< Equal to the cooresponding bit if the 5345 NPEI_INT_SUM register. */ 5346 uint64_t dma1dbo : 1; /**< Equal to the cooresponding bit if the 5347 NPEI_INT_SUM register. */ 5348 uint64_t dma0dbo : 1; /**< Equal to the cooresponding bit if the 5349 NPEI_INT_SUM register. */ 5350 uint64_t iob2big : 1; /**< Equal to the cooresponding bit if the 5351 NPEI_INT_SUM register. */ 5352 uint64_t bar0_to : 1; /**< Equal to the cooresponding bit if the 5353 NPEI_INT_SUM register. */ 5354 uint64_t rml_wto : 1; /**< Equal to the cooresponding bit if the 5355 NPEI_INT_SUM register. */ 5356 uint64_t rml_rto : 1; /**< Equal to the cooresponding bit if the 5357 NPEI_INT_SUM register. */ 5358#else 5359 uint64_t rml_rto : 1; 5360 uint64_t rml_wto : 1; 5361 uint64_t bar0_to : 1; 5362 uint64_t iob2big : 1; 5363 uint64_t dma0dbo : 1; 5364 uint64_t dma1dbo : 1; 5365 uint64_t dma2dbo : 1; 5366 uint64_t dma3dbo : 1; 5367 uint64_t reserved_8_8 : 1; 5368 uint64_t dma0fi : 1; 5369 uint64_t dma1fi : 1; 5370 uint64_t dcnt0 : 1; 5371 uint64_t dcnt1 : 1; 5372 uint64_t dtime0 : 1; 5373 uint64_t dtime1 : 1; 5374 uint64_t reserved_15_18 : 4; 5375 uint64_t c0_aeri : 1; 5376 uint64_t crs0_er : 1; 5377 uint64_t c0_se : 1; 5378 uint64_t crs0_dr : 1; 5379 uint64_t c0_wake : 1; 5380 uint64_t c0_pmei : 1; 5381 uint64_t c0_hpint : 1; 5382 uint64_t c1_aeri : 1; 5383 uint64_t crs1_er : 1; 5384 uint64_t c1_se : 1; 5385 uint64_t crs1_dr : 1; 5386 uint64_t c1_wake : 1; 5387 uint64_t c1_pmei : 1; 5388 uint64_t c1_hpint : 1; 5389 uint64_t c0_up_b0 : 1; 5390 uint64_t c0_up_b1 : 1; 5391 uint64_t c0_up_b2 : 1; 5392 uint64_t c0_up_wi : 1; 5393 uint64_t c0_up_bx : 1; 5394 uint64_t c0_un_b0 : 1; 5395 uint64_t c0_un_b1 : 1; 5396 uint64_t c0_un_b2 : 1; 5397 uint64_t c0_un_wi : 1; 5398 uint64_t c0_un_bx : 1; 5399 uint64_t c1_up_b0 : 1; 5400 uint64_t c1_up_b1 : 1; 5401 uint64_t c1_up_b2 : 1; 5402 uint64_t c1_up_wi : 1; 5403 uint64_t c1_up_bx : 1; 5404 uint64_t c1_un_b0 : 1; 5405 uint64_t c1_un_b1 : 1; 5406 uint64_t c1_un_b2 : 1; 5407 uint64_t c1_un_wi : 1; 5408 uint64_t c1_un_bx : 1; 5409 uint64_t c0_un_wf : 1; 5410 uint64_t c1_un_wf : 1; 5411 uint64_t c0_up_wf : 1; 5412 uint64_t c1_up_wf : 1; 5413 uint64_t c0_exc : 1; 5414 uint64_t c1_exc : 1; 5415 uint64_t c0_ldwn : 1; 5416 uint64_t c1_ldwn : 1; 5417 uint64_t int_a : 1; 5418 uint64_t reserved_62_62 : 1; 5419 uint64_t mio_inta : 1; 5420#endif 5421 } s; 5422 struct cvmx_npei_int_sum2_s cn52xx; 5423 struct cvmx_npei_int_sum2_s cn52xxp1; 5424 struct cvmx_npei_int_sum2_s cn56xx; 5425}; 5426typedef union cvmx_npei_int_sum2 cvmx_npei_int_sum2_t; 5427 5428/** 5429 * cvmx_npei_last_win_rdata0 5430 * 5431 * NPEI_LAST_WIN_RDATA0 = NPEI Last Window Read Data Port0 5432 * 5433 * The data from the last initiated window read. 5434 */ 5435union cvmx_npei_last_win_rdata0 5436{ 5437 uint64_t u64; 5438 struct cvmx_npei_last_win_rdata0_s 5439 { 5440#if __BYTE_ORDER == __BIG_ENDIAN 5441 uint64_t data : 64; /**< Last window read data. */ 5442#else 5443 uint64_t data : 64; 5444#endif 5445 } s; 5446 struct cvmx_npei_last_win_rdata0_s cn52xx; 5447 struct cvmx_npei_last_win_rdata0_s cn52xxp1; 5448 struct cvmx_npei_last_win_rdata0_s cn56xx; 5449 struct cvmx_npei_last_win_rdata0_s cn56xxp1; 5450}; 5451typedef union cvmx_npei_last_win_rdata0 cvmx_npei_last_win_rdata0_t; 5452 5453/** 5454 * cvmx_npei_last_win_rdata1 5455 * 5456 * NPEI_LAST_WIN_RDATA1 = NPEI Last Window Read Data Port1 5457 * 5458 * The data from the last initiated window read. 5459 */ 5460union cvmx_npei_last_win_rdata1 5461{ 5462 uint64_t u64; 5463 struct cvmx_npei_last_win_rdata1_s 5464 { 5465#if __BYTE_ORDER == __BIG_ENDIAN 5466 uint64_t data : 64; /**< Last window read data. */ 5467#else 5468 uint64_t data : 64; 5469#endif 5470 } s; 5471 struct cvmx_npei_last_win_rdata1_s cn52xx; 5472 struct cvmx_npei_last_win_rdata1_s cn52xxp1; 5473 struct cvmx_npei_last_win_rdata1_s cn56xx; 5474 struct cvmx_npei_last_win_rdata1_s cn56xxp1; 5475}; 5476typedef union cvmx_npei_last_win_rdata1 cvmx_npei_last_win_rdata1_t; 5477 5478/** 5479 * cvmx_npei_mem_access_ctl 5480 * 5481 * NPEI_MEM_ACCESS_CTL = NPEI's Memory Access Control 5482 * 5483 * Contains control for access to the PCIe address space. 5484 */ 5485union cvmx_npei_mem_access_ctl 5486{ 5487 uint64_t u64; 5488 struct cvmx_npei_mem_access_ctl_s 5489 { 5490#if __BYTE_ORDER == __BIG_ENDIAN 5491 uint64_t reserved_14_63 : 50; 5492 uint64_t max_word : 4; /**< The maximum number of words to merge into a single 5493 write operation from the PPs to the PCIe. Legal 5494 values are 1 to 16, where a '0' is treated as 16. */ 5495 uint64_t timer : 10; /**< When the NPEI starts a PP to PCIe write it waits 5496 no longer than the value of TIMER in eclks to 5497 merge additional writes from the PPs into 1 5498 large write. The values for this field is 1 to 5499 1024 where a value of '0' is treated as 1024. */ 5500#else 5501 uint64_t timer : 10; 5502 uint64_t max_word : 4; 5503 uint64_t reserved_14_63 : 50; 5504#endif 5505 } s; 5506 struct cvmx_npei_mem_access_ctl_s cn52xx; 5507 struct cvmx_npei_mem_access_ctl_s cn52xxp1; 5508 struct cvmx_npei_mem_access_ctl_s cn56xx; 5509 struct cvmx_npei_mem_access_ctl_s cn56xxp1; 5510}; 5511typedef union cvmx_npei_mem_access_ctl cvmx_npei_mem_access_ctl_t; 5512 5513/** 5514 * cvmx_npei_mem_access_subid# 5515 * 5516 * NPEI_MEM_ACCESS_SUBIDX = NPEI Memory Access SubidX Register 5517 * 5518 * Contains address index and control bits for access to memory from Core PPs. 5519 */ 5520union cvmx_npei_mem_access_subidx 5521{ 5522 uint64_t u64; 5523 struct cvmx_npei_mem_access_subidx_s 5524 { 5525#if __BYTE_ORDER == __BIG_ENDIAN 5526 uint64_t reserved_42_63 : 22; 5527 uint64_t zero : 1; /**< Causes all byte reads to be zero length reads. 5528 Returns to the EXEC a zero for all read data. */ 5529 uint64_t port : 2; /**< Port the request is sent to. */ 5530 uint64_t nmerge : 1; /**< No merging is allowed in this window. */ 5531 uint64_t esr : 2; /**< Endian-swap for Reads. */ 5532 uint64_t esw : 2; /**< Endian-swap for Writes. */ 5533 uint64_t nsr : 1; /**< No Snoop for Reads. */ 5534 uint64_t nsw : 1; /**< No Snoop for Writes. */ 5535 uint64_t ror : 1; /**< Relaxed Ordering for Reads. */ 5536 uint64_t row : 1; /**< Relaxed Ordering for Writes. */ 5537 uint64_t ba : 30; /**< PCIe Adddress Bits <63:34>. */ 5538#else 5539 uint64_t ba : 30; 5540 uint64_t row : 1; 5541 uint64_t ror : 1; 5542 uint64_t nsw : 1; 5543 uint64_t nsr : 1; 5544 uint64_t esw : 2; 5545 uint64_t esr : 2; 5546 uint64_t nmerge : 1; 5547 uint64_t port : 2; 5548 uint64_t zero : 1; 5549 uint64_t reserved_42_63 : 22; 5550#endif 5551 } s; 5552 struct cvmx_npei_mem_access_subidx_s cn52xx; 5553 struct cvmx_npei_mem_access_subidx_s cn52xxp1; 5554 struct cvmx_npei_mem_access_subidx_s cn56xx; 5555 struct cvmx_npei_mem_access_subidx_s cn56xxp1; 5556}; 5557typedef union cvmx_npei_mem_access_subidx cvmx_npei_mem_access_subidx_t; 5558 5559/** 5560 * cvmx_npei_msi_enb0 5561 * 5562 * NPEI_MSI_ENB0 = NPEI MSI Enable0 5563 * 5564 * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV0. 5565 */ 5566union cvmx_npei_msi_enb0 5567{ 5568 uint64_t u64; 5569 struct cvmx_npei_msi_enb0_s 5570 { 5571#if __BYTE_ORDER == __BIG_ENDIAN 5572 uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV0. */ 5573#else 5574 uint64_t enb : 64; 5575#endif 5576 } s; 5577 struct cvmx_npei_msi_enb0_s cn52xx; 5578 struct cvmx_npei_msi_enb0_s cn52xxp1; 5579 struct cvmx_npei_msi_enb0_s cn56xx; 5580 struct cvmx_npei_msi_enb0_s cn56xxp1; 5581}; 5582typedef union cvmx_npei_msi_enb0 cvmx_npei_msi_enb0_t; 5583 5584/** 5585 * cvmx_npei_msi_enb1 5586 * 5587 * NPEI_MSI_ENB1 = NPEI MSI Enable1 5588 * 5589 * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV1. 5590 */ 5591union cvmx_npei_msi_enb1 5592{ 5593 uint64_t u64; 5594 struct cvmx_npei_msi_enb1_s 5595 { 5596#if __BYTE_ORDER == __BIG_ENDIAN 5597 uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV1. */ 5598#else 5599 uint64_t enb : 64; 5600#endif 5601 } s; 5602 struct cvmx_npei_msi_enb1_s cn52xx; 5603 struct cvmx_npei_msi_enb1_s cn52xxp1; 5604 struct cvmx_npei_msi_enb1_s cn56xx; 5605 struct cvmx_npei_msi_enb1_s cn56xxp1; 5606}; 5607typedef union cvmx_npei_msi_enb1 cvmx_npei_msi_enb1_t; 5608 5609/** 5610 * cvmx_npei_msi_enb2 5611 * 5612 * NPEI_MSI_ENB2 = NPEI MSI Enable2 5613 * 5614 * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV2. 5615 */ 5616union cvmx_npei_msi_enb2 5617{ 5618 uint64_t u64; 5619 struct cvmx_npei_msi_enb2_s 5620 { 5621#if __BYTE_ORDER == __BIG_ENDIAN 5622 uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV2. */ 5623#else 5624 uint64_t enb : 64; 5625#endif 5626 } s; 5627 struct cvmx_npei_msi_enb2_s cn52xx; 5628 struct cvmx_npei_msi_enb2_s cn52xxp1; 5629 struct cvmx_npei_msi_enb2_s cn56xx; 5630 struct cvmx_npei_msi_enb2_s cn56xxp1; 5631}; 5632typedef union cvmx_npei_msi_enb2 cvmx_npei_msi_enb2_t; 5633 5634/** 5635 * cvmx_npei_msi_enb3 5636 * 5637 * NPEI_MSI_ENB3 = NPEI MSI Enable3 5638 * 5639 * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV3. 5640 */ 5641union cvmx_npei_msi_enb3 5642{ 5643 uint64_t u64; 5644 struct cvmx_npei_msi_enb3_s 5645 { 5646#if __BYTE_ORDER == __BIG_ENDIAN 5647 uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV3. */ 5648#else 5649 uint64_t enb : 64; 5650#endif 5651 } s; 5652 struct cvmx_npei_msi_enb3_s cn52xx; 5653 struct cvmx_npei_msi_enb3_s cn52xxp1; 5654 struct cvmx_npei_msi_enb3_s cn56xx; 5655 struct cvmx_npei_msi_enb3_s cn56xxp1; 5656}; 5657typedef union cvmx_npei_msi_enb3 cvmx_npei_msi_enb3_t; 5658 5659/** 5660 * cvmx_npei_msi_rcv0 5661 * 5662 * NPEI_MSI_RCV0 = NPEI MSI Receive0 5663 * 5664 * Contains bits [63:0] of the 256 bits oof MSI interrupts. 5665 */ 5666union cvmx_npei_msi_rcv0 5667{ 5668 uint64_t u64; 5669 struct cvmx_npei_msi_rcv0_s 5670 { 5671#if __BYTE_ORDER == __BIG_ENDIAN 5672 uint64_t intr : 64; /**< Bits 63-0 of the 256 bits of MSI interrupt. */ 5673#else 5674 uint64_t intr : 64; 5675#endif 5676 } s; 5677 struct cvmx_npei_msi_rcv0_s cn52xx; 5678 struct cvmx_npei_msi_rcv0_s cn52xxp1; 5679 struct cvmx_npei_msi_rcv0_s cn56xx; 5680 struct cvmx_npei_msi_rcv0_s cn56xxp1; 5681}; 5682typedef union cvmx_npei_msi_rcv0 cvmx_npei_msi_rcv0_t; 5683 5684/** 5685 * cvmx_npei_msi_rcv1 5686 * 5687 * NPEI_MSI_RCV1 = NPEI MSI Receive1 5688 * 5689 * Contains bits [127:64] of the 256 bits oof MSI interrupts. 5690 */ 5691union cvmx_npei_msi_rcv1 5692{ 5693 uint64_t u64; 5694 struct cvmx_npei_msi_rcv1_s 5695 { 5696#if __BYTE_ORDER == __BIG_ENDIAN 5697 uint64_t intr : 64; /**< Bits 127-64 of the 256 bits of MSI interrupt. */ 5698#else 5699 uint64_t intr : 64; 5700#endif 5701 } s; 5702 struct cvmx_npei_msi_rcv1_s cn52xx; 5703 struct cvmx_npei_msi_rcv1_s cn52xxp1; 5704 struct cvmx_npei_msi_rcv1_s cn56xx; 5705 struct cvmx_npei_msi_rcv1_s cn56xxp1; 5706}; 5707typedef union cvmx_npei_msi_rcv1 cvmx_npei_msi_rcv1_t; 5708 5709/** 5710 * cvmx_npei_msi_rcv2 5711 * 5712 * NPEI_MSI_RCV2 = NPEI MSI Receive2 5713 * 5714 * Contains bits [191:128] of the 256 bits oof MSI interrupts. 5715 */ 5716union cvmx_npei_msi_rcv2 5717{ 5718 uint64_t u64; 5719 struct cvmx_npei_msi_rcv2_s 5720 { 5721#if __BYTE_ORDER == __BIG_ENDIAN 5722 uint64_t intr : 64; /**< Bits 191-128 of the 256 bits of MSI interrupt. */ 5723#else 5724 uint64_t intr : 64; 5725#endif 5726 } s; 5727 struct cvmx_npei_msi_rcv2_s cn52xx; 5728 struct cvmx_npei_msi_rcv2_s cn52xxp1; 5729 struct cvmx_npei_msi_rcv2_s cn56xx; 5730 struct cvmx_npei_msi_rcv2_s cn56xxp1; 5731}; 5732typedef union cvmx_npei_msi_rcv2 cvmx_npei_msi_rcv2_t; 5733 5734/** 5735 * cvmx_npei_msi_rcv3 5736 * 5737 * NPEI_MSI_RCV3 = NPEI MSI Receive3 5738 * 5739 * Contains bits [255:192] of the 256 bits oof MSI interrupts. 5740 */ 5741union cvmx_npei_msi_rcv3 5742{ 5743 uint64_t u64; 5744 struct cvmx_npei_msi_rcv3_s 5745 { 5746#if __BYTE_ORDER == __BIG_ENDIAN 5747 uint64_t intr : 64; /**< Bits 255-192 of the 256 bits of MSI interrupt. */ 5748#else 5749 uint64_t intr : 64; 5750#endif 5751 } s; 5752 struct cvmx_npei_msi_rcv3_s cn52xx; 5753 struct cvmx_npei_msi_rcv3_s cn52xxp1; 5754 struct cvmx_npei_msi_rcv3_s cn56xx; 5755 struct cvmx_npei_msi_rcv3_s cn56xxp1; 5756}; 5757typedef union cvmx_npei_msi_rcv3 cvmx_npei_msi_rcv3_t; 5758 5759/** 5760 * cvmx_npei_msi_rd_map 5761 * 5762 * NPEI_MSI_RD_MAP = NPEI MSI Read MAP 5763 * 5764 * Used to read the mapping function of the NPEI_PCIE_MSI_RCV to NPEI_MSI_RCV registers. 5765 */ 5766union cvmx_npei_msi_rd_map 5767{ 5768 uint64_t u64; 5769 struct cvmx_npei_msi_rd_map_s 5770 { 5771#if __BYTE_ORDER == __BIG_ENDIAN 5772 uint64_t reserved_16_63 : 48; 5773 uint64_t rd_int : 8; /**< The value of the map at the location PREVIOUSLY 5774 written to the MSI_INT field of this register. */ 5775 uint64_t msi_int : 8; /**< Selects the value that would be received when the 5776 NPEI_PCIE_MSI_RCV register is written. */ 5777#else 5778 uint64_t msi_int : 8; 5779 uint64_t rd_int : 8; 5780 uint64_t reserved_16_63 : 48; 5781#endif 5782 } s; 5783 struct cvmx_npei_msi_rd_map_s cn52xx; 5784 struct cvmx_npei_msi_rd_map_s cn52xxp1; 5785 struct cvmx_npei_msi_rd_map_s cn56xx; 5786 struct cvmx_npei_msi_rd_map_s cn56xxp1; 5787}; 5788typedef union cvmx_npei_msi_rd_map cvmx_npei_msi_rd_map_t; 5789 5790/** 5791 * cvmx_npei_msi_w1c_enb0 5792 * 5793 * NPEI_MSI_W1C_ENB0 = NPEI MSI Write 1 To Clear Enable0 5794 * 5795 * Used to clear bits in NPEI_MSI_ENB0. This is a PASS2 register. 5796 */ 5797union cvmx_npei_msi_w1c_enb0 5798{ 5799 uint64_t u64; 5800 struct cvmx_npei_msi_w1c_enb0_s 5801 { 5802#if __BYTE_ORDER == __BIG_ENDIAN 5803 uint64_t clr : 64; /**< A write of '1' to a vector will clear the 5804 cooresponding bit in NPEI_MSI_ENB0. 5805 A read to this address will return 0. */ 5806#else 5807 uint64_t clr : 64; 5808#endif 5809 } s; 5810 struct cvmx_npei_msi_w1c_enb0_s cn52xx; 5811 struct cvmx_npei_msi_w1c_enb0_s cn56xx; 5812}; 5813typedef union cvmx_npei_msi_w1c_enb0 cvmx_npei_msi_w1c_enb0_t; 5814 5815/** 5816 * cvmx_npei_msi_w1c_enb1 5817 * 5818 * NPEI_MSI_W1C_ENB1 = NPEI MSI Write 1 To Clear Enable1 5819 * 5820 * Used to clear bits in NPEI_MSI_ENB1. This is a PASS2 register. 5821 */ 5822union cvmx_npei_msi_w1c_enb1 5823{ 5824 uint64_t u64; 5825 struct cvmx_npei_msi_w1c_enb1_s 5826 { 5827#if __BYTE_ORDER == __BIG_ENDIAN 5828 uint64_t clr : 64; /**< A write of '1' to a vector will clear the 5829 cooresponding bit in NPEI_MSI_ENB1. 5830 A read to this address will return 0. */ 5831#else 5832 uint64_t clr : 64; 5833#endif 5834 } s; 5835 struct cvmx_npei_msi_w1c_enb1_s cn52xx; 5836 struct cvmx_npei_msi_w1c_enb1_s cn56xx; 5837}; 5838typedef union cvmx_npei_msi_w1c_enb1 cvmx_npei_msi_w1c_enb1_t; 5839 5840/** 5841 * cvmx_npei_msi_w1c_enb2 5842 * 5843 * NPEI_MSI_W1C_ENB2 = NPEI MSI Write 1 To Clear Enable2 5844 * 5845 * Used to clear bits in NPEI_MSI_ENB2. This is a PASS2 register. 5846 */ 5847union cvmx_npei_msi_w1c_enb2 5848{ 5849 uint64_t u64; 5850 struct cvmx_npei_msi_w1c_enb2_s 5851 { 5852#if __BYTE_ORDER == __BIG_ENDIAN 5853 uint64_t clr : 64; /**< A write of '1' to a vector will clear the 5854 cooresponding bit in NPEI_MSI_ENB2. 5855 A read to this address will return 0. */ 5856#else 5857 uint64_t clr : 64; 5858#endif 5859 } s; 5860 struct cvmx_npei_msi_w1c_enb2_s cn52xx; 5861 struct cvmx_npei_msi_w1c_enb2_s cn56xx; 5862}; 5863typedef union cvmx_npei_msi_w1c_enb2 cvmx_npei_msi_w1c_enb2_t; 5864 5865/** 5866 * cvmx_npei_msi_w1c_enb3 5867 * 5868 * NPEI_MSI_W1C_ENB3 = NPEI MSI Write 1 To Clear Enable3 5869 * 5870 * Used to clear bits in NPEI_MSI_ENB3. This is a PASS2 register. 5871 */ 5872union cvmx_npei_msi_w1c_enb3 5873{ 5874 uint64_t u64; 5875 struct cvmx_npei_msi_w1c_enb3_s 5876 { 5877#if __BYTE_ORDER == __BIG_ENDIAN 5878 uint64_t clr : 64; /**< A write of '1' to a vector will clear the 5879 cooresponding bit in NPEI_MSI_ENB3. 5880 A read to this address will return 0. */ 5881#else 5882 uint64_t clr : 64; 5883#endif 5884 } s; 5885 struct cvmx_npei_msi_w1c_enb3_s cn52xx; 5886 struct cvmx_npei_msi_w1c_enb3_s cn56xx; 5887}; 5888typedef union cvmx_npei_msi_w1c_enb3 cvmx_npei_msi_w1c_enb3_t; 5889 5890/** 5891 * cvmx_npei_msi_w1s_enb0 5892 * 5893 * NPEI_MSI_W1S_ENB0 = NPEI MSI Write 1 To Set Enable0 5894 * 5895 * Used to set bits in NPEI_MSI_ENB0. This is a PASS2 register. 5896 */ 5897union cvmx_npei_msi_w1s_enb0 5898{ 5899 uint64_t u64; 5900 struct cvmx_npei_msi_w1s_enb0_s 5901 { 5902#if __BYTE_ORDER == __BIG_ENDIAN 5903 uint64_t set : 64; /**< A write of '1' to a vector will set the 5904 cooresponding bit in NPEI_MSI_ENB0. 5905 A read to this address will return 0. */ 5906#else 5907 uint64_t set : 64; 5908#endif 5909 } s; 5910 struct cvmx_npei_msi_w1s_enb0_s cn52xx; 5911 struct cvmx_npei_msi_w1s_enb0_s cn56xx; 5912}; 5913typedef union cvmx_npei_msi_w1s_enb0 cvmx_npei_msi_w1s_enb0_t; 5914 5915/** 5916 * cvmx_npei_msi_w1s_enb1 5917 * 5918 * NPEI_MSI_W1S_ENB0 = NPEI MSI Write 1 To Set Enable1 5919 * 5920 * Used to set bits in NPEI_MSI_ENB1. This is a PASS2 register. 5921 */ 5922union cvmx_npei_msi_w1s_enb1 5923{ 5924 uint64_t u64; 5925 struct cvmx_npei_msi_w1s_enb1_s 5926 { 5927#if __BYTE_ORDER == __BIG_ENDIAN 5928 uint64_t set : 64; /**< A write of '1' to a vector will set the 5929 cooresponding bit in NPEI_MSI_ENB1. 5930 A read to this address will return 0. */ 5931#else 5932 uint64_t set : 64; 5933#endif 5934 } s; 5935 struct cvmx_npei_msi_w1s_enb1_s cn52xx; 5936 struct cvmx_npei_msi_w1s_enb1_s cn56xx; 5937}; 5938typedef union cvmx_npei_msi_w1s_enb1 cvmx_npei_msi_w1s_enb1_t; 5939 5940/** 5941 * cvmx_npei_msi_w1s_enb2 5942 * 5943 * NPEI_MSI_W1S_ENB2 = NPEI MSI Write 1 To Set Enable2 5944 * 5945 * Used to set bits in NPEI_MSI_ENB2. This is a PASS2 register. 5946 */ 5947union cvmx_npei_msi_w1s_enb2 5948{ 5949 uint64_t u64; 5950 struct cvmx_npei_msi_w1s_enb2_s 5951 { 5952#if __BYTE_ORDER == __BIG_ENDIAN 5953 uint64_t set : 64; /**< A write of '1' to a vector will set the 5954 cooresponding bit in NPEI_MSI_ENB2. 5955 A read to this address will return 0. */ 5956#else 5957 uint64_t set : 64; 5958#endif 5959 } s; 5960 struct cvmx_npei_msi_w1s_enb2_s cn52xx; 5961 struct cvmx_npei_msi_w1s_enb2_s cn56xx; 5962}; 5963typedef union cvmx_npei_msi_w1s_enb2 cvmx_npei_msi_w1s_enb2_t; 5964 5965/** 5966 * cvmx_npei_msi_w1s_enb3 5967 * 5968 * NPEI_MSI_W1S_ENB3 = NPEI MSI Write 1 To Set Enable3 5969 * 5970 * Used to set bits in NPEI_MSI_ENB3. This is a PASS2 register. 5971 */ 5972union cvmx_npei_msi_w1s_enb3 5973{ 5974 uint64_t u64; 5975 struct cvmx_npei_msi_w1s_enb3_s 5976 { 5977#if __BYTE_ORDER == __BIG_ENDIAN 5978 uint64_t set : 64; /**< A write of '1' to a vector will set the 5979 cooresponding bit in NPEI_MSI_ENB3. 5980 A read to this address will return 0. */ 5981#else 5982 uint64_t set : 64; 5983#endif 5984 } s; 5985 struct cvmx_npei_msi_w1s_enb3_s cn52xx; 5986 struct cvmx_npei_msi_w1s_enb3_s cn56xx; 5987}; 5988typedef union cvmx_npei_msi_w1s_enb3 cvmx_npei_msi_w1s_enb3_t; 5989 5990/** 5991 * cvmx_npei_msi_wr_map 5992 * 5993 * NPEI_MSI_WR_MAP = NPEI MSI Write MAP 5994 * 5995 * Used to write the mapping function of the NPEI_PCIE_MSI_RCV to NPEI_MSI_RCV registers. 5996 */ 5997union cvmx_npei_msi_wr_map 5998{ 5999 uint64_t u64; 6000 struct cvmx_npei_msi_wr_map_s 6001 { 6002#if __BYTE_ORDER == __BIG_ENDIAN 6003 uint64_t reserved_16_63 : 48; 6004 uint64_t ciu_int : 8; /**< Selects which bit in the NPEI_MSI_RCV# (0-255) 6005 will be set when the value specified in the 6006 MSI_INT of this register is recevied during a 6007 write to the NPEI_PCIE_MSI_RCV register. */ 6008 uint64_t msi_int : 8; /**< Selects the value that would be received when the 6009 NPEI_PCIE_MSI_RCV register is written. */ 6010#else 6011 uint64_t msi_int : 8; 6012 uint64_t ciu_int : 8; 6013 uint64_t reserved_16_63 : 48; 6014#endif 6015 } s; 6016 struct cvmx_npei_msi_wr_map_s cn52xx; 6017 struct cvmx_npei_msi_wr_map_s cn52xxp1; 6018 struct cvmx_npei_msi_wr_map_s cn56xx; 6019 struct cvmx_npei_msi_wr_map_s cn56xxp1; 6020}; 6021typedef union cvmx_npei_msi_wr_map cvmx_npei_msi_wr_map_t; 6022 6023/** 6024 * cvmx_npei_pcie_credit_cnt 6025 * 6026 * NPEI_PCIE_CREDIT_CNT = NPEI PCIE Credit Count 6027 * 6028 * Contains the number of credits for the pcie port FIFOs used by the NPEI. This value needs to be set BEFORE PCIe traffic 6029 * flow from NPEI to PCIE Ports starts. A write to this register will cause the credit counts in the NPEI for the two 6030 * PCIE ports to be reset to the value in this register. 6031 */ 6032union cvmx_npei_pcie_credit_cnt 6033{ 6034 uint64_t u64; 6035 struct cvmx_npei_pcie_credit_cnt_s 6036 { 6037#if __BYTE_ORDER == __BIG_ENDIAN 6038 uint64_t reserved_48_63 : 16; 6039 uint64_t p1_ccnt : 8; /**< Port1 C-TLP FIFO Credits. 6040 Legal values are 0x25 to 0x80. */ 6041 uint64_t p1_ncnt : 8; /**< Port1 N-TLP FIFO Credits. 6042 Legal values are 0x5 to 0x10. */ 6043 uint64_t p1_pcnt : 8; /**< Port1 P-TLP FIFO Credits. 6044 Legal values are 0x25 to 0x80. */ 6045 uint64_t p0_ccnt : 8; /**< Port0 C-TLP FIFO Credits. 6046 Legal values are 0x25 to 0x80. */ 6047 uint64_t p0_ncnt : 8; /**< Port0 N-TLP FIFO Credits. 6048 Legal values are 0x5 to 0x10. */ 6049 uint64_t p0_pcnt : 8; /**< Port0 P-TLP FIFO Credits. 6050 Legal values are 0x25 to 0x80. */ 6051#else 6052 uint64_t p0_pcnt : 8; 6053 uint64_t p0_ncnt : 8; 6054 uint64_t p0_ccnt : 8; 6055 uint64_t p1_pcnt : 8; 6056 uint64_t p1_ncnt : 8; 6057 uint64_t p1_ccnt : 8; 6058 uint64_t reserved_48_63 : 16; 6059#endif 6060 } s; 6061 struct cvmx_npei_pcie_credit_cnt_s cn52xx; 6062 struct cvmx_npei_pcie_credit_cnt_s cn56xx; 6063}; 6064typedef union cvmx_npei_pcie_credit_cnt cvmx_npei_pcie_credit_cnt_t; 6065 6066/** 6067 * cvmx_npei_pcie_msi_rcv 6068 * 6069 * NPEI_PCIE_MSI_RCV = NPEI PCIe MSI Receive 6070 * 6071 * Register where MSI writes are directed from the PCIe. 6072 */ 6073union cvmx_npei_pcie_msi_rcv 6074{ 6075 uint64_t u64; 6076 struct cvmx_npei_pcie_msi_rcv_s 6077 { 6078#if __BYTE_ORDER == __BIG_ENDIAN 6079 uint64_t reserved_8_63 : 56; 6080 uint64_t intr : 8; /**< A write to this register will result in a bit in 6081 one of the NPEI_MSI_RCV# registers being set. 6082 Which bit is set is dependent on the previously 6083 written using the NPEI_MSI_WR_MAP register or if 6084 not previously written the reset value of the MAP. */ 6085#else 6086 uint64_t intr : 8; 6087 uint64_t reserved_8_63 : 56; 6088#endif 6089 } s; 6090 struct cvmx_npei_pcie_msi_rcv_s cn52xx; 6091 struct cvmx_npei_pcie_msi_rcv_s cn52xxp1; 6092 struct cvmx_npei_pcie_msi_rcv_s cn56xx; 6093 struct cvmx_npei_pcie_msi_rcv_s cn56xxp1; 6094}; 6095typedef union cvmx_npei_pcie_msi_rcv cvmx_npei_pcie_msi_rcv_t; 6096 6097/** 6098 * cvmx_npei_pcie_msi_rcv_b1 6099 * 6100 * NPEI_PCIE_MSI_RCV_B1 = NPEI PCIe MSI Receive Byte 1 6101 * 6102 * Register where MSI writes are directed from the PCIe. 6103 */ 6104union cvmx_npei_pcie_msi_rcv_b1 6105{ 6106 uint64_t u64; 6107 struct cvmx_npei_pcie_msi_rcv_b1_s 6108 { 6109#if __BYTE_ORDER == __BIG_ENDIAN 6110 uint64_t reserved_16_63 : 48; 6111 uint64_t intr : 8; /**< A write to this register will result in a bit in 6112 one of the NPEI_MSI_RCV# registers being set. 6113 Which bit is set is dependent on the previously 6114 written using the NPEI_MSI_WR_MAP register or if 6115 not previously written the reset value of the MAP. */ 6116 uint64_t reserved_0_7 : 8; 6117#else 6118 uint64_t reserved_0_7 : 8; 6119 uint64_t intr : 8; 6120 uint64_t reserved_16_63 : 48; 6121#endif 6122 } s; 6123 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx; 6124 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1; 6125 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx; 6126 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1; 6127}; 6128typedef union cvmx_npei_pcie_msi_rcv_b1 cvmx_npei_pcie_msi_rcv_b1_t; 6129 6130/** 6131 * cvmx_npei_pcie_msi_rcv_b2 6132 * 6133 * NPEI_PCIE_MSI_RCV_B2 = NPEI PCIe MSI Receive Byte 2 6134 * 6135 * Register where MSI writes are directed from the PCIe. 6136 */ 6137union cvmx_npei_pcie_msi_rcv_b2 6138{ 6139 uint64_t u64; 6140 struct cvmx_npei_pcie_msi_rcv_b2_s 6141 { 6142#if __BYTE_ORDER == __BIG_ENDIAN 6143 uint64_t reserved_24_63 : 40; 6144 uint64_t intr : 8; /**< A write to this register will result in a bit in 6145 one of the NPEI_MSI_RCV# registers being set. 6146 Which bit is set is dependent on the previously 6147 written using the NPEI_MSI_WR_MAP register or if 6148 not previously written the reset value of the MAP. */ 6149 uint64_t reserved_0_15 : 16; 6150#else 6151 uint64_t reserved_0_15 : 16; 6152 uint64_t intr : 8; 6153 uint64_t reserved_24_63 : 40; 6154#endif 6155 } s; 6156 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx; 6157 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1; 6158 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx; 6159 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1; 6160}; 6161typedef union cvmx_npei_pcie_msi_rcv_b2 cvmx_npei_pcie_msi_rcv_b2_t; 6162 6163/** 6164 * cvmx_npei_pcie_msi_rcv_b3 6165 * 6166 * NPEI_PCIE_MSI_RCV_B3 = NPEI PCIe MSI Receive Byte 3 6167 * 6168 * Register where MSI writes are directed from the PCIe. 6169 */ 6170union cvmx_npei_pcie_msi_rcv_b3 6171{ 6172 uint64_t u64; 6173 struct cvmx_npei_pcie_msi_rcv_b3_s 6174 { 6175#if __BYTE_ORDER == __BIG_ENDIAN 6176 uint64_t reserved_32_63 : 32; 6177 uint64_t intr : 8; /**< A write to this register will result in a bit in 6178 one of the NPEI_MSI_RCV# registers being set. 6179 Which bit is set is dependent on the previously 6180 written using the NPEI_MSI_WR_MAP register or if 6181 not previously written the reset value of the MAP. */ 6182 uint64_t reserved_0_23 : 24; 6183#else 6184 uint64_t reserved_0_23 : 24; 6185 uint64_t intr : 8; 6186 uint64_t reserved_32_63 : 32; 6187#endif 6188 } s; 6189 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx; 6190 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1; 6191 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx; 6192 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1; 6193}; 6194typedef union cvmx_npei_pcie_msi_rcv_b3 cvmx_npei_pcie_msi_rcv_b3_t; 6195 6196/** 6197 * cvmx_npei_pkt#_cnts 6198 * 6199 * NPEI_PKT[0..31]_CNTS = NPEI Packet ring# Counts 6200 * 6201 * The counters for output rings. 6202 */ 6203union cvmx_npei_pktx_cnts 6204{ 6205 uint64_t u64; 6206 struct cvmx_npei_pktx_cnts_s 6207 { 6208#if __BYTE_ORDER == __BIG_ENDIAN 6209 uint64_t reserved_54_63 : 10; 6210 uint64_t timer : 22; /**< Timer incremented every 1024 core clocks 6211 when NPEI_PKTS#_CNTS[CNT] is non zero. Field 6212 cleared when NPEI_PKTS#_CNTS[CNT] goes to 0. 6213 Field is also cleared when NPEI_PKT_TIME_INT is 6214 cleared. 6215 The first increment of this count can occur 6216 between 0 to 1023 core clocks. */ 6217 uint64_t cnt : 32; /**< ring counter. This field is incremented as 6218 packets are sent out and decremented in response to 6219 writes to this field. 6220 When NPEI_PKT_OUT_BMODE is '0' a value of 1 is 6221 added to the register for each packet, when '1' 6222 and the info-pointer is NOT used the length of the 6223 packet plus 8 is added, when '1' and info-pointer 6224 mode IS used the packet length is added to this 6225 field. */ 6226#else 6227 uint64_t cnt : 32; 6228 uint64_t timer : 22; 6229 uint64_t reserved_54_63 : 10; 6230#endif 6231 } s; 6232 struct cvmx_npei_pktx_cnts_s cn52xx; 6233 struct cvmx_npei_pktx_cnts_s cn56xx; 6234}; 6235typedef union cvmx_npei_pktx_cnts cvmx_npei_pktx_cnts_t; 6236 6237/** 6238 * cvmx_npei_pkt#_in_bp 6239 * 6240 * NPEI_PKT[0..31]_IN_BP = NPEI Packet ring# Input Backpressure 6241 * 6242 * The counters and thresholds for input packets to apply backpressure to processing of the packets. 6243 */ 6244union cvmx_npei_pktx_in_bp 6245{ 6246 uint64_t u64; 6247 struct cvmx_npei_pktx_in_bp_s 6248 { 6249#if __BYTE_ORDER == __BIG_ENDIAN 6250 uint64_t wmark : 32; /**< When CNT is greater than this threshold no more 6251 packets will be processed for this ring. 6252 When writing this field of the NPEI_PKT#_IN_BP 6253 register, use a 4-byte write so as to not write 6254 any other field of this register. */ 6255 uint64_t cnt : 32; /**< ring counter. This field is incremented by one 6256 whenever OCTEON receives, buffers, and creates a 6257 work queue entry for a packet that arrives by the 6258 cooresponding input ring. A write to this field 6259 will be subtracted from the field value. 6260 When writing this field of the NPEI_PKT#_IN_BP 6261 register, use a 4-byte write so as to not write 6262 any other field of this register. */ 6263#else 6264 uint64_t cnt : 32; 6265 uint64_t wmark : 32; 6266#endif 6267 } s; 6268 struct cvmx_npei_pktx_in_bp_s cn52xx; 6269 struct cvmx_npei_pktx_in_bp_s cn56xx; 6270}; 6271typedef union cvmx_npei_pktx_in_bp cvmx_npei_pktx_in_bp_t; 6272 6273/** 6274 * cvmx_npei_pkt#_instr_baddr 6275 * 6276 * NPEI_PKT[0..31]_INSTR_BADDR = NPEI Packet ring# Instruction Base Address 6277 * 6278 * Start of Instruction for input packets. 6279 */ 6280union cvmx_npei_pktx_instr_baddr 6281{ 6282 uint64_t u64; 6283 struct cvmx_npei_pktx_instr_baddr_s 6284 { 6285#if __BYTE_ORDER == __BIG_ENDIAN 6286 uint64_t addr : 61; /**< Base address for Instructions. */ 6287 uint64_t reserved_0_2 : 3; 6288#else 6289 uint64_t reserved_0_2 : 3; 6290 uint64_t addr : 61; 6291#endif 6292 } s; 6293 struct cvmx_npei_pktx_instr_baddr_s cn52xx; 6294 struct cvmx_npei_pktx_instr_baddr_s cn56xx; 6295}; 6296typedef union cvmx_npei_pktx_instr_baddr cvmx_npei_pktx_instr_baddr_t; 6297 6298/** 6299 * cvmx_npei_pkt#_instr_baoff_dbell 6300 * 6301 * NPEI_PKT[0..31]_INSTR_BAOFF_DBELL = NPEI Packet ring# Instruction Base Address Offset and Doorbell 6302 * 6303 * The doorbell and base address offset for next read. 6304 */ 6305union cvmx_npei_pktx_instr_baoff_dbell 6306{ 6307 uint64_t u64; 6308 struct cvmx_npei_pktx_instr_baoff_dbell_s 6309 { 6310#if __BYTE_ORDER == __BIG_ENDIAN 6311 uint64_t aoff : 32; /**< The offset from the NPEI_PKT[0..31]_INSTR_BADDR 6312 where the next instruction will be read. */ 6313 uint64_t dbell : 32; /**< Instruction doorbell count. Writes to this field 6314 will increment the value here. Reads will return 6315 present value. A write of 0xffffffff will set the 6316 DBELL and AOFF fields to '0'. */ 6317#else 6318 uint64_t dbell : 32; 6319 uint64_t aoff : 32; 6320#endif 6321 } s; 6322 struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx; 6323 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx; 6324}; 6325typedef union cvmx_npei_pktx_instr_baoff_dbell cvmx_npei_pktx_instr_baoff_dbell_t; 6326 6327/** 6328 * cvmx_npei_pkt#_instr_fifo_rsize 6329 * 6330 * NPEI_PKT[0..31]_INSTR_FIFO_RSIZE = NPEI Packet ring# Instruction FIFO and Ring Size. 6331 * 6332 * Fifo field and ring size for Instructions. 6333 */ 6334union cvmx_npei_pktx_instr_fifo_rsize 6335{ 6336 uint64_t u64; 6337 struct cvmx_npei_pktx_instr_fifo_rsize_s 6338 { 6339#if __BYTE_ORDER == __BIG_ENDIAN 6340 uint64_t max : 9; /**< Max Fifo Size. */ 6341 uint64_t rrp : 9; /**< Fifo read pointer. */ 6342 uint64_t wrp : 9; /**< Fifo write pointer. */ 6343 uint64_t fcnt : 5; /**< Fifo count. */ 6344 uint64_t rsize : 32; /**< Instruction ring size. */ 6345#else 6346 uint64_t rsize : 32; 6347 uint64_t fcnt : 5; 6348 uint64_t wrp : 9; 6349 uint64_t rrp : 9; 6350 uint64_t max : 9; 6351#endif 6352 } s; 6353 struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx; 6354 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx; 6355}; 6356typedef union cvmx_npei_pktx_instr_fifo_rsize cvmx_npei_pktx_instr_fifo_rsize_t; 6357 6358/** 6359 * cvmx_npei_pkt#_instr_header 6360 * 6361 * NPEI_PKT[0..31]_INSTR_HEADER = NPEI Packet ring# Instruction Header. 6362 * 6363 * VAlues used to build input packet header. 6364 */ 6365union cvmx_npei_pktx_instr_header 6366{ 6367 uint64_t u64; 6368 struct cvmx_npei_pktx_instr_header_s 6369 { 6370#if __BYTE_ORDER == __BIG_ENDIAN 6371 uint64_t reserved_44_63 : 20; 6372 uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */ 6373 uint64_t reserved_38_42 : 5; 6374 uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */ 6375 uint64_t reserved_35_35 : 1; 6376 uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */ 6377 uint64_t reserved_22_27 : 6; 6378 uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent 6379 as part of the packet data, regardless of the 6380 value of bit [63] of the instruction header. 6381 USE_IHDR must be set whenever PBP is set. */ 6382 uint64_t reserved_16_20 : 5; 6383 uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet 6384 is not raw and PBP is not set. */ 6385 uint64_t reserved_13_13 : 1; 6386 uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet 6387 is not raw and PBP is not set. */ 6388 uint64_t reserved_0_5 : 6; 6389#else 6390 uint64_t reserved_0_5 : 6; 6391 uint64_t skp_len : 7; 6392 uint64_t reserved_13_13 : 1; 6393 uint64_t par_mode : 2; 6394 uint64_t reserved_16_20 : 5; 6395 uint64_t use_ihdr : 1; 6396 uint64_t reserved_22_27 : 6; 6397 uint64_t rskp_len : 7; 6398 uint64_t reserved_35_35 : 1; 6399 uint64_t rparmode : 2; 6400 uint64_t reserved_38_42 : 5; 6401 uint64_t pbp : 1; 6402 uint64_t reserved_44_63 : 20; 6403#endif 6404 } s; 6405 struct cvmx_npei_pktx_instr_header_s cn52xx; 6406 struct cvmx_npei_pktx_instr_header_s cn56xx; 6407}; 6408typedef union cvmx_npei_pktx_instr_header cvmx_npei_pktx_instr_header_t; 6409 6410/** 6411 * cvmx_npei_pkt#_slist_baddr 6412 * 6413 * NPEI_PKT[0..31]_SLIST_BADDR = NPEI Packet ring# Scatter List Base Address 6414 * 6415 * Start of Scatter List for output packet pointers - MUST be 16 byte alligned 6416 */ 6417union cvmx_npei_pktx_slist_baddr 6418{ 6419 uint64_t u64; 6420 struct cvmx_npei_pktx_slist_baddr_s 6421 { 6422#if __BYTE_ORDER == __BIG_ENDIAN 6423 uint64_t addr : 60; /**< Base address for scatter list pointers. */ 6424 uint64_t reserved_0_3 : 4; 6425#else 6426 uint64_t reserved_0_3 : 4; 6427 uint64_t addr : 60; 6428#endif 6429 } s; 6430 struct cvmx_npei_pktx_slist_baddr_s cn52xx; 6431 struct cvmx_npei_pktx_slist_baddr_s cn56xx; 6432}; 6433typedef union cvmx_npei_pktx_slist_baddr cvmx_npei_pktx_slist_baddr_t; 6434 6435/** 6436 * cvmx_npei_pkt#_slist_baoff_dbell 6437 * 6438 * NPEI_PKT[0..31]_SLIST_BAOFF_DBELL = NPEI Packet ring# Scatter List Base Address Offset and Doorbell 6439 * 6440 * The doorbell and base address offset for next read. 6441 */ 6442union cvmx_npei_pktx_slist_baoff_dbell 6443{ 6444 uint64_t u64; 6445 struct cvmx_npei_pktx_slist_baoff_dbell_s 6446 { 6447#if __BYTE_ORDER == __BIG_ENDIAN 6448 uint64_t aoff : 32; /**< The offset from the NPEI_PKT[0..31]_SLIST_BADDR 6449 where the next SList pointer will be read. 6450 A write of 0xFFFFFFFF to the DBELL field will 6451 clear DBELL and AOFF */ 6452 uint64_t dbell : 32; /**< Scatter list doorbell count. Writes to this field 6453 will increment the value here. Reads will return 6454 present value. The value of this field is 6455 decremented as read operations are ISSUED for 6456 scatter pointers. 6457 A write of 0xFFFFFFFF will clear DBELL and AOFF */ 6458#else 6459 uint64_t dbell : 32; 6460 uint64_t aoff : 32; 6461#endif 6462 } s; 6463 struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx; 6464 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx; 6465}; 6466typedef union cvmx_npei_pktx_slist_baoff_dbell cvmx_npei_pktx_slist_baoff_dbell_t; 6467 6468/** 6469 * cvmx_npei_pkt#_slist_fifo_rsize 6470 * 6471 * NPEI_PKT[0..31]_SLIST_FIFO_RSIZE = NPEI Packet ring# Scatter List FIFO and Ring Size. 6472 * 6473 * The number of scatter pointer pairs in the scatter list. 6474 */ 6475union cvmx_npei_pktx_slist_fifo_rsize 6476{ 6477 uint64_t u64; 6478 struct cvmx_npei_pktx_slist_fifo_rsize_s 6479 { 6480#if __BYTE_ORDER == __BIG_ENDIAN 6481 uint64_t reserved_32_63 : 32; 6482 uint64_t rsize : 32; /**< The number of scatter pointer pairs contained in 6483 the scatter list ring. */ 6484#else 6485 uint64_t rsize : 32; 6486 uint64_t reserved_32_63 : 32; 6487#endif 6488 } s; 6489 struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx; 6490 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx; 6491}; 6492typedef union cvmx_npei_pktx_slist_fifo_rsize cvmx_npei_pktx_slist_fifo_rsize_t; 6493 6494/** 6495 * cvmx_npei_pkt_cnt_int 6496 * 6497 * NPEI_PKT_CNT_INT = NPI Packet Counter Interrupt 6498 * 6499 * The packets rings that are interrupting because of Packet Counters. 6500 */ 6501union cvmx_npei_pkt_cnt_int 6502{ 6503 uint64_t u64; 6504 struct cvmx_npei_pkt_cnt_int_s 6505 { 6506#if __BYTE_ORDER == __BIG_ENDIAN 6507 uint64_t reserved_32_63 : 32; 6508 uint64_t port : 32; /**< Bit vector cooresponding to ring number is set when 6509 NPEI_PKT#_CNTS[CNT] is greater 6510 than NPEI_PKT_INT_LEVELS[CNT]. */ 6511#else 6512 uint64_t port : 32; 6513 uint64_t reserved_32_63 : 32; 6514#endif 6515 } s; 6516 struct cvmx_npei_pkt_cnt_int_s cn52xx; 6517 struct cvmx_npei_pkt_cnt_int_s cn56xx; 6518}; 6519typedef union cvmx_npei_pkt_cnt_int cvmx_npei_pkt_cnt_int_t; 6520 6521/** 6522 * cvmx_npei_pkt_cnt_int_enb 6523 * 6524 * NPEI_PKT_CNT_INT_ENB = NPI Packet Counter Interrupt Enable 6525 * 6526 * Enable for the packets rings that are interrupting because of Packet Counters. 6527 */ 6528union cvmx_npei_pkt_cnt_int_enb 6529{ 6530 uint64_t u64; 6531 struct cvmx_npei_pkt_cnt_int_enb_s 6532 { 6533#if __BYTE_ORDER == __BIG_ENDIAN 6534 uint64_t reserved_32_63 : 32; 6535 uint64_t port : 32; /**< Bit vector cooresponding to ring number when set 6536 allows NPEI_PKT_CNT_INT to generate an interrupt. */ 6537#else 6538 uint64_t port : 32; 6539 uint64_t reserved_32_63 : 32; 6540#endif 6541 } s; 6542 struct cvmx_npei_pkt_cnt_int_enb_s cn52xx; 6543 struct cvmx_npei_pkt_cnt_int_enb_s cn56xx; 6544}; 6545typedef union cvmx_npei_pkt_cnt_int_enb cvmx_npei_pkt_cnt_int_enb_t; 6546 6547/** 6548 * cvmx_npei_pkt_data_out_es 6549 * 6550 * NPEI_PKT_DATA_OUT_ES = NPEI's Packet Data Out Endian Swap 6551 * 6552 * The Endian Swap for writing Data Out. 6553 */ 6554union cvmx_npei_pkt_data_out_es 6555{ 6556 uint64_t u64; 6557 struct cvmx_npei_pkt_data_out_es_s 6558 { 6559#if __BYTE_ORDER == __BIG_ENDIAN 6560 uint64_t es : 64; /**< The endian swap mode for Packet rings 0 through 31. 6561 Two bits are used per ring (i.e. ring 0 [1:0], 6562 ring 1 [3:2], ....). */ 6563#else 6564 uint64_t es : 64; 6565#endif 6566 } s; 6567 struct cvmx_npei_pkt_data_out_es_s cn52xx; 6568 struct cvmx_npei_pkt_data_out_es_s cn56xx; 6569}; 6570typedef union cvmx_npei_pkt_data_out_es cvmx_npei_pkt_data_out_es_t; 6571 6572/** 6573 * cvmx_npei_pkt_data_out_ns 6574 * 6575 * NPEI_PKT_DATA_OUT_NS = NPEI's Packet Data Out No Snoop 6576 * 6577 * The NS field for the TLP when writing packet data. 6578 */ 6579union cvmx_npei_pkt_data_out_ns 6580{ 6581 uint64_t u64; 6582 struct cvmx_npei_pkt_data_out_ns_s 6583 { 6584#if __BYTE_ORDER == __BIG_ENDIAN 6585 uint64_t reserved_32_63 : 32; 6586 uint64_t nsr : 32; /**< When asserted '1' the vector bit cooresponding 6587 to the Packet-ring will enable NS in TLP header. */ 6588#else 6589 uint64_t nsr : 32; 6590 uint64_t reserved_32_63 : 32; 6591#endif 6592 } s; 6593 struct cvmx_npei_pkt_data_out_ns_s cn52xx; 6594 struct cvmx_npei_pkt_data_out_ns_s cn56xx; 6595}; 6596typedef union cvmx_npei_pkt_data_out_ns cvmx_npei_pkt_data_out_ns_t; 6597 6598/** 6599 * cvmx_npei_pkt_data_out_ror 6600 * 6601 * NPEI_PKT_DATA_OUT_ROR = NPEI's Packet Data Out Relaxed Ordering 6602 * 6603 * The ROR field for the TLP when writing Packet Data. 6604 */ 6605union cvmx_npei_pkt_data_out_ror 6606{ 6607 uint64_t u64; 6608 struct cvmx_npei_pkt_data_out_ror_s 6609 { 6610#if __BYTE_ORDER == __BIG_ENDIAN 6611 uint64_t reserved_32_63 : 32; 6612 uint64_t ror : 32; /**< When asserted '1' the vector bit cooresponding 6613 to the Packet-ring will enable ROR in TLP header. */ 6614#else 6615 uint64_t ror : 32; 6616 uint64_t reserved_32_63 : 32; 6617#endif 6618 } s; 6619 struct cvmx_npei_pkt_data_out_ror_s cn52xx; 6620 struct cvmx_npei_pkt_data_out_ror_s cn56xx; 6621}; 6622typedef union cvmx_npei_pkt_data_out_ror cvmx_npei_pkt_data_out_ror_t; 6623 6624/** 6625 * cvmx_npei_pkt_dpaddr 6626 * 6627 * NPEI_PKT_DPADDR = NPEI's Packet Data Pointer Addr 6628 * 6629 * Used to detemine address and attributes for packet data writes. 6630 */ 6631union cvmx_npei_pkt_dpaddr 6632{ 6633 uint64_t u64; 6634 struct cvmx_npei_pkt_dpaddr_s 6635 { 6636#if __BYTE_ORDER == __BIG_ENDIAN 6637 uint64_t reserved_32_63 : 32; 6638 uint64_t dptr : 32; /**< When asserted '1' the vector bit cooresponding 6639 to the Packet-ring will use: 6640 the address[63:60] to write packet data 6641 comes from the DPTR[63:60] in the scatter-list 6642 pair and the RO, NS, ES values come from the O0_ES, 6643 O0_NS, O0_RO. When '0' the RO == DPTR[60], 6644 NS == DPTR[61], ES == DPTR[63:62], the address the 6645 packet will be written to is ADDR[63:60] == 6646 O0_ES[1:0], O0_NS, O0_RO. */ 6647#else 6648 uint64_t dptr : 32; 6649 uint64_t reserved_32_63 : 32; 6650#endif 6651 } s; 6652 struct cvmx_npei_pkt_dpaddr_s cn52xx; 6653 struct cvmx_npei_pkt_dpaddr_s cn56xx; 6654}; 6655typedef union cvmx_npei_pkt_dpaddr cvmx_npei_pkt_dpaddr_t; 6656 6657/** 6658 * cvmx_npei_pkt_in_bp 6659 * 6660 * NPEI_PKT_IN_BP = NPEI Packet Input Backpressure 6661 * 6662 * Which input rings have backpressure applied. 6663 */ 6664union cvmx_npei_pkt_in_bp 6665{ 6666 uint64_t u64; 6667 struct cvmx_npei_pkt_in_bp_s 6668 { 6669#if __BYTE_ORDER == __BIG_ENDIAN 6670 uint64_t reserved_32_63 : 32; 6671 uint64_t bp : 32; /**< A packet input ring that has its count greater 6672 than its WMARK will have backpressure applied. 6673 Each of the 32 bits coorespond to an input ring. 6674 When '1' that ring has backpressure applied an 6675 will fetch no more instructions, but will process 6676 any previously fetched instructions. */ 6677#else 6678 uint64_t bp : 32; 6679 uint64_t reserved_32_63 : 32; 6680#endif 6681 } s; 6682 struct cvmx_npei_pkt_in_bp_s cn52xx; 6683 struct cvmx_npei_pkt_in_bp_s cn56xx; 6684}; 6685typedef union cvmx_npei_pkt_in_bp cvmx_npei_pkt_in_bp_t; 6686 6687/** 6688 * cvmx_npei_pkt_in_done#_cnts 6689 * 6690 * NPEI_PKT_IN_DONE[0..31]_CNTS = NPEI Instruction Done ring# Counts 6691 * 6692 * Counters for instructions completed on Input rings. 6693 */ 6694union cvmx_npei_pkt_in_donex_cnts 6695{ 6696 uint64_t u64; 6697 struct cvmx_npei_pkt_in_donex_cnts_s 6698 { 6699#if __BYTE_ORDER == __BIG_ENDIAN 6700 uint64_t reserved_32_63 : 32; 6701 uint64_t cnt : 32; /**< This field is incrmented by '1' when an instruction 6702 is completed. This field is incremented as the 6703 last of the data is read from the PCIe. */ 6704#else 6705 uint64_t cnt : 32; 6706 uint64_t reserved_32_63 : 32; 6707#endif 6708 } s; 6709 struct cvmx_npei_pkt_in_donex_cnts_s cn52xx; 6710 struct cvmx_npei_pkt_in_donex_cnts_s cn56xx; 6711}; 6712typedef union cvmx_npei_pkt_in_donex_cnts cvmx_npei_pkt_in_donex_cnts_t; 6713 6714/** 6715 * cvmx_npei_pkt_in_instr_counts 6716 * 6717 * NPEI_PKT_IN_INSTR_COUNTS = NPEI Packet Input Instrutction Counts 6718 * 6719 * Keeps track of the number of instructions read into the FIFO and Packets sent to IPD. 6720 */ 6721union cvmx_npei_pkt_in_instr_counts 6722{ 6723 uint64_t u64; 6724 struct cvmx_npei_pkt_in_instr_counts_s 6725 { 6726#if __BYTE_ORDER == __BIG_ENDIAN 6727 uint64_t wr_cnt : 32; /**< Shows the number of packets sent to the IPD. */ 6728 uint64_t rd_cnt : 32; /**< Shows the value of instructions that have had reads 6729 issued for them. 6730 to the Packet-ring is in reset. */ 6731#else 6732 uint64_t rd_cnt : 32; 6733 uint64_t wr_cnt : 32; 6734#endif 6735 } s; 6736 struct cvmx_npei_pkt_in_instr_counts_s cn52xx; 6737 struct cvmx_npei_pkt_in_instr_counts_s cn56xx; 6738}; 6739typedef union cvmx_npei_pkt_in_instr_counts cvmx_npei_pkt_in_instr_counts_t; 6740 6741/** 6742 * cvmx_npei_pkt_in_pcie_port 6743 * 6744 * NPEI_PKT_IN_PCIE_PORT = NPEI's Packet In To PCIe Port Assignment 6745 * 6746 * Assigns Packet Input rings to PCIe ports. 6747 */ 6748union cvmx_npei_pkt_in_pcie_port 6749{ 6750 uint64_t u64; 6751 struct cvmx_npei_pkt_in_pcie_port_s 6752 { 6753#if __BYTE_ORDER == __BIG_ENDIAN 6754 uint64_t pp : 64; /**< The PCIe port that the Packet ring number is 6755 assigned. Two bits are used per ring (i.e. ring 0 6756 [1:0], ring 1 [3:2], ....). A value of '0 means 6757 that the Packetring is assign to PCIe Port 0, a '1' 6758 PCIe Port 1, '2' and '3' are reserved. */ 6759#else 6760 uint64_t pp : 64; 6761#endif 6762 } s; 6763 struct cvmx_npei_pkt_in_pcie_port_s cn52xx; 6764 struct cvmx_npei_pkt_in_pcie_port_s cn56xx; 6765}; 6766typedef union cvmx_npei_pkt_in_pcie_port cvmx_npei_pkt_in_pcie_port_t; 6767 6768/** 6769 * cvmx_npei_pkt_input_control 6770 * 6771 * NPEI_PKT_INPUT_CONTROL = NPEI's Packet Input Control 6772 * 6773 * Control for reads for gather list and instructions. 6774 */ 6775union cvmx_npei_pkt_input_control 6776{ 6777 uint64_t u64; 6778 struct cvmx_npei_pkt_input_control_s 6779 { 6780#if __BYTE_ORDER == __BIG_ENDIAN 6781 uint64_t reserved_23_63 : 41; 6782 uint64_t pkt_rr : 1; /**< When set '1' the input packet selection will be 6783 made with a Round Robin arbitration. When '0' 6784 the input packet ring is fixed in priority, 6785 where the lower ring number has higher priority. */ 6786 uint64_t pbp_dhi : 13; /**< Field when in [PBP] is set to be used in 6787 calculating a DPTR. */ 6788 uint64_t d_nsr : 1; /**< Enables '1' NoSnoop for reading of 6789 gather data. */ 6790 uint64_t d_esr : 2; /**< The Endian-Swap-Mode for reading of 6791 gather data. */ 6792 uint64_t d_ror : 1; /**< Enables '1' Relaxed Ordering for reading of 6793 gather data. */ 6794 uint64_t use_csr : 1; /**< When set '1' the csr value will be used for 6795 ROR, ESR, and NSR. When clear '0' the value in 6796 DPTR will be used. In turn the bits not used for 6797 ROR, ESR, and NSR, will be used for bits [63:60] 6798 of the address used to fetch packet data. */ 6799 uint64_t nsr : 1; /**< Enables '1' NoSnoop for reading of 6800 gather list and gather instruction. */ 6801 uint64_t esr : 2; /**< The Endian-Swap-Mode for reading of 6802 gather list and gather instruction. */ 6803 uint64_t ror : 1; /**< Enables '1' Relaxed Ordering for reading of 6804 gather list and gather instruction. */ 6805#else 6806 uint64_t ror : 1; 6807 uint64_t esr : 2; 6808 uint64_t nsr : 1; 6809 uint64_t use_csr : 1; 6810 uint64_t d_ror : 1; 6811 uint64_t d_esr : 2; 6812 uint64_t d_nsr : 1; 6813 uint64_t pbp_dhi : 13; 6814 uint64_t pkt_rr : 1; 6815 uint64_t reserved_23_63 : 41; 6816#endif 6817 } s; 6818 struct cvmx_npei_pkt_input_control_s cn52xx; 6819 struct cvmx_npei_pkt_input_control_s cn56xx; 6820}; 6821typedef union cvmx_npei_pkt_input_control cvmx_npei_pkt_input_control_t; 6822 6823/** 6824 * cvmx_npei_pkt_instr_enb 6825 * 6826 * NPEI_PKT_INSTR_ENB = NPEI's Packet Instruction Enable 6827 * 6828 * Enables the instruction fetch for a Packet-ring. 6829 */ 6830union cvmx_npei_pkt_instr_enb 6831{ 6832 uint64_t u64; 6833 struct cvmx_npei_pkt_instr_enb_s 6834 { 6835#if __BYTE_ORDER == __BIG_ENDIAN 6836 uint64_t reserved_32_63 : 32; 6837 uint64_t enb : 32; /**< When asserted '1' the vector bit cooresponding 6838 to the Packet-ring is enabled. */ 6839#else 6840 uint64_t enb : 32; 6841 uint64_t reserved_32_63 : 32; 6842#endif 6843 } s; 6844 struct cvmx_npei_pkt_instr_enb_s cn52xx; 6845 struct cvmx_npei_pkt_instr_enb_s cn56xx; 6846}; 6847typedef union cvmx_npei_pkt_instr_enb cvmx_npei_pkt_instr_enb_t; 6848 6849/** 6850 * cvmx_npei_pkt_instr_rd_size 6851 * 6852 * NPEI_PKT_INSTR_RD_SIZE = NPEI Instruction Read Size 6853 * 6854 * The number of instruction allowed to be read at one time. 6855 */ 6856union cvmx_npei_pkt_instr_rd_size 6857{ 6858 uint64_t u64; 6859 struct cvmx_npei_pkt_instr_rd_size_s 6860 { 6861#if __BYTE_ORDER == __BIG_ENDIAN 6862 uint64_t rdsize : 64; /**< Number of instructions to be read in one PCIe read 6863 request for the 4 PKOport - 8 rings. Every two bits 6864 (i.e. 1:0, 3:2, 5:4..) are assign to the port/ring 6865 combinations. 6866 - 15:0 PKOPort0,Ring 7..0 31:16 PKOPort1,Ring 7..0 6867 - 47:32 PKOPort2,Ring 7..0 63:48 PKOPort3,Ring 7..0 6868 Two bit value are: 6869 0 - 1 Instruction 6870 1 - 2 Instructions 6871 2 - 3 Instructions 6872 3 - 4 Instructions */ 6873#else 6874 uint64_t rdsize : 64; 6875#endif 6876 } s; 6877 struct cvmx_npei_pkt_instr_rd_size_s cn52xx; 6878 struct cvmx_npei_pkt_instr_rd_size_s cn56xx; 6879}; 6880typedef union cvmx_npei_pkt_instr_rd_size cvmx_npei_pkt_instr_rd_size_t; 6881 6882/** 6883 * cvmx_npei_pkt_instr_size 6884 * 6885 * NPEI_PKT_INSTR_SIZE = NPEI's Packet Instruction Size 6886 * 6887 * Determines if instructions are 64 or 32 byte in size for a Packet-ring. 6888 */ 6889union cvmx_npei_pkt_instr_size 6890{ 6891 uint64_t u64; 6892 struct cvmx_npei_pkt_instr_size_s 6893 { 6894#if __BYTE_ORDER == __BIG_ENDIAN 6895 uint64_t reserved_32_63 : 32; 6896 uint64_t is_64b : 32; /**< When asserted '1' the vector bit cooresponding 6897 to the Packet-ring is a 64-byte instruction. */ 6898#else 6899 uint64_t is_64b : 32; 6900 uint64_t reserved_32_63 : 32; 6901#endif 6902 } s; 6903 struct cvmx_npei_pkt_instr_size_s cn52xx; 6904 struct cvmx_npei_pkt_instr_size_s cn56xx; 6905}; 6906typedef union cvmx_npei_pkt_instr_size cvmx_npei_pkt_instr_size_t; 6907 6908/** 6909 * cvmx_npei_pkt_int_levels 6910 * 6911 * 0x90F0 reserved NPEI_PKT_PCIE_PORT2 6912 * 6913 * 6914 * NPEI_PKT_INT_LEVELS = NPEI's Packet Interrupt Levels 6915 * 6916 * Output packet interrupt levels. 6917 */ 6918union cvmx_npei_pkt_int_levels 6919{ 6920 uint64_t u64; 6921 struct cvmx_npei_pkt_int_levels_s 6922 { 6923#if __BYTE_ORDER == __BIG_ENDIAN 6924 uint64_t reserved_54_63 : 10; 6925 uint64_t time : 22; /**< When NPEI_PKT#_CNTS[TIMER] is greater than this 6926 value an interrupt is generated. */ 6927 uint64_t cnt : 32; /**< When NPEI_PKT#_CNTS[CNT] becomes 6928 greater than this value an interrupt is generated. */ 6929#else 6930 uint64_t cnt : 32; 6931 uint64_t time : 22; 6932 uint64_t reserved_54_63 : 10; 6933#endif 6934 } s; 6935 struct cvmx_npei_pkt_int_levels_s cn52xx; 6936 struct cvmx_npei_pkt_int_levels_s cn56xx; 6937}; 6938typedef union cvmx_npei_pkt_int_levels cvmx_npei_pkt_int_levels_t; 6939 6940/** 6941 * cvmx_npei_pkt_iptr 6942 * 6943 * NPEI_PKT_IPTR = NPEI's Packet Info Poitner 6944 * 6945 * Controls using the Info-Pointer to store length and data. 6946 */ 6947union cvmx_npei_pkt_iptr 6948{ 6949 uint64_t u64; 6950 struct cvmx_npei_pkt_iptr_s 6951 { 6952#if __BYTE_ORDER == __BIG_ENDIAN 6953 uint64_t reserved_32_63 : 32; 6954 uint64_t iptr : 32; /**< When asserted '1' the vector bit cooresponding 6955 to the Packet-ring will use the Info-Pointer to 6956 store length and data. */ 6957#else 6958 uint64_t iptr : 32; 6959 uint64_t reserved_32_63 : 32; 6960#endif 6961 } s; 6962 struct cvmx_npei_pkt_iptr_s cn52xx; 6963 struct cvmx_npei_pkt_iptr_s cn56xx; 6964}; 6965typedef union cvmx_npei_pkt_iptr cvmx_npei_pkt_iptr_t; 6966 6967/** 6968 * cvmx_npei_pkt_out_bmode 6969 * 6970 * NPEI_PKT_OUT_BMODE = NPEI's Packet Out Byte Mode 6971 * 6972 * Control the updating of the NPEI_PKT#_CNT register. 6973 */ 6974union cvmx_npei_pkt_out_bmode 6975{ 6976 uint64_t u64; 6977 struct cvmx_npei_pkt_out_bmode_s 6978 { 6979#if __BYTE_ORDER == __BIG_ENDIAN 6980 uint64_t reserved_32_63 : 32; 6981 uint64_t bmode : 32; /**< When asserted '1' the vector bit cooresponding 6982 to the Packet-ring will have its NPEI_PKT#_CNT 6983 register updated with the number of bytes in the 6984 packet sent, when '0' the register will have a 6985 value of '1' added. */ 6986#else 6987 uint64_t bmode : 32; 6988 uint64_t reserved_32_63 : 32; 6989#endif 6990 } s; 6991 struct cvmx_npei_pkt_out_bmode_s cn52xx; 6992 struct cvmx_npei_pkt_out_bmode_s cn56xx; 6993}; 6994typedef union cvmx_npei_pkt_out_bmode cvmx_npei_pkt_out_bmode_t; 6995 6996/** 6997 * cvmx_npei_pkt_out_enb 6998 * 6999 * NPEI_PKT_OUT_ENB = NPEI's Packet Output Enable 7000 * 7001 * Enables the output packet engines. 7002 */ 7003union cvmx_npei_pkt_out_enb 7004{ 7005 uint64_t u64; 7006 struct cvmx_npei_pkt_out_enb_s 7007 { 7008#if __BYTE_ORDER == __BIG_ENDIAN 7009 uint64_t reserved_32_63 : 32; 7010 uint64_t enb : 32; /**< When asserted '1' the vector bit cooresponding 7011 to the Packet-ring is enabled. 7012 If an error occurs on reading pointers for an 7013 output ring, the ring will be disabled by clearing 7014 the bit associated with the ring to '0'. */ 7015#else 7016 uint64_t enb : 32; 7017 uint64_t reserved_32_63 : 32; 7018#endif 7019 } s; 7020 struct cvmx_npei_pkt_out_enb_s cn52xx; 7021 struct cvmx_npei_pkt_out_enb_s cn56xx; 7022}; 7023typedef union cvmx_npei_pkt_out_enb cvmx_npei_pkt_out_enb_t; 7024 7025/** 7026 * cvmx_npei_pkt_output_wmark 7027 * 7028 * NPEI_PKT_OUTPUT_WMARK = NPEI's Packet Output Water Mark 7029 * 7030 * Value that when the NPEI_PKT#_SLIST_BAOFF_DBELL[DBELL] value is less then that backpressure for the rings will be applied. 7031 */ 7032union cvmx_npei_pkt_output_wmark 7033{ 7034 uint64_t u64; 7035 struct cvmx_npei_pkt_output_wmark_s 7036 { 7037#if __BYTE_ORDER == __BIG_ENDIAN 7038 uint64_t reserved_32_63 : 32; 7039 uint64_t wmark : 32; /**< Value when DBELL count drops below backpressure 7040 for the ring will be applied to the PKO. */ 7041#else 7042 uint64_t wmark : 32; 7043 uint64_t reserved_32_63 : 32; 7044#endif 7045 } s; 7046 struct cvmx_npei_pkt_output_wmark_s cn52xx; 7047 struct cvmx_npei_pkt_output_wmark_s cn56xx; 7048}; 7049typedef union cvmx_npei_pkt_output_wmark cvmx_npei_pkt_output_wmark_t; 7050 7051/** 7052 * cvmx_npei_pkt_pcie_port 7053 * 7054 * NPEI_PKT_PCIE_PORT = NPEI's Packet To PCIe Port Assignment 7055 * 7056 * Assigns Packet Ports to PCIe ports. 7057 */ 7058union cvmx_npei_pkt_pcie_port 7059{ 7060 uint64_t u64; 7061 struct cvmx_npei_pkt_pcie_port_s 7062 { 7063#if __BYTE_ORDER == __BIG_ENDIAN 7064 uint64_t pp : 64; /**< The PCIe port that the Packet ring number is 7065 assigned. Two bits are used per ring (i.e. ring 0 7066 [1:0], ring 1 [3:2], ....). A value of '0 means 7067 that the Packetring is assign to PCIe Port 0, a '1' 7068 PCIe Port 1, '2' and '3' are reserved. */ 7069#else 7070 uint64_t pp : 64; 7071#endif 7072 } s; 7073 struct cvmx_npei_pkt_pcie_port_s cn52xx; 7074 struct cvmx_npei_pkt_pcie_port_s cn56xx; 7075}; 7076typedef union cvmx_npei_pkt_pcie_port cvmx_npei_pkt_pcie_port_t; 7077 7078/** 7079 * cvmx_npei_pkt_port_in_rst 7080 * 7081 * NPEI_PKT_PORT_IN_RST = NPEI Packet Port In Reset 7082 * 7083 * Vector bits related to ring-port for ones that are reset. 7084 */ 7085union cvmx_npei_pkt_port_in_rst 7086{ 7087 uint64_t u64; 7088 struct cvmx_npei_pkt_port_in_rst_s 7089 { 7090#if __BYTE_ORDER == __BIG_ENDIAN 7091 uint64_t in_rst : 32; /**< When asserted '1' the vector bit cooresponding 7092 to the inbound Packet-ring is in reset. */ 7093 uint64_t out_rst : 32; /**< When asserted '1' the vector bit cooresponding 7094 to the outbound Packet-ring is in reset. */ 7095#else 7096 uint64_t out_rst : 32; 7097 uint64_t in_rst : 32; 7098#endif 7099 } s; 7100 struct cvmx_npei_pkt_port_in_rst_s cn52xx; 7101 struct cvmx_npei_pkt_port_in_rst_s cn56xx; 7102}; 7103typedef union cvmx_npei_pkt_port_in_rst cvmx_npei_pkt_port_in_rst_t; 7104 7105/** 7106 * cvmx_npei_pkt_slist_es 7107 * 7108 * NPEI_PKT_SLIST_ES = NPEI's Packet Scatter List Endian Swap 7109 * 7110 * The Endian Swap for Scatter List Read. 7111 */ 7112union cvmx_npei_pkt_slist_es 7113{ 7114 uint64_t u64; 7115 struct cvmx_npei_pkt_slist_es_s 7116 { 7117#if __BYTE_ORDER == __BIG_ENDIAN 7118 uint64_t es : 64; /**< The endian swap mode for Packet rings 0 through 31. 7119 Two bits are used per ring (i.e. ring 0 [1:0], 7120 ring 1 [3:2], ....). */ 7121#else 7122 uint64_t es : 64; 7123#endif 7124 } s; 7125 struct cvmx_npei_pkt_slist_es_s cn52xx; 7126 struct cvmx_npei_pkt_slist_es_s cn56xx; 7127}; 7128typedef union cvmx_npei_pkt_slist_es cvmx_npei_pkt_slist_es_t; 7129 7130/** 7131 * cvmx_npei_pkt_slist_id_size 7132 * 7133 * NPEI_PKT_SLIST_ID_SIZE = NPEI Packet Scatter List Info and Data Size 7134 * 7135 * The Size of the information and data fields pointed to by Scatter List pointers. 7136 */ 7137union cvmx_npei_pkt_slist_id_size 7138{ 7139 uint64_t u64; 7140 struct cvmx_npei_pkt_slist_id_size_s 7141 { 7142#if __BYTE_ORDER == __BIG_ENDIAN 7143 uint64_t reserved_23_63 : 41; 7144 uint64_t isize : 7; /**< Information size. Legal sizes are 0 to 120. */ 7145 uint64_t bsize : 16; /**< Data size. */ 7146#else 7147 uint64_t bsize : 16; 7148 uint64_t isize : 7; 7149 uint64_t reserved_23_63 : 41; 7150#endif 7151 } s; 7152 struct cvmx_npei_pkt_slist_id_size_s cn52xx; 7153 struct cvmx_npei_pkt_slist_id_size_s cn56xx; 7154}; 7155typedef union cvmx_npei_pkt_slist_id_size cvmx_npei_pkt_slist_id_size_t; 7156 7157/** 7158 * cvmx_npei_pkt_slist_ns 7159 * 7160 * NPEI_PKT_SLIST_NS = NPEI's Packet Scatter List No Snoop 7161 * 7162 * The NS field for the TLP when fetching Scatter List. 7163 */ 7164union cvmx_npei_pkt_slist_ns 7165{ 7166 uint64_t u64; 7167 struct cvmx_npei_pkt_slist_ns_s 7168 { 7169#if __BYTE_ORDER == __BIG_ENDIAN 7170 uint64_t reserved_32_63 : 32; 7171 uint64_t nsr : 32; /**< When asserted '1' the vector bit cooresponding 7172 to the Packet-ring will enable NS in TLP header. */ 7173#else 7174 uint64_t nsr : 32; 7175 uint64_t reserved_32_63 : 32; 7176#endif 7177 } s; 7178 struct cvmx_npei_pkt_slist_ns_s cn52xx; 7179 struct cvmx_npei_pkt_slist_ns_s cn56xx; 7180}; 7181typedef union cvmx_npei_pkt_slist_ns cvmx_npei_pkt_slist_ns_t; 7182 7183/** 7184 * cvmx_npei_pkt_slist_ror 7185 * 7186 * NPEI_PKT_SLIST_ROR = NPEI's Packet Scatter List Relaxed Ordering 7187 * 7188 * The ROR field for the TLP when fetching Scatter List. 7189 */ 7190union cvmx_npei_pkt_slist_ror 7191{ 7192 uint64_t u64; 7193 struct cvmx_npei_pkt_slist_ror_s 7194 { 7195#if __BYTE_ORDER == __BIG_ENDIAN 7196 uint64_t reserved_32_63 : 32; 7197 uint64_t ror : 32; /**< When asserted '1' the vector bit cooresponding 7198 to the Packet-ring will enable ROR in TLP header. */ 7199#else 7200 uint64_t ror : 32; 7201 uint64_t reserved_32_63 : 32; 7202#endif 7203 } s; 7204 struct cvmx_npei_pkt_slist_ror_s cn52xx; 7205 struct cvmx_npei_pkt_slist_ror_s cn56xx; 7206}; 7207typedef union cvmx_npei_pkt_slist_ror cvmx_npei_pkt_slist_ror_t; 7208 7209/** 7210 * cvmx_npei_pkt_time_int 7211 * 7212 * NPEI_PKT_TIME_INT = NPEI Packet Timer Interrupt 7213 * 7214 * The packets rings that are interrupting because of Packet Timers. 7215 */ 7216union cvmx_npei_pkt_time_int 7217{ 7218 uint64_t u64; 7219 struct cvmx_npei_pkt_time_int_s 7220 { 7221#if __BYTE_ORDER == __BIG_ENDIAN 7222 uint64_t reserved_32_63 : 32; 7223 uint64_t port : 32; /**< Bit vector cooresponding to ring number is set when 7224 NPEI_PKT#_CNTS[TIMER] is greater than 7225 NPEI_PKT_INT_LEVELS[TIME]. */ 7226#else 7227 uint64_t port : 32; 7228 uint64_t reserved_32_63 : 32; 7229#endif 7230 } s; 7231 struct cvmx_npei_pkt_time_int_s cn52xx; 7232 struct cvmx_npei_pkt_time_int_s cn56xx; 7233}; 7234typedef union cvmx_npei_pkt_time_int cvmx_npei_pkt_time_int_t; 7235 7236/** 7237 * cvmx_npei_pkt_time_int_enb 7238 * 7239 * NPEI_PKT_TIME_INT_ENB = NPEI Packet Timer Interrupt Enable 7240 * 7241 * The packets rings that are interrupting because of Packet Timers. 7242 */ 7243union cvmx_npei_pkt_time_int_enb 7244{ 7245 uint64_t u64; 7246 struct cvmx_npei_pkt_time_int_enb_s 7247 { 7248#if __BYTE_ORDER == __BIG_ENDIAN 7249 uint64_t reserved_32_63 : 32; 7250 uint64_t port : 32; /**< Bit vector cooresponding to ring number when set 7251 allows NPEI_PKT_TIME_INT to generate an interrupt. */ 7252#else 7253 uint64_t port : 32; 7254 uint64_t reserved_32_63 : 32; 7255#endif 7256 } s; 7257 struct cvmx_npei_pkt_time_int_enb_s cn52xx; 7258 struct cvmx_npei_pkt_time_int_enb_s cn56xx; 7259}; 7260typedef union cvmx_npei_pkt_time_int_enb cvmx_npei_pkt_time_int_enb_t; 7261 7262/** 7263 * cvmx_npei_rsl_int_blocks 7264 * 7265 * NPEI_RSL_INT_BLOCKS = NPEI RSL Interrupt Blocks Register 7266 * 7267 * Reading this register will return a vector with a bit set '1' for a corresponding RSL block 7268 * that presently has an interrupt pending. The Field Description below supplies the name of the 7269 * register that software should read to find out why that intterupt bit is set. 7270 */ 7271union cvmx_npei_rsl_int_blocks 7272{ 7273 uint64_t u64; 7274 struct cvmx_npei_rsl_int_blocks_s 7275 { 7276#if __BYTE_ORDER == __BIG_ENDIAN 7277 uint64_t reserved_31_63 : 33; 7278 uint64_t iob : 1; /**< IOB_INT_SUM */ 7279 uint64_t lmc1 : 1; /**< LMC1_MEM_CFG0 */ 7280 uint64_t agl : 1; /**< AGL_GMX_RX0_INT_REG & AGL_GMX_TX_INT_REG */ 7281 uint64_t reserved_24_27 : 4; 7282 uint64_t asxpcs1 : 1; /**< PCS1_INT*_REG */ 7283 uint64_t asxpcs0 : 1; /**< PCS0_INT*_REG */ 7284 uint64_t reserved_21_21 : 1; 7285 uint64_t pip : 1; /**< PIP_INT_REG. */ 7286 uint64_t spx1 : 1; /**< Always reads as zero */ 7287 uint64_t spx0 : 1; /**< Always reads as zero */ 7288 uint64_t lmc0 : 1; /**< LMC0_MEM_CFG0 */ 7289 uint64_t l2c : 1; /**< L2C_INT_STAT */ 7290 uint64_t usb1 : 1; /**< Always reads as zero */ 7291 uint64_t rad : 1; /**< RAD_REG_ERROR */ 7292 uint64_t usb : 1; /**< USBN0_INT_SUM */ 7293 uint64_t pow : 1; /**< POW_ECC_ERR */ 7294 uint64_t tim : 1; /**< TIM_REG_ERROR */ 7295 uint64_t pko : 1; /**< PKO_REG_ERROR */ 7296 uint64_t ipd : 1; /**< IPD_INT_SUM */ 7297 uint64_t reserved_8_8 : 1; 7298 uint64_t zip : 1; /**< ZIP_ERROR */ 7299 uint64_t dfa : 1; /**< Always reads as zero */ 7300 uint64_t fpa : 1; /**< FPA_INT_SUM */ 7301 uint64_t key : 1; /**< KEY_INT_SUM */ 7302 uint64_t npei : 1; /**< NPEI_INT_SUM */ 7303 uint64_t gmx1 : 1; /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */ 7304 uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */ 7305 uint64_t mio : 1; /**< MIO_BOOT_ERR */ 7306#else 7307 uint64_t mio : 1; 7308 uint64_t gmx0 : 1; 7309 uint64_t gmx1 : 1; 7310 uint64_t npei : 1; 7311 uint64_t key : 1; 7312 uint64_t fpa : 1; 7313 uint64_t dfa : 1; 7314 uint64_t zip : 1; 7315 uint64_t reserved_8_8 : 1; 7316 uint64_t ipd : 1; 7317 uint64_t pko : 1; 7318 uint64_t tim : 1; 7319 uint64_t pow : 1; 7320 uint64_t usb : 1; 7321 uint64_t rad : 1; 7322 uint64_t usb1 : 1; 7323 uint64_t l2c : 1; 7324 uint64_t lmc0 : 1; 7325 uint64_t spx0 : 1; 7326 uint64_t spx1 : 1; 7327 uint64_t pip : 1; 7328 uint64_t reserved_21_21 : 1; 7329 uint64_t asxpcs0 : 1; 7330 uint64_t asxpcs1 : 1; 7331 uint64_t reserved_24_27 : 4; 7332 uint64_t agl : 1; 7333 uint64_t lmc1 : 1; 7334 uint64_t iob : 1; 7335 uint64_t reserved_31_63 : 33; 7336#endif 7337 } s; 7338 struct cvmx_npei_rsl_int_blocks_s cn52xx; 7339 struct cvmx_npei_rsl_int_blocks_s cn52xxp1; 7340 struct cvmx_npei_rsl_int_blocks_s cn56xx; 7341 struct cvmx_npei_rsl_int_blocks_s cn56xxp1; 7342}; 7343typedef union cvmx_npei_rsl_int_blocks cvmx_npei_rsl_int_blocks_t; 7344 7345/** 7346 * cvmx_npei_scratch_1 7347 * 7348 * NPEI_SCRATCH_1 = NPEI's Scratch 1 7349 * 7350 * A general purpose 64 bit register for SW use. 7351 */ 7352union cvmx_npei_scratch_1 7353{ 7354 uint64_t u64; 7355 struct cvmx_npei_scratch_1_s 7356 { 7357#if __BYTE_ORDER == __BIG_ENDIAN 7358 uint64_t data : 64; /**< The value in this register is totaly SW dependent. */ 7359#else 7360 uint64_t data : 64; 7361#endif 7362 } s; 7363 struct cvmx_npei_scratch_1_s cn52xx; 7364 struct cvmx_npei_scratch_1_s cn52xxp1; 7365 struct cvmx_npei_scratch_1_s cn56xx; 7366 struct cvmx_npei_scratch_1_s cn56xxp1; 7367}; 7368typedef union cvmx_npei_scratch_1 cvmx_npei_scratch_1_t; 7369 7370/** 7371 * cvmx_npei_state1 7372 * 7373 * NPEI_STATE1 = NPEI State 1 7374 * 7375 * State machines in NPEI. For debug. 7376 */ 7377union cvmx_npei_state1 7378{ 7379 uint64_t u64; 7380 struct cvmx_npei_state1_s 7381 { 7382#if __BYTE_ORDER == __BIG_ENDIAN 7383 uint64_t cpl1 : 12; /**< CPL1 State */ 7384 uint64_t cpl0 : 12; /**< CPL0 State */ 7385 uint64_t arb : 1; /**< ARB State */ 7386 uint64_t csr : 39; /**< CSR State */ 7387#else 7388 uint64_t csr : 39; 7389 uint64_t arb : 1; 7390 uint64_t cpl0 : 12; 7391 uint64_t cpl1 : 12; 7392#endif 7393 } s; 7394 struct cvmx_npei_state1_s cn52xx; 7395 struct cvmx_npei_state1_s cn52xxp1; 7396 struct cvmx_npei_state1_s cn56xx; 7397 struct cvmx_npei_state1_s cn56xxp1; 7398}; 7399typedef union cvmx_npei_state1 cvmx_npei_state1_t; 7400 7401/** 7402 * cvmx_npei_state2 7403 * 7404 * NPEI_STATE2 = NPEI State 2 7405 * 7406 * State machines in NPEI. For debug. 7407 */ 7408union cvmx_npei_state2 7409{ 7410 uint64_t u64; 7411 struct cvmx_npei_state2_s 7412 { 7413#if __BYTE_ORDER == __BIG_ENDIAN 7414 uint64_t reserved_48_63 : 16; 7415 uint64_t npei : 1; /**< NPEI State */ 7416 uint64_t rac : 1; /**< RAC State */ 7417 uint64_t csm1 : 15; /**< CSM1 State */ 7418 uint64_t csm0 : 15; /**< CSM0 State */ 7419 uint64_t nnp0 : 8; /**< NNP0 State */ 7420 uint64_t nnd : 8; /**< NND State */ 7421#else 7422 uint64_t nnd : 8; 7423 uint64_t nnp0 : 8; 7424 uint64_t csm0 : 15; 7425 uint64_t csm1 : 15; 7426 uint64_t rac : 1; 7427 uint64_t npei : 1; 7428 uint64_t reserved_48_63 : 16; 7429#endif 7430 } s; 7431 struct cvmx_npei_state2_s cn52xx; 7432 struct cvmx_npei_state2_s cn52xxp1; 7433 struct cvmx_npei_state2_s cn56xx; 7434 struct cvmx_npei_state2_s cn56xxp1; 7435}; 7436typedef union cvmx_npei_state2 cvmx_npei_state2_t; 7437 7438/** 7439 * cvmx_npei_state3 7440 * 7441 * NPEI_STATE3 = NPEI State 3 7442 * 7443 * State machines in NPEI. For debug. 7444 */ 7445union cvmx_npei_state3 7446{ 7447 uint64_t u64; 7448 struct cvmx_npei_state3_s 7449 { 7450#if __BYTE_ORDER == __BIG_ENDIAN 7451 uint64_t reserved_56_63 : 8; 7452 uint64_t psm1 : 15; /**< PSM1 State */ 7453 uint64_t psm0 : 15; /**< PSM0 State */ 7454 uint64_t nsm1 : 13; /**< NSM1 State */ 7455 uint64_t nsm0 : 13; /**< NSM0 State */ 7456#else 7457 uint64_t nsm0 : 13; 7458 uint64_t nsm1 : 13; 7459 uint64_t psm0 : 15; 7460 uint64_t psm1 : 15; 7461 uint64_t reserved_56_63 : 8; 7462#endif 7463 } s; 7464 struct cvmx_npei_state3_s cn52xx; 7465 struct cvmx_npei_state3_s cn52xxp1; 7466 struct cvmx_npei_state3_s cn56xx; 7467 struct cvmx_npei_state3_s cn56xxp1; 7468}; 7469typedef union cvmx_npei_state3 cvmx_npei_state3_t; 7470 7471/** 7472 * cvmx_npei_win_rd_addr 7473 * 7474 * NPEI_WIN_RD_ADDR = NPEI Window Read Address Register 7475 * 7476 * The address to be read when the NPEI_WIN_RD_DATA register is read. 7477 */ 7478union cvmx_npei_win_rd_addr 7479{ 7480 uint64_t u64; 7481 struct cvmx_npei_win_rd_addr_s 7482 { 7483#if __BYTE_ORDER == __BIG_ENDIAN 7484 uint64_t reserved_51_63 : 13; 7485 uint64_t ld_cmd : 2; /**< The load command sent wit hthe read. 7486 0x0 == Load 8-bytes, 0x1 == Load 4-bytes, 7487 0x2 == Load 2-bytes, 0x3 == Load 1-bytes, */ 7488 uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 7489 read as '0'. */ 7490 uint64_t rd_addr : 48; /**< The address to be read from. Whenever the LSB of 7491 this register is written, the Read Operation will 7492 take place. 7493 [47:40] = NCB_ID 7494 [39:0] = Address 7495 When [47:43] == NPI & [42:0] == 0 bits [39:0] are: 7496 [39:32] == x, Not Used 7497 [31:27] == RSL_ID 7498 [12:0] == RSL Register Offset */ 7499#else 7500 uint64_t rd_addr : 48; 7501 uint64_t iobit : 1; 7502 uint64_t ld_cmd : 2; 7503 uint64_t reserved_51_63 : 13; 7504#endif 7505 } s; 7506 struct cvmx_npei_win_rd_addr_s cn52xx; 7507 struct cvmx_npei_win_rd_addr_s cn52xxp1; 7508 struct cvmx_npei_win_rd_addr_s cn56xx; 7509 struct cvmx_npei_win_rd_addr_s cn56xxp1; 7510}; 7511typedef union cvmx_npei_win_rd_addr cvmx_npei_win_rd_addr_t; 7512 7513/** 7514 * cvmx_npei_win_rd_data 7515 * 7516 * NPEI_WIN_RD_DATA = NPEI Window Read Data Register 7517 * 7518 * Reading this register causes a window read operation to take place. Address read is taht contained in the NPEI_WIN_RD_ADDR 7519 * register. 7520 */ 7521union cvmx_npei_win_rd_data 7522{ 7523 uint64_t u64; 7524 struct cvmx_npei_win_rd_data_s 7525 { 7526#if __BYTE_ORDER == __BIG_ENDIAN 7527 uint64_t rd_data : 64; /**< The read data. */ 7528#else 7529 uint64_t rd_data : 64; 7530#endif 7531 } s; 7532 struct cvmx_npei_win_rd_data_s cn52xx; 7533 struct cvmx_npei_win_rd_data_s cn52xxp1; 7534 struct cvmx_npei_win_rd_data_s cn56xx; 7535 struct cvmx_npei_win_rd_data_s cn56xxp1; 7536}; 7537typedef union cvmx_npei_win_rd_data cvmx_npei_win_rd_data_t; 7538 7539/** 7540 * cvmx_npei_win_wr_addr 7541 * 7542 * NPEI_WIN_WR_ADDR = NPEI Window Write Address Register 7543 * 7544 * Contains the address to be writen to when a write operation is started by writing the 7545 * NPEI_WIN_WR_DATA register (see below). 7546 * 7547 * Notes: 7548 * Even though address bit [2] can be set, it should always be kept to '0'. 7549 * 7550 */ 7551union cvmx_npei_win_wr_addr 7552{ 7553 uint64_t u64; 7554 struct cvmx_npei_win_wr_addr_s 7555 { 7556#if __BYTE_ORDER == __BIG_ENDIAN 7557 uint64_t reserved_49_63 : 15; 7558 uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 7559 read as '0'. */ 7560 uint64_t wr_addr : 46; /**< The address that will be written to when the 7561 NPEI_WIN_WR_DATA register is written. 7562 [47:40] = NCB_ID 7563 [39:3] = Address 7564 When [47:43] == NPI & [42:0] == 0 bits [39:0] are: 7565 [39:32] == x, Not Used 7566 [31:27] == RSL_ID 7567 [12:2] == RSL Register Offset 7568 [1:0] == x, Not Used */ 7569 uint64_t reserved_0_1 : 2; 7570#else 7571 uint64_t reserved_0_1 : 2; 7572 uint64_t wr_addr : 46; 7573 uint64_t iobit : 1; 7574 uint64_t reserved_49_63 : 15; 7575#endif 7576 } s; 7577 struct cvmx_npei_win_wr_addr_s cn52xx; 7578 struct cvmx_npei_win_wr_addr_s cn52xxp1; 7579 struct cvmx_npei_win_wr_addr_s cn56xx; 7580 struct cvmx_npei_win_wr_addr_s cn56xxp1; 7581}; 7582typedef union cvmx_npei_win_wr_addr cvmx_npei_win_wr_addr_t; 7583 7584/** 7585 * cvmx_npei_win_wr_data 7586 * 7587 * NPEI_WIN_WR_DATA = NPEI Window Write Data Register 7588 * 7589 * Contains the data to write to the address located in the NPEI_WIN_WR_ADDR Register. 7590 * Writing the least-significant-byte of this register will cause a write operation to take place. 7591 */ 7592union cvmx_npei_win_wr_data 7593{ 7594 uint64_t u64; 7595 struct cvmx_npei_win_wr_data_s 7596 { 7597#if __BYTE_ORDER == __BIG_ENDIAN 7598 uint64_t wr_data : 64; /**< The data to be written. Whenever the LSB of this 7599 register is written, the Window Write will take 7600 place. */ 7601#else 7602 uint64_t wr_data : 64; 7603#endif 7604 } s; 7605 struct cvmx_npei_win_wr_data_s cn52xx; 7606 struct cvmx_npei_win_wr_data_s cn52xxp1; 7607 struct cvmx_npei_win_wr_data_s cn56xx; 7608 struct cvmx_npei_win_wr_data_s cn56xxp1; 7609}; 7610typedef union cvmx_npei_win_wr_data cvmx_npei_win_wr_data_t; 7611 7612/** 7613 * cvmx_npei_win_wr_mask 7614 * 7615 * NPEI_WIN_WR_MASK = NPEI Window Write Mask Register 7616 * 7617 * Contains the mask for the data in the NPEI_WIN_WR_DATA Register. 7618 */ 7619union cvmx_npei_win_wr_mask 7620{ 7621 uint64_t u64; 7622 struct cvmx_npei_win_wr_mask_s 7623 { 7624#if __BYTE_ORDER == __BIG_ENDIAN 7625 uint64_t reserved_8_63 : 56; 7626 uint64_t wr_mask : 8; /**< The data to be written. When a bit is '0' 7627 the corresponding byte will be written. */ 7628#else 7629 uint64_t wr_mask : 8; 7630 uint64_t reserved_8_63 : 56; 7631#endif 7632 } s; 7633 struct cvmx_npei_win_wr_mask_s cn52xx; 7634 struct cvmx_npei_win_wr_mask_s cn52xxp1; 7635 struct cvmx_npei_win_wr_mask_s cn56xx; 7636 struct cvmx_npei_win_wr_mask_s cn56xxp1; 7637}; 7638typedef union cvmx_npei_win_wr_mask cvmx_npei_win_wr_mask_t; 7639 7640/** 7641 * cvmx_npei_window_ctl 7642 * 7643 * NPEI_WINDOW_CTL = NPEI's Window Control 7644 * 7645 * The name of this register is misleading. The timeout value is used for BAR0 access from PCIE0 and PCIE1. 7646 * Any access to the regigisters on the RML will timeout as 0xFFFF clock cycle. At time of timeout the next 7647 * RML access will start, and interrupt will be set, and in the case of reads no data will be returned. 7648 * 7649 * The value of this register should be set to a minimum of 0x200000 to ensure that a timeout to an RML register 7650 * occurs on the RML 0xFFFF timer before the timeout for a BAR0 access from the PCIE#. 7651 */ 7652union cvmx_npei_window_ctl 7653{ 7654 uint64_t u64; 7655 struct cvmx_npei_window_ctl_s 7656 { 7657#if __BYTE_ORDER == __BIG_ENDIAN 7658 uint64_t reserved_32_63 : 32; 7659 uint64_t time : 32; /**< Time to wait in core clocks to wait for a 7660 BAR0 access to completeon the NCB 7661 before timing out. A value of 0 will cause no 7662 timeouts. A minimum value of 0x200000 should be 7663 used when this register is not set to 0x0. */ 7664#else 7665 uint64_t time : 32; 7666 uint64_t reserved_32_63 : 32; 7667#endif 7668 } s; 7669 struct cvmx_npei_window_ctl_s cn52xx; 7670 struct cvmx_npei_window_ctl_s cn52xxp1; 7671 struct cvmx_npei_window_ctl_s cn56xx; 7672 struct cvmx_npei_window_ctl_s cn56xxp1; 7673}; 7674typedef union cvmx_npei_window_ctl cvmx_npei_window_ctl_t; 7675 7676#endif 7677