1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-npei-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon npei. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_NPEI_DEFS_H__ 53232812Sjmallett#define __CVMX_NPEI_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_NPEI_BAR1_INDEXX(unsigned long offset) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 61215976Sjmallett cvmx_warn("CVMX_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset); 62215976Sjmallett return 0x0000000000000000ull + ((offset) & 31) * 16; 63215976Sjmallett} 64215976Sjmallett#else 65215976Sjmallett#define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16) 66215976Sjmallett#endif 67215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68215976Sjmallett#define CVMX_NPEI_BIST_STATUS CVMX_NPEI_BIST_STATUS_FUNC() 69215976Sjmallettstatic inline uint64_t CVMX_NPEI_BIST_STATUS_FUNC(void) 70215976Sjmallett{ 71215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 72215976Sjmallett cvmx_warn("CVMX_NPEI_BIST_STATUS not supported on this chip\n"); 73215976Sjmallett return 0x0000000000000580ull; 74215976Sjmallett} 75215976Sjmallett#else 76215976Sjmallett#define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull) 77215976Sjmallett#endif 78215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 79215976Sjmallett#define CVMX_NPEI_BIST_STATUS2 CVMX_NPEI_BIST_STATUS2_FUNC() 80215976Sjmallettstatic inline uint64_t CVMX_NPEI_BIST_STATUS2_FUNC(void) 81215976Sjmallett{ 82215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 83215976Sjmallett cvmx_warn("CVMX_NPEI_BIST_STATUS2 not supported on this chip\n"); 84215976Sjmallett return 0x0000000000000680ull; 85215976Sjmallett} 86215976Sjmallett#else 87215976Sjmallett#define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull) 88215976Sjmallett#endif 89215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 90215976Sjmallett#define CVMX_NPEI_CTL_PORT0 CVMX_NPEI_CTL_PORT0_FUNC() 91215976Sjmallettstatic inline uint64_t CVMX_NPEI_CTL_PORT0_FUNC(void) 92215976Sjmallett{ 93215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 94215976Sjmallett cvmx_warn("CVMX_NPEI_CTL_PORT0 not supported on this chip\n"); 95215976Sjmallett return 0x0000000000000250ull; 96215976Sjmallett} 97215976Sjmallett#else 98215976Sjmallett#define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull) 99215976Sjmallett#endif 100215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 101215976Sjmallett#define CVMX_NPEI_CTL_PORT1 CVMX_NPEI_CTL_PORT1_FUNC() 102215976Sjmallettstatic inline uint64_t CVMX_NPEI_CTL_PORT1_FUNC(void) 103215976Sjmallett{ 104215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 105215976Sjmallett cvmx_warn("CVMX_NPEI_CTL_PORT1 not supported on this chip\n"); 106215976Sjmallett return 0x0000000000000260ull; 107215976Sjmallett} 108215976Sjmallett#else 109215976Sjmallett#define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull) 110215976Sjmallett#endif 111215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 112215976Sjmallett#define CVMX_NPEI_CTL_STATUS CVMX_NPEI_CTL_STATUS_FUNC() 113215976Sjmallettstatic inline uint64_t CVMX_NPEI_CTL_STATUS_FUNC(void) 114215976Sjmallett{ 115215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 116215976Sjmallett cvmx_warn("CVMX_NPEI_CTL_STATUS not supported on this chip\n"); 117215976Sjmallett return 0x0000000000000570ull; 118215976Sjmallett} 119215976Sjmallett#else 120215976Sjmallett#define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull) 121215976Sjmallett#endif 122215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 123215976Sjmallett#define CVMX_NPEI_CTL_STATUS2 CVMX_NPEI_CTL_STATUS2_FUNC() 124215976Sjmallettstatic inline uint64_t CVMX_NPEI_CTL_STATUS2_FUNC(void) 125215976Sjmallett{ 126215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 127215976Sjmallett cvmx_warn("CVMX_NPEI_CTL_STATUS2 not supported on this chip\n"); 128215976Sjmallett return 0x0000000000003C00ull; 129215976Sjmallett} 130215976Sjmallett#else 131215976Sjmallett#define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull) 132215976Sjmallett#endif 133215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 134215976Sjmallett#define CVMX_NPEI_DATA_OUT_CNT CVMX_NPEI_DATA_OUT_CNT_FUNC() 135215976Sjmallettstatic inline uint64_t CVMX_NPEI_DATA_OUT_CNT_FUNC(void) 136215976Sjmallett{ 137215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 138215976Sjmallett cvmx_warn("CVMX_NPEI_DATA_OUT_CNT not supported on this chip\n"); 139215976Sjmallett return 0x00000000000005F0ull; 140215976Sjmallett} 141215976Sjmallett#else 142215976Sjmallett#define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull) 143215976Sjmallett#endif 144215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 145215976Sjmallett#define CVMX_NPEI_DBG_DATA CVMX_NPEI_DBG_DATA_FUNC() 146215976Sjmallettstatic inline uint64_t CVMX_NPEI_DBG_DATA_FUNC(void) 147215976Sjmallett{ 148215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 149215976Sjmallett cvmx_warn("CVMX_NPEI_DBG_DATA not supported on this chip\n"); 150215976Sjmallett return 0x0000000000000510ull; 151215976Sjmallett} 152215976Sjmallett#else 153215976Sjmallett#define CVMX_NPEI_DBG_DATA (0x0000000000000510ull) 154215976Sjmallett#endif 155215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 156215976Sjmallett#define CVMX_NPEI_DBG_SELECT CVMX_NPEI_DBG_SELECT_FUNC() 157215976Sjmallettstatic inline uint64_t CVMX_NPEI_DBG_SELECT_FUNC(void) 158215976Sjmallett{ 159215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 160215976Sjmallett cvmx_warn("CVMX_NPEI_DBG_SELECT not supported on this chip\n"); 161215976Sjmallett return 0x0000000000000500ull; 162215976Sjmallett} 163215976Sjmallett#else 164215976Sjmallett#define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull) 165215976Sjmallett#endif 166215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 167215976Sjmallett#define CVMX_NPEI_DMA0_INT_LEVEL CVMX_NPEI_DMA0_INT_LEVEL_FUNC() 168215976Sjmallettstatic inline uint64_t CVMX_NPEI_DMA0_INT_LEVEL_FUNC(void) 169215976Sjmallett{ 170215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 171215976Sjmallett cvmx_warn("CVMX_NPEI_DMA0_INT_LEVEL not supported on this chip\n"); 172215976Sjmallett return 0x00000000000005C0ull; 173215976Sjmallett} 174215976Sjmallett#else 175215976Sjmallett#define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull) 176215976Sjmallett#endif 177215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 178215976Sjmallett#define CVMX_NPEI_DMA1_INT_LEVEL CVMX_NPEI_DMA1_INT_LEVEL_FUNC() 179215976Sjmallettstatic inline uint64_t CVMX_NPEI_DMA1_INT_LEVEL_FUNC(void) 180215976Sjmallett{ 181215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 182215976Sjmallett cvmx_warn("CVMX_NPEI_DMA1_INT_LEVEL not supported on this chip\n"); 183215976Sjmallett return 0x00000000000005D0ull; 184215976Sjmallett} 185215976Sjmallett#else 186215976Sjmallett#define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull) 187215976Sjmallett#endif 188215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 189215976Sjmallettstatic inline uint64_t CVMX_NPEI_DMAX_COUNTS(unsigned long offset) 190215976Sjmallett{ 191215976Sjmallett if (!( 192215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) || 193215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))))) 194215976Sjmallett cvmx_warn("CVMX_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset); 195215976Sjmallett return 0x0000000000000450ull + ((offset) & 7) * 16; 196215976Sjmallett} 197215976Sjmallett#else 198215976Sjmallett#define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16) 199215976Sjmallett#endif 200215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 201215976Sjmallettstatic inline uint64_t CVMX_NPEI_DMAX_DBELL(unsigned long offset) 202215976Sjmallett{ 203215976Sjmallett if (!( 204215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) || 205215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))))) 206215976Sjmallett cvmx_warn("CVMX_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset); 207215976Sjmallett return 0x00000000000003B0ull + ((offset) & 7) * 16; 208215976Sjmallett} 209215976Sjmallett#else 210215976Sjmallett#define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16) 211215976Sjmallett#endif 212215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 213215976Sjmallettstatic inline uint64_t CVMX_NPEI_DMAX_IBUFF_SADDR(unsigned long offset) 214215976Sjmallett{ 215215976Sjmallett if (!( 216215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) || 217215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))))) 218215976Sjmallett cvmx_warn("CVMX_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset); 219215976Sjmallett return 0x0000000000000400ull + ((offset) & 7) * 16; 220215976Sjmallett} 221215976Sjmallett#else 222215976Sjmallett#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16) 223215976Sjmallett#endif 224215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 225215976Sjmallettstatic inline uint64_t CVMX_NPEI_DMAX_NADDR(unsigned long offset) 226215976Sjmallett{ 227215976Sjmallett if (!( 228215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) || 229215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))))) 230215976Sjmallett cvmx_warn("CVMX_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset); 231215976Sjmallett return 0x00000000000004A0ull + ((offset) & 7) * 16; 232215976Sjmallett} 233215976Sjmallett#else 234215976Sjmallett#define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16) 235215976Sjmallett#endif 236215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 237215976Sjmallett#define CVMX_NPEI_DMA_CNTS CVMX_NPEI_DMA_CNTS_FUNC() 238215976Sjmallettstatic inline uint64_t CVMX_NPEI_DMA_CNTS_FUNC(void) 239215976Sjmallett{ 240215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 241215976Sjmallett cvmx_warn("CVMX_NPEI_DMA_CNTS not supported on this chip\n"); 242215976Sjmallett return 0x00000000000005E0ull; 243215976Sjmallett} 244215976Sjmallett#else 245215976Sjmallett#define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull) 246215976Sjmallett#endif 247215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 248215976Sjmallett#define CVMX_NPEI_DMA_CONTROL CVMX_NPEI_DMA_CONTROL_FUNC() 249215976Sjmallettstatic inline uint64_t CVMX_NPEI_DMA_CONTROL_FUNC(void) 250215976Sjmallett{ 251215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 252215976Sjmallett cvmx_warn("CVMX_NPEI_DMA_CONTROL not supported on this chip\n"); 253215976Sjmallett return 0x00000000000003A0ull; 254215976Sjmallett} 255215976Sjmallett#else 256215976Sjmallett#define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull) 257215976Sjmallett#endif 258215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 259215976Sjmallett#define CVMX_NPEI_DMA_PCIE_REQ_NUM CVMX_NPEI_DMA_PCIE_REQ_NUM_FUNC() 260215976Sjmallettstatic inline uint64_t CVMX_NPEI_DMA_PCIE_REQ_NUM_FUNC(void) 261215976Sjmallett{ 262215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 263215976Sjmallett cvmx_warn("CVMX_NPEI_DMA_PCIE_REQ_NUM not supported on this chip\n"); 264215976Sjmallett return 0x00000000000005B0ull; 265215976Sjmallett} 266215976Sjmallett#else 267215976Sjmallett#define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull) 268215976Sjmallett#endif 269215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 270215976Sjmallett#define CVMX_NPEI_DMA_STATE1 CVMX_NPEI_DMA_STATE1_FUNC() 271215976Sjmallettstatic inline uint64_t CVMX_NPEI_DMA_STATE1_FUNC(void) 272215976Sjmallett{ 273215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 274215976Sjmallett cvmx_warn("CVMX_NPEI_DMA_STATE1 not supported on this chip\n"); 275215976Sjmallett return 0x00000000000006C0ull; 276215976Sjmallett} 277215976Sjmallett#else 278215976Sjmallett#define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull) 279215976Sjmallett#endif 280215976Sjmallett#define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull) 281215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 282215976Sjmallett#define CVMX_NPEI_DMA_STATE2 CVMX_NPEI_DMA_STATE2_FUNC() 283215976Sjmallettstatic inline uint64_t CVMX_NPEI_DMA_STATE2_FUNC(void) 284215976Sjmallett{ 285215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 286215976Sjmallett cvmx_warn("CVMX_NPEI_DMA_STATE2 not supported on this chip\n"); 287215976Sjmallett return 0x00000000000006D0ull; 288215976Sjmallett} 289215976Sjmallett#else 290215976Sjmallett#define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull) 291215976Sjmallett#endif 292215976Sjmallett#define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull) 293215976Sjmallett#define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull) 294215976Sjmallett#define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull) 295215976Sjmallett#define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull) 296215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 297215976Sjmallett#define CVMX_NPEI_INT_A_ENB CVMX_NPEI_INT_A_ENB_FUNC() 298215976Sjmallettstatic inline uint64_t CVMX_NPEI_INT_A_ENB_FUNC(void) 299215976Sjmallett{ 300215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 301215976Sjmallett cvmx_warn("CVMX_NPEI_INT_A_ENB not supported on this chip\n"); 302215976Sjmallett return 0x0000000000000560ull; 303215976Sjmallett} 304215976Sjmallett#else 305215976Sjmallett#define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull) 306215976Sjmallett#endif 307215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 308215976Sjmallett#define CVMX_NPEI_INT_A_ENB2 CVMX_NPEI_INT_A_ENB2_FUNC() 309215976Sjmallettstatic inline uint64_t CVMX_NPEI_INT_A_ENB2_FUNC(void) 310215976Sjmallett{ 311215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 312215976Sjmallett cvmx_warn("CVMX_NPEI_INT_A_ENB2 not supported on this chip\n"); 313215976Sjmallett return 0x0000000000003CE0ull; 314215976Sjmallett} 315215976Sjmallett#else 316215976Sjmallett#define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull) 317215976Sjmallett#endif 318215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 319215976Sjmallett#define CVMX_NPEI_INT_A_SUM CVMX_NPEI_INT_A_SUM_FUNC() 320215976Sjmallettstatic inline uint64_t CVMX_NPEI_INT_A_SUM_FUNC(void) 321215976Sjmallett{ 322215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 323215976Sjmallett cvmx_warn("CVMX_NPEI_INT_A_SUM not supported on this chip\n"); 324215976Sjmallett return 0x0000000000000550ull; 325215976Sjmallett} 326215976Sjmallett#else 327215976Sjmallett#define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull) 328215976Sjmallett#endif 329215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 330215976Sjmallett#define CVMX_NPEI_INT_ENB CVMX_NPEI_INT_ENB_FUNC() 331215976Sjmallettstatic inline uint64_t CVMX_NPEI_INT_ENB_FUNC(void) 332215976Sjmallett{ 333215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 334215976Sjmallett cvmx_warn("CVMX_NPEI_INT_ENB not supported on this chip\n"); 335215976Sjmallett return 0x0000000000000540ull; 336215976Sjmallett} 337215976Sjmallett#else 338215976Sjmallett#define CVMX_NPEI_INT_ENB (0x0000000000000540ull) 339215976Sjmallett#endif 340215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 341215976Sjmallett#define CVMX_NPEI_INT_ENB2 CVMX_NPEI_INT_ENB2_FUNC() 342215976Sjmallettstatic inline uint64_t CVMX_NPEI_INT_ENB2_FUNC(void) 343215976Sjmallett{ 344215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 345215976Sjmallett cvmx_warn("CVMX_NPEI_INT_ENB2 not supported on this chip\n"); 346215976Sjmallett return 0x0000000000003CD0ull; 347215976Sjmallett} 348215976Sjmallett#else 349215976Sjmallett#define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull) 350215976Sjmallett#endif 351215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 352215976Sjmallett#define CVMX_NPEI_INT_INFO CVMX_NPEI_INT_INFO_FUNC() 353215976Sjmallettstatic inline uint64_t CVMX_NPEI_INT_INFO_FUNC(void) 354215976Sjmallett{ 355215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 356215976Sjmallett cvmx_warn("CVMX_NPEI_INT_INFO not supported on this chip\n"); 357215976Sjmallett return 0x0000000000000590ull; 358215976Sjmallett} 359215976Sjmallett#else 360215976Sjmallett#define CVMX_NPEI_INT_INFO (0x0000000000000590ull) 361215976Sjmallett#endif 362215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 363215976Sjmallett#define CVMX_NPEI_INT_SUM CVMX_NPEI_INT_SUM_FUNC() 364215976Sjmallettstatic inline uint64_t CVMX_NPEI_INT_SUM_FUNC(void) 365215976Sjmallett{ 366215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 367215976Sjmallett cvmx_warn("CVMX_NPEI_INT_SUM not supported on this chip\n"); 368215976Sjmallett return 0x0000000000000530ull; 369215976Sjmallett} 370215976Sjmallett#else 371215976Sjmallett#define CVMX_NPEI_INT_SUM (0x0000000000000530ull) 372215976Sjmallett#endif 373215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 374215976Sjmallett#define CVMX_NPEI_INT_SUM2 CVMX_NPEI_INT_SUM2_FUNC() 375215976Sjmallettstatic inline uint64_t CVMX_NPEI_INT_SUM2_FUNC(void) 376215976Sjmallett{ 377215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 378215976Sjmallett cvmx_warn("CVMX_NPEI_INT_SUM2 not supported on this chip\n"); 379215976Sjmallett return 0x0000000000003CC0ull; 380215976Sjmallett} 381215976Sjmallett#else 382215976Sjmallett#define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull) 383215976Sjmallett#endif 384215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 385215976Sjmallett#define CVMX_NPEI_LAST_WIN_RDATA0 CVMX_NPEI_LAST_WIN_RDATA0_FUNC() 386215976Sjmallettstatic inline uint64_t CVMX_NPEI_LAST_WIN_RDATA0_FUNC(void) 387215976Sjmallett{ 388215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 389215976Sjmallett cvmx_warn("CVMX_NPEI_LAST_WIN_RDATA0 not supported on this chip\n"); 390215976Sjmallett return 0x0000000000000600ull; 391215976Sjmallett} 392215976Sjmallett#else 393215976Sjmallett#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull) 394215976Sjmallett#endif 395215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 396215976Sjmallett#define CVMX_NPEI_LAST_WIN_RDATA1 CVMX_NPEI_LAST_WIN_RDATA1_FUNC() 397215976Sjmallettstatic inline uint64_t CVMX_NPEI_LAST_WIN_RDATA1_FUNC(void) 398215976Sjmallett{ 399215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 400215976Sjmallett cvmx_warn("CVMX_NPEI_LAST_WIN_RDATA1 not supported on this chip\n"); 401215976Sjmallett return 0x0000000000000610ull; 402215976Sjmallett} 403215976Sjmallett#else 404215976Sjmallett#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull) 405215976Sjmallett#endif 406215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 407215976Sjmallett#define CVMX_NPEI_MEM_ACCESS_CTL CVMX_NPEI_MEM_ACCESS_CTL_FUNC() 408215976Sjmallettstatic inline uint64_t CVMX_NPEI_MEM_ACCESS_CTL_FUNC(void) 409215976Sjmallett{ 410215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 411215976Sjmallett cvmx_warn("CVMX_NPEI_MEM_ACCESS_CTL not supported on this chip\n"); 412215976Sjmallett return 0x00000000000004F0ull; 413215976Sjmallett} 414215976Sjmallett#else 415215976Sjmallett#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull) 416215976Sjmallett#endif 417215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 418215976Sjmallettstatic inline uint64_t CVMX_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset) 419215976Sjmallett{ 420215976Sjmallett if (!( 421215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27)))) || 422215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27)))))) 423215976Sjmallett cvmx_warn("CVMX_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset); 424232812Sjmallett return 0x0000000000000280ull + ((offset) & 31) * 16 - 16*12; 425215976Sjmallett} 426215976Sjmallett#else 427232812Sjmallett#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12) 428215976Sjmallett#endif 429215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430215976Sjmallett#define CVMX_NPEI_MSI_ENB0 CVMX_NPEI_MSI_ENB0_FUNC() 431215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_ENB0_FUNC(void) 432215976Sjmallett{ 433215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 434215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_ENB0 not supported on this chip\n"); 435215976Sjmallett return 0x0000000000003C50ull; 436215976Sjmallett} 437215976Sjmallett#else 438215976Sjmallett#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull) 439215976Sjmallett#endif 440215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 441215976Sjmallett#define CVMX_NPEI_MSI_ENB1 CVMX_NPEI_MSI_ENB1_FUNC() 442215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_ENB1_FUNC(void) 443215976Sjmallett{ 444215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 445215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_ENB1 not supported on this chip\n"); 446215976Sjmallett return 0x0000000000003C60ull; 447215976Sjmallett} 448215976Sjmallett#else 449215976Sjmallett#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull) 450215976Sjmallett#endif 451215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452215976Sjmallett#define CVMX_NPEI_MSI_ENB2 CVMX_NPEI_MSI_ENB2_FUNC() 453215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_ENB2_FUNC(void) 454215976Sjmallett{ 455215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 456215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_ENB2 not supported on this chip\n"); 457215976Sjmallett return 0x0000000000003C70ull; 458215976Sjmallett} 459215976Sjmallett#else 460215976Sjmallett#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull) 461215976Sjmallett#endif 462215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 463215976Sjmallett#define CVMX_NPEI_MSI_ENB3 CVMX_NPEI_MSI_ENB3_FUNC() 464215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_ENB3_FUNC(void) 465215976Sjmallett{ 466215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 467215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_ENB3 not supported on this chip\n"); 468215976Sjmallett return 0x0000000000003C80ull; 469215976Sjmallett} 470215976Sjmallett#else 471215976Sjmallett#define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull) 472215976Sjmallett#endif 473215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 474215976Sjmallett#define CVMX_NPEI_MSI_RCV0 CVMX_NPEI_MSI_RCV0_FUNC() 475215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_RCV0_FUNC(void) 476215976Sjmallett{ 477215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 478215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_RCV0 not supported on this chip\n"); 479215976Sjmallett return 0x0000000000003C10ull; 480215976Sjmallett} 481215976Sjmallett#else 482215976Sjmallett#define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull) 483215976Sjmallett#endif 484215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485215976Sjmallett#define CVMX_NPEI_MSI_RCV1 CVMX_NPEI_MSI_RCV1_FUNC() 486215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_RCV1_FUNC(void) 487215976Sjmallett{ 488215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 489215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_RCV1 not supported on this chip\n"); 490215976Sjmallett return 0x0000000000003C20ull; 491215976Sjmallett} 492215976Sjmallett#else 493215976Sjmallett#define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull) 494215976Sjmallett#endif 495215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 496215976Sjmallett#define CVMX_NPEI_MSI_RCV2 CVMX_NPEI_MSI_RCV2_FUNC() 497215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_RCV2_FUNC(void) 498215976Sjmallett{ 499215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 500215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_RCV2 not supported on this chip\n"); 501215976Sjmallett return 0x0000000000003C30ull; 502215976Sjmallett} 503215976Sjmallett#else 504215976Sjmallett#define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull) 505215976Sjmallett#endif 506215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 507215976Sjmallett#define CVMX_NPEI_MSI_RCV3 CVMX_NPEI_MSI_RCV3_FUNC() 508215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_RCV3_FUNC(void) 509215976Sjmallett{ 510215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 511215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_RCV3 not supported on this chip\n"); 512215976Sjmallett return 0x0000000000003C40ull; 513215976Sjmallett} 514215976Sjmallett#else 515215976Sjmallett#define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull) 516215976Sjmallett#endif 517215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 518215976Sjmallett#define CVMX_NPEI_MSI_RD_MAP CVMX_NPEI_MSI_RD_MAP_FUNC() 519215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_RD_MAP_FUNC(void) 520215976Sjmallett{ 521215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 522215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_RD_MAP not supported on this chip\n"); 523215976Sjmallett return 0x0000000000003CA0ull; 524215976Sjmallett} 525215976Sjmallett#else 526215976Sjmallett#define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull) 527215976Sjmallett#endif 528215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 529215976Sjmallett#define CVMX_NPEI_MSI_W1C_ENB0 CVMX_NPEI_MSI_W1C_ENB0_FUNC() 530215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_W1C_ENB0_FUNC(void) 531215976Sjmallett{ 532215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 533215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_W1C_ENB0 not supported on this chip\n"); 534215976Sjmallett return 0x0000000000003CF0ull; 535215976Sjmallett} 536215976Sjmallett#else 537215976Sjmallett#define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull) 538215976Sjmallett#endif 539215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 540215976Sjmallett#define CVMX_NPEI_MSI_W1C_ENB1 CVMX_NPEI_MSI_W1C_ENB1_FUNC() 541215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_W1C_ENB1_FUNC(void) 542215976Sjmallett{ 543215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 544215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_W1C_ENB1 not supported on this chip\n"); 545215976Sjmallett return 0x0000000000003D00ull; 546215976Sjmallett} 547215976Sjmallett#else 548215976Sjmallett#define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull) 549215976Sjmallett#endif 550215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551215976Sjmallett#define CVMX_NPEI_MSI_W1C_ENB2 CVMX_NPEI_MSI_W1C_ENB2_FUNC() 552215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_W1C_ENB2_FUNC(void) 553215976Sjmallett{ 554215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 555215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_W1C_ENB2 not supported on this chip\n"); 556215976Sjmallett return 0x0000000000003D10ull; 557215976Sjmallett} 558215976Sjmallett#else 559215976Sjmallett#define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull) 560215976Sjmallett#endif 561215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 562215976Sjmallett#define CVMX_NPEI_MSI_W1C_ENB3 CVMX_NPEI_MSI_W1C_ENB3_FUNC() 563215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_W1C_ENB3_FUNC(void) 564215976Sjmallett{ 565215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 566215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_W1C_ENB3 not supported on this chip\n"); 567215976Sjmallett return 0x0000000000003D20ull; 568215976Sjmallett} 569215976Sjmallett#else 570215976Sjmallett#define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull) 571215976Sjmallett#endif 572215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 573215976Sjmallett#define CVMX_NPEI_MSI_W1S_ENB0 CVMX_NPEI_MSI_W1S_ENB0_FUNC() 574215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_W1S_ENB0_FUNC(void) 575215976Sjmallett{ 576215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 577215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_W1S_ENB0 not supported on this chip\n"); 578215976Sjmallett return 0x0000000000003D30ull; 579215976Sjmallett} 580215976Sjmallett#else 581215976Sjmallett#define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull) 582215976Sjmallett#endif 583215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 584215976Sjmallett#define CVMX_NPEI_MSI_W1S_ENB1 CVMX_NPEI_MSI_W1S_ENB1_FUNC() 585215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_W1S_ENB1_FUNC(void) 586215976Sjmallett{ 587215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 588215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_W1S_ENB1 not supported on this chip\n"); 589215976Sjmallett return 0x0000000000003D40ull; 590215976Sjmallett} 591215976Sjmallett#else 592215976Sjmallett#define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull) 593215976Sjmallett#endif 594215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 595215976Sjmallett#define CVMX_NPEI_MSI_W1S_ENB2 CVMX_NPEI_MSI_W1S_ENB2_FUNC() 596215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_W1S_ENB2_FUNC(void) 597215976Sjmallett{ 598215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 599215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_W1S_ENB2 not supported on this chip\n"); 600215976Sjmallett return 0x0000000000003D50ull; 601215976Sjmallett} 602215976Sjmallett#else 603215976Sjmallett#define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull) 604215976Sjmallett#endif 605215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 606215976Sjmallett#define CVMX_NPEI_MSI_W1S_ENB3 CVMX_NPEI_MSI_W1S_ENB3_FUNC() 607215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_W1S_ENB3_FUNC(void) 608215976Sjmallett{ 609215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 610215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_W1S_ENB3 not supported on this chip\n"); 611215976Sjmallett return 0x0000000000003D60ull; 612215976Sjmallett} 613215976Sjmallett#else 614215976Sjmallett#define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull) 615215976Sjmallett#endif 616215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 617215976Sjmallett#define CVMX_NPEI_MSI_WR_MAP CVMX_NPEI_MSI_WR_MAP_FUNC() 618215976Sjmallettstatic inline uint64_t CVMX_NPEI_MSI_WR_MAP_FUNC(void) 619215976Sjmallett{ 620215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 621215976Sjmallett cvmx_warn("CVMX_NPEI_MSI_WR_MAP not supported on this chip\n"); 622215976Sjmallett return 0x0000000000003C90ull; 623215976Sjmallett} 624215976Sjmallett#else 625215976Sjmallett#define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull) 626215976Sjmallett#endif 627215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 628215976Sjmallett#define CVMX_NPEI_PCIE_CREDIT_CNT CVMX_NPEI_PCIE_CREDIT_CNT_FUNC() 629215976Sjmallettstatic inline uint64_t CVMX_NPEI_PCIE_CREDIT_CNT_FUNC(void) 630215976Sjmallett{ 631215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 632215976Sjmallett cvmx_warn("CVMX_NPEI_PCIE_CREDIT_CNT not supported on this chip\n"); 633215976Sjmallett return 0x0000000000003D70ull; 634215976Sjmallett} 635215976Sjmallett#else 636215976Sjmallett#define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull) 637215976Sjmallett#endif 638215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 639215976Sjmallett#define CVMX_NPEI_PCIE_MSI_RCV CVMX_NPEI_PCIE_MSI_RCV_FUNC() 640215976Sjmallettstatic inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_FUNC(void) 641215976Sjmallett{ 642215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 643215976Sjmallett cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV not supported on this chip\n"); 644215976Sjmallett return 0x0000000000003CB0ull; 645215976Sjmallett} 646215976Sjmallett#else 647215976Sjmallett#define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull) 648215976Sjmallett#endif 649215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 650215976Sjmallett#define CVMX_NPEI_PCIE_MSI_RCV_B1 CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC() 651215976Sjmallettstatic inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B1_FUNC(void) 652215976Sjmallett{ 653215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 654215976Sjmallett cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n"); 655215976Sjmallett return 0x0000000000000650ull; 656215976Sjmallett} 657215976Sjmallett#else 658215976Sjmallett#define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull) 659215976Sjmallett#endif 660215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 661215976Sjmallett#define CVMX_NPEI_PCIE_MSI_RCV_B2 CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC() 662215976Sjmallettstatic inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B2_FUNC(void) 663215976Sjmallett{ 664215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 665215976Sjmallett cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n"); 666215976Sjmallett return 0x0000000000000660ull; 667215976Sjmallett} 668215976Sjmallett#else 669215976Sjmallett#define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull) 670215976Sjmallett#endif 671215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 672215976Sjmallett#define CVMX_NPEI_PCIE_MSI_RCV_B3 CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC() 673215976Sjmallettstatic inline uint64_t CVMX_NPEI_PCIE_MSI_RCV_B3_FUNC(void) 674215976Sjmallett{ 675215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 676215976Sjmallett cvmx_warn("CVMX_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n"); 677215976Sjmallett return 0x0000000000000670ull; 678215976Sjmallett} 679215976Sjmallett#else 680215976Sjmallett#define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull) 681215976Sjmallett#endif 682215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 683215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKTX_CNTS(unsigned long offset) 684215976Sjmallett{ 685215976Sjmallett if (!( 686215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 687215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 688215976Sjmallett cvmx_warn("CVMX_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset); 689215976Sjmallett return 0x0000000000002400ull + ((offset) & 31) * 16; 690215976Sjmallett} 691215976Sjmallett#else 692215976Sjmallett#define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16) 693215976Sjmallett#endif 694215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 695215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKTX_INSTR_BADDR(unsigned long offset) 696215976Sjmallett{ 697215976Sjmallett if (!( 698215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 699215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 700215976Sjmallett cvmx_warn("CVMX_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset); 701215976Sjmallett return 0x0000000000002800ull + ((offset) & 31) * 16; 702215976Sjmallett} 703215976Sjmallett#else 704215976Sjmallett#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16) 705215976Sjmallett#endif 706215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 707215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset) 708215976Sjmallett{ 709215976Sjmallett if (!( 710215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 711215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 712215976Sjmallett cvmx_warn("CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset); 713215976Sjmallett return 0x0000000000002C00ull + ((offset) & 31) * 16; 714215976Sjmallett} 715215976Sjmallett#else 716215976Sjmallett#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16) 717215976Sjmallett#endif 718215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 719215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset) 720215976Sjmallett{ 721215976Sjmallett if (!( 722215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 723215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 724215976Sjmallett cvmx_warn("CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset); 725215976Sjmallett return 0x0000000000003000ull + ((offset) & 31) * 16; 726215976Sjmallett} 727215976Sjmallett#else 728215976Sjmallett#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16) 729215976Sjmallett#endif 730215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 731215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKTX_INSTR_HEADER(unsigned long offset) 732215976Sjmallett{ 733215976Sjmallett if (!( 734215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 735215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 736215976Sjmallett cvmx_warn("CVMX_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset); 737215976Sjmallett return 0x0000000000003400ull + ((offset) & 31) * 16; 738215976Sjmallett} 739215976Sjmallett#else 740215976Sjmallett#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16) 741215976Sjmallett#endif 742215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 743215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKTX_IN_BP(unsigned long offset) 744215976Sjmallett{ 745215976Sjmallett if (!( 746215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 747215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 748215976Sjmallett cvmx_warn("CVMX_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset); 749215976Sjmallett return 0x0000000000003800ull + ((offset) & 31) * 16; 750215976Sjmallett} 751215976Sjmallett#else 752215976Sjmallett#define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16) 753215976Sjmallett#endif 754215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 755215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKTX_SLIST_BADDR(unsigned long offset) 756215976Sjmallett{ 757215976Sjmallett if (!( 758215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 759215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 760215976Sjmallett cvmx_warn("CVMX_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset); 761215976Sjmallett return 0x0000000000001400ull + ((offset) & 31) * 16; 762215976Sjmallett} 763215976Sjmallett#else 764215976Sjmallett#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16) 765215976Sjmallett#endif 766215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 767215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset) 768215976Sjmallett{ 769215976Sjmallett if (!( 770215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 771215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 772215976Sjmallett cvmx_warn("CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset); 773215976Sjmallett return 0x0000000000001800ull + ((offset) & 31) * 16; 774215976Sjmallett} 775215976Sjmallett#else 776215976Sjmallett#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16) 777215976Sjmallett#endif 778215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 779215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset) 780215976Sjmallett{ 781215976Sjmallett if (!( 782215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 783215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 784215976Sjmallett cvmx_warn("CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset); 785215976Sjmallett return 0x0000000000001C00ull + ((offset) & 31) * 16; 786215976Sjmallett} 787215976Sjmallett#else 788215976Sjmallett#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16) 789215976Sjmallett#endif 790215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 791215976Sjmallett#define CVMX_NPEI_PKT_CNT_INT CVMX_NPEI_PKT_CNT_INT_FUNC() 792215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_CNT_INT_FUNC(void) 793215976Sjmallett{ 794215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 795215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_CNT_INT not supported on this chip\n"); 796215976Sjmallett return 0x0000000000001110ull; 797215976Sjmallett} 798215976Sjmallett#else 799215976Sjmallett#define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull) 800215976Sjmallett#endif 801215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 802215976Sjmallett#define CVMX_NPEI_PKT_CNT_INT_ENB CVMX_NPEI_PKT_CNT_INT_ENB_FUNC() 803215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_CNT_INT_ENB_FUNC(void) 804215976Sjmallett{ 805215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 806215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_CNT_INT_ENB not supported on this chip\n"); 807215976Sjmallett return 0x0000000000001130ull; 808215976Sjmallett} 809215976Sjmallett#else 810215976Sjmallett#define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull) 811215976Sjmallett#endif 812215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 813215976Sjmallett#define CVMX_NPEI_PKT_DATA_OUT_ES CVMX_NPEI_PKT_DATA_OUT_ES_FUNC() 814215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ES_FUNC(void) 815215976Sjmallett{ 816215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 817215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_ES not supported on this chip\n"); 818215976Sjmallett return 0x00000000000010B0ull; 819215976Sjmallett} 820215976Sjmallett#else 821215976Sjmallett#define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull) 822215976Sjmallett#endif 823215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 824215976Sjmallett#define CVMX_NPEI_PKT_DATA_OUT_NS CVMX_NPEI_PKT_DATA_OUT_NS_FUNC() 825215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_DATA_OUT_NS_FUNC(void) 826215976Sjmallett{ 827215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 828215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_NS not supported on this chip\n"); 829215976Sjmallett return 0x00000000000010A0ull; 830215976Sjmallett} 831215976Sjmallett#else 832215976Sjmallett#define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull) 833215976Sjmallett#endif 834215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 835215976Sjmallett#define CVMX_NPEI_PKT_DATA_OUT_ROR CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC() 836215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_DATA_OUT_ROR_FUNC(void) 837215976Sjmallett{ 838215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 839215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n"); 840215976Sjmallett return 0x0000000000001090ull; 841215976Sjmallett} 842215976Sjmallett#else 843215976Sjmallett#define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull) 844215976Sjmallett#endif 845215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 846215976Sjmallett#define CVMX_NPEI_PKT_DPADDR CVMX_NPEI_PKT_DPADDR_FUNC() 847215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_DPADDR_FUNC(void) 848215976Sjmallett{ 849215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 850215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_DPADDR not supported on this chip\n"); 851215976Sjmallett return 0x0000000000001080ull; 852215976Sjmallett} 853215976Sjmallett#else 854215976Sjmallett#define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull) 855215976Sjmallett#endif 856215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 857215976Sjmallett#define CVMX_NPEI_PKT_INPUT_CONTROL CVMX_NPEI_PKT_INPUT_CONTROL_FUNC() 858215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_INPUT_CONTROL_FUNC(void) 859215976Sjmallett{ 860215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 861215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_INPUT_CONTROL not supported on this chip\n"); 862215976Sjmallett return 0x0000000000001150ull; 863215976Sjmallett} 864215976Sjmallett#else 865215976Sjmallett#define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull) 866215976Sjmallett#endif 867215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 868215976Sjmallett#define CVMX_NPEI_PKT_INSTR_ENB CVMX_NPEI_PKT_INSTR_ENB_FUNC() 869215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_INSTR_ENB_FUNC(void) 870215976Sjmallett{ 871215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 872215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_INSTR_ENB not supported on this chip\n"); 873215976Sjmallett return 0x0000000000001000ull; 874215976Sjmallett} 875215976Sjmallett#else 876215976Sjmallett#define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull) 877215976Sjmallett#endif 878215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 879215976Sjmallett#define CVMX_NPEI_PKT_INSTR_RD_SIZE CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC() 880215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_INSTR_RD_SIZE_FUNC(void) 881215976Sjmallett{ 882215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 883215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n"); 884215976Sjmallett return 0x0000000000001190ull; 885215976Sjmallett} 886215976Sjmallett#else 887215976Sjmallett#define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull) 888215976Sjmallett#endif 889215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 890215976Sjmallett#define CVMX_NPEI_PKT_INSTR_SIZE CVMX_NPEI_PKT_INSTR_SIZE_FUNC() 891215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_INSTR_SIZE_FUNC(void) 892215976Sjmallett{ 893215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 894215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_INSTR_SIZE not supported on this chip\n"); 895215976Sjmallett return 0x0000000000001020ull; 896215976Sjmallett} 897215976Sjmallett#else 898215976Sjmallett#define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull) 899215976Sjmallett#endif 900215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 901215976Sjmallett#define CVMX_NPEI_PKT_INT_LEVELS CVMX_NPEI_PKT_INT_LEVELS_FUNC() 902215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_INT_LEVELS_FUNC(void) 903215976Sjmallett{ 904215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 905215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_INT_LEVELS not supported on this chip\n"); 906215976Sjmallett return 0x0000000000001100ull; 907215976Sjmallett} 908215976Sjmallett#else 909215976Sjmallett#define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull) 910215976Sjmallett#endif 911215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 912215976Sjmallett#define CVMX_NPEI_PKT_IN_BP CVMX_NPEI_PKT_IN_BP_FUNC() 913215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_IN_BP_FUNC(void) 914215976Sjmallett{ 915215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 916215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_IN_BP not supported on this chip\n"); 917215976Sjmallett return 0x00000000000006B0ull; 918215976Sjmallett} 919215976Sjmallett#else 920215976Sjmallett#define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull) 921215976Sjmallett#endif 922215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 923215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset) 924215976Sjmallett{ 925215976Sjmallett if (!( 926215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 927215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 928215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset); 929215976Sjmallett return 0x0000000000002000ull + ((offset) & 31) * 16; 930215976Sjmallett} 931215976Sjmallett#else 932215976Sjmallett#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16) 933215976Sjmallett#endif 934215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 935215976Sjmallett#define CVMX_NPEI_PKT_IN_INSTR_COUNTS CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC() 936215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void) 937215976Sjmallett{ 938215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 939215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n"); 940215976Sjmallett return 0x00000000000006A0ull; 941215976Sjmallett} 942215976Sjmallett#else 943215976Sjmallett#define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull) 944215976Sjmallett#endif 945215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 946215976Sjmallett#define CVMX_NPEI_PKT_IN_PCIE_PORT CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC() 947215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_IN_PCIE_PORT_FUNC(void) 948215976Sjmallett{ 949215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 950215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n"); 951215976Sjmallett return 0x00000000000011A0ull; 952215976Sjmallett} 953215976Sjmallett#else 954215976Sjmallett#define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull) 955215976Sjmallett#endif 956215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 957215976Sjmallett#define CVMX_NPEI_PKT_IPTR CVMX_NPEI_PKT_IPTR_FUNC() 958215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_IPTR_FUNC(void) 959215976Sjmallett{ 960215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 961215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_IPTR not supported on this chip\n"); 962215976Sjmallett return 0x0000000000001070ull; 963215976Sjmallett} 964215976Sjmallett#else 965215976Sjmallett#define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull) 966215976Sjmallett#endif 967215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 968215976Sjmallett#define CVMX_NPEI_PKT_OUTPUT_WMARK CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC() 969215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_OUTPUT_WMARK_FUNC(void) 970215976Sjmallett{ 971215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 972215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n"); 973215976Sjmallett return 0x0000000000001160ull; 974215976Sjmallett} 975215976Sjmallett#else 976215976Sjmallett#define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull) 977215976Sjmallett#endif 978215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 979215976Sjmallett#define CVMX_NPEI_PKT_OUT_BMODE CVMX_NPEI_PKT_OUT_BMODE_FUNC() 980215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_OUT_BMODE_FUNC(void) 981215976Sjmallett{ 982215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 983215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_OUT_BMODE not supported on this chip\n"); 984215976Sjmallett return 0x00000000000010D0ull; 985215976Sjmallett} 986215976Sjmallett#else 987215976Sjmallett#define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull) 988215976Sjmallett#endif 989215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 990215976Sjmallett#define CVMX_NPEI_PKT_OUT_ENB CVMX_NPEI_PKT_OUT_ENB_FUNC() 991215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_OUT_ENB_FUNC(void) 992215976Sjmallett{ 993215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 994215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_OUT_ENB not supported on this chip\n"); 995215976Sjmallett return 0x0000000000001010ull; 996215976Sjmallett} 997215976Sjmallett#else 998215976Sjmallett#define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull) 999215976Sjmallett#endif 1000215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1001215976Sjmallett#define CVMX_NPEI_PKT_PCIE_PORT CVMX_NPEI_PKT_PCIE_PORT_FUNC() 1002215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_PCIE_PORT_FUNC(void) 1003215976Sjmallett{ 1004215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1005215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_PCIE_PORT not supported on this chip\n"); 1006215976Sjmallett return 0x00000000000010E0ull; 1007215976Sjmallett} 1008215976Sjmallett#else 1009215976Sjmallett#define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull) 1010215976Sjmallett#endif 1011215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1012215976Sjmallett#define CVMX_NPEI_PKT_PORT_IN_RST CVMX_NPEI_PKT_PORT_IN_RST_FUNC() 1013215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_PORT_IN_RST_FUNC(void) 1014215976Sjmallett{ 1015215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1016215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_PORT_IN_RST not supported on this chip\n"); 1017215976Sjmallett return 0x0000000000000690ull; 1018215976Sjmallett} 1019215976Sjmallett#else 1020215976Sjmallett#define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull) 1021215976Sjmallett#endif 1022215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1023215976Sjmallett#define CVMX_NPEI_PKT_SLIST_ES CVMX_NPEI_PKT_SLIST_ES_FUNC() 1024215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_SLIST_ES_FUNC(void) 1025215976Sjmallett{ 1026215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1027215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_SLIST_ES not supported on this chip\n"); 1028215976Sjmallett return 0x0000000000001050ull; 1029215976Sjmallett} 1030215976Sjmallett#else 1031215976Sjmallett#define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull) 1032215976Sjmallett#endif 1033215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1034215976Sjmallett#define CVMX_NPEI_PKT_SLIST_ID_SIZE CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC() 1035215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_SLIST_ID_SIZE_FUNC(void) 1036215976Sjmallett{ 1037215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1038215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n"); 1039215976Sjmallett return 0x0000000000001180ull; 1040215976Sjmallett} 1041215976Sjmallett#else 1042215976Sjmallett#define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull) 1043215976Sjmallett#endif 1044215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1045215976Sjmallett#define CVMX_NPEI_PKT_SLIST_NS CVMX_NPEI_PKT_SLIST_NS_FUNC() 1046215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_SLIST_NS_FUNC(void) 1047215976Sjmallett{ 1048215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1049215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_SLIST_NS not supported on this chip\n"); 1050215976Sjmallett return 0x0000000000001040ull; 1051215976Sjmallett} 1052215976Sjmallett#else 1053215976Sjmallett#define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull) 1054215976Sjmallett#endif 1055215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1056215976Sjmallett#define CVMX_NPEI_PKT_SLIST_ROR CVMX_NPEI_PKT_SLIST_ROR_FUNC() 1057215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_SLIST_ROR_FUNC(void) 1058215976Sjmallett{ 1059215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1060215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_SLIST_ROR not supported on this chip\n"); 1061215976Sjmallett return 0x0000000000001030ull; 1062215976Sjmallett} 1063215976Sjmallett#else 1064215976Sjmallett#define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull) 1065215976Sjmallett#endif 1066215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1067215976Sjmallett#define CVMX_NPEI_PKT_TIME_INT CVMX_NPEI_PKT_TIME_INT_FUNC() 1068215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_TIME_INT_FUNC(void) 1069215976Sjmallett{ 1070215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1071215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_TIME_INT not supported on this chip\n"); 1072215976Sjmallett return 0x0000000000001120ull; 1073215976Sjmallett} 1074215976Sjmallett#else 1075215976Sjmallett#define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull) 1076215976Sjmallett#endif 1077215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1078215976Sjmallett#define CVMX_NPEI_PKT_TIME_INT_ENB CVMX_NPEI_PKT_TIME_INT_ENB_FUNC() 1079215976Sjmallettstatic inline uint64_t CVMX_NPEI_PKT_TIME_INT_ENB_FUNC(void) 1080215976Sjmallett{ 1081215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1082215976Sjmallett cvmx_warn("CVMX_NPEI_PKT_TIME_INT_ENB not supported on this chip\n"); 1083215976Sjmallett return 0x0000000000001140ull; 1084215976Sjmallett} 1085215976Sjmallett#else 1086215976Sjmallett#define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull) 1087215976Sjmallett#endif 1088215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1089215976Sjmallett#define CVMX_NPEI_RSL_INT_BLOCKS CVMX_NPEI_RSL_INT_BLOCKS_FUNC() 1090215976Sjmallettstatic inline uint64_t CVMX_NPEI_RSL_INT_BLOCKS_FUNC(void) 1091215976Sjmallett{ 1092215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1093215976Sjmallett cvmx_warn("CVMX_NPEI_RSL_INT_BLOCKS not supported on this chip\n"); 1094215976Sjmallett return 0x0000000000000520ull; 1095215976Sjmallett} 1096215976Sjmallett#else 1097215976Sjmallett#define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull) 1098215976Sjmallett#endif 1099215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1100215976Sjmallett#define CVMX_NPEI_SCRATCH_1 CVMX_NPEI_SCRATCH_1_FUNC() 1101215976Sjmallettstatic inline uint64_t CVMX_NPEI_SCRATCH_1_FUNC(void) 1102215976Sjmallett{ 1103215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1104215976Sjmallett cvmx_warn("CVMX_NPEI_SCRATCH_1 not supported on this chip\n"); 1105215976Sjmallett return 0x0000000000000270ull; 1106215976Sjmallett} 1107215976Sjmallett#else 1108215976Sjmallett#define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull) 1109215976Sjmallett#endif 1110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1111215976Sjmallett#define CVMX_NPEI_STATE1 CVMX_NPEI_STATE1_FUNC() 1112215976Sjmallettstatic inline uint64_t CVMX_NPEI_STATE1_FUNC(void) 1113215976Sjmallett{ 1114215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1115215976Sjmallett cvmx_warn("CVMX_NPEI_STATE1 not supported on this chip\n"); 1116215976Sjmallett return 0x0000000000000620ull; 1117215976Sjmallett} 1118215976Sjmallett#else 1119215976Sjmallett#define CVMX_NPEI_STATE1 (0x0000000000000620ull) 1120215976Sjmallett#endif 1121215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1122215976Sjmallett#define CVMX_NPEI_STATE2 CVMX_NPEI_STATE2_FUNC() 1123215976Sjmallettstatic inline uint64_t CVMX_NPEI_STATE2_FUNC(void) 1124215976Sjmallett{ 1125215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1126215976Sjmallett cvmx_warn("CVMX_NPEI_STATE2 not supported on this chip\n"); 1127215976Sjmallett return 0x0000000000000630ull; 1128215976Sjmallett} 1129215976Sjmallett#else 1130215976Sjmallett#define CVMX_NPEI_STATE2 (0x0000000000000630ull) 1131215976Sjmallett#endif 1132215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1133215976Sjmallett#define CVMX_NPEI_STATE3 CVMX_NPEI_STATE3_FUNC() 1134215976Sjmallettstatic inline uint64_t CVMX_NPEI_STATE3_FUNC(void) 1135215976Sjmallett{ 1136215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1137215976Sjmallett cvmx_warn("CVMX_NPEI_STATE3 not supported on this chip\n"); 1138215976Sjmallett return 0x0000000000000640ull; 1139215976Sjmallett} 1140215976Sjmallett#else 1141215976Sjmallett#define CVMX_NPEI_STATE3 (0x0000000000000640ull) 1142215976Sjmallett#endif 1143215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1144215976Sjmallett#define CVMX_NPEI_WINDOW_CTL CVMX_NPEI_WINDOW_CTL_FUNC() 1145215976Sjmallettstatic inline uint64_t CVMX_NPEI_WINDOW_CTL_FUNC(void) 1146215976Sjmallett{ 1147215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1148215976Sjmallett cvmx_warn("CVMX_NPEI_WINDOW_CTL not supported on this chip\n"); 1149215976Sjmallett return 0x0000000000000380ull; 1150215976Sjmallett} 1151215976Sjmallett#else 1152215976Sjmallett#define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull) 1153215976Sjmallett#endif 1154215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1155215976Sjmallett#define CVMX_NPEI_WIN_RD_ADDR CVMX_NPEI_WIN_RD_ADDR_FUNC() 1156215976Sjmallettstatic inline uint64_t CVMX_NPEI_WIN_RD_ADDR_FUNC(void) 1157215976Sjmallett{ 1158215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1159215976Sjmallett cvmx_warn("CVMX_NPEI_WIN_RD_ADDR not supported on this chip\n"); 1160215976Sjmallett return 0x0000000000000210ull; 1161215976Sjmallett} 1162215976Sjmallett#else 1163215976Sjmallett#define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull) 1164215976Sjmallett#endif 1165215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1166215976Sjmallett#define CVMX_NPEI_WIN_RD_DATA CVMX_NPEI_WIN_RD_DATA_FUNC() 1167215976Sjmallettstatic inline uint64_t CVMX_NPEI_WIN_RD_DATA_FUNC(void) 1168215976Sjmallett{ 1169215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1170215976Sjmallett cvmx_warn("CVMX_NPEI_WIN_RD_DATA not supported on this chip\n"); 1171215976Sjmallett return 0x0000000000000240ull; 1172215976Sjmallett} 1173215976Sjmallett#else 1174215976Sjmallett#define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull) 1175215976Sjmallett#endif 1176215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1177215976Sjmallett#define CVMX_NPEI_WIN_WR_ADDR CVMX_NPEI_WIN_WR_ADDR_FUNC() 1178215976Sjmallettstatic inline uint64_t CVMX_NPEI_WIN_WR_ADDR_FUNC(void) 1179215976Sjmallett{ 1180215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1181215976Sjmallett cvmx_warn("CVMX_NPEI_WIN_WR_ADDR not supported on this chip\n"); 1182215976Sjmallett return 0x0000000000000200ull; 1183215976Sjmallett} 1184215976Sjmallett#else 1185215976Sjmallett#define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull) 1186215976Sjmallett#endif 1187215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1188215976Sjmallett#define CVMX_NPEI_WIN_WR_DATA CVMX_NPEI_WIN_WR_DATA_FUNC() 1189215976Sjmallettstatic inline uint64_t CVMX_NPEI_WIN_WR_DATA_FUNC(void) 1190215976Sjmallett{ 1191215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1192215976Sjmallett cvmx_warn("CVMX_NPEI_WIN_WR_DATA not supported on this chip\n"); 1193215976Sjmallett return 0x0000000000000220ull; 1194215976Sjmallett} 1195215976Sjmallett#else 1196215976Sjmallett#define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull) 1197215976Sjmallett#endif 1198215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1199215976Sjmallett#define CVMX_NPEI_WIN_WR_MASK CVMX_NPEI_WIN_WR_MASK_FUNC() 1200215976Sjmallettstatic inline uint64_t CVMX_NPEI_WIN_WR_MASK_FUNC(void) 1201215976Sjmallett{ 1202215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1203215976Sjmallett cvmx_warn("CVMX_NPEI_WIN_WR_MASK not supported on this chip\n"); 1204215976Sjmallett return 0x0000000000000230ull; 1205215976Sjmallett} 1206215976Sjmallett#else 1207215976Sjmallett#define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull) 1208215976Sjmallett#endif 1209215976Sjmallett 1210215976Sjmallett/** 1211215976Sjmallett * cvmx_npei_bar1_index# 1212215976Sjmallett * 1213215976Sjmallett * Total Address is 16Kb; 0x0000 - 0x3fff, 0x000 - 0x7fe(Reg, every other 8B) 1214215976Sjmallett * 1215215976Sjmallett * General 5kb; 0x0000 - 0x13ff, 0x000 - 0x27e(Reg-General) 1216215976Sjmallett * PktMem 10Kb; 0x1400 - 0x3bff, 0x280 - 0x77e(Reg-General-Packet) 1217215976Sjmallett * Rsvd 1Kb; 0x3c00 - 0x3fff, 0x780 - 0x7fe(Reg-NCB Only Mode) 1218215976Sjmallett * == NPEI_PKT_CNT_INT_ENB[PORT] 1219215976Sjmallett * == NPEI_PKT_TIME_INT_ENB[PORT] 1220215976Sjmallett * == NPEI_PKT_CNT_INT[PORT] 1221215976Sjmallett * == NPEI_PKT_TIME_INT[PORT] 1222215976Sjmallett * == NPEI_PKT_PCIE_PORT[PP] 1223215976Sjmallett * == NPEI_PKT_SLIST_ROR[ROR] 1224215976Sjmallett * == NPEI_PKT_SLIST_ROR[NSR] ? 1225215976Sjmallett * == NPEI_PKT_SLIST_ES[ES] 1226215976Sjmallett * == NPEI_PKTn_SLIST_BAOFF_DBELL[AOFF] 1227215976Sjmallett * == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL] 1228215976Sjmallett * == NPEI_PKTn_CNTS[CNT] 1229215976Sjmallett * NPEI_CTL_STATUS[OUTn_ENB] == NPEI_PKT_OUT_ENB[ENB] 1230215976Sjmallett * NPEI_BASE_ADDRESS_OUTPUTn[BADDR] == NPEI_PKTn_SLIST_BADDR[ADDR] 1231215976Sjmallett * NPEI_DESC_OUTPUTn[SIZE] == NPEI_PKTn_SLIST_FIFO_RSIZE[RSIZE] 1232215976Sjmallett * NPEI_Pn_DBPAIR_ADDR[NADDR] == NPEI_PKTn_SLIST_BADDR[ADDR] + NPEI_PKTn_SLIST_BAOFF_DBELL[AOFF] 1233215976Sjmallett * NPEI_PKT_CREDITSn[PTR_CNT] == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL] 1234215976Sjmallett * NPEI_P0_PAIR_CNTS[AVAIL] == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL] 1235215976Sjmallett * NPEI_P0_PAIR_CNTS[FCNT] == 1236215976Sjmallett * NPEI_PKTS_SENTn[PKT_CNT] == NPEI_PKTn_CNTS[CNT] 1237215976Sjmallett * NPEI_OUTPUT_CONTROL[Pn_BMODE] == NPEI_PKT_OUT_BMODE[BMODE] 1238215976Sjmallett * NPEI_PKT_CREDITSn[PKT_CNT] == NPEI_PKTn_CNTS[CNT] 1239215976Sjmallett * NPEI_BUFF_SIZE_OUTPUTn[BSIZE] == NPEI_PKT_SLIST_ID_SIZE[BSIZE] 1240215976Sjmallett * NPEI_BUFF_SIZE_OUTPUTn[ISIZE] == NPEI_PKT_SLIST_ID_SIZE[ISIZE] 1241215976Sjmallett * NPEI_OUTPUT_CONTROL[On_CSRM] == NPEI_PKT_DPADDR[DPTR] & NPEI_PKT_OUT_USE_IPTR[PORT] 1242215976Sjmallett * NPEI_OUTPUT_CONTROL[On_ES] == NPEI_PKT_DATA_OUT_ES[ES] 1243215976Sjmallett * NPEI_OUTPUT_CONTROL[On_NS] == NPEI_PKT_DATA_OUT_NS[NSR] ? 1244215976Sjmallett * NPEI_OUTPUT_CONTROL[On_RO] == NPEI_PKT_DATA_OUT_ROR[ROR] 1245215976Sjmallett * NPEI_PKTS_SENT_INT_LEVn[PKT_CNT] == NPEI_PKT_INT_LEVELS[CNT] 1246215976Sjmallett * NPEI_PKTS_SENT_TIMEn[PKT_TIME] == NPEI_PKT_INT_LEVELS[TIME] 1247215976Sjmallett * NPEI_OUTPUT_CONTROL[IPTR_On] == NPEI_PKT_IPTR[IPTR] 1248215976Sjmallett * NPEI_PCIE_PORT_OUTPUT[] == NPEI_PKT_PCIE_PORT[PP] 1249215976Sjmallett * 1250215976Sjmallett * NPEI_BAR1_INDEXX = NPEI BAR1 IndexX Register 1251215976Sjmallett * 1252215976Sjmallett * Contains address index and control bits for access to memory ranges of BAR-1. Index is build from supplied address [25:22]. 1253215976Sjmallett * NPEI_BAR1_INDEX0 through NPEI_BAR1_INDEX15 is used for transactions orginating with PCIE-PORT0 and NPEI_BAR1_INDEX16 1254215976Sjmallett * through NPEI_BAR1_INDEX31 is used for transactions originating with PCIE-PORT1. 1255215976Sjmallett */ 1256232812Sjmallettunion cvmx_npei_bar1_indexx { 1257215976Sjmallett uint32_t u32; 1258232812Sjmallett struct cvmx_npei_bar1_indexx_s { 1259232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1260215976Sjmallett uint32_t reserved_18_31 : 14; 1261215976Sjmallett uint32_t addr_idx : 14; /**< Address bits [35:22] sent to L2C */ 1262215976Sjmallett uint32_t ca : 1; /**< Set '1' when access is not to be cached in L2. */ 1263215976Sjmallett uint32_t end_swp : 2; /**< Endian Swap Mode */ 1264215976Sjmallett uint32_t addr_v : 1; /**< Set '1' when the selected address range is valid. */ 1265215976Sjmallett#else 1266215976Sjmallett uint32_t addr_v : 1; 1267215976Sjmallett uint32_t end_swp : 2; 1268215976Sjmallett uint32_t ca : 1; 1269215976Sjmallett uint32_t addr_idx : 14; 1270215976Sjmallett uint32_t reserved_18_31 : 14; 1271215976Sjmallett#endif 1272215976Sjmallett } s; 1273215976Sjmallett struct cvmx_npei_bar1_indexx_s cn52xx; 1274215976Sjmallett struct cvmx_npei_bar1_indexx_s cn52xxp1; 1275215976Sjmallett struct cvmx_npei_bar1_indexx_s cn56xx; 1276215976Sjmallett struct cvmx_npei_bar1_indexx_s cn56xxp1; 1277215976Sjmallett}; 1278215976Sjmalletttypedef union cvmx_npei_bar1_indexx cvmx_npei_bar1_indexx_t; 1279215976Sjmallett 1280215976Sjmallett/** 1281215976Sjmallett * cvmx_npei_bist_status 1282215976Sjmallett * 1283215976Sjmallett * NPEI_BIST_STATUS = NPI's BIST Status Register 1284215976Sjmallett * 1285215976Sjmallett * Results from BIST runs of NPEI's memories. 1286215976Sjmallett */ 1287232812Sjmallettunion cvmx_npei_bist_status { 1288215976Sjmallett uint64_t u64; 1289232812Sjmallett struct cvmx_npei_bist_status_s { 1290232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1291215976Sjmallett uint64_t pkt_rdf : 1; /**< BIST Status for PKT Read FIFO */ 1292215976Sjmallett uint64_t reserved_60_62 : 3; 1293215976Sjmallett uint64_t pcr_gim : 1; /**< BIST Status for PKT Gather Instr MEM */ 1294215976Sjmallett uint64_t pkt_pif : 1; /**< BIST Status for PKT INB FIFO */ 1295215976Sjmallett uint64_t pcsr_int : 1; /**< BIST Status for PKT pout_int_bstatus */ 1296215976Sjmallett uint64_t pcsr_im : 1; /**< BIST Status for PKT pcsr_instr_mem_bstatus */ 1297215976Sjmallett uint64_t pcsr_cnt : 1; /**< BIST Status for PKT pin_cnt_bstatus */ 1298215976Sjmallett uint64_t pcsr_id : 1; /**< BIST Status for PKT pcsr_in_done_bstatus */ 1299215976Sjmallett uint64_t pcsr_sl : 1; /**< BIST Status for PKT pcsr_slist_bstatus */ 1300215976Sjmallett uint64_t reserved_50_52 : 3; 1301215976Sjmallett uint64_t pkt_ind : 1; /**< BIST Status for PKT Instruction Done MEM */ 1302215976Sjmallett uint64_t pkt_slm : 1; /**< BIST Status for PKT SList MEM */ 1303215976Sjmallett uint64_t reserved_36_47 : 12; 1304215976Sjmallett uint64_t d0_pst : 1; /**< BIST Status for DMA0 Pcie Store */ 1305215976Sjmallett uint64_t d1_pst : 1; /**< BIST Status for DMA1 Pcie Store */ 1306215976Sjmallett uint64_t d2_pst : 1; /**< BIST Status for DMA2 Pcie Store */ 1307215976Sjmallett uint64_t d3_pst : 1; /**< BIST Status for DMA3 Pcie Store */ 1308215976Sjmallett uint64_t reserved_31_31 : 1; 1309215976Sjmallett uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */ 1310215976Sjmallett uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */ 1311215976Sjmallett uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */ 1312215976Sjmallett uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */ 1313215976Sjmallett uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */ 1314215976Sjmallett uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */ 1315215976Sjmallett uint64_t p2n1_po : 1; /**< BIST Status for P2N Port1 P Order */ 1316215976Sjmallett uint64_t p2n1_no : 1; /**< BIST Status for P2N Port1 N Order */ 1317215976Sjmallett uint64_t p2n1_co : 1; /**< BIST Status for P2N Port1 C Order */ 1318215976Sjmallett uint64_t p2n0_po : 1; /**< BIST Status for P2N Port0 P Order */ 1319215976Sjmallett uint64_t p2n0_no : 1; /**< BIST Status for P2N Port0 N Order */ 1320215976Sjmallett uint64_t p2n0_co : 1; /**< BIST Status for P2N Port0 C Order */ 1321215976Sjmallett uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */ 1322215976Sjmallett uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */ 1323215976Sjmallett uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */ 1324215976Sjmallett uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */ 1325215976Sjmallett uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */ 1326215976Sjmallett uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */ 1327215976Sjmallett uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */ 1328215976Sjmallett uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */ 1329215976Sjmallett uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */ 1330215976Sjmallett uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */ 1331215976Sjmallett uint64_t csm0 : 1; /**< BIST Status for CSM0 */ 1332215976Sjmallett uint64_t csm1 : 1; /**< BIST Status for CSM1 */ 1333215976Sjmallett uint64_t dif0 : 1; /**< BIST Status for DMA Instr0 */ 1334215976Sjmallett uint64_t dif1 : 1; /**< BIST Status for DMA Instr0 */ 1335215976Sjmallett uint64_t dif2 : 1; /**< BIST Status for DMA Instr0 */ 1336215976Sjmallett uint64_t dif3 : 1; /**< BIST Status for DMA Instr0 */ 1337215976Sjmallett uint64_t reserved_2_2 : 1; 1338215976Sjmallett uint64_t msi : 1; /**< BIST Status for MSI Memory Map */ 1339215976Sjmallett uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */ 1340215976Sjmallett#else 1341215976Sjmallett uint64_t ncb_cmd : 1; 1342215976Sjmallett uint64_t msi : 1; 1343215976Sjmallett uint64_t reserved_2_2 : 1; 1344215976Sjmallett uint64_t dif3 : 1; 1345215976Sjmallett uint64_t dif2 : 1; 1346215976Sjmallett uint64_t dif1 : 1; 1347215976Sjmallett uint64_t dif0 : 1; 1348215976Sjmallett uint64_t csm1 : 1; 1349215976Sjmallett uint64_t csm0 : 1; 1350215976Sjmallett uint64_t p2n1_p1 : 1; 1351215976Sjmallett uint64_t p2n1_p0 : 1; 1352215976Sjmallett uint64_t p2n1_n : 1; 1353215976Sjmallett uint64_t p2n1_c1 : 1; 1354215976Sjmallett uint64_t p2n1_c0 : 1; 1355215976Sjmallett uint64_t p2n0_p1 : 1; 1356215976Sjmallett uint64_t p2n0_p0 : 1; 1357215976Sjmallett uint64_t p2n0_n : 1; 1358215976Sjmallett uint64_t p2n0_c1 : 1; 1359215976Sjmallett uint64_t p2n0_c0 : 1; 1360215976Sjmallett uint64_t p2n0_co : 1; 1361215976Sjmallett uint64_t p2n0_no : 1; 1362215976Sjmallett uint64_t p2n0_po : 1; 1363215976Sjmallett uint64_t p2n1_co : 1; 1364215976Sjmallett uint64_t p2n1_no : 1; 1365215976Sjmallett uint64_t p2n1_po : 1; 1366215976Sjmallett uint64_t cpl_p1 : 1; 1367215976Sjmallett uint64_t cpl_p0 : 1; 1368215976Sjmallett uint64_t n2p1_o : 1; 1369215976Sjmallett uint64_t n2p1_c : 1; 1370215976Sjmallett uint64_t n2p0_o : 1; 1371215976Sjmallett uint64_t n2p0_c : 1; 1372215976Sjmallett uint64_t reserved_31_31 : 1; 1373215976Sjmallett uint64_t d3_pst : 1; 1374215976Sjmallett uint64_t d2_pst : 1; 1375215976Sjmallett uint64_t d1_pst : 1; 1376215976Sjmallett uint64_t d0_pst : 1; 1377215976Sjmallett uint64_t reserved_36_47 : 12; 1378215976Sjmallett uint64_t pkt_slm : 1; 1379215976Sjmallett uint64_t pkt_ind : 1; 1380215976Sjmallett uint64_t reserved_50_52 : 3; 1381215976Sjmallett uint64_t pcsr_sl : 1; 1382215976Sjmallett uint64_t pcsr_id : 1; 1383215976Sjmallett uint64_t pcsr_cnt : 1; 1384215976Sjmallett uint64_t pcsr_im : 1; 1385215976Sjmallett uint64_t pcsr_int : 1; 1386215976Sjmallett uint64_t pkt_pif : 1; 1387215976Sjmallett uint64_t pcr_gim : 1; 1388215976Sjmallett uint64_t reserved_60_62 : 3; 1389215976Sjmallett uint64_t pkt_rdf : 1; 1390215976Sjmallett#endif 1391215976Sjmallett } s; 1392232812Sjmallett struct cvmx_npei_bist_status_cn52xx { 1393232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1394215976Sjmallett uint64_t pkt_rdf : 1; /**< BIST Status for PKT Read FIFO */ 1395215976Sjmallett uint64_t reserved_60_62 : 3; 1396215976Sjmallett uint64_t pcr_gim : 1; /**< BIST Status for PKT Gather Instr MEM */ 1397215976Sjmallett uint64_t pkt_pif : 1; /**< BIST Status for PKT INB FIFO */ 1398215976Sjmallett uint64_t pcsr_int : 1; /**< BIST Status for PKT OUTB Interrupt MEM */ 1399215976Sjmallett uint64_t pcsr_im : 1; /**< BIST Status for PKT CSR Instr MEM */ 1400215976Sjmallett uint64_t pcsr_cnt : 1; /**< BIST Status for PKT INB Count MEM */ 1401215976Sjmallett uint64_t pcsr_id : 1; /**< BIST Status for PKT INB Instr Done MEM */ 1402215976Sjmallett uint64_t pcsr_sl : 1; /**< BIST Status for PKT OUTB SLIST MEM */ 1403215976Sjmallett uint64_t pkt_imem : 1; /**< BIST Status for PKT OUTB IFIFO */ 1404215976Sjmallett uint64_t pkt_pfm : 1; /**< BIST Status for PKT Front MEM */ 1405215976Sjmallett uint64_t pkt_pof : 1; /**< BIST Status for PKT OUTB FIFO */ 1406215976Sjmallett uint64_t reserved_48_49 : 2; 1407215976Sjmallett uint64_t pkt_pop0 : 1; /**< BIST Status for PKT OUTB Slist0 */ 1408215976Sjmallett uint64_t pkt_pop1 : 1; /**< BIST Status for PKT OUTB Slist1 */ 1409215976Sjmallett uint64_t d0_mem : 1; /**< BIST Status for DMA MEM 0 */ 1410215976Sjmallett uint64_t d1_mem : 1; /**< BIST Status for DMA MEM 1 */ 1411215976Sjmallett uint64_t d2_mem : 1; /**< BIST Status for DMA MEM 2 */ 1412215976Sjmallett uint64_t d3_mem : 1; /**< BIST Status for DMA MEM 3 */ 1413215976Sjmallett uint64_t d4_mem : 1; /**< BIST Status for DMA MEM 4 */ 1414215976Sjmallett uint64_t ds_mem : 1; /**< BIST Status for DMA Memory */ 1415215976Sjmallett uint64_t reserved_36_39 : 4; 1416215976Sjmallett uint64_t d0_pst : 1; /**< BIST Status for DMA0 Pcie Store */ 1417215976Sjmallett uint64_t d1_pst : 1; /**< BIST Status for DMA1 Pcie Store */ 1418215976Sjmallett uint64_t d2_pst : 1; /**< BIST Status for DMA2 Pcie Store */ 1419215976Sjmallett uint64_t d3_pst : 1; /**< BIST Status for DMA3 Pcie Store */ 1420215976Sjmallett uint64_t d4_pst : 1; /**< BIST Status for DMA4 Pcie Store */ 1421215976Sjmallett uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */ 1422215976Sjmallett uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */ 1423215976Sjmallett uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */ 1424215976Sjmallett uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */ 1425215976Sjmallett uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */ 1426215976Sjmallett uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */ 1427215976Sjmallett uint64_t p2n1_po : 1; /**< BIST Status for P2N Port1 P Order */ 1428215976Sjmallett uint64_t p2n1_no : 1; /**< BIST Status for P2N Port1 N Order */ 1429215976Sjmallett uint64_t p2n1_co : 1; /**< BIST Status for P2N Port1 C Order */ 1430215976Sjmallett uint64_t p2n0_po : 1; /**< BIST Status for P2N Port0 P Order */ 1431215976Sjmallett uint64_t p2n0_no : 1; /**< BIST Status for P2N Port0 N Order */ 1432215976Sjmallett uint64_t p2n0_co : 1; /**< BIST Status for P2N Port0 C Order */ 1433215976Sjmallett uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */ 1434215976Sjmallett uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */ 1435215976Sjmallett uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */ 1436215976Sjmallett uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */ 1437215976Sjmallett uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */ 1438215976Sjmallett uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */ 1439215976Sjmallett uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */ 1440215976Sjmallett uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */ 1441215976Sjmallett uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */ 1442215976Sjmallett uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */ 1443215976Sjmallett uint64_t csm0 : 1; /**< BIST Status for CSM0 */ 1444215976Sjmallett uint64_t csm1 : 1; /**< BIST Status for CSM1 */ 1445215976Sjmallett uint64_t dif0 : 1; /**< BIST Status for DMA Instr0 */ 1446215976Sjmallett uint64_t dif1 : 1; /**< BIST Status for DMA Instr0 */ 1447215976Sjmallett uint64_t dif2 : 1; /**< BIST Status for DMA Instr0 */ 1448215976Sjmallett uint64_t dif3 : 1; /**< BIST Status for DMA Instr0 */ 1449215976Sjmallett uint64_t dif4 : 1; /**< BIST Status for DMA Instr0 */ 1450215976Sjmallett uint64_t msi : 1; /**< BIST Status for MSI Memory Map */ 1451215976Sjmallett uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */ 1452215976Sjmallett#else 1453215976Sjmallett uint64_t ncb_cmd : 1; 1454215976Sjmallett uint64_t msi : 1; 1455215976Sjmallett uint64_t dif4 : 1; 1456215976Sjmallett uint64_t dif3 : 1; 1457215976Sjmallett uint64_t dif2 : 1; 1458215976Sjmallett uint64_t dif1 : 1; 1459215976Sjmallett uint64_t dif0 : 1; 1460215976Sjmallett uint64_t csm1 : 1; 1461215976Sjmallett uint64_t csm0 : 1; 1462215976Sjmallett uint64_t p2n1_p1 : 1; 1463215976Sjmallett uint64_t p2n1_p0 : 1; 1464215976Sjmallett uint64_t p2n1_n : 1; 1465215976Sjmallett uint64_t p2n1_c1 : 1; 1466215976Sjmallett uint64_t p2n1_c0 : 1; 1467215976Sjmallett uint64_t p2n0_p1 : 1; 1468215976Sjmallett uint64_t p2n0_p0 : 1; 1469215976Sjmallett uint64_t p2n0_n : 1; 1470215976Sjmallett uint64_t p2n0_c1 : 1; 1471215976Sjmallett uint64_t p2n0_c0 : 1; 1472215976Sjmallett uint64_t p2n0_co : 1; 1473215976Sjmallett uint64_t p2n0_no : 1; 1474215976Sjmallett uint64_t p2n0_po : 1; 1475215976Sjmallett uint64_t p2n1_co : 1; 1476215976Sjmallett uint64_t p2n1_no : 1; 1477215976Sjmallett uint64_t p2n1_po : 1; 1478215976Sjmallett uint64_t cpl_p1 : 1; 1479215976Sjmallett uint64_t cpl_p0 : 1; 1480215976Sjmallett uint64_t n2p1_o : 1; 1481215976Sjmallett uint64_t n2p1_c : 1; 1482215976Sjmallett uint64_t n2p0_o : 1; 1483215976Sjmallett uint64_t n2p0_c : 1; 1484215976Sjmallett uint64_t d4_pst : 1; 1485215976Sjmallett uint64_t d3_pst : 1; 1486215976Sjmallett uint64_t d2_pst : 1; 1487215976Sjmallett uint64_t d1_pst : 1; 1488215976Sjmallett uint64_t d0_pst : 1; 1489215976Sjmallett uint64_t reserved_36_39 : 4; 1490215976Sjmallett uint64_t ds_mem : 1; 1491215976Sjmallett uint64_t d4_mem : 1; 1492215976Sjmallett uint64_t d3_mem : 1; 1493215976Sjmallett uint64_t d2_mem : 1; 1494215976Sjmallett uint64_t d1_mem : 1; 1495215976Sjmallett uint64_t d0_mem : 1; 1496215976Sjmallett uint64_t pkt_pop1 : 1; 1497215976Sjmallett uint64_t pkt_pop0 : 1; 1498215976Sjmallett uint64_t reserved_48_49 : 2; 1499215976Sjmallett uint64_t pkt_pof : 1; 1500215976Sjmallett uint64_t pkt_pfm : 1; 1501215976Sjmallett uint64_t pkt_imem : 1; 1502215976Sjmallett uint64_t pcsr_sl : 1; 1503215976Sjmallett uint64_t pcsr_id : 1; 1504215976Sjmallett uint64_t pcsr_cnt : 1; 1505215976Sjmallett uint64_t pcsr_im : 1; 1506215976Sjmallett uint64_t pcsr_int : 1; 1507215976Sjmallett uint64_t pkt_pif : 1; 1508215976Sjmallett uint64_t pcr_gim : 1; 1509215976Sjmallett uint64_t reserved_60_62 : 3; 1510215976Sjmallett uint64_t pkt_rdf : 1; 1511215976Sjmallett#endif 1512215976Sjmallett } cn52xx; 1513232812Sjmallett struct cvmx_npei_bist_status_cn52xxp1 { 1514232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1515215976Sjmallett uint64_t reserved_46_63 : 18; 1516215976Sjmallett uint64_t d0_mem0 : 1; /**< BIST Status for DMA0 Memory */ 1517215976Sjmallett uint64_t d1_mem1 : 1; /**< BIST Status for DMA1 Memory */ 1518215976Sjmallett uint64_t d2_mem2 : 1; /**< BIST Status for DMA2 Memory */ 1519215976Sjmallett uint64_t d3_mem3 : 1; /**< BIST Status for DMA3 Memory */ 1520215976Sjmallett uint64_t dr0_mem : 1; /**< BIST Status for DMA0 Store */ 1521215976Sjmallett uint64_t d0_mem : 1; /**< BIST Status for DMA0 Memory */ 1522215976Sjmallett uint64_t d1_mem : 1; /**< BIST Status for DMA1 Memory */ 1523215976Sjmallett uint64_t d2_mem : 1; /**< BIST Status for DMA2 Memory */ 1524215976Sjmallett uint64_t d3_mem : 1; /**< BIST Status for DMA3 Memory */ 1525215976Sjmallett uint64_t dr1_mem : 1; /**< BIST Status for DMA1 Store */ 1526215976Sjmallett uint64_t d0_pst : 1; /**< BIST Status for DMA0 Pcie Store */ 1527215976Sjmallett uint64_t d1_pst : 1; /**< BIST Status for DMA1 Pcie Store */ 1528215976Sjmallett uint64_t d2_pst : 1; /**< BIST Status for DMA2 Pcie Store */ 1529215976Sjmallett uint64_t d3_pst : 1; /**< BIST Status for DMA3 Pcie Store */ 1530215976Sjmallett uint64_t dr2_mem : 1; /**< BIST Status for DMA2 Store */ 1531215976Sjmallett uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */ 1532215976Sjmallett uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */ 1533215976Sjmallett uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */ 1534215976Sjmallett uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */ 1535215976Sjmallett uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */ 1536215976Sjmallett uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */ 1537215976Sjmallett uint64_t p2n1_po : 1; /**< BIST Status for P2N Port1 P Order */ 1538215976Sjmallett uint64_t p2n1_no : 1; /**< BIST Status for P2N Port1 N Order */ 1539215976Sjmallett uint64_t p2n1_co : 1; /**< BIST Status for P2N Port1 C Order */ 1540215976Sjmallett uint64_t p2n0_po : 1; /**< BIST Status for P2N Port0 P Order */ 1541215976Sjmallett uint64_t p2n0_no : 1; /**< BIST Status for P2N Port0 N Order */ 1542215976Sjmallett uint64_t p2n0_co : 1; /**< BIST Status for P2N Port0 C Order */ 1543215976Sjmallett uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */ 1544215976Sjmallett uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */ 1545215976Sjmallett uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */ 1546215976Sjmallett uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */ 1547215976Sjmallett uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */ 1548215976Sjmallett uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */ 1549215976Sjmallett uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */ 1550215976Sjmallett uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */ 1551215976Sjmallett uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */ 1552215976Sjmallett uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */ 1553215976Sjmallett uint64_t csm0 : 1; /**< BIST Status for CSM0 */ 1554215976Sjmallett uint64_t csm1 : 1; /**< BIST Status for CSM1 */ 1555215976Sjmallett uint64_t dif0 : 1; /**< BIST Status for DMA Instr0 */ 1556215976Sjmallett uint64_t dif1 : 1; /**< BIST Status for DMA Instr0 */ 1557215976Sjmallett uint64_t dif2 : 1; /**< BIST Status for DMA Instr0 */ 1558215976Sjmallett uint64_t dif3 : 1; /**< BIST Status for DMA Instr0 */ 1559215976Sjmallett uint64_t dr3_mem : 1; /**< BIST Status for DMA3 Store */ 1560215976Sjmallett uint64_t msi : 1; /**< BIST Status for MSI Memory Map */ 1561215976Sjmallett uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */ 1562215976Sjmallett#else 1563215976Sjmallett uint64_t ncb_cmd : 1; 1564215976Sjmallett uint64_t msi : 1; 1565215976Sjmallett uint64_t dr3_mem : 1; 1566215976Sjmallett uint64_t dif3 : 1; 1567215976Sjmallett uint64_t dif2 : 1; 1568215976Sjmallett uint64_t dif1 : 1; 1569215976Sjmallett uint64_t dif0 : 1; 1570215976Sjmallett uint64_t csm1 : 1; 1571215976Sjmallett uint64_t csm0 : 1; 1572215976Sjmallett uint64_t p2n1_p1 : 1; 1573215976Sjmallett uint64_t p2n1_p0 : 1; 1574215976Sjmallett uint64_t p2n1_n : 1; 1575215976Sjmallett uint64_t p2n1_c1 : 1; 1576215976Sjmallett uint64_t p2n1_c0 : 1; 1577215976Sjmallett uint64_t p2n0_p1 : 1; 1578215976Sjmallett uint64_t p2n0_p0 : 1; 1579215976Sjmallett uint64_t p2n0_n : 1; 1580215976Sjmallett uint64_t p2n0_c1 : 1; 1581215976Sjmallett uint64_t p2n0_c0 : 1; 1582215976Sjmallett uint64_t p2n0_co : 1; 1583215976Sjmallett uint64_t p2n0_no : 1; 1584215976Sjmallett uint64_t p2n0_po : 1; 1585215976Sjmallett uint64_t p2n1_co : 1; 1586215976Sjmallett uint64_t p2n1_no : 1; 1587215976Sjmallett uint64_t p2n1_po : 1; 1588215976Sjmallett uint64_t cpl_p1 : 1; 1589215976Sjmallett uint64_t cpl_p0 : 1; 1590215976Sjmallett uint64_t n2p1_o : 1; 1591215976Sjmallett uint64_t n2p1_c : 1; 1592215976Sjmallett uint64_t n2p0_o : 1; 1593215976Sjmallett uint64_t n2p0_c : 1; 1594215976Sjmallett uint64_t dr2_mem : 1; 1595215976Sjmallett uint64_t d3_pst : 1; 1596215976Sjmallett uint64_t d2_pst : 1; 1597215976Sjmallett uint64_t d1_pst : 1; 1598215976Sjmallett uint64_t d0_pst : 1; 1599215976Sjmallett uint64_t dr1_mem : 1; 1600215976Sjmallett uint64_t d3_mem : 1; 1601215976Sjmallett uint64_t d2_mem : 1; 1602215976Sjmallett uint64_t d1_mem : 1; 1603215976Sjmallett uint64_t d0_mem : 1; 1604215976Sjmallett uint64_t dr0_mem : 1; 1605215976Sjmallett uint64_t d3_mem3 : 1; 1606215976Sjmallett uint64_t d2_mem2 : 1; 1607215976Sjmallett uint64_t d1_mem1 : 1; 1608215976Sjmallett uint64_t d0_mem0 : 1; 1609215976Sjmallett uint64_t reserved_46_63 : 18; 1610215976Sjmallett#endif 1611215976Sjmallett } cn52xxp1; 1612215976Sjmallett struct cvmx_npei_bist_status_cn52xx cn56xx; 1613232812Sjmallett struct cvmx_npei_bist_status_cn56xxp1 { 1614232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1615215976Sjmallett uint64_t reserved_58_63 : 6; 1616215976Sjmallett uint64_t pcsr_int : 1; /**< BIST Status for PKT pout_int_bstatus */ 1617215976Sjmallett uint64_t pcsr_im : 1; /**< BIST Status for PKT pcsr_instr_mem_bstatus */ 1618215976Sjmallett uint64_t pcsr_cnt : 1; /**< BIST Status for PKT pin_cnt_bstatus */ 1619215976Sjmallett uint64_t pcsr_id : 1; /**< BIST Status for PKT pcsr_in_done_bstatus */ 1620215976Sjmallett uint64_t pcsr_sl : 1; /**< BIST Status for PKT pcsr_slist_bstatus */ 1621215976Sjmallett uint64_t pkt_pout : 1; /**< BIST Status for PKT OUT Count MEM */ 1622215976Sjmallett uint64_t pkt_imem : 1; /**< BIST Status for PKT Instruction MEM */ 1623215976Sjmallett uint64_t pkt_cntm : 1; /**< BIST Status for PKT Count MEM */ 1624215976Sjmallett uint64_t pkt_ind : 1; /**< BIST Status for PKT Instruction Done MEM */ 1625215976Sjmallett uint64_t pkt_slm : 1; /**< BIST Status for PKT SList MEM */ 1626215976Sjmallett uint64_t pkt_odf : 1; /**< BIST Status for PKT Output Data FIFO */ 1627215976Sjmallett uint64_t pkt_oif : 1; /**< BIST Status for PKT Output INFO FIFO */ 1628215976Sjmallett uint64_t pkt_out : 1; /**< BIST Status for PKT Output FIFO */ 1629215976Sjmallett uint64_t pkt_i0 : 1; /**< BIST Status for PKT Instr0 */ 1630215976Sjmallett uint64_t pkt_i1 : 1; /**< BIST Status for PKT Instr1 */ 1631215976Sjmallett uint64_t pkt_s0 : 1; /**< BIST Status for PKT Slist0 */ 1632215976Sjmallett uint64_t pkt_s1 : 1; /**< BIST Status for PKT Slist1 */ 1633215976Sjmallett uint64_t d0_mem : 1; /**< BIST Status for DMA0 Memory */ 1634215976Sjmallett uint64_t d1_mem : 1; /**< BIST Status for DMA1 Memory */ 1635215976Sjmallett uint64_t d2_mem : 1; /**< BIST Status for DMA2 Memory */ 1636215976Sjmallett uint64_t d3_mem : 1; /**< BIST Status for DMA3 Memory */ 1637215976Sjmallett uint64_t d4_mem : 1; /**< BIST Status for DMA4 Memory */ 1638215976Sjmallett uint64_t d0_pst : 1; /**< BIST Status for DMA0 Pcie Store */ 1639215976Sjmallett uint64_t d1_pst : 1; /**< BIST Status for DMA1 Pcie Store */ 1640215976Sjmallett uint64_t d2_pst : 1; /**< BIST Status for DMA2 Pcie Store */ 1641215976Sjmallett uint64_t d3_pst : 1; /**< BIST Status for DMA3 Pcie Store */ 1642215976Sjmallett uint64_t d4_pst : 1; /**< BIST Status for DMA4 Pcie Store */ 1643215976Sjmallett uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */ 1644215976Sjmallett uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */ 1645215976Sjmallett uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */ 1646215976Sjmallett uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */ 1647215976Sjmallett uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */ 1648215976Sjmallett uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */ 1649215976Sjmallett uint64_t p2n1_po : 1; /**< BIST Status for P2N Port1 P Order */ 1650215976Sjmallett uint64_t p2n1_no : 1; /**< BIST Status for P2N Port1 N Order */ 1651215976Sjmallett uint64_t p2n1_co : 1; /**< BIST Status for P2N Port1 C Order */ 1652215976Sjmallett uint64_t p2n0_po : 1; /**< BIST Status for P2N Port0 P Order */ 1653215976Sjmallett uint64_t p2n0_no : 1; /**< BIST Status for P2N Port0 N Order */ 1654215976Sjmallett uint64_t p2n0_co : 1; /**< BIST Status for P2N Port0 C Order */ 1655215976Sjmallett uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */ 1656215976Sjmallett uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */ 1657215976Sjmallett uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */ 1658215976Sjmallett uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */ 1659215976Sjmallett uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */ 1660215976Sjmallett uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */ 1661215976Sjmallett uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */ 1662215976Sjmallett uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */ 1663215976Sjmallett uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */ 1664215976Sjmallett uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */ 1665215976Sjmallett uint64_t csm0 : 1; /**< BIST Status for CSM0 */ 1666215976Sjmallett uint64_t csm1 : 1; /**< BIST Status for CSM1 */ 1667215976Sjmallett uint64_t dif0 : 1; /**< BIST Status for DMA Instr0 */ 1668215976Sjmallett uint64_t dif1 : 1; /**< BIST Status for DMA Instr0 */ 1669215976Sjmallett uint64_t dif2 : 1; /**< BIST Status for DMA Instr0 */ 1670215976Sjmallett uint64_t dif3 : 1; /**< BIST Status for DMA Instr0 */ 1671215976Sjmallett uint64_t dif4 : 1; /**< BIST Status for DMA Instr0 */ 1672215976Sjmallett uint64_t msi : 1; /**< BIST Status for MSI Memory Map */ 1673215976Sjmallett uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */ 1674215976Sjmallett#else 1675215976Sjmallett uint64_t ncb_cmd : 1; 1676215976Sjmallett uint64_t msi : 1; 1677215976Sjmallett uint64_t dif4 : 1; 1678215976Sjmallett uint64_t dif3 : 1; 1679215976Sjmallett uint64_t dif2 : 1; 1680215976Sjmallett uint64_t dif1 : 1; 1681215976Sjmallett uint64_t dif0 : 1; 1682215976Sjmallett uint64_t csm1 : 1; 1683215976Sjmallett uint64_t csm0 : 1; 1684215976Sjmallett uint64_t p2n1_p1 : 1; 1685215976Sjmallett uint64_t p2n1_p0 : 1; 1686215976Sjmallett uint64_t p2n1_n : 1; 1687215976Sjmallett uint64_t p2n1_c1 : 1; 1688215976Sjmallett uint64_t p2n1_c0 : 1; 1689215976Sjmallett uint64_t p2n0_p1 : 1; 1690215976Sjmallett uint64_t p2n0_p0 : 1; 1691215976Sjmallett uint64_t p2n0_n : 1; 1692215976Sjmallett uint64_t p2n0_c1 : 1; 1693215976Sjmallett uint64_t p2n0_c0 : 1; 1694215976Sjmallett uint64_t p2n0_co : 1; 1695215976Sjmallett uint64_t p2n0_no : 1; 1696215976Sjmallett uint64_t p2n0_po : 1; 1697215976Sjmallett uint64_t p2n1_co : 1; 1698215976Sjmallett uint64_t p2n1_no : 1; 1699215976Sjmallett uint64_t p2n1_po : 1; 1700215976Sjmallett uint64_t cpl_p1 : 1; 1701215976Sjmallett uint64_t cpl_p0 : 1; 1702215976Sjmallett uint64_t n2p1_o : 1; 1703215976Sjmallett uint64_t n2p1_c : 1; 1704215976Sjmallett uint64_t n2p0_o : 1; 1705215976Sjmallett uint64_t n2p0_c : 1; 1706215976Sjmallett uint64_t d4_pst : 1; 1707215976Sjmallett uint64_t d3_pst : 1; 1708215976Sjmallett uint64_t d2_pst : 1; 1709215976Sjmallett uint64_t d1_pst : 1; 1710215976Sjmallett uint64_t d0_pst : 1; 1711215976Sjmallett uint64_t d4_mem : 1; 1712215976Sjmallett uint64_t d3_mem : 1; 1713215976Sjmallett uint64_t d2_mem : 1; 1714215976Sjmallett uint64_t d1_mem : 1; 1715215976Sjmallett uint64_t d0_mem : 1; 1716215976Sjmallett uint64_t pkt_s1 : 1; 1717215976Sjmallett uint64_t pkt_s0 : 1; 1718215976Sjmallett uint64_t pkt_i1 : 1; 1719215976Sjmallett uint64_t pkt_i0 : 1; 1720215976Sjmallett uint64_t pkt_out : 1; 1721215976Sjmallett uint64_t pkt_oif : 1; 1722215976Sjmallett uint64_t pkt_odf : 1; 1723215976Sjmallett uint64_t pkt_slm : 1; 1724215976Sjmallett uint64_t pkt_ind : 1; 1725215976Sjmallett uint64_t pkt_cntm : 1; 1726215976Sjmallett uint64_t pkt_imem : 1; 1727215976Sjmallett uint64_t pkt_pout : 1; 1728215976Sjmallett uint64_t pcsr_sl : 1; 1729215976Sjmallett uint64_t pcsr_id : 1; 1730215976Sjmallett uint64_t pcsr_cnt : 1; 1731215976Sjmallett uint64_t pcsr_im : 1; 1732215976Sjmallett uint64_t pcsr_int : 1; 1733215976Sjmallett uint64_t reserved_58_63 : 6; 1734215976Sjmallett#endif 1735215976Sjmallett } cn56xxp1; 1736215976Sjmallett}; 1737215976Sjmalletttypedef union cvmx_npei_bist_status cvmx_npei_bist_status_t; 1738215976Sjmallett 1739215976Sjmallett/** 1740215976Sjmallett * cvmx_npei_bist_status2 1741215976Sjmallett * 1742215976Sjmallett * NPEI_BIST_STATUS2 = NPI's BIST Status Register2 1743215976Sjmallett * 1744215976Sjmallett * Results from BIST runs of NPEI's memories. 1745215976Sjmallett */ 1746232812Sjmallettunion cvmx_npei_bist_status2 { 1747215976Sjmallett uint64_t u64; 1748232812Sjmallett struct cvmx_npei_bist_status2_s { 1749232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1750215976Sjmallett uint64_t reserved_14_63 : 50; 1751215976Sjmallett uint64_t prd_tag : 1; /**< BIST Status for DMA PCIE RD Tag MEM */ 1752215976Sjmallett uint64_t prd_st0 : 1; /**< BIST Status for DMA PCIE RD state MEM 0 */ 1753215976Sjmallett uint64_t prd_st1 : 1; /**< BIST Status for DMA PCIE RD state MEM 1 */ 1754215976Sjmallett uint64_t prd_err : 1; /**< BIST Status for DMA PCIE RD ERR state MEM */ 1755215976Sjmallett uint64_t nrd_st : 1; /**< BIST Status for DMA L2C RD state MEM */ 1756215976Sjmallett uint64_t nwe_st : 1; /**< BIST Status for DMA L2C WR state MEM */ 1757215976Sjmallett uint64_t nwe_wr0 : 1; /**< BIST Status for DMA L2C WR MEM 0 */ 1758215976Sjmallett uint64_t nwe_wr1 : 1; /**< BIST Status for DMA L2C WR MEM 1 */ 1759215976Sjmallett uint64_t pkt_rd : 1; /**< BIST Status for Inbound PKT MEM */ 1760215976Sjmallett uint64_t psc_p0 : 1; /**< BIST Status for PSC TLP 0 MEM */ 1761215976Sjmallett uint64_t psc_p1 : 1; /**< BIST Status for PSC TLP 1 MEM */ 1762215976Sjmallett uint64_t pkt_gd : 1; /**< BIST Status for PKT OUTB Gather Data FIFO */ 1763215976Sjmallett uint64_t pkt_gl : 1; /**< BIST Status for PKT_OUTB Gather List FIFO */ 1764215976Sjmallett uint64_t pkt_blk : 1; /**< BIST Status for PKT OUTB Blocked FIFO */ 1765215976Sjmallett#else 1766215976Sjmallett uint64_t pkt_blk : 1; 1767215976Sjmallett uint64_t pkt_gl : 1; 1768215976Sjmallett uint64_t pkt_gd : 1; 1769215976Sjmallett uint64_t psc_p1 : 1; 1770215976Sjmallett uint64_t psc_p0 : 1; 1771215976Sjmallett uint64_t pkt_rd : 1; 1772215976Sjmallett uint64_t nwe_wr1 : 1; 1773215976Sjmallett uint64_t nwe_wr0 : 1; 1774215976Sjmallett uint64_t nwe_st : 1; 1775215976Sjmallett uint64_t nrd_st : 1; 1776215976Sjmallett uint64_t prd_err : 1; 1777215976Sjmallett uint64_t prd_st1 : 1; 1778215976Sjmallett uint64_t prd_st0 : 1; 1779215976Sjmallett uint64_t prd_tag : 1; 1780215976Sjmallett uint64_t reserved_14_63 : 50; 1781215976Sjmallett#endif 1782215976Sjmallett } s; 1783215976Sjmallett struct cvmx_npei_bist_status2_s cn52xx; 1784215976Sjmallett struct cvmx_npei_bist_status2_s cn56xx; 1785215976Sjmallett}; 1786215976Sjmalletttypedef union cvmx_npei_bist_status2 cvmx_npei_bist_status2_t; 1787215976Sjmallett 1788215976Sjmallett/** 1789215976Sjmallett * cvmx_npei_ctl_port0 1790215976Sjmallett * 1791215976Sjmallett * NPEI_CTL_PORT0 = NPEI's Control Port 0 1792215976Sjmallett * 1793215976Sjmallett * Contains control for access for Port0 1794215976Sjmallett */ 1795232812Sjmallettunion cvmx_npei_ctl_port0 { 1796215976Sjmallett uint64_t u64; 1797232812Sjmallett struct cvmx_npei_ctl_port0_s { 1798232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1799215976Sjmallett uint64_t reserved_21_63 : 43; 1800215976Sjmallett uint64_t waitl_com : 1; /**< When set '1' casues the NPI to wait for a commit 1801215976Sjmallett from the L2C before sending additional completions 1802215976Sjmallett to the L2C from the PCIe. 1803215976Sjmallett Set this for more conservative behavior. Clear 1804215976Sjmallett this for more aggressive, higher-performance 1805215976Sjmallett behavior */ 1806215976Sjmallett uint64_t intd : 1; /**< When '0' Intd wire asserted. Before mapping. */ 1807215976Sjmallett uint64_t intc : 1; /**< When '0' Intc wire asserted. Before mapping. */ 1808215976Sjmallett uint64_t intb : 1; /**< When '0' Intb wire asserted. Before mapping. */ 1809215976Sjmallett uint64_t inta : 1; /**< When '0' Inta wire asserted. Before mapping. */ 1810215976Sjmallett uint64_t intd_map : 2; /**< Maps INTD to INTA(00), INTB(01), INTC(10) or 1811215976Sjmallett INTD (11). */ 1812215976Sjmallett uint64_t intc_map : 2; /**< Maps INTC to INTA(00), INTB(01), INTC(10) or 1813215976Sjmallett INTD (11). */ 1814215976Sjmallett uint64_t intb_map : 2; /**< Maps INTB to INTA(00), INTB(01), INTC(10) or 1815215976Sjmallett INTD (11). */ 1816215976Sjmallett uint64_t inta_map : 2; /**< Maps INTA to INTA(00), INTB(01), INTC(10) or 1817215976Sjmallett INTD (11). */ 1818215976Sjmallett uint64_t ctlp_ro : 1; /**< Relaxed ordering enable for Completion TLPS. */ 1819215976Sjmallett uint64_t reserved_6_6 : 1; 1820215976Sjmallett uint64_t ptlp_ro : 1; /**< Relaxed ordering enable for Posted TLPS. */ 1821215976Sjmallett uint64_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when 1822215976Sjmallett clear '0' BAR2 access will cause UR responses. */ 1823215976Sjmallett uint64_t bar2_esx : 2; /**< Value will be XORed with pci-address[37:36] to 1824215976Sjmallett determine the endian swap mode. */ 1825215976Sjmallett uint64_t bar2_cax : 1; /**< Value will be XORed with pcie-address[38] to 1826215976Sjmallett determine the L2 cache attribute. 1827215976Sjmallett Not cached in L2 if XOR result is 1 */ 1828215976Sjmallett uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit 1829215976Sjmallett from the L2C before sending additional stores to 1830215976Sjmallett the L2C from the PCIe. 1831215976Sjmallett Most applications will not notice a difference, so 1832215976Sjmallett should not set this bit. Setting the bit is more 1833215976Sjmallett conservative on ordering, lower performance */ 1834215976Sjmallett#else 1835215976Sjmallett uint64_t wait_com : 1; 1836215976Sjmallett uint64_t bar2_cax : 1; 1837215976Sjmallett uint64_t bar2_esx : 2; 1838215976Sjmallett uint64_t bar2_enb : 1; 1839215976Sjmallett uint64_t ptlp_ro : 1; 1840215976Sjmallett uint64_t reserved_6_6 : 1; 1841215976Sjmallett uint64_t ctlp_ro : 1; 1842215976Sjmallett uint64_t inta_map : 2; 1843215976Sjmallett uint64_t intb_map : 2; 1844215976Sjmallett uint64_t intc_map : 2; 1845215976Sjmallett uint64_t intd_map : 2; 1846215976Sjmallett uint64_t inta : 1; 1847215976Sjmallett uint64_t intb : 1; 1848215976Sjmallett uint64_t intc : 1; 1849215976Sjmallett uint64_t intd : 1; 1850215976Sjmallett uint64_t waitl_com : 1; 1851215976Sjmallett uint64_t reserved_21_63 : 43; 1852215976Sjmallett#endif 1853215976Sjmallett } s; 1854215976Sjmallett struct cvmx_npei_ctl_port0_s cn52xx; 1855215976Sjmallett struct cvmx_npei_ctl_port0_s cn52xxp1; 1856215976Sjmallett struct cvmx_npei_ctl_port0_s cn56xx; 1857215976Sjmallett struct cvmx_npei_ctl_port0_s cn56xxp1; 1858215976Sjmallett}; 1859215976Sjmalletttypedef union cvmx_npei_ctl_port0 cvmx_npei_ctl_port0_t; 1860215976Sjmallett 1861215976Sjmallett/** 1862215976Sjmallett * cvmx_npei_ctl_port1 1863215976Sjmallett * 1864215976Sjmallett * NPEI_CTL_PORT1 = NPEI's Control Port1 1865215976Sjmallett * 1866215976Sjmallett * Contains control for access for Port1 1867215976Sjmallett */ 1868232812Sjmallettunion cvmx_npei_ctl_port1 { 1869215976Sjmallett uint64_t u64; 1870232812Sjmallett struct cvmx_npei_ctl_port1_s { 1871232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1872215976Sjmallett uint64_t reserved_21_63 : 43; 1873215976Sjmallett uint64_t waitl_com : 1; /**< When set '1' casues the NPI to wait for a commit 1874215976Sjmallett from the L2C before sending additional completions 1875215976Sjmallett to the L2C from the PCIe. 1876215976Sjmallett Set this for more conservative behavior. Clear 1877215976Sjmallett this for more aggressive, higher-performance */ 1878215976Sjmallett uint64_t intd : 1; /**< When '0' Intd wire asserted. Before mapping. */ 1879215976Sjmallett uint64_t intc : 1; /**< When '0' Intc wire asserted. Before mapping. */ 1880215976Sjmallett uint64_t intb : 1; /**< When '0' Intv wire asserted. Before mapping. */ 1881215976Sjmallett uint64_t inta : 1; /**< When '0' Inta wire asserted. Before mapping. */ 1882215976Sjmallett uint64_t intd_map : 2; /**< Maps INTD to INTA(00), INTB(01), INTC(10) or 1883215976Sjmallett INTD (11). */ 1884215976Sjmallett uint64_t intc_map : 2; /**< Maps INTC to INTA(00), INTB(01), INTC(10) or 1885215976Sjmallett INTD (11). */ 1886215976Sjmallett uint64_t intb_map : 2; /**< Maps INTB to INTA(00), INTB(01), INTC(10) or 1887215976Sjmallett INTD (11). */ 1888215976Sjmallett uint64_t inta_map : 2; /**< Maps INTA to INTA(00), INTB(01), INTC(10) or 1889215976Sjmallett INTD (11). */ 1890215976Sjmallett uint64_t ctlp_ro : 1; /**< Relaxed ordering enable for Completion TLPS. */ 1891215976Sjmallett uint64_t reserved_6_6 : 1; 1892215976Sjmallett uint64_t ptlp_ro : 1; /**< Relaxed ordering enable for Posted TLPS. */ 1893215976Sjmallett uint64_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when 1894215976Sjmallett clear '0' BAR2 access will cause UR responses. */ 1895215976Sjmallett uint64_t bar2_esx : 2; /**< Value will be XORed with pci-address[37:36] to 1896215976Sjmallett determine the endian swap mode. */ 1897215976Sjmallett uint64_t bar2_cax : 1; /**< Value will be XORed with pcie-address[38] to 1898215976Sjmallett determine the L2 cache attribute. 1899215976Sjmallett Not cached in L2 if XOR result is 1 */ 1900215976Sjmallett uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit 1901215976Sjmallett from the L2C before sending additional stores to 1902215976Sjmallett the L2C from the PCIe. 1903215976Sjmallett Most applications will not notice a difference, so 1904215976Sjmallett should not set this bit. Setting the bit is more 1905215976Sjmallett conservative on ordering, lower performance */ 1906215976Sjmallett#else 1907215976Sjmallett uint64_t wait_com : 1; 1908215976Sjmallett uint64_t bar2_cax : 1; 1909215976Sjmallett uint64_t bar2_esx : 2; 1910215976Sjmallett uint64_t bar2_enb : 1; 1911215976Sjmallett uint64_t ptlp_ro : 1; 1912215976Sjmallett uint64_t reserved_6_6 : 1; 1913215976Sjmallett uint64_t ctlp_ro : 1; 1914215976Sjmallett uint64_t inta_map : 2; 1915215976Sjmallett uint64_t intb_map : 2; 1916215976Sjmallett uint64_t intc_map : 2; 1917215976Sjmallett uint64_t intd_map : 2; 1918215976Sjmallett uint64_t inta : 1; 1919215976Sjmallett uint64_t intb : 1; 1920215976Sjmallett uint64_t intc : 1; 1921215976Sjmallett uint64_t intd : 1; 1922215976Sjmallett uint64_t waitl_com : 1; 1923215976Sjmallett uint64_t reserved_21_63 : 43; 1924215976Sjmallett#endif 1925215976Sjmallett } s; 1926215976Sjmallett struct cvmx_npei_ctl_port1_s cn52xx; 1927215976Sjmallett struct cvmx_npei_ctl_port1_s cn52xxp1; 1928215976Sjmallett struct cvmx_npei_ctl_port1_s cn56xx; 1929215976Sjmallett struct cvmx_npei_ctl_port1_s cn56xxp1; 1930215976Sjmallett}; 1931215976Sjmalletttypedef union cvmx_npei_ctl_port1 cvmx_npei_ctl_port1_t; 1932215976Sjmallett 1933215976Sjmallett/** 1934215976Sjmallett * cvmx_npei_ctl_status 1935215976Sjmallett * 1936215976Sjmallett * NPEI_CTL_STATUS = NPEI Control Status Register 1937215976Sjmallett * 1938215976Sjmallett * Contains control and status for NPEI. Writes to this register are not oSrdered with writes/reads to the PCIe Memory space. 1939215976Sjmallett * To ensure that a write has completed the user must read the register before making an access(i.e. PCIe memory space) 1940215976Sjmallett * that requires the value of this register to be updated. 1941215976Sjmallett */ 1942232812Sjmallettunion cvmx_npei_ctl_status { 1943215976Sjmallett uint64_t u64; 1944232812Sjmallett struct cvmx_npei_ctl_status_s { 1945232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1946215976Sjmallett uint64_t reserved_44_63 : 20; 1947215976Sjmallett uint64_t p1_ntags : 6; /**< Number of tags avaiable for PCIe Port1. 1948215976Sjmallett In RC mode 1 tag is needed for each outbound TLP 1949215976Sjmallett that requires a CPL TLP. In Endpoint mode the 1950215976Sjmallett number of tags required for a TLP request is 1951215976Sjmallett 1 per 64-bytes of CPL data + 1. 1952215976Sjmallett This field should only be written as part of 1953215976Sjmallett reset sequence, before issuing any reads, CFGs, or 1954215976Sjmallett IO transactions from the core(s). */ 1955215976Sjmallett uint64_t p0_ntags : 6; /**< Number of tags avaiable for PCIe Port0. 1956215976Sjmallett In RC mode 1 tag is needed for each outbound TLP 1957215976Sjmallett that requires a CPL TLP. In Endpoint mode the 1958215976Sjmallett number of tags required for a TLP request is 1959215976Sjmallett 1 per 64-bytes of CPL data + 1. 1960215976Sjmallett This field should only be written as part of 1961215976Sjmallett reset sequence, before issuing any reads, CFGs, or 1962215976Sjmallett IO transactions from the core(s). */ 1963215976Sjmallett uint64_t cfg_rtry : 16; /**< The time x 0x10000 in core clocks to wait for a 1964215976Sjmallett CPL to a CFG RD that does not carry a Retry Status. 1965215976Sjmallett Until such time that the timeout occurs and Retry 1966215976Sjmallett Status is received for a CFG RD, the Read CFG Read 1967215976Sjmallett will be resent. A value of 0 disables retries and 1968215976Sjmallett treats a CPL Retry as a CPL UR. */ 1969215976Sjmallett uint64_t ring_en : 1; /**< When '0' forces "relative Q position" received 1970215976Sjmallett from PKO to be zero, and replicates the back- 1971215976Sjmallett pressure indication for the first ring attached 1972215976Sjmallett to a PKO port across all the rings attached to a 1973215976Sjmallett PKO port. When '1' backpressure is on a per 1974215976Sjmallett port/ring. */ 1975215976Sjmallett uint64_t lnk_rst : 1; /**< Set when PCIe Core 0 request a link reset due to 1976215976Sjmallett link down state. This bit is only reset on raw 1977215976Sjmallett reset so it can be read for state to determine if 1978215976Sjmallett a reset occured. Bit is cleared when a '1' is 1979215976Sjmallett written to this field. */ 1980215976Sjmallett uint64_t arb : 1; /**< PCIe switch arbitration mode. '0' == fixed priority 1981215976Sjmallett NPEI, PCIe0, then PCIe1. '1' == round robin. */ 1982215976Sjmallett uint64_t pkt_bp : 4; /**< Unused */ 1983215976Sjmallett uint64_t host_mode : 1; /**< Host mode */ 1984215976Sjmallett uint64_t chip_rev : 8; /**< The chip revision. */ 1985215976Sjmallett#else 1986215976Sjmallett uint64_t chip_rev : 8; 1987215976Sjmallett uint64_t host_mode : 1; 1988215976Sjmallett uint64_t pkt_bp : 4; 1989215976Sjmallett uint64_t arb : 1; 1990215976Sjmallett uint64_t lnk_rst : 1; 1991215976Sjmallett uint64_t ring_en : 1; 1992215976Sjmallett uint64_t cfg_rtry : 16; 1993215976Sjmallett uint64_t p0_ntags : 6; 1994215976Sjmallett uint64_t p1_ntags : 6; 1995215976Sjmallett uint64_t reserved_44_63 : 20; 1996215976Sjmallett#endif 1997215976Sjmallett } s; 1998215976Sjmallett struct cvmx_npei_ctl_status_s cn52xx; 1999232812Sjmallett struct cvmx_npei_ctl_status_cn52xxp1 { 2000232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2001215976Sjmallett uint64_t reserved_44_63 : 20; 2002215976Sjmallett uint64_t p1_ntags : 6; /**< Number of tags avaiable for PCIe Port1. 2003215976Sjmallett In RC mode 1 tag is needed for each outbound TLP 2004215976Sjmallett that requires a CPL TLP. In Endpoint mode the 2005215976Sjmallett number of tags required for a TLP request is 2006215976Sjmallett 1 per 64-bytes of CPL data + 1. 2007215976Sjmallett This field should only be written as part of 2008215976Sjmallett reset sequence, before issuing any reads, CFGs, or 2009215976Sjmallett IO transactions from the core(s). */ 2010215976Sjmallett uint64_t p0_ntags : 6; /**< Number of tags avaiable for PCIe Port0. 2011215976Sjmallett In RC mode 1 tag is needed for each outbound TLP 2012215976Sjmallett that requires a CPL TLP. In Endpoint mode the 2013215976Sjmallett number of tags required for a TLP request is 2014215976Sjmallett 1 per 64-bytes of CPL data + 1. 2015215976Sjmallett This field should only be written as part of 2016215976Sjmallett reset sequence, before issuing any reads, CFGs, or 2017215976Sjmallett IO transactions from the core(s). */ 2018215976Sjmallett uint64_t cfg_rtry : 16; /**< The time x 0x10000 in core clocks to wait for a 2019215976Sjmallett CPL to a CFG RD that does not carry a Retry Status. 2020215976Sjmallett Until such time that the timeout occurs and Retry 2021215976Sjmallett Status is received for a CFG RD, the Read CFG Read 2022215976Sjmallett will be resent. A value of 0 disables retries and 2023215976Sjmallett treats a CPL Retry as a CPL UR. */ 2024215976Sjmallett uint64_t reserved_15_15 : 1; 2025215976Sjmallett uint64_t lnk_rst : 1; /**< Set when PCIe Core 0 request a link reset due to 2026215976Sjmallett link down state. This bit is only reset on raw 2027215976Sjmallett reset so it can be read for state to determine if 2028215976Sjmallett a reset occured. Bit is cleared when a '1' is 2029215976Sjmallett written to this field. */ 2030215976Sjmallett uint64_t arb : 1; /**< PCIe switch arbitration mode. '0' == fixed priority 2031215976Sjmallett NPEI, PCIe0, then PCIe1. '1' == round robin. */ 2032215976Sjmallett uint64_t reserved_9_12 : 4; 2033215976Sjmallett uint64_t host_mode : 1; /**< Host mode */ 2034215976Sjmallett uint64_t chip_rev : 8; /**< The chip revision. */ 2035215976Sjmallett#else 2036215976Sjmallett uint64_t chip_rev : 8; 2037215976Sjmallett uint64_t host_mode : 1; 2038215976Sjmallett uint64_t reserved_9_12 : 4; 2039215976Sjmallett uint64_t arb : 1; 2040215976Sjmallett uint64_t lnk_rst : 1; 2041215976Sjmallett uint64_t reserved_15_15 : 1; 2042215976Sjmallett uint64_t cfg_rtry : 16; 2043215976Sjmallett uint64_t p0_ntags : 6; 2044215976Sjmallett uint64_t p1_ntags : 6; 2045215976Sjmallett uint64_t reserved_44_63 : 20; 2046215976Sjmallett#endif 2047215976Sjmallett } cn52xxp1; 2048215976Sjmallett struct cvmx_npei_ctl_status_s cn56xx; 2049232812Sjmallett struct cvmx_npei_ctl_status_cn56xxp1 { 2050232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2051215976Sjmallett uint64_t reserved_15_63 : 49; 2052215976Sjmallett uint64_t lnk_rst : 1; /**< Set when PCIe Core 0 request a link reset due to 2053215976Sjmallett link down state. This bit is only reset on raw 2054215976Sjmallett reset so it can be read for state to determine if 2055215976Sjmallett a reset occured. Bit is cleared when a '1' is 2056215976Sjmallett written to this field. */ 2057215976Sjmallett uint64_t arb : 1; /**< PCIe switch arbitration mode. '0' == fixed priority 2058215976Sjmallett NPEI, PCIe0, then PCIe1. '1' == round robin. */ 2059215976Sjmallett uint64_t pkt_bp : 4; /**< Unused */ 2060215976Sjmallett uint64_t host_mode : 1; /**< Host mode */ 2061215976Sjmallett uint64_t chip_rev : 8; /**< The chip revision. */ 2062215976Sjmallett#else 2063215976Sjmallett uint64_t chip_rev : 8; 2064215976Sjmallett uint64_t host_mode : 1; 2065215976Sjmallett uint64_t pkt_bp : 4; 2066215976Sjmallett uint64_t arb : 1; 2067215976Sjmallett uint64_t lnk_rst : 1; 2068215976Sjmallett uint64_t reserved_15_63 : 49; 2069215976Sjmallett#endif 2070215976Sjmallett } cn56xxp1; 2071215976Sjmallett}; 2072215976Sjmalletttypedef union cvmx_npei_ctl_status cvmx_npei_ctl_status_t; 2073215976Sjmallett 2074215976Sjmallett/** 2075215976Sjmallett * cvmx_npei_ctl_status2 2076215976Sjmallett * 2077215976Sjmallett * NPEI_CTL_STATUS2 = NPEI's Control Status2 Register 2078215976Sjmallett * 2079215976Sjmallett * Contains control and status for NPEI. 2080215976Sjmallett * Writes to this register are not ordered with writes/reads to the PCI Memory space. 2081215976Sjmallett * To ensure that a write has completed the user must read the register before 2082215976Sjmallett * making an access(i.e. PCI memory space) that requires the value of this register to be updated. 2083215976Sjmallett */ 2084232812Sjmallettunion cvmx_npei_ctl_status2 { 2085215976Sjmallett uint64_t u64; 2086232812Sjmallett struct cvmx_npei_ctl_status2_s { 2087232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2088215976Sjmallett uint64_t reserved_16_63 : 48; 2089215976Sjmallett uint64_t mps : 1; /**< Max Payload Size 2090215976Sjmallett 0 = 128B 2091215976Sjmallett 1 = 256B 2092215976Sjmallett Note: PCIE*_CFG030[MPS] must be set to the same 2093215976Sjmallett value for proper function. */ 2094215976Sjmallett uint64_t mrrs : 3; /**< Max Read Request Size 2095215976Sjmallett 0 = 128B 2096215976Sjmallett 1 = 256B 2097215976Sjmallett 2 = 512B 2098215976Sjmallett 3 = 1024B 2099215976Sjmallett 4 = 2048B 2100215976Sjmallett 5 = 4096B 2101215976Sjmallett Note: This field must not exceed the desired 2102215976Sjmallett max read request size. This means this field 2103215976Sjmallett should not exceed PCIE*_CFG030[MRRS]. */ 2104215976Sjmallett uint64_t c1_w_flt : 1; /**< When '1' enables the window filter for reads and 2105215976Sjmallett writes using the window registers. 2106215976Sjmallett PCIE-Port1. 2107215976Sjmallett Unfilter writes are: 2108215976Sjmallett MIO, SubId0 2109215976Sjmallett MIO, SubId7 2110215976Sjmallett NPEI, SubId0 2111215976Sjmallett NPEI, SubId7 2112215976Sjmallett POW, SubId7 2113215976Sjmallett IPD, SubId7 2114215976Sjmallett USBN0, SubId7 2115215976Sjmallett Unfiltered Reads are: 2116215976Sjmallett MIO, SubId0 2117215976Sjmallett MIO, SubId7 2118215976Sjmallett NPEI, SubId0 2119215976Sjmallett NPEI, SubId7 2120215976Sjmallett POW, SubId1 2121215976Sjmallett POW, SubId2 2122215976Sjmallett POW, SubId3 2123215976Sjmallett POW, SubId7 2124215976Sjmallett IPD, SubId7 2125215976Sjmallett USBN0, SubId7 */ 2126215976Sjmallett uint64_t c0_w_flt : 1; /**< When '1' enables the window filter for reads and 2127215976Sjmallett writes using the window registers. 2128215976Sjmallett PCIE-Port0. 2129215976Sjmallett Unfilter writes are: 2130215976Sjmallett MIO, SubId0 2131215976Sjmallett MIO, SubId7 2132215976Sjmallett NPEI, SubId0 2133215976Sjmallett NPEI, SubId7 2134215976Sjmallett POW, SubId7 2135215976Sjmallett IPD, SubId7 2136215976Sjmallett USBN0, SubId7 2137215976Sjmallett Unfiltered Reads are: 2138215976Sjmallett MIO, SubId0 2139215976Sjmallett MIO, SubId7 2140215976Sjmallett NPEI, SubId0 2141215976Sjmallett NPEI, SubId7 2142215976Sjmallett POW, SubId1 2143215976Sjmallett POW, SubId2 2144215976Sjmallett POW, SubId3 2145215976Sjmallett POW, SubId7 2146215976Sjmallett IPD, SubId7 2147215976Sjmallett USBN0, SubId7 */ 2148215976Sjmallett uint64_t c1_b1_s : 3; /**< Pcie-Port1, Bar1 Size. 1 == 64MB, 2 == 128MB, 2149215976Sjmallett 3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB, 2150215976Sjmallett 0 and 7 are reserved. */ 2151215976Sjmallett uint64_t c0_b1_s : 3; /**< Pcie-Port0, Bar1 Size. 1 == 64MB, 2 == 128MB, 2152215976Sjmallett 3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB, 2153215976Sjmallett 0 and 7 are reserved. */ 2154215976Sjmallett uint64_t c1_wi_d : 1; /**< When set '1' disables access to the Window 2155215976Sjmallett Registers from the PCIe-Port1. */ 2156215976Sjmallett uint64_t c1_b0_d : 1; /**< When set '1' disables access from PCIe-Port1 to 2157215976Sjmallett BAR-0 address offsets: Less Than 0x270, 2158215976Sjmallett Greater than 0x270 AND less than 0x0520, 0x3BC0, 2159215976Sjmallett 0x3CD0. */ 2160215976Sjmallett uint64_t c0_wi_d : 1; /**< When set '1' disables access to the Window 2161215976Sjmallett Registers from the PCIe-Port0. */ 2162215976Sjmallett uint64_t c0_b0_d : 1; /**< When set '1' disables access from PCIe-Port0 to 2163215976Sjmallett BAR-0 address offsets: Less Than 0x270, 2164215976Sjmallett Greater than 0x270 AND less than 0x0520, 0x3BC0, 2165215976Sjmallett 0x3CD0. */ 2166215976Sjmallett#else 2167215976Sjmallett uint64_t c0_b0_d : 1; 2168215976Sjmallett uint64_t c0_wi_d : 1; 2169215976Sjmallett uint64_t c1_b0_d : 1; 2170215976Sjmallett uint64_t c1_wi_d : 1; 2171215976Sjmallett uint64_t c0_b1_s : 3; 2172215976Sjmallett uint64_t c1_b1_s : 3; 2173215976Sjmallett uint64_t c0_w_flt : 1; 2174215976Sjmallett uint64_t c1_w_flt : 1; 2175215976Sjmallett uint64_t mrrs : 3; 2176215976Sjmallett uint64_t mps : 1; 2177215976Sjmallett uint64_t reserved_16_63 : 48; 2178215976Sjmallett#endif 2179215976Sjmallett } s; 2180215976Sjmallett struct cvmx_npei_ctl_status2_s cn52xx; 2181215976Sjmallett struct cvmx_npei_ctl_status2_s cn52xxp1; 2182215976Sjmallett struct cvmx_npei_ctl_status2_s cn56xx; 2183215976Sjmallett struct cvmx_npei_ctl_status2_s cn56xxp1; 2184215976Sjmallett}; 2185215976Sjmalletttypedef union cvmx_npei_ctl_status2 cvmx_npei_ctl_status2_t; 2186215976Sjmallett 2187215976Sjmallett/** 2188215976Sjmallett * cvmx_npei_data_out_cnt 2189215976Sjmallett * 2190215976Sjmallett * NPEI_DATA_OUT_CNT = NPEI DATA OUT COUNT 2191215976Sjmallett * 2192215976Sjmallett * The EXEC data out fifo-count and the data unload counter. 2193215976Sjmallett */ 2194232812Sjmallettunion cvmx_npei_data_out_cnt { 2195215976Sjmallett uint64_t u64; 2196232812Sjmallett struct cvmx_npei_data_out_cnt_s { 2197232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2198215976Sjmallett uint64_t reserved_44_63 : 20; 2199215976Sjmallett uint64_t p1_ucnt : 16; /**< PCIE-Port1 Fifo Unload Count. This counter is 2200215976Sjmallett incremented by '1' every time a word is removed 2201215976Sjmallett from the Data Out FIFO, whose count is shown in 2202215976Sjmallett P0_FCNT. */ 2203215976Sjmallett uint64_t p1_fcnt : 6; /**< PCIE-Port1 Data Out Fifo Count. Number of address 2204215976Sjmallett data words to be sent out the PCIe port presently 2205215976Sjmallett buffered in the FIFO. */ 2206215976Sjmallett uint64_t p0_ucnt : 16; /**< PCIE-Port0 Fifo Unload Count. This counter is 2207215976Sjmallett incremented by '1' every time a word is removed 2208215976Sjmallett from the Data Out FIFO, whose count is shown in 2209215976Sjmallett P0_FCNT. */ 2210215976Sjmallett uint64_t p0_fcnt : 6; /**< PCIE-Port0 Data Out Fifo Count. Number of address 2211215976Sjmallett data words to be sent out the PCIe port presently 2212215976Sjmallett buffered in the FIFO. */ 2213215976Sjmallett#else 2214215976Sjmallett uint64_t p0_fcnt : 6; 2215215976Sjmallett uint64_t p0_ucnt : 16; 2216215976Sjmallett uint64_t p1_fcnt : 6; 2217215976Sjmallett uint64_t p1_ucnt : 16; 2218215976Sjmallett uint64_t reserved_44_63 : 20; 2219215976Sjmallett#endif 2220215976Sjmallett } s; 2221215976Sjmallett struct cvmx_npei_data_out_cnt_s cn52xx; 2222215976Sjmallett struct cvmx_npei_data_out_cnt_s cn52xxp1; 2223215976Sjmallett struct cvmx_npei_data_out_cnt_s cn56xx; 2224215976Sjmallett struct cvmx_npei_data_out_cnt_s cn56xxp1; 2225215976Sjmallett}; 2226215976Sjmalletttypedef union cvmx_npei_data_out_cnt cvmx_npei_data_out_cnt_t; 2227215976Sjmallett 2228215976Sjmallett/** 2229215976Sjmallett * cvmx_npei_dbg_data 2230215976Sjmallett * 2231215976Sjmallett * NPEI_DBG_DATA = NPEI Debug Data Register 2232215976Sjmallett * 2233215976Sjmallett * Value returned on the debug-data lines from the RSLs 2234215976Sjmallett */ 2235232812Sjmallettunion cvmx_npei_dbg_data { 2236215976Sjmallett uint64_t u64; 2237232812Sjmallett struct cvmx_npei_dbg_data_s { 2238232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2239215976Sjmallett uint64_t reserved_28_63 : 36; 2240215976Sjmallett uint64_t qlm0_rev_lanes : 1; /**< Lane reversal for PCIe port 0 */ 2241215976Sjmallett uint64_t reserved_25_26 : 2; 2242215976Sjmallett uint64_t qlm1_spd : 2; /**< Sets the QLM1 frequency 2243215976Sjmallett 0=1.25 Gbaud 2244215976Sjmallett 1=2.5 Gbaud 2245215976Sjmallett 2=3.125 Gbaud 2246215976Sjmallett 3=3.75 Gbaud */ 2247215976Sjmallett uint64_t c_mul : 5; /**< PLL_MUL pins sampled at DCOK assertion 2248215976Sjmallett Core frequency = 50MHz*C_MUL */ 2249215976Sjmallett uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the 2250215976Sjmallett debug select value. */ 2251215976Sjmallett uint64_t data : 17; /**< Value on the debug data lines. */ 2252215976Sjmallett#else 2253215976Sjmallett uint64_t data : 17; 2254215976Sjmallett uint64_t dsel_ext : 1; 2255215976Sjmallett uint64_t c_mul : 5; 2256215976Sjmallett uint64_t qlm1_spd : 2; 2257215976Sjmallett uint64_t reserved_25_26 : 2; 2258215976Sjmallett uint64_t qlm0_rev_lanes : 1; 2259215976Sjmallett uint64_t reserved_28_63 : 36; 2260215976Sjmallett#endif 2261215976Sjmallett } s; 2262232812Sjmallett struct cvmx_npei_dbg_data_cn52xx { 2263232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2264215976Sjmallett uint64_t reserved_29_63 : 35; 2265215976Sjmallett uint64_t qlm0_link_width : 1; /**< Link width of PCIe port 0 2266215976Sjmallett 0 = PCIe port 0 is 2 lanes, 2267215976Sjmallett 2 lane PCIe port 1 exists 2268215976Sjmallett 1 = PCIe port 0 is 4 lanes, 2269215976Sjmallett PCIe port 1 does not exist */ 2270215976Sjmallett uint64_t qlm0_rev_lanes : 1; /**< Lane reversal for PCIe port 0 */ 2271215976Sjmallett uint64_t qlm1_mode : 2; /**< Sets the QLM1 Mode 2272215976Sjmallett 0=Reserved 2273215976Sjmallett 1=XAUI 2274215976Sjmallett 2=SGMII 2275215976Sjmallett 3=PICMG */ 2276215976Sjmallett uint64_t qlm1_spd : 2; /**< Sets the QLM1 frequency 2277215976Sjmallett 0=1.25 Gbaud 2278215976Sjmallett 1=2.5 Gbaud 2279215976Sjmallett 2=3.125 Gbaud 2280215976Sjmallett 3=3.75 Gbaud */ 2281215976Sjmallett uint64_t c_mul : 5; /**< PLL_MUL pins sampled at DCOK assertion 2282215976Sjmallett Core frequency = 50MHz*C_MUL */ 2283215976Sjmallett uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the 2284215976Sjmallett debug select value. */ 2285215976Sjmallett uint64_t data : 17; /**< Value on the debug data lines. */ 2286215976Sjmallett#else 2287215976Sjmallett uint64_t data : 17; 2288215976Sjmallett uint64_t dsel_ext : 1; 2289215976Sjmallett uint64_t c_mul : 5; 2290215976Sjmallett uint64_t qlm1_spd : 2; 2291215976Sjmallett uint64_t qlm1_mode : 2; 2292215976Sjmallett uint64_t qlm0_rev_lanes : 1; 2293215976Sjmallett uint64_t qlm0_link_width : 1; 2294215976Sjmallett uint64_t reserved_29_63 : 35; 2295215976Sjmallett#endif 2296215976Sjmallett } cn52xx; 2297215976Sjmallett struct cvmx_npei_dbg_data_cn52xx cn52xxp1; 2298232812Sjmallett struct cvmx_npei_dbg_data_cn56xx { 2299232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2300215976Sjmallett uint64_t reserved_29_63 : 35; 2301215976Sjmallett uint64_t qlm2_rev_lanes : 1; /**< Lane reversal for PCIe port 1 */ 2302215976Sjmallett uint64_t qlm0_rev_lanes : 1; /**< Lane reversal for PCIe port 0 */ 2303215976Sjmallett uint64_t qlm3_spd : 2; /**< Sets the QLM3 frequency 2304215976Sjmallett 0=1.25 Gbaud 2305215976Sjmallett 1=2.5 Gbaud 2306215976Sjmallett 2=3.125 Gbaud 2307215976Sjmallett 3=3.75 Gbaud */ 2308215976Sjmallett uint64_t qlm1_spd : 2; /**< Sets the QLM1 frequency 2309215976Sjmallett 0=1.25 Gbaud 2310215976Sjmallett 1=2.5 Gbaud 2311215976Sjmallett 2=3.125 Gbaud 2312215976Sjmallett 3=3.75 Gbaud */ 2313215976Sjmallett uint64_t c_mul : 5; /**< PLL_MUL pins sampled at DCOK assertion 2314215976Sjmallett Core frequency = 50MHz*C_MUL */ 2315215976Sjmallett uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the 2316215976Sjmallett debug select value. */ 2317215976Sjmallett uint64_t data : 17; /**< Value on the debug data lines. */ 2318215976Sjmallett#else 2319215976Sjmallett uint64_t data : 17; 2320215976Sjmallett uint64_t dsel_ext : 1; 2321215976Sjmallett uint64_t c_mul : 5; 2322215976Sjmallett uint64_t qlm1_spd : 2; 2323215976Sjmallett uint64_t qlm3_spd : 2; 2324215976Sjmallett uint64_t qlm0_rev_lanes : 1; 2325215976Sjmallett uint64_t qlm2_rev_lanes : 1; 2326215976Sjmallett uint64_t reserved_29_63 : 35; 2327215976Sjmallett#endif 2328215976Sjmallett } cn56xx; 2329215976Sjmallett struct cvmx_npei_dbg_data_cn56xx cn56xxp1; 2330215976Sjmallett}; 2331215976Sjmalletttypedef union cvmx_npei_dbg_data cvmx_npei_dbg_data_t; 2332215976Sjmallett 2333215976Sjmallett/** 2334215976Sjmallett * cvmx_npei_dbg_select 2335215976Sjmallett * 2336215976Sjmallett * NPEI_DBG_SELECT = Debug Select Register 2337215976Sjmallett * 2338215976Sjmallett * Contains the debug select value last written to the RSLs. 2339215976Sjmallett */ 2340232812Sjmallettunion cvmx_npei_dbg_select { 2341215976Sjmallett uint64_t u64; 2342232812Sjmallett struct cvmx_npei_dbg_select_s { 2343232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2344215976Sjmallett uint64_t reserved_16_63 : 48; 2345215976Sjmallett uint64_t dbg_sel : 16; /**< When this register is written its value is sent to 2346215976Sjmallett all RSLs. */ 2347215976Sjmallett#else 2348215976Sjmallett uint64_t dbg_sel : 16; 2349215976Sjmallett uint64_t reserved_16_63 : 48; 2350215976Sjmallett#endif 2351215976Sjmallett } s; 2352215976Sjmallett struct cvmx_npei_dbg_select_s cn52xx; 2353215976Sjmallett struct cvmx_npei_dbg_select_s cn52xxp1; 2354215976Sjmallett struct cvmx_npei_dbg_select_s cn56xx; 2355215976Sjmallett struct cvmx_npei_dbg_select_s cn56xxp1; 2356215976Sjmallett}; 2357215976Sjmalletttypedef union cvmx_npei_dbg_select cvmx_npei_dbg_select_t; 2358215976Sjmallett 2359215976Sjmallett/** 2360215976Sjmallett * cvmx_npei_dma#_counts 2361215976Sjmallett * 2362215976Sjmallett * NPEI_DMA[0..4]_COUNTS = DMA Instruction Counts 2363215976Sjmallett * 2364215976Sjmallett * Values for determing the number of instructions for DMA[0..4] in the NPEI. 2365215976Sjmallett */ 2366232812Sjmallettunion cvmx_npei_dmax_counts { 2367215976Sjmallett uint64_t u64; 2368232812Sjmallett struct cvmx_npei_dmax_counts_s { 2369232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2370215976Sjmallett uint64_t reserved_39_63 : 25; 2371215976Sjmallett uint64_t fcnt : 7; /**< Number of words in the Instruction FIFO. */ 2372215976Sjmallett uint64_t dbell : 32; /**< Number of available words of Instructions to read. */ 2373215976Sjmallett#else 2374215976Sjmallett uint64_t dbell : 32; 2375215976Sjmallett uint64_t fcnt : 7; 2376215976Sjmallett uint64_t reserved_39_63 : 25; 2377215976Sjmallett#endif 2378215976Sjmallett } s; 2379215976Sjmallett struct cvmx_npei_dmax_counts_s cn52xx; 2380215976Sjmallett struct cvmx_npei_dmax_counts_s cn52xxp1; 2381215976Sjmallett struct cvmx_npei_dmax_counts_s cn56xx; 2382215976Sjmallett struct cvmx_npei_dmax_counts_s cn56xxp1; 2383215976Sjmallett}; 2384215976Sjmalletttypedef union cvmx_npei_dmax_counts cvmx_npei_dmax_counts_t; 2385215976Sjmallett 2386215976Sjmallett/** 2387215976Sjmallett * cvmx_npei_dma#_dbell 2388215976Sjmallett * 2389215976Sjmallett * NPEI_DMA_DBELL[0..4] = DMA Door Bell 2390215976Sjmallett * 2391215976Sjmallett * The door bell register for DMA[0..4] queue. 2392215976Sjmallett */ 2393232812Sjmallettunion cvmx_npei_dmax_dbell { 2394215976Sjmallett uint32_t u32; 2395232812Sjmallett struct cvmx_npei_dmax_dbell_s { 2396232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2397215976Sjmallett uint32_t reserved_16_31 : 16; 2398215976Sjmallett uint32_t dbell : 16; /**< The value written to this register is added to the 2399215976Sjmallett number of 8byte words to be read and processes for 2400215976Sjmallett the low priority dma queue. */ 2401215976Sjmallett#else 2402215976Sjmallett uint32_t dbell : 16; 2403215976Sjmallett uint32_t reserved_16_31 : 16; 2404215976Sjmallett#endif 2405215976Sjmallett } s; 2406215976Sjmallett struct cvmx_npei_dmax_dbell_s cn52xx; 2407215976Sjmallett struct cvmx_npei_dmax_dbell_s cn52xxp1; 2408215976Sjmallett struct cvmx_npei_dmax_dbell_s cn56xx; 2409215976Sjmallett struct cvmx_npei_dmax_dbell_s cn56xxp1; 2410215976Sjmallett}; 2411215976Sjmalletttypedef union cvmx_npei_dmax_dbell cvmx_npei_dmax_dbell_t; 2412215976Sjmallett 2413215976Sjmallett/** 2414215976Sjmallett * cvmx_npei_dma#_ibuff_saddr 2415215976Sjmallett * 2416215976Sjmallett * NPEI_DMA[0..4]_IBUFF_SADDR = DMA Instruction Buffer Starting Address 2417215976Sjmallett * 2418215976Sjmallett * The address to start reading Instructions from for DMA[0..4]. 2419215976Sjmallett */ 2420232812Sjmallettunion cvmx_npei_dmax_ibuff_saddr { 2421215976Sjmallett uint64_t u64; 2422232812Sjmallett struct cvmx_npei_dmax_ibuff_saddr_s { 2423232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2424215976Sjmallett uint64_t reserved_37_63 : 27; 2425215976Sjmallett uint64_t idle : 1; /**< DMA Engine IDLE state */ 2426215976Sjmallett uint64_t saddr : 29; /**< The 128 byte aligned starting address to read the 2427215976Sjmallett first instruction. SADDR is address bit 35:7 of the 2428215976Sjmallett first instructions address. */ 2429215976Sjmallett uint64_t reserved_0_6 : 7; 2430215976Sjmallett#else 2431215976Sjmallett uint64_t reserved_0_6 : 7; 2432215976Sjmallett uint64_t saddr : 29; 2433215976Sjmallett uint64_t idle : 1; 2434215976Sjmallett uint64_t reserved_37_63 : 27; 2435215976Sjmallett#endif 2436215976Sjmallett } s; 2437215976Sjmallett struct cvmx_npei_dmax_ibuff_saddr_s cn52xx; 2438232812Sjmallett struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 { 2439232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2440215976Sjmallett uint64_t reserved_36_63 : 28; 2441215976Sjmallett uint64_t saddr : 29; /**< The 128 byte aligned starting address to read the 2442215976Sjmallett first instruction. SADDR is address bit 35:7 of the 2443215976Sjmallett first instructions address. */ 2444215976Sjmallett uint64_t reserved_0_6 : 7; 2445215976Sjmallett#else 2446215976Sjmallett uint64_t reserved_0_6 : 7; 2447215976Sjmallett uint64_t saddr : 29; 2448215976Sjmallett uint64_t reserved_36_63 : 28; 2449215976Sjmallett#endif 2450215976Sjmallett } cn52xxp1; 2451215976Sjmallett struct cvmx_npei_dmax_ibuff_saddr_s cn56xx; 2452215976Sjmallett struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1; 2453215976Sjmallett}; 2454215976Sjmalletttypedef union cvmx_npei_dmax_ibuff_saddr cvmx_npei_dmax_ibuff_saddr_t; 2455215976Sjmallett 2456215976Sjmallett/** 2457215976Sjmallett * cvmx_npei_dma#_naddr 2458215976Sjmallett * 2459215976Sjmallett * NPEI_DMA[0..4]_NADDR = DMA Next Ichunk Address 2460215976Sjmallett * 2461215976Sjmallett * Place NPEI will read the next Ichunk data from. This is valid when state is 0 2462215976Sjmallett */ 2463232812Sjmallettunion cvmx_npei_dmax_naddr { 2464215976Sjmallett uint64_t u64; 2465232812Sjmallett struct cvmx_npei_dmax_naddr_s { 2466232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2467215976Sjmallett uint64_t reserved_36_63 : 28; 2468215976Sjmallett uint64_t addr : 36; /**< The next L2C address to read DMA# instructions 2469215976Sjmallett from. */ 2470215976Sjmallett#else 2471215976Sjmallett uint64_t addr : 36; 2472215976Sjmallett uint64_t reserved_36_63 : 28; 2473215976Sjmallett#endif 2474215976Sjmallett } s; 2475215976Sjmallett struct cvmx_npei_dmax_naddr_s cn52xx; 2476215976Sjmallett struct cvmx_npei_dmax_naddr_s cn52xxp1; 2477215976Sjmallett struct cvmx_npei_dmax_naddr_s cn56xx; 2478215976Sjmallett struct cvmx_npei_dmax_naddr_s cn56xxp1; 2479215976Sjmallett}; 2480215976Sjmalletttypedef union cvmx_npei_dmax_naddr cvmx_npei_dmax_naddr_t; 2481215976Sjmallett 2482215976Sjmallett/** 2483215976Sjmallett * cvmx_npei_dma0_int_level 2484215976Sjmallett * 2485215976Sjmallett * NPEI_DMA0_INT_LEVEL = NPEI DMA0 Interrupt Level 2486215976Sjmallett * 2487215976Sjmallett * Thresholds for DMA count and timer interrupts for DMA0. 2488215976Sjmallett */ 2489232812Sjmallettunion cvmx_npei_dma0_int_level { 2490215976Sjmallett uint64_t u64; 2491232812Sjmallett struct cvmx_npei_dma0_int_level_s { 2492232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2493215976Sjmallett uint64_t time : 32; /**< Whenever the DMA_CNT0 timer exceeds 2494215976Sjmallett this value, NPEI_INT_SUM[DTIME0] is set. 2495215976Sjmallett The DMA_CNT0 timer increments every core clock 2496215976Sjmallett whenever NPEI_DMA_CNTS[DMA0]!=0, and is cleared 2497215976Sjmallett when NPEI_INT_SUM[DTIME0] is written with one. */ 2498215976Sjmallett uint64_t cnt : 32; /**< Whenever NPEI_DMA_CNTS[DMA0] exceeds this value, 2499215976Sjmallett NPEI_INT_SUM[DCNT0] is set. */ 2500215976Sjmallett#else 2501215976Sjmallett uint64_t cnt : 32; 2502215976Sjmallett uint64_t time : 32; 2503215976Sjmallett#endif 2504215976Sjmallett } s; 2505215976Sjmallett struct cvmx_npei_dma0_int_level_s cn52xx; 2506215976Sjmallett struct cvmx_npei_dma0_int_level_s cn52xxp1; 2507215976Sjmallett struct cvmx_npei_dma0_int_level_s cn56xx; 2508215976Sjmallett struct cvmx_npei_dma0_int_level_s cn56xxp1; 2509215976Sjmallett}; 2510215976Sjmalletttypedef union cvmx_npei_dma0_int_level cvmx_npei_dma0_int_level_t; 2511215976Sjmallett 2512215976Sjmallett/** 2513215976Sjmallett * cvmx_npei_dma1_int_level 2514215976Sjmallett * 2515215976Sjmallett * NPEI_DMA1_INT_LEVEL = NPEI DMA1 Interrupt Level 2516215976Sjmallett * 2517215976Sjmallett * Thresholds for DMA count and timer interrupts for DMA1. 2518215976Sjmallett */ 2519232812Sjmallettunion cvmx_npei_dma1_int_level { 2520215976Sjmallett uint64_t u64; 2521232812Sjmallett struct cvmx_npei_dma1_int_level_s { 2522232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2523215976Sjmallett uint64_t time : 32; /**< Whenever the DMA_CNT1 timer exceeds 2524215976Sjmallett this value, NPEI_INT_SUM[DTIME1] is set. 2525215976Sjmallett The DMA_CNT1 timer increments every core clock 2526215976Sjmallett whenever NPEI_DMA_CNTS[DMA1]!=0, and is cleared 2527215976Sjmallett when NPEI_INT_SUM[DTIME1] is written with one. */ 2528215976Sjmallett uint64_t cnt : 32; /**< Whenever NPEI_DMA_CNTS[DMA1] exceeds this value, 2529215976Sjmallett NPEI_INT_SUM[DCNT1] is set. */ 2530215976Sjmallett#else 2531215976Sjmallett uint64_t cnt : 32; 2532215976Sjmallett uint64_t time : 32; 2533215976Sjmallett#endif 2534215976Sjmallett } s; 2535215976Sjmallett struct cvmx_npei_dma1_int_level_s cn52xx; 2536215976Sjmallett struct cvmx_npei_dma1_int_level_s cn52xxp1; 2537215976Sjmallett struct cvmx_npei_dma1_int_level_s cn56xx; 2538215976Sjmallett struct cvmx_npei_dma1_int_level_s cn56xxp1; 2539215976Sjmallett}; 2540215976Sjmalletttypedef union cvmx_npei_dma1_int_level cvmx_npei_dma1_int_level_t; 2541215976Sjmallett 2542215976Sjmallett/** 2543215976Sjmallett * cvmx_npei_dma_cnts 2544215976Sjmallett * 2545215976Sjmallett * NPEI_DMA_CNTS = NPEI DMA Count 2546215976Sjmallett * 2547215976Sjmallett * The DMA Count values for DMA0 and DMA1. 2548215976Sjmallett */ 2549232812Sjmallettunion cvmx_npei_dma_cnts { 2550215976Sjmallett uint64_t u64; 2551232812Sjmallett struct cvmx_npei_dma_cnts_s { 2552232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2553215976Sjmallett uint64_t dma1 : 32; /**< The DMA counter 1. 2554215976Sjmallett Writing this field will cause the written value to 2555215976Sjmallett be subtracted from DMA1. SW should use a 4-byte 2556215976Sjmallett write to access this field so as not to change the 2557215976Sjmallett value of other fields in this register. 2558215976Sjmallett HW will optionally increment this field after 2559215976Sjmallett it completes an OUTBOUND or EXTERNAL-ONLY DMA 2560215976Sjmallett instruction. These increments may cause interrupts. 2561215976Sjmallett Refer to NPEI_DMA1_INT_LEVEL and 2562215976Sjmallett NPEI_INT_SUM[DCNT1,DTIME1]. */ 2563215976Sjmallett uint64_t dma0 : 32; /**< The DMA counter 0. 2564215976Sjmallett Writing this field will cause the written value to 2565215976Sjmallett be subtracted from DMA0. SW should use a 4-byte 2566215976Sjmallett write to access this field so as not to change the 2567215976Sjmallett value of other fields in this register. 2568215976Sjmallett HW will optionally increment this field after 2569215976Sjmallett it completes an OUTBOUND or EXTERNAL-ONLY DMA 2570215976Sjmallett instruction. These increments may cause interrupts. 2571215976Sjmallett Refer to NPEI_DMA0_INT_LEVEL and 2572215976Sjmallett NPEI_INT_SUM[DCNT0,DTIME0]. */ 2573215976Sjmallett#else 2574215976Sjmallett uint64_t dma0 : 32; 2575215976Sjmallett uint64_t dma1 : 32; 2576215976Sjmallett#endif 2577215976Sjmallett } s; 2578215976Sjmallett struct cvmx_npei_dma_cnts_s cn52xx; 2579215976Sjmallett struct cvmx_npei_dma_cnts_s cn52xxp1; 2580215976Sjmallett struct cvmx_npei_dma_cnts_s cn56xx; 2581215976Sjmallett struct cvmx_npei_dma_cnts_s cn56xxp1; 2582215976Sjmallett}; 2583215976Sjmalletttypedef union cvmx_npei_dma_cnts cvmx_npei_dma_cnts_t; 2584215976Sjmallett 2585215976Sjmallett/** 2586215976Sjmallett * cvmx_npei_dma_control 2587215976Sjmallett * 2588215976Sjmallett * NPEI_DMA_CONTROL = DMA Control Register 2589215976Sjmallett * 2590215976Sjmallett * Controls operation of the DMA IN/OUT. 2591215976Sjmallett */ 2592232812Sjmallettunion cvmx_npei_dma_control { 2593215976Sjmallett uint64_t u64; 2594232812Sjmallett struct cvmx_npei_dma_control_s { 2595232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2596215976Sjmallett uint64_t reserved_40_63 : 24; 2597215976Sjmallett uint64_t p_32b_m : 1; /**< DMA PCIE 32-bit word read disable bit 2598215976Sjmallett When 0, enable the feature */ 2599215976Sjmallett uint64_t dma4_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2600215976Sjmallett engine. After being enabled a DMA engine should not 2601215976Sjmallett be dis-abled while processing instructions. */ 2602215976Sjmallett uint64_t dma3_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2603215976Sjmallett engine. After being enabled a DMA engine should not 2604215976Sjmallett be dis-abled while processing instructions. */ 2605215976Sjmallett uint64_t dma2_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2606215976Sjmallett engine. After being enabled a DMA engine should not 2607215976Sjmallett be dis-abled while processing instructions. */ 2608215976Sjmallett uint64_t dma1_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2609215976Sjmallett engine. After being enabled a DMA engine should not 2610215976Sjmallett be dis-abled while processing instructions. */ 2611215976Sjmallett uint64_t dma0_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2612215976Sjmallett engine. After being enabled a DMA engine should not 2613215976Sjmallett be dis-abled while processing instructions. */ 2614215976Sjmallett uint64_t b0_lend : 1; /**< When set '1' and the NPEI is in the mode to write 2615215976Sjmallett 0 to L2C memory when a DMA is done, the address 2616215976Sjmallett to be written to will be treated as a Little 2617215976Sjmallett Endian address. */ 2618215976Sjmallett uint64_t dwb_denb : 1; /**< When set '1' the NPEI will send a value in the DWB 2619215976Sjmallett field for a free page operation for the memory 2620215976Sjmallett that contained the data. */ 2621215976Sjmallett uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are freed 2622215976Sjmallett this value is used for the DWB field of the 2623215976Sjmallett operation. */ 2624215976Sjmallett uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will 2625215976Sjmallett be returned to when used. */ 2626215976Sjmallett uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters, 2627215976Sjmallett if '0' then the number of bytes in the dma transfer 2628215976Sjmallett will be added to the count register. */ 2629215976Sjmallett uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */ 2630215976Sjmallett uint64_t o_ns : 1; /**< Nosnoop For DMA. */ 2631215976Sjmallett uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */ 2632215976Sjmallett uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used. 2633215976Sjmallett '1' use pointer values for address and register 2634215976Sjmallett values for RO, ES, and NS, '0' use register 2635215976Sjmallett values for address and pointer values for 2636215976Sjmallett RO, ES, and NS. */ 2637215976Sjmallett uint64_t csize : 14; /**< The size in words of the DMA Instruction Chunk. 2638215976Sjmallett This value should only be written once. After 2639215976Sjmallett writing this value a new value will not be 2640215976Sjmallett recognized until the end of the DMA I-Chunk is 2641215976Sjmallett reached. */ 2642215976Sjmallett#else 2643215976Sjmallett uint64_t csize : 14; 2644215976Sjmallett uint64_t o_mode : 1; 2645215976Sjmallett uint64_t o_es : 2; 2646215976Sjmallett uint64_t o_ns : 1; 2647215976Sjmallett uint64_t o_ro : 1; 2648215976Sjmallett uint64_t o_add1 : 1; 2649215976Sjmallett uint64_t fpa_que : 3; 2650215976Sjmallett uint64_t dwb_ichk : 9; 2651215976Sjmallett uint64_t dwb_denb : 1; 2652215976Sjmallett uint64_t b0_lend : 1; 2653215976Sjmallett uint64_t dma0_enb : 1; 2654215976Sjmallett uint64_t dma1_enb : 1; 2655215976Sjmallett uint64_t dma2_enb : 1; 2656215976Sjmallett uint64_t dma3_enb : 1; 2657215976Sjmallett uint64_t dma4_enb : 1; 2658215976Sjmallett uint64_t p_32b_m : 1; 2659215976Sjmallett uint64_t reserved_40_63 : 24; 2660215976Sjmallett#endif 2661215976Sjmallett } s; 2662215976Sjmallett struct cvmx_npei_dma_control_s cn52xx; 2663232812Sjmallett struct cvmx_npei_dma_control_cn52xxp1 { 2664232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2665215976Sjmallett uint64_t reserved_38_63 : 26; 2666215976Sjmallett uint64_t dma3_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2667215976Sjmallett engine. After being enabled a DMA engine should not 2668215976Sjmallett be dis-abled while processing instructions. */ 2669215976Sjmallett uint64_t dma2_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2670215976Sjmallett engine. After being enabled a DMA engine should not 2671215976Sjmallett be dis-abled while processing instructions. */ 2672215976Sjmallett uint64_t dma1_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2673215976Sjmallett engine. After being enabled a DMA engine should not 2674215976Sjmallett be dis-abled while processing instructions. */ 2675215976Sjmallett uint64_t dma0_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2676215976Sjmallett engine. After being enabled a DMA engine should not 2677215976Sjmallett be dis-abled while processing instructions. */ 2678215976Sjmallett uint64_t b0_lend : 1; /**< When set '1' and the NPEI is in the mode to write 2679215976Sjmallett 0 to L2C memory when a DMA is done, the address 2680215976Sjmallett to be written to will be treated as a Little 2681215976Sjmallett Endian address. */ 2682215976Sjmallett uint64_t dwb_denb : 1; /**< When set '1' the NPEI will send a value in the DWB 2683215976Sjmallett field for a free page operation for the memory 2684215976Sjmallett that contained the data. */ 2685215976Sjmallett uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are freed 2686215976Sjmallett this value is used for the DWB field of the 2687215976Sjmallett operation. */ 2688215976Sjmallett uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will 2689215976Sjmallett be returned to when used. */ 2690215976Sjmallett uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters, 2691215976Sjmallett if '0' then the number of bytes in the dma transfer 2692215976Sjmallett will be added to the count register. */ 2693215976Sjmallett uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */ 2694215976Sjmallett uint64_t o_ns : 1; /**< Nosnoop For DMA. */ 2695215976Sjmallett uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */ 2696215976Sjmallett uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used. 2697215976Sjmallett '1' use pointer values for address and register 2698215976Sjmallett values for RO, ES, and NS, '0' use register 2699215976Sjmallett values for address and pointer values for 2700215976Sjmallett RO, ES, and NS. */ 2701215976Sjmallett uint64_t csize : 14; /**< The size in words of the DMA Instruction Chunk. 2702215976Sjmallett This value should only be written once. After 2703215976Sjmallett writing this value a new value will not be 2704215976Sjmallett recognized until the end of the DMA I-Chunk is 2705215976Sjmallett reached. */ 2706215976Sjmallett#else 2707215976Sjmallett uint64_t csize : 14; 2708215976Sjmallett uint64_t o_mode : 1; 2709215976Sjmallett uint64_t o_es : 2; 2710215976Sjmallett uint64_t o_ns : 1; 2711215976Sjmallett uint64_t o_ro : 1; 2712215976Sjmallett uint64_t o_add1 : 1; 2713215976Sjmallett uint64_t fpa_que : 3; 2714215976Sjmallett uint64_t dwb_ichk : 9; 2715215976Sjmallett uint64_t dwb_denb : 1; 2716215976Sjmallett uint64_t b0_lend : 1; 2717215976Sjmallett uint64_t dma0_enb : 1; 2718215976Sjmallett uint64_t dma1_enb : 1; 2719215976Sjmallett uint64_t dma2_enb : 1; 2720215976Sjmallett uint64_t dma3_enb : 1; 2721215976Sjmallett uint64_t reserved_38_63 : 26; 2722215976Sjmallett#endif 2723215976Sjmallett } cn52xxp1; 2724215976Sjmallett struct cvmx_npei_dma_control_s cn56xx; 2725232812Sjmallett struct cvmx_npei_dma_control_cn56xxp1 { 2726232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2727215976Sjmallett uint64_t reserved_39_63 : 25; 2728215976Sjmallett uint64_t dma4_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2729215976Sjmallett engine. After being enabled a DMA engine should not 2730215976Sjmallett be dis-abled while processing instructions. */ 2731215976Sjmallett uint64_t dma3_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2732215976Sjmallett engine. After being enabled a DMA engine should not 2733215976Sjmallett be dis-abled while processing instructions. */ 2734215976Sjmallett uint64_t dma2_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2735215976Sjmallett engine. After being enabled a DMA engine should not 2736215976Sjmallett be dis-abled while processing instructions. */ 2737215976Sjmallett uint64_t dma1_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2738215976Sjmallett engine. After being enabled a DMA engine should not 2739215976Sjmallett be dis-abled while processing instructions. */ 2740215976Sjmallett uint64_t dma0_enb : 1; /**< DMA# enable. Enables the operation of the DMA 2741215976Sjmallett engine. After being enabled a DMA engine should not 2742215976Sjmallett be dis-abled while processing instructions. */ 2743215976Sjmallett uint64_t b0_lend : 1; /**< When set '1' and the NPEI is in the mode to write 2744215976Sjmallett 0 to L2C memory when a DMA is done, the address 2745215976Sjmallett to be written to will be treated as a Little 2746215976Sjmallett Endian address. */ 2747215976Sjmallett uint64_t dwb_denb : 1; /**< When set '1' the NPEI will send a value in the DWB 2748215976Sjmallett field for a free page operation for the memory 2749215976Sjmallett that contained the data. */ 2750215976Sjmallett uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are freed 2751215976Sjmallett this value is used for the DWB field of the 2752215976Sjmallett operation. */ 2753215976Sjmallett uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will 2754215976Sjmallett be returned to when used. */ 2755215976Sjmallett uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters, 2756215976Sjmallett if '0' then the number of bytes in the dma transfer 2757215976Sjmallett will be added to the count register. */ 2758215976Sjmallett uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */ 2759215976Sjmallett uint64_t o_ns : 1; /**< Nosnoop For DMA. */ 2760215976Sjmallett uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */ 2761215976Sjmallett uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used. 2762215976Sjmallett '1' use pointer values for address and register 2763215976Sjmallett values for RO, ES, and NS, '0' use register 2764215976Sjmallett values for address and pointer values for 2765215976Sjmallett RO, ES, and NS. */ 2766215976Sjmallett uint64_t csize : 14; /**< The size in words of the DMA Instruction Chunk. 2767215976Sjmallett This value should only be written once. After 2768215976Sjmallett writing this value a new value will not be 2769215976Sjmallett recognized until the end of the DMA I-Chunk is 2770215976Sjmallett reached. */ 2771215976Sjmallett#else 2772215976Sjmallett uint64_t csize : 14; 2773215976Sjmallett uint64_t o_mode : 1; 2774215976Sjmallett uint64_t o_es : 2; 2775215976Sjmallett uint64_t o_ns : 1; 2776215976Sjmallett uint64_t o_ro : 1; 2777215976Sjmallett uint64_t o_add1 : 1; 2778215976Sjmallett uint64_t fpa_que : 3; 2779215976Sjmallett uint64_t dwb_ichk : 9; 2780215976Sjmallett uint64_t dwb_denb : 1; 2781215976Sjmallett uint64_t b0_lend : 1; 2782215976Sjmallett uint64_t dma0_enb : 1; 2783215976Sjmallett uint64_t dma1_enb : 1; 2784215976Sjmallett uint64_t dma2_enb : 1; 2785215976Sjmallett uint64_t dma3_enb : 1; 2786215976Sjmallett uint64_t dma4_enb : 1; 2787215976Sjmallett uint64_t reserved_39_63 : 25; 2788215976Sjmallett#endif 2789215976Sjmallett } cn56xxp1; 2790215976Sjmallett}; 2791215976Sjmalletttypedef union cvmx_npei_dma_control cvmx_npei_dma_control_t; 2792215976Sjmallett 2793215976Sjmallett/** 2794215976Sjmallett * cvmx_npei_dma_pcie_req_num 2795215976Sjmallett * 2796215976Sjmallett * NPEI_DMA_PCIE_REQ_NUM = NPEI DMA PCIE Outstanding Read Request Number 2797215976Sjmallett * 2798215976Sjmallett * Outstanding PCIE read request number for DMAs and Packet, maximum number is 16 2799215976Sjmallett */ 2800232812Sjmallettunion cvmx_npei_dma_pcie_req_num { 2801215976Sjmallett uint64_t u64; 2802232812Sjmallett struct cvmx_npei_dma_pcie_req_num_s { 2803232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2804215976Sjmallett uint64_t dma_arb : 1; /**< DMA_PKT Read Request Arbitration 2805215976Sjmallett - 1: DMA0-4 and PKT are round robin. i.e. 2806215976Sjmallett DMA0-DMA1-DMA2-DMA3-DMA4-PKT... 2807215976Sjmallett - 0: DMA0-4 are round robin, pkt gets selected 2808215976Sjmallett half the time. i.e. 2809215976Sjmallett DMA0-PKT-DMA1-PKT-DMA2-PKT-DMA3-PKT-DMA4-PKT... */ 2810215976Sjmallett uint64_t reserved_53_62 : 10; 2811215976Sjmallett uint64_t pkt_cnt : 5; /**< PKT outstanding PCIE Read Request Number for each 2812215976Sjmallett PCIe port 2813215976Sjmallett When PKT_CNT=x, for each PCIe port, the number 2814215976Sjmallett of outstanding PCIe memory space reads by the PCIe 2815215976Sjmallett packet input/output will not exceed x. 2816215976Sjmallett Valid Number is between 1 and 16 */ 2817215976Sjmallett uint64_t reserved_45_47 : 3; 2818215976Sjmallett uint64_t dma4_cnt : 5; /**< DMA4 outstanding PCIE Read Request Number 2819215976Sjmallett When DMA4_CNT=x, the number of outstanding PCIe 2820215976Sjmallett memory space reads by the PCIe DMA engine 4 2821215976Sjmallett will not exceed x. 2822215976Sjmallett Valid Number is between 1 and 16 */ 2823215976Sjmallett uint64_t reserved_37_39 : 3; 2824215976Sjmallett uint64_t dma3_cnt : 5; /**< DMA3 outstanding PCIE Read Request Number 2825215976Sjmallett When DMA3_CNT=x, the number of outstanding PCIe 2826215976Sjmallett memory space reads by the PCIe DMA engine 3 2827215976Sjmallett will not exceed x. 2828215976Sjmallett Valid Number is between 1 and 16 */ 2829215976Sjmallett uint64_t reserved_29_31 : 3; 2830215976Sjmallett uint64_t dma2_cnt : 5; /**< DMA2 outstanding PCIE Read Request Number 2831215976Sjmallett When DMA2_CNT=x, the number of outstanding PCIe 2832215976Sjmallett memory space reads by the PCIe DMA engine 2 2833215976Sjmallett will not exceed x. 2834215976Sjmallett Valid Number is between 1 and 16 */ 2835215976Sjmallett uint64_t reserved_21_23 : 3; 2836215976Sjmallett uint64_t dma1_cnt : 5; /**< DMA1 outstanding PCIE Read Request Number 2837215976Sjmallett When DMA1_CNT=x, the number of outstanding PCIe 2838215976Sjmallett memory space reads by the PCIe DMA engine 1 2839215976Sjmallett will not exceed x. 2840215976Sjmallett Valid Number is between 1 and 16 */ 2841215976Sjmallett uint64_t reserved_13_15 : 3; 2842215976Sjmallett uint64_t dma0_cnt : 5; /**< DMA0 outstanding PCIE Read Request Number 2843215976Sjmallett When DMA0_CNT=x, the number of outstanding PCIe 2844215976Sjmallett memory space reads by the PCIe DMA engine 0 2845215976Sjmallett will not exceed x. 2846215976Sjmallett Valid Number is between 1 and 16 */ 2847215976Sjmallett uint64_t reserved_5_7 : 3; 2848215976Sjmallett uint64_t dma_cnt : 5; /**< Total outstanding PCIE Read Request Number for each 2849215976Sjmallett PCIe port 2850215976Sjmallett When DMA_CNT=x, for each PCIe port, the total 2851215976Sjmallett number of outstanding PCIe memory space reads 2852215976Sjmallett by the PCIe DMA engines and packet input/output 2853215976Sjmallett will not exceed x. 2854215976Sjmallett Valid Number is between 1 and 16 */ 2855215976Sjmallett#else 2856215976Sjmallett uint64_t dma_cnt : 5; 2857215976Sjmallett uint64_t reserved_5_7 : 3; 2858215976Sjmallett uint64_t dma0_cnt : 5; 2859215976Sjmallett uint64_t reserved_13_15 : 3; 2860215976Sjmallett uint64_t dma1_cnt : 5; 2861215976Sjmallett uint64_t reserved_21_23 : 3; 2862215976Sjmallett uint64_t dma2_cnt : 5; 2863215976Sjmallett uint64_t reserved_29_31 : 3; 2864215976Sjmallett uint64_t dma3_cnt : 5; 2865215976Sjmallett uint64_t reserved_37_39 : 3; 2866215976Sjmallett uint64_t dma4_cnt : 5; 2867215976Sjmallett uint64_t reserved_45_47 : 3; 2868215976Sjmallett uint64_t pkt_cnt : 5; 2869215976Sjmallett uint64_t reserved_53_62 : 10; 2870215976Sjmallett uint64_t dma_arb : 1; 2871215976Sjmallett#endif 2872215976Sjmallett } s; 2873215976Sjmallett struct cvmx_npei_dma_pcie_req_num_s cn52xx; 2874215976Sjmallett struct cvmx_npei_dma_pcie_req_num_s cn56xx; 2875215976Sjmallett}; 2876215976Sjmalletttypedef union cvmx_npei_dma_pcie_req_num cvmx_npei_dma_pcie_req_num_t; 2877215976Sjmallett 2878215976Sjmallett/** 2879215976Sjmallett * cvmx_npei_dma_state1 2880215976Sjmallett * 2881215976Sjmallett * NPEI_DMA_STATE1 = NPI's DMA State 1 2882215976Sjmallett * 2883215976Sjmallett * Results from DMA state register 1 2884215976Sjmallett */ 2885232812Sjmallettunion cvmx_npei_dma_state1 { 2886215976Sjmallett uint64_t u64; 2887232812Sjmallett struct cvmx_npei_dma_state1_s { 2888232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2889215976Sjmallett uint64_t reserved_40_63 : 24; 2890215976Sjmallett uint64_t d4_dwe : 8; /**< DMA4 PICe Write State */ 2891215976Sjmallett uint64_t d3_dwe : 8; /**< DMA3 PICe Write State */ 2892215976Sjmallett uint64_t d2_dwe : 8; /**< DMA2 PICe Write State */ 2893215976Sjmallett uint64_t d1_dwe : 8; /**< DMA1 PICe Write State */ 2894215976Sjmallett uint64_t d0_dwe : 8; /**< DMA0 PICe Write State */ 2895215976Sjmallett#else 2896215976Sjmallett uint64_t d0_dwe : 8; 2897215976Sjmallett uint64_t d1_dwe : 8; 2898215976Sjmallett uint64_t d2_dwe : 8; 2899215976Sjmallett uint64_t d3_dwe : 8; 2900215976Sjmallett uint64_t d4_dwe : 8; 2901215976Sjmallett uint64_t reserved_40_63 : 24; 2902215976Sjmallett#endif 2903215976Sjmallett } s; 2904215976Sjmallett struct cvmx_npei_dma_state1_s cn52xx; 2905215976Sjmallett}; 2906215976Sjmalletttypedef union cvmx_npei_dma_state1 cvmx_npei_dma_state1_t; 2907215976Sjmallett 2908215976Sjmallett/** 2909215976Sjmallett * cvmx_npei_dma_state1_p1 2910215976Sjmallett * 2911215976Sjmallett * NPEI_DMA_STATE1_P1 = NPEI DMA Request and Instruction State 2912215976Sjmallett * 2913215976Sjmallett * DMA engine Debug information. 2914215976Sjmallett */ 2915232812Sjmallettunion cvmx_npei_dma_state1_p1 { 2916215976Sjmallett uint64_t u64; 2917232812Sjmallett struct cvmx_npei_dma_state1_p1_s { 2918232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2919215976Sjmallett uint64_t reserved_60_63 : 4; 2920215976Sjmallett uint64_t d0_difst : 7; /**< DMA engine 0 dif instruction read state */ 2921215976Sjmallett uint64_t d1_difst : 7; /**< DMA engine 1 dif instruction read state */ 2922215976Sjmallett uint64_t d2_difst : 7; /**< DMA engine 2 dif instruction read state */ 2923215976Sjmallett uint64_t d3_difst : 7; /**< DMA engine 3 dif instruction read state */ 2924215976Sjmallett uint64_t d4_difst : 7; /**< DMA engine 4 dif instruction read state */ 2925215976Sjmallett uint64_t d0_reqst : 5; /**< DMA engine 0 request data state */ 2926215976Sjmallett uint64_t d1_reqst : 5; /**< DMA engine 1 request data state */ 2927215976Sjmallett uint64_t d2_reqst : 5; /**< DMA engine 2 request data state */ 2928215976Sjmallett uint64_t d3_reqst : 5; /**< DMA engine 3 request data state */ 2929215976Sjmallett uint64_t d4_reqst : 5; /**< DMA engine 4 request data state */ 2930215976Sjmallett#else 2931215976Sjmallett uint64_t d4_reqst : 5; 2932215976Sjmallett uint64_t d3_reqst : 5; 2933215976Sjmallett uint64_t d2_reqst : 5; 2934215976Sjmallett uint64_t d1_reqst : 5; 2935215976Sjmallett uint64_t d0_reqst : 5; 2936215976Sjmallett uint64_t d4_difst : 7; 2937215976Sjmallett uint64_t d3_difst : 7; 2938215976Sjmallett uint64_t d2_difst : 7; 2939215976Sjmallett uint64_t d1_difst : 7; 2940215976Sjmallett uint64_t d0_difst : 7; 2941215976Sjmallett uint64_t reserved_60_63 : 4; 2942215976Sjmallett#endif 2943215976Sjmallett } s; 2944232812Sjmallett struct cvmx_npei_dma_state1_p1_cn52xxp1 { 2945232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2946215976Sjmallett uint64_t reserved_60_63 : 4; 2947215976Sjmallett uint64_t d0_difst : 7; /**< DMA engine 0 dif instruction read state */ 2948215976Sjmallett uint64_t d1_difst : 7; /**< DMA engine 1 dif instruction read state */ 2949215976Sjmallett uint64_t d2_difst : 7; /**< DMA engine 2 dif instruction read state */ 2950215976Sjmallett uint64_t d3_difst : 7; /**< DMA engine 3 dif instruction read state */ 2951215976Sjmallett uint64_t reserved_25_31 : 7; 2952215976Sjmallett uint64_t d0_reqst : 5; /**< DMA engine 0 request data state */ 2953215976Sjmallett uint64_t d1_reqst : 5; /**< DMA engine 1 request data state */ 2954215976Sjmallett uint64_t d2_reqst : 5; /**< DMA engine 2 request data state */ 2955215976Sjmallett uint64_t d3_reqst : 5; /**< DMA engine 3 request data state */ 2956215976Sjmallett uint64_t reserved_0_4 : 5; 2957215976Sjmallett#else 2958215976Sjmallett uint64_t reserved_0_4 : 5; 2959215976Sjmallett uint64_t d3_reqst : 5; 2960215976Sjmallett uint64_t d2_reqst : 5; 2961215976Sjmallett uint64_t d1_reqst : 5; 2962215976Sjmallett uint64_t d0_reqst : 5; 2963215976Sjmallett uint64_t reserved_25_31 : 7; 2964215976Sjmallett uint64_t d3_difst : 7; 2965215976Sjmallett uint64_t d2_difst : 7; 2966215976Sjmallett uint64_t d1_difst : 7; 2967215976Sjmallett uint64_t d0_difst : 7; 2968215976Sjmallett uint64_t reserved_60_63 : 4; 2969215976Sjmallett#endif 2970215976Sjmallett } cn52xxp1; 2971215976Sjmallett struct cvmx_npei_dma_state1_p1_s cn56xxp1; 2972215976Sjmallett}; 2973215976Sjmalletttypedef union cvmx_npei_dma_state1_p1 cvmx_npei_dma_state1_p1_t; 2974215976Sjmallett 2975215976Sjmallett/** 2976215976Sjmallett * cvmx_npei_dma_state2 2977215976Sjmallett * 2978215976Sjmallett * NPEI_DMA_STATE2 = NPI's DMA State 2 2979215976Sjmallett * 2980215976Sjmallett * Results from DMA state register 2 2981215976Sjmallett */ 2982232812Sjmallettunion cvmx_npei_dma_state2 { 2983215976Sjmallett uint64_t u64; 2984232812Sjmallett struct cvmx_npei_dma_state2_s { 2985232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2986215976Sjmallett uint64_t reserved_28_63 : 36; 2987215976Sjmallett uint64_t ndwe : 4; /**< DMA L2C Write State */ 2988215976Sjmallett uint64_t reserved_21_23 : 3; 2989215976Sjmallett uint64_t ndre : 5; /**< DMA L2C Read State */ 2990215976Sjmallett uint64_t reserved_10_15 : 6; 2991215976Sjmallett uint64_t prd : 10; /**< DMA PICe Read State */ 2992215976Sjmallett#else 2993215976Sjmallett uint64_t prd : 10; 2994215976Sjmallett uint64_t reserved_10_15 : 6; 2995215976Sjmallett uint64_t ndre : 5; 2996215976Sjmallett uint64_t reserved_21_23 : 3; 2997215976Sjmallett uint64_t ndwe : 4; 2998215976Sjmallett uint64_t reserved_28_63 : 36; 2999215976Sjmallett#endif 3000215976Sjmallett } s; 3001215976Sjmallett struct cvmx_npei_dma_state2_s cn52xx; 3002215976Sjmallett}; 3003215976Sjmalletttypedef union cvmx_npei_dma_state2 cvmx_npei_dma_state2_t; 3004215976Sjmallett 3005215976Sjmallett/** 3006215976Sjmallett * cvmx_npei_dma_state2_p1 3007215976Sjmallett * 3008215976Sjmallett * NPEI_DMA_STATE2_P1 = NPEI DMA Instruction Fetch State 3009215976Sjmallett * 3010215976Sjmallett * DMA engine Debug information. 3011215976Sjmallett */ 3012232812Sjmallettunion cvmx_npei_dma_state2_p1 { 3013215976Sjmallett uint64_t u64; 3014232812Sjmallett struct cvmx_npei_dma_state2_p1_s { 3015232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3016215976Sjmallett uint64_t reserved_45_63 : 19; 3017215976Sjmallett uint64_t d0_dffst : 9; /**< DMA engine 0 dif instruction fetch state */ 3018215976Sjmallett uint64_t d1_dffst : 9; /**< DMA engine 1 dif instruction fetch state */ 3019215976Sjmallett uint64_t d2_dffst : 9; /**< DMA engine 2 dif instruction fetch state */ 3020215976Sjmallett uint64_t d3_dffst : 9; /**< DMA engine 3 dif instruction fetch state */ 3021215976Sjmallett uint64_t d4_dffst : 9; /**< DMA engine 4 dif instruction fetch state */ 3022215976Sjmallett#else 3023215976Sjmallett uint64_t d4_dffst : 9; 3024215976Sjmallett uint64_t d3_dffst : 9; 3025215976Sjmallett uint64_t d2_dffst : 9; 3026215976Sjmallett uint64_t d1_dffst : 9; 3027215976Sjmallett uint64_t d0_dffst : 9; 3028215976Sjmallett uint64_t reserved_45_63 : 19; 3029215976Sjmallett#endif 3030215976Sjmallett } s; 3031232812Sjmallett struct cvmx_npei_dma_state2_p1_cn52xxp1 { 3032232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3033215976Sjmallett uint64_t reserved_45_63 : 19; 3034215976Sjmallett uint64_t d0_dffst : 9; /**< DMA engine 0 dif instruction fetch state */ 3035215976Sjmallett uint64_t d1_dffst : 9; /**< DMA engine 1 dif instruction fetch state */ 3036215976Sjmallett uint64_t d2_dffst : 9; /**< DMA engine 2 dif instruction fetch state */ 3037215976Sjmallett uint64_t d3_dffst : 9; /**< DMA engine 3 dif instruction fetch state */ 3038215976Sjmallett uint64_t reserved_0_8 : 9; 3039215976Sjmallett#else 3040215976Sjmallett uint64_t reserved_0_8 : 9; 3041215976Sjmallett uint64_t d3_dffst : 9; 3042215976Sjmallett uint64_t d2_dffst : 9; 3043215976Sjmallett uint64_t d1_dffst : 9; 3044215976Sjmallett uint64_t d0_dffst : 9; 3045215976Sjmallett uint64_t reserved_45_63 : 19; 3046215976Sjmallett#endif 3047215976Sjmallett } cn52xxp1; 3048215976Sjmallett struct cvmx_npei_dma_state2_p1_s cn56xxp1; 3049215976Sjmallett}; 3050215976Sjmalletttypedef union cvmx_npei_dma_state2_p1 cvmx_npei_dma_state2_p1_t; 3051215976Sjmallett 3052215976Sjmallett/** 3053215976Sjmallett * cvmx_npei_dma_state3_p1 3054215976Sjmallett * 3055215976Sjmallett * NPEI_DMA_STATE3_P1 = NPEI DMA DRE State 3056215976Sjmallett * 3057215976Sjmallett * DMA engine Debug information. 3058215976Sjmallett */ 3059232812Sjmallettunion cvmx_npei_dma_state3_p1 { 3060215976Sjmallett uint64_t u64; 3061232812Sjmallett struct cvmx_npei_dma_state3_p1_s { 3062232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3063215976Sjmallett uint64_t reserved_60_63 : 4; 3064215976Sjmallett uint64_t d0_drest : 15; /**< DMA engine 0 dre state */ 3065215976Sjmallett uint64_t d1_drest : 15; /**< DMA engine 1 dre state */ 3066215976Sjmallett uint64_t d2_drest : 15; /**< DMA engine 2 dre state */ 3067215976Sjmallett uint64_t d3_drest : 15; /**< DMA engine 3 dre state */ 3068215976Sjmallett#else 3069215976Sjmallett uint64_t d3_drest : 15; 3070215976Sjmallett uint64_t d2_drest : 15; 3071215976Sjmallett uint64_t d1_drest : 15; 3072215976Sjmallett uint64_t d0_drest : 15; 3073215976Sjmallett uint64_t reserved_60_63 : 4; 3074215976Sjmallett#endif 3075215976Sjmallett } s; 3076215976Sjmallett struct cvmx_npei_dma_state3_p1_s cn52xxp1; 3077215976Sjmallett struct cvmx_npei_dma_state3_p1_s cn56xxp1; 3078215976Sjmallett}; 3079215976Sjmalletttypedef union cvmx_npei_dma_state3_p1 cvmx_npei_dma_state3_p1_t; 3080215976Sjmallett 3081215976Sjmallett/** 3082215976Sjmallett * cvmx_npei_dma_state4_p1 3083215976Sjmallett * 3084215976Sjmallett * NPEI_DMA_STATE4_P1 = NPEI DMA DWE State 3085215976Sjmallett * 3086215976Sjmallett * DMA engine Debug information. 3087215976Sjmallett */ 3088232812Sjmallettunion cvmx_npei_dma_state4_p1 { 3089215976Sjmallett uint64_t u64; 3090232812Sjmallett struct cvmx_npei_dma_state4_p1_s { 3091232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3092215976Sjmallett uint64_t reserved_52_63 : 12; 3093215976Sjmallett uint64_t d0_dwest : 13; /**< DMA engine 0 dwe state */ 3094215976Sjmallett uint64_t d1_dwest : 13; /**< DMA engine 1 dwe state */ 3095215976Sjmallett uint64_t d2_dwest : 13; /**< DMA engine 2 dwe state */ 3096215976Sjmallett uint64_t d3_dwest : 13; /**< DMA engine 3 dwe state */ 3097215976Sjmallett#else 3098215976Sjmallett uint64_t d3_dwest : 13; 3099215976Sjmallett uint64_t d2_dwest : 13; 3100215976Sjmallett uint64_t d1_dwest : 13; 3101215976Sjmallett uint64_t d0_dwest : 13; 3102215976Sjmallett uint64_t reserved_52_63 : 12; 3103215976Sjmallett#endif 3104215976Sjmallett } s; 3105215976Sjmallett struct cvmx_npei_dma_state4_p1_s cn52xxp1; 3106215976Sjmallett struct cvmx_npei_dma_state4_p1_s cn56xxp1; 3107215976Sjmallett}; 3108215976Sjmalletttypedef union cvmx_npei_dma_state4_p1 cvmx_npei_dma_state4_p1_t; 3109215976Sjmallett 3110215976Sjmallett/** 3111215976Sjmallett * cvmx_npei_dma_state5_p1 3112215976Sjmallett * 3113215976Sjmallett * NPEI_DMA_STATE5_P1 = NPEI DMA DWE and DRE State 3114215976Sjmallett * 3115215976Sjmallett * DMA engine Debug information. 3116215976Sjmallett */ 3117232812Sjmallettunion cvmx_npei_dma_state5_p1 { 3118215976Sjmallett uint64_t u64; 3119232812Sjmallett struct cvmx_npei_dma_state5_p1_s { 3120232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3121215976Sjmallett uint64_t reserved_28_63 : 36; 3122215976Sjmallett uint64_t d4_drest : 15; /**< DMA engine 4 dre state */ 3123215976Sjmallett uint64_t d4_dwest : 13; /**< DMA engine 4 dwe state */ 3124215976Sjmallett#else 3125215976Sjmallett uint64_t d4_dwest : 13; 3126215976Sjmallett uint64_t d4_drest : 15; 3127215976Sjmallett uint64_t reserved_28_63 : 36; 3128215976Sjmallett#endif 3129215976Sjmallett } s; 3130215976Sjmallett struct cvmx_npei_dma_state5_p1_s cn56xxp1; 3131215976Sjmallett}; 3132215976Sjmalletttypedef union cvmx_npei_dma_state5_p1 cvmx_npei_dma_state5_p1_t; 3133215976Sjmallett 3134215976Sjmallett/** 3135215976Sjmallett * cvmx_npei_int_a_enb 3136215976Sjmallett * 3137215976Sjmallett * NPEI_INTERRUPT_A_ENB = NPI's Interrupt A Enable Register 3138215976Sjmallett * 3139215976Sjmallett * Used to allow the generation of interrupts (MSI/INTA) to the PCIe CoresUsed to enable the various interrupting conditions of NPEI 3140215976Sjmallett */ 3141232812Sjmallettunion cvmx_npei_int_a_enb { 3142215976Sjmallett uint64_t u64; 3143232812Sjmallett struct cvmx_npei_int_a_enb_s { 3144232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3145215976Sjmallett uint64_t reserved_10_63 : 54; 3146215976Sjmallett uint64_t pout_err : 1; /**< Enables NPEI_INT_A_SUM[9] to generate an 3147215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3148215976Sjmallett uint64_t pin_bp : 1; /**< Enables NPEI_INT_A_SUM[8] to generate an 3149215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3150215976Sjmallett uint64_t p1_rdlk : 1; /**< Enables NPEI_INT_A_SUM[7] to generate an 3151215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3152215976Sjmallett uint64_t p0_rdlk : 1; /**< Enables NPEI_INT_A_SUM[6] to generate an 3153215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3154215976Sjmallett uint64_t pgl_err : 1; /**< Enables NPEI_INT_A_SUM[5] to generate an 3155215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3156215976Sjmallett uint64_t pdi_err : 1; /**< Enables NPEI_INT_A_SUM[4] to generate an 3157215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3158215976Sjmallett uint64_t pop_err : 1; /**< Enables NPEI_INT_A_SUM[3] to generate an 3159215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3160215976Sjmallett uint64_t pins_err : 1; /**< Enables NPEI_INT_A_SUM[2] to generate an 3161215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3162215976Sjmallett uint64_t dma1_cpl : 1; /**< Enables NPEI_INT_A_SUM[1] to generate an 3163215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3164215976Sjmallett uint64_t dma0_cpl : 1; /**< Enables NPEI_INT_A_SUM[0] to generate an 3165215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3166215976Sjmallett#else 3167215976Sjmallett uint64_t dma0_cpl : 1; 3168215976Sjmallett uint64_t dma1_cpl : 1; 3169215976Sjmallett uint64_t pins_err : 1; 3170215976Sjmallett uint64_t pop_err : 1; 3171215976Sjmallett uint64_t pdi_err : 1; 3172215976Sjmallett uint64_t pgl_err : 1; 3173215976Sjmallett uint64_t p0_rdlk : 1; 3174215976Sjmallett uint64_t p1_rdlk : 1; 3175215976Sjmallett uint64_t pin_bp : 1; 3176215976Sjmallett uint64_t pout_err : 1; 3177215976Sjmallett uint64_t reserved_10_63 : 54; 3178215976Sjmallett#endif 3179215976Sjmallett } s; 3180215976Sjmallett struct cvmx_npei_int_a_enb_s cn52xx; 3181232812Sjmallett struct cvmx_npei_int_a_enb_cn52xxp1 { 3182232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3183215976Sjmallett uint64_t reserved_2_63 : 62; 3184215976Sjmallett uint64_t dma1_cpl : 1; /**< Enables NPEI_INT_A_SUM[1] to generate an 3185215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3186215976Sjmallett uint64_t dma0_cpl : 1; /**< Enables NPEI_INT_A_SUM[0] to generate an 3187215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3188215976Sjmallett#else 3189215976Sjmallett uint64_t dma0_cpl : 1; 3190215976Sjmallett uint64_t dma1_cpl : 1; 3191215976Sjmallett uint64_t reserved_2_63 : 62; 3192215976Sjmallett#endif 3193215976Sjmallett } cn52xxp1; 3194215976Sjmallett struct cvmx_npei_int_a_enb_s cn56xx; 3195215976Sjmallett}; 3196215976Sjmalletttypedef union cvmx_npei_int_a_enb cvmx_npei_int_a_enb_t; 3197215976Sjmallett 3198215976Sjmallett/** 3199215976Sjmallett * cvmx_npei_int_a_enb2 3200215976Sjmallett * 3201215976Sjmallett * NPEI_INTERRUPT_A_ENB2 = NPEI's Interrupt A Enable2 Register 3202215976Sjmallett * 3203215976Sjmallett * Used to enable the various interrupting conditions of NPEI 3204215976Sjmallett */ 3205232812Sjmallettunion cvmx_npei_int_a_enb2 { 3206215976Sjmallett uint64_t u64; 3207232812Sjmallett struct cvmx_npei_int_a_enb2_s { 3208232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3209215976Sjmallett uint64_t reserved_10_63 : 54; 3210215976Sjmallett uint64_t pout_err : 1; /**< Enables NPEI_INT_A_SUM[9] to generate an 3211215976Sjmallett interrupt on the RSL. */ 3212215976Sjmallett uint64_t pin_bp : 1; /**< Enables NPEI_INT_A_SUM[8] to generate an 3213215976Sjmallett interrupt on the RSL. */ 3214215976Sjmallett uint64_t p1_rdlk : 1; /**< Enables NPEI_INT_A_SUM[7] to generate an 3215215976Sjmallett interrupt on the RSL. */ 3216215976Sjmallett uint64_t p0_rdlk : 1; /**< Enables NPEI_INT_A_SUM[6] to generate an 3217215976Sjmallett interrupt on the RSL. */ 3218215976Sjmallett uint64_t pgl_err : 1; /**< Enables NPEI_INT_A_SUM[5] to generate an 3219215976Sjmallett interrupt on the RSL. */ 3220215976Sjmallett uint64_t pdi_err : 1; /**< Enables NPEI_INT_A_SUM[4] to generate an 3221215976Sjmallett interrupt on the RSL. */ 3222215976Sjmallett uint64_t pop_err : 1; /**< Enables NPEI_INT_A_SUM[3] to generate an 3223215976Sjmallett interrupt on the RSL. */ 3224215976Sjmallett uint64_t pins_err : 1; /**< Enables NPEI_INT_A_SUM[2] to generate an 3225215976Sjmallett interrupt on the RSL. */ 3226215976Sjmallett uint64_t dma1_cpl : 1; /**< Enables NPEI_INT_A_SUM[1] to generate an 3227215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3228215976Sjmallett uint64_t dma0_cpl : 1; /**< Enables NPEI_INT_A_SUM[0] to generate an 3229215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3230215976Sjmallett#else 3231215976Sjmallett uint64_t dma0_cpl : 1; 3232215976Sjmallett uint64_t dma1_cpl : 1; 3233215976Sjmallett uint64_t pins_err : 1; 3234215976Sjmallett uint64_t pop_err : 1; 3235215976Sjmallett uint64_t pdi_err : 1; 3236215976Sjmallett uint64_t pgl_err : 1; 3237215976Sjmallett uint64_t p0_rdlk : 1; 3238215976Sjmallett uint64_t p1_rdlk : 1; 3239215976Sjmallett uint64_t pin_bp : 1; 3240215976Sjmallett uint64_t pout_err : 1; 3241215976Sjmallett uint64_t reserved_10_63 : 54; 3242215976Sjmallett#endif 3243215976Sjmallett } s; 3244215976Sjmallett struct cvmx_npei_int_a_enb2_s cn52xx; 3245232812Sjmallett struct cvmx_npei_int_a_enb2_cn52xxp1 { 3246232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3247215976Sjmallett uint64_t reserved_2_63 : 62; 3248215976Sjmallett uint64_t dma1_cpl : 1; /**< Enables NPEI_INT_A_SUM[1] to generate an 3249215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3250215976Sjmallett uint64_t dma0_cpl : 1; /**< Enables NPEI_INT_A_SUM[0] to generate an 3251215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3252215976Sjmallett#else 3253215976Sjmallett uint64_t dma0_cpl : 1; 3254215976Sjmallett uint64_t dma1_cpl : 1; 3255215976Sjmallett uint64_t reserved_2_63 : 62; 3256215976Sjmallett#endif 3257215976Sjmallett } cn52xxp1; 3258215976Sjmallett struct cvmx_npei_int_a_enb2_s cn56xx; 3259215976Sjmallett}; 3260215976Sjmalletttypedef union cvmx_npei_int_a_enb2 cvmx_npei_int_a_enb2_t; 3261215976Sjmallett 3262215976Sjmallett/** 3263215976Sjmallett * cvmx_npei_int_a_sum 3264215976Sjmallett * 3265215976Sjmallett * NPEI_INTERRUPT_A_SUM = NPI Interrupt A Summary Register 3266215976Sjmallett * 3267215976Sjmallett * Set when an interrupt condition occurs, write '1' to clear. When an interrupt bitin this register is set and 3268215976Sjmallett * the cooresponding bit in the NPEI_INT_A_ENB register is set, then NPEI_INT_SUM[61] will be set. 3269215976Sjmallett */ 3270232812Sjmallettunion cvmx_npei_int_a_sum { 3271215976Sjmallett uint64_t u64; 3272232812Sjmallett struct cvmx_npei_int_a_sum_s { 3273232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3274215976Sjmallett uint64_t reserved_10_63 : 54; 3275215976Sjmallett uint64_t pout_err : 1; /**< Set when PKO sends packet data with the error bit 3276215976Sjmallett set. */ 3277215976Sjmallett uint64_t pin_bp : 1; /**< Packet input count has exceeded the WMARK. 3278215976Sjmallett See NPEI_PKT_IN_BP */ 3279215976Sjmallett uint64_t p1_rdlk : 1; /**< PCIe port 1 received a read lock. */ 3280215976Sjmallett uint64_t p0_rdlk : 1; /**< PCIe port 0 received a read lock. */ 3281215976Sjmallett uint64_t pgl_err : 1; /**< When a read error occurs on a packet gather list 3282215976Sjmallett read this bit is set. */ 3283215976Sjmallett uint64_t pdi_err : 1; /**< When a read error occurs on a packet data read 3284215976Sjmallett this bit is set. */ 3285215976Sjmallett uint64_t pop_err : 1; /**< When a read error occurs on a packet scatter 3286215976Sjmallett pointer pair this bit is set. */ 3287215976Sjmallett uint64_t pins_err : 1; /**< When a read error occurs on a packet instruction 3288215976Sjmallett this bit is set. */ 3289215976Sjmallett uint64_t dma1_cpl : 1; /**< Set each time any PCIe DMA engine recieves a UR/CA 3290215976Sjmallett response from PCIe Port 1 */ 3291215976Sjmallett uint64_t dma0_cpl : 1; /**< Set each time any PCIe DMA engine recieves a UR/CA 3292215976Sjmallett response from PCIe Port 0 */ 3293215976Sjmallett#else 3294215976Sjmallett uint64_t dma0_cpl : 1; 3295215976Sjmallett uint64_t dma1_cpl : 1; 3296215976Sjmallett uint64_t pins_err : 1; 3297215976Sjmallett uint64_t pop_err : 1; 3298215976Sjmallett uint64_t pdi_err : 1; 3299215976Sjmallett uint64_t pgl_err : 1; 3300215976Sjmallett uint64_t p0_rdlk : 1; 3301215976Sjmallett uint64_t p1_rdlk : 1; 3302215976Sjmallett uint64_t pin_bp : 1; 3303215976Sjmallett uint64_t pout_err : 1; 3304215976Sjmallett uint64_t reserved_10_63 : 54; 3305215976Sjmallett#endif 3306215976Sjmallett } s; 3307215976Sjmallett struct cvmx_npei_int_a_sum_s cn52xx; 3308232812Sjmallett struct cvmx_npei_int_a_sum_cn52xxp1 { 3309232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3310215976Sjmallett uint64_t reserved_2_63 : 62; 3311215976Sjmallett uint64_t dma1_cpl : 1; /**< Set each time any PCIe DMA engine recieves a UR/CA 3312215976Sjmallett response from PCIe Port 1 */ 3313215976Sjmallett uint64_t dma0_cpl : 1; /**< Set each time any PCIe DMA engine recieves a UR/CA 3314215976Sjmallett response from PCIe Port 0 */ 3315215976Sjmallett#else 3316215976Sjmallett uint64_t dma0_cpl : 1; 3317215976Sjmallett uint64_t dma1_cpl : 1; 3318215976Sjmallett uint64_t reserved_2_63 : 62; 3319215976Sjmallett#endif 3320215976Sjmallett } cn52xxp1; 3321215976Sjmallett struct cvmx_npei_int_a_sum_s cn56xx; 3322215976Sjmallett}; 3323215976Sjmalletttypedef union cvmx_npei_int_a_sum cvmx_npei_int_a_sum_t; 3324215976Sjmallett 3325215976Sjmallett/** 3326215976Sjmallett * cvmx_npei_int_enb 3327215976Sjmallett * 3328215976Sjmallett * NPEI_INTERRUPT_ENB = NPI's Interrupt Enable Register 3329215976Sjmallett * 3330215976Sjmallett * Used to allow the generation of interrupts (MSI/INTA) to the PCIe CoresUsed to enable the various interrupting conditions of NPI 3331215976Sjmallett */ 3332232812Sjmallettunion cvmx_npei_int_enb { 3333215976Sjmallett uint64_t u64; 3334232812Sjmallett struct cvmx_npei_int_enb_s { 3335232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3336215976Sjmallett uint64_t mio_inta : 1; /**< Enables NPEI_INT_SUM[63] to generate an 3337215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3338215976Sjmallett uint64_t reserved_62_62 : 1; 3339215976Sjmallett uint64_t int_a : 1; /**< Enables NPEI_INT_SUM[61] to generate an 3340215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3341215976Sjmallett uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an 3342215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3343215976Sjmallett uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an 3344215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3345215976Sjmallett uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an 3346215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3347215976Sjmallett uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an 3348215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3349215976Sjmallett uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an 3350215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3351215976Sjmallett uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an 3352215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3353215976Sjmallett uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an 3354215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3355215976Sjmallett uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an 3356215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3357215976Sjmallett uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an 3358215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3359215976Sjmallett uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an 3360215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3361215976Sjmallett uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an 3362215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3363215976Sjmallett uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an 3364215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3365215976Sjmallett uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an 3366215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3367215976Sjmallett uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an 3368215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3369215976Sjmallett uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an 3370215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3371215976Sjmallett uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an 3372215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3373215976Sjmallett uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an 3374215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3375215976Sjmallett uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an 3376215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3377215976Sjmallett uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an 3378215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3379215976Sjmallett uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an 3380215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3381215976Sjmallett uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an 3382215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3383215976Sjmallett uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an 3384215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3385215976Sjmallett uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an 3386215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3387215976Sjmallett uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an 3388215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3389215976Sjmallett uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an 3390215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3391215976Sjmallett uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an 3392215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3393215976Sjmallett uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an 3394215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3395215976Sjmallett uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an 3396215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3397215976Sjmallett uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an 3398215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3399215976Sjmallett uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an 3400215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3401215976Sjmallett uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an 3402215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3403215976Sjmallett uint64_t crs1_dr : 1; /**< Enables NPEI_INT_SUM[29] to generate an 3404215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3405215976Sjmallett uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an 3406215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3407215976Sjmallett uint64_t crs1_er : 1; /**< Enables NPEI_INT_SUM[27] to generate an 3408215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3409215976Sjmallett uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an 3410215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3411215976Sjmallett uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an 3412215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3413215976Sjmallett uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an 3414215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3415215976Sjmallett uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an 3416215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3417215976Sjmallett uint64_t crs0_dr : 1; /**< Enables NPEI_INT_SUM[22] to generate an 3418215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3419215976Sjmallett uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an 3420215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3421215976Sjmallett uint64_t crs0_er : 1; /**< Enables NPEI_INT_SUM[20] to generate an 3422215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3423215976Sjmallett uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an 3424215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3425215976Sjmallett uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an 3426215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3427215976Sjmallett uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an 3428215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3429215976Sjmallett uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an 3430215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3431215976Sjmallett uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an 3432215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3433215976Sjmallett uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an 3434215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3435215976Sjmallett uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an 3436215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3437215976Sjmallett uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an 3438215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3439215976Sjmallett uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an 3440215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3441215976Sjmallett uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an 3442215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3443215976Sjmallett uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an 3444215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3445215976Sjmallett uint64_t dma4dbo : 1; /**< Enables NPEI_INT_SUM[8] to generate an 3446215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3447215976Sjmallett uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an 3448215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3449215976Sjmallett uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an 3450215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3451215976Sjmallett uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an 3452215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3453215976Sjmallett uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an 3454215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3455215976Sjmallett uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an 3456215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3457215976Sjmallett uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an 3458215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3459215976Sjmallett uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an 3460215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3461215976Sjmallett uint64_t rml_rto : 1; /**< Enables NPEI_INT_SUM[0] to generate an 3462215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3463215976Sjmallett#else 3464215976Sjmallett uint64_t rml_rto : 1; 3465215976Sjmallett uint64_t rml_wto : 1; 3466215976Sjmallett uint64_t bar0_to : 1; 3467215976Sjmallett uint64_t iob2big : 1; 3468215976Sjmallett uint64_t dma0dbo : 1; 3469215976Sjmallett uint64_t dma1dbo : 1; 3470215976Sjmallett uint64_t dma2dbo : 1; 3471215976Sjmallett uint64_t dma3dbo : 1; 3472215976Sjmallett uint64_t dma4dbo : 1; 3473215976Sjmallett uint64_t dma0fi : 1; 3474215976Sjmallett uint64_t dma1fi : 1; 3475215976Sjmallett uint64_t dcnt0 : 1; 3476215976Sjmallett uint64_t dcnt1 : 1; 3477215976Sjmallett uint64_t dtime0 : 1; 3478215976Sjmallett uint64_t dtime1 : 1; 3479215976Sjmallett uint64_t psldbof : 1; 3480215976Sjmallett uint64_t pidbof : 1; 3481215976Sjmallett uint64_t pcnt : 1; 3482215976Sjmallett uint64_t ptime : 1; 3483215976Sjmallett uint64_t c0_aeri : 1; 3484215976Sjmallett uint64_t crs0_er : 1; 3485215976Sjmallett uint64_t c0_se : 1; 3486215976Sjmallett uint64_t crs0_dr : 1; 3487215976Sjmallett uint64_t c0_wake : 1; 3488215976Sjmallett uint64_t c0_pmei : 1; 3489215976Sjmallett uint64_t c0_hpint : 1; 3490215976Sjmallett uint64_t c1_aeri : 1; 3491215976Sjmallett uint64_t crs1_er : 1; 3492215976Sjmallett uint64_t c1_se : 1; 3493215976Sjmallett uint64_t crs1_dr : 1; 3494215976Sjmallett uint64_t c1_wake : 1; 3495215976Sjmallett uint64_t c1_pmei : 1; 3496215976Sjmallett uint64_t c1_hpint : 1; 3497215976Sjmallett uint64_t c0_up_b0 : 1; 3498215976Sjmallett uint64_t c0_up_b1 : 1; 3499215976Sjmallett uint64_t c0_up_b2 : 1; 3500215976Sjmallett uint64_t c0_up_wi : 1; 3501215976Sjmallett uint64_t c0_up_bx : 1; 3502215976Sjmallett uint64_t c0_un_b0 : 1; 3503215976Sjmallett uint64_t c0_un_b1 : 1; 3504215976Sjmallett uint64_t c0_un_b2 : 1; 3505215976Sjmallett uint64_t c0_un_wi : 1; 3506215976Sjmallett uint64_t c0_un_bx : 1; 3507215976Sjmallett uint64_t c1_up_b0 : 1; 3508215976Sjmallett uint64_t c1_up_b1 : 1; 3509215976Sjmallett uint64_t c1_up_b2 : 1; 3510215976Sjmallett uint64_t c1_up_wi : 1; 3511215976Sjmallett uint64_t c1_up_bx : 1; 3512215976Sjmallett uint64_t c1_un_b0 : 1; 3513215976Sjmallett uint64_t c1_un_b1 : 1; 3514215976Sjmallett uint64_t c1_un_b2 : 1; 3515215976Sjmallett uint64_t c1_un_wi : 1; 3516215976Sjmallett uint64_t c1_un_bx : 1; 3517215976Sjmallett uint64_t c0_un_wf : 1; 3518215976Sjmallett uint64_t c1_un_wf : 1; 3519215976Sjmallett uint64_t c0_up_wf : 1; 3520215976Sjmallett uint64_t c1_up_wf : 1; 3521215976Sjmallett uint64_t c0_exc : 1; 3522215976Sjmallett uint64_t c1_exc : 1; 3523215976Sjmallett uint64_t c0_ldwn : 1; 3524215976Sjmallett uint64_t c1_ldwn : 1; 3525215976Sjmallett uint64_t int_a : 1; 3526215976Sjmallett uint64_t reserved_62_62 : 1; 3527215976Sjmallett uint64_t mio_inta : 1; 3528215976Sjmallett#endif 3529215976Sjmallett } s; 3530215976Sjmallett struct cvmx_npei_int_enb_s cn52xx; 3531232812Sjmallett struct cvmx_npei_int_enb_cn52xxp1 { 3532232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3533215976Sjmallett uint64_t mio_inta : 1; /**< Enables NPEI_INT_SUM[63] to generate an 3534215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3535215976Sjmallett uint64_t reserved_62_62 : 1; 3536215976Sjmallett uint64_t int_a : 1; /**< Enables NPEI_INT_SUM[61] to generate an 3537215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3538215976Sjmallett uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an 3539215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3540215976Sjmallett uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an 3541215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3542215976Sjmallett uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an 3543215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3544215976Sjmallett uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an 3545215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3546215976Sjmallett uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an 3547215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3548215976Sjmallett uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an 3549215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3550215976Sjmallett uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an 3551215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3552215976Sjmallett uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an 3553215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3554215976Sjmallett uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an 3555215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3556215976Sjmallett uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an 3557215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3558215976Sjmallett uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an 3559215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3560215976Sjmallett uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an 3561215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3562215976Sjmallett uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an 3563215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3564215976Sjmallett uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an 3565215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3566215976Sjmallett uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an 3567215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3568215976Sjmallett uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an 3569215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3570215976Sjmallett uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an 3571215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3572215976Sjmallett uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an 3573215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3574215976Sjmallett uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an 3575215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3576215976Sjmallett uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an 3577215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3578215976Sjmallett uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an 3579215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3580215976Sjmallett uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an 3581215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3582215976Sjmallett uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an 3583215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3584215976Sjmallett uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an 3585215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3586215976Sjmallett uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an 3587215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3588215976Sjmallett uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an 3589215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3590215976Sjmallett uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an 3591215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3592215976Sjmallett uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an 3593215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3594215976Sjmallett uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an 3595215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3596215976Sjmallett uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an 3597215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3598215976Sjmallett uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an 3599215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3600215976Sjmallett uint64_t crs1_dr : 1; /**< Enables NPEI_INT_SUM[29] to generate an 3601215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3602215976Sjmallett uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an 3603215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3604215976Sjmallett uint64_t crs1_er : 1; /**< Enables NPEI_INT_SUM[27] to generate an 3605215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3606215976Sjmallett uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an 3607215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3608215976Sjmallett uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an 3609215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3610215976Sjmallett uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an 3611215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3612215976Sjmallett uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an 3613215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3614215976Sjmallett uint64_t crs0_dr : 1; /**< Enables NPEI_INT_SUM[22] to generate an 3615215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3616215976Sjmallett uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an 3617215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3618215976Sjmallett uint64_t crs0_er : 1; /**< Enables NPEI_INT_SUM[20] to generate an 3619215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3620215976Sjmallett uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an 3621215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3622215976Sjmallett uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an 3623215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3624215976Sjmallett uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an 3625215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3626215976Sjmallett uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an 3627215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3628215976Sjmallett uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an 3629215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3630215976Sjmallett uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an 3631215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3632215976Sjmallett uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an 3633215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3634215976Sjmallett uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an 3635215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3636215976Sjmallett uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an 3637215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3638215976Sjmallett uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an 3639215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3640215976Sjmallett uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an 3641215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3642215976Sjmallett uint64_t reserved_8_8 : 1; 3643215976Sjmallett uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an 3644215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3645215976Sjmallett uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an 3646215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3647215976Sjmallett uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an 3648215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3649215976Sjmallett uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an 3650215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3651215976Sjmallett uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an 3652215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3653215976Sjmallett uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an 3654215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3655215976Sjmallett uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an 3656215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3657215976Sjmallett uint64_t rml_rto : 1; /**< Enables NPEI_INT_SUM[0] to generate an 3658215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3659215976Sjmallett#else 3660215976Sjmallett uint64_t rml_rto : 1; 3661215976Sjmallett uint64_t rml_wto : 1; 3662215976Sjmallett uint64_t bar0_to : 1; 3663215976Sjmallett uint64_t iob2big : 1; 3664215976Sjmallett uint64_t dma0dbo : 1; 3665215976Sjmallett uint64_t dma1dbo : 1; 3666215976Sjmallett uint64_t dma2dbo : 1; 3667215976Sjmallett uint64_t dma3dbo : 1; 3668215976Sjmallett uint64_t reserved_8_8 : 1; 3669215976Sjmallett uint64_t dma0fi : 1; 3670215976Sjmallett uint64_t dma1fi : 1; 3671215976Sjmallett uint64_t dcnt0 : 1; 3672215976Sjmallett uint64_t dcnt1 : 1; 3673215976Sjmallett uint64_t dtime0 : 1; 3674215976Sjmallett uint64_t dtime1 : 1; 3675215976Sjmallett uint64_t psldbof : 1; 3676215976Sjmallett uint64_t pidbof : 1; 3677215976Sjmallett uint64_t pcnt : 1; 3678215976Sjmallett uint64_t ptime : 1; 3679215976Sjmallett uint64_t c0_aeri : 1; 3680215976Sjmallett uint64_t crs0_er : 1; 3681215976Sjmallett uint64_t c0_se : 1; 3682215976Sjmallett uint64_t crs0_dr : 1; 3683215976Sjmallett uint64_t c0_wake : 1; 3684215976Sjmallett uint64_t c0_pmei : 1; 3685215976Sjmallett uint64_t c0_hpint : 1; 3686215976Sjmallett uint64_t c1_aeri : 1; 3687215976Sjmallett uint64_t crs1_er : 1; 3688215976Sjmallett uint64_t c1_se : 1; 3689215976Sjmallett uint64_t crs1_dr : 1; 3690215976Sjmallett uint64_t c1_wake : 1; 3691215976Sjmallett uint64_t c1_pmei : 1; 3692215976Sjmallett uint64_t c1_hpint : 1; 3693215976Sjmallett uint64_t c0_up_b0 : 1; 3694215976Sjmallett uint64_t c0_up_b1 : 1; 3695215976Sjmallett uint64_t c0_up_b2 : 1; 3696215976Sjmallett uint64_t c0_up_wi : 1; 3697215976Sjmallett uint64_t c0_up_bx : 1; 3698215976Sjmallett uint64_t c0_un_b0 : 1; 3699215976Sjmallett uint64_t c0_un_b1 : 1; 3700215976Sjmallett uint64_t c0_un_b2 : 1; 3701215976Sjmallett uint64_t c0_un_wi : 1; 3702215976Sjmallett uint64_t c0_un_bx : 1; 3703215976Sjmallett uint64_t c1_up_b0 : 1; 3704215976Sjmallett uint64_t c1_up_b1 : 1; 3705215976Sjmallett uint64_t c1_up_b2 : 1; 3706215976Sjmallett uint64_t c1_up_wi : 1; 3707215976Sjmallett uint64_t c1_up_bx : 1; 3708215976Sjmallett uint64_t c1_un_b0 : 1; 3709215976Sjmallett uint64_t c1_un_b1 : 1; 3710215976Sjmallett uint64_t c1_un_b2 : 1; 3711215976Sjmallett uint64_t c1_un_wi : 1; 3712215976Sjmallett uint64_t c1_un_bx : 1; 3713215976Sjmallett uint64_t c0_un_wf : 1; 3714215976Sjmallett uint64_t c1_un_wf : 1; 3715215976Sjmallett uint64_t c0_up_wf : 1; 3716215976Sjmallett uint64_t c1_up_wf : 1; 3717215976Sjmallett uint64_t c0_exc : 1; 3718215976Sjmallett uint64_t c1_exc : 1; 3719215976Sjmallett uint64_t c0_ldwn : 1; 3720215976Sjmallett uint64_t c1_ldwn : 1; 3721215976Sjmallett uint64_t int_a : 1; 3722215976Sjmallett uint64_t reserved_62_62 : 1; 3723215976Sjmallett uint64_t mio_inta : 1; 3724215976Sjmallett#endif 3725215976Sjmallett } cn52xxp1; 3726215976Sjmallett struct cvmx_npei_int_enb_s cn56xx; 3727232812Sjmallett struct cvmx_npei_int_enb_cn56xxp1 { 3728232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3729215976Sjmallett uint64_t mio_inta : 1; /**< Enables NPEI_INT_SUM[63] to generate an 3730215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3731215976Sjmallett uint64_t reserved_61_62 : 2; 3732215976Sjmallett uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an 3733215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3734215976Sjmallett uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an 3735215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3736215976Sjmallett uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an 3737215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3738215976Sjmallett uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an 3739215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3740215976Sjmallett uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an 3741215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3742215976Sjmallett uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an 3743215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3744215976Sjmallett uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an 3745215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3746215976Sjmallett uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an 3747215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3748215976Sjmallett uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an 3749215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3750215976Sjmallett uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an 3751215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3752215976Sjmallett uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an 3753215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3754215976Sjmallett uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an 3755215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3756215976Sjmallett uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an 3757215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3758215976Sjmallett uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an 3759215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3760215976Sjmallett uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an 3761215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3762215976Sjmallett uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an 3763215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3764215976Sjmallett uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an 3765215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3766215976Sjmallett uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an 3767215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3768215976Sjmallett uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an 3769215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3770215976Sjmallett uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an 3771215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3772215976Sjmallett uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an 3773215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3774215976Sjmallett uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an 3775215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3776215976Sjmallett uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an 3777215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3778215976Sjmallett uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an 3779215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3780215976Sjmallett uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an 3781215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3782215976Sjmallett uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an 3783215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3784215976Sjmallett uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an 3785215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3786215976Sjmallett uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an 3787215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3788215976Sjmallett uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an 3789215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3790215976Sjmallett uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an 3791215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3792215976Sjmallett uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an 3793215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3794215976Sjmallett uint64_t reserved_29_29 : 1; 3795215976Sjmallett uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an 3796215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3797215976Sjmallett uint64_t reserved_27_27 : 1; 3798215976Sjmallett uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an 3799215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3800215976Sjmallett uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an 3801215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3802215976Sjmallett uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an 3803215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3804215976Sjmallett uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an 3805215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3806215976Sjmallett uint64_t reserved_22_22 : 1; 3807215976Sjmallett uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an 3808215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3809215976Sjmallett uint64_t reserved_20_20 : 1; 3810215976Sjmallett uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an 3811215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3812215976Sjmallett uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an 3813215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3814215976Sjmallett uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an 3815215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3816215976Sjmallett uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an 3817215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3818215976Sjmallett uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an 3819215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3820215976Sjmallett uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an 3821215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3822215976Sjmallett uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an 3823215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3824215976Sjmallett uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an 3825215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3826215976Sjmallett uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an 3827215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3828215976Sjmallett uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an 3829215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3830215976Sjmallett uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an 3831215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3832215976Sjmallett uint64_t dma4dbo : 1; /**< Enables NPEI_INT_SUM[8] to generate an 3833215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3834215976Sjmallett uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an 3835215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3836215976Sjmallett uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an 3837215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3838215976Sjmallett uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an 3839215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3840215976Sjmallett uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an 3841215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3842215976Sjmallett uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an 3843215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3844215976Sjmallett uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an 3845215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3846215976Sjmallett uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an 3847215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3848215976Sjmallett uint64_t rml_rto : 1; /**< Enables NPEI_INT_SUM[0] to generate an 3849215976Sjmallett interrupt to the PCIE core for MSI/inta. */ 3850215976Sjmallett#else 3851215976Sjmallett uint64_t rml_rto : 1; 3852215976Sjmallett uint64_t rml_wto : 1; 3853215976Sjmallett uint64_t bar0_to : 1; 3854215976Sjmallett uint64_t iob2big : 1; 3855215976Sjmallett uint64_t dma0dbo : 1; 3856215976Sjmallett uint64_t dma1dbo : 1; 3857215976Sjmallett uint64_t dma2dbo : 1; 3858215976Sjmallett uint64_t dma3dbo : 1; 3859215976Sjmallett uint64_t dma4dbo : 1; 3860215976Sjmallett uint64_t dma0fi : 1; 3861215976Sjmallett uint64_t dma1fi : 1; 3862215976Sjmallett uint64_t dcnt0 : 1; 3863215976Sjmallett uint64_t dcnt1 : 1; 3864215976Sjmallett uint64_t dtime0 : 1; 3865215976Sjmallett uint64_t dtime1 : 1; 3866215976Sjmallett uint64_t psldbof : 1; 3867215976Sjmallett uint64_t pidbof : 1; 3868215976Sjmallett uint64_t pcnt : 1; 3869215976Sjmallett uint64_t ptime : 1; 3870215976Sjmallett uint64_t c0_aeri : 1; 3871215976Sjmallett uint64_t reserved_20_20 : 1; 3872215976Sjmallett uint64_t c0_se : 1; 3873215976Sjmallett uint64_t reserved_22_22 : 1; 3874215976Sjmallett uint64_t c0_wake : 1; 3875215976Sjmallett uint64_t c0_pmei : 1; 3876215976Sjmallett uint64_t c0_hpint : 1; 3877215976Sjmallett uint64_t c1_aeri : 1; 3878215976Sjmallett uint64_t reserved_27_27 : 1; 3879215976Sjmallett uint64_t c1_se : 1; 3880215976Sjmallett uint64_t reserved_29_29 : 1; 3881215976Sjmallett uint64_t c1_wake : 1; 3882215976Sjmallett uint64_t c1_pmei : 1; 3883215976Sjmallett uint64_t c1_hpint : 1; 3884215976Sjmallett uint64_t c0_up_b0 : 1; 3885215976Sjmallett uint64_t c0_up_b1 : 1; 3886215976Sjmallett uint64_t c0_up_b2 : 1; 3887215976Sjmallett uint64_t c0_up_wi : 1; 3888215976Sjmallett uint64_t c0_up_bx : 1; 3889215976Sjmallett uint64_t c0_un_b0 : 1; 3890215976Sjmallett uint64_t c0_un_b1 : 1; 3891215976Sjmallett uint64_t c0_un_b2 : 1; 3892215976Sjmallett uint64_t c0_un_wi : 1; 3893215976Sjmallett uint64_t c0_un_bx : 1; 3894215976Sjmallett uint64_t c1_up_b0 : 1; 3895215976Sjmallett uint64_t c1_up_b1 : 1; 3896215976Sjmallett uint64_t c1_up_b2 : 1; 3897215976Sjmallett uint64_t c1_up_wi : 1; 3898215976Sjmallett uint64_t c1_up_bx : 1; 3899215976Sjmallett uint64_t c1_un_b0 : 1; 3900215976Sjmallett uint64_t c1_un_b1 : 1; 3901215976Sjmallett uint64_t c1_un_b2 : 1; 3902215976Sjmallett uint64_t c1_un_wi : 1; 3903215976Sjmallett uint64_t c1_un_bx : 1; 3904215976Sjmallett uint64_t c0_un_wf : 1; 3905215976Sjmallett uint64_t c1_un_wf : 1; 3906215976Sjmallett uint64_t c0_up_wf : 1; 3907215976Sjmallett uint64_t c1_up_wf : 1; 3908215976Sjmallett uint64_t c0_exc : 1; 3909215976Sjmallett uint64_t c1_exc : 1; 3910215976Sjmallett uint64_t c0_ldwn : 1; 3911215976Sjmallett uint64_t c1_ldwn : 1; 3912215976Sjmallett uint64_t reserved_61_62 : 2; 3913215976Sjmallett uint64_t mio_inta : 1; 3914215976Sjmallett#endif 3915215976Sjmallett } cn56xxp1; 3916215976Sjmallett}; 3917215976Sjmalletttypedef union cvmx_npei_int_enb cvmx_npei_int_enb_t; 3918215976Sjmallett 3919215976Sjmallett/** 3920215976Sjmallett * cvmx_npei_int_enb2 3921215976Sjmallett * 3922215976Sjmallett * NPEI_INTERRUPT_ENB2 = NPI's Interrupt Enable2 Register 3923215976Sjmallett * 3924215976Sjmallett * Used to enable the various interrupting conditions of NPI 3925215976Sjmallett */ 3926232812Sjmallettunion cvmx_npei_int_enb2 { 3927215976Sjmallett uint64_t u64; 3928232812Sjmallett struct cvmx_npei_int_enb2_s { 3929232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3930215976Sjmallett uint64_t reserved_62_63 : 2; 3931215976Sjmallett uint64_t int_a : 1; /**< Enables NPEI_INT_SUM2[61] to generate an 3932215976Sjmallett interrupt on the RSL. */ 3933215976Sjmallett uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an 3934215976Sjmallett interrupt on the RSL. */ 3935215976Sjmallett uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an 3936215976Sjmallett interrupt on the RSL. */ 3937215976Sjmallett uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an 3938215976Sjmallett interrupt on the RSL. */ 3939215976Sjmallett uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an 3940215976Sjmallett interrupt on the RSL. */ 3941215976Sjmallett uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an 3942215976Sjmallett interrupt on the RSL. */ 3943215976Sjmallett uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an 3944215976Sjmallett interrupt on the RSL. */ 3945215976Sjmallett uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an 3946215976Sjmallett interrupt on the RSL. */ 3947215976Sjmallett uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an 3948215976Sjmallett interrupt on the RSL. */ 3949215976Sjmallett uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an 3950215976Sjmallett interrupt on the RSL. */ 3951215976Sjmallett uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an 3952215976Sjmallett interrupt on the RSL. */ 3953215976Sjmallett uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an 3954215976Sjmallett interrupt on the RSL. */ 3955215976Sjmallett uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an 3956215976Sjmallett interrupt on the RSL. */ 3957215976Sjmallett uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an 3958215976Sjmallett interrupt on the RSL. */ 3959215976Sjmallett uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an 3960215976Sjmallett interrupt on the RSL. */ 3961215976Sjmallett uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an 3962215976Sjmallett interrupt on the RSL. */ 3963215976Sjmallett uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an 3964215976Sjmallett interrupt on the RSL. */ 3965215976Sjmallett uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an 3966215976Sjmallett interrupt on the RSL. */ 3967215976Sjmallett uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an 3968215976Sjmallett interrupt on the RSL. */ 3969215976Sjmallett uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an 3970215976Sjmallett interrupt on the RSL. */ 3971215976Sjmallett uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an 3972215976Sjmallett interrupt on the RSL. */ 3973215976Sjmallett uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an 3974215976Sjmallett interrupt on the RSL. */ 3975215976Sjmallett uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an 3976215976Sjmallett interrupt on the RSL. */ 3977215976Sjmallett uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an 3978215976Sjmallett interrupt on the RSL. */ 3979215976Sjmallett uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an 3980215976Sjmallett interrupt on the RSL. */ 3981215976Sjmallett uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an 3982215976Sjmallett interrupt on the RSL. */ 3983215976Sjmallett uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an 3984215976Sjmallett interrupt on the RSL. */ 3985215976Sjmallett uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an 3986215976Sjmallett interrupt on the RSL. */ 3987215976Sjmallett uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an 3988215976Sjmallett interrupt on the RSL. */ 3989215976Sjmallett uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an 3990215976Sjmallett interrupt on the RSL. */ 3991215976Sjmallett uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an 3992215976Sjmallett interrupt on the RSL. */ 3993215976Sjmallett uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an 3994215976Sjmallett interrupt on the RSL. */ 3995215976Sjmallett uint64_t crs1_dr : 1; /**< Enables NPEI_INT_SUM2[29] to generate an 3996215976Sjmallett interrupt on the RSL. */ 3997215976Sjmallett uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an 3998215976Sjmallett interrupt on the RSL. */ 3999215976Sjmallett uint64_t crs1_er : 1; /**< Enables NPEI_INT_SUM2[27] to generate an 4000215976Sjmallett interrupt on the RSL. */ 4001215976Sjmallett uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an 4002215976Sjmallett interrupt on the RSL. */ 4003215976Sjmallett uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an 4004215976Sjmallett interrupt on the RSL. */ 4005215976Sjmallett uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an 4006215976Sjmallett interrupt on the RSL. */ 4007215976Sjmallett uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an 4008215976Sjmallett interrupt on the RSL. */ 4009215976Sjmallett uint64_t crs0_dr : 1; /**< Enables NPEI_INT_SUM2[22] to generate an 4010215976Sjmallett interrupt on the RSL. */ 4011215976Sjmallett uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an 4012215976Sjmallett interrupt on the RSL. */ 4013215976Sjmallett uint64_t crs0_er : 1; /**< Enables NPEI_INT_SUM2[20] to generate an 4014215976Sjmallett interrupt on the RSL. */ 4015215976Sjmallett uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an 4016215976Sjmallett interrupt on the RSL. */ 4017215976Sjmallett uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an 4018215976Sjmallett interrupt on the RSL. */ 4019215976Sjmallett uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an 4020215976Sjmallett interrupt on the RSL. */ 4021215976Sjmallett uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an 4022215976Sjmallett interrupt on the RSL. */ 4023215976Sjmallett uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an 4024215976Sjmallett interrupt on the RSL. */ 4025215976Sjmallett uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an 4026215976Sjmallett interrupt on the RSL. */ 4027215976Sjmallett uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an 4028215976Sjmallett interrupt on the RSL. */ 4029215976Sjmallett uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an 4030215976Sjmallett interrupt on the RSL. */ 4031215976Sjmallett uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an 4032215976Sjmallett interrupt on the RSL. */ 4033215976Sjmallett uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an 4034215976Sjmallett interrupt on the RSL. */ 4035215976Sjmallett uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an 4036215976Sjmallett interrupt on the RSL. */ 4037215976Sjmallett uint64_t dma4dbo : 1; /**< Enables NPEI_INT_SUM[8] to generate an 4038215976Sjmallett interrupt on the RSL. */ 4039215976Sjmallett uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an 4040215976Sjmallett interrupt on the RSL. */ 4041215976Sjmallett uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an 4042215976Sjmallett interrupt on the RSL. */ 4043215976Sjmallett uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an 4044215976Sjmallett interrupt on the RSL. */ 4045215976Sjmallett uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an 4046215976Sjmallett interrupt on the RSL. */ 4047215976Sjmallett uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an 4048215976Sjmallett interrupt on the RSL. */ 4049215976Sjmallett uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an 4050215976Sjmallett interrupt on the RSL. */ 4051215976Sjmallett uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an 4052215976Sjmallett interrupt on the RSL. */ 4053215976Sjmallett uint64_t rml_rto : 1; /**< Enables NPEI_INT_UM[0] to generate an 4054215976Sjmallett interrupt on the RSL. */ 4055215976Sjmallett#else 4056215976Sjmallett uint64_t rml_rto : 1; 4057215976Sjmallett uint64_t rml_wto : 1; 4058215976Sjmallett uint64_t bar0_to : 1; 4059215976Sjmallett uint64_t iob2big : 1; 4060215976Sjmallett uint64_t dma0dbo : 1; 4061215976Sjmallett uint64_t dma1dbo : 1; 4062215976Sjmallett uint64_t dma2dbo : 1; 4063215976Sjmallett uint64_t dma3dbo : 1; 4064215976Sjmallett uint64_t dma4dbo : 1; 4065215976Sjmallett uint64_t dma0fi : 1; 4066215976Sjmallett uint64_t dma1fi : 1; 4067215976Sjmallett uint64_t dcnt0 : 1; 4068215976Sjmallett uint64_t dcnt1 : 1; 4069215976Sjmallett uint64_t dtime0 : 1; 4070215976Sjmallett uint64_t dtime1 : 1; 4071215976Sjmallett uint64_t psldbof : 1; 4072215976Sjmallett uint64_t pidbof : 1; 4073215976Sjmallett uint64_t pcnt : 1; 4074215976Sjmallett uint64_t ptime : 1; 4075215976Sjmallett uint64_t c0_aeri : 1; 4076215976Sjmallett uint64_t crs0_er : 1; 4077215976Sjmallett uint64_t c0_se : 1; 4078215976Sjmallett uint64_t crs0_dr : 1; 4079215976Sjmallett uint64_t c0_wake : 1; 4080215976Sjmallett uint64_t c0_pmei : 1; 4081215976Sjmallett uint64_t c0_hpint : 1; 4082215976Sjmallett uint64_t c1_aeri : 1; 4083215976Sjmallett uint64_t crs1_er : 1; 4084215976Sjmallett uint64_t c1_se : 1; 4085215976Sjmallett uint64_t crs1_dr : 1; 4086215976Sjmallett uint64_t c1_wake : 1; 4087215976Sjmallett uint64_t c1_pmei : 1; 4088215976Sjmallett uint64_t c1_hpint : 1; 4089215976Sjmallett uint64_t c0_up_b0 : 1; 4090215976Sjmallett uint64_t c0_up_b1 : 1; 4091215976Sjmallett uint64_t c0_up_b2 : 1; 4092215976Sjmallett uint64_t c0_up_wi : 1; 4093215976Sjmallett uint64_t c0_up_bx : 1; 4094215976Sjmallett uint64_t c0_un_b0 : 1; 4095215976Sjmallett uint64_t c0_un_b1 : 1; 4096215976Sjmallett uint64_t c0_un_b2 : 1; 4097215976Sjmallett uint64_t c0_un_wi : 1; 4098215976Sjmallett uint64_t c0_un_bx : 1; 4099215976Sjmallett uint64_t c1_up_b0 : 1; 4100215976Sjmallett uint64_t c1_up_b1 : 1; 4101215976Sjmallett uint64_t c1_up_b2 : 1; 4102215976Sjmallett uint64_t c1_up_wi : 1; 4103215976Sjmallett uint64_t c1_up_bx : 1; 4104215976Sjmallett uint64_t c1_un_b0 : 1; 4105215976Sjmallett uint64_t c1_un_b1 : 1; 4106215976Sjmallett uint64_t c1_un_b2 : 1; 4107215976Sjmallett uint64_t c1_un_wi : 1; 4108215976Sjmallett uint64_t c1_un_bx : 1; 4109215976Sjmallett uint64_t c0_un_wf : 1; 4110215976Sjmallett uint64_t c1_un_wf : 1; 4111215976Sjmallett uint64_t c0_up_wf : 1; 4112215976Sjmallett uint64_t c1_up_wf : 1; 4113215976Sjmallett uint64_t c0_exc : 1; 4114215976Sjmallett uint64_t c1_exc : 1; 4115215976Sjmallett uint64_t c0_ldwn : 1; 4116215976Sjmallett uint64_t c1_ldwn : 1; 4117215976Sjmallett uint64_t int_a : 1; 4118215976Sjmallett uint64_t reserved_62_63 : 2; 4119215976Sjmallett#endif 4120215976Sjmallett } s; 4121215976Sjmallett struct cvmx_npei_int_enb2_s cn52xx; 4122232812Sjmallett struct cvmx_npei_int_enb2_cn52xxp1 { 4123232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4124215976Sjmallett uint64_t reserved_62_63 : 2; 4125215976Sjmallett uint64_t int_a : 1; /**< Enables NPEI_INT_SUM2[61] to generate an 4126215976Sjmallett interrupt on the RSL. */ 4127215976Sjmallett uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM2[60] to generate an 4128215976Sjmallett interrupt on the RSL. */ 4129215976Sjmallett uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM2[59] to generate an 4130215976Sjmallett interrupt on the RSL. */ 4131215976Sjmallett uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM2[58] to generate an 4132215976Sjmallett interrupt on the RSL. */ 4133215976Sjmallett uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM2[57] to generate an 4134215976Sjmallett interrupt on the RSL. */ 4135215976Sjmallett uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM2[56] to generate an 4136215976Sjmallett interrupt on the RSL. */ 4137215976Sjmallett uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM2[55] to generate an 4138215976Sjmallett interrupt on the RSL. */ 4139215976Sjmallett uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM2[54] to generate an 4140215976Sjmallett interrupt on the RSL. */ 4141215976Sjmallett uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM2[53] to generate an 4142215976Sjmallett interrupt on the RSL. */ 4143215976Sjmallett uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM2[52] to generate an 4144215976Sjmallett interrupt on the RSL. */ 4145215976Sjmallett uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM2[51] to generate an 4146215976Sjmallett interrupt on the RSL. */ 4147215976Sjmallett uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM2[50] to generate an 4148215976Sjmallett interrupt on the RSL. */ 4149215976Sjmallett uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM2[49] to generate an 4150215976Sjmallett interrupt on the RSL. */ 4151215976Sjmallett uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM2[48] to generate an 4152215976Sjmallett interrupt on the RSL. */ 4153215976Sjmallett uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM2[47] to generate an 4154215976Sjmallett interrupt on the RSL. */ 4155215976Sjmallett uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM2[46] to generate an 4156215976Sjmallett interrupt on the RSL. */ 4157215976Sjmallett uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM2[45] to generate an 4158215976Sjmallett interrupt on the RSL. */ 4159215976Sjmallett uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM2[44] to generate an 4160215976Sjmallett interrupt on the RSL. */ 4161215976Sjmallett uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM2[43] to generate an 4162215976Sjmallett interrupt on the RSL. */ 4163215976Sjmallett uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM2[42] to generate an 4164215976Sjmallett interrupt on the RSL. */ 4165215976Sjmallett uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM2[41] to generate an 4166215976Sjmallett interrupt on the RSL. */ 4167215976Sjmallett uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM2[40] to generate an 4168215976Sjmallett interrupt on the RSL. */ 4169215976Sjmallett uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM2[39] to generate an 4170215976Sjmallett interrupt on the RSL. */ 4171215976Sjmallett uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM2[38] to generate an 4172215976Sjmallett interrupt on the RSL. */ 4173215976Sjmallett uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM2[37] to generate an 4174215976Sjmallett interrupt on the RSL. */ 4175215976Sjmallett uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM2[36] to generate an 4176215976Sjmallett interrupt on the RSL. */ 4177215976Sjmallett uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM2[35] to generate an 4178215976Sjmallett interrupt on the RSL. */ 4179215976Sjmallett uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM2[34] to generate an 4180215976Sjmallett interrupt on the RSL. */ 4181215976Sjmallett uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM2[33] to generate an 4182215976Sjmallett interrupt on the RSL. */ 4183215976Sjmallett uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM2[32] to generate an 4184215976Sjmallett interrupt on the RSL. */ 4185215976Sjmallett uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM2[31] to generate an 4186215976Sjmallett interrupt on the RSL. */ 4187215976Sjmallett uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM2[30] to generate an 4188215976Sjmallett interrupt on the RSL. */ 4189215976Sjmallett uint64_t crs1_dr : 1; /**< Enables NPEI_INT_SUM2[29] to generate an 4190215976Sjmallett interrupt on the RSL. */ 4191215976Sjmallett uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM2[28] to generate an 4192215976Sjmallett interrupt on the RSL. */ 4193215976Sjmallett uint64_t crs1_er : 1; /**< Enables NPEI_INT_SUM2[27] to generate an 4194215976Sjmallett interrupt on the RSL. */ 4195215976Sjmallett uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM2[26] to generate an 4196215976Sjmallett interrupt on the RSL. */ 4197215976Sjmallett uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM2[25] to generate an 4198215976Sjmallett interrupt on the RSL. */ 4199215976Sjmallett uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM2[24] to generate an 4200215976Sjmallett interrupt on the RSL. */ 4201215976Sjmallett uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM2[23] to generate an 4202215976Sjmallett interrupt on the RSL. */ 4203215976Sjmallett uint64_t crs0_dr : 1; /**< Enables NPEI_INT_SUM2[22] to generate an 4204215976Sjmallett interrupt on the RSL. */ 4205215976Sjmallett uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM2[21] to generate an 4206215976Sjmallett interrupt on the RSL. */ 4207215976Sjmallett uint64_t crs0_er : 1; /**< Enables NPEI_INT_SUM2[20] to generate an 4208215976Sjmallett interrupt on the RSL. */ 4209215976Sjmallett uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM2[19] to generate an 4210215976Sjmallett interrupt on the RSL. */ 4211215976Sjmallett uint64_t ptime : 1; /**< Enables NPEI_INT_SUM2[18] to generate an 4212215976Sjmallett interrupt on the RSL. */ 4213215976Sjmallett uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM2[17] to generate an 4214215976Sjmallett interrupt on the RSL. */ 4215215976Sjmallett uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM2[16] to generate an 4216215976Sjmallett interrupt on the RSL. */ 4217215976Sjmallett uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM2[15] to generate an 4218215976Sjmallett interrupt on the RSL. */ 4219215976Sjmallett uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM2[14] to generate an 4220215976Sjmallett interrupt on the RSL. */ 4221215976Sjmallett uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM2[13] to generate an 4222215976Sjmallett interrupt on the RSL. */ 4223215976Sjmallett uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM2[12] to generate an 4224215976Sjmallett interrupt on the RSL. */ 4225215976Sjmallett uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM2[11] to generate an 4226215976Sjmallett interrupt on the RSL. */ 4227215976Sjmallett uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM2[10] to generate an 4228215976Sjmallett interrupt on the RSL. */ 4229215976Sjmallett uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM2[9] to generate an 4230215976Sjmallett interrupt on the RSL. */ 4231215976Sjmallett uint64_t reserved_8_8 : 1; 4232215976Sjmallett uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM2[7] to generate an 4233215976Sjmallett interrupt on the RSL. */ 4234215976Sjmallett uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM2[6] to generate an 4235215976Sjmallett interrupt on the RSL. */ 4236215976Sjmallett uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM2[5] to generate an 4237215976Sjmallett interrupt on the RSL. */ 4238215976Sjmallett uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM2[4] to generate an 4239215976Sjmallett interrupt on the RSL. */ 4240215976Sjmallett uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM2[3] to generate an 4241215976Sjmallett interrupt on the RSL. */ 4242215976Sjmallett uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM2[2] to generate an 4243215976Sjmallett interrupt on the RSL. */ 4244215976Sjmallett uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM2[1] to generate an 4245215976Sjmallett interrupt on the RSL. */ 4246215976Sjmallett uint64_t rml_rto : 1; /**< Enables NPEI_INT_SUM2[0] to generate an 4247215976Sjmallett interrupt on the RSL. */ 4248215976Sjmallett#else 4249215976Sjmallett uint64_t rml_rto : 1; 4250215976Sjmallett uint64_t rml_wto : 1; 4251215976Sjmallett uint64_t bar0_to : 1; 4252215976Sjmallett uint64_t iob2big : 1; 4253215976Sjmallett uint64_t dma0dbo : 1; 4254215976Sjmallett uint64_t dma1dbo : 1; 4255215976Sjmallett uint64_t dma2dbo : 1; 4256215976Sjmallett uint64_t dma3dbo : 1; 4257215976Sjmallett uint64_t reserved_8_8 : 1; 4258215976Sjmallett uint64_t dma0fi : 1; 4259215976Sjmallett uint64_t dma1fi : 1; 4260215976Sjmallett uint64_t dcnt0 : 1; 4261215976Sjmallett uint64_t dcnt1 : 1; 4262215976Sjmallett uint64_t dtime0 : 1; 4263215976Sjmallett uint64_t dtime1 : 1; 4264215976Sjmallett uint64_t psldbof : 1; 4265215976Sjmallett uint64_t pidbof : 1; 4266215976Sjmallett uint64_t pcnt : 1; 4267215976Sjmallett uint64_t ptime : 1; 4268215976Sjmallett uint64_t c0_aeri : 1; 4269215976Sjmallett uint64_t crs0_er : 1; 4270215976Sjmallett uint64_t c0_se : 1; 4271215976Sjmallett uint64_t crs0_dr : 1; 4272215976Sjmallett uint64_t c0_wake : 1; 4273215976Sjmallett uint64_t c0_pmei : 1; 4274215976Sjmallett uint64_t c0_hpint : 1; 4275215976Sjmallett uint64_t c1_aeri : 1; 4276215976Sjmallett uint64_t crs1_er : 1; 4277215976Sjmallett uint64_t c1_se : 1; 4278215976Sjmallett uint64_t crs1_dr : 1; 4279215976Sjmallett uint64_t c1_wake : 1; 4280215976Sjmallett uint64_t c1_pmei : 1; 4281215976Sjmallett uint64_t c1_hpint : 1; 4282215976Sjmallett uint64_t c0_up_b0 : 1; 4283215976Sjmallett uint64_t c0_up_b1 : 1; 4284215976Sjmallett uint64_t c0_up_b2 : 1; 4285215976Sjmallett uint64_t c0_up_wi : 1; 4286215976Sjmallett uint64_t c0_up_bx : 1; 4287215976Sjmallett uint64_t c0_un_b0 : 1; 4288215976Sjmallett uint64_t c0_un_b1 : 1; 4289215976Sjmallett uint64_t c0_un_b2 : 1; 4290215976Sjmallett uint64_t c0_un_wi : 1; 4291215976Sjmallett uint64_t c0_un_bx : 1; 4292215976Sjmallett uint64_t c1_up_b0 : 1; 4293215976Sjmallett uint64_t c1_up_b1 : 1; 4294215976Sjmallett uint64_t c1_up_b2 : 1; 4295215976Sjmallett uint64_t c1_up_wi : 1; 4296215976Sjmallett uint64_t c1_up_bx : 1; 4297215976Sjmallett uint64_t c1_un_b0 : 1; 4298215976Sjmallett uint64_t c1_un_b1 : 1; 4299215976Sjmallett uint64_t c1_un_b2 : 1; 4300215976Sjmallett uint64_t c1_un_wi : 1; 4301215976Sjmallett uint64_t c1_un_bx : 1; 4302215976Sjmallett uint64_t c0_un_wf : 1; 4303215976Sjmallett uint64_t c1_un_wf : 1; 4304215976Sjmallett uint64_t c0_up_wf : 1; 4305215976Sjmallett uint64_t c1_up_wf : 1; 4306215976Sjmallett uint64_t c0_exc : 1; 4307215976Sjmallett uint64_t c1_exc : 1; 4308215976Sjmallett uint64_t c0_ldwn : 1; 4309215976Sjmallett uint64_t c1_ldwn : 1; 4310215976Sjmallett uint64_t int_a : 1; 4311215976Sjmallett uint64_t reserved_62_63 : 2; 4312215976Sjmallett#endif 4313215976Sjmallett } cn52xxp1; 4314215976Sjmallett struct cvmx_npei_int_enb2_s cn56xx; 4315232812Sjmallett struct cvmx_npei_int_enb2_cn56xxp1 { 4316232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4317215976Sjmallett uint64_t reserved_61_63 : 3; 4318215976Sjmallett uint64_t c1_ldwn : 1; /**< Enables NPEI_INT_SUM[60] to generate an 4319215976Sjmallett interrupt on the RSL. */ 4320215976Sjmallett uint64_t c0_ldwn : 1; /**< Enables NPEI_INT_SUM[59] to generate an 4321215976Sjmallett interrupt on the RSL. */ 4322215976Sjmallett uint64_t c1_exc : 1; /**< Enables NPEI_INT_SUM[58] to generate an 4323215976Sjmallett interrupt on the RSL. */ 4324215976Sjmallett uint64_t c0_exc : 1; /**< Enables NPEI_INT_SUM[57] to generate an 4325215976Sjmallett interrupt on the RSL. */ 4326215976Sjmallett uint64_t c1_up_wf : 1; /**< Enables NPEI_INT_SUM[56] to generate an 4327215976Sjmallett interrupt on the RSL. */ 4328215976Sjmallett uint64_t c0_up_wf : 1; /**< Enables NPEI_INT_SUM[55] to generate an 4329215976Sjmallett interrupt on the RSL. */ 4330215976Sjmallett uint64_t c1_un_wf : 1; /**< Enables NPEI_INT_SUM[54] to generate an 4331215976Sjmallett interrupt on the RSL. */ 4332215976Sjmallett uint64_t c0_un_wf : 1; /**< Enables NPEI_INT_SUM[53] to generate an 4333215976Sjmallett interrupt on the RSL. */ 4334215976Sjmallett uint64_t c1_un_bx : 1; /**< Enables NPEI_INT_SUM[52] to generate an 4335215976Sjmallett interrupt on the RSL. */ 4336215976Sjmallett uint64_t c1_un_wi : 1; /**< Enables NPEI_INT_SUM[51] to generate an 4337215976Sjmallett interrupt on the RSL. */ 4338215976Sjmallett uint64_t c1_un_b2 : 1; /**< Enables NPEI_INT_SUM[50] to generate an 4339215976Sjmallett interrupt on the RSL. */ 4340215976Sjmallett uint64_t c1_un_b1 : 1; /**< Enables NPEI_INT_SUM[49] to generate an 4341215976Sjmallett interrupt on the RSL. */ 4342215976Sjmallett uint64_t c1_un_b0 : 1; /**< Enables NPEI_INT_SUM[48] to generate an 4343215976Sjmallett interrupt on the RSL. */ 4344215976Sjmallett uint64_t c1_up_bx : 1; /**< Enables NPEI_INT_SUM[47] to generate an 4345215976Sjmallett interrupt on the RSL. */ 4346215976Sjmallett uint64_t c1_up_wi : 1; /**< Enables NPEI_INT_SUM[46] to generate an 4347215976Sjmallett interrupt on the RSL. */ 4348215976Sjmallett uint64_t c1_up_b2 : 1; /**< Enables NPEI_INT_SUM[45] to generate an 4349215976Sjmallett interrupt on the RSL. */ 4350215976Sjmallett uint64_t c1_up_b1 : 1; /**< Enables NPEI_INT_SUM[44] to generate an 4351215976Sjmallett interrupt on the RSL. */ 4352215976Sjmallett uint64_t c1_up_b0 : 1; /**< Enables NPEI_INT_SUM[43] to generate an 4353215976Sjmallett interrupt on the RSL. */ 4354215976Sjmallett uint64_t c0_un_bx : 1; /**< Enables NPEI_INT_SUM[42] to generate an 4355215976Sjmallett interrupt on the RSL. */ 4356215976Sjmallett uint64_t c0_un_wi : 1; /**< Enables NPEI_INT_SUM[41] to generate an 4357215976Sjmallett interrupt on the RSL. */ 4358215976Sjmallett uint64_t c0_un_b2 : 1; /**< Enables NPEI_INT_SUM[40] to generate an 4359215976Sjmallett interrupt on the RSL. */ 4360215976Sjmallett uint64_t c0_un_b1 : 1; /**< Enables NPEI_INT_SUM[39] to generate an 4361215976Sjmallett interrupt on the RSL. */ 4362215976Sjmallett uint64_t c0_un_b0 : 1; /**< Enables NPEI_INT_SUM[38] to generate an 4363215976Sjmallett interrupt on the RSL. */ 4364215976Sjmallett uint64_t c0_up_bx : 1; /**< Enables NPEI_INT_SUM[37] to generate an 4365215976Sjmallett interrupt on the RSL. */ 4366215976Sjmallett uint64_t c0_up_wi : 1; /**< Enables NPEI_INT_SUM[36] to generate an 4367215976Sjmallett interrupt on the RSL. */ 4368215976Sjmallett uint64_t c0_up_b2 : 1; /**< Enables NPEI_INT_SUM[35] to generate an 4369215976Sjmallett interrupt on the RSL. */ 4370215976Sjmallett uint64_t c0_up_b1 : 1; /**< Enables NPEI_INT_SUM[34] to generate an 4371215976Sjmallett interrupt on the RSL. */ 4372215976Sjmallett uint64_t c0_up_b0 : 1; /**< Enables NPEI_INT_SUM[33] to generate an 4373215976Sjmallett interrupt on the RSL. */ 4374215976Sjmallett uint64_t c1_hpint : 1; /**< Enables NPEI_INT_SUM[32] to generate an 4375215976Sjmallett interrupt on the RSL. */ 4376215976Sjmallett uint64_t c1_pmei : 1; /**< Enables NPEI_INT_SUM[31] to generate an 4377215976Sjmallett interrupt on the RSL. */ 4378215976Sjmallett uint64_t c1_wake : 1; /**< Enables NPEI_INT_SUM[30] to generate an 4379215976Sjmallett interrupt on the RSL. */ 4380215976Sjmallett uint64_t reserved_29_29 : 1; 4381215976Sjmallett uint64_t c1_se : 1; /**< Enables NPEI_INT_SUM[28] to generate an 4382215976Sjmallett interrupt on the RSL. */ 4383215976Sjmallett uint64_t reserved_27_27 : 1; 4384215976Sjmallett uint64_t c1_aeri : 1; /**< Enables NPEI_INT_SUM[26] to generate an 4385215976Sjmallett interrupt on the RSL. */ 4386215976Sjmallett uint64_t c0_hpint : 1; /**< Enables NPEI_INT_SUM[25] to generate an 4387215976Sjmallett interrupt on the RSL. */ 4388215976Sjmallett uint64_t c0_pmei : 1; /**< Enables NPEI_INT_SUM[24] to generate an 4389215976Sjmallett interrupt on the RSL. */ 4390215976Sjmallett uint64_t c0_wake : 1; /**< Enables NPEI_INT_SUM[23] to generate an 4391215976Sjmallett interrupt on the RSL. */ 4392215976Sjmallett uint64_t reserved_22_22 : 1; 4393215976Sjmallett uint64_t c0_se : 1; /**< Enables NPEI_INT_SUM[21] to generate an 4394215976Sjmallett interrupt on the RSL. */ 4395215976Sjmallett uint64_t reserved_20_20 : 1; 4396215976Sjmallett uint64_t c0_aeri : 1; /**< Enables NPEI_INT_SUM[19] to generate an 4397215976Sjmallett interrupt on the RSL. */ 4398215976Sjmallett uint64_t ptime : 1; /**< Enables NPEI_INT_SUM[18] to generate an 4399215976Sjmallett interrupt on the RSL. */ 4400215976Sjmallett uint64_t pcnt : 1; /**< Enables NPEI_INT_SUM[17] to generate an 4401215976Sjmallett interrupt on the RSL. */ 4402215976Sjmallett uint64_t pidbof : 1; /**< Enables NPEI_INT_SUM[16] to generate an 4403215976Sjmallett interrupt on the RSL. */ 4404215976Sjmallett uint64_t psldbof : 1; /**< Enables NPEI_INT_SUM[15] to generate an 4405215976Sjmallett interrupt on the RSL. */ 4406215976Sjmallett uint64_t dtime1 : 1; /**< Enables NPEI_INT_SUM[14] to generate an 4407215976Sjmallett interrupt on the RSL. */ 4408215976Sjmallett uint64_t dtime0 : 1; /**< Enables NPEI_INT_SUM[13] to generate an 4409215976Sjmallett interrupt on the RSL. */ 4410215976Sjmallett uint64_t dcnt1 : 1; /**< Enables NPEI_INT_SUM[12] to generate an 4411215976Sjmallett interrupt on the RSL. */ 4412215976Sjmallett uint64_t dcnt0 : 1; /**< Enables NPEI_INT_SUM[11] to generate an 4413215976Sjmallett interrupt on the RSL. */ 4414215976Sjmallett uint64_t dma1fi : 1; /**< Enables NPEI_INT_SUM[10] to generate an 4415215976Sjmallett interrupt on the RSL. */ 4416215976Sjmallett uint64_t dma0fi : 1; /**< Enables NPEI_INT_SUM[9] to generate an 4417215976Sjmallett interrupt on the RSL. */ 4418215976Sjmallett uint64_t dma4dbo : 1; /**< Enables NPEI_INT_SUM[8] to generate an 4419215976Sjmallett interrupt on the RSL. */ 4420215976Sjmallett uint64_t dma3dbo : 1; /**< Enables NPEI_INT_SUM[7] to generate an 4421215976Sjmallett interrupt on the RSL. */ 4422215976Sjmallett uint64_t dma2dbo : 1; /**< Enables NPEI_INT_SUM[6] to generate an 4423215976Sjmallett interrupt on the RSL. */ 4424215976Sjmallett uint64_t dma1dbo : 1; /**< Enables NPEI_INT_SUM[5] to generate an 4425215976Sjmallett interrupt on the RSL. */ 4426215976Sjmallett uint64_t dma0dbo : 1; /**< Enables NPEI_INT_SUM[4] to generate an 4427215976Sjmallett interrupt on the RSL. */ 4428215976Sjmallett uint64_t iob2big : 1; /**< Enables NPEI_INT_SUM[3] to generate an 4429215976Sjmallett interrupt on the RSL. */ 4430215976Sjmallett uint64_t bar0_to : 1; /**< Enables NPEI_INT_SUM[2] to generate an 4431215976Sjmallett interrupt on the RSL. */ 4432215976Sjmallett uint64_t rml_wto : 1; /**< Enables NPEI_INT_SUM[1] to generate an 4433215976Sjmallett interrupt on the RSL. */ 4434215976Sjmallett uint64_t rml_rto : 1; /**< Enables NPEI_INT_UM[0] to generate an 4435215976Sjmallett interrupt on the RSL. */ 4436215976Sjmallett#else 4437215976Sjmallett uint64_t rml_rto : 1; 4438215976Sjmallett uint64_t rml_wto : 1; 4439215976Sjmallett uint64_t bar0_to : 1; 4440215976Sjmallett uint64_t iob2big : 1; 4441215976Sjmallett uint64_t dma0dbo : 1; 4442215976Sjmallett uint64_t dma1dbo : 1; 4443215976Sjmallett uint64_t dma2dbo : 1; 4444215976Sjmallett uint64_t dma3dbo : 1; 4445215976Sjmallett uint64_t dma4dbo : 1; 4446215976Sjmallett uint64_t dma0fi : 1; 4447215976Sjmallett uint64_t dma1fi : 1; 4448215976Sjmallett uint64_t dcnt0 : 1; 4449215976Sjmallett uint64_t dcnt1 : 1; 4450215976Sjmallett uint64_t dtime0 : 1; 4451215976Sjmallett uint64_t dtime1 : 1; 4452215976Sjmallett uint64_t psldbof : 1; 4453215976Sjmallett uint64_t pidbof : 1; 4454215976Sjmallett uint64_t pcnt : 1; 4455215976Sjmallett uint64_t ptime : 1; 4456215976Sjmallett uint64_t c0_aeri : 1; 4457215976Sjmallett uint64_t reserved_20_20 : 1; 4458215976Sjmallett uint64_t c0_se : 1; 4459215976Sjmallett uint64_t reserved_22_22 : 1; 4460215976Sjmallett uint64_t c0_wake : 1; 4461215976Sjmallett uint64_t c0_pmei : 1; 4462215976Sjmallett uint64_t c0_hpint : 1; 4463215976Sjmallett uint64_t c1_aeri : 1; 4464215976Sjmallett uint64_t reserved_27_27 : 1; 4465215976Sjmallett uint64_t c1_se : 1; 4466215976Sjmallett uint64_t reserved_29_29 : 1; 4467215976Sjmallett uint64_t c1_wake : 1; 4468215976Sjmallett uint64_t c1_pmei : 1; 4469215976Sjmallett uint64_t c1_hpint : 1; 4470215976Sjmallett uint64_t c0_up_b0 : 1; 4471215976Sjmallett uint64_t c0_up_b1 : 1; 4472215976Sjmallett uint64_t c0_up_b2 : 1; 4473215976Sjmallett uint64_t c0_up_wi : 1; 4474215976Sjmallett uint64_t c0_up_bx : 1; 4475215976Sjmallett uint64_t c0_un_b0 : 1; 4476215976Sjmallett uint64_t c0_un_b1 : 1; 4477215976Sjmallett uint64_t c0_un_b2 : 1; 4478215976Sjmallett uint64_t c0_un_wi : 1; 4479215976Sjmallett uint64_t c0_un_bx : 1; 4480215976Sjmallett uint64_t c1_up_b0 : 1; 4481215976Sjmallett uint64_t c1_up_b1 : 1; 4482215976Sjmallett uint64_t c1_up_b2 : 1; 4483215976Sjmallett uint64_t c1_up_wi : 1; 4484215976Sjmallett uint64_t c1_up_bx : 1; 4485215976Sjmallett uint64_t c1_un_b0 : 1; 4486215976Sjmallett uint64_t c1_un_b1 : 1; 4487215976Sjmallett uint64_t c1_un_b2 : 1; 4488215976Sjmallett uint64_t c1_un_wi : 1; 4489215976Sjmallett uint64_t c1_un_bx : 1; 4490215976Sjmallett uint64_t c0_un_wf : 1; 4491215976Sjmallett uint64_t c1_un_wf : 1; 4492215976Sjmallett uint64_t c0_up_wf : 1; 4493215976Sjmallett uint64_t c1_up_wf : 1; 4494215976Sjmallett uint64_t c0_exc : 1; 4495215976Sjmallett uint64_t c1_exc : 1; 4496215976Sjmallett uint64_t c0_ldwn : 1; 4497215976Sjmallett uint64_t c1_ldwn : 1; 4498215976Sjmallett uint64_t reserved_61_63 : 3; 4499215976Sjmallett#endif 4500215976Sjmallett } cn56xxp1; 4501215976Sjmallett}; 4502215976Sjmalletttypedef union cvmx_npei_int_enb2 cvmx_npei_int_enb2_t; 4503215976Sjmallett 4504215976Sjmallett/** 4505215976Sjmallett * cvmx_npei_int_info 4506215976Sjmallett * 4507215976Sjmallett * NPEI_INT_INFO = NPI Interrupt Information 4508215976Sjmallett * 4509215976Sjmallett * Contains information about some of the interrupt condition that can occur in the NPEI_INTERRUPT_SUM register. 4510215976Sjmallett */ 4511232812Sjmallettunion cvmx_npei_int_info { 4512215976Sjmallett uint64_t u64; 4513232812Sjmallett struct cvmx_npei_int_info_s { 4514232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4515215976Sjmallett uint64_t reserved_12_63 : 52; 4516215976Sjmallett uint64_t pidbof : 6; /**< Field set when the NPEI_INTERRUPT_SUM[PIDBOF] bit 4517215976Sjmallett is set. This field when set will not change again 4518215976Sjmallett unitl NPEI_INTERRUPT_SUM[PIDBOF] is cleared. */ 4519215976Sjmallett uint64_t psldbof : 6; /**< Field set when the NPEI_INTERRUPT_SUM[PSLDBOF] bit 4520215976Sjmallett is set. This field when set will not change again 4521215976Sjmallett unitl NPEI_INTERRUPT_SUM[PSLDBOF] is cleared. */ 4522215976Sjmallett#else 4523215976Sjmallett uint64_t psldbof : 6; 4524215976Sjmallett uint64_t pidbof : 6; 4525215976Sjmallett uint64_t reserved_12_63 : 52; 4526215976Sjmallett#endif 4527215976Sjmallett } s; 4528215976Sjmallett struct cvmx_npei_int_info_s cn52xx; 4529215976Sjmallett struct cvmx_npei_int_info_s cn56xx; 4530215976Sjmallett struct cvmx_npei_int_info_s cn56xxp1; 4531215976Sjmallett}; 4532215976Sjmalletttypedef union cvmx_npei_int_info cvmx_npei_int_info_t; 4533215976Sjmallett 4534215976Sjmallett/** 4535215976Sjmallett * cvmx_npei_int_sum 4536215976Sjmallett * 4537215976Sjmallett * NPEI_INTERRUPT_SUM = NPI Interrupt Summary Register 4538215976Sjmallett * 4539215976Sjmallett * Set when an interrupt condition occurs, write '1' to clear. 4540215976Sjmallett * 4541215976Sjmallett * HACK: These used to exist, how are TO handled? 4542215976Sjmallett * <3> PO0_2SML R/W1C 0x0 0 The packet being sent out on Port0 is smaller $R NS 4543215976Sjmallett * than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. 4544215976Sjmallett * <7> I0_RTOUT R/W1C 0x0 0 Port-0 had a read timeout while attempting to $R NS 4545215976Sjmallett * read instructions. 4546215976Sjmallett * <15> P0_RTOUT R/W1C 0x0 0 Port-0 had a read timeout while attempting to $R NS 4547215976Sjmallett * read packet data. 4548215976Sjmallett * <23> G0_RTOUT R/W1C 0x0 0 Port-0 had a read timeout while attempting to $R NS 4549215976Sjmallett * read a gather list. 4550215976Sjmallett * <31> P0_PTOUT R/W1C 0x0 0 Port-0 output had a read timeout on a DATA/INFO $R NS 4551215976Sjmallett * pair. 4552215976Sjmallett */ 4553232812Sjmallettunion cvmx_npei_int_sum { 4554215976Sjmallett uint64_t u64; 4555232812Sjmallett struct cvmx_npei_int_sum_s { 4556232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4557215976Sjmallett uint64_t mio_inta : 1; /**< Interrupt from MIO. */ 4558215976Sjmallett uint64_t reserved_62_62 : 1; 4559215976Sjmallett uint64_t int_a : 1; /**< Set when a bit in the NPEI_INT_A_SUM register and 4560215976Sjmallett the cooresponding bit in the NPEI_INT_A_ENB 4561215976Sjmallett register is set. */ 4562215976Sjmallett uint64_t c1_ldwn : 1; /**< Reset request due to link1 down status. */ 4563215976Sjmallett uint64_t c0_ldwn : 1; /**< Reset request due to link0 down status. */ 4564215976Sjmallett uint64_t c1_exc : 1; /**< Set when the PESC1_DBG_INFO register has a bit 4565215976Sjmallett set and its cooresponding PESC1_DBG_INFO_EN bit 4566215976Sjmallett is set. */ 4567215976Sjmallett uint64_t c0_exc : 1; /**< Set when the PESC0_DBG_INFO register has a bit 4568215976Sjmallett set and its cooresponding PESC0_DBG_INFO_EN bit 4569215976Sjmallett is set. */ 4570215976Sjmallett uint64_t c1_up_wf : 1; /**< Received Unsupported P-TLP for filtered window 4571215976Sjmallett register. Core1. */ 4572215976Sjmallett uint64_t c0_up_wf : 1; /**< Received Unsupported P-TLP for filtered window 4573215976Sjmallett register. Core0. */ 4574215976Sjmallett uint64_t c1_un_wf : 1; /**< Received Unsupported N-TLP for filtered window 4575215976Sjmallett register. Core1. */ 4576215976Sjmallett uint64_t c0_un_wf : 1; /**< Received Unsupported N-TLP for filtered window 4577215976Sjmallett register. Core0. */ 4578215976Sjmallett uint64_t c1_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar. 4579215976Sjmallett Core 1. */ 4580215976Sjmallett uint64_t c1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register. 4581215976Sjmallett Core 1. */ 4582215976Sjmallett uint64_t c1_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2. 4583215976Sjmallett Core 1. */ 4584215976Sjmallett uint64_t c1_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1. 4585215976Sjmallett Core 1. */ 4586215976Sjmallett uint64_t c1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0. 4587215976Sjmallett Core 1. */ 4588215976Sjmallett uint64_t c1_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar. 4589215976Sjmallett Core 1. */ 4590215976Sjmallett uint64_t c1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register. 4591215976Sjmallett Core 1. */ 4592215976Sjmallett uint64_t c1_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2. 4593215976Sjmallett Core 1. */ 4594215976Sjmallett uint64_t c1_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1. 4595215976Sjmallett Core 1. */ 4596215976Sjmallett uint64_t c1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0. 4597215976Sjmallett Core 1. */ 4598215976Sjmallett uint64_t c0_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar. 4599215976Sjmallett Core 0. */ 4600215976Sjmallett uint64_t c0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register. 4601215976Sjmallett Core 0. */ 4602215976Sjmallett uint64_t c0_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2. 4603215976Sjmallett Core 0. */ 4604215976Sjmallett uint64_t c0_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1. 4605215976Sjmallett Core 0. */ 4606215976Sjmallett uint64_t c0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0. 4607215976Sjmallett Core 0. */ 4608215976Sjmallett uint64_t c0_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar. 4609215976Sjmallett Core 0. */ 4610215976Sjmallett uint64_t c0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register. 4611215976Sjmallett Core 0. */ 4612215976Sjmallett uint64_t c0_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2. 4613215976Sjmallett Core 0. */ 4614215976Sjmallett uint64_t c0_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1. 4615215976Sjmallett Core 0. */ 4616215976Sjmallett uint64_t c0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0. 4617215976Sjmallett Core 0. */ 4618215976Sjmallett uint64_t c1_hpint : 1; /**< Hot-Plug Interrupt. 4619215976Sjmallett Pcie Core 1 (hp_int). 4620215976Sjmallett This interrupt will only be generated when 4621215976Sjmallett PCIERC1_CFG034[DLLS_C] is generated. Hot plug is 4622215976Sjmallett not supported. */ 4623215976Sjmallett uint64_t c1_pmei : 1; /**< PME Interrupt. 4624215976Sjmallett Pcie Core 1. (cfg_pme_int) */ 4625215976Sjmallett uint64_t c1_wake : 1; /**< Wake up from Power Management Unit. 4626215976Sjmallett Pcie Core 1. (wake_n) 4627215976Sjmallett Octeon will never generate this interrupt. */ 4628215976Sjmallett uint64_t crs1_dr : 1; /**< Had a CRS when Retries were disabled. */ 4629215976Sjmallett uint64_t c1_se : 1; /**< System Error, RC Mode Only. 4630215976Sjmallett Pcie Core 1. (cfg_sys_err_rc) */ 4631215976Sjmallett uint64_t crs1_er : 1; /**< Had a CRS Timeout when Retries were enabled. */ 4632215976Sjmallett uint64_t c1_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only. 4633215976Sjmallett Pcie Core 1. */ 4634215976Sjmallett uint64_t c0_hpint : 1; /**< Hot-Plug Interrupt. 4635215976Sjmallett Pcie Core 0 (hp_int). 4636215976Sjmallett This interrupt will only be generated when 4637215976Sjmallett PCIERC0_CFG034[DLLS_C] is generated. Hot plug is 4638215976Sjmallett not supported. */ 4639215976Sjmallett uint64_t c0_pmei : 1; /**< PME Interrupt. 4640215976Sjmallett Pcie Core 0. (cfg_pme_int) */ 4641215976Sjmallett uint64_t c0_wake : 1; /**< Wake up from Power Management Unit. 4642215976Sjmallett Pcie Core 0. (wake_n) 4643215976Sjmallett Octeon will never generate this interrupt. */ 4644215976Sjmallett uint64_t crs0_dr : 1; /**< Had a CRS when Retries were disabled. */ 4645215976Sjmallett uint64_t c0_se : 1; /**< System Error, RC Mode Only. 4646215976Sjmallett Pcie Core 0. (cfg_sys_err_rc) */ 4647215976Sjmallett uint64_t crs0_er : 1; /**< Had a CRS Timeout when Retries were enabled. */ 4648215976Sjmallett uint64_t c0_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only. 4649215976Sjmallett Pcie Core 0 (cfg_aer_rc_err_int). */ 4650215976Sjmallett uint64_t ptime : 1; /**< Packet Timer has an interrupt. Which rings can 4651215976Sjmallett be found in NPEI_PKT_TIME_INT. */ 4652215976Sjmallett uint64_t pcnt : 1; /**< Packet Counter has an interrupt. Which rings can 4653215976Sjmallett be found in NPEI_PKT_CNT_INT. */ 4654215976Sjmallett uint64_t pidbof : 1; /**< Packet Instruction Doorbell count overflowed. Which 4655215976Sjmallett doorbell can be found in NPEI_INT_INFO[PIDBOF] */ 4656215976Sjmallett uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell count overflowed. Which 4657215976Sjmallett doorbell can be found in NPEI_INT_INFO[PSLDBOF] */ 4658215976Sjmallett uint64_t dtime1 : 1; /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the 4659215976Sjmallett DMA_CNT1 timer increments every core clock. When 4660215976Sjmallett DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME], 4661215976Sjmallett this bit is set. Writing a '1' to this bit also 4662215976Sjmallett clears the DMA_CNT1 timer. */ 4663215976Sjmallett uint64_t dtime0 : 1; /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the 4664215976Sjmallett DMA_CNT0 timer increments every core clock. When 4665215976Sjmallett DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME], 4666215976Sjmallett this bit is set. Writing a '1' to this bit also 4667215976Sjmallett clears the DMA_CNT0 timer. */ 4668215976Sjmallett uint64_t dcnt1 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is 4669215976Sjmallett greater than NPEI_DMA1_INT_LEVEL[CNT]. */ 4670215976Sjmallett uint64_t dcnt0 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is 4671215976Sjmallett greater than NPEI_DMA0_INT_LEVEL[CNT]. */ 4672215976Sjmallett uint64_t dma1fi : 1; /**< DMA0 set Forced Interrupt. */ 4673215976Sjmallett uint64_t dma0fi : 1; /**< DMA0 set Forced Interrupt. */ 4674215976Sjmallett uint64_t dma4dbo : 1; /**< DMA4 doorbell overflow. 4675215976Sjmallett Bit[32] of the doorbell count was set. */ 4676215976Sjmallett uint64_t dma3dbo : 1; /**< DMA3 doorbell overflow. 4677215976Sjmallett Bit[32] of the doorbell count was set. */ 4678215976Sjmallett uint64_t dma2dbo : 1; /**< DMA2 doorbell overflow. 4679215976Sjmallett Bit[32] of the doorbell count was set. */ 4680215976Sjmallett uint64_t dma1dbo : 1; /**< DMA1 doorbell overflow. 4681215976Sjmallett Bit[32] of the doorbell count was set. */ 4682215976Sjmallett uint64_t dma0dbo : 1; /**< DMA0 doorbell overflow. 4683215976Sjmallett Bit[32] of the doorbell count was set. */ 4684215976Sjmallett uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */ 4685215976Sjmallett uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive 4686215976Sjmallett read-data/commit in 0xffff core clocks. */ 4687215976Sjmallett uint64_t rml_wto : 1; /**< RML write did not get commit in 0xffff core clocks. */ 4688215976Sjmallett uint64_t rml_rto : 1; /**< RML read did not return data in 0xffff core clocks. */ 4689215976Sjmallett#else 4690215976Sjmallett uint64_t rml_rto : 1; 4691215976Sjmallett uint64_t rml_wto : 1; 4692215976Sjmallett uint64_t bar0_to : 1; 4693215976Sjmallett uint64_t iob2big : 1; 4694215976Sjmallett uint64_t dma0dbo : 1; 4695215976Sjmallett uint64_t dma1dbo : 1; 4696215976Sjmallett uint64_t dma2dbo : 1; 4697215976Sjmallett uint64_t dma3dbo : 1; 4698215976Sjmallett uint64_t dma4dbo : 1; 4699215976Sjmallett uint64_t dma0fi : 1; 4700215976Sjmallett uint64_t dma1fi : 1; 4701215976Sjmallett uint64_t dcnt0 : 1; 4702215976Sjmallett uint64_t dcnt1 : 1; 4703215976Sjmallett uint64_t dtime0 : 1; 4704215976Sjmallett uint64_t dtime1 : 1; 4705215976Sjmallett uint64_t psldbof : 1; 4706215976Sjmallett uint64_t pidbof : 1; 4707215976Sjmallett uint64_t pcnt : 1; 4708215976Sjmallett uint64_t ptime : 1; 4709215976Sjmallett uint64_t c0_aeri : 1; 4710215976Sjmallett uint64_t crs0_er : 1; 4711215976Sjmallett uint64_t c0_se : 1; 4712215976Sjmallett uint64_t crs0_dr : 1; 4713215976Sjmallett uint64_t c0_wake : 1; 4714215976Sjmallett uint64_t c0_pmei : 1; 4715215976Sjmallett uint64_t c0_hpint : 1; 4716215976Sjmallett uint64_t c1_aeri : 1; 4717215976Sjmallett uint64_t crs1_er : 1; 4718215976Sjmallett uint64_t c1_se : 1; 4719215976Sjmallett uint64_t crs1_dr : 1; 4720215976Sjmallett uint64_t c1_wake : 1; 4721215976Sjmallett uint64_t c1_pmei : 1; 4722215976Sjmallett uint64_t c1_hpint : 1; 4723215976Sjmallett uint64_t c0_up_b0 : 1; 4724215976Sjmallett uint64_t c0_up_b1 : 1; 4725215976Sjmallett uint64_t c0_up_b2 : 1; 4726215976Sjmallett uint64_t c0_up_wi : 1; 4727215976Sjmallett uint64_t c0_up_bx : 1; 4728215976Sjmallett uint64_t c0_un_b0 : 1; 4729215976Sjmallett uint64_t c0_un_b1 : 1; 4730215976Sjmallett uint64_t c0_un_b2 : 1; 4731215976Sjmallett uint64_t c0_un_wi : 1; 4732215976Sjmallett uint64_t c0_un_bx : 1; 4733215976Sjmallett uint64_t c1_up_b0 : 1; 4734215976Sjmallett uint64_t c1_up_b1 : 1; 4735215976Sjmallett uint64_t c1_up_b2 : 1; 4736215976Sjmallett uint64_t c1_up_wi : 1; 4737215976Sjmallett uint64_t c1_up_bx : 1; 4738215976Sjmallett uint64_t c1_un_b0 : 1; 4739215976Sjmallett uint64_t c1_un_b1 : 1; 4740215976Sjmallett uint64_t c1_un_b2 : 1; 4741215976Sjmallett uint64_t c1_un_wi : 1; 4742215976Sjmallett uint64_t c1_un_bx : 1; 4743215976Sjmallett uint64_t c0_un_wf : 1; 4744215976Sjmallett uint64_t c1_un_wf : 1; 4745215976Sjmallett uint64_t c0_up_wf : 1; 4746215976Sjmallett uint64_t c1_up_wf : 1; 4747215976Sjmallett uint64_t c0_exc : 1; 4748215976Sjmallett uint64_t c1_exc : 1; 4749215976Sjmallett uint64_t c0_ldwn : 1; 4750215976Sjmallett uint64_t c1_ldwn : 1; 4751215976Sjmallett uint64_t int_a : 1; 4752215976Sjmallett uint64_t reserved_62_62 : 1; 4753215976Sjmallett uint64_t mio_inta : 1; 4754215976Sjmallett#endif 4755215976Sjmallett } s; 4756215976Sjmallett struct cvmx_npei_int_sum_s cn52xx; 4757232812Sjmallett struct cvmx_npei_int_sum_cn52xxp1 { 4758232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4759215976Sjmallett uint64_t mio_inta : 1; /**< Interrupt from MIO. */ 4760215976Sjmallett uint64_t reserved_62_62 : 1; 4761215976Sjmallett uint64_t int_a : 1; /**< Set when a bit in the NPEI_INT_A_SUM register and 4762215976Sjmallett the cooresponding bit in the NPEI_INT_A_ENB 4763215976Sjmallett register is set. */ 4764215976Sjmallett uint64_t c1_ldwn : 1; /**< Reset request due to link1 down status. */ 4765215976Sjmallett uint64_t c0_ldwn : 1; /**< Reset request due to link0 down status. */ 4766215976Sjmallett uint64_t c1_exc : 1; /**< Set when the PESC1_DBG_INFO register has a bit 4767215976Sjmallett set and its cooresponding PESC1_DBG_INFO_EN bit 4768215976Sjmallett is set. */ 4769215976Sjmallett uint64_t c0_exc : 1; /**< Set when the PESC0_DBG_INFO register has a bit 4770215976Sjmallett set and its cooresponding PESC0_DBG_INFO_EN bit 4771215976Sjmallett is set. */ 4772215976Sjmallett uint64_t c1_up_wf : 1; /**< Received Unsupported P-TLP for filtered window 4773215976Sjmallett register. Core1. */ 4774215976Sjmallett uint64_t c0_up_wf : 1; /**< Received Unsupported P-TLP for filtered window 4775215976Sjmallett register. Core0. */ 4776215976Sjmallett uint64_t c1_un_wf : 1; /**< Received Unsupported N-TLP for filtered window 4777215976Sjmallett register. Core1. */ 4778215976Sjmallett uint64_t c0_un_wf : 1; /**< Received Unsupported N-TLP for filtered window 4779215976Sjmallett register. Core0. */ 4780215976Sjmallett uint64_t c1_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar. 4781215976Sjmallett Core 1. */ 4782215976Sjmallett uint64_t c1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register. 4783215976Sjmallett Core 1. */ 4784215976Sjmallett uint64_t c1_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2. 4785215976Sjmallett Core 1. */ 4786215976Sjmallett uint64_t c1_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1. 4787215976Sjmallett Core 1. */ 4788215976Sjmallett uint64_t c1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0. 4789215976Sjmallett Core 1. */ 4790215976Sjmallett uint64_t c1_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar. 4791215976Sjmallett Core 1. */ 4792215976Sjmallett uint64_t c1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register. 4793215976Sjmallett Core 1. */ 4794215976Sjmallett uint64_t c1_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2. 4795215976Sjmallett Core 1. */ 4796215976Sjmallett uint64_t c1_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1. 4797215976Sjmallett Core 1. */ 4798215976Sjmallett uint64_t c1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0. 4799215976Sjmallett Core 1. */ 4800215976Sjmallett uint64_t c0_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar. 4801215976Sjmallett Core 0. */ 4802215976Sjmallett uint64_t c0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register. 4803215976Sjmallett Core 0. */ 4804215976Sjmallett uint64_t c0_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2. 4805215976Sjmallett Core 0. */ 4806215976Sjmallett uint64_t c0_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1. 4807215976Sjmallett Core 0. */ 4808215976Sjmallett uint64_t c0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0. 4809215976Sjmallett Core 0. */ 4810215976Sjmallett uint64_t c0_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar. 4811215976Sjmallett Core 0. */ 4812215976Sjmallett uint64_t c0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register. 4813215976Sjmallett Core 0. */ 4814215976Sjmallett uint64_t c0_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2. 4815215976Sjmallett Core 0. */ 4816215976Sjmallett uint64_t c0_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1. 4817215976Sjmallett Core 0. */ 4818215976Sjmallett uint64_t c0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0. 4819215976Sjmallett Core 0. */ 4820215976Sjmallett uint64_t c1_hpint : 1; /**< Hot-Plug Interrupt. 4821215976Sjmallett Pcie Core 1 (hp_int). 4822215976Sjmallett This interrupt will only be generated when 4823215976Sjmallett PCIERC1_CFG034[DLLS_C] is generated. Hot plug is 4824215976Sjmallett not supported. */ 4825215976Sjmallett uint64_t c1_pmei : 1; /**< PME Interrupt. 4826215976Sjmallett Pcie Core 1. (cfg_pme_int) */ 4827215976Sjmallett uint64_t c1_wake : 1; /**< Wake up from Power Management Unit. 4828215976Sjmallett Pcie Core 1. (wake_n) 4829215976Sjmallett Octeon will never generate this interrupt. */ 4830215976Sjmallett uint64_t crs1_dr : 1; /**< Had a CRS when Retries were disabled. */ 4831215976Sjmallett uint64_t c1_se : 1; /**< System Error, RC Mode Only. 4832215976Sjmallett Pcie Core 1. (cfg_sys_err_rc) */ 4833215976Sjmallett uint64_t crs1_er : 1; /**< Had a CRS Timeout when Retries were enabled. */ 4834215976Sjmallett uint64_t c1_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only. 4835215976Sjmallett Pcie Core 1. */ 4836215976Sjmallett uint64_t c0_hpint : 1; /**< Hot-Plug Interrupt. 4837215976Sjmallett Pcie Core 0 (hp_int). 4838215976Sjmallett This interrupt will only be generated when 4839215976Sjmallett PCIERC0_CFG034[DLLS_C] is generated. Hot plug is 4840215976Sjmallett not supported. */ 4841215976Sjmallett uint64_t c0_pmei : 1; /**< PME Interrupt. 4842215976Sjmallett Pcie Core 0. (cfg_pme_int) */ 4843215976Sjmallett uint64_t c0_wake : 1; /**< Wake up from Power Management Unit. 4844215976Sjmallett Pcie Core 0. (wake_n) 4845215976Sjmallett Octeon will never generate this interrupt. */ 4846215976Sjmallett uint64_t crs0_dr : 1; /**< Had a CRS when Retries were disabled. */ 4847215976Sjmallett uint64_t c0_se : 1; /**< System Error, RC Mode Only. 4848215976Sjmallett Pcie Core 0. (cfg_sys_err_rc) */ 4849215976Sjmallett uint64_t crs0_er : 1; /**< Had a CRS Timeout when Retries were enabled. */ 4850215976Sjmallett uint64_t c0_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only. 4851215976Sjmallett Pcie Core 0 (cfg_aer_rc_err_int). */ 4852215976Sjmallett uint64_t reserved_15_18 : 4; 4853215976Sjmallett uint64_t dtime1 : 1; /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the 4854215976Sjmallett DMA_CNT1 timer increments every core clock. When 4855215976Sjmallett DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME], 4856215976Sjmallett this bit is set. Writing a '1' to this bit also 4857215976Sjmallett clears the DMA_CNT1 timer. */ 4858215976Sjmallett uint64_t dtime0 : 1; /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the 4859215976Sjmallett DMA_CNT0 timer increments every core clock. When 4860215976Sjmallett DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME], 4861215976Sjmallett this bit is set. Writing a '1' to this bit also 4862215976Sjmallett clears the DMA_CNT0 timer. */ 4863215976Sjmallett uint64_t dcnt1 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is 4864215976Sjmallett greater than NPEI_DMA1_INT_LEVEL[CNT]. */ 4865215976Sjmallett uint64_t dcnt0 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is 4866215976Sjmallett greater than NPEI_DMA0_INT_LEVEL[CNT]. */ 4867215976Sjmallett uint64_t dma1fi : 1; /**< DMA0 set Forced Interrupt. */ 4868215976Sjmallett uint64_t dma0fi : 1; /**< DMA0 set Forced Interrupt. */ 4869215976Sjmallett uint64_t reserved_8_8 : 1; 4870215976Sjmallett uint64_t dma3dbo : 1; /**< DMA3 doorbell count overflow. 4871215976Sjmallett Bit[32] of the doorbell count was set. */ 4872215976Sjmallett uint64_t dma2dbo : 1; /**< DMA2 doorbell count overflow. 4873215976Sjmallett Bit[32] of the doorbell count was set. */ 4874215976Sjmallett uint64_t dma1dbo : 1; /**< DMA1 doorbell count overflow. 4875215976Sjmallett Bit[32] of the doorbell count was set. */ 4876215976Sjmallett uint64_t dma0dbo : 1; /**< DMA0 doorbell count overflow. 4877215976Sjmallett Bit[32] of the doorbell count was set. */ 4878215976Sjmallett uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */ 4879215976Sjmallett uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive 4880215976Sjmallett read-data/commit in 0xffff core clocks. */ 4881215976Sjmallett uint64_t rml_wto : 1; /**< RML write did not get commit in 0xffff core clocks. */ 4882215976Sjmallett uint64_t rml_rto : 1; /**< RML read did not return data in 0xffff core clocks. */ 4883215976Sjmallett#else 4884215976Sjmallett uint64_t rml_rto : 1; 4885215976Sjmallett uint64_t rml_wto : 1; 4886215976Sjmallett uint64_t bar0_to : 1; 4887215976Sjmallett uint64_t iob2big : 1; 4888215976Sjmallett uint64_t dma0dbo : 1; 4889215976Sjmallett uint64_t dma1dbo : 1; 4890215976Sjmallett uint64_t dma2dbo : 1; 4891215976Sjmallett uint64_t dma3dbo : 1; 4892215976Sjmallett uint64_t reserved_8_8 : 1; 4893215976Sjmallett uint64_t dma0fi : 1; 4894215976Sjmallett uint64_t dma1fi : 1; 4895215976Sjmallett uint64_t dcnt0 : 1; 4896215976Sjmallett uint64_t dcnt1 : 1; 4897215976Sjmallett uint64_t dtime0 : 1; 4898215976Sjmallett uint64_t dtime1 : 1; 4899215976Sjmallett uint64_t reserved_15_18 : 4; 4900215976Sjmallett uint64_t c0_aeri : 1; 4901215976Sjmallett uint64_t crs0_er : 1; 4902215976Sjmallett uint64_t c0_se : 1; 4903215976Sjmallett uint64_t crs0_dr : 1; 4904215976Sjmallett uint64_t c0_wake : 1; 4905215976Sjmallett uint64_t c0_pmei : 1; 4906215976Sjmallett uint64_t c0_hpint : 1; 4907215976Sjmallett uint64_t c1_aeri : 1; 4908215976Sjmallett uint64_t crs1_er : 1; 4909215976Sjmallett uint64_t c1_se : 1; 4910215976Sjmallett uint64_t crs1_dr : 1; 4911215976Sjmallett uint64_t c1_wake : 1; 4912215976Sjmallett uint64_t c1_pmei : 1; 4913215976Sjmallett uint64_t c1_hpint : 1; 4914215976Sjmallett uint64_t c0_up_b0 : 1; 4915215976Sjmallett uint64_t c0_up_b1 : 1; 4916215976Sjmallett uint64_t c0_up_b2 : 1; 4917215976Sjmallett uint64_t c0_up_wi : 1; 4918215976Sjmallett uint64_t c0_up_bx : 1; 4919215976Sjmallett uint64_t c0_un_b0 : 1; 4920215976Sjmallett uint64_t c0_un_b1 : 1; 4921215976Sjmallett uint64_t c0_un_b2 : 1; 4922215976Sjmallett uint64_t c0_un_wi : 1; 4923215976Sjmallett uint64_t c0_un_bx : 1; 4924215976Sjmallett uint64_t c1_up_b0 : 1; 4925215976Sjmallett uint64_t c1_up_b1 : 1; 4926215976Sjmallett uint64_t c1_up_b2 : 1; 4927215976Sjmallett uint64_t c1_up_wi : 1; 4928215976Sjmallett uint64_t c1_up_bx : 1; 4929215976Sjmallett uint64_t c1_un_b0 : 1; 4930215976Sjmallett uint64_t c1_un_b1 : 1; 4931215976Sjmallett uint64_t c1_un_b2 : 1; 4932215976Sjmallett uint64_t c1_un_wi : 1; 4933215976Sjmallett uint64_t c1_un_bx : 1; 4934215976Sjmallett uint64_t c0_un_wf : 1; 4935215976Sjmallett uint64_t c1_un_wf : 1; 4936215976Sjmallett uint64_t c0_up_wf : 1; 4937215976Sjmallett uint64_t c1_up_wf : 1; 4938215976Sjmallett uint64_t c0_exc : 1; 4939215976Sjmallett uint64_t c1_exc : 1; 4940215976Sjmallett uint64_t c0_ldwn : 1; 4941215976Sjmallett uint64_t c1_ldwn : 1; 4942215976Sjmallett uint64_t int_a : 1; 4943215976Sjmallett uint64_t reserved_62_62 : 1; 4944215976Sjmallett uint64_t mio_inta : 1; 4945215976Sjmallett#endif 4946215976Sjmallett } cn52xxp1; 4947215976Sjmallett struct cvmx_npei_int_sum_s cn56xx; 4948232812Sjmallett struct cvmx_npei_int_sum_cn56xxp1 { 4949232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4950215976Sjmallett uint64_t mio_inta : 1; /**< Interrupt from MIO. */ 4951215976Sjmallett uint64_t reserved_61_62 : 2; 4952215976Sjmallett uint64_t c1_ldwn : 1; /**< Reset request due to link1 down status. */ 4953215976Sjmallett uint64_t c0_ldwn : 1; /**< Reset request due to link0 down status. */ 4954215976Sjmallett uint64_t c1_exc : 1; /**< Set when the PESC1_DBG_INFO register has a bit 4955215976Sjmallett set and its cooresponding PESC1_DBG_INFO_EN bit 4956215976Sjmallett is set. */ 4957215976Sjmallett uint64_t c0_exc : 1; /**< Set when the PESC0_DBG_INFO register has a bit 4958215976Sjmallett set and its cooresponding PESC0_DBG_INFO_EN bit 4959215976Sjmallett is set. */ 4960215976Sjmallett uint64_t c1_up_wf : 1; /**< Received Unsupported P-TLP for filtered window 4961215976Sjmallett register. Core1. */ 4962215976Sjmallett uint64_t c0_up_wf : 1; /**< Received Unsupported P-TLP for filtered window 4963215976Sjmallett register. Core0. */ 4964215976Sjmallett uint64_t c1_un_wf : 1; /**< Received Unsupported N-TLP for filtered window 4965215976Sjmallett register. Core1. */ 4966215976Sjmallett uint64_t c0_un_wf : 1; /**< Received Unsupported N-TLP for filtered window 4967215976Sjmallett register. Core0. */ 4968215976Sjmallett uint64_t c1_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar. 4969215976Sjmallett Core 1. */ 4970215976Sjmallett uint64_t c1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register. 4971215976Sjmallett Core 1. */ 4972215976Sjmallett uint64_t c1_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2. 4973215976Sjmallett Core 1. */ 4974215976Sjmallett uint64_t c1_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1. 4975215976Sjmallett Core 1. */ 4976215976Sjmallett uint64_t c1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0. 4977215976Sjmallett Core 1. */ 4978215976Sjmallett uint64_t c1_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar. 4979215976Sjmallett Core 1. */ 4980215976Sjmallett uint64_t c1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register. 4981215976Sjmallett Core 1. */ 4982215976Sjmallett uint64_t c1_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2. 4983215976Sjmallett Core 1. */ 4984215976Sjmallett uint64_t c1_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1. 4985215976Sjmallett Core 1. */ 4986215976Sjmallett uint64_t c1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0. 4987215976Sjmallett Core 1. */ 4988215976Sjmallett uint64_t c0_un_bx : 1; /**< Received Unsupported N-TLP for unknown Bar. 4989215976Sjmallett Core 0. */ 4990215976Sjmallett uint64_t c0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register. 4991215976Sjmallett Core 0. */ 4992215976Sjmallett uint64_t c0_un_b2 : 1; /**< Received Unsupported N-TLP for Bar2. 4993215976Sjmallett Core 0. */ 4994215976Sjmallett uint64_t c0_un_b1 : 1; /**< Received Unsupported N-TLP for Bar1. 4995215976Sjmallett Core 0. */ 4996215976Sjmallett uint64_t c0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0. 4997215976Sjmallett Core 0. */ 4998215976Sjmallett uint64_t c0_up_bx : 1; /**< Received Unsupported P-TLP for unknown Bar. 4999215976Sjmallett Core 0. */ 5000215976Sjmallett uint64_t c0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register. 5001215976Sjmallett Core 0. */ 5002215976Sjmallett uint64_t c0_up_b2 : 1; /**< Received Unsupported P-TLP for Bar2. 5003215976Sjmallett Core 0. */ 5004215976Sjmallett uint64_t c0_up_b1 : 1; /**< Received Unsupported P-TLP for Bar1. 5005215976Sjmallett Core 0. */ 5006215976Sjmallett uint64_t c0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0. 5007215976Sjmallett Core 0. */ 5008215976Sjmallett uint64_t c1_hpint : 1; /**< Hot-Plug Interrupt. 5009215976Sjmallett Pcie Core 1 (hp_int). 5010215976Sjmallett This interrupt will only be generated when 5011215976Sjmallett PCIERC1_CFG034[DLLS_C] is generated. Hot plug is 5012215976Sjmallett not supported. */ 5013215976Sjmallett uint64_t c1_pmei : 1; /**< PME Interrupt. 5014215976Sjmallett Pcie Core 1. (cfg_pme_int) */ 5015215976Sjmallett uint64_t c1_wake : 1; /**< Wake up from Power Management Unit. 5016215976Sjmallett Pcie Core 1. (wake_n) 5017215976Sjmallett Octeon will never generate this interrupt. */ 5018215976Sjmallett uint64_t reserved_29_29 : 1; 5019215976Sjmallett uint64_t c1_se : 1; /**< System Error, RC Mode Only. 5020215976Sjmallett Pcie Core 1. (cfg_sys_err_rc) */ 5021215976Sjmallett uint64_t reserved_27_27 : 1; 5022215976Sjmallett uint64_t c1_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only. 5023215976Sjmallett Pcie Core 1. */ 5024215976Sjmallett uint64_t c0_hpint : 1; /**< Hot-Plug Interrupt. 5025215976Sjmallett Pcie Core 0 (hp_int). 5026215976Sjmallett This interrupt will only be generated when 5027215976Sjmallett PCIERC0_CFG034[DLLS_C] is generated. Hot plug is 5028215976Sjmallett not supported. */ 5029215976Sjmallett uint64_t c0_pmei : 1; /**< PME Interrupt. 5030215976Sjmallett Pcie Core 0. (cfg_pme_int) */ 5031215976Sjmallett uint64_t c0_wake : 1; /**< Wake up from Power Management Unit. 5032215976Sjmallett Pcie Core 0. (wake_n) 5033215976Sjmallett Octeon will never generate this interrupt. */ 5034215976Sjmallett uint64_t reserved_22_22 : 1; 5035215976Sjmallett uint64_t c0_se : 1; /**< System Error, RC Mode Only. 5036215976Sjmallett Pcie Core 0. (cfg_sys_err_rc) */ 5037215976Sjmallett uint64_t reserved_20_20 : 1; 5038215976Sjmallett uint64_t c0_aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only. 5039215976Sjmallett Pcie Core 0 (cfg_aer_rc_err_int). */ 5040215976Sjmallett uint64_t reserved_15_18 : 4; 5041215976Sjmallett uint64_t dtime1 : 1; /**< Whenever NPEI_DMA_CNTS[DMA1] is not 0, the 5042215976Sjmallett DMA_CNT1 timer increments every core clock. When 5043215976Sjmallett DMA_CNT1 timer exceeds NPEI_DMA1_INT_LEVEL[TIME], 5044215976Sjmallett this bit is set. Writing a '1' to this bit also 5045215976Sjmallett clears the DMA_CNT1 timer. */ 5046215976Sjmallett uint64_t dtime0 : 1; /**< Whenever NPEI_DMA_CNTS[DMA0] is not 0, the 5047215976Sjmallett DMA_CNT0 timer increments every core clock. When 5048215976Sjmallett DMA_CNT0 timer exceeds NPEI_DMA0_INT_LEVEL[TIME], 5049215976Sjmallett this bit is set. Writing a '1' to this bit also 5050215976Sjmallett clears the DMA_CNT0 timer. */ 5051215976Sjmallett uint64_t dcnt1 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA1] was/is 5052215976Sjmallett greater than NPEI_DMA1_INT_LEVEL[CNT]. */ 5053215976Sjmallett uint64_t dcnt0 : 1; /**< This bit indicates that NPEI_DMA_CNTS[DMA0] was/is 5054215976Sjmallett greater than NPEI_DMA0_INT_LEVEL[CNT]. */ 5055215976Sjmallett uint64_t dma1fi : 1; /**< DMA0 set Forced Interrupt. */ 5056215976Sjmallett uint64_t dma0fi : 1; /**< DMA0 set Forced Interrupt. */ 5057215976Sjmallett uint64_t dma4dbo : 1; /**< DMA4 doorbell overflow. 5058215976Sjmallett Bit[32] of the doorbell count was set. */ 5059215976Sjmallett uint64_t dma3dbo : 1; /**< DMA3 doorbell overflow. 5060215976Sjmallett Bit[32] of the doorbell count was set. */ 5061215976Sjmallett uint64_t dma2dbo : 1; /**< DMA2 doorbell overflow. 5062215976Sjmallett Bit[32] of the doorbell count was set. */ 5063215976Sjmallett uint64_t dma1dbo : 1; /**< DMA1 doorbell overflow. 5064215976Sjmallett Bit[32] of the doorbell count was set. */ 5065215976Sjmallett uint64_t dma0dbo : 1; /**< DMA0 doorbell overflow. 5066215976Sjmallett Bit[32] of the doorbell count was set. */ 5067215976Sjmallett uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */ 5068215976Sjmallett uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive 5069215976Sjmallett read-data/commit in 0xffff core clocks. */ 5070215976Sjmallett uint64_t rml_wto : 1; /**< RML write did not get commit in 0xffff core clocks. */ 5071215976Sjmallett uint64_t rml_rto : 1; /**< RML read did not return data in 0xffff core clocks. */ 5072215976Sjmallett#else 5073215976Sjmallett uint64_t rml_rto : 1; 5074215976Sjmallett uint64_t rml_wto : 1; 5075215976Sjmallett uint64_t bar0_to : 1; 5076215976Sjmallett uint64_t iob2big : 1; 5077215976Sjmallett uint64_t dma0dbo : 1; 5078215976Sjmallett uint64_t dma1dbo : 1; 5079215976Sjmallett uint64_t dma2dbo : 1; 5080215976Sjmallett uint64_t dma3dbo : 1; 5081215976Sjmallett uint64_t dma4dbo : 1; 5082215976Sjmallett uint64_t dma0fi : 1; 5083215976Sjmallett uint64_t dma1fi : 1; 5084215976Sjmallett uint64_t dcnt0 : 1; 5085215976Sjmallett uint64_t dcnt1 : 1; 5086215976Sjmallett uint64_t dtime0 : 1; 5087215976Sjmallett uint64_t dtime1 : 1; 5088215976Sjmallett uint64_t reserved_15_18 : 4; 5089215976Sjmallett uint64_t c0_aeri : 1; 5090215976Sjmallett uint64_t reserved_20_20 : 1; 5091215976Sjmallett uint64_t c0_se : 1; 5092215976Sjmallett uint64_t reserved_22_22 : 1; 5093215976Sjmallett uint64_t c0_wake : 1; 5094215976Sjmallett uint64_t c0_pmei : 1; 5095215976Sjmallett uint64_t c0_hpint : 1; 5096215976Sjmallett uint64_t c1_aeri : 1; 5097215976Sjmallett uint64_t reserved_27_27 : 1; 5098215976Sjmallett uint64_t c1_se : 1; 5099215976Sjmallett uint64_t reserved_29_29 : 1; 5100215976Sjmallett uint64_t c1_wake : 1; 5101215976Sjmallett uint64_t c1_pmei : 1; 5102215976Sjmallett uint64_t c1_hpint : 1; 5103215976Sjmallett uint64_t c0_up_b0 : 1; 5104215976Sjmallett uint64_t c0_up_b1 : 1; 5105215976Sjmallett uint64_t c0_up_b2 : 1; 5106215976Sjmallett uint64_t c0_up_wi : 1; 5107215976Sjmallett uint64_t c0_up_bx : 1; 5108215976Sjmallett uint64_t c0_un_b0 : 1; 5109215976Sjmallett uint64_t c0_un_b1 : 1; 5110215976Sjmallett uint64_t c0_un_b2 : 1; 5111215976Sjmallett uint64_t c0_un_wi : 1; 5112215976Sjmallett uint64_t c0_un_bx : 1; 5113215976Sjmallett uint64_t c1_up_b0 : 1; 5114215976Sjmallett uint64_t c1_up_b1 : 1; 5115215976Sjmallett uint64_t c1_up_b2 : 1; 5116215976Sjmallett uint64_t c1_up_wi : 1; 5117215976Sjmallett uint64_t c1_up_bx : 1; 5118215976Sjmallett uint64_t c1_un_b0 : 1; 5119215976Sjmallett uint64_t c1_un_b1 : 1; 5120215976Sjmallett uint64_t c1_un_b2 : 1; 5121215976Sjmallett uint64_t c1_un_wi : 1; 5122215976Sjmallett uint64_t c1_un_bx : 1; 5123215976Sjmallett uint64_t c0_un_wf : 1; 5124215976Sjmallett uint64_t c1_un_wf : 1; 5125215976Sjmallett uint64_t c0_up_wf : 1; 5126215976Sjmallett uint64_t c1_up_wf : 1; 5127215976Sjmallett uint64_t c0_exc : 1; 5128215976Sjmallett uint64_t c1_exc : 1; 5129215976Sjmallett uint64_t c0_ldwn : 1; 5130215976Sjmallett uint64_t c1_ldwn : 1; 5131215976Sjmallett uint64_t reserved_61_62 : 2; 5132215976Sjmallett uint64_t mio_inta : 1; 5133215976Sjmallett#endif 5134215976Sjmallett } cn56xxp1; 5135215976Sjmallett}; 5136215976Sjmalletttypedef union cvmx_npei_int_sum cvmx_npei_int_sum_t; 5137215976Sjmallett 5138215976Sjmallett/** 5139215976Sjmallett * cvmx_npei_int_sum2 5140215976Sjmallett * 5141215976Sjmallett * NPEI_INTERRUPT_SUM2 = NPI Interrupt Summary2 Register 5142215976Sjmallett * 5143215976Sjmallett * This is a read only copy of the NPEI_INTERRUPT_SUM register with bit variances. 5144215976Sjmallett */ 5145232812Sjmallettunion cvmx_npei_int_sum2 { 5146215976Sjmallett uint64_t u64; 5147232812Sjmallett struct cvmx_npei_int_sum2_s { 5148232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5149215976Sjmallett uint64_t mio_inta : 1; /**< Equal to the cooresponding bit if the 5150215976Sjmallett NPEI_INT_SUM register. */ 5151215976Sjmallett uint64_t reserved_62_62 : 1; 5152215976Sjmallett uint64_t int_a : 1; /**< Set when a bit in the NPEI_INT_A_SUM register and 5153215976Sjmallett the cooresponding bit in the NPEI_INT_A_ENB2 5154215976Sjmallett register is set. */ 5155215976Sjmallett uint64_t c1_ldwn : 1; /**< Equal to the cooresponding bit if the 5156215976Sjmallett NPEI_INT_SUM register. */ 5157215976Sjmallett uint64_t c0_ldwn : 1; /**< Equal to the cooresponding bit if the 5158215976Sjmallett NPEI_INT_SUM register. */ 5159215976Sjmallett uint64_t c1_exc : 1; /**< Equal to the cooresponding bit if the 5160215976Sjmallett NPEI_INT_SUM register. */ 5161215976Sjmallett uint64_t c0_exc : 1; /**< Equal to the cooresponding bit if the 5162215976Sjmallett NPEI_INT_SUM register. */ 5163215976Sjmallett uint64_t c1_up_wf : 1; /**< Equal to the cooresponding bit if the 5164215976Sjmallett NPEI_INT_SUM register. */ 5165215976Sjmallett uint64_t c0_up_wf : 1; /**< Equal to the cooresponding bit if the 5166215976Sjmallett NPEI_INT_SUM register. */ 5167215976Sjmallett uint64_t c1_un_wf : 1; /**< Equal to the cooresponding bit if the 5168215976Sjmallett NPEI_INT_SUM register. */ 5169215976Sjmallett uint64_t c0_un_wf : 1; /**< Equal to the cooresponding bit if the 5170215976Sjmallett NPEI_INT_SUM register. */ 5171215976Sjmallett uint64_t c1_un_bx : 1; /**< Equal to the cooresponding bit if the 5172215976Sjmallett NPEI_INT_SUM register. */ 5173215976Sjmallett uint64_t c1_un_wi : 1; /**< Equal to the cooresponding bit if the 5174215976Sjmallett NPEI_INT_SUM register. */ 5175215976Sjmallett uint64_t c1_un_b2 : 1; /**< Equal to the cooresponding bit if the 5176215976Sjmallett NPEI_INT_SUM register. */ 5177215976Sjmallett uint64_t c1_un_b1 : 1; /**< Equal to the cooresponding bit if the 5178215976Sjmallett NPEI_INT_SUM register. */ 5179215976Sjmallett uint64_t c1_un_b0 : 1; /**< Equal to the cooresponding bit if the 5180215976Sjmallett NPEI_INT_SUM register. */ 5181215976Sjmallett uint64_t c1_up_bx : 1; /**< Equal to the cooresponding bit if the 5182215976Sjmallett NPEI_INT_SUM register. */ 5183215976Sjmallett uint64_t c1_up_wi : 1; /**< Equal to the cooresponding bit if the 5184215976Sjmallett NPEI_INT_SUM register. */ 5185215976Sjmallett uint64_t c1_up_b2 : 1; /**< Equal to the cooresponding bit if the 5186215976Sjmallett NPEI_INT_SUM register. */ 5187215976Sjmallett uint64_t c1_up_b1 : 1; /**< Equal to the cooresponding bit if the 5188215976Sjmallett NPEI_INT_SUM register. */ 5189215976Sjmallett uint64_t c1_up_b0 : 1; /**< Equal to the cooresponding bit if the 5190215976Sjmallett NPEI_INT_SUM register. */ 5191215976Sjmallett uint64_t c0_un_bx : 1; /**< Equal to the cooresponding bit if the 5192215976Sjmallett NPEI_INT_SUM register. */ 5193215976Sjmallett uint64_t c0_un_wi : 1; /**< Equal to the cooresponding bit if the 5194215976Sjmallett NPEI_INT_SUM register. */ 5195215976Sjmallett uint64_t c0_un_b2 : 1; /**< Equal to the cooresponding bit if the 5196215976Sjmallett NPEI_INT_SUM register. */ 5197215976Sjmallett uint64_t c0_un_b1 : 1; /**< Equal to the cooresponding bit if the 5198215976Sjmallett NPEI_INT_SUM register. */ 5199215976Sjmallett uint64_t c0_un_b0 : 1; /**< Equal to the cooresponding bit if the 5200215976Sjmallett NPEI_INT_SUM register. */ 5201215976Sjmallett uint64_t c0_up_bx : 1; /**< Equal to the cooresponding bit if the 5202215976Sjmallett NPEI_INT_SUM register. */ 5203215976Sjmallett uint64_t c0_up_wi : 1; /**< Equal to the cooresponding bit if the 5204215976Sjmallett NPEI_INT_SUM register. */ 5205215976Sjmallett uint64_t c0_up_b2 : 1; /**< Equal to the cooresponding bit if the 5206215976Sjmallett NPEI_INT_SUM register. */ 5207215976Sjmallett uint64_t c0_up_b1 : 1; /**< Equal to the cooresponding bit if the 5208215976Sjmallett NPEI_INT_SUM register. */ 5209215976Sjmallett uint64_t c0_up_b0 : 1; /**< Equal to the cooresponding bit if the 5210215976Sjmallett NPEI_INT_SUM register. */ 5211215976Sjmallett uint64_t c1_hpint : 1; /**< Equal to the cooresponding bit if the 5212215976Sjmallett NPEI_INT_SUM register. */ 5213215976Sjmallett uint64_t c1_pmei : 1; /**< Equal to the cooresponding bit if the 5214215976Sjmallett NPEI_INT_SUM register. */ 5215215976Sjmallett uint64_t c1_wake : 1; /**< Equal to the cooresponding bit if the 5216215976Sjmallett NPEI_INT_SUM register. */ 5217215976Sjmallett uint64_t crs1_dr : 1; /**< Equal to the cooresponding bit if the 5218215976Sjmallett NPEI_INT_SUM register. */ 5219215976Sjmallett uint64_t c1_se : 1; /**< Equal to the cooresponding bit if the 5220215976Sjmallett NPEI_INT_SUM register. */ 5221215976Sjmallett uint64_t crs1_er : 1; /**< Equal to the cooresponding bit if the 5222215976Sjmallett NPEI_INT_SUM register. */ 5223215976Sjmallett uint64_t c1_aeri : 1; /**< Equal to the cooresponding bit if the 5224215976Sjmallett NPEI_INT_SUM register. */ 5225215976Sjmallett uint64_t c0_hpint : 1; /**< Equal to the cooresponding bit if the 5226215976Sjmallett NPEI_INT_SUM register. */ 5227215976Sjmallett uint64_t c0_pmei : 1; /**< Equal to the cooresponding bit if the 5228215976Sjmallett NPEI_INT_SUM register. */ 5229215976Sjmallett uint64_t c0_wake : 1; /**< Equal to the cooresponding bit if the 5230215976Sjmallett NPEI_INT_SUM register. */ 5231215976Sjmallett uint64_t crs0_dr : 1; /**< Equal to the cooresponding bit if the 5232215976Sjmallett NPEI_INT_SUM register. */ 5233215976Sjmallett uint64_t c0_se : 1; /**< Equal to the cooresponding bit if the 5234215976Sjmallett NPEI_INT_SUM register. */ 5235215976Sjmallett uint64_t crs0_er : 1; /**< Equal to the cooresponding bit if the 5236215976Sjmallett NPEI_INT_SUM register. */ 5237215976Sjmallett uint64_t c0_aeri : 1; /**< Equal to the cooresponding bit if the 5238215976Sjmallett NPEI_INT_SUM register. */ 5239215976Sjmallett uint64_t reserved_15_18 : 4; 5240215976Sjmallett uint64_t dtime1 : 1; /**< Equal to the cooresponding bit if the 5241215976Sjmallett NPEI_INT_SUM register. */ 5242215976Sjmallett uint64_t dtime0 : 1; /**< Equal to the cooresponding bit if the 5243215976Sjmallett NPEI_INT_SUM register. */ 5244215976Sjmallett uint64_t dcnt1 : 1; /**< Equal to the cooresponding bit if the 5245215976Sjmallett NPEI_INT_SUM register. */ 5246215976Sjmallett uint64_t dcnt0 : 1; /**< Equal to the cooresponding bit if the 5247215976Sjmallett NPEI_INT_SUM register. */ 5248215976Sjmallett uint64_t dma1fi : 1; /**< Equal to the cooresponding bit if the 5249215976Sjmallett NPEI_INT_SUM register. */ 5250215976Sjmallett uint64_t dma0fi : 1; /**< Equal to the cooresponding bit if the 5251215976Sjmallett NPEI_INT_SUM register. */ 5252215976Sjmallett uint64_t reserved_8_8 : 1; 5253215976Sjmallett uint64_t dma3dbo : 1; /**< Equal to the cooresponding bit if the 5254215976Sjmallett NPEI_INT_SUM register. */ 5255215976Sjmallett uint64_t dma2dbo : 1; /**< Equal to the cooresponding bit if the 5256215976Sjmallett NPEI_INT_SUM register. */ 5257215976Sjmallett uint64_t dma1dbo : 1; /**< Equal to the cooresponding bit if the 5258215976Sjmallett NPEI_INT_SUM register. */ 5259215976Sjmallett uint64_t dma0dbo : 1; /**< Equal to the cooresponding bit if the 5260215976Sjmallett NPEI_INT_SUM register. */ 5261215976Sjmallett uint64_t iob2big : 1; /**< Equal to the cooresponding bit if the 5262215976Sjmallett NPEI_INT_SUM register. */ 5263215976Sjmallett uint64_t bar0_to : 1; /**< Equal to the cooresponding bit if the 5264215976Sjmallett NPEI_INT_SUM register. */ 5265215976Sjmallett uint64_t rml_wto : 1; /**< Equal to the cooresponding bit if the 5266215976Sjmallett NPEI_INT_SUM register. */ 5267215976Sjmallett uint64_t rml_rto : 1; /**< Equal to the cooresponding bit if the 5268215976Sjmallett NPEI_INT_SUM register. */ 5269215976Sjmallett#else 5270215976Sjmallett uint64_t rml_rto : 1; 5271215976Sjmallett uint64_t rml_wto : 1; 5272215976Sjmallett uint64_t bar0_to : 1; 5273215976Sjmallett uint64_t iob2big : 1; 5274215976Sjmallett uint64_t dma0dbo : 1; 5275215976Sjmallett uint64_t dma1dbo : 1; 5276215976Sjmallett uint64_t dma2dbo : 1; 5277215976Sjmallett uint64_t dma3dbo : 1; 5278215976Sjmallett uint64_t reserved_8_8 : 1; 5279215976Sjmallett uint64_t dma0fi : 1; 5280215976Sjmallett uint64_t dma1fi : 1; 5281215976Sjmallett uint64_t dcnt0 : 1; 5282215976Sjmallett uint64_t dcnt1 : 1; 5283215976Sjmallett uint64_t dtime0 : 1; 5284215976Sjmallett uint64_t dtime1 : 1; 5285215976Sjmallett uint64_t reserved_15_18 : 4; 5286215976Sjmallett uint64_t c0_aeri : 1; 5287215976Sjmallett uint64_t crs0_er : 1; 5288215976Sjmallett uint64_t c0_se : 1; 5289215976Sjmallett uint64_t crs0_dr : 1; 5290215976Sjmallett uint64_t c0_wake : 1; 5291215976Sjmallett uint64_t c0_pmei : 1; 5292215976Sjmallett uint64_t c0_hpint : 1; 5293215976Sjmallett uint64_t c1_aeri : 1; 5294215976Sjmallett uint64_t crs1_er : 1; 5295215976Sjmallett uint64_t c1_se : 1; 5296215976Sjmallett uint64_t crs1_dr : 1; 5297215976Sjmallett uint64_t c1_wake : 1; 5298215976Sjmallett uint64_t c1_pmei : 1; 5299215976Sjmallett uint64_t c1_hpint : 1; 5300215976Sjmallett uint64_t c0_up_b0 : 1; 5301215976Sjmallett uint64_t c0_up_b1 : 1; 5302215976Sjmallett uint64_t c0_up_b2 : 1; 5303215976Sjmallett uint64_t c0_up_wi : 1; 5304215976Sjmallett uint64_t c0_up_bx : 1; 5305215976Sjmallett uint64_t c0_un_b0 : 1; 5306215976Sjmallett uint64_t c0_un_b1 : 1; 5307215976Sjmallett uint64_t c0_un_b2 : 1; 5308215976Sjmallett uint64_t c0_un_wi : 1; 5309215976Sjmallett uint64_t c0_un_bx : 1; 5310215976Sjmallett uint64_t c1_up_b0 : 1; 5311215976Sjmallett uint64_t c1_up_b1 : 1; 5312215976Sjmallett uint64_t c1_up_b2 : 1; 5313215976Sjmallett uint64_t c1_up_wi : 1; 5314215976Sjmallett uint64_t c1_up_bx : 1; 5315215976Sjmallett uint64_t c1_un_b0 : 1; 5316215976Sjmallett uint64_t c1_un_b1 : 1; 5317215976Sjmallett uint64_t c1_un_b2 : 1; 5318215976Sjmallett uint64_t c1_un_wi : 1; 5319215976Sjmallett uint64_t c1_un_bx : 1; 5320215976Sjmallett uint64_t c0_un_wf : 1; 5321215976Sjmallett uint64_t c1_un_wf : 1; 5322215976Sjmallett uint64_t c0_up_wf : 1; 5323215976Sjmallett uint64_t c1_up_wf : 1; 5324215976Sjmallett uint64_t c0_exc : 1; 5325215976Sjmallett uint64_t c1_exc : 1; 5326215976Sjmallett uint64_t c0_ldwn : 1; 5327215976Sjmallett uint64_t c1_ldwn : 1; 5328215976Sjmallett uint64_t int_a : 1; 5329215976Sjmallett uint64_t reserved_62_62 : 1; 5330215976Sjmallett uint64_t mio_inta : 1; 5331215976Sjmallett#endif 5332215976Sjmallett } s; 5333215976Sjmallett struct cvmx_npei_int_sum2_s cn52xx; 5334215976Sjmallett struct cvmx_npei_int_sum2_s cn52xxp1; 5335215976Sjmallett struct cvmx_npei_int_sum2_s cn56xx; 5336215976Sjmallett}; 5337215976Sjmalletttypedef union cvmx_npei_int_sum2 cvmx_npei_int_sum2_t; 5338215976Sjmallett 5339215976Sjmallett/** 5340215976Sjmallett * cvmx_npei_last_win_rdata0 5341215976Sjmallett * 5342215976Sjmallett * NPEI_LAST_WIN_RDATA0 = NPEI Last Window Read Data Port0 5343215976Sjmallett * 5344215976Sjmallett * The data from the last initiated window read. 5345215976Sjmallett */ 5346232812Sjmallettunion cvmx_npei_last_win_rdata0 { 5347215976Sjmallett uint64_t u64; 5348232812Sjmallett struct cvmx_npei_last_win_rdata0_s { 5349232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5350215976Sjmallett uint64_t data : 64; /**< Last window read data. */ 5351215976Sjmallett#else 5352215976Sjmallett uint64_t data : 64; 5353215976Sjmallett#endif 5354215976Sjmallett } s; 5355215976Sjmallett struct cvmx_npei_last_win_rdata0_s cn52xx; 5356215976Sjmallett struct cvmx_npei_last_win_rdata0_s cn52xxp1; 5357215976Sjmallett struct cvmx_npei_last_win_rdata0_s cn56xx; 5358215976Sjmallett struct cvmx_npei_last_win_rdata0_s cn56xxp1; 5359215976Sjmallett}; 5360215976Sjmalletttypedef union cvmx_npei_last_win_rdata0 cvmx_npei_last_win_rdata0_t; 5361215976Sjmallett 5362215976Sjmallett/** 5363215976Sjmallett * cvmx_npei_last_win_rdata1 5364215976Sjmallett * 5365215976Sjmallett * NPEI_LAST_WIN_RDATA1 = NPEI Last Window Read Data Port1 5366215976Sjmallett * 5367215976Sjmallett * The data from the last initiated window read. 5368215976Sjmallett */ 5369232812Sjmallettunion cvmx_npei_last_win_rdata1 { 5370215976Sjmallett uint64_t u64; 5371232812Sjmallett struct cvmx_npei_last_win_rdata1_s { 5372232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5373215976Sjmallett uint64_t data : 64; /**< Last window read data. */ 5374215976Sjmallett#else 5375215976Sjmallett uint64_t data : 64; 5376215976Sjmallett#endif 5377215976Sjmallett } s; 5378215976Sjmallett struct cvmx_npei_last_win_rdata1_s cn52xx; 5379215976Sjmallett struct cvmx_npei_last_win_rdata1_s cn52xxp1; 5380215976Sjmallett struct cvmx_npei_last_win_rdata1_s cn56xx; 5381215976Sjmallett struct cvmx_npei_last_win_rdata1_s cn56xxp1; 5382215976Sjmallett}; 5383215976Sjmalletttypedef union cvmx_npei_last_win_rdata1 cvmx_npei_last_win_rdata1_t; 5384215976Sjmallett 5385215976Sjmallett/** 5386215976Sjmallett * cvmx_npei_mem_access_ctl 5387215976Sjmallett * 5388215976Sjmallett * NPEI_MEM_ACCESS_CTL = NPEI's Memory Access Control 5389215976Sjmallett * 5390215976Sjmallett * Contains control for access to the PCIe address space. 5391215976Sjmallett */ 5392232812Sjmallettunion cvmx_npei_mem_access_ctl { 5393215976Sjmallett uint64_t u64; 5394232812Sjmallett struct cvmx_npei_mem_access_ctl_s { 5395232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5396215976Sjmallett uint64_t reserved_14_63 : 50; 5397215976Sjmallett uint64_t max_word : 4; /**< The maximum number of words to merge into a single 5398215976Sjmallett write operation from the PPs to the PCIe. Legal 5399215976Sjmallett values are 1 to 16, where a '0' is treated as 16. */ 5400215976Sjmallett uint64_t timer : 10; /**< When the NPEI starts a PP to PCIe write it waits 5401215976Sjmallett no longer than the value of TIMER in eclks to 5402215976Sjmallett merge additional writes from the PPs into 1 5403215976Sjmallett large write. The values for this field is 1 to 5404215976Sjmallett 1024 where a value of '0' is treated as 1024. */ 5405215976Sjmallett#else 5406215976Sjmallett uint64_t timer : 10; 5407215976Sjmallett uint64_t max_word : 4; 5408215976Sjmallett uint64_t reserved_14_63 : 50; 5409215976Sjmallett#endif 5410215976Sjmallett } s; 5411215976Sjmallett struct cvmx_npei_mem_access_ctl_s cn52xx; 5412215976Sjmallett struct cvmx_npei_mem_access_ctl_s cn52xxp1; 5413215976Sjmallett struct cvmx_npei_mem_access_ctl_s cn56xx; 5414215976Sjmallett struct cvmx_npei_mem_access_ctl_s cn56xxp1; 5415215976Sjmallett}; 5416215976Sjmalletttypedef union cvmx_npei_mem_access_ctl cvmx_npei_mem_access_ctl_t; 5417215976Sjmallett 5418215976Sjmallett/** 5419215976Sjmallett * cvmx_npei_mem_access_subid# 5420215976Sjmallett * 5421215976Sjmallett * NPEI_MEM_ACCESS_SUBIDX = NPEI Memory Access SubidX Register 5422215976Sjmallett * 5423215976Sjmallett * Contains address index and control bits for access to memory from Core PPs. 5424215976Sjmallett */ 5425232812Sjmallettunion cvmx_npei_mem_access_subidx { 5426215976Sjmallett uint64_t u64; 5427232812Sjmallett struct cvmx_npei_mem_access_subidx_s { 5428232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5429215976Sjmallett uint64_t reserved_42_63 : 22; 5430215976Sjmallett uint64_t zero : 1; /**< Causes all byte reads to be zero length reads. 5431215976Sjmallett Returns to the EXEC a zero for all read data. */ 5432215976Sjmallett uint64_t port : 2; /**< Port the request is sent to. */ 5433215976Sjmallett uint64_t nmerge : 1; /**< No merging is allowed in this window. */ 5434215976Sjmallett uint64_t esr : 2; /**< Endian-swap for Reads. */ 5435215976Sjmallett uint64_t esw : 2; /**< Endian-swap for Writes. */ 5436215976Sjmallett uint64_t nsr : 1; /**< No Snoop for Reads. */ 5437215976Sjmallett uint64_t nsw : 1; /**< No Snoop for Writes. */ 5438215976Sjmallett uint64_t ror : 1; /**< Relaxed Ordering for Reads. */ 5439215976Sjmallett uint64_t row : 1; /**< Relaxed Ordering for Writes. */ 5440215976Sjmallett uint64_t ba : 30; /**< PCIe Adddress Bits <63:34>. */ 5441215976Sjmallett#else 5442215976Sjmallett uint64_t ba : 30; 5443215976Sjmallett uint64_t row : 1; 5444215976Sjmallett uint64_t ror : 1; 5445215976Sjmallett uint64_t nsw : 1; 5446215976Sjmallett uint64_t nsr : 1; 5447215976Sjmallett uint64_t esw : 2; 5448215976Sjmallett uint64_t esr : 2; 5449215976Sjmallett uint64_t nmerge : 1; 5450215976Sjmallett uint64_t port : 2; 5451215976Sjmallett uint64_t zero : 1; 5452215976Sjmallett uint64_t reserved_42_63 : 22; 5453215976Sjmallett#endif 5454215976Sjmallett } s; 5455215976Sjmallett struct cvmx_npei_mem_access_subidx_s cn52xx; 5456215976Sjmallett struct cvmx_npei_mem_access_subidx_s cn52xxp1; 5457215976Sjmallett struct cvmx_npei_mem_access_subidx_s cn56xx; 5458215976Sjmallett struct cvmx_npei_mem_access_subidx_s cn56xxp1; 5459215976Sjmallett}; 5460215976Sjmalletttypedef union cvmx_npei_mem_access_subidx cvmx_npei_mem_access_subidx_t; 5461215976Sjmallett 5462215976Sjmallett/** 5463215976Sjmallett * cvmx_npei_msi_enb0 5464215976Sjmallett * 5465215976Sjmallett * NPEI_MSI_ENB0 = NPEI MSI Enable0 5466215976Sjmallett * 5467215976Sjmallett * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV0. 5468215976Sjmallett */ 5469232812Sjmallettunion cvmx_npei_msi_enb0 { 5470215976Sjmallett uint64_t u64; 5471232812Sjmallett struct cvmx_npei_msi_enb0_s { 5472232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5473215976Sjmallett uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV0. */ 5474215976Sjmallett#else 5475215976Sjmallett uint64_t enb : 64; 5476215976Sjmallett#endif 5477215976Sjmallett } s; 5478215976Sjmallett struct cvmx_npei_msi_enb0_s cn52xx; 5479215976Sjmallett struct cvmx_npei_msi_enb0_s cn52xxp1; 5480215976Sjmallett struct cvmx_npei_msi_enb0_s cn56xx; 5481215976Sjmallett struct cvmx_npei_msi_enb0_s cn56xxp1; 5482215976Sjmallett}; 5483215976Sjmalletttypedef union cvmx_npei_msi_enb0 cvmx_npei_msi_enb0_t; 5484215976Sjmallett 5485215976Sjmallett/** 5486215976Sjmallett * cvmx_npei_msi_enb1 5487215976Sjmallett * 5488215976Sjmallett * NPEI_MSI_ENB1 = NPEI MSI Enable1 5489215976Sjmallett * 5490215976Sjmallett * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV1. 5491215976Sjmallett */ 5492232812Sjmallettunion cvmx_npei_msi_enb1 { 5493215976Sjmallett uint64_t u64; 5494232812Sjmallett struct cvmx_npei_msi_enb1_s { 5495232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5496215976Sjmallett uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV1. */ 5497215976Sjmallett#else 5498215976Sjmallett uint64_t enb : 64; 5499215976Sjmallett#endif 5500215976Sjmallett } s; 5501215976Sjmallett struct cvmx_npei_msi_enb1_s cn52xx; 5502215976Sjmallett struct cvmx_npei_msi_enb1_s cn52xxp1; 5503215976Sjmallett struct cvmx_npei_msi_enb1_s cn56xx; 5504215976Sjmallett struct cvmx_npei_msi_enb1_s cn56xxp1; 5505215976Sjmallett}; 5506215976Sjmalletttypedef union cvmx_npei_msi_enb1 cvmx_npei_msi_enb1_t; 5507215976Sjmallett 5508215976Sjmallett/** 5509215976Sjmallett * cvmx_npei_msi_enb2 5510215976Sjmallett * 5511215976Sjmallett * NPEI_MSI_ENB2 = NPEI MSI Enable2 5512215976Sjmallett * 5513215976Sjmallett * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV2. 5514215976Sjmallett */ 5515232812Sjmallettunion cvmx_npei_msi_enb2 { 5516215976Sjmallett uint64_t u64; 5517232812Sjmallett struct cvmx_npei_msi_enb2_s { 5518232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5519215976Sjmallett uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV2. */ 5520215976Sjmallett#else 5521215976Sjmallett uint64_t enb : 64; 5522215976Sjmallett#endif 5523215976Sjmallett } s; 5524215976Sjmallett struct cvmx_npei_msi_enb2_s cn52xx; 5525215976Sjmallett struct cvmx_npei_msi_enb2_s cn52xxp1; 5526215976Sjmallett struct cvmx_npei_msi_enb2_s cn56xx; 5527215976Sjmallett struct cvmx_npei_msi_enb2_s cn56xxp1; 5528215976Sjmallett}; 5529215976Sjmalletttypedef union cvmx_npei_msi_enb2 cvmx_npei_msi_enb2_t; 5530215976Sjmallett 5531215976Sjmallett/** 5532215976Sjmallett * cvmx_npei_msi_enb3 5533215976Sjmallett * 5534215976Sjmallett * NPEI_MSI_ENB3 = NPEI MSI Enable3 5535215976Sjmallett * 5536215976Sjmallett * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV3. 5537215976Sjmallett */ 5538232812Sjmallettunion cvmx_npei_msi_enb3 { 5539215976Sjmallett uint64_t u64; 5540232812Sjmallett struct cvmx_npei_msi_enb3_s { 5541232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5542215976Sjmallett uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV3. */ 5543215976Sjmallett#else 5544215976Sjmallett uint64_t enb : 64; 5545215976Sjmallett#endif 5546215976Sjmallett } s; 5547215976Sjmallett struct cvmx_npei_msi_enb3_s cn52xx; 5548215976Sjmallett struct cvmx_npei_msi_enb3_s cn52xxp1; 5549215976Sjmallett struct cvmx_npei_msi_enb3_s cn56xx; 5550215976Sjmallett struct cvmx_npei_msi_enb3_s cn56xxp1; 5551215976Sjmallett}; 5552215976Sjmalletttypedef union cvmx_npei_msi_enb3 cvmx_npei_msi_enb3_t; 5553215976Sjmallett 5554215976Sjmallett/** 5555215976Sjmallett * cvmx_npei_msi_rcv0 5556215976Sjmallett * 5557215976Sjmallett * NPEI_MSI_RCV0 = NPEI MSI Receive0 5558215976Sjmallett * 5559215976Sjmallett * Contains bits [63:0] of the 256 bits oof MSI interrupts. 5560215976Sjmallett */ 5561232812Sjmallettunion cvmx_npei_msi_rcv0 { 5562215976Sjmallett uint64_t u64; 5563232812Sjmallett struct cvmx_npei_msi_rcv0_s { 5564232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5565215976Sjmallett uint64_t intr : 64; /**< Bits 63-0 of the 256 bits of MSI interrupt. */ 5566215976Sjmallett#else 5567215976Sjmallett uint64_t intr : 64; 5568215976Sjmallett#endif 5569215976Sjmallett } s; 5570215976Sjmallett struct cvmx_npei_msi_rcv0_s cn52xx; 5571215976Sjmallett struct cvmx_npei_msi_rcv0_s cn52xxp1; 5572215976Sjmallett struct cvmx_npei_msi_rcv0_s cn56xx; 5573215976Sjmallett struct cvmx_npei_msi_rcv0_s cn56xxp1; 5574215976Sjmallett}; 5575215976Sjmalletttypedef union cvmx_npei_msi_rcv0 cvmx_npei_msi_rcv0_t; 5576215976Sjmallett 5577215976Sjmallett/** 5578215976Sjmallett * cvmx_npei_msi_rcv1 5579215976Sjmallett * 5580215976Sjmallett * NPEI_MSI_RCV1 = NPEI MSI Receive1 5581215976Sjmallett * 5582215976Sjmallett * Contains bits [127:64] of the 256 bits oof MSI interrupts. 5583215976Sjmallett */ 5584232812Sjmallettunion cvmx_npei_msi_rcv1 { 5585215976Sjmallett uint64_t u64; 5586232812Sjmallett struct cvmx_npei_msi_rcv1_s { 5587232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5588215976Sjmallett uint64_t intr : 64; /**< Bits 127-64 of the 256 bits of MSI interrupt. */ 5589215976Sjmallett#else 5590215976Sjmallett uint64_t intr : 64; 5591215976Sjmallett#endif 5592215976Sjmallett } s; 5593215976Sjmallett struct cvmx_npei_msi_rcv1_s cn52xx; 5594215976Sjmallett struct cvmx_npei_msi_rcv1_s cn52xxp1; 5595215976Sjmallett struct cvmx_npei_msi_rcv1_s cn56xx; 5596215976Sjmallett struct cvmx_npei_msi_rcv1_s cn56xxp1; 5597215976Sjmallett}; 5598215976Sjmalletttypedef union cvmx_npei_msi_rcv1 cvmx_npei_msi_rcv1_t; 5599215976Sjmallett 5600215976Sjmallett/** 5601215976Sjmallett * cvmx_npei_msi_rcv2 5602215976Sjmallett * 5603215976Sjmallett * NPEI_MSI_RCV2 = NPEI MSI Receive2 5604215976Sjmallett * 5605215976Sjmallett * Contains bits [191:128] of the 256 bits oof MSI interrupts. 5606215976Sjmallett */ 5607232812Sjmallettunion cvmx_npei_msi_rcv2 { 5608215976Sjmallett uint64_t u64; 5609232812Sjmallett struct cvmx_npei_msi_rcv2_s { 5610232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5611215976Sjmallett uint64_t intr : 64; /**< Bits 191-128 of the 256 bits of MSI interrupt. */ 5612215976Sjmallett#else 5613215976Sjmallett uint64_t intr : 64; 5614215976Sjmallett#endif 5615215976Sjmallett } s; 5616215976Sjmallett struct cvmx_npei_msi_rcv2_s cn52xx; 5617215976Sjmallett struct cvmx_npei_msi_rcv2_s cn52xxp1; 5618215976Sjmallett struct cvmx_npei_msi_rcv2_s cn56xx; 5619215976Sjmallett struct cvmx_npei_msi_rcv2_s cn56xxp1; 5620215976Sjmallett}; 5621215976Sjmalletttypedef union cvmx_npei_msi_rcv2 cvmx_npei_msi_rcv2_t; 5622215976Sjmallett 5623215976Sjmallett/** 5624215976Sjmallett * cvmx_npei_msi_rcv3 5625215976Sjmallett * 5626215976Sjmallett * NPEI_MSI_RCV3 = NPEI MSI Receive3 5627215976Sjmallett * 5628215976Sjmallett * Contains bits [255:192] of the 256 bits oof MSI interrupts. 5629215976Sjmallett */ 5630232812Sjmallettunion cvmx_npei_msi_rcv3 { 5631215976Sjmallett uint64_t u64; 5632232812Sjmallett struct cvmx_npei_msi_rcv3_s { 5633232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5634215976Sjmallett uint64_t intr : 64; /**< Bits 255-192 of the 256 bits of MSI interrupt. */ 5635215976Sjmallett#else 5636215976Sjmallett uint64_t intr : 64; 5637215976Sjmallett#endif 5638215976Sjmallett } s; 5639215976Sjmallett struct cvmx_npei_msi_rcv3_s cn52xx; 5640215976Sjmallett struct cvmx_npei_msi_rcv3_s cn52xxp1; 5641215976Sjmallett struct cvmx_npei_msi_rcv3_s cn56xx; 5642215976Sjmallett struct cvmx_npei_msi_rcv3_s cn56xxp1; 5643215976Sjmallett}; 5644215976Sjmalletttypedef union cvmx_npei_msi_rcv3 cvmx_npei_msi_rcv3_t; 5645215976Sjmallett 5646215976Sjmallett/** 5647215976Sjmallett * cvmx_npei_msi_rd_map 5648215976Sjmallett * 5649215976Sjmallett * NPEI_MSI_RD_MAP = NPEI MSI Read MAP 5650215976Sjmallett * 5651215976Sjmallett * Used to read the mapping function of the NPEI_PCIE_MSI_RCV to NPEI_MSI_RCV registers. 5652215976Sjmallett */ 5653232812Sjmallettunion cvmx_npei_msi_rd_map { 5654215976Sjmallett uint64_t u64; 5655232812Sjmallett struct cvmx_npei_msi_rd_map_s { 5656232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5657215976Sjmallett uint64_t reserved_16_63 : 48; 5658215976Sjmallett uint64_t rd_int : 8; /**< The value of the map at the location PREVIOUSLY 5659215976Sjmallett written to the MSI_INT field of this register. */ 5660215976Sjmallett uint64_t msi_int : 8; /**< Selects the value that would be received when the 5661215976Sjmallett NPEI_PCIE_MSI_RCV register is written. */ 5662215976Sjmallett#else 5663215976Sjmallett uint64_t msi_int : 8; 5664215976Sjmallett uint64_t rd_int : 8; 5665215976Sjmallett uint64_t reserved_16_63 : 48; 5666215976Sjmallett#endif 5667215976Sjmallett } s; 5668215976Sjmallett struct cvmx_npei_msi_rd_map_s cn52xx; 5669215976Sjmallett struct cvmx_npei_msi_rd_map_s cn52xxp1; 5670215976Sjmallett struct cvmx_npei_msi_rd_map_s cn56xx; 5671215976Sjmallett struct cvmx_npei_msi_rd_map_s cn56xxp1; 5672215976Sjmallett}; 5673215976Sjmalletttypedef union cvmx_npei_msi_rd_map cvmx_npei_msi_rd_map_t; 5674215976Sjmallett 5675215976Sjmallett/** 5676215976Sjmallett * cvmx_npei_msi_w1c_enb0 5677215976Sjmallett * 5678215976Sjmallett * NPEI_MSI_W1C_ENB0 = NPEI MSI Write 1 To Clear Enable0 5679215976Sjmallett * 5680215976Sjmallett * Used to clear bits in NPEI_MSI_ENB0. This is a PASS2 register. 5681215976Sjmallett */ 5682232812Sjmallettunion cvmx_npei_msi_w1c_enb0 { 5683215976Sjmallett uint64_t u64; 5684232812Sjmallett struct cvmx_npei_msi_w1c_enb0_s { 5685232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5686215976Sjmallett uint64_t clr : 64; /**< A write of '1' to a vector will clear the 5687215976Sjmallett cooresponding bit in NPEI_MSI_ENB0. 5688215976Sjmallett A read to this address will return 0. */ 5689215976Sjmallett#else 5690215976Sjmallett uint64_t clr : 64; 5691215976Sjmallett#endif 5692215976Sjmallett } s; 5693215976Sjmallett struct cvmx_npei_msi_w1c_enb0_s cn52xx; 5694215976Sjmallett struct cvmx_npei_msi_w1c_enb0_s cn56xx; 5695215976Sjmallett}; 5696215976Sjmalletttypedef union cvmx_npei_msi_w1c_enb0 cvmx_npei_msi_w1c_enb0_t; 5697215976Sjmallett 5698215976Sjmallett/** 5699215976Sjmallett * cvmx_npei_msi_w1c_enb1 5700215976Sjmallett * 5701215976Sjmallett * NPEI_MSI_W1C_ENB1 = NPEI MSI Write 1 To Clear Enable1 5702215976Sjmallett * 5703215976Sjmallett * Used to clear bits in NPEI_MSI_ENB1. This is a PASS2 register. 5704215976Sjmallett */ 5705232812Sjmallettunion cvmx_npei_msi_w1c_enb1 { 5706215976Sjmallett uint64_t u64; 5707232812Sjmallett struct cvmx_npei_msi_w1c_enb1_s { 5708232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5709215976Sjmallett uint64_t clr : 64; /**< A write of '1' to a vector will clear the 5710215976Sjmallett cooresponding bit in NPEI_MSI_ENB1. 5711215976Sjmallett A read to this address will return 0. */ 5712215976Sjmallett#else 5713215976Sjmallett uint64_t clr : 64; 5714215976Sjmallett#endif 5715215976Sjmallett } s; 5716215976Sjmallett struct cvmx_npei_msi_w1c_enb1_s cn52xx; 5717215976Sjmallett struct cvmx_npei_msi_w1c_enb1_s cn56xx; 5718215976Sjmallett}; 5719215976Sjmalletttypedef union cvmx_npei_msi_w1c_enb1 cvmx_npei_msi_w1c_enb1_t; 5720215976Sjmallett 5721215976Sjmallett/** 5722215976Sjmallett * cvmx_npei_msi_w1c_enb2 5723215976Sjmallett * 5724215976Sjmallett * NPEI_MSI_W1C_ENB2 = NPEI MSI Write 1 To Clear Enable2 5725215976Sjmallett * 5726215976Sjmallett * Used to clear bits in NPEI_MSI_ENB2. This is a PASS2 register. 5727215976Sjmallett */ 5728232812Sjmallettunion cvmx_npei_msi_w1c_enb2 { 5729215976Sjmallett uint64_t u64; 5730232812Sjmallett struct cvmx_npei_msi_w1c_enb2_s { 5731232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5732215976Sjmallett uint64_t clr : 64; /**< A write of '1' to a vector will clear the 5733215976Sjmallett cooresponding bit in NPEI_MSI_ENB2. 5734215976Sjmallett A read to this address will return 0. */ 5735215976Sjmallett#else 5736215976Sjmallett uint64_t clr : 64; 5737215976Sjmallett#endif 5738215976Sjmallett } s; 5739215976Sjmallett struct cvmx_npei_msi_w1c_enb2_s cn52xx; 5740215976Sjmallett struct cvmx_npei_msi_w1c_enb2_s cn56xx; 5741215976Sjmallett}; 5742215976Sjmalletttypedef union cvmx_npei_msi_w1c_enb2 cvmx_npei_msi_w1c_enb2_t; 5743215976Sjmallett 5744215976Sjmallett/** 5745215976Sjmallett * cvmx_npei_msi_w1c_enb3 5746215976Sjmallett * 5747215976Sjmallett * NPEI_MSI_W1C_ENB3 = NPEI MSI Write 1 To Clear Enable3 5748215976Sjmallett * 5749215976Sjmallett * Used to clear bits in NPEI_MSI_ENB3. This is a PASS2 register. 5750215976Sjmallett */ 5751232812Sjmallettunion cvmx_npei_msi_w1c_enb3 { 5752215976Sjmallett uint64_t u64; 5753232812Sjmallett struct cvmx_npei_msi_w1c_enb3_s { 5754232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5755215976Sjmallett uint64_t clr : 64; /**< A write of '1' to a vector will clear the 5756215976Sjmallett cooresponding bit in NPEI_MSI_ENB3. 5757215976Sjmallett A read to this address will return 0. */ 5758215976Sjmallett#else 5759215976Sjmallett uint64_t clr : 64; 5760215976Sjmallett#endif 5761215976Sjmallett } s; 5762215976Sjmallett struct cvmx_npei_msi_w1c_enb3_s cn52xx; 5763215976Sjmallett struct cvmx_npei_msi_w1c_enb3_s cn56xx; 5764215976Sjmallett}; 5765215976Sjmalletttypedef union cvmx_npei_msi_w1c_enb3 cvmx_npei_msi_w1c_enb3_t; 5766215976Sjmallett 5767215976Sjmallett/** 5768215976Sjmallett * cvmx_npei_msi_w1s_enb0 5769215976Sjmallett * 5770215976Sjmallett * NPEI_MSI_W1S_ENB0 = NPEI MSI Write 1 To Set Enable0 5771215976Sjmallett * 5772215976Sjmallett * Used to set bits in NPEI_MSI_ENB0. This is a PASS2 register. 5773215976Sjmallett */ 5774232812Sjmallettunion cvmx_npei_msi_w1s_enb0 { 5775215976Sjmallett uint64_t u64; 5776232812Sjmallett struct cvmx_npei_msi_w1s_enb0_s { 5777232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5778215976Sjmallett uint64_t set : 64; /**< A write of '1' to a vector will set the 5779215976Sjmallett cooresponding bit in NPEI_MSI_ENB0. 5780215976Sjmallett A read to this address will return 0. */ 5781215976Sjmallett#else 5782215976Sjmallett uint64_t set : 64; 5783215976Sjmallett#endif 5784215976Sjmallett } s; 5785215976Sjmallett struct cvmx_npei_msi_w1s_enb0_s cn52xx; 5786215976Sjmallett struct cvmx_npei_msi_w1s_enb0_s cn56xx; 5787215976Sjmallett}; 5788215976Sjmalletttypedef union cvmx_npei_msi_w1s_enb0 cvmx_npei_msi_w1s_enb0_t; 5789215976Sjmallett 5790215976Sjmallett/** 5791215976Sjmallett * cvmx_npei_msi_w1s_enb1 5792215976Sjmallett * 5793215976Sjmallett * NPEI_MSI_W1S_ENB0 = NPEI MSI Write 1 To Set Enable1 5794215976Sjmallett * 5795215976Sjmallett * Used to set bits in NPEI_MSI_ENB1. This is a PASS2 register. 5796215976Sjmallett */ 5797232812Sjmallettunion cvmx_npei_msi_w1s_enb1 { 5798215976Sjmallett uint64_t u64; 5799232812Sjmallett struct cvmx_npei_msi_w1s_enb1_s { 5800232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5801215976Sjmallett uint64_t set : 64; /**< A write of '1' to a vector will set the 5802215976Sjmallett cooresponding bit in NPEI_MSI_ENB1. 5803215976Sjmallett A read to this address will return 0. */ 5804215976Sjmallett#else 5805215976Sjmallett uint64_t set : 64; 5806215976Sjmallett#endif 5807215976Sjmallett } s; 5808215976Sjmallett struct cvmx_npei_msi_w1s_enb1_s cn52xx; 5809215976Sjmallett struct cvmx_npei_msi_w1s_enb1_s cn56xx; 5810215976Sjmallett}; 5811215976Sjmalletttypedef union cvmx_npei_msi_w1s_enb1 cvmx_npei_msi_w1s_enb1_t; 5812215976Sjmallett 5813215976Sjmallett/** 5814215976Sjmallett * cvmx_npei_msi_w1s_enb2 5815215976Sjmallett * 5816215976Sjmallett * NPEI_MSI_W1S_ENB2 = NPEI MSI Write 1 To Set Enable2 5817215976Sjmallett * 5818215976Sjmallett * Used to set bits in NPEI_MSI_ENB2. This is a PASS2 register. 5819215976Sjmallett */ 5820232812Sjmallettunion cvmx_npei_msi_w1s_enb2 { 5821215976Sjmallett uint64_t u64; 5822232812Sjmallett struct cvmx_npei_msi_w1s_enb2_s { 5823232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5824215976Sjmallett uint64_t set : 64; /**< A write of '1' to a vector will set the 5825215976Sjmallett cooresponding bit in NPEI_MSI_ENB2. 5826215976Sjmallett A read to this address will return 0. */ 5827215976Sjmallett#else 5828215976Sjmallett uint64_t set : 64; 5829215976Sjmallett#endif 5830215976Sjmallett } s; 5831215976Sjmallett struct cvmx_npei_msi_w1s_enb2_s cn52xx; 5832215976Sjmallett struct cvmx_npei_msi_w1s_enb2_s cn56xx; 5833215976Sjmallett}; 5834215976Sjmalletttypedef union cvmx_npei_msi_w1s_enb2 cvmx_npei_msi_w1s_enb2_t; 5835215976Sjmallett 5836215976Sjmallett/** 5837215976Sjmallett * cvmx_npei_msi_w1s_enb3 5838215976Sjmallett * 5839215976Sjmallett * NPEI_MSI_W1S_ENB3 = NPEI MSI Write 1 To Set Enable3 5840215976Sjmallett * 5841215976Sjmallett * Used to set bits in NPEI_MSI_ENB3. This is a PASS2 register. 5842215976Sjmallett */ 5843232812Sjmallettunion cvmx_npei_msi_w1s_enb3 { 5844215976Sjmallett uint64_t u64; 5845232812Sjmallett struct cvmx_npei_msi_w1s_enb3_s { 5846232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5847215976Sjmallett uint64_t set : 64; /**< A write of '1' to a vector will set the 5848215976Sjmallett cooresponding bit in NPEI_MSI_ENB3. 5849215976Sjmallett A read to this address will return 0. */ 5850215976Sjmallett#else 5851215976Sjmallett uint64_t set : 64; 5852215976Sjmallett#endif 5853215976Sjmallett } s; 5854215976Sjmallett struct cvmx_npei_msi_w1s_enb3_s cn52xx; 5855215976Sjmallett struct cvmx_npei_msi_w1s_enb3_s cn56xx; 5856215976Sjmallett}; 5857215976Sjmalletttypedef union cvmx_npei_msi_w1s_enb3 cvmx_npei_msi_w1s_enb3_t; 5858215976Sjmallett 5859215976Sjmallett/** 5860215976Sjmallett * cvmx_npei_msi_wr_map 5861215976Sjmallett * 5862215976Sjmallett * NPEI_MSI_WR_MAP = NPEI MSI Write MAP 5863215976Sjmallett * 5864215976Sjmallett * Used to write the mapping function of the NPEI_PCIE_MSI_RCV to NPEI_MSI_RCV registers. 5865215976Sjmallett */ 5866232812Sjmallettunion cvmx_npei_msi_wr_map { 5867215976Sjmallett uint64_t u64; 5868232812Sjmallett struct cvmx_npei_msi_wr_map_s { 5869232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5870215976Sjmallett uint64_t reserved_16_63 : 48; 5871215976Sjmallett uint64_t ciu_int : 8; /**< Selects which bit in the NPEI_MSI_RCV# (0-255) 5872215976Sjmallett will be set when the value specified in the 5873215976Sjmallett MSI_INT of this register is recevied during a 5874215976Sjmallett write to the NPEI_PCIE_MSI_RCV register. */ 5875215976Sjmallett uint64_t msi_int : 8; /**< Selects the value that would be received when the 5876215976Sjmallett NPEI_PCIE_MSI_RCV register is written. */ 5877215976Sjmallett#else 5878215976Sjmallett uint64_t msi_int : 8; 5879215976Sjmallett uint64_t ciu_int : 8; 5880215976Sjmallett uint64_t reserved_16_63 : 48; 5881215976Sjmallett#endif 5882215976Sjmallett } s; 5883215976Sjmallett struct cvmx_npei_msi_wr_map_s cn52xx; 5884215976Sjmallett struct cvmx_npei_msi_wr_map_s cn52xxp1; 5885215976Sjmallett struct cvmx_npei_msi_wr_map_s cn56xx; 5886215976Sjmallett struct cvmx_npei_msi_wr_map_s cn56xxp1; 5887215976Sjmallett}; 5888215976Sjmalletttypedef union cvmx_npei_msi_wr_map cvmx_npei_msi_wr_map_t; 5889215976Sjmallett 5890215976Sjmallett/** 5891215976Sjmallett * cvmx_npei_pcie_credit_cnt 5892215976Sjmallett * 5893215976Sjmallett * NPEI_PCIE_CREDIT_CNT = NPEI PCIE Credit Count 5894215976Sjmallett * 5895215976Sjmallett * Contains the number of credits for the pcie port FIFOs used by the NPEI. This value needs to be set BEFORE PCIe traffic 5896215976Sjmallett * flow from NPEI to PCIE Ports starts. A write to this register will cause the credit counts in the NPEI for the two 5897215976Sjmallett * PCIE ports to be reset to the value in this register. 5898215976Sjmallett */ 5899232812Sjmallettunion cvmx_npei_pcie_credit_cnt { 5900215976Sjmallett uint64_t u64; 5901232812Sjmallett struct cvmx_npei_pcie_credit_cnt_s { 5902232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5903215976Sjmallett uint64_t reserved_48_63 : 16; 5904215976Sjmallett uint64_t p1_ccnt : 8; /**< Port1 C-TLP FIFO Credits. 5905215976Sjmallett Legal values are 0x25 to 0x80. */ 5906215976Sjmallett uint64_t p1_ncnt : 8; /**< Port1 N-TLP FIFO Credits. 5907215976Sjmallett Legal values are 0x5 to 0x10. */ 5908215976Sjmallett uint64_t p1_pcnt : 8; /**< Port1 P-TLP FIFO Credits. 5909215976Sjmallett Legal values are 0x25 to 0x80. */ 5910215976Sjmallett uint64_t p0_ccnt : 8; /**< Port0 C-TLP FIFO Credits. 5911215976Sjmallett Legal values are 0x25 to 0x80. */ 5912215976Sjmallett uint64_t p0_ncnt : 8; /**< Port0 N-TLP FIFO Credits. 5913215976Sjmallett Legal values are 0x5 to 0x10. */ 5914215976Sjmallett uint64_t p0_pcnt : 8; /**< Port0 P-TLP FIFO Credits. 5915215976Sjmallett Legal values are 0x25 to 0x80. */ 5916215976Sjmallett#else 5917215976Sjmallett uint64_t p0_pcnt : 8; 5918215976Sjmallett uint64_t p0_ncnt : 8; 5919215976Sjmallett uint64_t p0_ccnt : 8; 5920215976Sjmallett uint64_t p1_pcnt : 8; 5921215976Sjmallett uint64_t p1_ncnt : 8; 5922215976Sjmallett uint64_t p1_ccnt : 8; 5923215976Sjmallett uint64_t reserved_48_63 : 16; 5924215976Sjmallett#endif 5925215976Sjmallett } s; 5926215976Sjmallett struct cvmx_npei_pcie_credit_cnt_s cn52xx; 5927215976Sjmallett struct cvmx_npei_pcie_credit_cnt_s cn56xx; 5928215976Sjmallett}; 5929215976Sjmalletttypedef union cvmx_npei_pcie_credit_cnt cvmx_npei_pcie_credit_cnt_t; 5930215976Sjmallett 5931215976Sjmallett/** 5932215976Sjmallett * cvmx_npei_pcie_msi_rcv 5933215976Sjmallett * 5934215976Sjmallett * NPEI_PCIE_MSI_RCV = NPEI PCIe MSI Receive 5935215976Sjmallett * 5936215976Sjmallett * Register where MSI writes are directed from the PCIe. 5937215976Sjmallett */ 5938232812Sjmallettunion cvmx_npei_pcie_msi_rcv { 5939215976Sjmallett uint64_t u64; 5940232812Sjmallett struct cvmx_npei_pcie_msi_rcv_s { 5941232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5942215976Sjmallett uint64_t reserved_8_63 : 56; 5943215976Sjmallett uint64_t intr : 8; /**< A write to this register will result in a bit in 5944215976Sjmallett one of the NPEI_MSI_RCV# registers being set. 5945215976Sjmallett Which bit is set is dependent on the previously 5946215976Sjmallett written using the NPEI_MSI_WR_MAP register or if 5947215976Sjmallett not previously written the reset value of the MAP. */ 5948215976Sjmallett#else 5949215976Sjmallett uint64_t intr : 8; 5950215976Sjmallett uint64_t reserved_8_63 : 56; 5951215976Sjmallett#endif 5952215976Sjmallett } s; 5953215976Sjmallett struct cvmx_npei_pcie_msi_rcv_s cn52xx; 5954215976Sjmallett struct cvmx_npei_pcie_msi_rcv_s cn52xxp1; 5955215976Sjmallett struct cvmx_npei_pcie_msi_rcv_s cn56xx; 5956215976Sjmallett struct cvmx_npei_pcie_msi_rcv_s cn56xxp1; 5957215976Sjmallett}; 5958215976Sjmalletttypedef union cvmx_npei_pcie_msi_rcv cvmx_npei_pcie_msi_rcv_t; 5959215976Sjmallett 5960215976Sjmallett/** 5961215976Sjmallett * cvmx_npei_pcie_msi_rcv_b1 5962215976Sjmallett * 5963215976Sjmallett * NPEI_PCIE_MSI_RCV_B1 = NPEI PCIe MSI Receive Byte 1 5964215976Sjmallett * 5965215976Sjmallett * Register where MSI writes are directed from the PCIe. 5966215976Sjmallett */ 5967232812Sjmallettunion cvmx_npei_pcie_msi_rcv_b1 { 5968215976Sjmallett uint64_t u64; 5969232812Sjmallett struct cvmx_npei_pcie_msi_rcv_b1_s { 5970232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5971215976Sjmallett uint64_t reserved_16_63 : 48; 5972215976Sjmallett uint64_t intr : 8; /**< A write to this register will result in a bit in 5973215976Sjmallett one of the NPEI_MSI_RCV# registers being set. 5974215976Sjmallett Which bit is set is dependent on the previously 5975215976Sjmallett written using the NPEI_MSI_WR_MAP register or if 5976215976Sjmallett not previously written the reset value of the MAP. */ 5977215976Sjmallett uint64_t reserved_0_7 : 8; 5978215976Sjmallett#else 5979215976Sjmallett uint64_t reserved_0_7 : 8; 5980215976Sjmallett uint64_t intr : 8; 5981215976Sjmallett uint64_t reserved_16_63 : 48; 5982215976Sjmallett#endif 5983215976Sjmallett } s; 5984215976Sjmallett struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx; 5985215976Sjmallett struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1; 5986215976Sjmallett struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx; 5987215976Sjmallett struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1; 5988215976Sjmallett}; 5989215976Sjmalletttypedef union cvmx_npei_pcie_msi_rcv_b1 cvmx_npei_pcie_msi_rcv_b1_t; 5990215976Sjmallett 5991215976Sjmallett/** 5992215976Sjmallett * cvmx_npei_pcie_msi_rcv_b2 5993215976Sjmallett * 5994215976Sjmallett * NPEI_PCIE_MSI_RCV_B2 = NPEI PCIe MSI Receive Byte 2 5995215976Sjmallett * 5996215976Sjmallett * Register where MSI writes are directed from the PCIe. 5997215976Sjmallett */ 5998232812Sjmallettunion cvmx_npei_pcie_msi_rcv_b2 { 5999215976Sjmallett uint64_t u64; 6000232812Sjmallett struct cvmx_npei_pcie_msi_rcv_b2_s { 6001232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6002215976Sjmallett uint64_t reserved_24_63 : 40; 6003215976Sjmallett uint64_t intr : 8; /**< A write to this register will result in a bit in 6004215976Sjmallett one of the NPEI_MSI_RCV# registers being set. 6005215976Sjmallett Which bit is set is dependent on the previously 6006215976Sjmallett written using the NPEI_MSI_WR_MAP register or if 6007215976Sjmallett not previously written the reset value of the MAP. */ 6008215976Sjmallett uint64_t reserved_0_15 : 16; 6009215976Sjmallett#else 6010215976Sjmallett uint64_t reserved_0_15 : 16; 6011215976Sjmallett uint64_t intr : 8; 6012215976Sjmallett uint64_t reserved_24_63 : 40; 6013215976Sjmallett#endif 6014215976Sjmallett } s; 6015215976Sjmallett struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx; 6016215976Sjmallett struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1; 6017215976Sjmallett struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx; 6018215976Sjmallett struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1; 6019215976Sjmallett}; 6020215976Sjmalletttypedef union cvmx_npei_pcie_msi_rcv_b2 cvmx_npei_pcie_msi_rcv_b2_t; 6021215976Sjmallett 6022215976Sjmallett/** 6023215976Sjmallett * cvmx_npei_pcie_msi_rcv_b3 6024215976Sjmallett * 6025215976Sjmallett * NPEI_PCIE_MSI_RCV_B3 = NPEI PCIe MSI Receive Byte 3 6026215976Sjmallett * 6027215976Sjmallett * Register where MSI writes are directed from the PCIe. 6028215976Sjmallett */ 6029232812Sjmallettunion cvmx_npei_pcie_msi_rcv_b3 { 6030215976Sjmallett uint64_t u64; 6031232812Sjmallett struct cvmx_npei_pcie_msi_rcv_b3_s { 6032232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6033215976Sjmallett uint64_t reserved_32_63 : 32; 6034215976Sjmallett uint64_t intr : 8; /**< A write to this register will result in a bit in 6035215976Sjmallett one of the NPEI_MSI_RCV# registers being set. 6036215976Sjmallett Which bit is set is dependent on the previously 6037215976Sjmallett written using the NPEI_MSI_WR_MAP register or if 6038215976Sjmallett not previously written the reset value of the MAP. */ 6039215976Sjmallett uint64_t reserved_0_23 : 24; 6040215976Sjmallett#else 6041215976Sjmallett uint64_t reserved_0_23 : 24; 6042215976Sjmallett uint64_t intr : 8; 6043215976Sjmallett uint64_t reserved_32_63 : 32; 6044215976Sjmallett#endif 6045215976Sjmallett } s; 6046215976Sjmallett struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx; 6047215976Sjmallett struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1; 6048215976Sjmallett struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx; 6049215976Sjmallett struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1; 6050215976Sjmallett}; 6051215976Sjmalletttypedef union cvmx_npei_pcie_msi_rcv_b3 cvmx_npei_pcie_msi_rcv_b3_t; 6052215976Sjmallett 6053215976Sjmallett/** 6054215976Sjmallett * cvmx_npei_pkt#_cnts 6055215976Sjmallett * 6056215976Sjmallett * NPEI_PKT[0..31]_CNTS = NPEI Packet ring# Counts 6057215976Sjmallett * 6058215976Sjmallett * The counters for output rings. 6059215976Sjmallett */ 6060232812Sjmallettunion cvmx_npei_pktx_cnts { 6061215976Sjmallett uint64_t u64; 6062232812Sjmallett struct cvmx_npei_pktx_cnts_s { 6063232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6064215976Sjmallett uint64_t reserved_54_63 : 10; 6065215976Sjmallett uint64_t timer : 22; /**< Timer incremented every 1024 core clocks 6066215976Sjmallett when NPEI_PKTS#_CNTS[CNT] is non zero. Field 6067215976Sjmallett cleared when NPEI_PKTS#_CNTS[CNT] goes to 0. 6068215976Sjmallett Field is also cleared when NPEI_PKT_TIME_INT is 6069215976Sjmallett cleared. 6070215976Sjmallett The first increment of this count can occur 6071215976Sjmallett between 0 to 1023 core clocks. */ 6072215976Sjmallett uint64_t cnt : 32; /**< ring counter. This field is incremented as 6073215976Sjmallett packets are sent out and decremented in response to 6074215976Sjmallett writes to this field. 6075215976Sjmallett When NPEI_PKT_OUT_BMODE is '0' a value of 1 is 6076215976Sjmallett added to the register for each packet, when '1' 6077215976Sjmallett and the info-pointer is NOT used the length of the 6078215976Sjmallett packet plus 8 is added, when '1' and info-pointer 6079215976Sjmallett mode IS used the packet length is added to this 6080215976Sjmallett field. */ 6081215976Sjmallett#else 6082215976Sjmallett uint64_t cnt : 32; 6083215976Sjmallett uint64_t timer : 22; 6084215976Sjmallett uint64_t reserved_54_63 : 10; 6085215976Sjmallett#endif 6086215976Sjmallett } s; 6087215976Sjmallett struct cvmx_npei_pktx_cnts_s cn52xx; 6088215976Sjmallett struct cvmx_npei_pktx_cnts_s cn56xx; 6089215976Sjmallett}; 6090215976Sjmalletttypedef union cvmx_npei_pktx_cnts cvmx_npei_pktx_cnts_t; 6091215976Sjmallett 6092215976Sjmallett/** 6093215976Sjmallett * cvmx_npei_pkt#_in_bp 6094215976Sjmallett * 6095215976Sjmallett * NPEI_PKT[0..31]_IN_BP = NPEI Packet ring# Input Backpressure 6096215976Sjmallett * 6097215976Sjmallett * The counters and thresholds for input packets to apply backpressure to processing of the packets. 6098215976Sjmallett */ 6099232812Sjmallettunion cvmx_npei_pktx_in_bp { 6100215976Sjmallett uint64_t u64; 6101232812Sjmallett struct cvmx_npei_pktx_in_bp_s { 6102232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6103215976Sjmallett uint64_t wmark : 32; /**< When CNT is greater than this threshold no more 6104215976Sjmallett packets will be processed for this ring. 6105215976Sjmallett When writing this field of the NPEI_PKT#_IN_BP 6106215976Sjmallett register, use a 4-byte write so as to not write 6107215976Sjmallett any other field of this register. */ 6108215976Sjmallett uint64_t cnt : 32; /**< ring counter. This field is incremented by one 6109215976Sjmallett whenever OCTEON receives, buffers, and creates a 6110215976Sjmallett work queue entry for a packet that arrives by the 6111215976Sjmallett cooresponding input ring. A write to this field 6112215976Sjmallett will be subtracted from the field value. 6113215976Sjmallett When writing this field of the NPEI_PKT#_IN_BP 6114215976Sjmallett register, use a 4-byte write so as to not write 6115215976Sjmallett any other field of this register. */ 6116215976Sjmallett#else 6117215976Sjmallett uint64_t cnt : 32; 6118215976Sjmallett uint64_t wmark : 32; 6119215976Sjmallett#endif 6120215976Sjmallett } s; 6121215976Sjmallett struct cvmx_npei_pktx_in_bp_s cn52xx; 6122215976Sjmallett struct cvmx_npei_pktx_in_bp_s cn56xx; 6123215976Sjmallett}; 6124215976Sjmalletttypedef union cvmx_npei_pktx_in_bp cvmx_npei_pktx_in_bp_t; 6125215976Sjmallett 6126215976Sjmallett/** 6127215976Sjmallett * cvmx_npei_pkt#_instr_baddr 6128215976Sjmallett * 6129215976Sjmallett * NPEI_PKT[0..31]_INSTR_BADDR = NPEI Packet ring# Instruction Base Address 6130215976Sjmallett * 6131215976Sjmallett * Start of Instruction for input packets. 6132215976Sjmallett */ 6133232812Sjmallettunion cvmx_npei_pktx_instr_baddr { 6134215976Sjmallett uint64_t u64; 6135232812Sjmallett struct cvmx_npei_pktx_instr_baddr_s { 6136232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6137215976Sjmallett uint64_t addr : 61; /**< Base address for Instructions. */ 6138215976Sjmallett uint64_t reserved_0_2 : 3; 6139215976Sjmallett#else 6140215976Sjmallett uint64_t reserved_0_2 : 3; 6141215976Sjmallett uint64_t addr : 61; 6142215976Sjmallett#endif 6143215976Sjmallett } s; 6144215976Sjmallett struct cvmx_npei_pktx_instr_baddr_s cn52xx; 6145215976Sjmallett struct cvmx_npei_pktx_instr_baddr_s cn56xx; 6146215976Sjmallett}; 6147215976Sjmalletttypedef union cvmx_npei_pktx_instr_baddr cvmx_npei_pktx_instr_baddr_t; 6148215976Sjmallett 6149215976Sjmallett/** 6150215976Sjmallett * cvmx_npei_pkt#_instr_baoff_dbell 6151215976Sjmallett * 6152215976Sjmallett * NPEI_PKT[0..31]_INSTR_BAOFF_DBELL = NPEI Packet ring# Instruction Base Address Offset and Doorbell 6153215976Sjmallett * 6154215976Sjmallett * The doorbell and base address offset for next read. 6155215976Sjmallett */ 6156232812Sjmallettunion cvmx_npei_pktx_instr_baoff_dbell { 6157215976Sjmallett uint64_t u64; 6158232812Sjmallett struct cvmx_npei_pktx_instr_baoff_dbell_s { 6159232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6160215976Sjmallett uint64_t aoff : 32; /**< The offset from the NPEI_PKT[0..31]_INSTR_BADDR 6161215976Sjmallett where the next instruction will be read. */ 6162215976Sjmallett uint64_t dbell : 32; /**< Instruction doorbell count. Writes to this field 6163215976Sjmallett will increment the value here. Reads will return 6164215976Sjmallett present value. A write of 0xffffffff will set the 6165215976Sjmallett DBELL and AOFF fields to '0'. */ 6166215976Sjmallett#else 6167215976Sjmallett uint64_t dbell : 32; 6168215976Sjmallett uint64_t aoff : 32; 6169215976Sjmallett#endif 6170215976Sjmallett } s; 6171215976Sjmallett struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx; 6172215976Sjmallett struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx; 6173215976Sjmallett}; 6174215976Sjmalletttypedef union cvmx_npei_pktx_instr_baoff_dbell cvmx_npei_pktx_instr_baoff_dbell_t; 6175215976Sjmallett 6176215976Sjmallett/** 6177215976Sjmallett * cvmx_npei_pkt#_instr_fifo_rsize 6178215976Sjmallett * 6179215976Sjmallett * NPEI_PKT[0..31]_INSTR_FIFO_RSIZE = NPEI Packet ring# Instruction FIFO and Ring Size. 6180215976Sjmallett * 6181215976Sjmallett * Fifo field and ring size for Instructions. 6182215976Sjmallett */ 6183232812Sjmallettunion cvmx_npei_pktx_instr_fifo_rsize { 6184215976Sjmallett uint64_t u64; 6185232812Sjmallett struct cvmx_npei_pktx_instr_fifo_rsize_s { 6186232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6187215976Sjmallett uint64_t max : 9; /**< Max Fifo Size. */ 6188215976Sjmallett uint64_t rrp : 9; /**< Fifo read pointer. */ 6189215976Sjmallett uint64_t wrp : 9; /**< Fifo write pointer. */ 6190215976Sjmallett uint64_t fcnt : 5; /**< Fifo count. */ 6191215976Sjmallett uint64_t rsize : 32; /**< Instruction ring size. */ 6192215976Sjmallett#else 6193215976Sjmallett uint64_t rsize : 32; 6194215976Sjmallett uint64_t fcnt : 5; 6195215976Sjmallett uint64_t wrp : 9; 6196215976Sjmallett uint64_t rrp : 9; 6197215976Sjmallett uint64_t max : 9; 6198215976Sjmallett#endif 6199215976Sjmallett } s; 6200215976Sjmallett struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx; 6201215976Sjmallett struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx; 6202215976Sjmallett}; 6203215976Sjmalletttypedef union cvmx_npei_pktx_instr_fifo_rsize cvmx_npei_pktx_instr_fifo_rsize_t; 6204215976Sjmallett 6205215976Sjmallett/** 6206215976Sjmallett * cvmx_npei_pkt#_instr_header 6207215976Sjmallett * 6208215976Sjmallett * NPEI_PKT[0..31]_INSTR_HEADER = NPEI Packet ring# Instruction Header. 6209215976Sjmallett * 6210215976Sjmallett * VAlues used to build input packet header. 6211215976Sjmallett */ 6212232812Sjmallettunion cvmx_npei_pktx_instr_header { 6213215976Sjmallett uint64_t u64; 6214232812Sjmallett struct cvmx_npei_pktx_instr_header_s { 6215232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6216215976Sjmallett uint64_t reserved_44_63 : 20; 6217215976Sjmallett uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */ 6218215976Sjmallett uint64_t reserved_38_42 : 5; 6219215976Sjmallett uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */ 6220215976Sjmallett uint64_t reserved_35_35 : 1; 6221215976Sjmallett uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */ 6222215976Sjmallett uint64_t reserved_22_27 : 6; 6223215976Sjmallett uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent 6224215976Sjmallett as part of the packet data, regardless of the 6225215976Sjmallett value of bit [63] of the instruction header. 6226215976Sjmallett USE_IHDR must be set whenever PBP is set. */ 6227215976Sjmallett uint64_t reserved_16_20 : 5; 6228215976Sjmallett uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet 6229215976Sjmallett is not raw and PBP is not set. */ 6230215976Sjmallett uint64_t reserved_13_13 : 1; 6231215976Sjmallett uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet 6232215976Sjmallett is not raw and PBP is not set. */ 6233215976Sjmallett uint64_t reserved_0_5 : 6; 6234215976Sjmallett#else 6235215976Sjmallett uint64_t reserved_0_5 : 6; 6236215976Sjmallett uint64_t skp_len : 7; 6237215976Sjmallett uint64_t reserved_13_13 : 1; 6238215976Sjmallett uint64_t par_mode : 2; 6239215976Sjmallett uint64_t reserved_16_20 : 5; 6240215976Sjmallett uint64_t use_ihdr : 1; 6241215976Sjmallett uint64_t reserved_22_27 : 6; 6242215976Sjmallett uint64_t rskp_len : 7; 6243215976Sjmallett uint64_t reserved_35_35 : 1; 6244215976Sjmallett uint64_t rparmode : 2; 6245215976Sjmallett uint64_t reserved_38_42 : 5; 6246215976Sjmallett uint64_t pbp : 1; 6247215976Sjmallett uint64_t reserved_44_63 : 20; 6248215976Sjmallett#endif 6249215976Sjmallett } s; 6250215976Sjmallett struct cvmx_npei_pktx_instr_header_s cn52xx; 6251215976Sjmallett struct cvmx_npei_pktx_instr_header_s cn56xx; 6252215976Sjmallett}; 6253215976Sjmalletttypedef union cvmx_npei_pktx_instr_header cvmx_npei_pktx_instr_header_t; 6254215976Sjmallett 6255215976Sjmallett/** 6256215976Sjmallett * cvmx_npei_pkt#_slist_baddr 6257215976Sjmallett * 6258215976Sjmallett * NPEI_PKT[0..31]_SLIST_BADDR = NPEI Packet ring# Scatter List Base Address 6259215976Sjmallett * 6260215976Sjmallett * Start of Scatter List for output packet pointers - MUST be 16 byte alligned 6261215976Sjmallett */ 6262232812Sjmallettunion cvmx_npei_pktx_slist_baddr { 6263215976Sjmallett uint64_t u64; 6264232812Sjmallett struct cvmx_npei_pktx_slist_baddr_s { 6265232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6266215976Sjmallett uint64_t addr : 60; /**< Base address for scatter list pointers. */ 6267215976Sjmallett uint64_t reserved_0_3 : 4; 6268215976Sjmallett#else 6269215976Sjmallett uint64_t reserved_0_3 : 4; 6270215976Sjmallett uint64_t addr : 60; 6271215976Sjmallett#endif 6272215976Sjmallett } s; 6273215976Sjmallett struct cvmx_npei_pktx_slist_baddr_s cn52xx; 6274215976Sjmallett struct cvmx_npei_pktx_slist_baddr_s cn56xx; 6275215976Sjmallett}; 6276215976Sjmalletttypedef union cvmx_npei_pktx_slist_baddr cvmx_npei_pktx_slist_baddr_t; 6277215976Sjmallett 6278215976Sjmallett/** 6279215976Sjmallett * cvmx_npei_pkt#_slist_baoff_dbell 6280215976Sjmallett * 6281215976Sjmallett * NPEI_PKT[0..31]_SLIST_BAOFF_DBELL = NPEI Packet ring# Scatter List Base Address Offset and Doorbell 6282215976Sjmallett * 6283215976Sjmallett * The doorbell and base address offset for next read. 6284215976Sjmallett */ 6285232812Sjmallettunion cvmx_npei_pktx_slist_baoff_dbell { 6286215976Sjmallett uint64_t u64; 6287232812Sjmallett struct cvmx_npei_pktx_slist_baoff_dbell_s { 6288232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6289215976Sjmallett uint64_t aoff : 32; /**< The offset from the NPEI_PKT[0..31]_SLIST_BADDR 6290215976Sjmallett where the next SList pointer will be read. 6291215976Sjmallett A write of 0xFFFFFFFF to the DBELL field will 6292215976Sjmallett clear DBELL and AOFF */ 6293215976Sjmallett uint64_t dbell : 32; /**< Scatter list doorbell count. Writes to this field 6294215976Sjmallett will increment the value here. Reads will return 6295215976Sjmallett present value. The value of this field is 6296215976Sjmallett decremented as read operations are ISSUED for 6297215976Sjmallett scatter pointers. 6298215976Sjmallett A write of 0xFFFFFFFF will clear DBELL and AOFF */ 6299215976Sjmallett#else 6300215976Sjmallett uint64_t dbell : 32; 6301215976Sjmallett uint64_t aoff : 32; 6302215976Sjmallett#endif 6303215976Sjmallett } s; 6304215976Sjmallett struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx; 6305215976Sjmallett struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx; 6306215976Sjmallett}; 6307215976Sjmalletttypedef union cvmx_npei_pktx_slist_baoff_dbell cvmx_npei_pktx_slist_baoff_dbell_t; 6308215976Sjmallett 6309215976Sjmallett/** 6310215976Sjmallett * cvmx_npei_pkt#_slist_fifo_rsize 6311215976Sjmallett * 6312215976Sjmallett * NPEI_PKT[0..31]_SLIST_FIFO_RSIZE = NPEI Packet ring# Scatter List FIFO and Ring Size. 6313215976Sjmallett * 6314215976Sjmallett * The number of scatter pointer pairs in the scatter list. 6315215976Sjmallett */ 6316232812Sjmallettunion cvmx_npei_pktx_slist_fifo_rsize { 6317215976Sjmallett uint64_t u64; 6318232812Sjmallett struct cvmx_npei_pktx_slist_fifo_rsize_s { 6319232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6320215976Sjmallett uint64_t reserved_32_63 : 32; 6321215976Sjmallett uint64_t rsize : 32; /**< The number of scatter pointer pairs contained in 6322215976Sjmallett the scatter list ring. */ 6323215976Sjmallett#else 6324215976Sjmallett uint64_t rsize : 32; 6325215976Sjmallett uint64_t reserved_32_63 : 32; 6326215976Sjmallett#endif 6327215976Sjmallett } s; 6328215976Sjmallett struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx; 6329215976Sjmallett struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx; 6330215976Sjmallett}; 6331215976Sjmalletttypedef union cvmx_npei_pktx_slist_fifo_rsize cvmx_npei_pktx_slist_fifo_rsize_t; 6332215976Sjmallett 6333215976Sjmallett/** 6334215976Sjmallett * cvmx_npei_pkt_cnt_int 6335215976Sjmallett * 6336215976Sjmallett * NPEI_PKT_CNT_INT = NPI Packet Counter Interrupt 6337215976Sjmallett * 6338215976Sjmallett * The packets rings that are interrupting because of Packet Counters. 6339215976Sjmallett */ 6340232812Sjmallettunion cvmx_npei_pkt_cnt_int { 6341215976Sjmallett uint64_t u64; 6342232812Sjmallett struct cvmx_npei_pkt_cnt_int_s { 6343232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6344215976Sjmallett uint64_t reserved_32_63 : 32; 6345215976Sjmallett uint64_t port : 32; /**< Bit vector cooresponding to ring number is set when 6346215976Sjmallett NPEI_PKT#_CNTS[CNT] is greater 6347215976Sjmallett than NPEI_PKT_INT_LEVELS[CNT]. */ 6348215976Sjmallett#else 6349215976Sjmallett uint64_t port : 32; 6350215976Sjmallett uint64_t reserved_32_63 : 32; 6351215976Sjmallett#endif 6352215976Sjmallett } s; 6353215976Sjmallett struct cvmx_npei_pkt_cnt_int_s cn52xx; 6354215976Sjmallett struct cvmx_npei_pkt_cnt_int_s cn56xx; 6355215976Sjmallett}; 6356215976Sjmalletttypedef union cvmx_npei_pkt_cnt_int cvmx_npei_pkt_cnt_int_t; 6357215976Sjmallett 6358215976Sjmallett/** 6359215976Sjmallett * cvmx_npei_pkt_cnt_int_enb 6360215976Sjmallett * 6361215976Sjmallett * NPEI_PKT_CNT_INT_ENB = NPI Packet Counter Interrupt Enable 6362215976Sjmallett * 6363215976Sjmallett * Enable for the packets rings that are interrupting because of Packet Counters. 6364215976Sjmallett */ 6365232812Sjmallettunion cvmx_npei_pkt_cnt_int_enb { 6366215976Sjmallett uint64_t u64; 6367232812Sjmallett struct cvmx_npei_pkt_cnt_int_enb_s { 6368232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6369215976Sjmallett uint64_t reserved_32_63 : 32; 6370215976Sjmallett uint64_t port : 32; /**< Bit vector cooresponding to ring number when set 6371215976Sjmallett allows NPEI_PKT_CNT_INT to generate an interrupt. */ 6372215976Sjmallett#else 6373215976Sjmallett uint64_t port : 32; 6374215976Sjmallett uint64_t reserved_32_63 : 32; 6375215976Sjmallett#endif 6376215976Sjmallett } s; 6377215976Sjmallett struct cvmx_npei_pkt_cnt_int_enb_s cn52xx; 6378215976Sjmallett struct cvmx_npei_pkt_cnt_int_enb_s cn56xx; 6379215976Sjmallett}; 6380215976Sjmalletttypedef union cvmx_npei_pkt_cnt_int_enb cvmx_npei_pkt_cnt_int_enb_t; 6381215976Sjmallett 6382215976Sjmallett/** 6383215976Sjmallett * cvmx_npei_pkt_data_out_es 6384215976Sjmallett * 6385215976Sjmallett * NPEI_PKT_DATA_OUT_ES = NPEI's Packet Data Out Endian Swap 6386215976Sjmallett * 6387215976Sjmallett * The Endian Swap for writing Data Out. 6388215976Sjmallett */ 6389232812Sjmallettunion cvmx_npei_pkt_data_out_es { 6390215976Sjmallett uint64_t u64; 6391232812Sjmallett struct cvmx_npei_pkt_data_out_es_s { 6392232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6393215976Sjmallett uint64_t es : 64; /**< The endian swap mode for Packet rings 0 through 31. 6394215976Sjmallett Two bits are used per ring (i.e. ring 0 [1:0], 6395215976Sjmallett ring 1 [3:2], ....). */ 6396215976Sjmallett#else 6397215976Sjmallett uint64_t es : 64; 6398215976Sjmallett#endif 6399215976Sjmallett } s; 6400215976Sjmallett struct cvmx_npei_pkt_data_out_es_s cn52xx; 6401215976Sjmallett struct cvmx_npei_pkt_data_out_es_s cn56xx; 6402215976Sjmallett}; 6403215976Sjmalletttypedef union cvmx_npei_pkt_data_out_es cvmx_npei_pkt_data_out_es_t; 6404215976Sjmallett 6405215976Sjmallett/** 6406215976Sjmallett * cvmx_npei_pkt_data_out_ns 6407215976Sjmallett * 6408215976Sjmallett * NPEI_PKT_DATA_OUT_NS = NPEI's Packet Data Out No Snoop 6409215976Sjmallett * 6410215976Sjmallett * The NS field for the TLP when writing packet data. 6411215976Sjmallett */ 6412232812Sjmallettunion cvmx_npei_pkt_data_out_ns { 6413215976Sjmallett uint64_t u64; 6414232812Sjmallett struct cvmx_npei_pkt_data_out_ns_s { 6415232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6416215976Sjmallett uint64_t reserved_32_63 : 32; 6417215976Sjmallett uint64_t nsr : 32; /**< When asserted '1' the vector bit cooresponding 6418215976Sjmallett to the Packet-ring will enable NS in TLP header. */ 6419215976Sjmallett#else 6420215976Sjmallett uint64_t nsr : 32; 6421215976Sjmallett uint64_t reserved_32_63 : 32; 6422215976Sjmallett#endif 6423215976Sjmallett } s; 6424215976Sjmallett struct cvmx_npei_pkt_data_out_ns_s cn52xx; 6425215976Sjmallett struct cvmx_npei_pkt_data_out_ns_s cn56xx; 6426215976Sjmallett}; 6427215976Sjmalletttypedef union cvmx_npei_pkt_data_out_ns cvmx_npei_pkt_data_out_ns_t; 6428215976Sjmallett 6429215976Sjmallett/** 6430215976Sjmallett * cvmx_npei_pkt_data_out_ror 6431215976Sjmallett * 6432215976Sjmallett * NPEI_PKT_DATA_OUT_ROR = NPEI's Packet Data Out Relaxed Ordering 6433215976Sjmallett * 6434215976Sjmallett * The ROR field for the TLP when writing Packet Data. 6435215976Sjmallett */ 6436232812Sjmallettunion cvmx_npei_pkt_data_out_ror { 6437215976Sjmallett uint64_t u64; 6438232812Sjmallett struct cvmx_npei_pkt_data_out_ror_s { 6439232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6440215976Sjmallett uint64_t reserved_32_63 : 32; 6441215976Sjmallett uint64_t ror : 32; /**< When asserted '1' the vector bit cooresponding 6442215976Sjmallett to the Packet-ring will enable ROR in TLP header. */ 6443215976Sjmallett#else 6444215976Sjmallett uint64_t ror : 32; 6445215976Sjmallett uint64_t reserved_32_63 : 32; 6446215976Sjmallett#endif 6447215976Sjmallett } s; 6448215976Sjmallett struct cvmx_npei_pkt_data_out_ror_s cn52xx; 6449215976Sjmallett struct cvmx_npei_pkt_data_out_ror_s cn56xx; 6450215976Sjmallett}; 6451215976Sjmalletttypedef union cvmx_npei_pkt_data_out_ror cvmx_npei_pkt_data_out_ror_t; 6452215976Sjmallett 6453215976Sjmallett/** 6454215976Sjmallett * cvmx_npei_pkt_dpaddr 6455215976Sjmallett * 6456215976Sjmallett * NPEI_PKT_DPADDR = NPEI's Packet Data Pointer Addr 6457215976Sjmallett * 6458215976Sjmallett * Used to detemine address and attributes for packet data writes. 6459215976Sjmallett */ 6460232812Sjmallettunion cvmx_npei_pkt_dpaddr { 6461215976Sjmallett uint64_t u64; 6462232812Sjmallett struct cvmx_npei_pkt_dpaddr_s { 6463232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6464215976Sjmallett uint64_t reserved_32_63 : 32; 6465215976Sjmallett uint64_t dptr : 32; /**< When asserted '1' the vector bit cooresponding 6466215976Sjmallett to the Packet-ring will use: 6467215976Sjmallett the address[63:60] to write packet data 6468215976Sjmallett comes from the DPTR[63:60] in the scatter-list 6469215976Sjmallett pair and the RO, NS, ES values come from the O0_ES, 6470215976Sjmallett O0_NS, O0_RO. When '0' the RO == DPTR[60], 6471215976Sjmallett NS == DPTR[61], ES == DPTR[63:62], the address the 6472215976Sjmallett packet will be written to is ADDR[63:60] == 6473215976Sjmallett O0_ES[1:0], O0_NS, O0_RO. */ 6474215976Sjmallett#else 6475215976Sjmallett uint64_t dptr : 32; 6476215976Sjmallett uint64_t reserved_32_63 : 32; 6477215976Sjmallett#endif 6478215976Sjmallett } s; 6479215976Sjmallett struct cvmx_npei_pkt_dpaddr_s cn52xx; 6480215976Sjmallett struct cvmx_npei_pkt_dpaddr_s cn56xx; 6481215976Sjmallett}; 6482215976Sjmalletttypedef union cvmx_npei_pkt_dpaddr cvmx_npei_pkt_dpaddr_t; 6483215976Sjmallett 6484215976Sjmallett/** 6485215976Sjmallett * cvmx_npei_pkt_in_bp 6486215976Sjmallett * 6487215976Sjmallett * NPEI_PKT_IN_BP = NPEI Packet Input Backpressure 6488215976Sjmallett * 6489215976Sjmallett * Which input rings have backpressure applied. 6490215976Sjmallett */ 6491232812Sjmallettunion cvmx_npei_pkt_in_bp { 6492215976Sjmallett uint64_t u64; 6493232812Sjmallett struct cvmx_npei_pkt_in_bp_s { 6494232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6495215976Sjmallett uint64_t reserved_32_63 : 32; 6496215976Sjmallett uint64_t bp : 32; /**< A packet input ring that has its count greater 6497215976Sjmallett than its WMARK will have backpressure applied. 6498215976Sjmallett Each of the 32 bits coorespond to an input ring. 6499215976Sjmallett When '1' that ring has backpressure applied an 6500215976Sjmallett will fetch no more instructions, but will process 6501215976Sjmallett any previously fetched instructions. */ 6502215976Sjmallett#else 6503215976Sjmallett uint64_t bp : 32; 6504215976Sjmallett uint64_t reserved_32_63 : 32; 6505215976Sjmallett#endif 6506215976Sjmallett } s; 6507215976Sjmallett struct cvmx_npei_pkt_in_bp_s cn52xx; 6508215976Sjmallett struct cvmx_npei_pkt_in_bp_s cn56xx; 6509215976Sjmallett}; 6510215976Sjmalletttypedef union cvmx_npei_pkt_in_bp cvmx_npei_pkt_in_bp_t; 6511215976Sjmallett 6512215976Sjmallett/** 6513215976Sjmallett * cvmx_npei_pkt_in_done#_cnts 6514215976Sjmallett * 6515215976Sjmallett * NPEI_PKT_IN_DONE[0..31]_CNTS = NPEI Instruction Done ring# Counts 6516215976Sjmallett * 6517215976Sjmallett * Counters for instructions completed on Input rings. 6518215976Sjmallett */ 6519232812Sjmallettunion cvmx_npei_pkt_in_donex_cnts { 6520215976Sjmallett uint64_t u64; 6521232812Sjmallett struct cvmx_npei_pkt_in_donex_cnts_s { 6522232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6523215976Sjmallett uint64_t reserved_32_63 : 32; 6524215976Sjmallett uint64_t cnt : 32; /**< This field is incrmented by '1' when an instruction 6525215976Sjmallett is completed. This field is incremented as the 6526215976Sjmallett last of the data is read from the PCIe. */ 6527215976Sjmallett#else 6528215976Sjmallett uint64_t cnt : 32; 6529215976Sjmallett uint64_t reserved_32_63 : 32; 6530215976Sjmallett#endif 6531215976Sjmallett } s; 6532215976Sjmallett struct cvmx_npei_pkt_in_donex_cnts_s cn52xx; 6533215976Sjmallett struct cvmx_npei_pkt_in_donex_cnts_s cn56xx; 6534215976Sjmallett}; 6535215976Sjmalletttypedef union cvmx_npei_pkt_in_donex_cnts cvmx_npei_pkt_in_donex_cnts_t; 6536215976Sjmallett 6537215976Sjmallett/** 6538215976Sjmallett * cvmx_npei_pkt_in_instr_counts 6539215976Sjmallett * 6540215976Sjmallett * NPEI_PKT_IN_INSTR_COUNTS = NPEI Packet Input Instrutction Counts 6541215976Sjmallett * 6542215976Sjmallett * Keeps track of the number of instructions read into the FIFO and Packets sent to IPD. 6543215976Sjmallett */ 6544232812Sjmallettunion cvmx_npei_pkt_in_instr_counts { 6545215976Sjmallett uint64_t u64; 6546232812Sjmallett struct cvmx_npei_pkt_in_instr_counts_s { 6547232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6548215976Sjmallett uint64_t wr_cnt : 32; /**< Shows the number of packets sent to the IPD. */ 6549215976Sjmallett uint64_t rd_cnt : 32; /**< Shows the value of instructions that have had reads 6550215976Sjmallett issued for them. 6551215976Sjmallett to the Packet-ring is in reset. */ 6552215976Sjmallett#else 6553215976Sjmallett uint64_t rd_cnt : 32; 6554215976Sjmallett uint64_t wr_cnt : 32; 6555215976Sjmallett#endif 6556215976Sjmallett } s; 6557215976Sjmallett struct cvmx_npei_pkt_in_instr_counts_s cn52xx; 6558215976Sjmallett struct cvmx_npei_pkt_in_instr_counts_s cn56xx; 6559215976Sjmallett}; 6560215976Sjmalletttypedef union cvmx_npei_pkt_in_instr_counts cvmx_npei_pkt_in_instr_counts_t; 6561215976Sjmallett 6562215976Sjmallett/** 6563215976Sjmallett * cvmx_npei_pkt_in_pcie_port 6564215976Sjmallett * 6565215976Sjmallett * NPEI_PKT_IN_PCIE_PORT = NPEI's Packet In To PCIe Port Assignment 6566215976Sjmallett * 6567215976Sjmallett * Assigns Packet Input rings to PCIe ports. 6568215976Sjmallett */ 6569232812Sjmallettunion cvmx_npei_pkt_in_pcie_port { 6570215976Sjmallett uint64_t u64; 6571232812Sjmallett struct cvmx_npei_pkt_in_pcie_port_s { 6572232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6573215976Sjmallett uint64_t pp : 64; /**< The PCIe port that the Packet ring number is 6574215976Sjmallett assigned. Two bits are used per ring (i.e. ring 0 6575215976Sjmallett [1:0], ring 1 [3:2], ....). A value of '0 means 6576215976Sjmallett that the Packetring is assign to PCIe Port 0, a '1' 6577215976Sjmallett PCIe Port 1, '2' and '3' are reserved. */ 6578215976Sjmallett#else 6579215976Sjmallett uint64_t pp : 64; 6580215976Sjmallett#endif 6581215976Sjmallett } s; 6582215976Sjmallett struct cvmx_npei_pkt_in_pcie_port_s cn52xx; 6583215976Sjmallett struct cvmx_npei_pkt_in_pcie_port_s cn56xx; 6584215976Sjmallett}; 6585215976Sjmalletttypedef union cvmx_npei_pkt_in_pcie_port cvmx_npei_pkt_in_pcie_port_t; 6586215976Sjmallett 6587215976Sjmallett/** 6588215976Sjmallett * cvmx_npei_pkt_input_control 6589215976Sjmallett * 6590215976Sjmallett * NPEI_PKT_INPUT_CONTROL = NPEI's Packet Input Control 6591215976Sjmallett * 6592215976Sjmallett * Control for reads for gather list and instructions. 6593215976Sjmallett */ 6594232812Sjmallettunion cvmx_npei_pkt_input_control { 6595215976Sjmallett uint64_t u64; 6596232812Sjmallett struct cvmx_npei_pkt_input_control_s { 6597232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6598215976Sjmallett uint64_t reserved_23_63 : 41; 6599215976Sjmallett uint64_t pkt_rr : 1; /**< When set '1' the input packet selection will be 6600215976Sjmallett made with a Round Robin arbitration. When '0' 6601215976Sjmallett the input packet ring is fixed in priority, 6602215976Sjmallett where the lower ring number has higher priority. */ 6603215976Sjmallett uint64_t pbp_dhi : 13; /**< Field when in [PBP] is set to be used in 6604215976Sjmallett calculating a DPTR. */ 6605215976Sjmallett uint64_t d_nsr : 1; /**< Enables '1' NoSnoop for reading of 6606215976Sjmallett gather data. */ 6607215976Sjmallett uint64_t d_esr : 2; /**< The Endian-Swap-Mode for reading of 6608215976Sjmallett gather data. */ 6609215976Sjmallett uint64_t d_ror : 1; /**< Enables '1' Relaxed Ordering for reading of 6610215976Sjmallett gather data. */ 6611215976Sjmallett uint64_t use_csr : 1; /**< When set '1' the csr value will be used for 6612215976Sjmallett ROR, ESR, and NSR. When clear '0' the value in 6613215976Sjmallett DPTR will be used. In turn the bits not used for 6614215976Sjmallett ROR, ESR, and NSR, will be used for bits [63:60] 6615215976Sjmallett of the address used to fetch packet data. */ 6616215976Sjmallett uint64_t nsr : 1; /**< Enables '1' NoSnoop for reading of 6617215976Sjmallett gather list and gather instruction. */ 6618215976Sjmallett uint64_t esr : 2; /**< The Endian-Swap-Mode for reading of 6619215976Sjmallett gather list and gather instruction. */ 6620215976Sjmallett uint64_t ror : 1; /**< Enables '1' Relaxed Ordering for reading of 6621215976Sjmallett gather list and gather instruction. */ 6622215976Sjmallett#else 6623215976Sjmallett uint64_t ror : 1; 6624215976Sjmallett uint64_t esr : 2; 6625215976Sjmallett uint64_t nsr : 1; 6626215976Sjmallett uint64_t use_csr : 1; 6627215976Sjmallett uint64_t d_ror : 1; 6628215976Sjmallett uint64_t d_esr : 2; 6629215976Sjmallett uint64_t d_nsr : 1; 6630215976Sjmallett uint64_t pbp_dhi : 13; 6631215976Sjmallett uint64_t pkt_rr : 1; 6632215976Sjmallett uint64_t reserved_23_63 : 41; 6633215976Sjmallett#endif 6634215976Sjmallett } s; 6635215976Sjmallett struct cvmx_npei_pkt_input_control_s cn52xx; 6636215976Sjmallett struct cvmx_npei_pkt_input_control_s cn56xx; 6637215976Sjmallett}; 6638215976Sjmalletttypedef union cvmx_npei_pkt_input_control cvmx_npei_pkt_input_control_t; 6639215976Sjmallett 6640215976Sjmallett/** 6641215976Sjmallett * cvmx_npei_pkt_instr_enb 6642215976Sjmallett * 6643215976Sjmallett * NPEI_PKT_INSTR_ENB = NPEI's Packet Instruction Enable 6644215976Sjmallett * 6645215976Sjmallett * Enables the instruction fetch for a Packet-ring. 6646215976Sjmallett */ 6647232812Sjmallettunion cvmx_npei_pkt_instr_enb { 6648215976Sjmallett uint64_t u64; 6649232812Sjmallett struct cvmx_npei_pkt_instr_enb_s { 6650232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6651215976Sjmallett uint64_t reserved_32_63 : 32; 6652215976Sjmallett uint64_t enb : 32; /**< When asserted '1' the vector bit cooresponding 6653215976Sjmallett to the Packet-ring is enabled. */ 6654215976Sjmallett#else 6655215976Sjmallett uint64_t enb : 32; 6656215976Sjmallett uint64_t reserved_32_63 : 32; 6657215976Sjmallett#endif 6658215976Sjmallett } s; 6659215976Sjmallett struct cvmx_npei_pkt_instr_enb_s cn52xx; 6660215976Sjmallett struct cvmx_npei_pkt_instr_enb_s cn56xx; 6661215976Sjmallett}; 6662215976Sjmalletttypedef union cvmx_npei_pkt_instr_enb cvmx_npei_pkt_instr_enb_t; 6663215976Sjmallett 6664215976Sjmallett/** 6665215976Sjmallett * cvmx_npei_pkt_instr_rd_size 6666215976Sjmallett * 6667215976Sjmallett * NPEI_PKT_INSTR_RD_SIZE = NPEI Instruction Read Size 6668215976Sjmallett * 6669215976Sjmallett * The number of instruction allowed to be read at one time. 6670215976Sjmallett */ 6671232812Sjmallettunion cvmx_npei_pkt_instr_rd_size { 6672215976Sjmallett uint64_t u64; 6673232812Sjmallett struct cvmx_npei_pkt_instr_rd_size_s { 6674232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6675215976Sjmallett uint64_t rdsize : 64; /**< Number of instructions to be read in one PCIe read 6676215976Sjmallett request for the 4 PKOport - 8 rings. Every two bits 6677215976Sjmallett (i.e. 1:0, 3:2, 5:4..) are assign to the port/ring 6678215976Sjmallett combinations. 6679215976Sjmallett - 15:0 PKOPort0,Ring 7..0 31:16 PKOPort1,Ring 7..0 6680215976Sjmallett - 47:32 PKOPort2,Ring 7..0 63:48 PKOPort3,Ring 7..0 6681215976Sjmallett Two bit value are: 6682215976Sjmallett 0 - 1 Instruction 6683215976Sjmallett 1 - 2 Instructions 6684215976Sjmallett 2 - 3 Instructions 6685215976Sjmallett 3 - 4 Instructions */ 6686215976Sjmallett#else 6687215976Sjmallett uint64_t rdsize : 64; 6688215976Sjmallett#endif 6689215976Sjmallett } s; 6690215976Sjmallett struct cvmx_npei_pkt_instr_rd_size_s cn52xx; 6691215976Sjmallett struct cvmx_npei_pkt_instr_rd_size_s cn56xx; 6692215976Sjmallett}; 6693215976Sjmalletttypedef union cvmx_npei_pkt_instr_rd_size cvmx_npei_pkt_instr_rd_size_t; 6694215976Sjmallett 6695215976Sjmallett/** 6696215976Sjmallett * cvmx_npei_pkt_instr_size 6697215976Sjmallett * 6698215976Sjmallett * NPEI_PKT_INSTR_SIZE = NPEI's Packet Instruction Size 6699215976Sjmallett * 6700215976Sjmallett * Determines if instructions are 64 or 32 byte in size for a Packet-ring. 6701215976Sjmallett */ 6702232812Sjmallettunion cvmx_npei_pkt_instr_size { 6703215976Sjmallett uint64_t u64; 6704232812Sjmallett struct cvmx_npei_pkt_instr_size_s { 6705232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6706215976Sjmallett uint64_t reserved_32_63 : 32; 6707215976Sjmallett uint64_t is_64b : 32; /**< When asserted '1' the vector bit cooresponding 6708215976Sjmallett to the Packet-ring is a 64-byte instruction. */ 6709215976Sjmallett#else 6710215976Sjmallett uint64_t is_64b : 32; 6711215976Sjmallett uint64_t reserved_32_63 : 32; 6712215976Sjmallett#endif 6713215976Sjmallett } s; 6714215976Sjmallett struct cvmx_npei_pkt_instr_size_s cn52xx; 6715215976Sjmallett struct cvmx_npei_pkt_instr_size_s cn56xx; 6716215976Sjmallett}; 6717215976Sjmalletttypedef union cvmx_npei_pkt_instr_size cvmx_npei_pkt_instr_size_t; 6718215976Sjmallett 6719215976Sjmallett/** 6720215976Sjmallett * cvmx_npei_pkt_int_levels 6721215976Sjmallett * 6722215976Sjmallett * 0x90F0 reserved NPEI_PKT_PCIE_PORT2 6723215976Sjmallett * 6724215976Sjmallett * 6725215976Sjmallett * NPEI_PKT_INT_LEVELS = NPEI's Packet Interrupt Levels 6726215976Sjmallett * 6727215976Sjmallett * Output packet interrupt levels. 6728215976Sjmallett */ 6729232812Sjmallettunion cvmx_npei_pkt_int_levels { 6730215976Sjmallett uint64_t u64; 6731232812Sjmallett struct cvmx_npei_pkt_int_levels_s { 6732232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6733215976Sjmallett uint64_t reserved_54_63 : 10; 6734215976Sjmallett uint64_t time : 22; /**< When NPEI_PKT#_CNTS[TIMER] is greater than this 6735215976Sjmallett value an interrupt is generated. */ 6736215976Sjmallett uint64_t cnt : 32; /**< When NPEI_PKT#_CNTS[CNT] becomes 6737215976Sjmallett greater than this value an interrupt is generated. */ 6738215976Sjmallett#else 6739215976Sjmallett uint64_t cnt : 32; 6740215976Sjmallett uint64_t time : 22; 6741215976Sjmallett uint64_t reserved_54_63 : 10; 6742215976Sjmallett#endif 6743215976Sjmallett } s; 6744215976Sjmallett struct cvmx_npei_pkt_int_levels_s cn52xx; 6745215976Sjmallett struct cvmx_npei_pkt_int_levels_s cn56xx; 6746215976Sjmallett}; 6747215976Sjmalletttypedef union cvmx_npei_pkt_int_levels cvmx_npei_pkt_int_levels_t; 6748215976Sjmallett 6749215976Sjmallett/** 6750215976Sjmallett * cvmx_npei_pkt_iptr 6751215976Sjmallett * 6752215976Sjmallett * NPEI_PKT_IPTR = NPEI's Packet Info Poitner 6753215976Sjmallett * 6754215976Sjmallett * Controls using the Info-Pointer to store length and data. 6755215976Sjmallett */ 6756232812Sjmallettunion cvmx_npei_pkt_iptr { 6757215976Sjmallett uint64_t u64; 6758232812Sjmallett struct cvmx_npei_pkt_iptr_s { 6759232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6760215976Sjmallett uint64_t reserved_32_63 : 32; 6761215976Sjmallett uint64_t iptr : 32; /**< When asserted '1' the vector bit cooresponding 6762215976Sjmallett to the Packet-ring will use the Info-Pointer to 6763215976Sjmallett store length and data. */ 6764215976Sjmallett#else 6765215976Sjmallett uint64_t iptr : 32; 6766215976Sjmallett uint64_t reserved_32_63 : 32; 6767215976Sjmallett#endif 6768215976Sjmallett } s; 6769215976Sjmallett struct cvmx_npei_pkt_iptr_s cn52xx; 6770215976Sjmallett struct cvmx_npei_pkt_iptr_s cn56xx; 6771215976Sjmallett}; 6772215976Sjmalletttypedef union cvmx_npei_pkt_iptr cvmx_npei_pkt_iptr_t; 6773215976Sjmallett 6774215976Sjmallett/** 6775215976Sjmallett * cvmx_npei_pkt_out_bmode 6776215976Sjmallett * 6777215976Sjmallett * NPEI_PKT_OUT_BMODE = NPEI's Packet Out Byte Mode 6778215976Sjmallett * 6779215976Sjmallett * Control the updating of the NPEI_PKT#_CNT register. 6780215976Sjmallett */ 6781232812Sjmallettunion cvmx_npei_pkt_out_bmode { 6782215976Sjmallett uint64_t u64; 6783232812Sjmallett struct cvmx_npei_pkt_out_bmode_s { 6784232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6785215976Sjmallett uint64_t reserved_32_63 : 32; 6786215976Sjmallett uint64_t bmode : 32; /**< When asserted '1' the vector bit cooresponding 6787215976Sjmallett to the Packet-ring will have its NPEI_PKT#_CNT 6788215976Sjmallett register updated with the number of bytes in the 6789215976Sjmallett packet sent, when '0' the register will have a 6790215976Sjmallett value of '1' added. */ 6791215976Sjmallett#else 6792215976Sjmallett uint64_t bmode : 32; 6793215976Sjmallett uint64_t reserved_32_63 : 32; 6794215976Sjmallett#endif 6795215976Sjmallett } s; 6796215976Sjmallett struct cvmx_npei_pkt_out_bmode_s cn52xx; 6797215976Sjmallett struct cvmx_npei_pkt_out_bmode_s cn56xx; 6798215976Sjmallett}; 6799215976Sjmalletttypedef union cvmx_npei_pkt_out_bmode cvmx_npei_pkt_out_bmode_t; 6800215976Sjmallett 6801215976Sjmallett/** 6802215976Sjmallett * cvmx_npei_pkt_out_enb 6803215976Sjmallett * 6804215976Sjmallett * NPEI_PKT_OUT_ENB = NPEI's Packet Output Enable 6805215976Sjmallett * 6806215976Sjmallett * Enables the output packet engines. 6807215976Sjmallett */ 6808232812Sjmallettunion cvmx_npei_pkt_out_enb { 6809215976Sjmallett uint64_t u64; 6810232812Sjmallett struct cvmx_npei_pkt_out_enb_s { 6811232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6812215976Sjmallett uint64_t reserved_32_63 : 32; 6813215976Sjmallett uint64_t enb : 32; /**< When asserted '1' the vector bit cooresponding 6814215976Sjmallett to the Packet-ring is enabled. 6815215976Sjmallett If an error occurs on reading pointers for an 6816215976Sjmallett output ring, the ring will be disabled by clearing 6817215976Sjmallett the bit associated with the ring to '0'. */ 6818215976Sjmallett#else 6819215976Sjmallett uint64_t enb : 32; 6820215976Sjmallett uint64_t reserved_32_63 : 32; 6821215976Sjmallett#endif 6822215976Sjmallett } s; 6823215976Sjmallett struct cvmx_npei_pkt_out_enb_s cn52xx; 6824215976Sjmallett struct cvmx_npei_pkt_out_enb_s cn56xx; 6825215976Sjmallett}; 6826215976Sjmalletttypedef union cvmx_npei_pkt_out_enb cvmx_npei_pkt_out_enb_t; 6827215976Sjmallett 6828215976Sjmallett/** 6829215976Sjmallett * cvmx_npei_pkt_output_wmark 6830215976Sjmallett * 6831215976Sjmallett * NPEI_PKT_OUTPUT_WMARK = NPEI's Packet Output Water Mark 6832215976Sjmallett * 6833215976Sjmallett * Value that when the NPEI_PKT#_SLIST_BAOFF_DBELL[DBELL] value is less then that backpressure for the rings will be applied. 6834215976Sjmallett */ 6835232812Sjmallettunion cvmx_npei_pkt_output_wmark { 6836215976Sjmallett uint64_t u64; 6837232812Sjmallett struct cvmx_npei_pkt_output_wmark_s { 6838232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6839215976Sjmallett uint64_t reserved_32_63 : 32; 6840215976Sjmallett uint64_t wmark : 32; /**< Value when DBELL count drops below backpressure 6841215976Sjmallett for the ring will be applied to the PKO. */ 6842215976Sjmallett#else 6843215976Sjmallett uint64_t wmark : 32; 6844215976Sjmallett uint64_t reserved_32_63 : 32; 6845215976Sjmallett#endif 6846215976Sjmallett } s; 6847215976Sjmallett struct cvmx_npei_pkt_output_wmark_s cn52xx; 6848215976Sjmallett struct cvmx_npei_pkt_output_wmark_s cn56xx; 6849215976Sjmallett}; 6850215976Sjmalletttypedef union cvmx_npei_pkt_output_wmark cvmx_npei_pkt_output_wmark_t; 6851215976Sjmallett 6852215976Sjmallett/** 6853215976Sjmallett * cvmx_npei_pkt_pcie_port 6854215976Sjmallett * 6855215976Sjmallett * NPEI_PKT_PCIE_PORT = NPEI's Packet To PCIe Port Assignment 6856215976Sjmallett * 6857215976Sjmallett * Assigns Packet Ports to PCIe ports. 6858215976Sjmallett */ 6859232812Sjmallettunion cvmx_npei_pkt_pcie_port { 6860215976Sjmallett uint64_t u64; 6861232812Sjmallett struct cvmx_npei_pkt_pcie_port_s { 6862232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6863215976Sjmallett uint64_t pp : 64; /**< The PCIe port that the Packet ring number is 6864215976Sjmallett assigned. Two bits are used per ring (i.e. ring 0 6865215976Sjmallett [1:0], ring 1 [3:2], ....). A value of '0 means 6866215976Sjmallett that the Packetring is assign to PCIe Port 0, a '1' 6867215976Sjmallett PCIe Port 1, '2' and '3' are reserved. */ 6868215976Sjmallett#else 6869215976Sjmallett uint64_t pp : 64; 6870215976Sjmallett#endif 6871215976Sjmallett } s; 6872215976Sjmallett struct cvmx_npei_pkt_pcie_port_s cn52xx; 6873215976Sjmallett struct cvmx_npei_pkt_pcie_port_s cn56xx; 6874215976Sjmallett}; 6875215976Sjmalletttypedef union cvmx_npei_pkt_pcie_port cvmx_npei_pkt_pcie_port_t; 6876215976Sjmallett 6877215976Sjmallett/** 6878215976Sjmallett * cvmx_npei_pkt_port_in_rst 6879215976Sjmallett * 6880215976Sjmallett * NPEI_PKT_PORT_IN_RST = NPEI Packet Port In Reset 6881215976Sjmallett * 6882215976Sjmallett * Vector bits related to ring-port for ones that are reset. 6883215976Sjmallett */ 6884232812Sjmallettunion cvmx_npei_pkt_port_in_rst { 6885215976Sjmallett uint64_t u64; 6886232812Sjmallett struct cvmx_npei_pkt_port_in_rst_s { 6887232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6888215976Sjmallett uint64_t in_rst : 32; /**< When asserted '1' the vector bit cooresponding 6889215976Sjmallett to the inbound Packet-ring is in reset. */ 6890215976Sjmallett uint64_t out_rst : 32; /**< When asserted '1' the vector bit cooresponding 6891215976Sjmallett to the outbound Packet-ring is in reset. */ 6892215976Sjmallett#else 6893215976Sjmallett uint64_t out_rst : 32; 6894215976Sjmallett uint64_t in_rst : 32; 6895215976Sjmallett#endif 6896215976Sjmallett } s; 6897215976Sjmallett struct cvmx_npei_pkt_port_in_rst_s cn52xx; 6898215976Sjmallett struct cvmx_npei_pkt_port_in_rst_s cn56xx; 6899215976Sjmallett}; 6900215976Sjmalletttypedef union cvmx_npei_pkt_port_in_rst cvmx_npei_pkt_port_in_rst_t; 6901215976Sjmallett 6902215976Sjmallett/** 6903215976Sjmallett * cvmx_npei_pkt_slist_es 6904215976Sjmallett * 6905215976Sjmallett * NPEI_PKT_SLIST_ES = NPEI's Packet Scatter List Endian Swap 6906215976Sjmallett * 6907215976Sjmallett * The Endian Swap for Scatter List Read. 6908215976Sjmallett */ 6909232812Sjmallettunion cvmx_npei_pkt_slist_es { 6910215976Sjmallett uint64_t u64; 6911232812Sjmallett struct cvmx_npei_pkt_slist_es_s { 6912232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6913215976Sjmallett uint64_t es : 64; /**< The endian swap mode for Packet rings 0 through 31. 6914215976Sjmallett Two bits are used per ring (i.e. ring 0 [1:0], 6915215976Sjmallett ring 1 [3:2], ....). */ 6916215976Sjmallett#else 6917215976Sjmallett uint64_t es : 64; 6918215976Sjmallett#endif 6919215976Sjmallett } s; 6920215976Sjmallett struct cvmx_npei_pkt_slist_es_s cn52xx; 6921215976Sjmallett struct cvmx_npei_pkt_slist_es_s cn56xx; 6922215976Sjmallett}; 6923215976Sjmalletttypedef union cvmx_npei_pkt_slist_es cvmx_npei_pkt_slist_es_t; 6924215976Sjmallett 6925215976Sjmallett/** 6926215976Sjmallett * cvmx_npei_pkt_slist_id_size 6927215976Sjmallett * 6928215976Sjmallett * NPEI_PKT_SLIST_ID_SIZE = NPEI Packet Scatter List Info and Data Size 6929215976Sjmallett * 6930215976Sjmallett * The Size of the information and data fields pointed to by Scatter List pointers. 6931215976Sjmallett */ 6932232812Sjmallettunion cvmx_npei_pkt_slist_id_size { 6933215976Sjmallett uint64_t u64; 6934232812Sjmallett struct cvmx_npei_pkt_slist_id_size_s { 6935232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6936215976Sjmallett uint64_t reserved_23_63 : 41; 6937215976Sjmallett uint64_t isize : 7; /**< Information size. Legal sizes are 0 to 120. */ 6938215976Sjmallett uint64_t bsize : 16; /**< Data size. */ 6939215976Sjmallett#else 6940215976Sjmallett uint64_t bsize : 16; 6941215976Sjmallett uint64_t isize : 7; 6942215976Sjmallett uint64_t reserved_23_63 : 41; 6943215976Sjmallett#endif 6944215976Sjmallett } s; 6945215976Sjmallett struct cvmx_npei_pkt_slist_id_size_s cn52xx; 6946215976Sjmallett struct cvmx_npei_pkt_slist_id_size_s cn56xx; 6947215976Sjmallett}; 6948215976Sjmalletttypedef union cvmx_npei_pkt_slist_id_size cvmx_npei_pkt_slist_id_size_t; 6949215976Sjmallett 6950215976Sjmallett/** 6951215976Sjmallett * cvmx_npei_pkt_slist_ns 6952215976Sjmallett * 6953215976Sjmallett * NPEI_PKT_SLIST_NS = NPEI's Packet Scatter List No Snoop 6954215976Sjmallett * 6955215976Sjmallett * The NS field for the TLP when fetching Scatter List. 6956215976Sjmallett */ 6957232812Sjmallettunion cvmx_npei_pkt_slist_ns { 6958215976Sjmallett uint64_t u64; 6959232812Sjmallett struct cvmx_npei_pkt_slist_ns_s { 6960232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6961215976Sjmallett uint64_t reserved_32_63 : 32; 6962215976Sjmallett uint64_t nsr : 32; /**< When asserted '1' the vector bit cooresponding 6963215976Sjmallett to the Packet-ring will enable NS in TLP header. */ 6964215976Sjmallett#else 6965215976Sjmallett uint64_t nsr : 32; 6966215976Sjmallett uint64_t reserved_32_63 : 32; 6967215976Sjmallett#endif 6968215976Sjmallett } s; 6969215976Sjmallett struct cvmx_npei_pkt_slist_ns_s cn52xx; 6970215976Sjmallett struct cvmx_npei_pkt_slist_ns_s cn56xx; 6971215976Sjmallett}; 6972215976Sjmalletttypedef union cvmx_npei_pkt_slist_ns cvmx_npei_pkt_slist_ns_t; 6973215976Sjmallett 6974215976Sjmallett/** 6975215976Sjmallett * cvmx_npei_pkt_slist_ror 6976215976Sjmallett * 6977215976Sjmallett * NPEI_PKT_SLIST_ROR = NPEI's Packet Scatter List Relaxed Ordering 6978215976Sjmallett * 6979215976Sjmallett * The ROR field for the TLP when fetching Scatter List. 6980215976Sjmallett */ 6981232812Sjmallettunion cvmx_npei_pkt_slist_ror { 6982215976Sjmallett uint64_t u64; 6983232812Sjmallett struct cvmx_npei_pkt_slist_ror_s { 6984232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6985215976Sjmallett uint64_t reserved_32_63 : 32; 6986215976Sjmallett uint64_t ror : 32; /**< When asserted '1' the vector bit cooresponding 6987215976Sjmallett to the Packet-ring will enable ROR in TLP header. */ 6988215976Sjmallett#else 6989215976Sjmallett uint64_t ror : 32; 6990215976Sjmallett uint64_t reserved_32_63 : 32; 6991215976Sjmallett#endif 6992215976Sjmallett } s; 6993215976Sjmallett struct cvmx_npei_pkt_slist_ror_s cn52xx; 6994215976Sjmallett struct cvmx_npei_pkt_slist_ror_s cn56xx; 6995215976Sjmallett}; 6996215976Sjmalletttypedef union cvmx_npei_pkt_slist_ror cvmx_npei_pkt_slist_ror_t; 6997215976Sjmallett 6998215976Sjmallett/** 6999215976Sjmallett * cvmx_npei_pkt_time_int 7000215976Sjmallett * 7001215976Sjmallett * NPEI_PKT_TIME_INT = NPEI Packet Timer Interrupt 7002215976Sjmallett * 7003215976Sjmallett * The packets rings that are interrupting because of Packet Timers. 7004215976Sjmallett */ 7005232812Sjmallettunion cvmx_npei_pkt_time_int { 7006215976Sjmallett uint64_t u64; 7007232812Sjmallett struct cvmx_npei_pkt_time_int_s { 7008232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7009215976Sjmallett uint64_t reserved_32_63 : 32; 7010215976Sjmallett uint64_t port : 32; /**< Bit vector cooresponding to ring number is set when 7011215976Sjmallett NPEI_PKT#_CNTS[TIMER] is greater than 7012215976Sjmallett NPEI_PKT_INT_LEVELS[TIME]. */ 7013215976Sjmallett#else 7014215976Sjmallett uint64_t port : 32; 7015215976Sjmallett uint64_t reserved_32_63 : 32; 7016215976Sjmallett#endif 7017215976Sjmallett } s; 7018215976Sjmallett struct cvmx_npei_pkt_time_int_s cn52xx; 7019215976Sjmallett struct cvmx_npei_pkt_time_int_s cn56xx; 7020215976Sjmallett}; 7021215976Sjmalletttypedef union cvmx_npei_pkt_time_int cvmx_npei_pkt_time_int_t; 7022215976Sjmallett 7023215976Sjmallett/** 7024215976Sjmallett * cvmx_npei_pkt_time_int_enb 7025215976Sjmallett * 7026215976Sjmallett * NPEI_PKT_TIME_INT_ENB = NPEI Packet Timer Interrupt Enable 7027215976Sjmallett * 7028215976Sjmallett * The packets rings that are interrupting because of Packet Timers. 7029215976Sjmallett */ 7030232812Sjmallettunion cvmx_npei_pkt_time_int_enb { 7031215976Sjmallett uint64_t u64; 7032232812Sjmallett struct cvmx_npei_pkt_time_int_enb_s { 7033232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7034215976Sjmallett uint64_t reserved_32_63 : 32; 7035215976Sjmallett uint64_t port : 32; /**< Bit vector cooresponding to ring number when set 7036215976Sjmallett allows NPEI_PKT_TIME_INT to generate an interrupt. */ 7037215976Sjmallett#else 7038215976Sjmallett uint64_t port : 32; 7039215976Sjmallett uint64_t reserved_32_63 : 32; 7040215976Sjmallett#endif 7041215976Sjmallett } s; 7042215976Sjmallett struct cvmx_npei_pkt_time_int_enb_s cn52xx; 7043215976Sjmallett struct cvmx_npei_pkt_time_int_enb_s cn56xx; 7044215976Sjmallett}; 7045215976Sjmalletttypedef union cvmx_npei_pkt_time_int_enb cvmx_npei_pkt_time_int_enb_t; 7046215976Sjmallett 7047215976Sjmallett/** 7048215976Sjmallett * cvmx_npei_rsl_int_blocks 7049215976Sjmallett * 7050215976Sjmallett * NPEI_RSL_INT_BLOCKS = NPEI RSL Interrupt Blocks Register 7051215976Sjmallett * 7052215976Sjmallett * Reading this register will return a vector with a bit set '1' for a corresponding RSL block 7053215976Sjmallett * that presently has an interrupt pending. The Field Description below supplies the name of the 7054215976Sjmallett * register that software should read to find out why that intterupt bit is set. 7055215976Sjmallett */ 7056232812Sjmallettunion cvmx_npei_rsl_int_blocks { 7057215976Sjmallett uint64_t u64; 7058232812Sjmallett struct cvmx_npei_rsl_int_blocks_s { 7059232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7060215976Sjmallett uint64_t reserved_31_63 : 33; 7061215976Sjmallett uint64_t iob : 1; /**< IOB_INT_SUM */ 7062215976Sjmallett uint64_t lmc1 : 1; /**< LMC1_MEM_CFG0 */ 7063215976Sjmallett uint64_t agl : 1; /**< AGL_GMX_RX0_INT_REG & AGL_GMX_TX_INT_REG */ 7064215976Sjmallett uint64_t reserved_24_27 : 4; 7065215976Sjmallett uint64_t asxpcs1 : 1; /**< PCS1_INT*_REG */ 7066215976Sjmallett uint64_t asxpcs0 : 1; /**< PCS0_INT*_REG */ 7067215976Sjmallett uint64_t reserved_21_21 : 1; 7068215976Sjmallett uint64_t pip : 1; /**< PIP_INT_REG. */ 7069215976Sjmallett uint64_t spx1 : 1; /**< Always reads as zero */ 7070215976Sjmallett uint64_t spx0 : 1; /**< Always reads as zero */ 7071215976Sjmallett uint64_t lmc0 : 1; /**< LMC0_MEM_CFG0 */ 7072215976Sjmallett uint64_t l2c : 1; /**< L2C_INT_STAT */ 7073215976Sjmallett uint64_t usb1 : 1; /**< Always reads as zero */ 7074215976Sjmallett uint64_t rad : 1; /**< RAD_REG_ERROR */ 7075215976Sjmallett uint64_t usb : 1; /**< USBN0_INT_SUM */ 7076215976Sjmallett uint64_t pow : 1; /**< POW_ECC_ERR */ 7077215976Sjmallett uint64_t tim : 1; /**< TIM_REG_ERROR */ 7078215976Sjmallett uint64_t pko : 1; /**< PKO_REG_ERROR */ 7079215976Sjmallett uint64_t ipd : 1; /**< IPD_INT_SUM */ 7080215976Sjmallett uint64_t reserved_8_8 : 1; 7081215976Sjmallett uint64_t zip : 1; /**< ZIP_ERROR */ 7082215976Sjmallett uint64_t dfa : 1; /**< Always reads as zero */ 7083215976Sjmallett uint64_t fpa : 1; /**< FPA_INT_SUM */ 7084215976Sjmallett uint64_t key : 1; /**< KEY_INT_SUM */ 7085215976Sjmallett uint64_t npei : 1; /**< NPEI_INT_SUM */ 7086215976Sjmallett uint64_t gmx1 : 1; /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */ 7087215976Sjmallett uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */ 7088215976Sjmallett uint64_t mio : 1; /**< MIO_BOOT_ERR */ 7089215976Sjmallett#else 7090215976Sjmallett uint64_t mio : 1; 7091215976Sjmallett uint64_t gmx0 : 1; 7092215976Sjmallett uint64_t gmx1 : 1; 7093215976Sjmallett uint64_t npei : 1; 7094215976Sjmallett uint64_t key : 1; 7095215976Sjmallett uint64_t fpa : 1; 7096215976Sjmallett uint64_t dfa : 1; 7097215976Sjmallett uint64_t zip : 1; 7098215976Sjmallett uint64_t reserved_8_8 : 1; 7099215976Sjmallett uint64_t ipd : 1; 7100215976Sjmallett uint64_t pko : 1; 7101215976Sjmallett uint64_t tim : 1; 7102215976Sjmallett uint64_t pow : 1; 7103215976Sjmallett uint64_t usb : 1; 7104215976Sjmallett uint64_t rad : 1; 7105215976Sjmallett uint64_t usb1 : 1; 7106215976Sjmallett uint64_t l2c : 1; 7107215976Sjmallett uint64_t lmc0 : 1; 7108215976Sjmallett uint64_t spx0 : 1; 7109215976Sjmallett uint64_t spx1 : 1; 7110215976Sjmallett uint64_t pip : 1; 7111215976Sjmallett uint64_t reserved_21_21 : 1; 7112215976Sjmallett uint64_t asxpcs0 : 1; 7113215976Sjmallett uint64_t asxpcs1 : 1; 7114215976Sjmallett uint64_t reserved_24_27 : 4; 7115215976Sjmallett uint64_t agl : 1; 7116215976Sjmallett uint64_t lmc1 : 1; 7117215976Sjmallett uint64_t iob : 1; 7118215976Sjmallett uint64_t reserved_31_63 : 33; 7119215976Sjmallett#endif 7120215976Sjmallett } s; 7121215976Sjmallett struct cvmx_npei_rsl_int_blocks_s cn52xx; 7122215976Sjmallett struct cvmx_npei_rsl_int_blocks_s cn52xxp1; 7123215976Sjmallett struct cvmx_npei_rsl_int_blocks_s cn56xx; 7124215976Sjmallett struct cvmx_npei_rsl_int_blocks_s cn56xxp1; 7125215976Sjmallett}; 7126215976Sjmalletttypedef union cvmx_npei_rsl_int_blocks cvmx_npei_rsl_int_blocks_t; 7127215976Sjmallett 7128215976Sjmallett/** 7129215976Sjmallett * cvmx_npei_scratch_1 7130215976Sjmallett * 7131215976Sjmallett * NPEI_SCRATCH_1 = NPEI's Scratch 1 7132215976Sjmallett * 7133215976Sjmallett * A general purpose 64 bit register for SW use. 7134215976Sjmallett */ 7135232812Sjmallettunion cvmx_npei_scratch_1 { 7136215976Sjmallett uint64_t u64; 7137232812Sjmallett struct cvmx_npei_scratch_1_s { 7138232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7139215976Sjmallett uint64_t data : 64; /**< The value in this register is totaly SW dependent. */ 7140215976Sjmallett#else 7141215976Sjmallett uint64_t data : 64; 7142215976Sjmallett#endif 7143215976Sjmallett } s; 7144215976Sjmallett struct cvmx_npei_scratch_1_s cn52xx; 7145215976Sjmallett struct cvmx_npei_scratch_1_s cn52xxp1; 7146215976Sjmallett struct cvmx_npei_scratch_1_s cn56xx; 7147215976Sjmallett struct cvmx_npei_scratch_1_s cn56xxp1; 7148215976Sjmallett}; 7149215976Sjmalletttypedef union cvmx_npei_scratch_1 cvmx_npei_scratch_1_t; 7150215976Sjmallett 7151215976Sjmallett/** 7152215976Sjmallett * cvmx_npei_state1 7153215976Sjmallett * 7154215976Sjmallett * NPEI_STATE1 = NPEI State 1 7155215976Sjmallett * 7156215976Sjmallett * State machines in NPEI. For debug. 7157215976Sjmallett */ 7158232812Sjmallettunion cvmx_npei_state1 { 7159215976Sjmallett uint64_t u64; 7160232812Sjmallett struct cvmx_npei_state1_s { 7161232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7162215976Sjmallett uint64_t cpl1 : 12; /**< CPL1 State */ 7163215976Sjmallett uint64_t cpl0 : 12; /**< CPL0 State */ 7164215976Sjmallett uint64_t arb : 1; /**< ARB State */ 7165215976Sjmallett uint64_t csr : 39; /**< CSR State */ 7166215976Sjmallett#else 7167215976Sjmallett uint64_t csr : 39; 7168215976Sjmallett uint64_t arb : 1; 7169215976Sjmallett uint64_t cpl0 : 12; 7170215976Sjmallett uint64_t cpl1 : 12; 7171215976Sjmallett#endif 7172215976Sjmallett } s; 7173215976Sjmallett struct cvmx_npei_state1_s cn52xx; 7174215976Sjmallett struct cvmx_npei_state1_s cn52xxp1; 7175215976Sjmallett struct cvmx_npei_state1_s cn56xx; 7176215976Sjmallett struct cvmx_npei_state1_s cn56xxp1; 7177215976Sjmallett}; 7178215976Sjmalletttypedef union cvmx_npei_state1 cvmx_npei_state1_t; 7179215976Sjmallett 7180215976Sjmallett/** 7181215976Sjmallett * cvmx_npei_state2 7182215976Sjmallett * 7183215976Sjmallett * NPEI_STATE2 = NPEI State 2 7184215976Sjmallett * 7185215976Sjmallett * State machines in NPEI. For debug. 7186215976Sjmallett */ 7187232812Sjmallettunion cvmx_npei_state2 { 7188215976Sjmallett uint64_t u64; 7189232812Sjmallett struct cvmx_npei_state2_s { 7190232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7191215976Sjmallett uint64_t reserved_48_63 : 16; 7192215976Sjmallett uint64_t npei : 1; /**< NPEI State */ 7193215976Sjmallett uint64_t rac : 1; /**< RAC State */ 7194215976Sjmallett uint64_t csm1 : 15; /**< CSM1 State */ 7195215976Sjmallett uint64_t csm0 : 15; /**< CSM0 State */ 7196215976Sjmallett uint64_t nnp0 : 8; /**< NNP0 State */ 7197215976Sjmallett uint64_t nnd : 8; /**< NND State */ 7198215976Sjmallett#else 7199215976Sjmallett uint64_t nnd : 8; 7200215976Sjmallett uint64_t nnp0 : 8; 7201215976Sjmallett uint64_t csm0 : 15; 7202215976Sjmallett uint64_t csm1 : 15; 7203215976Sjmallett uint64_t rac : 1; 7204215976Sjmallett uint64_t npei : 1; 7205215976Sjmallett uint64_t reserved_48_63 : 16; 7206215976Sjmallett#endif 7207215976Sjmallett } s; 7208215976Sjmallett struct cvmx_npei_state2_s cn52xx; 7209215976Sjmallett struct cvmx_npei_state2_s cn52xxp1; 7210215976Sjmallett struct cvmx_npei_state2_s cn56xx; 7211215976Sjmallett struct cvmx_npei_state2_s cn56xxp1; 7212215976Sjmallett}; 7213215976Sjmalletttypedef union cvmx_npei_state2 cvmx_npei_state2_t; 7214215976Sjmallett 7215215976Sjmallett/** 7216215976Sjmallett * cvmx_npei_state3 7217215976Sjmallett * 7218215976Sjmallett * NPEI_STATE3 = NPEI State 3 7219215976Sjmallett * 7220215976Sjmallett * State machines in NPEI. For debug. 7221215976Sjmallett */ 7222232812Sjmallettunion cvmx_npei_state3 { 7223215976Sjmallett uint64_t u64; 7224232812Sjmallett struct cvmx_npei_state3_s { 7225232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7226215976Sjmallett uint64_t reserved_56_63 : 8; 7227215976Sjmallett uint64_t psm1 : 15; /**< PSM1 State */ 7228215976Sjmallett uint64_t psm0 : 15; /**< PSM0 State */ 7229215976Sjmallett uint64_t nsm1 : 13; /**< NSM1 State */ 7230215976Sjmallett uint64_t nsm0 : 13; /**< NSM0 State */ 7231215976Sjmallett#else 7232215976Sjmallett uint64_t nsm0 : 13; 7233215976Sjmallett uint64_t nsm1 : 13; 7234215976Sjmallett uint64_t psm0 : 15; 7235215976Sjmallett uint64_t psm1 : 15; 7236215976Sjmallett uint64_t reserved_56_63 : 8; 7237215976Sjmallett#endif 7238215976Sjmallett } s; 7239215976Sjmallett struct cvmx_npei_state3_s cn52xx; 7240215976Sjmallett struct cvmx_npei_state3_s cn52xxp1; 7241215976Sjmallett struct cvmx_npei_state3_s cn56xx; 7242215976Sjmallett struct cvmx_npei_state3_s cn56xxp1; 7243215976Sjmallett}; 7244215976Sjmalletttypedef union cvmx_npei_state3 cvmx_npei_state3_t; 7245215976Sjmallett 7246215976Sjmallett/** 7247215976Sjmallett * cvmx_npei_win_rd_addr 7248215976Sjmallett * 7249215976Sjmallett * NPEI_WIN_RD_ADDR = NPEI Window Read Address Register 7250215976Sjmallett * 7251215976Sjmallett * The address to be read when the NPEI_WIN_RD_DATA register is read. 7252215976Sjmallett */ 7253232812Sjmallettunion cvmx_npei_win_rd_addr { 7254215976Sjmallett uint64_t u64; 7255232812Sjmallett struct cvmx_npei_win_rd_addr_s { 7256232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7257215976Sjmallett uint64_t reserved_51_63 : 13; 7258215976Sjmallett uint64_t ld_cmd : 2; /**< The load command sent wit hthe read. 7259215976Sjmallett 0x0 == Load 8-bytes, 0x1 == Load 4-bytes, 7260215976Sjmallett 0x2 == Load 2-bytes, 0x3 == Load 1-bytes, */ 7261215976Sjmallett uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 7262215976Sjmallett read as '0'. */ 7263215976Sjmallett uint64_t rd_addr : 48; /**< The address to be read from. Whenever the LSB of 7264215976Sjmallett this register is written, the Read Operation will 7265215976Sjmallett take place. 7266215976Sjmallett [47:40] = NCB_ID 7267215976Sjmallett [39:0] = Address 7268215976Sjmallett When [47:43] == NPI & [42:0] == 0 bits [39:0] are: 7269215976Sjmallett [39:32] == x, Not Used 7270215976Sjmallett [31:27] == RSL_ID 7271215976Sjmallett [12:0] == RSL Register Offset */ 7272215976Sjmallett#else 7273215976Sjmallett uint64_t rd_addr : 48; 7274215976Sjmallett uint64_t iobit : 1; 7275215976Sjmallett uint64_t ld_cmd : 2; 7276215976Sjmallett uint64_t reserved_51_63 : 13; 7277215976Sjmallett#endif 7278215976Sjmallett } s; 7279215976Sjmallett struct cvmx_npei_win_rd_addr_s cn52xx; 7280215976Sjmallett struct cvmx_npei_win_rd_addr_s cn52xxp1; 7281215976Sjmallett struct cvmx_npei_win_rd_addr_s cn56xx; 7282215976Sjmallett struct cvmx_npei_win_rd_addr_s cn56xxp1; 7283215976Sjmallett}; 7284215976Sjmalletttypedef union cvmx_npei_win_rd_addr cvmx_npei_win_rd_addr_t; 7285215976Sjmallett 7286215976Sjmallett/** 7287215976Sjmallett * cvmx_npei_win_rd_data 7288215976Sjmallett * 7289215976Sjmallett * NPEI_WIN_RD_DATA = NPEI Window Read Data Register 7290215976Sjmallett * 7291215976Sjmallett * Reading this register causes a window read operation to take place. Address read is taht contained in the NPEI_WIN_RD_ADDR 7292215976Sjmallett * register. 7293215976Sjmallett */ 7294232812Sjmallettunion cvmx_npei_win_rd_data { 7295215976Sjmallett uint64_t u64; 7296232812Sjmallett struct cvmx_npei_win_rd_data_s { 7297232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7298215976Sjmallett uint64_t rd_data : 64; /**< The read data. */ 7299215976Sjmallett#else 7300215976Sjmallett uint64_t rd_data : 64; 7301215976Sjmallett#endif 7302215976Sjmallett } s; 7303215976Sjmallett struct cvmx_npei_win_rd_data_s cn52xx; 7304215976Sjmallett struct cvmx_npei_win_rd_data_s cn52xxp1; 7305215976Sjmallett struct cvmx_npei_win_rd_data_s cn56xx; 7306215976Sjmallett struct cvmx_npei_win_rd_data_s cn56xxp1; 7307215976Sjmallett}; 7308215976Sjmalletttypedef union cvmx_npei_win_rd_data cvmx_npei_win_rd_data_t; 7309215976Sjmallett 7310215976Sjmallett/** 7311215976Sjmallett * cvmx_npei_win_wr_addr 7312215976Sjmallett * 7313215976Sjmallett * NPEI_WIN_WR_ADDR = NPEI Window Write Address Register 7314215976Sjmallett * 7315215976Sjmallett * Contains the address to be writen to when a write operation is started by writing the 7316215976Sjmallett * NPEI_WIN_WR_DATA register (see below). 7317215976Sjmallett * 7318215976Sjmallett * Notes: 7319215976Sjmallett * Even though address bit [2] can be set, it should always be kept to '0'. 7320215976Sjmallett * 7321215976Sjmallett */ 7322232812Sjmallettunion cvmx_npei_win_wr_addr { 7323215976Sjmallett uint64_t u64; 7324232812Sjmallett struct cvmx_npei_win_wr_addr_s { 7325232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7326215976Sjmallett uint64_t reserved_49_63 : 15; 7327215976Sjmallett uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 7328215976Sjmallett read as '0'. */ 7329215976Sjmallett uint64_t wr_addr : 46; /**< The address that will be written to when the 7330215976Sjmallett NPEI_WIN_WR_DATA register is written. 7331215976Sjmallett [47:40] = NCB_ID 7332215976Sjmallett [39:3] = Address 7333215976Sjmallett When [47:43] == NPI & [42:0] == 0 bits [39:0] are: 7334215976Sjmallett [39:32] == x, Not Used 7335215976Sjmallett [31:27] == RSL_ID 7336215976Sjmallett [12:2] == RSL Register Offset 7337215976Sjmallett [1:0] == x, Not Used */ 7338215976Sjmallett uint64_t reserved_0_1 : 2; 7339215976Sjmallett#else 7340215976Sjmallett uint64_t reserved_0_1 : 2; 7341215976Sjmallett uint64_t wr_addr : 46; 7342215976Sjmallett uint64_t iobit : 1; 7343215976Sjmallett uint64_t reserved_49_63 : 15; 7344215976Sjmallett#endif 7345215976Sjmallett } s; 7346215976Sjmallett struct cvmx_npei_win_wr_addr_s cn52xx; 7347215976Sjmallett struct cvmx_npei_win_wr_addr_s cn52xxp1; 7348215976Sjmallett struct cvmx_npei_win_wr_addr_s cn56xx; 7349215976Sjmallett struct cvmx_npei_win_wr_addr_s cn56xxp1; 7350215976Sjmallett}; 7351215976Sjmalletttypedef union cvmx_npei_win_wr_addr cvmx_npei_win_wr_addr_t; 7352215976Sjmallett 7353215976Sjmallett/** 7354215976Sjmallett * cvmx_npei_win_wr_data 7355215976Sjmallett * 7356215976Sjmallett * NPEI_WIN_WR_DATA = NPEI Window Write Data Register 7357215976Sjmallett * 7358215976Sjmallett * Contains the data to write to the address located in the NPEI_WIN_WR_ADDR Register. 7359215976Sjmallett * Writing the least-significant-byte of this register will cause a write operation to take place. 7360215976Sjmallett */ 7361232812Sjmallettunion cvmx_npei_win_wr_data { 7362215976Sjmallett uint64_t u64; 7363232812Sjmallett struct cvmx_npei_win_wr_data_s { 7364232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7365215976Sjmallett uint64_t wr_data : 64; /**< The data to be written. Whenever the LSB of this 7366215976Sjmallett register is written, the Window Write will take 7367215976Sjmallett place. */ 7368215976Sjmallett#else 7369215976Sjmallett uint64_t wr_data : 64; 7370215976Sjmallett#endif 7371215976Sjmallett } s; 7372215976Sjmallett struct cvmx_npei_win_wr_data_s cn52xx; 7373215976Sjmallett struct cvmx_npei_win_wr_data_s cn52xxp1; 7374215976Sjmallett struct cvmx_npei_win_wr_data_s cn56xx; 7375215976Sjmallett struct cvmx_npei_win_wr_data_s cn56xxp1; 7376215976Sjmallett}; 7377215976Sjmalletttypedef union cvmx_npei_win_wr_data cvmx_npei_win_wr_data_t; 7378215976Sjmallett 7379215976Sjmallett/** 7380215976Sjmallett * cvmx_npei_win_wr_mask 7381215976Sjmallett * 7382215976Sjmallett * NPEI_WIN_WR_MASK = NPEI Window Write Mask Register 7383215976Sjmallett * 7384215976Sjmallett * Contains the mask for the data in the NPEI_WIN_WR_DATA Register. 7385215976Sjmallett */ 7386232812Sjmallettunion cvmx_npei_win_wr_mask { 7387215976Sjmallett uint64_t u64; 7388232812Sjmallett struct cvmx_npei_win_wr_mask_s { 7389232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7390215976Sjmallett uint64_t reserved_8_63 : 56; 7391215976Sjmallett uint64_t wr_mask : 8; /**< The data to be written. When a bit is '0' 7392215976Sjmallett the corresponding byte will be written. */ 7393215976Sjmallett#else 7394215976Sjmallett uint64_t wr_mask : 8; 7395215976Sjmallett uint64_t reserved_8_63 : 56; 7396215976Sjmallett#endif 7397215976Sjmallett } s; 7398215976Sjmallett struct cvmx_npei_win_wr_mask_s cn52xx; 7399215976Sjmallett struct cvmx_npei_win_wr_mask_s cn52xxp1; 7400215976Sjmallett struct cvmx_npei_win_wr_mask_s cn56xx; 7401215976Sjmallett struct cvmx_npei_win_wr_mask_s cn56xxp1; 7402215976Sjmallett}; 7403215976Sjmalletttypedef union cvmx_npei_win_wr_mask cvmx_npei_win_wr_mask_t; 7404215976Sjmallett 7405215976Sjmallett/** 7406215976Sjmallett * cvmx_npei_window_ctl 7407215976Sjmallett * 7408215976Sjmallett * NPEI_WINDOW_CTL = NPEI's Window Control 7409215976Sjmallett * 7410215976Sjmallett * The name of this register is misleading. The timeout value is used for BAR0 access from PCIE0 and PCIE1. 7411215976Sjmallett * Any access to the regigisters on the RML will timeout as 0xFFFF clock cycle. At time of timeout the next 7412215976Sjmallett * RML access will start, and interrupt will be set, and in the case of reads no data will be returned. 7413215976Sjmallett * 7414215976Sjmallett * The value of this register should be set to a minimum of 0x200000 to ensure that a timeout to an RML register 7415215976Sjmallett * occurs on the RML 0xFFFF timer before the timeout for a BAR0 access from the PCIE#. 7416215976Sjmallett */ 7417232812Sjmallettunion cvmx_npei_window_ctl { 7418215976Sjmallett uint64_t u64; 7419232812Sjmallett struct cvmx_npei_window_ctl_s { 7420232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 7421215976Sjmallett uint64_t reserved_32_63 : 32; 7422215976Sjmallett uint64_t time : 32; /**< Time to wait in core clocks to wait for a 7423215976Sjmallett BAR0 access to completeon the NCB 7424215976Sjmallett before timing out. A value of 0 will cause no 7425215976Sjmallett timeouts. A minimum value of 0x200000 should be 7426215976Sjmallett used when this register is not set to 0x0. */ 7427215976Sjmallett#else 7428215976Sjmallett uint64_t time : 32; 7429215976Sjmallett uint64_t reserved_32_63 : 32; 7430215976Sjmallett#endif 7431215976Sjmallett } s; 7432215976Sjmallett struct cvmx_npei_window_ctl_s cn52xx; 7433215976Sjmallett struct cvmx_npei_window_ctl_s cn52xxp1; 7434215976Sjmallett struct cvmx_npei_window_ctl_s cn56xx; 7435215976Sjmallett struct cvmx_npei_window_ctl_s cn56xxp1; 7436215976Sjmallett}; 7437215976Sjmalletttypedef union cvmx_npei_window_ctl cvmx_npei_window_ctl_t; 7438215976Sjmallett 7439215976Sjmallett#endif 7440