cvmx-ndf-defs.h revision 256281
193418Sbrian/***********************license start*************** 293418Sbrian * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 393418Sbrian * reserved. 493418Sbrian * 593418Sbrian * 693418Sbrian * Redistribution and use in source and binary forms, with or without 793418Sbrian * modification, are permitted provided that the following conditions are 893418Sbrian * met: 993418Sbrian * 1093418Sbrian * * Redistributions of source code must retain the above copyright 1193418Sbrian * notice, this list of conditions and the following disclaimer. 1293418Sbrian * 1393418Sbrian * * Redistributions in binary form must reproduce the above 1493418Sbrian * copyright notice, this list of conditions and the following 1593418Sbrian * disclaimer in the documentation and/or other materials provided 1693418Sbrian * with the distribution. 1793418Sbrian 1893418Sbrian * * Neither the name of Cavium Inc. nor the names of 1993418Sbrian * its contributors may be used to endorse or promote products 2093418Sbrian * derived from this software without specific prior written 2193418Sbrian * permission. 2293418Sbrian 2393418Sbrian * This Software, including technical data, may be subject to U.S. export control 2493418Sbrian * laws, including the U.S. Export Administration Act and its associated 2593418Sbrian * regulations, and may be subject to export or import regulations in other 2693418Sbrian * countries. 2793418Sbrian 2893418Sbrian * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 2993418Sbrian * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 3093418Sbrian * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 3193418Sbrian * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 3293418Sbrian * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 3393418Sbrian * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 3493418Sbrian * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 3593418Sbrian * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 3693418Sbrian * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 3793418Sbrian * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 3893418Sbrian ***********************license end**************************************/ 3993418Sbrian 4093418Sbrian 4193418Sbrian/** 4293418Sbrian * cvmx-ndf-defs.h 4393418Sbrian * 4493418Sbrian * Configuration and status register (CSR) type definitions for 4593418Sbrian * Octeon ndf. 4693418Sbrian * 4793418Sbrian * This file is auto generated. Do not edit. 4893418Sbrian * 4993418Sbrian * <hr>$Revision$<hr> 5093418Sbrian * 5193418Sbrian */ 5293418Sbrian#ifndef __CVMX_NDF_DEFS_H__ 5393418Sbrian#define __CVMX_NDF_DEFS_H__ 5493418Sbrian 5593418Sbrian#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 5693418Sbrian#define CVMX_NDF_BT_PG_INFO CVMX_NDF_BT_PG_INFO_FUNC() 5793418Sbrianstatic inline uint64_t CVMX_NDF_BT_PG_INFO_FUNC(void) 5893418Sbrian{ 5993418Sbrian if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 6093418Sbrian cvmx_warn("CVMX_NDF_BT_PG_INFO not supported on this chip\n"); 6193418Sbrian return CVMX_ADD_IO_SEG(0x0001070001000018ull); 6293418Sbrian} 6393418Sbrian#else 6493418Sbrian#define CVMX_NDF_BT_PG_INFO (CVMX_ADD_IO_SEG(0x0001070001000018ull)) 6593418Sbrian#endif 6693418Sbrian#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 6793418Sbrian#define CVMX_NDF_CMD CVMX_NDF_CMD_FUNC() 6893418Sbrianstatic inline uint64_t CVMX_NDF_CMD_FUNC(void) 6993418Sbrian{ 7093418Sbrian if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 7193418Sbrian cvmx_warn("CVMX_NDF_CMD not supported on this chip\n"); 7293418Sbrian return CVMX_ADD_IO_SEG(0x0001070001000000ull); 7393418Sbrian} 7493418Sbrian#else 7593418Sbrian#define CVMX_NDF_CMD (CVMX_ADD_IO_SEG(0x0001070001000000ull)) 7693418Sbrian#endif 7793418Sbrian#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 7893418Sbrian#define CVMX_NDF_DRBELL CVMX_NDF_DRBELL_FUNC() 7993418Sbrianstatic inline uint64_t CVMX_NDF_DRBELL_FUNC(void) 8093418Sbrian{ 8193418Sbrian if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 8293418Sbrian cvmx_warn("CVMX_NDF_DRBELL not supported on this chip\n"); 8393418Sbrian return CVMX_ADD_IO_SEG(0x0001070001000030ull); 8493418Sbrian} 8593418Sbrian#else 8693418Sbrian#define CVMX_NDF_DRBELL (CVMX_ADD_IO_SEG(0x0001070001000030ull)) 8793418Sbrian#endif 8893418Sbrian#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 8993418Sbrian#define CVMX_NDF_ECC_CNT CVMX_NDF_ECC_CNT_FUNC() 9093418Sbrianstatic inline uint64_t CVMX_NDF_ECC_CNT_FUNC(void) 9193418Sbrian{ 9293418Sbrian if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 9393418Sbrian cvmx_warn("CVMX_NDF_ECC_CNT not supported on this chip\n"); 94122758Sharti return CVMX_ADD_IO_SEG(0x0001070001000010ull); 9593418Sbrian} 9693418Sbrian#else 9793418Sbrian#define CVMX_NDF_ECC_CNT (CVMX_ADD_IO_SEG(0x0001070001000010ull)) 9893418Sbrian#endif 9993418Sbrian#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 10093418Sbrian#define CVMX_NDF_INT CVMX_NDF_INT_FUNC() 101134789Sbrianstatic inline uint64_t CVMX_NDF_INT_FUNC(void) 10293418Sbrian{ 10393418Sbrian if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 10493418Sbrian cvmx_warn("CVMX_NDF_INT not supported on this chip\n"); 10593418Sbrian return CVMX_ADD_IO_SEG(0x0001070001000020ull); 10693418Sbrian} 10793418Sbrian#else 108134789Sbrian#define CVMX_NDF_INT (CVMX_ADD_IO_SEG(0x0001070001000020ull)) 10993418Sbrian#endif 110122758Sharti#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 11193418Sbrian#define CVMX_NDF_INT_EN CVMX_NDF_INT_EN_FUNC() 112134789Sbrianstatic inline uint64_t CVMX_NDF_INT_EN_FUNC(void) 113134789Sbrian{ 11493418Sbrian if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 11593418Sbrian cvmx_warn("CVMX_NDF_INT_EN not supported on this chip\n"); 11693418Sbrian return CVMX_ADD_IO_SEG(0x0001070001000028ull); 11793418Sbrian} 11893418Sbrian#else 11993418Sbrian#define CVMX_NDF_INT_EN (CVMX_ADD_IO_SEG(0x0001070001000028ull)) 12093418Sbrian#endif 12193418Sbrian#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 12293418Sbrian#define CVMX_NDF_MISC CVMX_NDF_MISC_FUNC() 12393418Sbrianstatic inline uint64_t CVMX_NDF_MISC_FUNC(void) 12493418Sbrian{ 12593418Sbrian if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 12693418Sbrian cvmx_warn("CVMX_NDF_MISC not supported on this chip\n"); 12793418Sbrian return CVMX_ADD_IO_SEG(0x0001070001000008ull); 12893418Sbrian} 12993418Sbrian#else 13093418Sbrian#define CVMX_NDF_MISC (CVMX_ADD_IO_SEG(0x0001070001000008ull)) 13193418Sbrian#endif 13293418Sbrian#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 13393418Sbrian#define CVMX_NDF_ST_REG CVMX_NDF_ST_REG_FUNC() 13493418Sbrianstatic inline uint64_t CVMX_NDF_ST_REG_FUNC(void) 13593418Sbrian{ 13693418Sbrian if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 13793418Sbrian cvmx_warn("CVMX_NDF_ST_REG not supported on this chip\n"); 13893418Sbrian return CVMX_ADD_IO_SEG(0x0001070001000038ull); 13993418Sbrian} 14093418Sbrian#else 14193418Sbrian#define CVMX_NDF_ST_REG (CVMX_ADD_IO_SEG(0x0001070001000038ull)) 14293418Sbrian#endif 14393418Sbrian 14493418Sbrian/** 145134789Sbrian * cvmx_ndf_bt_pg_info 14693418Sbrian * 14793418Sbrian * Notes: 14893418Sbrian * NDF_BT_PG_INFO provides page size and number of column plus row address cycles information. SW writes to this CSR 14993418Sbrian * during boot from Nand Flash. Additionally SW also writes the multiplier value for timing parameters. This value is 15093418Sbrian * used during boot, in the SET_TM_PARAM command. This information is used only by the boot load state machine and is 15193418Sbrian * otherwise a don't care, once boot is disabled. Also, boot dma's do not use this value. 15293418Sbrian * 15393418Sbrian * Bytes per Nand Flash page = 2 ** (SIZE + 1) times 256 bytes. 15493418Sbrian * 512, 1k, 2k, 4k, 8k, 16k, 32k and 64k are legal bytes per page values 15593418Sbrian * 15693418Sbrian * Legal values for ADR_CYC field are 3 through 8. SW CSR writes with a value less than 3 will write a 3 to this 15793418Sbrian * field, and a SW CSR write with a value greater than 8, will write an 8 to this field. 15893418Sbrian * 15993418Sbrian * Like all NDF_... registers, 64-bit operations must be used to access this register 16093418Sbrian */ 16193418Sbrianunion cvmx_ndf_bt_pg_info { 16293418Sbrian uint64_t u64; 16393418Sbrian struct cvmx_ndf_bt_pg_info_s { 16493418Sbrian#ifdef __BIG_ENDIAN_BITFIELD 16593418Sbrian uint64_t reserved_11_63 : 53; 16693418Sbrian uint64_t t_mult : 4; /**< Boot time TIM_MULT[3:0] field of SET__TM_PAR[63:0] 16793418Sbrian command */ 16893418Sbrian uint64_t adr_cyc : 4; /**< # of column address cycles */ 16993418Sbrian uint64_t size : 3; /**< bytes per page in the nand device */ 17093418Sbrian#else 17193418Sbrian uint64_t size : 3; 172122758Sharti uint64_t adr_cyc : 4; 173134789Sbrian uint64_t t_mult : 4; 17493418Sbrian uint64_t reserved_11_63 : 53; 17593418Sbrian#endif 17693418Sbrian } s; 17793418Sbrian struct cvmx_ndf_bt_pg_info_s cn52xx; 17893418Sbrian struct cvmx_ndf_bt_pg_info_s cn63xx; 17993418Sbrian struct cvmx_ndf_bt_pg_info_s cn63xxp1; 18093418Sbrian struct cvmx_ndf_bt_pg_info_s cn66xx; 18193418Sbrian struct cvmx_ndf_bt_pg_info_s cn68xx; 18293418Sbrian struct cvmx_ndf_bt_pg_info_s cn68xxp1; 18393418Sbrian}; 18493418Sbriantypedef union cvmx_ndf_bt_pg_info cvmx_ndf_bt_pg_info_t; 18593418Sbrian 18693418Sbrian/** 18793418Sbrian * cvmx_ndf_cmd 18893418Sbrian * 18993418Sbrian * Notes: 19093418Sbrian * When SW reads this csr, RD_VAL bit in NDF_MISC csr is cleared to 0. SW must always write all 8 bytes whenever it writes 19193418Sbrian * this csr. If there are fewer than 8 bytes left in the command sequence that SW wants the NAND flash controller to execute, it 19293418Sbrian * must insert Idle (WAIT) commands to make up 8 bytes. SW also must ensure there is enough vacancy in the command fifo to accept these 19393418Sbrian * 8 bytes, by first reading the FR_BYT field in the NDF_MISC csr. 19493418Sbrian * 19593418Sbrian * Like all NDF_... registers, 64-bit operations must be used to access this register 19693418Sbrian */ 19793418Sbrianunion cvmx_ndf_cmd { 19893418Sbrian uint64_t u64; 19993418Sbrian struct cvmx_ndf_cmd_s { 20093418Sbrian#ifdef __BIG_ENDIAN_BITFIELD 20193418Sbrian uint64_t nf_cmd : 64; /**< 8 Command Bytes */ 20293418Sbrian#else 20393418Sbrian uint64_t nf_cmd : 64; 20493418Sbrian#endif 20593418Sbrian } s; 20693418Sbrian struct cvmx_ndf_cmd_s cn52xx; 20793418Sbrian struct cvmx_ndf_cmd_s cn63xx; 20893418Sbrian struct cvmx_ndf_cmd_s cn63xxp1; 20993418Sbrian struct cvmx_ndf_cmd_s cn66xx; 21093418Sbrian struct cvmx_ndf_cmd_s cn68xx; 21193418Sbrian struct cvmx_ndf_cmd_s cn68xxp1; 21293418Sbrian}; 21393418Sbriantypedef union cvmx_ndf_cmd cvmx_ndf_cmd_t; 21493418Sbrian 21593418Sbrian/** 21693418Sbrian * cvmx_ndf_drbell 21793418Sbrian * 21893418Sbrian * Notes: 21993418Sbrian * SW csr writes will increment CNT by the signed 8 bit value being written. SW csr reads return the current CNT value. 22093418Sbrian * HW will also modify the value of the CNT field. Everytime HW executes a BUS_ACQ[15:0] command, to arbitrate and win the 22193418Sbrian * flash bus, it decrements the CNT field by 1. If the CNT field is already 0 or negative, HW command execution unit will 22293418Sbrian * stall when it fetches the new BUS_ACQ[15:0] command, from the command fifo. Only when the SW writes to this CSR with a 22393418Sbrian * non-zero data value, can the execution unit come out of the stalled condition, and resume execution. 22493418Sbrian * 22593418Sbrian * The intended use of this doorbell CSR is to control execution of the Nand Flash commands. The NDF execution unit 22693418Sbrian * has to arbitrate for the flash bus, before it can enable a Nand Flash device connected to the Octeon chip, by 22793418Sbrian * asserting the device's chip enable. Therefore SW should first load the command fifo, with a full sequence of 228134789Sbrian * commands to perform a Nand Flash device task. This command sequence will start with a bus acquire command and 22993418Sbrian * the last command in the sequence will be a bus release command. The execution unit will start execution of 230134789Sbrian * the sequence only if the [CNT] field is non-zero when it fetches the bus acquire command, which is the first 23193418Sbrian * command in this sequence. SW can also, load multiple such sequences, each starting with a chip enable command 23293418Sbrian * and ending with a chip disable command, and then write a non-zero data value to this csr to increment the 23393418Sbrian * CNT field by the number of the command sequences, loaded to the command fifo. 23493418Sbrian * 23593418Sbrian * Like all NDF_... registers, 64-bit operations must be used to access this register 236122758Sharti */ 23793418Sbrianunion cvmx_ndf_drbell { 23893418Sbrian uint64_t u64; 23993418Sbrian struct cvmx_ndf_drbell_s { 24093418Sbrian#ifdef __BIG_ENDIAN_BITFIELD 24193418Sbrian uint64_t reserved_8_63 : 56; 24293418Sbrian uint64_t cnt : 8; /**< Doorbell count register, 2's complement 8 bit value */ 24393418Sbrian#else 24493418Sbrian uint64_t cnt : 8; 24593418Sbrian uint64_t reserved_8_63 : 56; 24693418Sbrian#endif 24793418Sbrian } s; 24893418Sbrian struct cvmx_ndf_drbell_s cn52xx; 24993418Sbrian struct cvmx_ndf_drbell_s cn63xx; 25093418Sbrian struct cvmx_ndf_drbell_s cn63xxp1; 25193418Sbrian struct cvmx_ndf_drbell_s cn66xx; 25293418Sbrian struct cvmx_ndf_drbell_s cn68xx; 25393418Sbrian struct cvmx_ndf_drbell_s cn68xxp1; 25493418Sbrian}; 25593418Sbriantypedef union cvmx_ndf_drbell cvmx_ndf_drbell_t; 25693418Sbrian 25793418Sbrian/** 25893418Sbrian * cvmx_ndf_ecc_cnt 25993418Sbrian * 26093418Sbrian * Notes: 26193418Sbrian * XOR_ECC[31:8] = [ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256] xor [ecc_258, ecc_257, ecc_256] 26293418Sbrian * ecc_258, ecc_257 and ecc_256 are bytes stored in Nand Flash and read out during boot 26393418Sbrian * ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256 are generated from data read out from Nand Flash 26493418Sbrian * 26593418Sbrian * Like all NDF_... registers, 64-bit operations must be used to access this register 26693418Sbrian */ 26793418Sbrianunion cvmx_ndf_ecc_cnt { 26893418Sbrian uint64_t u64; 26993418Sbrian struct cvmx_ndf_ecc_cnt_s { 27093418Sbrian#ifdef __BIG_ENDIAN_BITFIELD 27193418Sbrian uint64_t reserved_32_63 : 32; 27293418Sbrian uint64_t xor_ecc : 24; /**< result of XOR of ecc read bytes and ecc genarated 27393418Sbrian bytes. The value pertains to the last 1 bit ecc err */ 27493418Sbrian uint64_t ecc_err : 8; /**< Count = \# of 1 bit errors fixed during boot 27593418Sbrian This count saturates instead of wrapping around. */ 27693418Sbrian#else 27793418Sbrian uint64_t ecc_err : 8; 27893418Sbrian uint64_t xor_ecc : 24; 27993418Sbrian uint64_t reserved_32_63 : 32; 28093418Sbrian#endif 28193418Sbrian } s; 282134789Sbrian struct cvmx_ndf_ecc_cnt_s cn52xx; 28393418Sbrian struct cvmx_ndf_ecc_cnt_s cn63xx; 284196513Sbrian struct cvmx_ndf_ecc_cnt_s cn63xxp1; 28593418Sbrian struct cvmx_ndf_ecc_cnt_s cn66xx; 28693418Sbrian struct cvmx_ndf_ecc_cnt_s cn68xx; 287196513Sbrian struct cvmx_ndf_ecc_cnt_s cn68xxp1; 288196513Sbrian}; 28993418Sbriantypedef union cvmx_ndf_ecc_cnt cvmx_ndf_ecc_cnt_t; 29093418Sbrian 29193418Sbrian/** 29293418Sbrian * cvmx_ndf_int 29393418Sbrian * 29493418Sbrian * Notes: 295196513Sbrian * FULL status is updated when the command fifo becomes full as a result of SW writing a new command to it. 29693418Sbrian * 29793418Sbrian * EMPTY status is updated when the command fifo becomes empty as a result of command execution unit fetching the 29893418Sbrian * last instruction out of the command fifo. 29993418Sbrian * 30093418Sbrian * Like all NDF_... registers, 64-bit operations must be used to access this register 30193418Sbrian */ 30293418Sbrianunion cvmx_ndf_int { 30393418Sbrian uint64_t u64; 30493418Sbrian struct cvmx_ndf_int_s { 30593418Sbrian#ifdef __BIG_ENDIAN_BITFIELD 30693418Sbrian uint64_t reserved_7_63 : 57; 30793418Sbrian uint64_t ovrf : 1; /**< NDF_CMD write when fifo is full. Generally a 30893418Sbrian fatal error. */ 30993418Sbrian uint64_t ecc_mult : 1; /**< Multi bit ECC error detected during boot */ 31093418Sbrian uint64_t ecc_1bit : 1; /**< Single bit ECC error detected and fixed during boot */ 31193418Sbrian uint64_t sm_bad : 1; /**< One of the state machines in a bad state */ 31293418Sbrian uint64_t wdog : 1; /**< Watch Dog timer expired during command execution */ 31393418Sbrian uint64_t full : 1; /**< Command fifo is full */ 31493418Sbrian uint64_t empty : 1; /**< Command fifo is empty */ 31593418Sbrian#else 31693418Sbrian uint64_t empty : 1; 31796582Sbrian uint64_t full : 1; 31893418Sbrian uint64_t wdog : 1; 31993418Sbrian uint64_t sm_bad : 1; 32093418Sbrian uint64_t ecc_1bit : 1; 32193418Sbrian uint64_t ecc_mult : 1; 32293418Sbrian uint64_t ovrf : 1; 323134789Sbrian uint64_t reserved_7_63 : 57; 32493418Sbrian#endif 32593418Sbrian } s; 32693418Sbrian struct cvmx_ndf_int_s cn52xx; 32793418Sbrian struct cvmx_ndf_int_s cn63xx; 32893418Sbrian struct cvmx_ndf_int_s cn63xxp1; 32993418Sbrian struct cvmx_ndf_int_s cn66xx; 33093418Sbrian struct cvmx_ndf_int_s cn68xx; 33193418Sbrian struct cvmx_ndf_int_s cn68xxp1; 33293418Sbrian}; 33393418Sbriantypedef union cvmx_ndf_int cvmx_ndf_int_t; 33493418Sbrian 33593418Sbrian/** 33693418Sbrian * cvmx_ndf_int_en 33793418Sbrian * 33893418Sbrian * Notes: 33993418Sbrian * Like all NDF_... registers, 64-bit operations must be used to access this register 34093418Sbrian * 34193418Sbrian */ 34293418Sbrianunion cvmx_ndf_int_en { 34393418Sbrian uint64_t u64; 34493418Sbrian struct cvmx_ndf_int_en_s { 34593418Sbrian#ifdef __BIG_ENDIAN_BITFIELD 34693418Sbrian uint64_t reserved_7_63 : 57; 34793418Sbrian uint64_t ovrf : 1; /**< Wrote to a full command fifo */ 34893418Sbrian uint64_t ecc_mult : 1; /**< Multi bit ECC error detected during boot */ 34993418Sbrian uint64_t ecc_1bit : 1; /**< Single bit ECC error detected and fixed during boot */ 35093418Sbrian uint64_t sm_bad : 1; /**< One of the state machines in a bad state */ 35193418Sbrian uint64_t wdog : 1; /**< Watch Dog timer expired during command execution */ 35293418Sbrian uint64_t full : 1; /**< Command fifo is full */ 35393418Sbrian uint64_t empty : 1; /**< Command fifo is empty */ 35493418Sbrian#else 35593418Sbrian uint64_t empty : 1; 35693418Sbrian uint64_t full : 1; 35793418Sbrian uint64_t wdog : 1; 35893418Sbrian uint64_t sm_bad : 1; 35993418Sbrian uint64_t ecc_1bit : 1; 36093418Sbrian uint64_t ecc_mult : 1; 36193418Sbrian uint64_t ovrf : 1; 36293418Sbrian uint64_t reserved_7_63 : 57; 36393418Sbrian#endif 36493418Sbrian } s; 36593418Sbrian struct cvmx_ndf_int_en_s cn52xx; 36693418Sbrian struct cvmx_ndf_int_en_s cn63xx; 36793418Sbrian struct cvmx_ndf_int_en_s cn63xxp1; 36893418Sbrian struct cvmx_ndf_int_en_s cn66xx; 36993418Sbrian struct cvmx_ndf_int_en_s cn68xx; 37093418Sbrian struct cvmx_ndf_int_en_s cn68xxp1; 37193418Sbrian}; 37293418Sbriantypedef union cvmx_ndf_int_en cvmx_ndf_int_en_t; 37393418Sbrian 37493418Sbrian/** 37593418Sbrian * cvmx_ndf_misc 37693418Sbrian * 37793418Sbrian * Notes: 37893418Sbrian * NBR_HWM this field specifies the high water mark for the NCB outbound load/store commands receive fifo. 37993418Sbrian * the fifo size is 16 entries. 38093418Sbrian * 38193418Sbrian * WAIT_CNT this field allows glitch filtering of the WAIT_n input to octeon, from Flash Memory. The count 38293418Sbrian * represents number of eclk cycles. 38393418Sbrian * 38493418Sbrian * FR_BYT this field specifies \# of unfilled bytes in the command fifo. Bytes become unfilled as commands 38593418Sbrian * complete execution and exit. (fifo is 256 bytes when BT_DIS=0, and 1536 bytes when BT_DIS=1) 38693418Sbrian * 38793418Sbrian * RD_DONE this W1C bit is set to 1 by HW when it reads the last 8 bytes out of the command fifo, 38893418Sbrian * in response to RD_CMD bit being set to 1 by SW. 38993418Sbrian * 39093418Sbrian * RD_VAL this read only bit is set to 1 by HW when it reads next 8 bytes from command fifo in response 39193418Sbrian * to RD_CMD bit being set to 1. A SW read of NDF_CMD csr clears this bit to 0. 39293418Sbrian * 39393418Sbrian * RD_CMD this R/W bit starts read out from the command fifo, 8 bytes at a time. SW should first read the 39493418Sbrian * RD_VAL bit in this csr to see if next 8 bytes from the command fifo are available in the 39593418Sbrian * NDF_CMD csr. All command fifo reads start and end on an 8 byte boundary. A RD_CMD in the 39693418Sbrian * middle of command execution will cause the execution to freeze until RD_DONE is set to 1. RD_CMD 39793418Sbrian * bit will be cleared on any NDF_CMD csr write by SW. 39893418Sbrian * 39993418Sbrian * BT_DMA this indicates to the NAND flash boot control state machine that boot dma read can begin. 40093418Sbrian * SW should set this bit to 1 after SW has loaded the command fifo. HW sets the bit to 0 40193418Sbrian * when boot dma command execution is complete. If chip enable 0 is not nand flash, this bit is 40293418Sbrian * permanently 1'b0 with SW writes ignored. Whenever BT_DIS=1, this bit will be 0. 40393418Sbrian * 40493418Sbrian * BT_DIS this R/W bit indicates to NAND flash boot control state machine that boot operation has ended. 40593418Sbrian * whenever this bit changes from 0 to a 1, the command fifo is emptied as a side effect. This bit must 40693418Sbrian * never be set when booting from nand flash and region zero is enabled. 40793418Sbrian * 40893418Sbrian * EX_DIS When 1, command execution stops after completing execution of all commands currently in the command 40993418Sbrian * fifo. Once command execution has stopped, and then new commands are loaded into the command fifo, execution 41093418Sbrian * will not resume as long as this bit is 1. When this bit is 0, command execution will resume if command fifo 41193418Sbrian * is not empty. EX_DIS should be set to 1, during boot i.e. when BT_DIS = 0. 41293418Sbrian * 41393418Sbrian * RST_FF reset command fifo to make it empty, any command inflight is not aborted before reseting 41493418Sbrian * the fifo. The fifo comes up empty at the end of power on reset. 41593418Sbrian * 41693418Sbrian * Like all NDF_... registers, 64-bit operations must be used to access this register 41793418Sbrian */ 41893418Sbrianunion cvmx_ndf_misc { 41993418Sbrian uint64_t u64; 42093418Sbrian struct cvmx_ndf_misc_s { 42193418Sbrian#ifdef __BIG_ENDIAN_BITFIELD 42293418Sbrian uint64_t reserved_28_63 : 36; 42393418Sbrian uint64_t mb_dis : 1; /**< Disable multibit error hangs and allow boot loads 42493418Sbrian or boot dma's proceed as if no multi bit errors 42593418Sbrian occured. HW will fix single bit errors as usual */ 42693418Sbrian uint64_t nbr_hwm : 3; /**< Hi Water mark for NBR fifo or load/stores */ 42793418Sbrian uint64_t wait_cnt : 6; /**< WAIT input filter count */ 42893418Sbrian uint64_t fr_byt : 11; /**< Number of unfilled Command fifo bytes */ 42993418Sbrian uint64_t rd_done : 1; /**< This W1C bit is set to 1 by HW when it completes 43093418Sbrian command fifo read out, in response to RD_CMD */ 431134789Sbrian uint64_t rd_val : 1; /**< This RO bit is set to 1 by HW when it reads next 8 43293418Sbrian bytes from Command fifo into the NDF_CMD csr 43393418Sbrian SW reads NDF_CMD csr, HW clears this bit to 0 */ 43493418Sbrian uint64_t rd_cmd : 1; /**< When 1, HW reads out contents of the Command fifo 8 43593418Sbrian bytes at a time into the NDF_CMD csr */ 43693418Sbrian uint64_t bt_dma : 1; /**< When set to 1, boot time dma is enabled */ 43793418Sbrian uint64_t bt_dis : 1; /**< When boot operation is over SW must set to 1 43893418Sbrian causes boot state mchines to sleep */ 43993418Sbrian uint64_t ex_dis : 1; /**< When set to 1, suspends execution of commands at 44093418Sbrian next command in the fifo. */ 44193418Sbrian uint64_t rst_ff : 1; /**< 1=reset command fifo to make it empty, 44293418Sbrian 0=normal operation */ 44393418Sbrian#else 44493418Sbrian uint64_t rst_ff : 1; 44593418Sbrian uint64_t ex_dis : 1; 44693418Sbrian uint64_t bt_dis : 1; 44793418Sbrian uint64_t bt_dma : 1; 44893418Sbrian uint64_t rd_cmd : 1; 44993418Sbrian uint64_t rd_val : 1; 45093418Sbrian uint64_t rd_done : 1; 45193418Sbrian uint64_t fr_byt : 11; 45293418Sbrian uint64_t wait_cnt : 6; 45393418Sbrian uint64_t nbr_hwm : 3; 45493418Sbrian uint64_t mb_dis : 1; 45593418Sbrian uint64_t reserved_28_63 : 36; 45693418Sbrian#endif 45793418Sbrian } s; 45893418Sbrian struct cvmx_ndf_misc_cn52xx { 45993418Sbrian#ifdef __BIG_ENDIAN_BITFIELD 46093418Sbrian uint64_t reserved_27_63 : 37; 46193418Sbrian uint64_t nbr_hwm : 3; /**< Hi Water mark for NBR fifo or load/stores */ 46293418Sbrian uint64_t wait_cnt : 6; /**< WAIT input filter count */ 46393418Sbrian uint64_t fr_byt : 11; /**< Number of unfilled Command fifo bytes */ 46493418Sbrian uint64_t rd_done : 1; /**< This W1C bit is set to 1 by HW when it completes 46593418Sbrian command fifo read out, in response to RD_CMD */ 466122758Sharti uint64_t rd_val : 1; /**< This RO bit is set to 1 by HW when it reads next 8 467122758Sharti bytes from Command fifo into the NDF_CMD csr 468122758Sharti SW reads NDF_CMD csr, HW clears this bit to 0 */ 469122758Sharti uint64_t rd_cmd : 1; /**< When 1, HW reads out contents of the Command fifo 8 470122758Sharti bytes at a time into the NDF_CMD csr */ 47193418Sbrian uint64_t bt_dma : 1; /**< When set to 1, boot time dma is enabled */ 472134789Sbrian uint64_t bt_dis : 1; /**< When boot operation is over SW must set to 1 473134789Sbrian causes boot state mchines to sleep */ 47493418Sbrian uint64_t ex_dis : 1; /**< When set to 1, suspends execution of commands at 47593418Sbrian next command in the fifo. */ 47693418Sbrian uint64_t rst_ff : 1; /**< 1=reset command fifo to make it empty, 47793418Sbrian 0=normal operation */ 47893418Sbrian#else 47993418Sbrian uint64_t rst_ff : 1; 48093418Sbrian uint64_t ex_dis : 1; 48193418Sbrian uint64_t bt_dis : 1; 48293418Sbrian uint64_t bt_dma : 1; 48393418Sbrian uint64_t rd_cmd : 1; 48493418Sbrian uint64_t rd_val : 1; 48593418Sbrian uint64_t rd_done : 1; 48693418Sbrian uint64_t fr_byt : 11; 48793418Sbrian uint64_t wait_cnt : 6; 48893418Sbrian uint64_t nbr_hwm : 3; 48993418Sbrian uint64_t reserved_27_63 : 37; 49093418Sbrian#endif 49193418Sbrian } cn52xx; 49293418Sbrian struct cvmx_ndf_misc_s cn63xx; 49393418Sbrian struct cvmx_ndf_misc_s cn63xxp1; 49493418Sbrian struct cvmx_ndf_misc_s cn66xx; 49593418Sbrian struct cvmx_ndf_misc_s cn68xx; 49693418Sbrian struct cvmx_ndf_misc_s cn68xxp1; 49793418Sbrian}; 49893418Sbriantypedef union cvmx_ndf_misc cvmx_ndf_misc_t; 49993418Sbrian 50093418Sbrian/** 50193418Sbrian * cvmx_ndf_st_reg 50293418Sbrian * 50393418Sbrian * Notes: 50493418Sbrian * This CSR aggregates all state machines used in nand flash controller for debug. 50593418Sbrian * Like all NDF_... registers, 64-bit operations must be used to access this register 50693418Sbrian */ 50793418Sbrianunion cvmx_ndf_st_reg { 50893418Sbrian uint64_t u64; 50993418Sbrian struct cvmx_ndf_st_reg_s { 51093418Sbrian#ifdef __BIG_ENDIAN_BITFIELD 51193418Sbrian uint64_t reserved_16_63 : 48; 51293418Sbrian uint64_t exe_idle : 1; /**< Command Execution status 1=IDLE, 0=Busy 51393418Sbrian 1 means execution of command sequence is complete 51493418Sbrian and command fifo is empty */ 51593418Sbrian uint64_t exe_sm : 4; /**< Command Execution State machine states */ 51693418Sbrian uint64_t bt_sm : 4; /**< Boot load and Boot dma State machine states */ 51793418Sbrian uint64_t rd_ff_bad : 1; /**< CMD fifo read back State machine in bad state */ 51893418Sbrian uint64_t rd_ff : 2; /**< CMD fifo read back State machine states */ 51993418Sbrian uint64_t main_bad : 1; /**< Main State machine in bad state */ 52093418Sbrian uint64_t main_sm : 3; /**< Main State machine states */ 52193418Sbrian#else 52293418Sbrian uint64_t main_sm : 3; 52393418Sbrian uint64_t main_bad : 1; 52493418Sbrian uint64_t rd_ff : 2; 52593418Sbrian uint64_t rd_ff_bad : 1; 52693418Sbrian uint64_t bt_sm : 4; 52793418Sbrian uint64_t exe_sm : 4; 52893418Sbrian uint64_t exe_idle : 1; 52993418Sbrian uint64_t reserved_16_63 : 48; 53093418Sbrian#endif 53193418Sbrian } s; 53293418Sbrian struct cvmx_ndf_st_reg_s cn52xx; 53393418Sbrian struct cvmx_ndf_st_reg_s cn63xx; 53493418Sbrian struct cvmx_ndf_st_reg_s cn63xxp1; 53593418Sbrian struct cvmx_ndf_st_reg_s cn66xx; 53693418Sbrian struct cvmx_ndf_st_reg_s cn68xx; 53793418Sbrian struct cvmx_ndf_st_reg_s cn68xxp1; 53893418Sbrian}; 53993418Sbriantypedef union cvmx_ndf_st_reg cvmx_ndf_st_reg_t; 54093418Sbrian 54193418Sbrian#endif 54293418Sbrian