cvmx-ndf-defs.h revision 232812
1118611Snjl/***********************license start*************** 2118611Snjl * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3118611Snjl * reserved. 4207344Sjkim * 5118611Snjl * 6118611Snjl * Redistribution and use in source and binary forms, with or without 7118611Snjl * modification, are permitted provided that the following conditions are 8217365Sjkim * met: 9217365Sjkim * 10118611Snjl * * Redistributions of source code must retain the above copyright 11118611Snjl * notice, this list of conditions and the following disclaimer. 12217365Sjkim * 13217365Sjkim * * Redistributions in binary form must reproduce the above 14217365Sjkim * copyright notice, this list of conditions and the following 15217365Sjkim * disclaimer in the documentation and/or other materials provided 16217365Sjkim * with the distribution. 17217365Sjkim 18217365Sjkim * * Neither the name of Cavium Inc. nor the names of 19217365Sjkim * its contributors may be used to endorse or promote products 20217365Sjkim * derived from this software without specific prior written 21217365Sjkim * permission. 22217365Sjkim 23217365Sjkim * This Software, including technical data, may be subject to U.S. export control 24217365Sjkim * laws, including the U.S. Export Administration Act and its associated 25217365Sjkim * regulations, and may be subject to export or import regulations in other 26118611Snjl * countries. 27217365Sjkim 28217365Sjkim * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29217365Sjkim * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30118611Snjl * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31217365Sjkim * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32217365Sjkim * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33217365Sjkim * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34217365Sjkim * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35217365Sjkim * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36217365Sjkim * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37217365Sjkim * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38217365Sjkim ***********************license end**************************************/ 39217365Sjkim 40217365Sjkim 41217365Sjkim/** 42217365Sjkim * cvmx-ndf-defs.h 43217365Sjkim * 44118611Snjl * Configuration and status register (CSR) type definitions for 45118611Snjl * Octeon ndf. 46151937Sjkim * 47118611Snjl * This file is auto generated. Do not edit. 48193529Sjkim * 49118611Snjl * <hr>$Revision$<hr> 50118611Snjl * 51118611Snjl */ 52118611Snjl#ifndef __CVMX_NDF_DEFS_H__ 53118611Snjl#define __CVMX_NDF_DEFS_H__ 54118611Snjl 55118611Snjl#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56118611Snjl#define CVMX_NDF_BT_PG_INFO CVMX_NDF_BT_PG_INFO_FUNC() 57207344Sjkimstatic inline uint64_t CVMX_NDF_BT_PG_INFO_FUNC(void) 58207344Sjkim{ 59207344Sjkim if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 60207344Sjkim cvmx_warn("CVMX_NDF_BT_PG_INFO not supported on this chip\n"); 61207344Sjkim return CVMX_ADD_IO_SEG(0x0001070001000018ull); 62207344Sjkim} 63207344Sjkim#else 64207344Sjkim#define CVMX_NDF_BT_PG_INFO (CVMX_ADD_IO_SEG(0x0001070001000018ull)) 65207344Sjkim#endif 66207344Sjkim#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67207344Sjkim#define CVMX_NDF_CMD CVMX_NDF_CMD_FUNC() 68207344Sjkimstatic inline uint64_t CVMX_NDF_CMD_FUNC(void) 69207344Sjkim{ 70213806Sjkim if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 71207344Sjkim cvmx_warn("CVMX_NDF_CMD not supported on this chip\n"); 72207344Sjkim return CVMX_ADD_IO_SEG(0x0001070001000000ull); 73207344Sjkim} 74207344Sjkim#else 75207344Sjkim#define CVMX_NDF_CMD (CVMX_ADD_IO_SEG(0x0001070001000000ull)) 76207344Sjkim#endif 77207344Sjkim#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78207344Sjkim#define CVMX_NDF_DRBELL CVMX_NDF_DRBELL_FUNC() 79207344Sjkimstatic inline uint64_t CVMX_NDF_DRBELL_FUNC(void) 80207344Sjkim{ 81207344Sjkim if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 82207344Sjkim cvmx_warn("CVMX_NDF_DRBELL not supported on this chip\n"); 83207344Sjkim return CVMX_ADD_IO_SEG(0x0001070001000030ull); 84207344Sjkim} 85207344Sjkim#else 86207344Sjkim#define CVMX_NDF_DRBELL (CVMX_ADD_IO_SEG(0x0001070001000030ull)) 87207344Sjkim#endif 88207344Sjkim#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89207344Sjkim#define CVMX_NDF_ECC_CNT CVMX_NDF_ECC_CNT_FUNC() 90213806Sjkimstatic inline uint64_t CVMX_NDF_ECC_CNT_FUNC(void) 91213806Sjkim{ 92207344Sjkim if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 93207344Sjkim cvmx_warn("CVMX_NDF_ECC_CNT not supported on this chip\n"); 94207344Sjkim return CVMX_ADD_IO_SEG(0x0001070001000010ull); 95207344Sjkim} 96207344Sjkim#else 97207344Sjkim#define CVMX_NDF_ECC_CNT (CVMX_ADD_IO_SEG(0x0001070001000010ull)) 98207344Sjkim#endif 99213806Sjkim#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100213806Sjkim#define CVMX_NDF_INT CVMX_NDF_INT_FUNC() 101213806Sjkimstatic inline uint64_t CVMX_NDF_INT_FUNC(void) 102213806Sjkim{ 103213806Sjkim if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 104213806Sjkim cvmx_warn("CVMX_NDF_INT not supported on this chip\n"); 105213806Sjkim return CVMX_ADD_IO_SEG(0x0001070001000020ull); 106213806Sjkim} 107213806Sjkim#else 108213806Sjkim#define CVMX_NDF_INT (CVMX_ADD_IO_SEG(0x0001070001000020ull)) 109213806Sjkim#endif 110213806Sjkim#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111213806Sjkim#define CVMX_NDF_INT_EN CVMX_NDF_INT_EN_FUNC() 112213806Sjkimstatic inline uint64_t CVMX_NDF_INT_EN_FUNC(void) 113213806Sjkim{ 114213806Sjkim if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 115213806Sjkim cvmx_warn("CVMX_NDF_INT_EN not supported on this chip\n"); 116213806Sjkim return CVMX_ADD_IO_SEG(0x0001070001000028ull); 117213806Sjkim} 118213806Sjkim#else 119213806Sjkim#define CVMX_NDF_INT_EN (CVMX_ADD_IO_SEG(0x0001070001000028ull)) 120213806Sjkim#endif 121213806Sjkim#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122213806Sjkim#define CVMX_NDF_MISC CVMX_NDF_MISC_FUNC() 123213806Sjkimstatic inline uint64_t CVMX_NDF_MISC_FUNC(void) 124213806Sjkim{ 125213806Sjkim if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 126213806Sjkim cvmx_warn("CVMX_NDF_MISC not supported on this chip\n"); 127207344Sjkim return CVMX_ADD_IO_SEG(0x0001070001000008ull); 128207344Sjkim} 129207344Sjkim#else 130207344Sjkim#define CVMX_NDF_MISC (CVMX_ADD_IO_SEG(0x0001070001000008ull)) 131207344Sjkim#endif 132207344Sjkim#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133207344Sjkim#define CVMX_NDF_ST_REG CVMX_NDF_ST_REG_FUNC() 134207344Sjkimstatic inline uint64_t CVMX_NDF_ST_REG_FUNC(void) 135207344Sjkim{ 136207344Sjkim if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))) 137207344Sjkim cvmx_warn("CVMX_NDF_ST_REG not supported on this chip\n"); 138207344Sjkim return CVMX_ADD_IO_SEG(0x0001070001000038ull); 139207344Sjkim} 140207344Sjkim#else 141207344Sjkim#define CVMX_NDF_ST_REG (CVMX_ADD_IO_SEG(0x0001070001000038ull)) 142207344Sjkim#endif 143207344Sjkim 144207344Sjkim/** 145207344Sjkim * cvmx_ndf_bt_pg_info 146207344Sjkim * 147207344Sjkim * Notes: 148207344Sjkim * NDF_BT_PG_INFO provides page size and number of column plus row address cycles information. SW writes to this CSR 149207344Sjkim * during boot from Nand Flash. Additionally SW also writes the multiplier value for timing parameters. This value is 150207344Sjkim * used during boot, in the SET_TM_PARAM command. This information is used only by the boot load state machine and is 151207344Sjkim * otherwise a don't care, once boot is disabled. Also, boot dma's do not use this value. 152207344Sjkim * 153207344Sjkim * Bytes per Nand Flash page = 2 ** (SIZE + 1) times 256 bytes. 154207344Sjkim * 512, 1k, 2k, 4k, 8k, 16k, 32k and 64k are legal bytes per page values 155207344Sjkim * 156207344Sjkim * Legal values for ADR_CYC field are 3 through 8. SW CSR writes with a value less than 3 will write a 3 to this 157207344Sjkim * field, and a SW CSR write with a value greater than 8, will write an 8 to this field. 158207344Sjkim * 159207344Sjkim * Like all NDF_... registers, 64-bit operations must be used to access this register 160207344Sjkim */ 161207344Sjkimunion cvmx_ndf_bt_pg_info { 162207344Sjkim uint64_t u64; 163207344Sjkim struct cvmx_ndf_bt_pg_info_s { 164207344Sjkim#ifdef __BIG_ENDIAN_BITFIELD 165207344Sjkim uint64_t reserved_11_63 : 53; 166207344Sjkim uint64_t t_mult : 4; /**< Boot time TIM_MULT[3:0] field of SET__TM_PAR[63:0] 167207344Sjkim command */ 168207344Sjkim uint64_t adr_cyc : 4; /**< # of column address cycles */ 169207344Sjkim uint64_t size : 3; /**< bytes per page in the nand device */ 170207344Sjkim#else 171207344Sjkim uint64_t size : 3; 172207344Sjkim uint64_t adr_cyc : 4; 173207344Sjkim uint64_t t_mult : 4; 174207344Sjkim uint64_t reserved_11_63 : 53; 175207344Sjkim#endif 176207344Sjkim } s; 177207344Sjkim struct cvmx_ndf_bt_pg_info_s cn52xx; 178207344Sjkim struct cvmx_ndf_bt_pg_info_s cn63xx; 179207344Sjkim struct cvmx_ndf_bt_pg_info_s cn63xxp1; 180207344Sjkim struct cvmx_ndf_bt_pg_info_s cn66xx; 181207344Sjkim struct cvmx_ndf_bt_pg_info_s cn68xx; 182207344Sjkim struct cvmx_ndf_bt_pg_info_s cn68xxp1; 183207344Sjkim}; 184207344Sjkimtypedef union cvmx_ndf_bt_pg_info cvmx_ndf_bt_pg_info_t; 185207344Sjkim 186207344Sjkim/** 187207344Sjkim * cvmx_ndf_cmd 188207344Sjkim * 189207344Sjkim * Notes: 190207344Sjkim * When SW reads this csr, RD_VAL bit in NDF_MISC csr is cleared to 0. SW must always write all 8 bytes whenever it writes 191213806Sjkim * this csr. If there are fewer than 8 bytes left in the command sequence that SW wants the NAND flash controller to execute, it 192207344Sjkim * must insert Idle (WAIT) commands to make up 8 bytes. SW also must ensure there is enough vacancy in the command fifo to accept these 193207344Sjkim * 8 bytes, by first reading the FR_BYT field in the NDF_MISC csr. 194207344Sjkim * 195207344Sjkim * Like all NDF_... registers, 64-bit operations must be used to access this register 196207344Sjkim */ 197207344Sjkimunion cvmx_ndf_cmd { 198207344Sjkim uint64_t u64; 199207344Sjkim struct cvmx_ndf_cmd_s { 200207344Sjkim#ifdef __BIG_ENDIAN_BITFIELD 201207344Sjkim uint64_t nf_cmd : 64; /**< 8 Command Bytes */ 202207344Sjkim#else 203207344Sjkim uint64_t nf_cmd : 64; 204207344Sjkim#endif 205207344Sjkim } s; 206207344Sjkim struct cvmx_ndf_cmd_s cn52xx; 207207344Sjkim struct cvmx_ndf_cmd_s cn63xx; 208207344Sjkim struct cvmx_ndf_cmd_s cn63xxp1; 209207344Sjkim struct cvmx_ndf_cmd_s cn66xx; 210207344Sjkim struct cvmx_ndf_cmd_s cn68xx; 211207344Sjkim struct cvmx_ndf_cmd_s cn68xxp1; 212207344Sjkim}; 213207344Sjkimtypedef union cvmx_ndf_cmd cvmx_ndf_cmd_t; 214207344Sjkim 215207344Sjkim/** 216207344Sjkim * cvmx_ndf_drbell 217207344Sjkim * 218207344Sjkim * Notes: 219207344Sjkim * SW csr writes will increment CNT by the signed 8 bit value being written. SW csr reads return the current CNT value. 220207344Sjkim * HW will also modify the value of the CNT field. Everytime HW executes a BUS_ACQ[15:0] command, to arbitrate and win the 221213806Sjkim * flash bus, it decrements the CNT field by 1. If the CNT field is already 0 or negative, HW command execution unit will 222213806Sjkim * stall when it fetches the new BUS_ACQ[15:0] command, from the command fifo. Only when the SW writes to this CSR with a 223207344Sjkim * non-zero data value, can the execution unit come out of the stalled condition, and resume execution. 224207344Sjkim * 225207344Sjkim * The intended use of this doorbell CSR is to control execution of the Nand Flash commands. The NDF execution unit 226207344Sjkim * has to arbitrate for the flash bus, before it can enable a Nand Flash device connected to the Octeon chip, by 227207344Sjkim * asserting the device's chip enable. Therefore SW should first load the command fifo, with a full sequence of 228207344Sjkim * commands to perform a Nand Flash device task. This command sequence will start with a bus acquire command and 229207344Sjkim * the last command in the sequence will be a bus release command. The execution unit will start execution of 230213806Sjkim * the sequence only if the [CNT] field is non-zero when it fetches the bus acquire command, which is the first 231213806Sjkim * command in this sequence. SW can also, load multiple such sequences, each starting with a chip enable command 232213806Sjkim * and ending with a chip disable command, and then write a non-zero data value to this csr to increment the 233213806Sjkim * CNT field by the number of the command sequences, loaded to the command fifo. 234213806Sjkim * 235213806Sjkim * Like all NDF_... registers, 64-bit operations must be used to access this register 236213806Sjkim */ 237213806Sjkimunion cvmx_ndf_drbell { 238213806Sjkim uint64_t u64; 239213806Sjkim struct cvmx_ndf_drbell_s { 240213806Sjkim#ifdef __BIG_ENDIAN_BITFIELD 241213806Sjkim uint64_t reserved_8_63 : 56; 242213806Sjkim uint64_t cnt : 8; /**< Doorbell count register, 2's complement 8 bit value */ 243213806Sjkim#else 244213806Sjkim uint64_t cnt : 8; 245213806Sjkim uint64_t reserved_8_63 : 56; 246213806Sjkim#endif 247213806Sjkim } s; 248213806Sjkim struct cvmx_ndf_drbell_s cn52xx; 249213806Sjkim struct cvmx_ndf_drbell_s cn63xx; 250213806Sjkim struct cvmx_ndf_drbell_s cn63xxp1; 251213806Sjkim struct cvmx_ndf_drbell_s cn66xx; 252213806Sjkim struct cvmx_ndf_drbell_s cn68xx; 253213806Sjkim struct cvmx_ndf_drbell_s cn68xxp1; 254213806Sjkim}; 255213806Sjkimtypedef union cvmx_ndf_drbell cvmx_ndf_drbell_t; 256207344Sjkim 257207344Sjkim/** 258207344Sjkim * cvmx_ndf_ecc_cnt 259207344Sjkim * 260207344Sjkim * Notes: 261207344Sjkim * XOR_ECC[31:8] = [ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256] xor [ecc_258, ecc_257, ecc_256] 262207344Sjkim * ecc_258, ecc_257 and ecc_256 are bytes stored in Nand Flash and read out during boot 263207344Sjkim * ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256 are generated from data read out from Nand Flash 264207344Sjkim * 265207344Sjkim * Like all NDF_... registers, 64-bit operations must be used to access this register 266207344Sjkim */ 267207344Sjkimunion cvmx_ndf_ecc_cnt { 268207344Sjkim uint64_t u64; 269207344Sjkim struct cvmx_ndf_ecc_cnt_s { 270207344Sjkim#ifdef __BIG_ENDIAN_BITFIELD 271207344Sjkim uint64_t reserved_32_63 : 32; 272207344Sjkim uint64_t xor_ecc : 24; /**< result of XOR of ecc read bytes and ecc genarated 273207344Sjkim bytes. The value pertains to the last 1 bit ecc err */ 274207344Sjkim uint64_t ecc_err : 8; /**< Count = \# of 1 bit errors fixed during boot 275207344Sjkim This count saturates instead of wrapping around. */ 276207344Sjkim#else 277207344Sjkim uint64_t ecc_err : 8; 278207344Sjkim uint64_t xor_ecc : 24; 279207344Sjkim uint64_t reserved_32_63 : 32; 280207344Sjkim#endif 281207344Sjkim } s; 282207344Sjkim struct cvmx_ndf_ecc_cnt_s cn52xx; 283207344Sjkim struct cvmx_ndf_ecc_cnt_s cn63xx; 284207344Sjkim struct cvmx_ndf_ecc_cnt_s cn63xxp1; 285207344Sjkim struct cvmx_ndf_ecc_cnt_s cn66xx; 286207344Sjkim struct cvmx_ndf_ecc_cnt_s cn68xx; 287207344Sjkim struct cvmx_ndf_ecc_cnt_s cn68xxp1; 288207344Sjkim}; 289207344Sjkimtypedef union cvmx_ndf_ecc_cnt cvmx_ndf_ecc_cnt_t; 290207344Sjkim 291207344Sjkim/** 292207344Sjkim * cvmx_ndf_int 293207344Sjkim * 294207344Sjkim * Notes: 295207344Sjkim * FULL status is updated when the command fifo becomes full as a result of SW writing a new command to it. 296207344Sjkim * 297207344Sjkim * EMPTY status is updated when the command fifo becomes empty as a result of command execution unit fetching the 298207344Sjkim * last instruction out of the command fifo. 299207344Sjkim * 300207344Sjkim * Like all NDF_... registers, 64-bit operations must be used to access this register 301207344Sjkim */ 302207344Sjkimunion cvmx_ndf_int { 303207344Sjkim uint64_t u64; 304207344Sjkim struct cvmx_ndf_int_s { 305207344Sjkim#ifdef __BIG_ENDIAN_BITFIELD 306207344Sjkim uint64_t reserved_7_63 : 57; 307207344Sjkim uint64_t ovrf : 1; /**< NDF_CMD write when fifo is full. Generally a 308207344Sjkim fatal error. */ 309207344Sjkim uint64_t ecc_mult : 1; /**< Multi bit ECC error detected during boot */ 310207344Sjkim uint64_t ecc_1bit : 1; /**< Single bit ECC error detected and fixed during boot */ 311207344Sjkim uint64_t sm_bad : 1; /**< One of the state machines in a bad state */ 312207344Sjkim uint64_t wdog : 1; /**< Watch Dog timer expired during command execution */ 313207344Sjkim uint64_t full : 1; /**< Command fifo is full */ 314207344Sjkim uint64_t empty : 1; /**< Command fifo is empty */ 315207344Sjkim#else 316207344Sjkim uint64_t empty : 1; 317207344Sjkim uint64_t full : 1; 318207344Sjkim uint64_t wdog : 1; 319207344Sjkim uint64_t sm_bad : 1; 320207344Sjkim uint64_t ecc_1bit : 1; 321207344Sjkim uint64_t ecc_mult : 1; 322207344Sjkim uint64_t ovrf : 1; 323207344Sjkim uint64_t reserved_7_63 : 57; 324207344Sjkim#endif 325207344Sjkim } s; 326207344Sjkim struct cvmx_ndf_int_s cn52xx; 327207344Sjkim struct cvmx_ndf_int_s cn63xx; 328207344Sjkim struct cvmx_ndf_int_s cn63xxp1; 329207344Sjkim struct cvmx_ndf_int_s cn66xx; 330207344Sjkim struct cvmx_ndf_int_s cn68xx; 331207344Sjkim struct cvmx_ndf_int_s cn68xxp1; 332207344Sjkim}; 333207344Sjkimtypedef union cvmx_ndf_int cvmx_ndf_int_t; 334207344Sjkim 335207344Sjkim/** 336207344Sjkim * cvmx_ndf_int_en 337207344Sjkim * 338207344Sjkim * Notes: 339207344Sjkim * Like all NDF_... registers, 64-bit operations must be used to access this register 340207344Sjkim * 341207344Sjkim */ 342207344Sjkimunion cvmx_ndf_int_en { 343207344Sjkim uint64_t u64; 344207344Sjkim struct cvmx_ndf_int_en_s { 345207344Sjkim#ifdef __BIG_ENDIAN_BITFIELD 346207344Sjkim uint64_t reserved_7_63 : 57; 347207344Sjkim uint64_t ovrf : 1; /**< Wrote to a full command fifo */ 348207344Sjkim uint64_t ecc_mult : 1; /**< Multi bit ECC error detected during boot */ 349207344Sjkim uint64_t ecc_1bit : 1; /**< Single bit ECC error detected and fixed during boot */ 350207344Sjkim uint64_t sm_bad : 1; /**< One of the state machines in a bad state */ 351207344Sjkim uint64_t wdog : 1; /**< Watch Dog timer expired during command execution */ 352207344Sjkim uint64_t full : 1; /**< Command fifo is full */ 353207344Sjkim uint64_t empty : 1; /**< Command fifo is empty */ 354207344Sjkim#else 355207344Sjkim uint64_t empty : 1; 356207344Sjkim uint64_t full : 1; 357207344Sjkim uint64_t wdog : 1; 358207344Sjkim uint64_t sm_bad : 1; 359207344Sjkim uint64_t ecc_1bit : 1; 360207344Sjkim uint64_t ecc_mult : 1; 361207344Sjkim uint64_t ovrf : 1; 362207344Sjkim uint64_t reserved_7_63 : 57; 363207344Sjkim#endif 364207344Sjkim } s; 365207344Sjkim struct cvmx_ndf_int_en_s cn52xx; 366207344Sjkim struct cvmx_ndf_int_en_s cn63xx; 367207344Sjkim struct cvmx_ndf_int_en_s cn63xxp1; 368207344Sjkim struct cvmx_ndf_int_en_s cn66xx; 369207344Sjkim struct cvmx_ndf_int_en_s cn68xx; 370207344Sjkim struct cvmx_ndf_int_en_s cn68xxp1; 371207344Sjkim}; 372207344Sjkimtypedef union cvmx_ndf_int_en cvmx_ndf_int_en_t; 373207344Sjkim 374207344Sjkim/** 375207344Sjkim * cvmx_ndf_misc 376207344Sjkim * 377207344Sjkim * Notes: 378207344Sjkim * NBR_HWM this field specifies the high water mark for the NCB outbound load/store commands receive fifo. 379207344Sjkim * the fifo size is 16 entries. 380207344Sjkim * 381207344Sjkim * WAIT_CNT this field allows glitch filtering of the WAIT_n input to octeon, from Flash Memory. The count 382207344Sjkim * represents number of eclk cycles. 383207344Sjkim * 384207344Sjkim * FR_BYT this field specifies \# of unfilled bytes in the command fifo. Bytes become unfilled as commands 385207344Sjkim * complete execution and exit. (fifo is 256 bytes when BT_DIS=0, and 1536 bytes when BT_DIS=1) 386207344Sjkim * 387207344Sjkim * RD_DONE this W1C bit is set to 1 by HW when it reads the last 8 bytes out of the command fifo, 388207344Sjkim * in response to RD_CMD bit being set to 1 by SW. 389207344Sjkim * 390207344Sjkim * RD_VAL this read only bit is set to 1 by HW when it reads next 8 bytes from command fifo in response 391207344Sjkim * to RD_CMD bit being set to 1. A SW read of NDF_CMD csr clears this bit to 0. 392207344Sjkim * 393207344Sjkim * RD_CMD this R/W bit starts read out from the command fifo, 8 bytes at a time. SW should first read the 394207344Sjkim * RD_VAL bit in this csr to see if next 8 bytes from the command fifo are available in the 395207344Sjkim * NDF_CMD csr. All command fifo reads start and end on an 8 byte boundary. A RD_CMD in the 396207344Sjkim * middle of command execution will cause the execution to freeze until RD_DONE is set to 1. RD_CMD 397207344Sjkim * bit will be cleared on any NDF_CMD csr write by SW. 398207344Sjkim * 399207344Sjkim * BT_DMA this indicates to the NAND flash boot control state machine that boot dma read can begin. 400207344Sjkim * SW should set this bit to 1 after SW has loaded the command fifo. HW sets the bit to 0 401207344Sjkim * when boot dma command execution is complete. If chip enable 0 is not nand flash, this bit is 402207344Sjkim * permanently 1'b0 with SW writes ignored. Whenever BT_DIS=1, this bit will be 0. 403207344Sjkim * 404207344Sjkim * BT_DIS this R/W bit indicates to NAND flash boot control state machine that boot operation has ended. 405207344Sjkim * whenever this bit changes from 0 to a 1, the command fifo is emptied as a side effect. This bit must 406207344Sjkim * never be set when booting from nand flash and region zero is enabled. 407118611Snjl * 408118611Snjl * EX_DIS When 1, command execution stops after completing execution of all commands currently in the command 409118611Snjl * fifo. Once command execution has stopped, and then new commands are loaded into the command fifo, execution 410118611Snjl * will not resume as long as this bit is 1. When this bit is 0, command execution will resume if command fifo 411118611Snjl * is not empty. EX_DIS should be set to 1, during boot i.e. when BT_DIS = 0. 412118611Snjl * 413118611Snjl * RST_FF reset command fifo to make it empty, any command inflight is not aborted before reseting 414118611Snjl * the fifo. The fifo comes up empty at the end of power on reset. 415118611Snjl * 416118611Snjl * Like all NDF_... registers, 64-bit operations must be used to access this register 417118611Snjl */ 418118611Snjlunion cvmx_ndf_misc { 419118611Snjl uint64_t u64; 420118611Snjl struct cvmx_ndf_misc_s { 421118611Snjl#ifdef __BIG_ENDIAN_BITFIELD 422118611Snjl uint64_t reserved_28_63 : 36; 423118611Snjl uint64_t mb_dis : 1; /**< Disable multibit error hangs and allow boot loads 424118611Snjl or boot dma's proceed as if no multi bit errors 425118611Snjl occured. HW will fix single bit errors as usual */ 426118611Snjl uint64_t nbr_hwm : 3; /**< Hi Water mark for NBR fifo or load/stores */ 427118611Snjl uint64_t wait_cnt : 6; /**< WAIT input filter count */ 428118611Snjl uint64_t fr_byt : 11; /**< Number of unfilled Command fifo bytes */ 429118611Snjl uint64_t rd_done : 1; /**< This W1C bit is set to 1 by HW when it completes 430118611Snjl command fifo read out, in response to RD_CMD */ 431118611Snjl uint64_t rd_val : 1; /**< This RO bit is set to 1 by HW when it reads next 8 432118611Snjl bytes from Command fifo into the NDF_CMD csr 433118611Snjl SW reads NDF_CMD csr, HW clears this bit to 0 */ 434118611Snjl uint64_t rd_cmd : 1; /**< When 1, HW reads out contents of the Command fifo 8 435118611Snjl bytes at a time into the NDF_CMD csr */ 436118611Snjl uint64_t bt_dma : 1; /**< When set to 1, boot time dma is enabled */ 437118611Snjl uint64_t bt_dis : 1; /**< When boot operation is over SW must set to 1 438118611Snjl causes boot state mchines to sleep */ 439118611Snjl uint64_t ex_dis : 1; /**< When set to 1, suspends execution of commands at 440118611Snjl next command in the fifo. */ 441118611Snjl uint64_t rst_ff : 1; /**< 1=reset command fifo to make it empty, 442151937Sjkim 0=normal operation */ 443118611Snjl#else 444118611Snjl uint64_t rst_ff : 1; 445118611Snjl uint64_t ex_dis : 1; 446118611Snjl uint64_t bt_dis : 1; 447118611Snjl uint64_t bt_dma : 1; 448118611Snjl uint64_t rd_cmd : 1; 449118611Snjl uint64_t rd_val : 1; 450118611Snjl uint64_t rd_done : 1; 451118611Snjl uint64_t fr_byt : 11; 452118611Snjl uint64_t wait_cnt : 6; 453118611Snjl uint64_t nbr_hwm : 3; 454118611Snjl uint64_t mb_dis : 1; 455118611Snjl uint64_t reserved_28_63 : 36; 456118611Snjl#endif 457118611Snjl } s; 458118611Snjl struct cvmx_ndf_misc_cn52xx { 459118611Snjl#ifdef __BIG_ENDIAN_BITFIELD 460118611Snjl uint64_t reserved_27_63 : 37; 461118611Snjl uint64_t nbr_hwm : 3; /**< Hi Water mark for NBR fifo or load/stores */ 462118611Snjl uint64_t wait_cnt : 6; /**< WAIT input filter count */ 463118611Snjl uint64_t fr_byt : 11; /**< Number of unfilled Command fifo bytes */ 464118611Snjl uint64_t rd_done : 1; /**< This W1C bit is set to 1 by HW when it completes 465202771Sjkim command fifo read out, in response to RD_CMD */ 466118611Snjl uint64_t rd_val : 1; /**< This RO bit is set to 1 by HW when it reads next 8 467118611Snjl bytes from Command fifo into the NDF_CMD csr 468118611Snjl SW reads NDF_CMD csr, HW clears this bit to 0 */ 469118611Snjl uint64_t rd_cmd : 1; /**< When 1, HW reads out contents of the Command fifo 8 470118611Snjl bytes at a time into the NDF_CMD csr */ 471118611Snjl uint64_t bt_dma : 1; /**< When set to 1, boot time dma is enabled */ 472118611Snjl uint64_t bt_dis : 1; /**< When boot operation is over SW must set to 1 473118611Snjl causes boot state mchines to sleep */ 474151937Sjkim uint64_t ex_dis : 1; /**< When set to 1, suspends execution of commands at 475118611Snjl next command in the fifo. */ 476118611Snjl uint64_t rst_ff : 1; /**< 1=reset command fifo to make it empty, 477118611Snjl 0=normal operation */ 478118611Snjl#else 479118611Snjl uint64_t rst_ff : 1; 480118611Snjl uint64_t ex_dis : 1; 481118611Snjl uint64_t bt_dis : 1; 482118611Snjl uint64_t bt_dma : 1; 483118611Snjl uint64_t rd_cmd : 1; 484118611Snjl uint64_t rd_val : 1; 485118611Snjl uint64_t rd_done : 1; 486118611Snjl uint64_t fr_byt : 11; 487118611Snjl uint64_t wait_cnt : 6; 488118611Snjl uint64_t nbr_hwm : 3; 489118611Snjl uint64_t reserved_27_63 : 37; 490118611Snjl#endif 491118611Snjl } cn52xx; 492118611Snjl struct cvmx_ndf_misc_s cn63xx; 493118611Snjl struct cvmx_ndf_misc_s cn63xxp1; 494118611Snjl struct cvmx_ndf_misc_s cn66xx; 495118611Snjl struct cvmx_ndf_misc_s cn68xx; 496118611Snjl struct cvmx_ndf_misc_s cn68xxp1; 497118611Snjl}; 498118611Snjltypedef union cvmx_ndf_misc cvmx_ndf_misc_t; 499118611Snjl 500118611Snjl/** 501118611Snjl * cvmx_ndf_st_reg 502118611Snjl * 503118611Snjl * Notes: 504118611Snjl * This CSR aggregates all state machines used in nand flash controller for debug. 505151937Sjkim * Like all NDF_... registers, 64-bit operations must be used to access this register 506118611Snjl */ 507118611Snjlunion cvmx_ndf_st_reg { 508118611Snjl uint64_t u64; 509118611Snjl struct cvmx_ndf_st_reg_s { 510118611Snjl#ifdef __BIG_ENDIAN_BITFIELD 511118611Snjl uint64_t reserved_16_63 : 48; 512118611Snjl uint64_t exe_idle : 1; /**< Command Execution status 1=IDLE, 0=Busy 513118611Snjl 1 means execution of command sequence is complete 514118611Snjl and command fifo is empty */ 515118611Snjl uint64_t exe_sm : 4; /**< Command Execution State machine states */ 516118611Snjl uint64_t bt_sm : 4; /**< Boot load and Boot dma State machine states */ 517118611Snjl uint64_t rd_ff_bad : 1; /**< CMD fifo read back State machine in bad state */ 518118611Snjl uint64_t rd_ff : 2; /**< CMD fifo read back State machine states */ 519118611Snjl uint64_t main_bad : 1; /**< Main State machine in bad state */ 520118611Snjl uint64_t main_sm : 3; /**< Main State machine states */ 521118611Snjl#else 522118611Snjl uint64_t main_sm : 3; 523118611Snjl uint64_t main_bad : 1; 524118611Snjl uint64_t rd_ff : 2; 525118611Snjl uint64_t rd_ff_bad : 1; 526118611Snjl uint64_t bt_sm : 4; 527118611Snjl uint64_t exe_sm : 4; 528118611Snjl uint64_t exe_idle : 1; 529118611Snjl uint64_t reserved_16_63 : 48; 530118611Snjl#endif 531118611Snjl } s; 532118611Snjl struct cvmx_ndf_st_reg_s cn52xx; 533118611Snjl struct cvmx_ndf_st_reg_s cn63xx; 534118611Snjl struct cvmx_ndf_st_reg_s cn63xxp1; 535118611Snjl struct cvmx_ndf_st_reg_s cn66xx; 536118611Snjl struct cvmx_ndf_st_reg_s cn68xx; 537118611Snjl struct cvmx_ndf_st_reg_s cn68xxp1; 538118611Snjl}; 539118611Snjltypedef union cvmx_ndf_st_reg cvmx_ndf_st_reg_t; 540118611Snjl 541118611Snjl#endif 542118611Snjl