cvmx-ndf-defs.h revision 215976
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THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-ndf-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon ndf. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_NDF_TYPEDEFS_H__ 53#define __CVMX_NDF_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_NDF_BT_PG_INFO CVMX_NDF_BT_PG_INFO_FUNC() 57static inline uint64_t CVMX_NDF_BT_PG_INFO_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 60 cvmx_warn("CVMX_NDF_BT_PG_INFO not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x0001070001000018ull); 62} 63#else 64#define CVMX_NDF_BT_PG_INFO (CVMX_ADD_IO_SEG(0x0001070001000018ull)) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67#define CVMX_NDF_CMD CVMX_NDF_CMD_FUNC() 68static inline uint64_t CVMX_NDF_CMD_FUNC(void) 69{ 70 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 71 cvmx_warn("CVMX_NDF_CMD not supported on this chip\n"); 72 return CVMX_ADD_IO_SEG(0x0001070001000000ull); 73} 74#else 75#define CVMX_NDF_CMD (CVMX_ADD_IO_SEG(0x0001070001000000ull)) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78#define CVMX_NDF_DRBELL CVMX_NDF_DRBELL_FUNC() 79static inline uint64_t CVMX_NDF_DRBELL_FUNC(void) 80{ 81 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 82 cvmx_warn("CVMX_NDF_DRBELL not supported on this chip\n"); 83 return CVMX_ADD_IO_SEG(0x0001070001000030ull); 84} 85#else 86#define CVMX_NDF_DRBELL (CVMX_ADD_IO_SEG(0x0001070001000030ull)) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89#define CVMX_NDF_ECC_CNT CVMX_NDF_ECC_CNT_FUNC() 90static inline uint64_t CVMX_NDF_ECC_CNT_FUNC(void) 91{ 92 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 93 cvmx_warn("CVMX_NDF_ECC_CNT not supported on this chip\n"); 94 return CVMX_ADD_IO_SEG(0x0001070001000010ull); 95} 96#else 97#define CVMX_NDF_ECC_CNT (CVMX_ADD_IO_SEG(0x0001070001000010ull)) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100#define CVMX_NDF_INT CVMX_NDF_INT_FUNC() 101static inline uint64_t CVMX_NDF_INT_FUNC(void) 102{ 103 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 104 cvmx_warn("CVMX_NDF_INT not supported on this chip\n"); 105 return CVMX_ADD_IO_SEG(0x0001070001000020ull); 106} 107#else 108#define CVMX_NDF_INT (CVMX_ADD_IO_SEG(0x0001070001000020ull)) 109#endif 110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111#define CVMX_NDF_INT_EN CVMX_NDF_INT_EN_FUNC() 112static inline uint64_t CVMX_NDF_INT_EN_FUNC(void) 113{ 114 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 115 cvmx_warn("CVMX_NDF_INT_EN not supported on this chip\n"); 116 return CVMX_ADD_IO_SEG(0x0001070001000028ull); 117} 118#else 119#define CVMX_NDF_INT_EN (CVMX_ADD_IO_SEG(0x0001070001000028ull)) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122#define CVMX_NDF_MISC CVMX_NDF_MISC_FUNC() 123static inline uint64_t CVMX_NDF_MISC_FUNC(void) 124{ 125 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 126 cvmx_warn("CVMX_NDF_MISC not supported on this chip\n"); 127 return CVMX_ADD_IO_SEG(0x0001070001000008ull); 128} 129#else 130#define CVMX_NDF_MISC (CVMX_ADD_IO_SEG(0x0001070001000008ull)) 131#endif 132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133#define CVMX_NDF_ST_REG CVMX_NDF_ST_REG_FUNC() 134static inline uint64_t CVMX_NDF_ST_REG_FUNC(void) 135{ 136 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 137 cvmx_warn("CVMX_NDF_ST_REG not supported on this chip\n"); 138 return CVMX_ADD_IO_SEG(0x0001070001000038ull); 139} 140#else 141#define CVMX_NDF_ST_REG (CVMX_ADD_IO_SEG(0x0001070001000038ull)) 142#endif 143 144/** 145 * cvmx_ndf_bt_pg_info 146 * 147 * Notes: 148 * NDF_BT_PG_INFO provides page size and number of column plus row address cycles information. SW writes to this CSR 149 * during boot from Nand Flash. Additionally SW also writes the multiplier value for timing parameters. This value is 150 * used during boot, in the SET_TM_PARAM command. This information is used only by the boot load state machine and is 151 * otherwise a don't care, once boot is disabled. Also, boot dma's do not use this value. 152 * 153 * Bytes per Nand Flash page = 2 ** (SIZE + 1) times 256 bytes. 154 * 512, 1k, 2k, 4k, 8k, 16k, 32k and 64k are legal bytes per page values 155 * 156 * Legal values for ADR_CYC field are 3 through 8. SW CSR writes with a value less than 3 will write a 3 to this 157 * field, and a SW CSR write with a value greater than 8, will write an 8 to this field. 158 * 159 * Like all NDF_... registers, 64-bit operations must be used to access this register 160 */ 161union cvmx_ndf_bt_pg_info 162{ 163 uint64_t u64; 164 struct cvmx_ndf_bt_pg_info_s 165 { 166#if __BYTE_ORDER == __BIG_ENDIAN 167 uint64_t reserved_11_63 : 53; 168 uint64_t t_mult : 4; /**< Boot time TIM_MULT[3:0] field of SET__TM_PAR[63:0] 169 command */ 170 uint64_t adr_cyc : 4; /**< # of column address cycles */ 171 uint64_t size : 3; /**< bytes per page in the nand device */ 172#else 173 uint64_t size : 3; 174 uint64_t adr_cyc : 4; 175 uint64_t t_mult : 4; 176 uint64_t reserved_11_63 : 53; 177#endif 178 } s; 179 struct cvmx_ndf_bt_pg_info_s cn52xx; 180 struct cvmx_ndf_bt_pg_info_s cn63xx; 181 struct cvmx_ndf_bt_pg_info_s cn63xxp1; 182}; 183typedef union cvmx_ndf_bt_pg_info cvmx_ndf_bt_pg_info_t; 184 185/** 186 * cvmx_ndf_cmd 187 * 188 * Notes: 189 * When SW reads this csr, RD_VAL bit in NDF_MISC csr is cleared to 0. SW must always write all 8 bytes whenever it writes 190 * this csr. If there are fewer than 8 bytes left in the command sequence that SW wants the NAND flash controller to execute, it 191 * must insert Idle (WAIT) commands to make up 8 bytes. SW also must ensure there is enough vacancy in the command fifo to accept these 192 * 8 bytes, by first reading the FR_BYT field in the NDF_MISC csr. 193 * 194 * Like all NDF_... registers, 64-bit operations must be used to access this register 195 */ 196union cvmx_ndf_cmd 197{ 198 uint64_t u64; 199 struct cvmx_ndf_cmd_s 200 { 201#if __BYTE_ORDER == __BIG_ENDIAN 202 uint64_t nf_cmd : 64; /**< 8 Command Bytes */ 203#else 204 uint64_t nf_cmd : 64; 205#endif 206 } s; 207 struct cvmx_ndf_cmd_s cn52xx; 208 struct cvmx_ndf_cmd_s cn63xx; 209 struct cvmx_ndf_cmd_s cn63xxp1; 210}; 211typedef union cvmx_ndf_cmd cvmx_ndf_cmd_t; 212 213/** 214 * cvmx_ndf_drbell 215 * 216 * Notes: 217 * SW csr writes will increment CNT by the signed 8 bit value being written. SW csr reads return the current CNT value. 218 * HW will also modify the value of the CNT field. Everytime HW executes a BUS_ACQ[15:0] command, to arbitrate and win the 219 * flash bus, it decrements the CNT field by 1. If the CNT field is already 0 or negative, HW command execution unit will 220 * stall when it fetches the new BUS_ACQ[15:0] command, from the command fifo. Only when the SW writes to this CSR with a 221 * non-zero data value, can the execution unit come out of the stalled condition, and resume execution. 222 * 223 * The intended use of this doorbell CSR is to control execution of the Nand Flash commands. The NDF execution unit 224 * has to arbitrate for the flash bus, before it can enable a Nand Flash device connected to the Octeon chip, by 225 * asserting the device's chip enable. Therefore SW should first load the command fifo, with a full sequence of 226 * commands to perform a Nand Flash device task. This command sequence will start with a bus acquire command and 227 * the last command in the sequence will be a bus release command. The execution unit will start execution of 228 * the sequence only if the [CNT] field is non-zero when it fetches the bus acquire command, which is the first 229 * command in this sequence. SW can also, load multiple such sequences, each starting with a chip enable command 230 * and ending with a chip disable command, and then write a non-zero data value to this csr to increment the 231 * CNT field by the number of the command sequences, loaded to the command fifo. 232 * 233 * Like all NDF_... registers, 64-bit operations must be used to access this register 234 */ 235union cvmx_ndf_drbell 236{ 237 uint64_t u64; 238 struct cvmx_ndf_drbell_s 239 { 240#if __BYTE_ORDER == __BIG_ENDIAN 241 uint64_t reserved_8_63 : 56; 242 uint64_t cnt : 8; /**< Doorbell count register, 2's complement 8 bit value */ 243#else 244 uint64_t cnt : 8; 245 uint64_t reserved_8_63 : 56; 246#endif 247 } s; 248 struct cvmx_ndf_drbell_s cn52xx; 249 struct cvmx_ndf_drbell_s cn63xx; 250 struct cvmx_ndf_drbell_s cn63xxp1; 251}; 252typedef union cvmx_ndf_drbell cvmx_ndf_drbell_t; 253 254/** 255 * cvmx_ndf_ecc_cnt 256 * 257 * Notes: 258 * XOR_ECC[31:8] = [ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256] xor [ecc_258, ecc_257, ecc_256] 259 * ecc_258, ecc_257 and ecc_256 are bytes stored in Nand Flash and read out during boot 260 * ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256 are generated from data read out from Nand Flash 261 * 262 * Like all NDF_... registers, 64-bit operations must be used to access this register 263 */ 264union cvmx_ndf_ecc_cnt 265{ 266 uint64_t u64; 267 struct cvmx_ndf_ecc_cnt_s 268 { 269#if __BYTE_ORDER == __BIG_ENDIAN 270 uint64_t reserved_32_63 : 32; 271 uint64_t xor_ecc : 24; /**< result of XOR of ecc read bytes and ecc genarated 272 bytes. The value pertains to the last 1 bit ecc err */ 273 uint64_t ecc_err : 8; /**< Count = \# of 1 bit errors fixed during boot 274 This count saturates instead of wrapping around. */ 275#else 276 uint64_t ecc_err : 8; 277 uint64_t xor_ecc : 24; 278 uint64_t reserved_32_63 : 32; 279#endif 280 } s; 281 struct cvmx_ndf_ecc_cnt_s cn52xx; 282 struct cvmx_ndf_ecc_cnt_s cn63xx; 283 struct cvmx_ndf_ecc_cnt_s cn63xxp1; 284}; 285typedef union cvmx_ndf_ecc_cnt cvmx_ndf_ecc_cnt_t; 286 287/** 288 * cvmx_ndf_int 289 * 290 * Notes: 291 * FULL status is updated when the command fifo becomes full as a result of SW writing a new command to it. 292 * 293 * EMPTY status is updated when the command fifo becomes empty as a result of command execution unit fetching the 294 * last instruction out of the command fifo. 295 * 296 * Like all NDF_... registers, 64-bit operations must be used to access this register 297 */ 298union cvmx_ndf_int 299{ 300 uint64_t u64; 301 struct cvmx_ndf_int_s 302 { 303#if __BYTE_ORDER == __BIG_ENDIAN 304 uint64_t reserved_7_63 : 57; 305 uint64_t ovrf : 1; /**< NDF_CMD write when fifo is full. Generally a 306 fatal error. */ 307 uint64_t ecc_mult : 1; /**< Multi bit ECC error detected during boot */ 308 uint64_t ecc_1bit : 1; /**< Single bit ECC error detected and fixed during boot */ 309 uint64_t sm_bad : 1; /**< One of the state machines in a bad state */ 310 uint64_t wdog : 1; /**< Watch Dog timer expired during command execution */ 311 uint64_t full : 1; /**< Command fifo is full */ 312 uint64_t empty : 1; /**< Command fifo is empty */ 313#else 314 uint64_t empty : 1; 315 uint64_t full : 1; 316 uint64_t wdog : 1; 317 uint64_t sm_bad : 1; 318 uint64_t ecc_1bit : 1; 319 uint64_t ecc_mult : 1; 320 uint64_t ovrf : 1; 321 uint64_t reserved_7_63 : 57; 322#endif 323 } s; 324 struct cvmx_ndf_int_s cn52xx; 325 struct cvmx_ndf_int_s cn63xx; 326 struct cvmx_ndf_int_s cn63xxp1; 327}; 328typedef union cvmx_ndf_int cvmx_ndf_int_t; 329 330/** 331 * cvmx_ndf_int_en 332 * 333 * Notes: 334 * Like all NDF_... registers, 64-bit operations must be used to access this register 335 * 336 */ 337union cvmx_ndf_int_en 338{ 339 uint64_t u64; 340 struct cvmx_ndf_int_en_s 341 { 342#if __BYTE_ORDER == __BIG_ENDIAN 343 uint64_t reserved_7_63 : 57; 344 uint64_t ovrf : 1; /**< Wrote to a full command fifo */ 345 uint64_t ecc_mult : 1; /**< Multi bit ECC error detected during boot */ 346 uint64_t ecc_1bit : 1; /**< Single bit ECC error detected and fixed during boot */ 347 uint64_t sm_bad : 1; /**< One of the state machines in a bad state */ 348 uint64_t wdog : 1; /**< Watch Dog timer expired during command execution */ 349 uint64_t full : 1; /**< Command fifo is full */ 350 uint64_t empty : 1; /**< Command fifo is empty */ 351#else 352 uint64_t empty : 1; 353 uint64_t full : 1; 354 uint64_t wdog : 1; 355 uint64_t sm_bad : 1; 356 uint64_t ecc_1bit : 1; 357 uint64_t ecc_mult : 1; 358 uint64_t ovrf : 1; 359 uint64_t reserved_7_63 : 57; 360#endif 361 } s; 362 struct cvmx_ndf_int_en_s cn52xx; 363 struct cvmx_ndf_int_en_s cn63xx; 364 struct cvmx_ndf_int_en_s cn63xxp1; 365}; 366typedef union cvmx_ndf_int_en cvmx_ndf_int_en_t; 367 368/** 369 * cvmx_ndf_misc 370 * 371 * Notes: 372 * NBR_HWM this field specifies the high water mark for the NCB outbound load/store commands receive fifo. 373 * the fifo size is 16 entries. 374 * 375 * WAIT_CNT this field allows glitch filtering of the WAIT_n input to octeon, from Flash Memory. The count 376 * represents number of eclk cycles. 377 * 378 * FR_BYT this field specifies \# of unfilled bytes in the command fifo. Bytes become unfilled as commands 379 * complete execution and exit. (fifo is 256 bytes when BT_DIS=0, and 1536 bytes when BT_DIS=1) 380 * 381 * RD_DONE this W1C bit is set to 1 by HW when it reads the last 8 bytes out of the command fifo, 382 * in response to RD_CMD bit being set to 1 by SW. 383 * 384 * RD_VAL this read only bit is set to 1 by HW when it reads next 8 bytes from command fifo in response 385 * to RD_CMD bit being set to 1. A SW read of NDF_CMD csr clears this bit to 0. 386 * 387 * RD_CMD this R/W bit starts read out from the command fifo, 8 bytes at a time. SW should first read the 388 * RD_VAL bit in this csr to see if next 8 bytes from the command fifo are available in the 389 * NDF_CMD csr. All command fifo reads start and end on an 8 byte boundary. A RD_CMD in the 390 * middle of command execution will cause the execution to freeze until RD_DONE is set to 1. RD_CMD 391 * bit will be cleared on any NDF_CMD csr write by SW. 392 * 393 * BT_DMA this indicates to the NAND flash boot control state machine that boot dma read can begin. 394 * SW should set this bit to 1 after SW has loaded the command fifo. HW sets the bit to 0 395 * when boot dma command execution is complete. If chip enable 0 is not nand flash, this bit is 396 * permanently 1'b0 with SW writes ignored. Whenever BT_DIS=1, this bit will be 0. 397 * 398 * BT_DIS this R/W bit indicates to NAND flash boot control state machine that boot operation has ended. 399 * whenever this bit changes from 0 to a 1, the command fifo is emptied as a side effect. This bit must 400 * never be set when booting from nand flash and region zero is enabled. 401 * 402 * EX_DIS When 1, command execution stops after completing execution of all commands currently in the command 403 * fifo. Once command execution has stopped, and then new commands are loaded into the command fifo, execution 404 * will not resume as long as this bit is 1. When this bit is 0, command execution will resume if command fifo 405 * is not empty. EX_DIS should be set to 1, during boot i.e. when BT_DIS = 0. 406 * 407 * RST_FF reset command fifo to make it empty, any command inflight is not aborted before reseting 408 * the fifo. The fifo comes up empty at the end of power on reset. 409 * 410 * Like all NDF_... registers, 64-bit operations must be used to access this register 411 */ 412union cvmx_ndf_misc 413{ 414 uint64_t u64; 415 struct cvmx_ndf_misc_s 416 { 417#if __BYTE_ORDER == __BIG_ENDIAN 418 uint64_t reserved_28_63 : 36; 419 uint64_t mb_dis : 1; /**< Disable multibit error hangs and allow boot loads 420 or boot dma's proceed as if no multi bit errors 421 occured. HW will fix single bit errors as usual */ 422 uint64_t nbr_hwm : 3; /**< Hi Water mark for NBR fifo or load/stores */ 423 uint64_t wait_cnt : 6; /**< WAIT input filter count */ 424 uint64_t fr_byt : 11; /**< Number of unfilled Command fifo bytes */ 425 uint64_t rd_done : 1; /**< This W1C bit is set to 1 by HW when it completes 426 command fifo read out, in response to RD_CMD */ 427 uint64_t rd_val : 1; /**< This RO bit is set to 1 by HW when it reads next 8 428 bytes from Command fifo into the NDF_CMD csr 429 SW reads NDF_CMD csr, HW clears this bit to 0 */ 430 uint64_t rd_cmd : 1; /**< When 1, HW reads out contents of the Command fifo 8 431 bytes at a time into the NDF_CMD csr */ 432 uint64_t bt_dma : 1; /**< When set to 1, boot time dma is enabled */ 433 uint64_t bt_dis : 1; /**< When boot operation is over SW must set to 1 434 causes boot state mchines to sleep */ 435 uint64_t ex_dis : 1; /**< When set to 1, suspends execution of commands at 436 next command in the fifo. */ 437 uint64_t rst_ff : 1; /**< 1=reset command fifo to make it empty, 438 0=normal operation */ 439#else 440 uint64_t rst_ff : 1; 441 uint64_t ex_dis : 1; 442 uint64_t bt_dis : 1; 443 uint64_t bt_dma : 1; 444 uint64_t rd_cmd : 1; 445 uint64_t rd_val : 1; 446 uint64_t rd_done : 1; 447 uint64_t fr_byt : 11; 448 uint64_t wait_cnt : 6; 449 uint64_t nbr_hwm : 3; 450 uint64_t mb_dis : 1; 451 uint64_t reserved_28_63 : 36; 452#endif 453 } s; 454 struct cvmx_ndf_misc_cn52xx 455 { 456#if __BYTE_ORDER == __BIG_ENDIAN 457 uint64_t reserved_27_63 : 37; 458 uint64_t nbr_hwm : 3; /**< Hi Water mark for NBR fifo or load/stores */ 459 uint64_t wait_cnt : 6; /**< WAIT input filter count */ 460 uint64_t fr_byt : 11; /**< Number of unfilled Command fifo bytes */ 461 uint64_t rd_done : 1; /**< This W1C bit is set to 1 by HW when it completes 462 command fifo read out, in response to RD_CMD */ 463 uint64_t rd_val : 1; /**< This RO bit is set to 1 by HW when it reads next 8 464 bytes from Command fifo into the NDF_CMD csr 465 SW reads NDF_CMD csr, HW clears this bit to 0 */ 466 uint64_t rd_cmd : 1; /**< When 1, HW reads out contents of the Command fifo 8 467 bytes at a time into the NDF_CMD csr */ 468 uint64_t bt_dma : 1; /**< When set to 1, boot time dma is enabled */ 469 uint64_t bt_dis : 1; /**< When boot operation is over SW must set to 1 470 causes boot state mchines to sleep */ 471 uint64_t ex_dis : 1; /**< When set to 1, suspends execution of commands at 472 next command in the fifo. */ 473 uint64_t rst_ff : 1; /**< 1=reset command fifo to make it empty, 474 0=normal operation */ 475#else 476 uint64_t rst_ff : 1; 477 uint64_t ex_dis : 1; 478 uint64_t bt_dis : 1; 479 uint64_t bt_dma : 1; 480 uint64_t rd_cmd : 1; 481 uint64_t rd_val : 1; 482 uint64_t rd_done : 1; 483 uint64_t fr_byt : 11; 484 uint64_t wait_cnt : 6; 485 uint64_t nbr_hwm : 3; 486 uint64_t reserved_27_63 : 37; 487#endif 488 } cn52xx; 489 struct cvmx_ndf_misc_s cn63xx; 490 struct cvmx_ndf_misc_s cn63xxp1; 491}; 492typedef union cvmx_ndf_misc cvmx_ndf_misc_t; 493 494/** 495 * cvmx_ndf_st_reg 496 * 497 * Notes: 498 * This CSR aggregates all state machines used in nand flash controller for debug. 499 * Like all NDF_... registers, 64-bit operations must be used to access this register 500 */ 501union cvmx_ndf_st_reg 502{ 503 uint64_t u64; 504 struct cvmx_ndf_st_reg_s 505 { 506#if __BYTE_ORDER == __BIG_ENDIAN 507 uint64_t reserved_16_63 : 48; 508 uint64_t exe_idle : 1; /**< Command Execution status 1=IDLE, 0=Busy 509 1 means execution of command sequence is complete 510 and command fifo is empty */ 511 uint64_t exe_sm : 4; /**< Command Execution State machine states */ 512 uint64_t bt_sm : 4; /**< Boot load and Boot dma State machine states */ 513 uint64_t rd_ff_bad : 1; /**< CMD fifo read back State machine in bad state */ 514 uint64_t rd_ff : 2; /**< CMD fifo read back State machine states */ 515 uint64_t main_bad : 1; /**< Main State machine in bad state */ 516 uint64_t main_sm : 3; /**< Main State machine states */ 517#else 518 uint64_t main_sm : 3; 519 uint64_t main_bad : 1; 520 uint64_t rd_ff : 2; 521 uint64_t rd_ff_bad : 1; 522 uint64_t bt_sm : 4; 523 uint64_t exe_sm : 4; 524 uint64_t exe_idle : 1; 525 uint64_t reserved_16_63 : 48; 526#endif 527 } s; 528 struct cvmx_ndf_st_reg_s cn52xx; 529 struct cvmx_ndf_st_reg_s cn63xx; 530 struct cvmx_ndf_st_reg_s cn63xxp1; 531}; 532typedef union cvmx_ndf_st_reg cvmx_ndf_st_reg_t; 533 534#endif 535