cvmx-nand.h revision 210286
10SN/A/***********************license start*************** 20SN/A * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 30SN/A * reserved. 40SN/A * 50SN/A * 60SN/A * Redistribution and use in source and binary forms, with or without 70SN/A * modification, are permitted provided that the following conditions are 80SN/A * met: 90SN/A * 100SN/A * * Redistributions of source code must retain the above copyright 110SN/A * notice, this list of conditions and the following disclaimer. 120SN/A * 130SN/A * * Redistributions in binary form must reproduce the above 140SN/A * copyright notice, this list of conditions and the following 150SN/A * disclaimer in the documentation and/or other materials provided 160SN/A * with the distribution. 170SN/A * 180SN/A * * Neither the name of Cavium Networks nor the names of 190SN/A * its contributors may be used to endorse or promote products 200SN/A * derived from this software without specific prior written 210SN/A * permission. 220SN/A * 230SN/A * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 240SN/A * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 250SN/A * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 260SN/A * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 270SN/A * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 280SN/A * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 290SN/A * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 300SN/A * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 310SN/A * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 320SN/A * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 330SN/A * 340SN/A * 350SN/A * For any questions regarding licensing please contact marketing@caviumnetworks.com 360SN/A * 370SN/A ***********************license end**************************************/ 380SN/A 390SN/A 400SN/A 410SN/A 420SN/A 430SN/A 440SN/A/** 450SN/A * @file 460SN/A * 470SN/A * This header defines the CVMX interface to the NAND flash controller. The 480SN/A * basic operations common to all NAND devices are supported by this API, but 490SN/A * many more advanced functions are not support. The low level hardware supports 500SN/A * all types of transactions, but this API only implements the must commonly 510SN/A * used operations. This API performs no locking, so it is the responsibility of 520SN/A * the caller to make sure only one thread of execution is accessing the NAND 530SN/A * controller at a time. Most applications should not use this API directly but 540SN/A * instead use a flash logical layer supplied through a secondary system. For 550SN/A * example, the Linux MTD layer provides a driver for running JFFS2 on top of 560SN/A * NAND flash. 570SN/A * 580SN/A * <h2>Selecting the NAND Chip</h2> 590SN/A * 600SN/A * Octeon's NAND controller assumes a single NAND chip is connected to a boot 610SN/A * bus chip select. Throughout this API, NAND chips are referred to by the chip 620SN/A * select they are connected to (0-7). Chip select 0 will only be a NAND chip 630SN/A * when you are booting from NAND flash. 640SN/A * 650SN/A * <h2>NAND Addressing</h2> 660SN/A * 670SN/A * Various functions in cvmx-nand use addresses to index into NAND flash. All 680SN/A * functions us a uniform address translation scheme to map the passed address 690SN/A * into a NAND block, page, and column. In NAND flash a page represents the 700SN/A * basic unit of reads and writes. Each page contains a power of two number of 710SN/A * bytes and some number of extra out of band (OOB) bytes. A fixed number of 720SN/A * pages fit into each NAND block. Here is the mapping of bits in the cvmx-nand 730SN/A * address to the NAND hardware: 740SN/A * <pre> 750SN/A * 63 56 48 40 32 24 16 8 0 760SN/A * +-------+-------+-------+-------+-------+-------+-------+------+ 770SN/A * | 64 bit cvmx-nand nand_address| 780SN/A * +------------------------------------------------+----+--------+ 790SN/A * | block |page| column | 800SN/A * +-------+-------+-------+-------+-------+--------+----+--------+ 810SN/A * 63 56 48 40 32 24 16 8 0 820SN/A * </pre> 830SN/A * Basically the block, page, and column addresses are packet together. Before 840SN/A * being sent out the NAND pins for addressing the column is padded out to an 850SN/A * even number of bytes. This means that column address are 2 bytes, or 2 860SN/A * address cycles, for page sizes between 512 and 65536 bytes. Page sizes 870SN/A * between 128KB and 16MB would use 3 column address cycles. NAND device 880SN/A * normally either have 32 or 64 pages per block, needing either 5 or 6 address 890SN/A * bits respectively. This means you have 10 bits for block address using 4 900SN/A * address cycles, or 18 for 5 address cycles. Using the cvmx-nand addressing 910SN/A * scheme, it is not possible to directly index the OOB data. Instead you can 920SN/A * access it by reading or writing more data than the normal page size would 930SN/A * allow. Logically the OOB data is appended onto the the page data. For 940SN/A * example, this means that a read of 65 bytes from a column address of 0x7ff 950SN/A * would yield byte 2047 of the page and then 64 bytes of OOB data. 960SN/A * 970SN/A * <hr>$Revision: 35726 $<hr> 980SN/A */ 990SN/A 1000SN/A#ifndef __CVMX_NAND_H__ 1010SN/A#define __CVMX_NAND_H__ 1020SN/A 1030SN/A#ifdef __cplusplus 1040SN/Aextern "C" { 1050SN/A#endif 1060SN/A 1070SN/A 1080SN/A/* Block size for boot ECC */ 1090SN/A#define CVMX_NAND_BOOT_ECC_BLOCK_SIZE (256) 1100SN/A/* ECC bytes for each block */ 1110SN/A#define CVMX_NAND_BOOT_ECC_ECC_SIZE (8) 1120SN/A 1130SN/A/** 1140SN/A * Flags to be passed to the initialize function 1150SN/A */ 1160SN/Atypedef enum 1170SN/A{ 1180SN/A CVMX_NAND_INITIALIZE_FLAGS_16BIT = 1<<0, 1190SN/A CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE = 1<<1, 1200SN/A CVMX_NAND_INITIALIZE_FLAGS_DEBUG = 1<<15, 1210SN/A} cvmx_nand_initialize_flags_t; 1220SN/A 1230SN/A/** 1240SN/A * Return codes from NAND functions 1250SN/A */ 1260SN/Atypedef enum 1270SN/A{ 1280SN/A CVMX_NAND_SUCCESS = 0, 1290SN/A CVMX_NAND_NO_MEMORY = -1, 1300SN/A CVMX_NAND_BUSY = -2, 1310SN/A CVMX_NAND_INVALID_PARAM = -3, 1320SN/A CVMX_NAND_TIMEOUT = -4, 1330SN/A} cvmx_nand_status_t; 1340SN/A 1350SN/A/** 1360SN/A * NAND NOP command definition 1370SN/A */ 1380SN/Atypedef struct 1390SN/A{ 1400SN/A uint64_t reserved_64_127 : 64; 1410SN/A uint64_t reserved_4_63 : 60; 1420SN/A uint64_t zero : 4; 1430SN/A} cvmx_nand_cmd_nop_t; 1440SN/A 1450SN/A/** 1460SN/A * NAND SET_TM_PAR command definition 1470SN/A */ 1480SN/Atypedef struct 1490SN/A{ 1500SN/A uint64_t reserved_64_127 : 64; 1510SN/A uint64_t tim_par7 : 8; 1520SN/A uint64_t tim_par6 : 8; 1530SN/A uint64_t tim_par5 : 8; 1540SN/A uint64_t tim_par4 : 8; 1550SN/A uint64_t tim_par3 : 8; 1560SN/A uint64_t tim_par2 : 8; 1570SN/A uint64_t tim_par1 : 8; 1580SN/A uint64_t tim_mult : 4; 1590SN/A uint64_t one : 4; 1600SN/A} cvmx_nand_cmd_set_tm_par_t; 1610SN/A 1620SN/A/** 1630SN/A * NAND WAIT command definition 1640SN/A */ 1650SN/Atypedef struct 1660SN/A{ 1670SN/A uint64_t reserved_64_127 : 64; 1680SN/A uint64_t reserved_11_63 : 53; 1690SN/A uint64_t n : 3; 1700SN/A uint64_t reserved_5_7 : 3; 1710SN/A uint64_t r_b : 1; 1720SN/A uint64_t two : 4; 1730SN/A} cvmx_nand_cmd_wait_t; 1740SN/A 1750SN/A/** 1760SN/A * NAND CHIP_EN command definition 1770SN/A */ 1780SN/Atypedef struct 1790SN/A{ 1800SN/A uint64_t reserved_64_127 : 64; 1810SN/A uint64_t reserved_10_63 : 54; 1820SN/A uint64_t width : 2; 1830SN/A uint64_t one : 1; 1840SN/A uint64_t chip : 3; 1850SN/A uint64_t three : 4; 1860SN/A} cvmx_nand_cmd_chip_en_t; 1870SN/A 1880SN/A/** 1890SN/A * NAND CHIP_DIS command definition 1900SN/A */ 1910SN/Atypedef struct 1920SN/A{ 1930SN/A uint64_t reserved_64_127 : 64; 1940SN/A uint64_t reserved_4_63 : 60; 1950SN/A uint64_t three : 4; 1960SN/A} cvmx_nand_cmd_chip_dis_t; 1970SN/A 1980SN/A/** 1990SN/A * NAND CLE command definition 2000SN/A */ 2010SN/Atypedef struct 2020SN/A{ 2030SN/A uint64_t reserved_64_127 : 64; 2040SN/A uint64_t reserved_25_63 : 39; 2050SN/A uint64_t clen3 : 3; 2060SN/A uint64_t clen2 : 3; 2070SN/A uint64_t clen1 : 3; 2080SN/A uint64_t cmd_data : 8; 2090SN/A uint64_t reserved_4_7 : 4; 2100SN/A uint64_t four : 4; 2110SN/A} cvmx_nand_cmd_cle_t; 2120SN/A 2130SN/A/** 2140SN/A * NAND ALE command definition 2150SN/A */ 2160SN/Atypedef struct 2170SN/A{ 2180SN/A uint64_t reserved_96_127 : 32; 2190SN/A uint64_t adr_bytes_h : 32; 2200SN/A uint64_t adr_bytes_l : 32; 2210SN/A uint64_t reserved_28_31 : 4; 2220SN/A uint64_t alen4 : 3; 2230SN/A uint64_t alen3 : 3; 2240SN/A uint64_t alen2 : 3; 2250SN/A uint64_t alen1 : 3; 2260SN/A uint64_t reserved_12_15 : 4; 2270SN/A uint64_t adr_byte_num : 4; 2280SN/A uint64_t reserved_4_7 : 4; 2290SN/A uint64_t five : 4; 2300SN/A} cvmx_nand_cmd_ale_t; 2310SN/A 2320SN/A/** 2330SN/A * NAND WR command definition 2340SN/A */ 2350SN/Atypedef struct 2360SN/A{ 2370SN/A uint64_t reserved_64_127 : 64; 2380SN/A uint64_t reserved_31_63 : 34; 2390SN/A uint64_t wrn2 : 3; 2400SN/A uint64_t wrn1 : 3; 2410SN/A uint64_t reserved_20_24 : 4; 2420SN/A uint64_t data_bytes : 16; 2430SN/A uint64_t eight : 4; 2440SN/A} cvmx_nand_cmd_wr_t; 2450SN/A 2460SN/A/** 2470SN/A * NAND RD command definition 2480SN/A */ 2490SN/Atypedef struct 2500SN/A{ 2510SN/A uint64_t reserved_64_127 : 64; 2520SN/A uint64_t reserved_32_63 : 32; 2530SN/A uint64_t rdn4 : 3; 2540SN/A uint64_t rdn3 : 3; 2550SN/A uint64_t rdn2 : 3; 2560SN/A uint64_t rdn1 : 3; 2570SN/A uint64_t data_bytes : 16; 2580SN/A uint64_t nine : 4; 2590SN/A} cvmx_nand_cmd_rd_t; 2600SN/A 2610SN/A/** 2620SN/A * NAND RD_EDO command definition 2630SN/A */ 2640SN/Atypedef struct 2650SN/A{ 2660SN/A uint64_t reserved_64_127 : 64; 2670SN/A uint64_t reserved_32_63 : 32; 2680SN/A uint64_t rdn4 : 3; 2690SN/A uint64_t rdn3 : 3; 2700SN/A uint64_t rdn2 : 3; 2710SN/A uint64_t rdn1 : 3; 2720SN/A uint64_t data_bytes : 16; 2730SN/A uint64_t ten : 4; 2740SN/A} cvmx_nand_cmd_rd_edo_t; 2750SN/A 2760SN/A/** 2770SN/A * NAND WAIT_STATUS command definition 2780SN/A */ 2790SN/Atypedef struct 2800SN/A{ 2810SN/A uint64_t rdn4 : 3; 2820SN/A uint64_t rdn3 : 3; 2830SN/A uint64_t rdn2 : 3; 2840SN/A uint64_t rdn1 : 3; 2850SN/A uint64_t comp_byte : 8; 2860SN/A uint64_t and_mask : 8; 2870SN/A uint64_t nine : 4; 2880SN/A uint64_t reserved_28_95 : 64; 2890SN/A uint64_t clen4 : 3; 2900SN/A uint64_t clen3 : 3; 2910SN/A uint64_t clen2 : 3; 2920SN/A uint64_t clen1 : 3; 2930SN/A uint64_t data : 8; 2940SN/A uint64_t reserved_4_7 : 4; 2950SN/A uint64_t eleven : 4; 2960SN/A} cvmx_nand_cmd_wait_status_t; 2970SN/A 2980SN/A/** 2990SN/A * NAND WAIT_STATUS_ALE command definition 3000SN/A */ 3010SN/Atypedef struct 3020SN/A{ 3030SN/A uint64_t rdn4 : 3; 3040SN/A uint64_t rdn3 : 3; 3050SN/A uint64_t rdn2 : 3; 3060SN/A uint64_t rdn1 : 3; 3070SN/A uint64_t comp_byte : 8; 3080SN/A uint64_t and_mask : 8; 3090SN/A uint64_t nine : 4; 3100SN/A uint64_t adr_bytes : 32; 3110SN/A uint64_t reserved_60_63 : 4; 3120SN/A uint64_t alen4 : 3; 3130SN/A uint64_t alen3 : 3; 3140SN/A uint64_t alen2 : 3; 3150SN/A uint64_t alen1 : 3; 3160SN/A uint64_t reserved_44_47 : 4; 3170SN/A uint64_t adr_byte_num : 4; 3180SN/A uint64_t five : 4; 3190SN/A uint64_t reserved_25_31 : 7; 3200SN/A uint64_t clen3 : 3; 3210SN/A uint64_t clen2 : 3; 3220SN/A uint64_t clen1 : 3; 3230SN/A uint64_t data : 8; 3240SN/A uint64_t reserved_4_7 : 4; 3250SN/A uint64_t eleven : 4; 3260SN/A} cvmx_nand_cmd_wait_status_ale_t; 3270SN/A 3280SN/A/** 3290SN/A * NAND BUS_ACQ command definition 3300SN/A */ 3310SN/Atypedef struct 3320SN/A{ 3330SN/A uint64_t reserved_64_127 : 64; 3340SN/A uint64_t reserved_8_63 : 56; 3350SN/A uint64_t one : 4; 3360SN/A uint64_t fifteen : 4; 3370SN/A} cvmx_nand_cmd_bus_acq_t; 3380SN/A 3390SN/A/** 3400SN/A * NAND BUS_REL command definition 3410SN/A */ 3420SN/Atypedef struct 3430SN/A{ 3440SN/A uint64_t reserved_64_127 : 64; 3450SN/A uint64_t reserved_8_63 : 56; 3460SN/A uint64_t zero : 4; 3470SN/A uint64_t fifteen : 4; 3480SN/A} cvmx_nand_cmd_bus_rel_t; 3490SN/A 3500SN/A/** 3510SN/A * NAND command union of all possible commands 3520SN/A */ 3530SN/Atypedef union 3540SN/A{ 3550SN/A uint64_t u64[2]; 3560SN/A cvmx_nand_cmd_nop_t nop; 3570SN/A cvmx_nand_cmd_set_tm_par_t set_tm_par; 3580SN/A cvmx_nand_cmd_wait_t wait; 3590SN/A cvmx_nand_cmd_chip_en_t chip_en; 3600SN/A cvmx_nand_cmd_chip_dis_t chip_dis; 3610SN/A cvmx_nand_cmd_cle_t cle; 3620SN/A cvmx_nand_cmd_ale_t ale; 3630SN/A cvmx_nand_cmd_rd_t rd; 3640SN/A cvmx_nand_cmd_rd_edo_t rd_edo; 3650SN/A cvmx_nand_cmd_wr_t wr; 3660SN/A cvmx_nand_cmd_wait_status_t wait_status; 3670SN/A cvmx_nand_cmd_wait_status_ale_t wait_status_ale; 3680SN/A cvmx_nand_cmd_bus_acq_t bus_acq; 3690SN/A cvmx_nand_cmd_bus_rel_t bus_rel; 3700SN/A struct 3710SN/A { 3720SN/A uint64_t reserved_64_127: 64; 3730SN/A uint64_t reserved_4_63 : 60; 3740SN/A uint64_t op_code : 4; 3750SN/A } s; 3760SN/A} cvmx_nand_cmd_t; 3770SN/A 3780SN/A 3790SN/Atypedef struct __attribute__ ((packed)) 3800SN/A{ 3810SN/A char onfi[4]; /**< Bytes 0-3: The ASCII characters 'O', 'N', 'F', 'I' */ 3820SN/A uint16_t revision_number; /**< Bytes 4-5: ONFI revision number 3830SN/A - 2-15 Reserved (0) 3840SN/A - 1 1 = supports ONFI version 1.0 3850SN/A - 0 Reserved (0) */ 3860SN/A uint16_t features; /**< Bytes 6-7: Features supported 3870SN/A - 5-15 Reserved (0) 3880SN/A - 4 1 = supports odd to even page Copyback 3890SN/A - 3 1 = supports interleaved operations 3900SN/A - 2 1 = supports non-sequential page programming 3910SN/A - 1 1 = supports multiple LUN operations 3920SN/A - 0 1 = supports 16-bit data bus width */ 3930SN/A uint16_t optional_commands; /**< Bytes 8-9: Optional commands supported 3940SN/A - 6-15 Reserved (0) 3950SN/A - 5 1 = supports Read Unique ID 3960SN/A - 4 1 = supports Copyback 3970SN/A - 3 1 = supports Read Status Enhanced 3980SN/A - 2 1 = supports Get Features and Set Features 399 - 1 1 = supports Read Cache commands 400 - 0 1 = supports Page Cache Program command */ 401 uint8_t reserved_10_31[22]; /**< Bytes 10-31: Reserved */ 402 403 char manufacturer[12]; /**< Bytes 32-43: Device manufacturer (12 ASCII characters) */ 404 char model[20]; /**< Bytes 40-63: Device model (20 ASCII characters) */ 405 uint8_t jedec_id; /**< Byte 64: JEDEC manufacturer ID */ 406 uint16_t date_code; /**< Byte 65-66: Date code */ 407 uint8_t reserved_67_79[13]; /**< Bytes 67-79: Reserved */ 408 409 uint32_t page_data_bytes; /**< Bytes 80-83: Number of data bytes per page */ 410 uint16_t page_spare_bytes; /**< Bytes 84-85: Number of spare bytes per page */ 411 uint32_t partial_page_data_bytes; /**< Bytes 86-89: Number of data bytes per partial page */ 412 uint16_t partial_page_spare_bytes; /**< Bytes 90-91: Number of spare bytes per partial page */ 413 uint32_t pages_per_block; /**< Bytes 92-95: Number of pages per block */ 414 uint32_t blocks_per_lun; /**< Bytes 96-99: Number of blocks per logical unit (LUN) */ 415 uint8_t number_lun; /**< Byte 100: Number of logical units (LUNs) */ 416 uint8_t address_cycles; /**< Byte 101: Number of address cycles 417 - 4-7 Column address cycles 418 - 0-3 Row address cycles */ 419 uint8_t bits_per_cell; /**< Byte 102: Number of bits per cell */ 420 uint16_t bad_block_per_lun; /**< Bytes 103-104: Bad blocks maximum per LUN */ 421 uint16_t block_endurance; /**< Bytes 105-106: Block endurance */ 422 uint8_t good_blocks; /**< Byte 107: Guaranteed valid blocks at beginning of target */ 423 uint16_t good_block_endurance; /**< Bytes 108-109: Block endurance for guaranteed valid blocks */ 424 uint8_t programs_per_page; /**< Byte 110: Number of programs per page */ 425 uint8_t partial_program_attrib; /**< Byte 111: Partial programming attributes 426 - 5-7 Reserved 427 - 4 1 = partial page layout is partial page data followed by partial page spare 428 - 1-3 Reserved 429 - 0 1 = partial page programming has constraints */ 430 uint8_t bits_ecc; /**< Byte 112: Number of bits ECC correctability */ 431 uint8_t interleaved_address_bits; /**< Byte 113: Number of interleaved address bits 432 - 4-7 Reserved (0) 433 - 0-3 Number of interleaved address bits */ 434 uint8_t interleaved_attrib; /**< Byte 114: Interleaved operation attributes 435 - 4-7 Reserved (0) 436 - 3 Address restrictions for program cache 437 - 2 1 = program cache supported 438 - 1 1 = no block address restrictions 439 - 0 Overlapped / concurrent interleaving support */ 440 uint8_t reserved_115_127[13]; /**< Bytes 115-127: Reserved (0) */ 441 442 uint8_t pin_capacitance; /**< Byte 128: I/O pin capacitance */ 443 uint16_t timing_mode; /**< Byte 129-130: Timing mode support 444 - 6-15 Reserved (0) 445 - 5 1 = supports timing mode 5 446 - 4 1 = supports timing mode 4 447 - 3 1 = supports timing mode 3 448 - 2 1 = supports timing mode 2 449 - 1 1 = supports timing mode 1 450 - 0 1 = supports timing mode 0, shall be 1 */ 451 uint16_t cache_timing_mode; /**< Byte 131-132: Program cache timing mode support 452 - 6-15 Reserved (0) 453 - 5 1 = supports timing mode 5 454 - 4 1 = supports timing mode 4 455 - 3 1 = supports timing mode 3 456 - 2 1 = supports timing mode 2 457 - 1 1 = supports timing mode 1 458 - 0 1 = supports timing mode 0 */ 459 uint16_t t_prog; /**< Byte 133-134: Maximum page program time (us) */ 460 uint16_t t_bers; /**< Byte 135-136: Maximum block erase time (us) */ 461 uint16_t t_r; /**< Byte 137-148: Maximum page read time (us) */ 462 uint16_t t_ccs; /**< Byte 139-140: Minimum change column setup time (ns) */ 463 uint8_t reserved_141_163[23]; /**< Byte 141-163: Reserved (0) */ 464 465 uint16_t vendor_revision; /**< Byte 164-165: Vendor specific Revision number */ 466 uint8_t vendor_specific[88]; /**< Byte 166-253: Vendor specific */ 467 uint16_t crc; /**< Byte 254-255: Integrity CRC */ 468} cvmx_nand_onfi_param_page_t; 469 470 471/** 472 * Called to initialize the NAND controller for use. Note that 473 * you must be running out of L2 or memory and not NAND before 474 * calling this function. 475 * 476 * @param flags Optional initialization flags 477 * @param active_chips 478 * Each bit in this parameter represents a chip select that might 479 * contain NAND flash. Any chip select present in this bitmask may 480 * be connected to NAND. It is normally safe to pass 0xff here and 481 * let the API probe all 8 chip selects. 482 * 483 * @return Zero on success, a negative cvmx_nand_status_t error code on failure 484 */ 485extern cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int active_chips); 486 487 488/** 489 * Call to shutdown the NAND controller after all transactions 490 * are done. In most setups this will never be called. 491 * 492 * @return Zero on success, a negative cvmx_nand_status_t error code on failure 493 */ 494extern cvmx_nand_status_t cvmx_nand_shutdown(void); 495 496 497/** 498 * Returns a bitmask representing the chip selects that are 499 * connected to NAND chips. This can be called after the 500 * initialize to determine the actual number of NAND chips 501 * found. Each bit in the response coresponds to a chip select. 502 * 503 * @return Zero if no NAND chips were found. Otherwise a bit is set for 504 * each chip select (1<<chip). 505 */ 506extern int cvmx_nand_get_active_chips(void); 507 508 509/** 510 * Override the timing parameters for a NAND chip 511 * 512 * @param chip Chip select to override 513 * @param tim_mult 514 * @param tim_par 515 * @param clen 516 * @param alen 517 * @param rdn 518 * @param wrn 519 * 520 * @return Zero on success, a negative cvmx_nand_status_t error code on failure 521 */ 522extern cvmx_nand_status_t cvmx_nand_set_timing(int chip, int tim_mult, int tim_par[7], int clen[4], int alen[4], int rdn[4], int wrn[2]); 523 524 525/** 526 * Submit a command to the NAND command queue. Generally this 527 * will not be used directly. Instead most programs will use the other 528 * higher level NAND functions. 529 * 530 * @param cmd Command to submit 531 * 532 * @return Zero on success, a negative cvmx_nand_status_t error code on failure 533 */ 534extern cvmx_nand_status_t cvmx_nand_submit(cvmx_nand_cmd_t cmd); 535 536/** 537 * Read a page from NAND. If the buffer has room, the out of band 538 * data will be included. 539 * 540 * @param chip Chip select for NAND flash 541 * @param nand_address 542 * Location in NAND to read. See description in file comment 543 * @param buffer_address 544 * Physical address to store the result at 545 * @param buffer_length 546 * Number of bytes to read 547 * 548 * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure 549 */ 550extern int cvmx_nand_page_read(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length); 551 552/** 553 * Write a page to NAND. The buffer must contain the entire page 554 * including the out of band data. 555 * 556 * @param chip Chip select for NAND flash 557 * @param nand_address 558 * Location in NAND to write. See description in file comment 559 * @param buffer_address 560 * Physical address to read the data from 561 * 562 * @return Zero on success, a negative cvmx_nand_status_t error code on failure 563 */ 564extern cvmx_nand_status_t cvmx_nand_page_write(int chip, uint64_t nand_address, uint64_t buffer_address); 565 566/** 567 * Erase a NAND block. A single block contains multiple pages. 568 * 569 * @param chip Chip select for NAND flash 570 * @param nand_address 571 * Location in NAND to erase. See description in file comment 572 * 573 * @return Zero on success, a negative cvmx_nand_status_t error code on failure 574 */ 575extern cvmx_nand_status_t cvmx_nand_block_erase(int chip, uint64_t nand_address); 576 577/** 578 * Read the NAND ID information 579 * 580 * @param chip Chip select for NAND flash 581 * @param nand_address 582 * NAND address to read ID from. Usually this is either 0x0 or 0x20. 583 * @param buffer_address 584 * Physical address to store data in 585 * @param buffer_length 586 * Length of the buffer. Usually this is 4 bytes 587 * 588 * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure 589 */ 590extern int cvmx_nand_read_id(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length); 591 592/** 593 * Read the NAND parameter page 594 * 595 * @param chip Chip select for NAND flash 596 * @param buffer_address 597 * Physical address to store data in 598 * @param buffer_length 599 * Length of the buffer. Usually this is 4 bytes 600 * 601 * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure 602 */ 603extern int cvmx_nand_read_param_page(int chip, uint64_t buffer_address, int buffer_length); 604 605/** 606 * Get the status of the NAND flash 607 * 608 * @param chip Chip select for NAND flash 609 * 610 * @return NAND status or a negative cvmx_nand_status_t error code on failure 611 */ 612extern int cvmx_nand_get_status(int chip); 613 614/** 615 * Get the page size, excluding out of band data. This function 616 * will return zero for chip selects not connected to NAND. 617 * 618 * @param chip Chip select for NAND flash 619 * 620 * @return Page size in bytes or a negative cvmx_nand_status_t error code on failure 621 */ 622extern int cvmx_nand_get_page_size(int chip); 623 624/** 625 * Get the OOB size. 626 * 627 * @param chip Chip select for NAND flash 628 * 629 * @return OOB in bytes or a negative cvmx_nand_status_t error code on failure 630 */ 631extern int cvmx_nand_get_oob_size(int chip); 632 633/** 634 * Get the number of pages per NAND block 635 * 636 * @param chip Chip select for NAND flash 637 * 638 * @return Numboer of pages in each block or a negative cvmx_nand_status_t error code on failure 639 */ 640extern int cvmx_nand_get_pages_per_block(int chip); 641 642/** 643 * Get the number of blocks in the NAND flash 644 * 645 * @param chip Chip select for NAND flash 646 * 647 * @return Number of blocks or a negative cvmx_nand_status_t error code on failure 648 */ 649extern int cvmx_nand_get_blocks(int chip); 650 651/** 652 * Reset the NAND flash 653 * 654 * @param chip Chip select for NAND flash 655 * 656 * @return Zero on success, a negative cvmx_nand_status_t error code on failure 657 */ 658extern cvmx_nand_status_t cvmx_nand_reset(int chip); 659 660/** 661 * This function computes the Octeon specific ECC data used by the NAND boot 662 * feature. 663 * 664 * @param block pointer to 256 bytes of data 665 * @param eccp pointer to where 8 bytes of ECC data will be stored 666 */ 667extern void cvmx_nand_compute_boot_ecc(unsigned char *block, unsigned char *eccp); 668 669 670extern int cvmx_nand_correct_boot_ecc(uint8_t *block); 671#ifdef __cplusplus 672} 673#endif 674 675#endif /* __CVMX_NAND_H__ */ 676