cvmx-mpi-defs.h revision 215976
1107572Sgrehan/***********************license start*************** 2107572Sgrehan * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3107572Sgrehan * reserved. 4107572Sgrehan * 5107572Sgrehan * 6107572Sgrehan * Redistribution and use in source and binary forms, with or without 7107572Sgrehan * modification, are permitted provided that the following conditions are 8107572Sgrehan * met: 9107572Sgrehan * 10107572Sgrehan * * Redistributions of source code must retain the above copyright 11107572Sgrehan * notice, this list of conditions and the following disclaimer. 12107572Sgrehan * 13107572Sgrehan * * Redistributions in binary form must reproduce the above 14107572Sgrehan * copyright notice, this list of conditions and the following 15107572Sgrehan * disclaimer in the documentation and/or other materials provided 16107572Sgrehan * with the distribution. 17107572Sgrehan 18107572Sgrehan * * Neither the name of Cavium Networks nor the names of 19107572Sgrehan * its contributors may be used to endorse or promote products 20107572Sgrehan * derived from this software without specific prior written 21107572Sgrehan * permission. 22107572Sgrehan 23107572Sgrehan * This Software, including technical data, may be subject to U.S. export control 24107572Sgrehan * laws, including the U.S. Export Administration Act and its associated 25107572Sgrehan * regulations, and may be subject to export or import regulations in other 26107572Sgrehan * countries. 27107572Sgrehan 28107572Sgrehan * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29107572Sgrehan * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30107572Sgrehan * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31107572Sgrehan * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32115396Skan * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33107572Sgrehan * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34107572Sgrehan * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35107572Sgrehan * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36107572Sgrehan * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37107572Sgrehan * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38107572Sgrehan ***********************license end**************************************/ 39107572Sgrehan 40107572Sgrehan 41107572Sgrehan/** 42107572Sgrehan * cvmx-mpi-defs.h 43107572Sgrehan * 44107572Sgrehan * Configuration and status register (CSR) type definitions for 45107572Sgrehan * Octeon mpi. 46107572Sgrehan * 47107572Sgrehan * This file is auto generated. Do not edit. 48107572Sgrehan * 49107572Sgrehan * <hr>$Revision$<hr> 50107572Sgrehan * 51233694Skib */ 52233694Skib#ifndef __CVMX_MPI_TYPEDEFS_H__ 53233694Skib#define __CVMX_MPI_TYPEDEFS_H__ 54107572Sgrehan 55115396Skan#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56107572Sgrehan#define CVMX_MPI_CFG CVMX_MPI_CFG_FUNC() 57107572Sgrehanstatic inline uint64_t CVMX_MPI_CFG_FUNC(void) 58107572Sgrehan{ 59107572Sgrehan if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))) 60107572Sgrehan cvmx_warn("CVMX_MPI_CFG not supported on this chip\n"); 61107572Sgrehan return CVMX_ADD_IO_SEG(0x0001070000001000ull); 62107572Sgrehan} 63204211Snwhitehorn#else 64107572Sgrehan#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull)) 65107572Sgrehan#endif 66107572Sgrehan#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67137122Sssouhlalstatic inline uint64_t CVMX_MPI_DATX(unsigned long offset) 68137122Sssouhlal{ 69137122Sssouhlal if (!( 70137122Sssouhlal (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 8))) || 71137122Sssouhlal (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 8))) || 72137122Sssouhlal (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 8))))) 73137122Sssouhlal cvmx_warn("CVMX_MPI_DATX(%lu) is invalid on this chip\n", offset); 74137122Sssouhlal return CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8; 75133133Sdfr} 76133133Sdfr#else 77133133Sdfr#define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8) 78133133Sdfr#endif 79133133Sdfr#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80133133Sdfr#define CVMX_MPI_STS CVMX_MPI_STS_FUNC() 81133133Sdfrstatic inline uint64_t CVMX_MPI_STS_FUNC(void) 82133133Sdfr{ 83133133Sdfr if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))) 84133133Sdfr cvmx_warn("CVMX_MPI_STS not supported on this chip\n"); 85133133Sdfr return CVMX_ADD_IO_SEG(0x0001070000001008ull); 86133133Sdfr} 87133133Sdfr#else 88133133Sdfr#define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull)) 89133133Sdfr#endif 90217851Skib#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 91217851Skib#define CVMX_MPI_TX CVMX_MPI_TX_FUNC() 92217851Skibstatic inline uint64_t CVMX_MPI_TX_FUNC(void) 93107572Sgrehan{ 94 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))) 95 cvmx_warn("CVMX_MPI_TX not supported on this chip\n"); 96 return CVMX_ADD_IO_SEG(0x0001070000001010ull); 97} 98#else 99#define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull)) 100#endif 101 102/** 103 * cvmx_mpi_cfg 104 */ 105union cvmx_mpi_cfg 106{ 107 uint64_t u64; 108 struct cvmx_mpi_cfg_s 109 { 110#if __BYTE_ORDER == __BIG_ENDIAN 111 uint64_t reserved_29_63 : 35; 112 uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV) 113 CLKDIV = Feclk / (2 * Fsclk) */ 114 uint64_t reserved_12_15 : 4; 115 uint64_t cslate : 1; /**< If 0, MPI_CS asserts 1/2 SCLK before transaction 116 1, MPI_CS assert coincident with transaction 117 NOTE: only used if CSENA == 1 */ 118 uint64_t tritx : 1; /**< If 0, MPI_TX pin is driven when slave is not 119 expected to be driving 120 1, MPI_TX pin is tristated when not transmitting 121 NOTE: only used when WIREOR==1 */ 122 uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between 123 commands. */ 124 uint64_t cshi : 1; /**< If 0, CS is low asserted 125 1, CS is high asserted */ 126 uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX 127 1, CS is driven per MPI_TX intruction */ 128 uint64_t int_ena : 1; /**< If 0, polling is required 129 1, MPI engine interrupts X end of transaction */ 130 uint64_t lsbfirst : 1; /**< If 0, shift MSB first 131 1, shift LSB first */ 132 uint64_t wireor : 1; /**< If 0, MPI_TX and MPI_RX are separate wires (SPI) 133 MPI_TX pin is always driven 134 1, MPI_TX/RX is all from MPI_TX pin (MPI) 135 MPI_TX pin is tristated when not transmitting 136 NOTE: if WIREOR==1, MPI_RX pin is not used by the 137 MPI engine */ 138 uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after 139 completion of MPI transaction 140 1, clock never idles, requires CS deassertion 141 assertion between commands */ 142 uint64_t idlelo : 1; /**< If 0, MPI_CLK idles high, 1st transition is hi->lo 143 1, MPI_CLK idles low, 1st transition is lo->hi */ 144 uint64_t enable : 1; /**< If 0, all MPI pins are GPIOs 145 1, MPI_CLK, MPI_CS, and MPI_TX are driven */ 146#else 147 uint64_t enable : 1; 148 uint64_t idlelo : 1; 149 uint64_t clk_cont : 1; 150 uint64_t wireor : 1; 151 uint64_t lsbfirst : 1; 152 uint64_t int_ena : 1; 153 uint64_t csena : 1; 154 uint64_t cshi : 1; 155 uint64_t idleclks : 2; 156 uint64_t tritx : 1; 157 uint64_t cslate : 1; 158 uint64_t reserved_12_15 : 4; 159 uint64_t clkdiv : 13; 160 uint64_t reserved_29_63 : 35; 161#endif 162 } s; 163 struct cvmx_mpi_cfg_s cn30xx; 164 struct cvmx_mpi_cfg_cn31xx 165 { 166#if __BYTE_ORDER == __BIG_ENDIAN 167 uint64_t reserved_29_63 : 35; 168 uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV) 169 CLKDIV = Feclk / (2 * Fsclk) */ 170 uint64_t reserved_11_15 : 5; 171 uint64_t tritx : 1; /**< If 0, MPI_TX pin is driven when slave is not 172 expected to be driving 173 1, MPI_TX pin is tristated when not transmitting 174 NOTE: only used when WIREOR==1 */ 175 uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between 176 commands. */ 177 uint64_t cshi : 1; /**< If 0, CS is low asserted 178 1, CS is high asserted */ 179 uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX 180 1, CS is driven per MPI_TX intruction */ 181 uint64_t int_ena : 1; /**< If 0, polling is required 182 1, MPI engine interrupts X end of transaction */ 183 uint64_t lsbfirst : 1; /**< If 0, shift MSB first 184 1, shift LSB first */ 185 uint64_t wireor : 1; /**< If 0, MPI_TX and MPI_RX are separate wires (SPI) 186 MPI_TX pin is always driven 187 1, MPI_TX/RX is all from MPI_TX pin (MPI) 188 MPI_TX pin is tristated when not transmitting 189 NOTE: if WIREOR==1, MPI_RX pin is not used by the 190 MPI engine */ 191 uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after 192 completion of MPI transaction 193 1, clock never idles, requires CS deassertion 194 assertion between commands */ 195 uint64_t idlelo : 1; /**< If 0, MPI_CLK idles high, 1st transition is hi->lo 196 1, MPI_CLK idles low, 1st transition is lo->hi */ 197 uint64_t enable : 1; /**< If 0, all MPI pins are GPIOs 198 1, MPI_CLK, MPI_CS, and MPI_TX are driven */ 199#else 200 uint64_t enable : 1; 201 uint64_t idlelo : 1; 202 uint64_t clk_cont : 1; 203 uint64_t wireor : 1; 204 uint64_t lsbfirst : 1; 205 uint64_t int_ena : 1; 206 uint64_t csena : 1; 207 uint64_t cshi : 1; 208 uint64_t idleclks : 2; 209 uint64_t tritx : 1; 210 uint64_t reserved_11_15 : 5; 211 uint64_t clkdiv : 13; 212 uint64_t reserved_29_63 : 35; 213#endif 214 } cn31xx; 215 struct cvmx_mpi_cfg_s cn50xx; 216}; 217typedef union cvmx_mpi_cfg cvmx_mpi_cfg_t; 218 219/** 220 * cvmx_mpi_dat# 221 */ 222union cvmx_mpi_datx 223{ 224 uint64_t u64; 225 struct cvmx_mpi_datx_s 226 { 227#if __BYTE_ORDER == __BIG_ENDIAN 228 uint64_t reserved_8_63 : 56; 229 uint64_t data : 8; /**< Data to transmit/received */ 230#else 231 uint64_t data : 8; 232 uint64_t reserved_8_63 : 56; 233#endif 234 } s; 235 struct cvmx_mpi_datx_s cn30xx; 236 struct cvmx_mpi_datx_s cn31xx; 237 struct cvmx_mpi_datx_s cn50xx; 238}; 239typedef union cvmx_mpi_datx cvmx_mpi_datx_t; 240 241/** 242 * cvmx_mpi_sts 243 */ 244union cvmx_mpi_sts 245{ 246 uint64_t u64; 247 struct cvmx_mpi_sts_s 248 { 249#if __BYTE_ORDER == __BIG_ENDIAN 250 uint64_t reserved_13_63 : 51; 251 uint64_t rxnum : 5; /**< Number of bytes written for transaction */ 252 uint64_t reserved_1_7 : 7; 253 uint64_t busy : 1; /**< If 0, no MPI transaction in progress 254 1, MPI engine is processing a transaction */ 255#else 256 uint64_t busy : 1; 257 uint64_t reserved_1_7 : 7; 258 uint64_t rxnum : 5; 259 uint64_t reserved_13_63 : 51; 260#endif 261 } s; 262 struct cvmx_mpi_sts_s cn30xx; 263 struct cvmx_mpi_sts_s cn31xx; 264 struct cvmx_mpi_sts_s cn50xx; 265}; 266typedef union cvmx_mpi_sts cvmx_mpi_sts_t; 267 268/** 269 * cvmx_mpi_tx 270 */ 271union cvmx_mpi_tx 272{ 273 uint64_t u64; 274 struct cvmx_mpi_tx_s 275 { 276#if __BYTE_ORDER == __BIG_ENDIAN 277 uint64_t reserved_17_63 : 47; 278 uint64_t leavecs : 1; /**< If 0, deassert CS after transaction is done 279 1, leave CS asserted after transactrion is done */ 280 uint64_t reserved_13_15 : 3; 281 uint64_t txnum : 5; /**< Number of bytes to transmit */ 282 uint64_t reserved_5_7 : 3; 283 uint64_t totnum : 5; /**< Number of bytes to shift (transmit + receive) */ 284#else 285 uint64_t totnum : 5; 286 uint64_t reserved_5_7 : 3; 287 uint64_t txnum : 5; 288 uint64_t reserved_13_15 : 3; 289 uint64_t leavecs : 1; 290 uint64_t reserved_17_63 : 47; 291#endif 292 } s; 293 struct cvmx_mpi_tx_s cn30xx; 294 struct cvmx_mpi_tx_s cn31xx; 295 struct cvmx_mpi_tx_s cn50xx; 296}; 297typedef union cvmx_mpi_tx cvmx_mpi_tx_t; 298 299#endif 300