1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-mpi-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon mpi. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_MPI_DEFS_H__ 53232812Sjmallett#define __CVMX_MPI_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_MPI_CFG CVMX_MPI_CFG_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_MPI_CFG_FUNC(void) 58215976Sjmallett{ 59232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 60215976Sjmallett cvmx_warn("CVMX_MPI_CFG not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000001000ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallettstatic inline uint64_t CVMX_MPI_DATX(unsigned long offset) 68215976Sjmallett{ 69215976Sjmallett if (!( 70215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 8))) || 71215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 8))) || 72232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 8))) || 73232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 8))) || 74232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 8))) || 75232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 8))))) 76215976Sjmallett cvmx_warn("CVMX_MPI_DATX(%lu) is invalid on this chip\n", offset); 77215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8; 78215976Sjmallett} 79215976Sjmallett#else 80215976Sjmallett#define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8) 81215976Sjmallett#endif 82215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 83215976Sjmallett#define CVMX_MPI_STS CVMX_MPI_STS_FUNC() 84215976Sjmallettstatic inline uint64_t CVMX_MPI_STS_FUNC(void) 85215976Sjmallett{ 86232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 87215976Sjmallett cvmx_warn("CVMX_MPI_STS not supported on this chip\n"); 88215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000001008ull); 89215976Sjmallett} 90215976Sjmallett#else 91215976Sjmallett#define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull)) 92215976Sjmallett#endif 93215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 94215976Sjmallett#define CVMX_MPI_TX CVMX_MPI_TX_FUNC() 95215976Sjmallettstatic inline uint64_t CVMX_MPI_TX_FUNC(void) 96215976Sjmallett{ 97232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 98215976Sjmallett cvmx_warn("CVMX_MPI_TX not supported on this chip\n"); 99215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000001010ull); 100215976Sjmallett} 101215976Sjmallett#else 102215976Sjmallett#define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull)) 103215976Sjmallett#endif 104215976Sjmallett 105215976Sjmallett/** 106215976Sjmallett * cvmx_mpi_cfg 107232812Sjmallett * 108232812Sjmallett * SPI_MPI interface 109232812Sjmallett * 110232812Sjmallett * 111232812Sjmallett * Notes: 112232812Sjmallett * Some of the SPI/MPI pins are muxed with UART pins. 113232812Sjmallett * SPI_CLK : spi clock, dedicated pin 114232812Sjmallett * SPI_DI : spi input, shared with UART0_DCD_N/SPI_DI, enabled when MPI_CFG[ENABLE]=1 115232812Sjmallett * SPI_DO : spi output, mux to UART0_DTR_N/SPI_DO, enabled when MPI_CFG[ENABLE]=1 116232812Sjmallett * SPI_CS0_L : chips select 0, mux to BOOT_CE_N<6>/SPI_CS0_L pin, enabled when MPI_CFG[CSENA0]=1 and MPI_CFG[ENABLE]=1 117232812Sjmallett * SPI_CS1_L : chips select 1, mux to BOOT_CE_N<7>/SPI_CS1_L pin, enabled when MPI_CFG[CSENA1]=1 and MPI_CFG[ENABLE]=1 118215976Sjmallett */ 119232812Sjmallettunion cvmx_mpi_cfg { 120215976Sjmallett uint64_t u64; 121232812Sjmallett struct cvmx_mpi_cfg_s { 122232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 123215976Sjmallett uint64_t reserved_29_63 : 35; 124232812Sjmallett uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) | NS 125232812Sjmallett CLKDIV = Fsclk / (2 * Fspi_clk) */ 126232812Sjmallett uint64_t csena3 : 1; /**< If 0, UART1_RTS_L/SPI_CS3_L pin is UART pin | NS 127232812Sjmallett 1, UART1_RTS_L/SPI_CS3_L pin is SPI pin 128232812Sjmallett SPI_CS3_L drives UART1_RTS_L/SPI_CS3_L */ 129232812Sjmallett uint64_t csena2 : 1; /**< If 0, UART0_RTS_L/SPI_CS2_L pin is UART pin | NS 130232812Sjmallett 1, UART0_RTS_L/SPI_CS2_L pin is SPI pin 131232812Sjmallett SPI_CS2_L drives UART0_RTS_L/SPI_CS2_L */ 132232812Sjmallett uint64_t csena1 : 1; /**< If 0, BOOT_CE_N<7>/SPI_CS1_L pin is BOOT pin | NS 133232812Sjmallett 1, BOOT_CE_N<7>/SPI_CS1_L pin is SPI pin 134232812Sjmallett SPI_CS1_L drives BOOT_CE_N<7>/SPI_CS1_L */ 135232812Sjmallett uint64_t csena0 : 1; /**< If 0, BOOT_CE_N<6>/SPI_CS0_L pin is BOOT pin | NS 136232812Sjmallett 1, BOOT_CE_N<6>/SPI_CS0_L pin is SPI pin 137232812Sjmallett SPI_CS0_L drives BOOT_CE_N<6>/SPI_CS0_L */ 138232812Sjmallett uint64_t cslate : 1; /**< If 0, SPI_CS asserts 1/2 SCLK before transaction | NS 139232812Sjmallett 1, SPI_CS assert coincident with transaction 140232812Sjmallett NOTE: This control apply for 2 CSs */ 141232812Sjmallett uint64_t tritx : 1; /**< If 0, SPI_DO pin is driven when slave is not | NS 142232812Sjmallett expected to be driving 143232812Sjmallett 1, SPI_DO pin is tristated when not transmitting 144232812Sjmallett NOTE: only used when WIREOR==1 */ 145232812Sjmallett uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between | NS 146232812Sjmallett commands. */ 147232812Sjmallett uint64_t cshi : 1; /**< If 0, CS is low asserted | NS 148232812Sjmallett 1, CS is high asserted */ 149232812Sjmallett uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX 150232812Sjmallett 1, CS is driven per MPI_TX intruction */ 151232812Sjmallett uint64_t int_ena : 1; /**< If 0, polling is required | NS 152232812Sjmallett 1, MPI engine interrupts X end of transaction */ 153232812Sjmallett uint64_t lsbfirst : 1; /**< If 0, shift MSB first | NS 154232812Sjmallett 1, shift LSB first */ 155232812Sjmallett uint64_t wireor : 1; /**< If 0, SPI_DO and SPI_DI are separate wires (SPI) | NS 156232812Sjmallett SPI_DO pin is always driven 157232812Sjmallett 1, SPI_DO/DI is all from SPI_DO pin (MPI) 158232812Sjmallett SPI_DO pin is tristated when not transmitting 159232812Sjmallett NOTE: if WIREOR==1, SPI_DI pin is not used by the 160232812Sjmallett MPI engine */ 161232812Sjmallett uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after | NS 162232812Sjmallett completion of MPI transaction 163232812Sjmallett 1, clock never idles, requires CS deassertion 164232812Sjmallett assertion between commands */ 165232812Sjmallett uint64_t idlelo : 1; /**< If 0, SPI_CLK idles high, 1st transition is hi->lo | NS 166232812Sjmallett 1, SPI_CLK idles low, 1st transition is lo->hi */ 167232812Sjmallett uint64_t enable : 1; /**< If 0, UART0_DTR_L/SPI_DO, UART0_DCD_L/SPI_DI | NS 168232812Sjmallett BOOT_CE_N<7:6>/SPI_CSx_L 169232812Sjmallett pins are UART/BOOT pins 170232812Sjmallett 1, UART0_DTR_L/SPI_DO and UART0_DCD_L/SPI_DI 171232812Sjmallett pins are SPI/MPI pins. 172232812Sjmallett BOOT_CE_N<6>/SPI_CS0_L is SPI pin if CSENA0=1 173232812Sjmallett BOOT_CE_N<7>/SPI_CS1_L is SPI pin if CSENA1=1 */ 174232812Sjmallett#else 175232812Sjmallett uint64_t enable : 1; 176232812Sjmallett uint64_t idlelo : 1; 177232812Sjmallett uint64_t clk_cont : 1; 178232812Sjmallett uint64_t wireor : 1; 179232812Sjmallett uint64_t lsbfirst : 1; 180232812Sjmallett uint64_t int_ena : 1; 181232812Sjmallett uint64_t csena : 1; 182232812Sjmallett uint64_t cshi : 1; 183232812Sjmallett uint64_t idleclks : 2; 184232812Sjmallett uint64_t tritx : 1; 185232812Sjmallett uint64_t cslate : 1; 186232812Sjmallett uint64_t csena0 : 1; 187232812Sjmallett uint64_t csena1 : 1; 188232812Sjmallett uint64_t csena2 : 1; 189232812Sjmallett uint64_t csena3 : 1; 190232812Sjmallett uint64_t clkdiv : 13; 191232812Sjmallett uint64_t reserved_29_63 : 35; 192232812Sjmallett#endif 193232812Sjmallett } s; 194232812Sjmallett struct cvmx_mpi_cfg_cn30xx { 195232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 196232812Sjmallett uint64_t reserved_29_63 : 35; 197215976Sjmallett uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV) 198215976Sjmallett CLKDIV = Feclk / (2 * Fsclk) */ 199215976Sjmallett uint64_t reserved_12_15 : 4; 200215976Sjmallett uint64_t cslate : 1; /**< If 0, MPI_CS asserts 1/2 SCLK before transaction 201215976Sjmallett 1, MPI_CS assert coincident with transaction 202215976Sjmallett NOTE: only used if CSENA == 1 */ 203215976Sjmallett uint64_t tritx : 1; /**< If 0, MPI_TX pin is driven when slave is not 204215976Sjmallett expected to be driving 205215976Sjmallett 1, MPI_TX pin is tristated when not transmitting 206215976Sjmallett NOTE: only used when WIREOR==1 */ 207215976Sjmallett uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between 208215976Sjmallett commands. */ 209215976Sjmallett uint64_t cshi : 1; /**< If 0, CS is low asserted 210215976Sjmallett 1, CS is high asserted */ 211215976Sjmallett uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX 212215976Sjmallett 1, CS is driven per MPI_TX intruction */ 213215976Sjmallett uint64_t int_ena : 1; /**< If 0, polling is required 214215976Sjmallett 1, MPI engine interrupts X end of transaction */ 215215976Sjmallett uint64_t lsbfirst : 1; /**< If 0, shift MSB first 216215976Sjmallett 1, shift LSB first */ 217215976Sjmallett uint64_t wireor : 1; /**< If 0, MPI_TX and MPI_RX are separate wires (SPI) 218215976Sjmallett MPI_TX pin is always driven 219215976Sjmallett 1, MPI_TX/RX is all from MPI_TX pin (MPI) 220215976Sjmallett MPI_TX pin is tristated when not transmitting 221215976Sjmallett NOTE: if WIREOR==1, MPI_RX pin is not used by the 222215976Sjmallett MPI engine */ 223215976Sjmallett uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after 224215976Sjmallett completion of MPI transaction 225215976Sjmallett 1, clock never idles, requires CS deassertion 226215976Sjmallett assertion between commands */ 227215976Sjmallett uint64_t idlelo : 1; /**< If 0, MPI_CLK idles high, 1st transition is hi->lo 228215976Sjmallett 1, MPI_CLK idles low, 1st transition is lo->hi */ 229215976Sjmallett uint64_t enable : 1; /**< If 0, all MPI pins are GPIOs 230215976Sjmallett 1, MPI_CLK, MPI_CS, and MPI_TX are driven */ 231215976Sjmallett#else 232215976Sjmallett uint64_t enable : 1; 233215976Sjmallett uint64_t idlelo : 1; 234215976Sjmallett uint64_t clk_cont : 1; 235215976Sjmallett uint64_t wireor : 1; 236215976Sjmallett uint64_t lsbfirst : 1; 237215976Sjmallett uint64_t int_ena : 1; 238215976Sjmallett uint64_t csena : 1; 239215976Sjmallett uint64_t cshi : 1; 240215976Sjmallett uint64_t idleclks : 2; 241215976Sjmallett uint64_t tritx : 1; 242215976Sjmallett uint64_t cslate : 1; 243215976Sjmallett uint64_t reserved_12_15 : 4; 244215976Sjmallett uint64_t clkdiv : 13; 245215976Sjmallett uint64_t reserved_29_63 : 35; 246215976Sjmallett#endif 247232812Sjmallett } cn30xx; 248232812Sjmallett struct cvmx_mpi_cfg_cn31xx { 249232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 250215976Sjmallett uint64_t reserved_29_63 : 35; 251215976Sjmallett uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV) 252215976Sjmallett CLKDIV = Feclk / (2 * Fsclk) */ 253215976Sjmallett uint64_t reserved_11_15 : 5; 254215976Sjmallett uint64_t tritx : 1; /**< If 0, MPI_TX pin is driven when slave is not 255215976Sjmallett expected to be driving 256215976Sjmallett 1, MPI_TX pin is tristated when not transmitting 257215976Sjmallett NOTE: only used when WIREOR==1 */ 258215976Sjmallett uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between 259215976Sjmallett commands. */ 260215976Sjmallett uint64_t cshi : 1; /**< If 0, CS is low asserted 261215976Sjmallett 1, CS is high asserted */ 262215976Sjmallett uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX 263215976Sjmallett 1, CS is driven per MPI_TX intruction */ 264215976Sjmallett uint64_t int_ena : 1; /**< If 0, polling is required 265215976Sjmallett 1, MPI engine interrupts X end of transaction */ 266215976Sjmallett uint64_t lsbfirst : 1; /**< If 0, shift MSB first 267215976Sjmallett 1, shift LSB first */ 268215976Sjmallett uint64_t wireor : 1; /**< If 0, MPI_TX and MPI_RX are separate wires (SPI) 269215976Sjmallett MPI_TX pin is always driven 270215976Sjmallett 1, MPI_TX/RX is all from MPI_TX pin (MPI) 271215976Sjmallett MPI_TX pin is tristated when not transmitting 272215976Sjmallett NOTE: if WIREOR==1, MPI_RX pin is not used by the 273215976Sjmallett MPI engine */ 274215976Sjmallett uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after 275215976Sjmallett completion of MPI transaction 276215976Sjmallett 1, clock never idles, requires CS deassertion 277215976Sjmallett assertion between commands */ 278215976Sjmallett uint64_t idlelo : 1; /**< If 0, MPI_CLK idles high, 1st transition is hi->lo 279215976Sjmallett 1, MPI_CLK idles low, 1st transition is lo->hi */ 280215976Sjmallett uint64_t enable : 1; /**< If 0, all MPI pins are GPIOs 281215976Sjmallett 1, MPI_CLK, MPI_CS, and MPI_TX are driven */ 282215976Sjmallett#else 283215976Sjmallett uint64_t enable : 1; 284215976Sjmallett uint64_t idlelo : 1; 285215976Sjmallett uint64_t clk_cont : 1; 286215976Sjmallett uint64_t wireor : 1; 287215976Sjmallett uint64_t lsbfirst : 1; 288215976Sjmallett uint64_t int_ena : 1; 289215976Sjmallett uint64_t csena : 1; 290215976Sjmallett uint64_t cshi : 1; 291215976Sjmallett uint64_t idleclks : 2; 292215976Sjmallett uint64_t tritx : 1; 293215976Sjmallett uint64_t reserved_11_15 : 5; 294215976Sjmallett uint64_t clkdiv : 13; 295215976Sjmallett uint64_t reserved_29_63 : 35; 296215976Sjmallett#endif 297215976Sjmallett } cn31xx; 298232812Sjmallett struct cvmx_mpi_cfg_cn30xx cn50xx; 299232812Sjmallett struct cvmx_mpi_cfg_cn61xx { 300232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 301232812Sjmallett uint64_t reserved_29_63 : 35; 302232812Sjmallett uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) | NS 303232812Sjmallett CLKDIV = Fsclk / (2 * Fspi_clk) */ 304232812Sjmallett uint64_t reserved_14_15 : 2; 305232812Sjmallett uint64_t csena1 : 1; /**< If 0, BOOT_CE_N<7>/SPI_CS1_L pin is BOOT pin | NS 306232812Sjmallett 1, BOOT_CE_N<7>/SPI_CS1_L pin is SPI pin 307232812Sjmallett SPI_CS1_L drives BOOT_CE_N<7>/SPI_CS1_L */ 308232812Sjmallett uint64_t csena0 : 1; /**< If 0, BOOT_CE_N<6>/SPI_CS0_L pin is BOOT pin | NS 309232812Sjmallett 1, BOOT_CE_N<6>/SPI_CS0_L pin is SPI pin 310232812Sjmallett SPI_CS0_L drives BOOT_CE_N<6>/SPI_CS0_L */ 311232812Sjmallett uint64_t cslate : 1; /**< If 0, SPI_CS asserts 1/2 SCLK before transaction | NS 312232812Sjmallett 1, SPI_CS assert coincident with transaction 313232812Sjmallett NOTE: This control apply for 2 CSs */ 314232812Sjmallett uint64_t tritx : 1; /**< If 0, SPI_DO pin is driven when slave is not | NS 315232812Sjmallett expected to be driving 316232812Sjmallett 1, SPI_DO pin is tristated when not transmitting 317232812Sjmallett NOTE: only used when WIREOR==1 */ 318232812Sjmallett uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between | NS 319232812Sjmallett commands. */ 320232812Sjmallett uint64_t cshi : 1; /**< If 0, CS is low asserted | NS 321232812Sjmallett 1, CS is high asserted */ 322232812Sjmallett uint64_t reserved_6_6 : 1; 323232812Sjmallett uint64_t int_ena : 1; /**< If 0, polling is required | NS 324232812Sjmallett 1, MPI engine interrupts X end of transaction */ 325232812Sjmallett uint64_t lsbfirst : 1; /**< If 0, shift MSB first | NS 326232812Sjmallett 1, shift LSB first */ 327232812Sjmallett uint64_t wireor : 1; /**< If 0, SPI_DO and SPI_DI are separate wires (SPI) | NS 328232812Sjmallett SPI_DO pin is always driven 329232812Sjmallett 1, SPI_DO/DI is all from SPI_DO pin (MPI) 330232812Sjmallett SPI_DO pin is tristated when not transmitting 331232812Sjmallett NOTE: if WIREOR==1, SPI_DI pin is not used by the 332232812Sjmallett MPI engine */ 333232812Sjmallett uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after | NS 334232812Sjmallett completion of MPI transaction 335232812Sjmallett 1, clock never idles, requires CS deassertion 336232812Sjmallett assertion between commands */ 337232812Sjmallett uint64_t idlelo : 1; /**< If 0, SPI_CLK idles high, 1st transition is hi->lo | NS 338232812Sjmallett 1, SPI_CLK idles low, 1st transition is lo->hi */ 339232812Sjmallett uint64_t enable : 1; /**< If 0, UART0_DTR_L/SPI_DO, UART0_DCD_L/SPI_DI | NS 340232812Sjmallett BOOT_CE_N<7:6>/SPI_CSx_L 341232812Sjmallett pins are UART/BOOT pins 342232812Sjmallett 1, UART0_DTR_L/SPI_DO and UART0_DCD_L/SPI_DI 343232812Sjmallett pins are SPI/MPI pins. 344232812Sjmallett BOOT_CE_N<6>/SPI_CS0_L is SPI pin if CSENA0=1 345232812Sjmallett BOOT_CE_N<7>/SPI_CS1_L is SPI pin if CSENA1=1 */ 346232812Sjmallett#else 347232812Sjmallett uint64_t enable : 1; 348232812Sjmallett uint64_t idlelo : 1; 349232812Sjmallett uint64_t clk_cont : 1; 350232812Sjmallett uint64_t wireor : 1; 351232812Sjmallett uint64_t lsbfirst : 1; 352232812Sjmallett uint64_t int_ena : 1; 353232812Sjmallett uint64_t reserved_6_6 : 1; 354232812Sjmallett uint64_t cshi : 1; 355232812Sjmallett uint64_t idleclks : 2; 356232812Sjmallett uint64_t tritx : 1; 357232812Sjmallett uint64_t cslate : 1; 358232812Sjmallett uint64_t csena0 : 1; 359232812Sjmallett uint64_t csena1 : 1; 360232812Sjmallett uint64_t reserved_14_15 : 2; 361232812Sjmallett uint64_t clkdiv : 13; 362232812Sjmallett uint64_t reserved_29_63 : 35; 363232812Sjmallett#endif 364232812Sjmallett } cn61xx; 365232812Sjmallett struct cvmx_mpi_cfg_cn66xx { 366232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 367232812Sjmallett uint64_t reserved_29_63 : 35; 368232812Sjmallett uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) | NS 369232812Sjmallett CLKDIV = Fsclk / (2 * Fspi_clk) */ 370232812Sjmallett uint64_t csena3 : 1; /**< If 0, UART1_RTS_L/SPI_CS3_L pin is UART pin | NS 371232812Sjmallett 1, UART1_RTS_L/SPI_CS3_L pin is SPI pin 372232812Sjmallett SPI_CS3_L drives UART1_RTS_L/SPI_CS3_L */ 373232812Sjmallett uint64_t csena2 : 1; /**< If 0, UART0_RTS_L/SPI_CS2_L pin is UART pin | NS 374232812Sjmallett 1, UART0_RTS_L/SPI_CS2_L pin is SPI pin 375232812Sjmallett SPI_CS2_L drives UART0_RTS_L/SPI_CS2_L */ 376232812Sjmallett uint64_t reserved_12_13 : 2; 377232812Sjmallett uint64_t cslate : 1; /**< If 0, SPI_CS asserts 1/2 SCLK before transaction | NS 378232812Sjmallett 1, SPI_CS assert coincident with transaction 379232812Sjmallett NOTE: This control apply for 4 CSs */ 380232812Sjmallett uint64_t tritx : 1; /**< If 0, SPI_DO pin is driven when slave is not | NS 381232812Sjmallett expected to be driving 382232812Sjmallett 1, SPI_DO pin is tristated when not transmitting 383232812Sjmallett NOTE: only used when WIREOR==1 */ 384232812Sjmallett uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between | NS 385232812Sjmallett commands. */ 386232812Sjmallett uint64_t cshi : 1; /**< If 0, CS is low asserted | NS 387232812Sjmallett 1, CS is high asserted */ 388232812Sjmallett uint64_t reserved_6_6 : 1; 389232812Sjmallett uint64_t int_ena : 1; /**< If 0, polling is required | NS 390232812Sjmallett 1, MPI engine interrupts X end of transaction */ 391232812Sjmallett uint64_t lsbfirst : 1; /**< If 0, shift MSB first | NS 392232812Sjmallett 1, shift LSB first */ 393232812Sjmallett uint64_t wireor : 1; /**< If 0, SPI_DO and SPI_DI are separate wires (SPI) | NS 394232812Sjmallett SPI_DO pin is always driven 395232812Sjmallett 1, SPI_DO/DI is all from SPI_DO pin (MPI) 396232812Sjmallett SPI_DO pin is tristated when not transmitting 397232812Sjmallett NOTE: if WIREOR==1, SPI_DI pin is not used by the 398232812Sjmallett MPI engine */ 399232812Sjmallett uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after | NS 400232812Sjmallett completion of MPI transaction 401232812Sjmallett 1, clock never idles, requires CS deassertion 402232812Sjmallett assertion between commands */ 403232812Sjmallett uint64_t idlelo : 1; /**< If 0, SPI_CLK idles high, 1st transition is hi->lo | NS 404232812Sjmallett 1, SPI_CLK idles low, 1st transition is lo->hi */ 405232812Sjmallett uint64_t enable : 1; /**< If 0, UART0_DTR_L/SPI_DO, UART0_DCD_L/SPI_DI | NS 406232812Sjmallett UART0_RTS_L/SPI_CS2_L, UART1_RTS_L/SPI_CS3_L 407232812Sjmallett pins are UART pins 408232812Sjmallett 1, UART0_DTR_L/SPI_DO and UART0_DCD_L/SPI_DI 409232812Sjmallett pins are SPI/MPI pins. 410232812Sjmallett UART0_RTS_L/SPI_CS2_L is SPI pin if CSENA2=1 411232812Sjmallett UART1_RTS_L/SPI_CS3_L is SPI pin if CSENA3=1 */ 412232812Sjmallett#else 413232812Sjmallett uint64_t enable : 1; 414232812Sjmallett uint64_t idlelo : 1; 415232812Sjmallett uint64_t clk_cont : 1; 416232812Sjmallett uint64_t wireor : 1; 417232812Sjmallett uint64_t lsbfirst : 1; 418232812Sjmallett uint64_t int_ena : 1; 419232812Sjmallett uint64_t reserved_6_6 : 1; 420232812Sjmallett uint64_t cshi : 1; 421232812Sjmallett uint64_t idleclks : 2; 422232812Sjmallett uint64_t tritx : 1; 423232812Sjmallett uint64_t cslate : 1; 424232812Sjmallett uint64_t reserved_12_13 : 2; 425232812Sjmallett uint64_t csena2 : 1; 426232812Sjmallett uint64_t csena3 : 1; 427232812Sjmallett uint64_t clkdiv : 13; 428232812Sjmallett uint64_t reserved_29_63 : 35; 429232812Sjmallett#endif 430232812Sjmallett } cn66xx; 431232812Sjmallett struct cvmx_mpi_cfg_cn61xx cnf71xx; 432215976Sjmallett}; 433215976Sjmalletttypedef union cvmx_mpi_cfg cvmx_mpi_cfg_t; 434215976Sjmallett 435215976Sjmallett/** 436215976Sjmallett * cvmx_mpi_dat# 437215976Sjmallett */ 438232812Sjmallettunion cvmx_mpi_datx { 439215976Sjmallett uint64_t u64; 440232812Sjmallett struct cvmx_mpi_datx_s { 441232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 442215976Sjmallett uint64_t reserved_8_63 : 56; 443232812Sjmallett uint64_t data : 8; /**< Data to transmit/received | NS */ 444215976Sjmallett#else 445215976Sjmallett uint64_t data : 8; 446215976Sjmallett uint64_t reserved_8_63 : 56; 447215976Sjmallett#endif 448215976Sjmallett } s; 449215976Sjmallett struct cvmx_mpi_datx_s cn30xx; 450215976Sjmallett struct cvmx_mpi_datx_s cn31xx; 451215976Sjmallett struct cvmx_mpi_datx_s cn50xx; 452232812Sjmallett struct cvmx_mpi_datx_s cn61xx; 453232812Sjmallett struct cvmx_mpi_datx_s cn66xx; 454232812Sjmallett struct cvmx_mpi_datx_s cnf71xx; 455215976Sjmallett}; 456215976Sjmalletttypedef union cvmx_mpi_datx cvmx_mpi_datx_t; 457215976Sjmallett 458215976Sjmallett/** 459215976Sjmallett * cvmx_mpi_sts 460215976Sjmallett */ 461232812Sjmallettunion cvmx_mpi_sts { 462215976Sjmallett uint64_t u64; 463232812Sjmallett struct cvmx_mpi_sts_s { 464232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 465215976Sjmallett uint64_t reserved_13_63 : 51; 466232812Sjmallett uint64_t rxnum : 5; /**< Number of bytes written for transaction | NS */ 467215976Sjmallett uint64_t reserved_1_7 : 7; 468232812Sjmallett uint64_t busy : 1; /**< If 0, no MPI transaction in progress | NS 469215976Sjmallett 1, MPI engine is processing a transaction */ 470215976Sjmallett#else 471215976Sjmallett uint64_t busy : 1; 472215976Sjmallett uint64_t reserved_1_7 : 7; 473215976Sjmallett uint64_t rxnum : 5; 474215976Sjmallett uint64_t reserved_13_63 : 51; 475215976Sjmallett#endif 476215976Sjmallett } s; 477215976Sjmallett struct cvmx_mpi_sts_s cn30xx; 478215976Sjmallett struct cvmx_mpi_sts_s cn31xx; 479215976Sjmallett struct cvmx_mpi_sts_s cn50xx; 480232812Sjmallett struct cvmx_mpi_sts_s cn61xx; 481232812Sjmallett struct cvmx_mpi_sts_s cn66xx; 482232812Sjmallett struct cvmx_mpi_sts_s cnf71xx; 483215976Sjmallett}; 484215976Sjmalletttypedef union cvmx_mpi_sts cvmx_mpi_sts_t; 485215976Sjmallett 486215976Sjmallett/** 487215976Sjmallett * cvmx_mpi_tx 488215976Sjmallett */ 489232812Sjmallettunion cvmx_mpi_tx { 490215976Sjmallett uint64_t u64; 491232812Sjmallett struct cvmx_mpi_tx_s { 492232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 493232812Sjmallett uint64_t reserved_22_63 : 42; 494232812Sjmallett uint64_t csid : 2; /**< Which CS to assert for this transaction | NS */ 495232812Sjmallett uint64_t reserved_17_19 : 3; 496232812Sjmallett uint64_t leavecs : 1; /**< If 0, deassert CS after transaction is done | NS 497232812Sjmallett 1, leave CS asserted after transactrion is done */ 498232812Sjmallett uint64_t reserved_13_15 : 3; 499232812Sjmallett uint64_t txnum : 5; /**< Number of bytes to transmit | NS */ 500232812Sjmallett uint64_t reserved_5_7 : 3; 501232812Sjmallett uint64_t totnum : 5; /**< Number of bytes to shift (transmit + receive) | NS */ 502232812Sjmallett#else 503232812Sjmallett uint64_t totnum : 5; 504232812Sjmallett uint64_t reserved_5_7 : 3; 505232812Sjmallett uint64_t txnum : 5; 506232812Sjmallett uint64_t reserved_13_15 : 3; 507232812Sjmallett uint64_t leavecs : 1; 508232812Sjmallett uint64_t reserved_17_19 : 3; 509232812Sjmallett uint64_t csid : 2; 510232812Sjmallett uint64_t reserved_22_63 : 42; 511232812Sjmallett#endif 512232812Sjmallett } s; 513232812Sjmallett struct cvmx_mpi_tx_cn30xx { 514232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 515215976Sjmallett uint64_t reserved_17_63 : 47; 516215976Sjmallett uint64_t leavecs : 1; /**< If 0, deassert CS after transaction is done 517215976Sjmallett 1, leave CS asserted after transactrion is done */ 518215976Sjmallett uint64_t reserved_13_15 : 3; 519215976Sjmallett uint64_t txnum : 5; /**< Number of bytes to transmit */ 520215976Sjmallett uint64_t reserved_5_7 : 3; 521215976Sjmallett uint64_t totnum : 5; /**< Number of bytes to shift (transmit + receive) */ 522215976Sjmallett#else 523215976Sjmallett uint64_t totnum : 5; 524215976Sjmallett uint64_t reserved_5_7 : 3; 525215976Sjmallett uint64_t txnum : 5; 526215976Sjmallett uint64_t reserved_13_15 : 3; 527215976Sjmallett uint64_t leavecs : 1; 528215976Sjmallett uint64_t reserved_17_63 : 47; 529215976Sjmallett#endif 530232812Sjmallett } cn30xx; 531232812Sjmallett struct cvmx_mpi_tx_cn30xx cn31xx; 532232812Sjmallett struct cvmx_mpi_tx_cn30xx cn50xx; 533232812Sjmallett struct cvmx_mpi_tx_cn61xx { 534232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 535232812Sjmallett uint64_t reserved_21_63 : 43; 536232812Sjmallett uint64_t csid : 1; /**< Which CS to assert for this transaction | NS */ 537232812Sjmallett uint64_t reserved_17_19 : 3; 538232812Sjmallett uint64_t leavecs : 1; /**< If 0, deassert CS after transaction is done | NS 539232812Sjmallett 1, leave CS asserted after transactrion is done */ 540232812Sjmallett uint64_t reserved_13_15 : 3; 541232812Sjmallett uint64_t txnum : 5; /**< Number of bytes to transmit | NS */ 542232812Sjmallett uint64_t reserved_5_7 : 3; 543232812Sjmallett uint64_t totnum : 5; /**< Number of bytes to shift (transmit + receive) | NS */ 544232812Sjmallett#else 545232812Sjmallett uint64_t totnum : 5; 546232812Sjmallett uint64_t reserved_5_7 : 3; 547232812Sjmallett uint64_t txnum : 5; 548232812Sjmallett uint64_t reserved_13_15 : 3; 549232812Sjmallett uint64_t leavecs : 1; 550232812Sjmallett uint64_t reserved_17_19 : 3; 551232812Sjmallett uint64_t csid : 1; 552232812Sjmallett uint64_t reserved_21_63 : 43; 553232812Sjmallett#endif 554232812Sjmallett } cn61xx; 555232812Sjmallett struct cvmx_mpi_tx_s cn66xx; 556232812Sjmallett struct cvmx_mpi_tx_cn61xx cnf71xx; 557215976Sjmallett}; 558215976Sjmalletttypedef union cvmx_mpi_tx cvmx_mpi_tx_t; 559215976Sjmallett 560215976Sjmallett#endif 561