1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-mixx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon mixx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_MIXX_DEFS_H__ 53232812Sjmallett#define __CVMX_MIXX_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_MIXX_BIST(unsigned long offset) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 61232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 62232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 63232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 64232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 65215976Sjmallett cvmx_warn("CVMX_MIXX_BIST(%lu) is invalid on this chip\n", offset); 66215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048; 67215976Sjmallett} 68215976Sjmallett#else 69215976Sjmallett#define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048) 70215976Sjmallett#endif 71215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 72215976Sjmallettstatic inline uint64_t CVMX_MIXX_CTL(unsigned long offset) 73215976Sjmallett{ 74215976Sjmallett if (!( 75215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 76215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 77232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 78232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 79232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 80232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 81215976Sjmallett cvmx_warn("CVMX_MIXX_CTL(%lu) is invalid on this chip\n", offset); 82215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048; 83215976Sjmallett} 84215976Sjmallett#else 85215976Sjmallett#define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048) 86215976Sjmallett#endif 87215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 88215976Sjmallettstatic inline uint64_t CVMX_MIXX_INTENA(unsigned long offset) 89215976Sjmallett{ 90215976Sjmallett if (!( 91215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 92215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 93232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 94232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 95232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 96232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 97215976Sjmallett cvmx_warn("CVMX_MIXX_INTENA(%lu) is invalid on this chip\n", offset); 98215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048; 99215976Sjmallett} 100215976Sjmallett#else 101215976Sjmallett#define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048) 102215976Sjmallett#endif 103215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104215976Sjmallettstatic inline uint64_t CVMX_MIXX_IRCNT(unsigned long offset) 105215976Sjmallett{ 106215976Sjmallett if (!( 107215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 108215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 109232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 110232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 111232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 112232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 113215976Sjmallett cvmx_warn("CVMX_MIXX_IRCNT(%lu) is invalid on this chip\n", offset); 114215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048; 115215976Sjmallett} 116215976Sjmallett#else 117215976Sjmallett#define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048) 118215976Sjmallett#endif 119215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 120215976Sjmallettstatic inline uint64_t CVMX_MIXX_IRHWM(unsigned long offset) 121215976Sjmallett{ 122215976Sjmallett if (!( 123215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 124215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 125232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 126232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 127232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 128232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 129215976Sjmallett cvmx_warn("CVMX_MIXX_IRHWM(%lu) is invalid on this chip\n", offset); 130215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048; 131215976Sjmallett} 132215976Sjmallett#else 133215976Sjmallett#define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048) 134215976Sjmallett#endif 135215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 136215976Sjmallettstatic inline uint64_t CVMX_MIXX_IRING1(unsigned long offset) 137215976Sjmallett{ 138215976Sjmallett if (!( 139215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 140215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 141232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 142232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 143232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 144232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 145215976Sjmallett cvmx_warn("CVMX_MIXX_IRING1(%lu) is invalid on this chip\n", offset); 146215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048; 147215976Sjmallett} 148215976Sjmallett#else 149215976Sjmallett#define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048) 150215976Sjmallett#endif 151215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 152215976Sjmallettstatic inline uint64_t CVMX_MIXX_IRING2(unsigned long offset) 153215976Sjmallett{ 154215976Sjmallett if (!( 155215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 156215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 157232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 158232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 159232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 160232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 161215976Sjmallett cvmx_warn("CVMX_MIXX_IRING2(%lu) is invalid on this chip\n", offset); 162215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048; 163215976Sjmallett} 164215976Sjmallett#else 165215976Sjmallett#define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048) 166215976Sjmallett#endif 167215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 168215976Sjmallettstatic inline uint64_t CVMX_MIXX_ISR(unsigned long offset) 169215976Sjmallett{ 170215976Sjmallett if (!( 171215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 172215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 173232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 174232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 175232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 176232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 177215976Sjmallett cvmx_warn("CVMX_MIXX_ISR(%lu) is invalid on this chip\n", offset); 178215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048; 179215976Sjmallett} 180215976Sjmallett#else 181215976Sjmallett#define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048) 182215976Sjmallett#endif 183215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 184215976Sjmallettstatic inline uint64_t CVMX_MIXX_ORCNT(unsigned long offset) 185215976Sjmallett{ 186215976Sjmallett if (!( 187215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 188215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 189232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 190232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 191232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 192232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 193215976Sjmallett cvmx_warn("CVMX_MIXX_ORCNT(%lu) is invalid on this chip\n", offset); 194215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048; 195215976Sjmallett} 196215976Sjmallett#else 197215976Sjmallett#define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048) 198215976Sjmallett#endif 199215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 200215976Sjmallettstatic inline uint64_t CVMX_MIXX_ORHWM(unsigned long offset) 201215976Sjmallett{ 202215976Sjmallett if (!( 203215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 204215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 205232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 206232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 207232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 208232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 209215976Sjmallett cvmx_warn("CVMX_MIXX_ORHWM(%lu) is invalid on this chip\n", offset); 210215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048; 211215976Sjmallett} 212215976Sjmallett#else 213215976Sjmallett#define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048) 214215976Sjmallett#endif 215215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 216215976Sjmallettstatic inline uint64_t CVMX_MIXX_ORING1(unsigned long offset) 217215976Sjmallett{ 218215976Sjmallett if (!( 219215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 220215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 221232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 222232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 223232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 224232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 225215976Sjmallett cvmx_warn("CVMX_MIXX_ORING1(%lu) is invalid on this chip\n", offset); 226215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048; 227215976Sjmallett} 228215976Sjmallett#else 229215976Sjmallett#define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048) 230215976Sjmallett#endif 231215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232215976Sjmallettstatic inline uint64_t CVMX_MIXX_ORING2(unsigned long offset) 233215976Sjmallett{ 234215976Sjmallett if (!( 235215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 236215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 237232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 238232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 239232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 240232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 241215976Sjmallett cvmx_warn("CVMX_MIXX_ORING2(%lu) is invalid on this chip\n", offset); 242215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048; 243215976Sjmallett} 244215976Sjmallett#else 245215976Sjmallett#define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048) 246215976Sjmallett#endif 247215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 248215976Sjmallettstatic inline uint64_t CVMX_MIXX_REMCNT(unsigned long offset) 249215976Sjmallett{ 250215976Sjmallett if (!( 251215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 252215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) || 253232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 254232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 255232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 256232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 257215976Sjmallett cvmx_warn("CVMX_MIXX_REMCNT(%lu) is invalid on this chip\n", offset); 258215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048; 259215976Sjmallett} 260215976Sjmallett#else 261215976Sjmallett#define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048) 262215976Sjmallett#endif 263215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 264215976Sjmallettstatic inline uint64_t CVMX_MIXX_TSCTL(unsigned long offset) 265215976Sjmallett{ 266215976Sjmallett if (!( 267232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 268232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 269232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 270232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 271215976Sjmallett cvmx_warn("CVMX_MIXX_TSCTL(%lu) is invalid on this chip\n", offset); 272215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048; 273215976Sjmallett} 274215976Sjmallett#else 275215976Sjmallett#define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048) 276215976Sjmallett#endif 277215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 278215976Sjmallettstatic inline uint64_t CVMX_MIXX_TSTAMP(unsigned long offset) 279215976Sjmallett{ 280215976Sjmallett if (!( 281232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 282232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 283232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 284232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0))))) 285215976Sjmallett cvmx_warn("CVMX_MIXX_TSTAMP(%lu) is invalid on this chip\n", offset); 286215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048; 287215976Sjmallett} 288215976Sjmallett#else 289215976Sjmallett#define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048) 290215976Sjmallett#endif 291215976Sjmallett 292215976Sjmallett/** 293215976Sjmallett * cvmx_mix#_bist 294215976Sjmallett * 295215976Sjmallett * MIX_BIST = MIX BIST Register 296215976Sjmallett * 297215976Sjmallett * Description: 298215976Sjmallett * NOTE: To read the MIX_BIST register, a device would issue an IOBLD64 directed at the MIO. 299215976Sjmallett */ 300232812Sjmallettunion cvmx_mixx_bist { 301215976Sjmallett uint64_t u64; 302232812Sjmallett struct cvmx_mixx_bist_s { 303232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 304215976Sjmallett uint64_t reserved_6_63 : 58; 305215976Sjmallett uint64_t opfdat : 1; /**< Bist Results for AGO OPF Buffer RAM 306215976Sjmallett - 0: GOOD (or bist in progress/never run) 307215976Sjmallett - 1: BAD */ 308215976Sjmallett uint64_t mrgdat : 1; /**< Bist Results for AGI MRG Buffer RAM 309215976Sjmallett - 0: GOOD (or bist in progress/never run) 310215976Sjmallett - 1: BAD */ 311215976Sjmallett uint64_t mrqdat : 1; /**< Bist Results for NBR CSR RdReq RAM 312215976Sjmallett - 0: GOOD (or bist in progress/never run) 313215976Sjmallett - 1: BAD */ 314215976Sjmallett uint64_t ipfdat : 1; /**< Bist Results for MIX Inbound Packet RAM 315215976Sjmallett - 0: GOOD (or bist in progress/never run) 316215976Sjmallett - 1: BAD */ 317215976Sjmallett uint64_t irfdat : 1; /**< Bist Results for MIX I-Ring Entry RAM 318215976Sjmallett - 0: GOOD (or bist in progress/never run) 319215976Sjmallett - 1: BAD */ 320215976Sjmallett uint64_t orfdat : 1; /**< Bist Results for MIX O-Ring Entry RAM 321215976Sjmallett - 0: GOOD (or bist in progress/never run) 322215976Sjmallett - 1: BAD */ 323215976Sjmallett#else 324215976Sjmallett uint64_t orfdat : 1; 325215976Sjmallett uint64_t irfdat : 1; 326215976Sjmallett uint64_t ipfdat : 1; 327215976Sjmallett uint64_t mrqdat : 1; 328215976Sjmallett uint64_t mrgdat : 1; 329215976Sjmallett uint64_t opfdat : 1; 330215976Sjmallett uint64_t reserved_6_63 : 58; 331215976Sjmallett#endif 332215976Sjmallett } s; 333232812Sjmallett struct cvmx_mixx_bist_cn52xx { 334232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 335215976Sjmallett uint64_t reserved_4_63 : 60; 336215976Sjmallett uint64_t mrqdat : 1; /**< Bist Results for NBR CSR RdReq RAM 337215976Sjmallett - 0: GOOD (or bist in progress/never run) 338215976Sjmallett - 1: BAD */ 339215976Sjmallett uint64_t ipfdat : 1; /**< Bist Results for MIX Inbound Packet RAM 340215976Sjmallett - 0: GOOD (or bist in progress/never run) 341215976Sjmallett - 1: BAD */ 342215976Sjmallett uint64_t irfdat : 1; /**< Bist Results for MIX I-Ring Entry RAM 343215976Sjmallett - 0: GOOD (or bist in progress/never run) 344215976Sjmallett - 1: BAD */ 345215976Sjmallett uint64_t orfdat : 1; /**< Bist Results for MIX O-Ring Entry RAM 346215976Sjmallett - 0: GOOD (or bist in progress/never run) 347215976Sjmallett - 1: BAD */ 348215976Sjmallett#else 349215976Sjmallett uint64_t orfdat : 1; 350215976Sjmallett uint64_t irfdat : 1; 351215976Sjmallett uint64_t ipfdat : 1; 352215976Sjmallett uint64_t mrqdat : 1; 353215976Sjmallett uint64_t reserved_4_63 : 60; 354215976Sjmallett#endif 355215976Sjmallett } cn52xx; 356215976Sjmallett struct cvmx_mixx_bist_cn52xx cn52xxp1; 357215976Sjmallett struct cvmx_mixx_bist_cn52xx cn56xx; 358215976Sjmallett struct cvmx_mixx_bist_cn52xx cn56xxp1; 359232812Sjmallett struct cvmx_mixx_bist_s cn61xx; 360215976Sjmallett struct cvmx_mixx_bist_s cn63xx; 361215976Sjmallett struct cvmx_mixx_bist_s cn63xxp1; 362232812Sjmallett struct cvmx_mixx_bist_s cn66xx; 363232812Sjmallett struct cvmx_mixx_bist_s cn68xx; 364232812Sjmallett struct cvmx_mixx_bist_s cn68xxp1; 365215976Sjmallett}; 366215976Sjmalletttypedef union cvmx_mixx_bist cvmx_mixx_bist_t; 367215976Sjmallett 368215976Sjmallett/** 369215976Sjmallett * cvmx_mix#_ctl 370215976Sjmallett * 371215976Sjmallett * MIX_CTL = MIX Control Register 372215976Sjmallett * 373215976Sjmallett * Description: 374215976Sjmallett * NOTE: To write to the MIX_CTL register, a device would issue an IOBST directed at the MIO. 375215976Sjmallett * To read the MIX_CTL register, a device would issue an IOBLD64 directed at the MIO. 376215976Sjmallett */ 377232812Sjmallettunion cvmx_mixx_ctl { 378215976Sjmallett uint64_t u64; 379232812Sjmallett struct cvmx_mixx_ctl_s { 380232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 381215976Sjmallett uint64_t reserved_12_63 : 52; 382215976Sjmallett uint64_t ts_thresh : 4; /**< TimeStamp Interrupt Threshold 383215976Sjmallett When the \#of pending Timestamp interrupts (MIX_TSCTL[TSCNT] 384215976Sjmallett is greater than MIX_CTL[TS_THRESH], then a programmable 385215976Sjmallett TimeStamp Interrupt is issued (see MIX_INTR[TS] 386215976Sjmallett MIX_INTENA[TSENA]). 387215976Sjmallett SWNOTE: For o63, since the implementation only supports 388215976Sjmallett 4 oustanding timestamp interrupts, this field should 389215976Sjmallett only be programmed from [0..3]. */ 390215976Sjmallett uint64_t crc_strip : 1; /**< HW CRC Strip Enable 391215976Sjmallett When enabled, the last 4 bytes(CRC) of the ingress packet 392215976Sjmallett are not included in cumulative packet byte length. 393215976Sjmallett In other words, the cumulative LEN field for all 394215976Sjmallett I-Ring Buffer Entries associated with a given ingress 395215976Sjmallett packet will be 4 bytes less (so that the final 4B HW CRC 396215976Sjmallett packet data is not processed by software). */ 397215976Sjmallett uint64_t busy : 1; /**< MIX Busy Status bit 398215976Sjmallett MIX will assert busy status any time there are: 399215976Sjmallett 1) L2/DRAM reads in-flight (NCB-arb to read 400215976Sjmallett response) 401215976Sjmallett 2) L2/DRAM writes in-flight (NCB-arb to write 402215976Sjmallett data is sent. 403215976Sjmallett 3) L2/DRAM write commits in-flight (NCB-arb to write 404215976Sjmallett commit response). 405215976Sjmallett NOTE: After MIX_CTL[EN]=0, the MIX will eventually 406215976Sjmallett complete any "inflight" transactions, at which point the 407215976Sjmallett BUSY will de-assert. */ 408215976Sjmallett uint64_t en : 1; /**< MIX Enable bit 409215976Sjmallett When EN=0, MIX will no longer arbitrate for 410215976Sjmallett any new L2/DRAM read/write requests on the NCB Bus. 411215976Sjmallett MIX will complete any requests that are currently 412215976Sjmallett pended for the NCB Bus. */ 413215976Sjmallett uint64_t reset : 1; /**< MIX Soft Reset 414215976Sjmallett When SW writes a '1' to MIX_CTL[RESET], the 415215976Sjmallett MII-MIX/AGL logic will execute a soft reset. 416215976Sjmallett NOTE: During a soft reset, CSR accesses are not effected. 417215976Sjmallett However, the values of the CSR fields will be effected by 418215976Sjmallett soft reset (except MIX_CTL[RESET] itself). 419215976Sjmallett NOTE: After power-on, the MII-AGL/MIX are held in reset 420232812Sjmallett until the MIX_CTL[RESET] is written to zero. SW MUST also 421232812Sjmallett perform a MIX_CTL CSR read after this write to ensure the 422232812Sjmallett soft reset de-assertion has had sufficient time to propagate 423232812Sjmallett to all MIO-MIX internal logic before any subsequent MIX CSR 424232812Sjmallett accesses are issued. 425215976Sjmallett The intended "soft reset" sequence is: (please also 426215976Sjmallett refer to HRM Section 12.6.2 on MIX/AGL Block Reset). 427215976Sjmallett 1) Write MIX_CTL[EN]=0 428215976Sjmallett [To prevent any NEW transactions from being started] 429215976Sjmallett 2) Wait for MIX_CTL[BUSY]=0 430215976Sjmallett [To indicate that all inflight transactions have 431215976Sjmallett completed] 432215976Sjmallett 3) Write MIX_CTL[RESET]=1, followed by a MIX_CTL CSR read 433215976Sjmallett and wait for the result. 434215976Sjmallett 4) Re-Initialize the MIX/AGL just as would be done 435215976Sjmallett for a hard reset. 436215976Sjmallett NOTE: Once the MII has been soft-reset, please refer to HRM Section 437215976Sjmallett 12.6.1 MIX/AGL BringUp Sequence to complete the MIX/AGL 438215976Sjmallett re-initialization sequence. */ 439215976Sjmallett uint64_t lendian : 1; /**< Packet Little Endian Mode 440215976Sjmallett (0: Big Endian Mode/1: Little Endian Mode) 441215976Sjmallett When the mode is set, MIX will byte-swap packet data 442215976Sjmallett loads/stores at the MIX/NCB boundary. */ 443215976Sjmallett uint64_t nbtarb : 1; /**< MIX CB-Request Arbitration Mode. 444215976Sjmallett When set to zero, the arbiter is fixed priority with 445215976Sjmallett the following priority scheme: 446215976Sjmallett Highest Priority: I-Ring Packet Write Request 447215976Sjmallett O-Ring Packet Read Request 448215976Sjmallett I-Ring Entry Write Request 449215976Sjmallett I-Ring Entry Read Request 450215976Sjmallett O-Ring Entry Read Request 451215976Sjmallett When set to one, the arbiter is round robin. */ 452215976Sjmallett uint64_t mrq_hwm : 2; /**< MIX CB-Request FIFO Programmable High Water Mark. 453215976Sjmallett The MRQ contains 16 CB-Requests which are CSR Rd/Wr 454215976Sjmallett Requests. If the MRQ backs up with "HWM" entries, 455215976Sjmallett then new CB-Requests are 'stalled'. 456215976Sjmallett [0]: HWM = 11 457215976Sjmallett [1]: HWM = 10 458215976Sjmallett [2]: HWM = 9 459215976Sjmallett [3]: HWM = 8 460215976Sjmallett NOTE: This must only be written at power-on/boot time. */ 461215976Sjmallett#else 462215976Sjmallett uint64_t mrq_hwm : 2; 463215976Sjmallett uint64_t nbtarb : 1; 464215976Sjmallett uint64_t lendian : 1; 465215976Sjmallett uint64_t reset : 1; 466215976Sjmallett uint64_t en : 1; 467215976Sjmallett uint64_t busy : 1; 468215976Sjmallett uint64_t crc_strip : 1; 469215976Sjmallett uint64_t ts_thresh : 4; 470215976Sjmallett uint64_t reserved_12_63 : 52; 471215976Sjmallett#endif 472215976Sjmallett } s; 473232812Sjmallett struct cvmx_mixx_ctl_cn52xx { 474232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 475215976Sjmallett uint64_t reserved_8_63 : 56; 476215976Sjmallett uint64_t crc_strip : 1; /**< HW CRC Strip Enable 477215976Sjmallett When enabled, the last 4 bytes(CRC) of the ingress packet 478215976Sjmallett are not included in cumulative packet byte length. 479215976Sjmallett In other words, the cumulative LEN field for all 480215976Sjmallett I-Ring Buffer Entries associated with a given ingress 481215976Sjmallett packet will be 4 bytes less (so that the final 4B HW CRC 482215976Sjmallett packet data is not processed by software). */ 483215976Sjmallett uint64_t busy : 1; /**< MIX Busy Status bit 484215976Sjmallett MIX will assert busy status any time there are: 485215976Sjmallett 1) L2/DRAM reads in-flight (NCB-arb to read 486215976Sjmallett response) 487215976Sjmallett 2) L2/DRAM writes in-flight (NCB-arb to write 488215976Sjmallett data is sent. 489215976Sjmallett 3) L2/DRAM write commits in-flight (NCB-arb to write 490215976Sjmallett commit response). 491215976Sjmallett NOTE: After MIX_CTL[EN]=0, the MIX will eventually 492215976Sjmallett complete any "inflight" transactions, at which point the 493215976Sjmallett BUSY will de-assert. */ 494215976Sjmallett uint64_t en : 1; /**< MIX Enable bit 495215976Sjmallett When EN=0, MIX will no longer arbitrate for 496215976Sjmallett any new L2/DRAM read/write requests on the NCB Bus. 497215976Sjmallett MIX will complete any requests that are currently 498215976Sjmallett pended for the NCB Bus. */ 499215976Sjmallett uint64_t reset : 1; /**< MIX Soft Reset 500215976Sjmallett When SW writes a '1' to MIX_CTL[RESET], the 501215976Sjmallett MII-MIX/AGL logic will execute a soft reset. 502215976Sjmallett NOTE: During a soft reset, CSR accesses are not effected. 503215976Sjmallett However, the values of the CSR fields will be effected by 504215976Sjmallett soft reset (except MIX_CTL[RESET] itself). 505215976Sjmallett NOTE: After power-on, the MII-AGL/MIX are held in reset 506232812Sjmallett until the MIX_CTL[RESET] is written to zero. SW MUST also 507232812Sjmallett perform a MIX_CTL CSR read after this write to ensure the 508232812Sjmallett soft reset de-assertion has had sufficient time to propagate 509232812Sjmallett to all MIO-MIX internal logic before any subsequent MIX CSR 510232812Sjmallett accesses are issued. 511215976Sjmallett The intended "soft reset" sequence is: (please also 512215976Sjmallett refer to HRM Section 12.6.2 on MIX/AGL Block Reset). 513215976Sjmallett 1) Write MIX_CTL[EN]=0 514215976Sjmallett [To prevent any NEW transactions from being started] 515215976Sjmallett 2) Wait for MIX_CTL[BUSY]=0 516215976Sjmallett [To indicate that all inflight transactions have 517215976Sjmallett completed] 518215976Sjmallett 3) Write MIX_CTL[RESET]=1, followed by a MIX_CTL CSR read 519215976Sjmallett and wait for the result. 520215976Sjmallett 4) Re-Initialize the MIX/AGL just as would be done 521215976Sjmallett for a hard reset. 522215976Sjmallett NOTE: Once the MII has been soft-reset, please refer to HRM Section 523215976Sjmallett 12.6.1 MIX/AGL BringUp Sequence to complete the MIX/AGL 524215976Sjmallett re-initialization sequence. */ 525215976Sjmallett uint64_t lendian : 1; /**< Packet Little Endian Mode 526215976Sjmallett (0: Big Endian Mode/1: Little Endian Mode) 527215976Sjmallett When the mode is set, MIX will byte-swap packet data 528215976Sjmallett loads/stores at the MIX/NCB boundary. */ 529215976Sjmallett uint64_t nbtarb : 1; /**< MIX CB-Request Arbitration Mode. 530215976Sjmallett When set to zero, the arbiter is fixed priority with 531215976Sjmallett the following priority scheme: 532215976Sjmallett Highest Priority: I-Ring Packet Write Request 533215976Sjmallett O-Ring Packet Read Request 534215976Sjmallett I-Ring Entry Write Request 535215976Sjmallett I-Ring Entry Read Request 536215976Sjmallett O-Ring Entry Read Request 537215976Sjmallett When set to one, the arbiter is round robin. */ 538215976Sjmallett uint64_t mrq_hwm : 2; /**< MIX CB-Request FIFO Programmable High Water Mark. 539215976Sjmallett The MRQ contains 16 CB-Requests which are CSR Rd/Wr 540215976Sjmallett Requests. If the MRQ backs up with "HWM" entries, 541215976Sjmallett then new CB-Requests are 'stalled'. 542215976Sjmallett [0]: HWM = 11 543215976Sjmallett [1]: HWM = 10 544215976Sjmallett [2]: HWM = 9 545215976Sjmallett [3]: HWM = 8 546215976Sjmallett NOTE: This must only be written at power-on/boot time. */ 547215976Sjmallett#else 548215976Sjmallett uint64_t mrq_hwm : 2; 549215976Sjmallett uint64_t nbtarb : 1; 550215976Sjmallett uint64_t lendian : 1; 551215976Sjmallett uint64_t reset : 1; 552215976Sjmallett uint64_t en : 1; 553215976Sjmallett uint64_t busy : 1; 554215976Sjmallett uint64_t crc_strip : 1; 555215976Sjmallett uint64_t reserved_8_63 : 56; 556215976Sjmallett#endif 557215976Sjmallett } cn52xx; 558215976Sjmallett struct cvmx_mixx_ctl_cn52xx cn52xxp1; 559215976Sjmallett struct cvmx_mixx_ctl_cn52xx cn56xx; 560215976Sjmallett struct cvmx_mixx_ctl_cn52xx cn56xxp1; 561232812Sjmallett struct cvmx_mixx_ctl_s cn61xx; 562215976Sjmallett struct cvmx_mixx_ctl_s cn63xx; 563215976Sjmallett struct cvmx_mixx_ctl_s cn63xxp1; 564232812Sjmallett struct cvmx_mixx_ctl_s cn66xx; 565232812Sjmallett struct cvmx_mixx_ctl_s cn68xx; 566232812Sjmallett struct cvmx_mixx_ctl_s cn68xxp1; 567215976Sjmallett}; 568215976Sjmalletttypedef union cvmx_mixx_ctl cvmx_mixx_ctl_t; 569215976Sjmallett 570215976Sjmallett/** 571215976Sjmallett * cvmx_mix#_intena 572215976Sjmallett * 573215976Sjmallett * MIX_INTENA = MIX Local Interrupt Enable Mask Register 574215976Sjmallett * 575215976Sjmallett * Description: 576215976Sjmallett * NOTE: To write to the MIX_INTENA register, a device would issue an IOBST directed at the MIO. 577215976Sjmallett * To read the MIX_INTENA register, a device would issue an IOBLD64 directed at the MIO. 578215976Sjmallett */ 579232812Sjmallettunion cvmx_mixx_intena { 580215976Sjmallett uint64_t u64; 581232812Sjmallett struct cvmx_mixx_intena_s { 582232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 583215976Sjmallett uint64_t reserved_8_63 : 56; 584215976Sjmallett uint64_t tsena : 1; /**< TimeStamp Interrupt Enable 585232812Sjmallett If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII]) 586215976Sjmallett and this local interrupt mask bit is set, than an 587215976Sjmallett interrupt is reported for an Outbound Ring with Timestamp 588215976Sjmallett event (see: MIX_ISR[TS]). */ 589215976Sjmallett uint64_t orunena : 1; /**< ORCNT UnderFlow Detected Enable 590232812Sjmallett If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII]) 591215976Sjmallett and this local interrupt mask bit is set, than an 592215976Sjmallett interrupt is reported for an ORCNT underflow condition 593215976Sjmallett MIX_ISR[ORUN]. */ 594215976Sjmallett uint64_t irunena : 1; /**< IRCNT UnderFlow Interrupt Enable 595232812Sjmallett If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII]) 596215976Sjmallett and this local interrupt mask bit is set, than an 597215976Sjmallett interrupt is reported for an IRCNT underflow condition 598215976Sjmallett MIX_ISR[IRUN]. */ 599215976Sjmallett uint64_t data_drpena : 1; /**< Data was dropped due to RX FIFO full Interrupt 600215976Sjmallett enable. If both the global interrupt mask bits 601232812Sjmallett (CIU2_EN_xx_yy_PKT[MII]) and the local interrupt mask 602215976Sjmallett bit(DATA_DRPENA) is set, than an interrupt is 603215976Sjmallett reported for this event. */ 604215976Sjmallett uint64_t ithena : 1; /**< Inbound Ring Threshold Exceeded Interrupt Enable 605232812Sjmallett If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII]) 606215976Sjmallett and this local interrupt mask bit is set, than an 607215976Sjmallett interrupt is reported for an Inbound Ring Threshold 608215976Sjmallett Exceeded event(IRTHRESH). */ 609215976Sjmallett uint64_t othena : 1; /**< Outbound Ring Threshold Exceeded Interrupt Enable 610232812Sjmallett If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII]) 611215976Sjmallett and this local interrupt mask bit is set, than an 612215976Sjmallett interrupt is reported for an Outbound Ring Threshold 613215976Sjmallett Exceeded event(ORTHRESH). */ 614215976Sjmallett uint64_t ivfena : 1; /**< Inbound DoorBell(IDBELL) Overflow Detected 615232812Sjmallett If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII]) 616215976Sjmallett and this local interrupt mask bit is set, than an 617215976Sjmallett interrupt is reported for an Inbound Doorbell Overflow 618215976Sjmallett event(IDBOVF). */ 619215976Sjmallett uint64_t ovfena : 1; /**< Outbound DoorBell(ODBELL) Overflow Interrupt Enable 620232812Sjmallett If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII]) 621215976Sjmallett and this local interrupt mask bit is set, than an 622215976Sjmallett interrupt is reported for an Outbound Doorbell Overflow 623215976Sjmallett event(ODBOVF). */ 624215976Sjmallett#else 625215976Sjmallett uint64_t ovfena : 1; 626215976Sjmallett uint64_t ivfena : 1; 627215976Sjmallett uint64_t othena : 1; 628215976Sjmallett uint64_t ithena : 1; 629215976Sjmallett uint64_t data_drpena : 1; 630215976Sjmallett uint64_t irunena : 1; 631215976Sjmallett uint64_t orunena : 1; 632215976Sjmallett uint64_t tsena : 1; 633215976Sjmallett uint64_t reserved_8_63 : 56; 634215976Sjmallett#endif 635215976Sjmallett } s; 636232812Sjmallett struct cvmx_mixx_intena_cn52xx { 637232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 638215976Sjmallett uint64_t reserved_7_63 : 57; 639215976Sjmallett uint64_t orunena : 1; /**< ORCNT UnderFlow Detected 640215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 641215976Sjmallett and this local interrupt mask bit is set, than an 642215976Sjmallett interrupt is reported for an ORCNT underflow condition 643215976Sjmallett MIX_ISR[ORUN]. */ 644215976Sjmallett uint64_t irunena : 1; /**< IRCNT UnderFlow Interrupt Enable 645215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 646215976Sjmallett and this local interrupt mask bit is set, than an 647215976Sjmallett interrupt is reported for an IRCNT underflow condition 648215976Sjmallett MIX_ISR[IRUN]. */ 649215976Sjmallett uint64_t data_drpena : 1; /**< Data was dropped due to RX FIFO full Interrupt 650215976Sjmallett enable. If both the global interrupt mask bits 651215976Sjmallett (CIU_INTx_EN*[MII]) and the local interrupt mask 652215976Sjmallett bit(DATA_DRPENA) is set, than an interrupt is 653215976Sjmallett reported for this event. */ 654215976Sjmallett uint64_t ithena : 1; /**< Inbound Ring Threshold Exceeded Interrupt Enable 655215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 656215976Sjmallett and this local interrupt mask bit is set, than an 657215976Sjmallett interrupt is reported for an Inbound Ring Threshold 658215976Sjmallett Exceeded event(IRTHRESH). */ 659215976Sjmallett uint64_t othena : 1; /**< Outbound Ring Threshold Exceeded Interrupt Enable 660215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 661215976Sjmallett and this local interrupt mask bit is set, than an 662215976Sjmallett interrupt is reported for an Outbound Ring Threshold 663215976Sjmallett Exceeded event(ORTHRESH). */ 664215976Sjmallett uint64_t ivfena : 1; /**< Inbound DoorBell(IDBELL) Overflow Detected 665215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 666215976Sjmallett and this local interrupt mask bit is set, than an 667215976Sjmallett interrupt is reported for an Inbound Doorbell Overflow 668215976Sjmallett event(IDBOVF). */ 669215976Sjmallett uint64_t ovfena : 1; /**< Outbound DoorBell(ODBELL) Overflow Interrupt Enable 670215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 671215976Sjmallett and this local interrupt mask bit is set, than an 672215976Sjmallett interrupt is reported for an Outbound Doorbell Overflow 673215976Sjmallett event(ODBOVF). */ 674215976Sjmallett#else 675215976Sjmallett uint64_t ovfena : 1; 676215976Sjmallett uint64_t ivfena : 1; 677215976Sjmallett uint64_t othena : 1; 678215976Sjmallett uint64_t ithena : 1; 679215976Sjmallett uint64_t data_drpena : 1; 680215976Sjmallett uint64_t irunena : 1; 681215976Sjmallett uint64_t orunena : 1; 682215976Sjmallett uint64_t reserved_7_63 : 57; 683215976Sjmallett#endif 684215976Sjmallett } cn52xx; 685215976Sjmallett struct cvmx_mixx_intena_cn52xx cn52xxp1; 686215976Sjmallett struct cvmx_mixx_intena_cn52xx cn56xx; 687215976Sjmallett struct cvmx_mixx_intena_cn52xx cn56xxp1; 688232812Sjmallett struct cvmx_mixx_intena_s cn61xx; 689215976Sjmallett struct cvmx_mixx_intena_s cn63xx; 690215976Sjmallett struct cvmx_mixx_intena_s cn63xxp1; 691232812Sjmallett struct cvmx_mixx_intena_s cn66xx; 692232812Sjmallett struct cvmx_mixx_intena_s cn68xx; 693232812Sjmallett struct cvmx_mixx_intena_s cn68xxp1; 694215976Sjmallett}; 695215976Sjmalletttypedef union cvmx_mixx_intena cvmx_mixx_intena_t; 696215976Sjmallett 697215976Sjmallett/** 698215976Sjmallett * cvmx_mix#_ircnt 699215976Sjmallett * 700215976Sjmallett * MIX_IRCNT = MIX I-Ring Pending Packet Counter 701215976Sjmallett * 702215976Sjmallett * Description: 703215976Sjmallett * NOTE: To write to the MIX_IRCNT register, a device would issue an IOBST directed at the MIO. 704215976Sjmallett * To read the MIX_IRCNT register, a device would issue an IOBLD64 directed at the MIO. 705215976Sjmallett */ 706232812Sjmallettunion cvmx_mixx_ircnt { 707215976Sjmallett uint64_t u64; 708232812Sjmallett struct cvmx_mixx_ircnt_s { 709232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 710215976Sjmallett uint64_t reserved_20_63 : 44; 711215976Sjmallett uint64_t ircnt : 20; /**< Pending \# of I-Ring Packets. 712215976Sjmallett Whenever HW writes a completion code of Done, Trunc, 713215976Sjmallett CRCErr or Err, it increments the IRCNT (to indicate 714215976Sjmallett to SW the \# of pending Input packets in system memory). 715215976Sjmallett NOTE: The HW guarantees that the completion code write 716215976Sjmallett is always visible in system memory BEFORE it increments 717215976Sjmallett the IRCNT. 718215976Sjmallett Reads of IRCNT return the current inbound packet count. 719215976Sjmallett Writes of IRCNT decrement the count by the value 720215976Sjmallett written. 721215976Sjmallett This register is used to generate interrupts to alert 722215976Sjmallett SW of pending inbound MIX packets in system memory. 723215976Sjmallett NOTE: In the case of inbound packets that span multiple 724215976Sjmallett I-Ring entries, SW must keep track of the \# of I-Ring Entries 725215976Sjmallett associated with a given inbound packet to reclaim the 726215976Sjmallett proper \# of I-Ring Entries for re-use. */ 727215976Sjmallett#else 728215976Sjmallett uint64_t ircnt : 20; 729215976Sjmallett uint64_t reserved_20_63 : 44; 730215976Sjmallett#endif 731215976Sjmallett } s; 732215976Sjmallett struct cvmx_mixx_ircnt_s cn52xx; 733215976Sjmallett struct cvmx_mixx_ircnt_s cn52xxp1; 734215976Sjmallett struct cvmx_mixx_ircnt_s cn56xx; 735215976Sjmallett struct cvmx_mixx_ircnt_s cn56xxp1; 736232812Sjmallett struct cvmx_mixx_ircnt_s cn61xx; 737215976Sjmallett struct cvmx_mixx_ircnt_s cn63xx; 738215976Sjmallett struct cvmx_mixx_ircnt_s cn63xxp1; 739232812Sjmallett struct cvmx_mixx_ircnt_s cn66xx; 740232812Sjmallett struct cvmx_mixx_ircnt_s cn68xx; 741232812Sjmallett struct cvmx_mixx_ircnt_s cn68xxp1; 742215976Sjmallett}; 743215976Sjmalletttypedef union cvmx_mixx_ircnt cvmx_mixx_ircnt_t; 744215976Sjmallett 745215976Sjmallett/** 746215976Sjmallett * cvmx_mix#_irhwm 747215976Sjmallett * 748215976Sjmallett * MIX_IRHWM = MIX I-Ring High-Water Mark Threshold Register 749215976Sjmallett * 750215976Sjmallett * Description: 751215976Sjmallett * NOTE: To write to the MIX_IHWM register, a device would issue an IOBST directed at the MIO. 752215976Sjmallett * To read the MIX_IHWM register, a device would issue an IOBLD64 directed at the MIO. 753215976Sjmallett */ 754232812Sjmallettunion cvmx_mixx_irhwm { 755215976Sjmallett uint64_t u64; 756232812Sjmallett struct cvmx_mixx_irhwm_s { 757232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 758215976Sjmallett uint64_t reserved_40_63 : 24; 759215976Sjmallett uint64_t ibplwm : 20; /**< I-Ring BackPressure Low Water Mark Threshold. 760215976Sjmallett When the \#of available I-Ring Entries (IDBELL) 761215976Sjmallett is less than IBPLWM, the AGL-MAC will: 762215976Sjmallett a) In full-duplex mode: send periodic PAUSE packets. 763215976Sjmallett b) In half-duplex mode: Force collisions. 764215976Sjmallett This programmable mechanism is provided as a means 765215976Sjmallett to backpressure input traffic 'early' enough (so 766215976Sjmallett that packets are not 'dropped' by OCTEON). */ 767215976Sjmallett uint64_t irhwm : 20; /**< I-Ring Entry High Water Mark Threshold. 768215976Sjmallett Used to determine when the \# of Inbound packets 769215976Sjmallett in system memory(MIX_IRCNT[IRCNT]) exceeds this IRHWM 770215976Sjmallett threshold. 771232812Sjmallett NOTE: The power-on value of the CIU2_EN_xx_yy_PKT[MII] 772215976Sjmallett interrupt enable bits is zero and must be enabled 773215976Sjmallett to allow interrupts to be reported. */ 774215976Sjmallett#else 775215976Sjmallett uint64_t irhwm : 20; 776215976Sjmallett uint64_t ibplwm : 20; 777215976Sjmallett uint64_t reserved_40_63 : 24; 778215976Sjmallett#endif 779215976Sjmallett } s; 780215976Sjmallett struct cvmx_mixx_irhwm_s cn52xx; 781215976Sjmallett struct cvmx_mixx_irhwm_s cn52xxp1; 782215976Sjmallett struct cvmx_mixx_irhwm_s cn56xx; 783215976Sjmallett struct cvmx_mixx_irhwm_s cn56xxp1; 784232812Sjmallett struct cvmx_mixx_irhwm_s cn61xx; 785215976Sjmallett struct cvmx_mixx_irhwm_s cn63xx; 786215976Sjmallett struct cvmx_mixx_irhwm_s cn63xxp1; 787232812Sjmallett struct cvmx_mixx_irhwm_s cn66xx; 788232812Sjmallett struct cvmx_mixx_irhwm_s cn68xx; 789232812Sjmallett struct cvmx_mixx_irhwm_s cn68xxp1; 790215976Sjmallett}; 791215976Sjmalletttypedef union cvmx_mixx_irhwm cvmx_mixx_irhwm_t; 792215976Sjmallett 793215976Sjmallett/** 794215976Sjmallett * cvmx_mix#_iring1 795215976Sjmallett * 796215976Sjmallett * MIX_IRING1 = MIX Inbound Ring Register \#1 797215976Sjmallett * 798215976Sjmallett * Description: 799215976Sjmallett * NOTE: To write to the MIX_IRING1 register, a device would issue an IOBST directed at the MIO. 800215976Sjmallett * To read the MIX_IRING1 register, a device would issue an IOBLD64 directed at the MIO. 801215976Sjmallett */ 802232812Sjmallettunion cvmx_mixx_iring1 { 803215976Sjmallett uint64_t u64; 804232812Sjmallett struct cvmx_mixx_iring1_s { 805232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 806215976Sjmallett uint64_t reserved_60_63 : 4; 807215976Sjmallett uint64_t isize : 20; /**< Represents the Inbound Ring Buffer's Size(in 8B 808215976Sjmallett words). The ring can be as large as 1M entries. 809215976Sjmallett NOTE: This CSR MUST BE setup written by SW poweron 810215976Sjmallett (when IDBELL/IRCNT=0). */ 811215976Sjmallett uint64_t ibase : 37; /**< Represents the 8B-aligned base address of the first 812215976Sjmallett Inbound Ring entry in system memory. 813215976Sjmallett NOTE: SW MUST ONLY write to this register during 814215976Sjmallett power-on/boot code. */ 815215976Sjmallett uint64_t reserved_0_2 : 3; 816215976Sjmallett#else 817215976Sjmallett uint64_t reserved_0_2 : 3; 818215976Sjmallett uint64_t ibase : 37; 819215976Sjmallett uint64_t isize : 20; 820215976Sjmallett uint64_t reserved_60_63 : 4; 821215976Sjmallett#endif 822215976Sjmallett } s; 823232812Sjmallett struct cvmx_mixx_iring1_cn52xx { 824232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 825215976Sjmallett uint64_t reserved_60_63 : 4; 826215976Sjmallett uint64_t isize : 20; /**< Represents the Inbound Ring Buffer's Size(in 8B 827215976Sjmallett words). The ring can be as large as 1M entries. 828215976Sjmallett NOTE: This CSR MUST BE setup written by SW poweron 829215976Sjmallett (when IDBELL/IRCNT=0). */ 830215976Sjmallett uint64_t reserved_36_39 : 4; 831215976Sjmallett uint64_t ibase : 33; /**< Represents the 8B-aligned base address of the first 832215976Sjmallett Inbound Ring entry in system memory. 833215976Sjmallett NOTE: SW MUST ONLY write to this register during 834215976Sjmallett power-on/boot code. */ 835215976Sjmallett uint64_t reserved_0_2 : 3; 836215976Sjmallett#else 837215976Sjmallett uint64_t reserved_0_2 : 3; 838215976Sjmallett uint64_t ibase : 33; 839215976Sjmallett uint64_t reserved_36_39 : 4; 840215976Sjmallett uint64_t isize : 20; 841215976Sjmallett uint64_t reserved_60_63 : 4; 842215976Sjmallett#endif 843215976Sjmallett } cn52xx; 844215976Sjmallett struct cvmx_mixx_iring1_cn52xx cn52xxp1; 845215976Sjmallett struct cvmx_mixx_iring1_cn52xx cn56xx; 846215976Sjmallett struct cvmx_mixx_iring1_cn52xx cn56xxp1; 847232812Sjmallett struct cvmx_mixx_iring1_s cn61xx; 848215976Sjmallett struct cvmx_mixx_iring1_s cn63xx; 849215976Sjmallett struct cvmx_mixx_iring1_s cn63xxp1; 850232812Sjmallett struct cvmx_mixx_iring1_s cn66xx; 851232812Sjmallett struct cvmx_mixx_iring1_s cn68xx; 852232812Sjmallett struct cvmx_mixx_iring1_s cn68xxp1; 853215976Sjmallett}; 854215976Sjmalletttypedef union cvmx_mixx_iring1 cvmx_mixx_iring1_t; 855215976Sjmallett 856215976Sjmallett/** 857215976Sjmallett * cvmx_mix#_iring2 858215976Sjmallett * 859215976Sjmallett * MIX_IRING2 = MIX Inbound Ring Register \#2 860215976Sjmallett * 861215976Sjmallett * Description: 862215976Sjmallett * NOTE: To write to the MIX_IRING2 register, a device would issue an IOBST directed at the MIO. 863215976Sjmallett * To read the MIX_IRING2 register, a device would issue an IOBLD64 directed at the MIO. 864215976Sjmallett */ 865232812Sjmallettunion cvmx_mixx_iring2 { 866215976Sjmallett uint64_t u64; 867232812Sjmallett struct cvmx_mixx_iring2_s { 868232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 869215976Sjmallett uint64_t reserved_52_63 : 12; 870215976Sjmallett uint64_t itlptr : 20; /**< The Inbound Ring Tail Pointer selects the I-Ring 871215976Sjmallett Entry that the HW will process next. After the HW 872215976Sjmallett completes receiving an inbound packet, it increments 873215976Sjmallett the I-Ring Tail Pointer. [NOTE: The I-Ring Tail 874215976Sjmallett Pointer HW increment is always modulo ISIZE. 875215976Sjmallett NOTE: This field is 'read-only' to SW. */ 876215976Sjmallett uint64_t reserved_20_31 : 12; 877215976Sjmallett uint64_t idbell : 20; /**< Represents the cumulative total of pending 878215976Sjmallett Inbound Ring Buffer Entries. Each I-Ring 879215976Sjmallett Buffer Entry contains 1) an L2/DRAM byte pointer 880215976Sjmallett along with a 2) a Byte Length. 881215976Sjmallett After SW inserts a new entry into the I-Ring Buffer, 882215976Sjmallett it "rings the doorbell for the inbound ring". When 883215976Sjmallett the MIX HW receives the doorbell ring, it advances 884215976Sjmallett the doorbell count for the I-Ring. 885215976Sjmallett SW must never cause the doorbell count for the 886215976Sjmallett I-Ring to exceed the size of the I-ring(ISIZE). 887215976Sjmallett A read of the CSR indicates the current doorbell 888215976Sjmallett count. */ 889215976Sjmallett#else 890215976Sjmallett uint64_t idbell : 20; 891215976Sjmallett uint64_t reserved_20_31 : 12; 892215976Sjmallett uint64_t itlptr : 20; 893215976Sjmallett uint64_t reserved_52_63 : 12; 894215976Sjmallett#endif 895215976Sjmallett } s; 896215976Sjmallett struct cvmx_mixx_iring2_s cn52xx; 897215976Sjmallett struct cvmx_mixx_iring2_s cn52xxp1; 898215976Sjmallett struct cvmx_mixx_iring2_s cn56xx; 899215976Sjmallett struct cvmx_mixx_iring2_s cn56xxp1; 900232812Sjmallett struct cvmx_mixx_iring2_s cn61xx; 901215976Sjmallett struct cvmx_mixx_iring2_s cn63xx; 902215976Sjmallett struct cvmx_mixx_iring2_s cn63xxp1; 903232812Sjmallett struct cvmx_mixx_iring2_s cn66xx; 904232812Sjmallett struct cvmx_mixx_iring2_s cn68xx; 905232812Sjmallett struct cvmx_mixx_iring2_s cn68xxp1; 906215976Sjmallett}; 907215976Sjmalletttypedef union cvmx_mixx_iring2 cvmx_mixx_iring2_t; 908215976Sjmallett 909215976Sjmallett/** 910215976Sjmallett * cvmx_mix#_isr 911215976Sjmallett * 912215976Sjmallett * MIX_ISR = MIX Interrupt/Status Register 913215976Sjmallett * 914215976Sjmallett * Description: 915215976Sjmallett * NOTE: To write to the MIX_ISR register, a device would issue an IOBST directed at the MIO. 916215976Sjmallett * To read the MIX_ISR register, a device would issue an IOBLD64 directed at the MIO. 917215976Sjmallett */ 918232812Sjmallettunion cvmx_mixx_isr { 919215976Sjmallett uint64_t u64; 920232812Sjmallett struct cvmx_mixx_isr_s { 921232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 922215976Sjmallett uint64_t reserved_8_63 : 56; 923215976Sjmallett uint64_t ts : 1; /**< TimeStamp Interrupt 924215976Sjmallett When the \#of pending Timestamp Interrupts (MIX_TSCTL[TSCNT]) 925215976Sjmallett is greater than the TimeStamp Interrupt Threshold 926215976Sjmallett (MIX_CTL[TS_THRESH]) value this interrupt bit is set. 927232812Sjmallett If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII]) 928215976Sjmallett and this local interrupt mask bit is set, than an 929215976Sjmallett interrupt is reported for an Outbound Ring with Timestamp 930215976Sjmallett event (see: MIX_INTENA[TSENA]). */ 931215976Sjmallett uint64_t orun : 1; /**< ORCNT UnderFlow Detected 932215976Sjmallett If SW writes a larger value than what is currently 933215976Sjmallett in the MIX_ORCNT[ORCNT], then HW will report the 934215976Sjmallett underflow condition. 935215976Sjmallett NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero. 936215976Sjmallett NOTE: If an ORUN underflow condition is detected, 937215976Sjmallett the integrity of the MIX/AGL HW state has 938215976Sjmallett been compromised. To recover, SW must issue a 939215976Sjmallett software reset sequence (see: MIX_CTL[RESET] */ 940215976Sjmallett uint64_t irun : 1; /**< IRCNT UnderFlow Detected 941215976Sjmallett If SW writes a larger value than what is currently 942215976Sjmallett in the MIX_IRCNT[IRCNT], then HW will report the 943215976Sjmallett underflow condition. 944215976Sjmallett NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero. 945215976Sjmallett NOTE: If an IRUN underflow condition is detected, 946215976Sjmallett the integrity of the MIX/AGL HW state has 947215976Sjmallett been compromised. To recover, SW must issue a 948215976Sjmallett software reset sequence (see: MIX_CTL[RESET] */ 949215976Sjmallett uint64_t data_drp : 1; /**< Data was dropped due to RX FIFO full 950215976Sjmallett If this does occur, the DATA_DRP is set and the 951232812Sjmallett CIU2_RAW_PKT[MII] bit is set. 952232812Sjmallett If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII]) 953215976Sjmallett and the local interrupt mask bit(DATA_DRPENA) is set, than an 954215976Sjmallett interrupt is reported for this event. */ 955215976Sjmallett uint64_t irthresh : 1; /**< Inbound Ring Packet Threshold Exceeded 956215976Sjmallett When the pending \#inbound packets in system 957215976Sjmallett memory(IRCNT) has exceeded a programmable threshold 958215976Sjmallett (IRHWM), then this bit is set. If this does occur, 959232812Sjmallett the IRTHRESH is set and the CIU2_RAW_PKT[MII] bit 960232812Sjmallett is set if ((MIX_ISR & MIX_INTENA) != 0)). 961232812Sjmallett If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII]) 962215976Sjmallett and the local interrupt mask bit(ITHENA) is set, than an 963215976Sjmallett interrupt is reported for this event. */ 964215976Sjmallett uint64_t orthresh : 1; /**< Outbound Ring Packet Threshold Exceeded 965215976Sjmallett When the pending \#outbound packets in system 966215976Sjmallett memory(ORCNT) has exceeded a programmable threshold 967215976Sjmallett (ORHWM), then this bit is set. If this does occur, 968232812Sjmallett the ORTHRESH is set and the CIU2_RAW_PKT[MII] bit 969232812Sjmallett is set if ((MIX_ISR & MIX_INTENA) != 0)). 970232812Sjmallett If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII]) 971215976Sjmallett and the local interrupt mask bit(OTHENA) is set, than an 972215976Sjmallett interrupt is reported for this event. */ 973215976Sjmallett uint64_t idblovf : 1; /**< Inbound DoorBell(IDBELL) Overflow Detected 974215976Sjmallett If SW attempts to write to the MIX_IRING2[IDBELL] 975215976Sjmallett with a value greater than the remaining \#of 976215976Sjmallett I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then 977215976Sjmallett the following occurs: 978215976Sjmallett 1) The MIX_IRING2[IDBELL] write is IGNORED 979232812Sjmallett 2) The ODBLOVF is set and the CIU2_RAW_PKT[MII] 980232812Sjmallett bit is set if ((MIX_ISR & MIX_INTENA) != 0)). 981232812Sjmallett If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII]) 982215976Sjmallett and the local interrupt mask bit(IVFENA) is set, than an 983215976Sjmallett interrupt is reported for this event. 984215976Sjmallett SW should keep track of the \#I-Ring Entries in use 985215976Sjmallett (ie: cumulative \# of IDBELL writes), and ensure that 986215976Sjmallett future IDBELL writes don't exceed the size of the 987215976Sjmallett I-Ring Buffer (MIX_IRING2[ISIZE]). 988215976Sjmallett SW must reclaim I-Ring Entries by keeping track of the 989215976Sjmallett \#IRing-Entries, and writing to the MIX_IRCNT[IRCNT]. 990215976Sjmallett NOTE: The MIX_IRCNT[IRCNT] register represents the 991215976Sjmallett total \#packets(not IRing Entries) and SW must further 992215976Sjmallett keep track of the \# of I-Ring Entries associated with 993215976Sjmallett each packet as they are processed. 994215976Sjmallett NOTE: There is no recovery from an IDBLOVF Interrupt. 995215976Sjmallett If it occurs, it's an indication that SW has 996215976Sjmallett overwritten the I-Ring buffer, and the only recourse 997215976Sjmallett is a HW reset. */ 998215976Sjmallett uint64_t odblovf : 1; /**< Outbound DoorBell(ODBELL) Overflow Detected 999215976Sjmallett If SW attempts to write to the MIX_ORING2[ODBELL] 1000215976Sjmallett with a value greater than the remaining \#of 1001215976Sjmallett O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then 1002215976Sjmallett the following occurs: 1003215976Sjmallett 1) The MIX_ORING2[ODBELL] write is IGNORED 1004232812Sjmallett 2) The ODBLOVF is set and the CIU2_RAW_PKT[MII] 1005232812Sjmallett bit is set if ((MIX_ISR & MIX_INTENA) != 0)). 1006232812Sjmallett If both the global interrupt mask bits (CIU2_EN_xx_yy_PKT[MII]) 1007215976Sjmallett and the local interrupt mask bit(OVFENA) is set, than an 1008215976Sjmallett interrupt is reported for this event. 1009215976Sjmallett SW should keep track of the \#I-Ring Entries in use 1010215976Sjmallett (ie: cumulative \# of ODBELL writes), and ensure that 1011215976Sjmallett future ODBELL writes don't exceed the size of the 1012215976Sjmallett O-Ring Buffer (MIX_ORING2[OSIZE]). 1013215976Sjmallett SW must reclaim O-Ring Entries by writing to the 1014215976Sjmallett MIX_ORCNT[ORCNT]. . 1015215976Sjmallett NOTE: There is no recovery from an ODBLOVF Interrupt. 1016215976Sjmallett If it occurs, it's an indication that SW has 1017215976Sjmallett overwritten the O-Ring buffer, and the only recourse 1018215976Sjmallett is a HW reset. */ 1019215976Sjmallett#else 1020215976Sjmallett uint64_t odblovf : 1; 1021215976Sjmallett uint64_t idblovf : 1; 1022215976Sjmallett uint64_t orthresh : 1; 1023215976Sjmallett uint64_t irthresh : 1; 1024215976Sjmallett uint64_t data_drp : 1; 1025215976Sjmallett uint64_t irun : 1; 1026215976Sjmallett uint64_t orun : 1; 1027215976Sjmallett uint64_t ts : 1; 1028215976Sjmallett uint64_t reserved_8_63 : 56; 1029215976Sjmallett#endif 1030215976Sjmallett } s; 1031232812Sjmallett struct cvmx_mixx_isr_cn52xx { 1032232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1033215976Sjmallett uint64_t reserved_7_63 : 57; 1034215976Sjmallett uint64_t orun : 1; /**< ORCNT UnderFlow Detected 1035215976Sjmallett If SW writes a larger value than what is currently 1036215976Sjmallett in the MIX_ORCNT[ORCNT], then HW will report the 1037215976Sjmallett underflow condition. 1038215976Sjmallett NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero. 1039215976Sjmallett NOTE: If an ORUN underflow condition is detected, 1040215976Sjmallett the integrity of the MIX/AGL HW state has 1041215976Sjmallett been compromised. To recover, SW must issue a 1042215976Sjmallett software reset sequence (see: MIX_CTL[RESET] */ 1043215976Sjmallett uint64_t irun : 1; /**< IRCNT UnderFlow Detected 1044215976Sjmallett If SW writes a larger value than what is currently 1045215976Sjmallett in the MIX_IRCNT[IRCNT], then HW will report the 1046215976Sjmallett underflow condition. 1047215976Sjmallett NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero. 1048215976Sjmallett NOTE: If an IRUN underflow condition is detected, 1049215976Sjmallett the integrity of the MIX/AGL HW state has 1050215976Sjmallett been compromised. To recover, SW must issue a 1051215976Sjmallett software reset sequence (see: MIX_CTL[RESET] */ 1052215976Sjmallett uint64_t data_drp : 1; /**< Data was dropped due to RX FIFO full 1053215976Sjmallett If this does occur, the DATA_DRP is set and the 1054215976Sjmallett CIU_INTx_SUM0,4[MII] bits are set. 1055215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 1056215976Sjmallett and the local interrupt mask bit(DATA_DRPENA) is set, than an 1057215976Sjmallett interrupt is reported for this event. */ 1058215976Sjmallett uint64_t irthresh : 1; /**< Inbound Ring Packet Threshold Exceeded 1059215976Sjmallett When the pending \#inbound packets in system 1060215976Sjmallett memory(IRCNT) has exceeded a programmable threshold 1061215976Sjmallett (IRHWM), then this bit is set. If this does occur, 1062215976Sjmallett the IRTHRESH is set and the CIU_INTx_SUM0,4[MII] bits 1063215976Sjmallett are set if ((MIX_ISR & MIX_INTENA) != 0)). 1064215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 1065215976Sjmallett and the local interrupt mask bit(ITHENA) is set, than an 1066215976Sjmallett interrupt is reported for this event. */ 1067215976Sjmallett uint64_t orthresh : 1; /**< Outbound Ring Packet Threshold Exceeded 1068215976Sjmallett When the pending \#outbound packets in system 1069215976Sjmallett memory(ORCNT) has exceeded a programmable threshold 1070215976Sjmallett (ORHWM), then this bit is set. If this does occur, 1071215976Sjmallett the ORTHRESH is set and the CIU_INTx_SUM0,4[MII] bits 1072215976Sjmallett are set if ((MIX_ISR & MIX_INTENA) != 0)). 1073215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 1074215976Sjmallett and the local interrupt mask bit(OTHENA) is set, than an 1075215976Sjmallett interrupt is reported for this event. */ 1076215976Sjmallett uint64_t idblovf : 1; /**< Inbound DoorBell(IDBELL) Overflow Detected 1077215976Sjmallett If SW attempts to write to the MIX_IRING2[IDBELL] 1078215976Sjmallett with a value greater than the remaining \#of 1079215976Sjmallett I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then 1080215976Sjmallett the following occurs: 1081215976Sjmallett 1) The MIX_IRING2[IDBELL] write is IGNORED 1082215976Sjmallett 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII] 1083215976Sjmallett bits are set if ((MIX_ISR & MIX_INTENA) != 0)). 1084215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 1085215976Sjmallett and the local interrupt mask bit(IVFENA) is set, than an 1086215976Sjmallett interrupt is reported for this event. 1087215976Sjmallett SW should keep track of the \#I-Ring Entries in use 1088215976Sjmallett (ie: cumulative \# of IDBELL writes), and ensure that 1089215976Sjmallett future IDBELL writes don't exceed the size of the 1090215976Sjmallett I-Ring Buffer (MIX_IRING2[ISIZE]). 1091215976Sjmallett SW must reclaim I-Ring Entries by keeping track of the 1092215976Sjmallett \#IRing-Entries, and writing to the MIX_IRCNT[IRCNT]. 1093215976Sjmallett NOTE: The MIX_IRCNT[IRCNT] register represents the 1094215976Sjmallett total \#packets(not IRing Entries) and SW must further 1095215976Sjmallett keep track of the \# of I-Ring Entries associated with 1096215976Sjmallett each packet as they are processed. 1097215976Sjmallett NOTE: There is no recovery from an IDBLOVF Interrupt. 1098215976Sjmallett If it occurs, it's an indication that SW has 1099215976Sjmallett overwritten the I-Ring buffer, and the only recourse 1100215976Sjmallett is a HW reset. */ 1101215976Sjmallett uint64_t odblovf : 1; /**< Outbound DoorBell(ODBELL) Overflow Detected 1102215976Sjmallett If SW attempts to write to the MIX_ORING2[ODBELL] 1103215976Sjmallett with a value greater than the remaining \#of 1104215976Sjmallett O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then 1105215976Sjmallett the following occurs: 1106215976Sjmallett 1) The MIX_ORING2[ODBELL] write is IGNORED 1107215976Sjmallett 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII] 1108215976Sjmallett bits are set if ((MIX_ISR & MIX_INTENA) != 0)). 1109215976Sjmallett If both the global interrupt mask bits (CIU_INTx_EN*[MII]) 1110215976Sjmallett and the local interrupt mask bit(OVFENA) is set, than an 1111215976Sjmallett interrupt is reported for this event. 1112215976Sjmallett SW should keep track of the \#I-Ring Entries in use 1113215976Sjmallett (ie: cumulative \# of ODBELL writes), and ensure that 1114215976Sjmallett future ODBELL writes don't exceed the size of the 1115215976Sjmallett O-Ring Buffer (MIX_ORING2[OSIZE]). 1116215976Sjmallett SW must reclaim O-Ring Entries by writing to the 1117215976Sjmallett MIX_ORCNT[ORCNT]. . 1118215976Sjmallett NOTE: There is no recovery from an ODBLOVF Interrupt. 1119215976Sjmallett If it occurs, it's an indication that SW has 1120215976Sjmallett overwritten the O-Ring buffer, and the only recourse 1121215976Sjmallett is a HW reset. */ 1122215976Sjmallett#else 1123215976Sjmallett uint64_t odblovf : 1; 1124215976Sjmallett uint64_t idblovf : 1; 1125215976Sjmallett uint64_t orthresh : 1; 1126215976Sjmallett uint64_t irthresh : 1; 1127215976Sjmallett uint64_t data_drp : 1; 1128215976Sjmallett uint64_t irun : 1; 1129215976Sjmallett uint64_t orun : 1; 1130215976Sjmallett uint64_t reserved_7_63 : 57; 1131215976Sjmallett#endif 1132215976Sjmallett } cn52xx; 1133215976Sjmallett struct cvmx_mixx_isr_cn52xx cn52xxp1; 1134215976Sjmallett struct cvmx_mixx_isr_cn52xx cn56xx; 1135215976Sjmallett struct cvmx_mixx_isr_cn52xx cn56xxp1; 1136232812Sjmallett struct cvmx_mixx_isr_s cn61xx; 1137215976Sjmallett struct cvmx_mixx_isr_s cn63xx; 1138215976Sjmallett struct cvmx_mixx_isr_s cn63xxp1; 1139232812Sjmallett struct cvmx_mixx_isr_s cn66xx; 1140232812Sjmallett struct cvmx_mixx_isr_s cn68xx; 1141232812Sjmallett struct cvmx_mixx_isr_s cn68xxp1; 1142215976Sjmallett}; 1143215976Sjmalletttypedef union cvmx_mixx_isr cvmx_mixx_isr_t; 1144215976Sjmallett 1145215976Sjmallett/** 1146215976Sjmallett * cvmx_mix#_orcnt 1147215976Sjmallett * 1148215976Sjmallett * MIX_ORCNT = MIX O-Ring Packets Sent Counter 1149215976Sjmallett * 1150215976Sjmallett * Description: 1151215976Sjmallett * NOTE: To write to the MIX_ORCNT register, a device would issue an IOBST directed at the MIO. 1152215976Sjmallett * To read the MIX_ORCNT register, a device would issue an IOBLD64 directed at the MIO. 1153215976Sjmallett */ 1154232812Sjmallettunion cvmx_mixx_orcnt { 1155215976Sjmallett uint64_t u64; 1156232812Sjmallett struct cvmx_mixx_orcnt_s { 1157232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1158215976Sjmallett uint64_t reserved_20_63 : 44; 1159215976Sjmallett uint64_t orcnt : 20; /**< Pending \# of O-Ring Packets. 1160215976Sjmallett Whenever HW removes a packet from the O-Ring, it 1161215976Sjmallett increments the ORCNT (to indicate to SW the \# of 1162215976Sjmallett Output packets in system memory that can be reclaimed). 1163215976Sjmallett Reads of ORCNT return the current count. 1164215976Sjmallett Writes of ORCNT decrement the count by the value 1165215976Sjmallett written. 1166215976Sjmallett This register is used to generate interrupts to alert 1167215976Sjmallett SW of pending outbound MIX packets that have been 1168215976Sjmallett removed from system memory. (see MIX_ISR[ORTHRESH] 1169215976Sjmallett description for more details). 1170215976Sjmallett NOTE: For outbound packets, the \# of O-Ring Packets 1171215976Sjmallett is equal to the \# of O-Ring Entries. */ 1172215976Sjmallett#else 1173215976Sjmallett uint64_t orcnt : 20; 1174215976Sjmallett uint64_t reserved_20_63 : 44; 1175215976Sjmallett#endif 1176215976Sjmallett } s; 1177215976Sjmallett struct cvmx_mixx_orcnt_s cn52xx; 1178215976Sjmallett struct cvmx_mixx_orcnt_s cn52xxp1; 1179215976Sjmallett struct cvmx_mixx_orcnt_s cn56xx; 1180215976Sjmallett struct cvmx_mixx_orcnt_s cn56xxp1; 1181232812Sjmallett struct cvmx_mixx_orcnt_s cn61xx; 1182215976Sjmallett struct cvmx_mixx_orcnt_s cn63xx; 1183215976Sjmallett struct cvmx_mixx_orcnt_s cn63xxp1; 1184232812Sjmallett struct cvmx_mixx_orcnt_s cn66xx; 1185232812Sjmallett struct cvmx_mixx_orcnt_s cn68xx; 1186232812Sjmallett struct cvmx_mixx_orcnt_s cn68xxp1; 1187215976Sjmallett}; 1188215976Sjmalletttypedef union cvmx_mixx_orcnt cvmx_mixx_orcnt_t; 1189215976Sjmallett 1190215976Sjmallett/** 1191215976Sjmallett * cvmx_mix#_orhwm 1192215976Sjmallett * 1193215976Sjmallett * MIX_ORHWM = MIX O-Ring High-Water Mark Threshold Register 1194215976Sjmallett * 1195215976Sjmallett * Description: 1196215976Sjmallett * NOTE: To write to the MIX_ORHWM register, a device would issue an IOBST directed at the MIO. 1197215976Sjmallett * To read the MIX_ORHWM register, a device would issue an IOBLD64 directed at the MIO. 1198215976Sjmallett */ 1199232812Sjmallettunion cvmx_mixx_orhwm { 1200215976Sjmallett uint64_t u64; 1201232812Sjmallett struct cvmx_mixx_orhwm_s { 1202232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1203215976Sjmallett uint64_t reserved_20_63 : 44; 1204215976Sjmallett uint64_t orhwm : 20; /**< O-Ring Entry High Water Mark Threshold. 1205215976Sjmallett Used to determine when the \# of Outbound packets 1206215976Sjmallett in system memory that can be reclaimed 1207215976Sjmallett (MIX_ORCNT[ORCNT]) exceeds this ORHWM threshold. 1208232812Sjmallett NOTE: The power-on value of the CIU2_EN_xx_yy_PKT[MII] 1209215976Sjmallett interrupt enable bits is zero and must be enabled 1210215976Sjmallett to allow interrupts to be reported. */ 1211215976Sjmallett#else 1212215976Sjmallett uint64_t orhwm : 20; 1213215976Sjmallett uint64_t reserved_20_63 : 44; 1214215976Sjmallett#endif 1215215976Sjmallett } s; 1216215976Sjmallett struct cvmx_mixx_orhwm_s cn52xx; 1217215976Sjmallett struct cvmx_mixx_orhwm_s cn52xxp1; 1218215976Sjmallett struct cvmx_mixx_orhwm_s cn56xx; 1219215976Sjmallett struct cvmx_mixx_orhwm_s cn56xxp1; 1220232812Sjmallett struct cvmx_mixx_orhwm_s cn61xx; 1221215976Sjmallett struct cvmx_mixx_orhwm_s cn63xx; 1222215976Sjmallett struct cvmx_mixx_orhwm_s cn63xxp1; 1223232812Sjmallett struct cvmx_mixx_orhwm_s cn66xx; 1224232812Sjmallett struct cvmx_mixx_orhwm_s cn68xx; 1225232812Sjmallett struct cvmx_mixx_orhwm_s cn68xxp1; 1226215976Sjmallett}; 1227215976Sjmalletttypedef union cvmx_mixx_orhwm cvmx_mixx_orhwm_t; 1228215976Sjmallett 1229215976Sjmallett/** 1230215976Sjmallett * cvmx_mix#_oring1 1231215976Sjmallett * 1232215976Sjmallett * MIX_ORING1 = MIX Outbound Ring Register \#1 1233215976Sjmallett * 1234215976Sjmallett * Description: 1235215976Sjmallett * NOTE: To write to the MIX_ORING1 register, a device would issue an IOBST directed at the MIO. 1236215976Sjmallett * To read the MIX_ORING1 register, a device would issue an IOBLD64 directed at the MIO. 1237215976Sjmallett */ 1238232812Sjmallettunion cvmx_mixx_oring1 { 1239215976Sjmallett uint64_t u64; 1240232812Sjmallett struct cvmx_mixx_oring1_s { 1241232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1242215976Sjmallett uint64_t reserved_60_63 : 4; 1243215976Sjmallett uint64_t osize : 20; /**< Represents the Outbound Ring Buffer's Size(in 8B 1244215976Sjmallett words). The ring can be as large as 1M entries. 1245215976Sjmallett NOTE: This CSR MUST BE setup written by SW poweron 1246215976Sjmallett (when ODBELL/ORCNT=0). */ 1247215976Sjmallett uint64_t obase : 37; /**< Represents the 8B-aligned base address of the first 1248215976Sjmallett Outbound Ring(O-Ring) Entry in system memory. 1249215976Sjmallett NOTE: SW MUST ONLY write to this register during 1250215976Sjmallett power-on/boot code. */ 1251215976Sjmallett uint64_t reserved_0_2 : 3; 1252215976Sjmallett#else 1253215976Sjmallett uint64_t reserved_0_2 : 3; 1254215976Sjmallett uint64_t obase : 37; 1255215976Sjmallett uint64_t osize : 20; 1256215976Sjmallett uint64_t reserved_60_63 : 4; 1257215976Sjmallett#endif 1258215976Sjmallett } s; 1259232812Sjmallett struct cvmx_mixx_oring1_cn52xx { 1260232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1261215976Sjmallett uint64_t reserved_60_63 : 4; 1262215976Sjmallett uint64_t osize : 20; /**< Represents the Outbound Ring Buffer's Size(in 8B 1263215976Sjmallett words). The ring can be as large as 1M entries. 1264215976Sjmallett NOTE: This CSR MUST BE setup written by SW poweron 1265215976Sjmallett (when ODBELL/ORCNT=0). */ 1266215976Sjmallett uint64_t reserved_36_39 : 4; 1267215976Sjmallett uint64_t obase : 33; /**< Represents the 8B-aligned base address of the first 1268215976Sjmallett Outbound Ring(O-Ring) Entry in system memory. 1269215976Sjmallett NOTE: SW MUST ONLY write to this register during 1270215976Sjmallett power-on/boot code. */ 1271215976Sjmallett uint64_t reserved_0_2 : 3; 1272215976Sjmallett#else 1273215976Sjmallett uint64_t reserved_0_2 : 3; 1274215976Sjmallett uint64_t obase : 33; 1275215976Sjmallett uint64_t reserved_36_39 : 4; 1276215976Sjmallett uint64_t osize : 20; 1277215976Sjmallett uint64_t reserved_60_63 : 4; 1278215976Sjmallett#endif 1279215976Sjmallett } cn52xx; 1280215976Sjmallett struct cvmx_mixx_oring1_cn52xx cn52xxp1; 1281215976Sjmallett struct cvmx_mixx_oring1_cn52xx cn56xx; 1282215976Sjmallett struct cvmx_mixx_oring1_cn52xx cn56xxp1; 1283232812Sjmallett struct cvmx_mixx_oring1_s cn61xx; 1284215976Sjmallett struct cvmx_mixx_oring1_s cn63xx; 1285215976Sjmallett struct cvmx_mixx_oring1_s cn63xxp1; 1286232812Sjmallett struct cvmx_mixx_oring1_s cn66xx; 1287232812Sjmallett struct cvmx_mixx_oring1_s cn68xx; 1288232812Sjmallett struct cvmx_mixx_oring1_s cn68xxp1; 1289215976Sjmallett}; 1290215976Sjmalletttypedef union cvmx_mixx_oring1 cvmx_mixx_oring1_t; 1291215976Sjmallett 1292215976Sjmallett/** 1293215976Sjmallett * cvmx_mix#_oring2 1294215976Sjmallett * 1295215976Sjmallett * MIX_ORING2 = MIX Outbound Ring Register \#2 1296215976Sjmallett * 1297215976Sjmallett * Description: 1298215976Sjmallett * NOTE: To write to the MIX_ORING2 register, a device would issue an IOBST directed at the MIO. 1299215976Sjmallett * To read the MIX_ORING2 register, a device would issue an IOBLD64 directed at the MIO. 1300215976Sjmallett */ 1301232812Sjmallettunion cvmx_mixx_oring2 { 1302215976Sjmallett uint64_t u64; 1303232812Sjmallett struct cvmx_mixx_oring2_s { 1304232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1305215976Sjmallett uint64_t reserved_52_63 : 12; 1306215976Sjmallett uint64_t otlptr : 20; /**< The Outbound Ring Tail Pointer selects the O-Ring 1307215976Sjmallett Entry that the HW will process next. After the HW 1308215976Sjmallett completes sending an outbound packet, it increments 1309215976Sjmallett the O-Ring Tail Pointer. [NOTE: The O-Ring Tail 1310215976Sjmallett Pointer HW increment is always modulo 1311215976Sjmallett MIX_ORING2[OSIZE]. 1312215976Sjmallett NOTE: This field is 'read-only' to SW. */ 1313215976Sjmallett uint64_t reserved_20_31 : 12; 1314215976Sjmallett uint64_t odbell : 20; /**< Represents the cumulative total of pending 1315215976Sjmallett Outbound Ring(O-Ring) Buffer Entries. Each O-Ring 1316215976Sjmallett Buffer Entry contains 1) an L2/DRAM byte pointer 1317215976Sjmallett along with a 2) a Byte Length. 1318215976Sjmallett After SW inserts new entries into the O-Ring Buffer, 1319215976Sjmallett it "rings the doorbell with the count of the newly 1320215976Sjmallett inserted entries". When the MIX HW receives the 1321215976Sjmallett doorbell ring, it increments the current doorbell 1322215976Sjmallett count by the CSR write value. 1323215976Sjmallett SW must never cause the doorbell count for the 1324215976Sjmallett O-Ring to exceed the size of the ring(OSIZE). 1325215976Sjmallett A read of the CSR indicates the current doorbell 1326215976Sjmallett count. */ 1327215976Sjmallett#else 1328215976Sjmallett uint64_t odbell : 20; 1329215976Sjmallett uint64_t reserved_20_31 : 12; 1330215976Sjmallett uint64_t otlptr : 20; 1331215976Sjmallett uint64_t reserved_52_63 : 12; 1332215976Sjmallett#endif 1333215976Sjmallett } s; 1334215976Sjmallett struct cvmx_mixx_oring2_s cn52xx; 1335215976Sjmallett struct cvmx_mixx_oring2_s cn52xxp1; 1336215976Sjmallett struct cvmx_mixx_oring2_s cn56xx; 1337215976Sjmallett struct cvmx_mixx_oring2_s cn56xxp1; 1338232812Sjmallett struct cvmx_mixx_oring2_s cn61xx; 1339215976Sjmallett struct cvmx_mixx_oring2_s cn63xx; 1340215976Sjmallett struct cvmx_mixx_oring2_s cn63xxp1; 1341232812Sjmallett struct cvmx_mixx_oring2_s cn66xx; 1342232812Sjmallett struct cvmx_mixx_oring2_s cn68xx; 1343232812Sjmallett struct cvmx_mixx_oring2_s cn68xxp1; 1344215976Sjmallett}; 1345215976Sjmalletttypedef union cvmx_mixx_oring2 cvmx_mixx_oring2_t; 1346215976Sjmallett 1347215976Sjmallett/** 1348215976Sjmallett * cvmx_mix#_remcnt 1349215976Sjmallett * 1350215976Sjmallett * MIX_REMCNT = MIX Ring Buffer Remainder Counts (useful for HW debug only) 1351215976Sjmallett * 1352215976Sjmallett * Description: 1353215976Sjmallett * NOTE: To read the MIX_REMCNT register, a device would issue an IOBLD64 directed at the MIO. 1354215976Sjmallett */ 1355232812Sjmallettunion cvmx_mixx_remcnt { 1356215976Sjmallett uint64_t u64; 1357232812Sjmallett struct cvmx_mixx_remcnt_s { 1358232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1359215976Sjmallett uint64_t reserved_52_63 : 12; 1360215976Sjmallett uint64_t iremcnt : 20; /**< Remaining I-Ring Buffer Count 1361215976Sjmallett Reflects the \# of unused/remaining I-Ring Entries 1362215976Sjmallett that HW currently detects in the I-Ring Buffer. 1363215976Sjmallett HW uses this value to detect I-Ring Doorbell overflows. 1364215976Sjmallett (see: MIX_ISR[IDBLOVF]) 1365215976Sjmallett When SW writes the MIX_IRING1[ISIZE], the IREMCNT 1366215976Sjmallett is loaded with MIX_IRING2[ISIZE] value. (NOTE: ISIZE should only 1367215976Sjmallett be written at power-on, when it's known that there are 1368215976Sjmallett no I-Ring Entries currently in use by HW). 1369215976Sjmallett When SW writes to the IDBELL register, the IREMCNT 1370215976Sjmallett is decremented by the CSR write value. 1371215976Sjmallett When HW issues an IRing Write Request(onto NCB Bus), 1372215976Sjmallett the IREMCNT is incremented by 1. */ 1373215976Sjmallett uint64_t reserved_20_31 : 12; 1374215976Sjmallett uint64_t oremcnt : 20; /**< Remaining O-Ring Buffer Count 1375215976Sjmallett Reflects the \# of unused/remaining O-Ring Entries 1376215976Sjmallett that HW currently detects in the O-Ring Buffer. 1377215976Sjmallett HW uses this value to detect O-Ring Doorbell overflows. 1378215976Sjmallett (see: MIX_ISR[ODBLOVF]) 1379215976Sjmallett When SW writes the MIX_IRING1[OSIZE], the OREMCNT 1380215976Sjmallett is loaded with MIX_ORING2[OSIZE] value. (NOTE: OSIZE should only 1381215976Sjmallett be written at power-on, when it's known that there are 1382215976Sjmallett no O-Ring Entries currently in use by HW). 1383215976Sjmallett When SW writes to the ODBELL register, the OREMCNT 1384215976Sjmallett is decremented by the CSR write value. 1385215976Sjmallett When SW writes to MIX_[OREMCNT], the OREMCNT is decremented 1386215976Sjmallett by the CSR write value. */ 1387215976Sjmallett#else 1388215976Sjmallett uint64_t oremcnt : 20; 1389215976Sjmallett uint64_t reserved_20_31 : 12; 1390215976Sjmallett uint64_t iremcnt : 20; 1391215976Sjmallett uint64_t reserved_52_63 : 12; 1392215976Sjmallett#endif 1393215976Sjmallett } s; 1394215976Sjmallett struct cvmx_mixx_remcnt_s cn52xx; 1395215976Sjmallett struct cvmx_mixx_remcnt_s cn52xxp1; 1396215976Sjmallett struct cvmx_mixx_remcnt_s cn56xx; 1397215976Sjmallett struct cvmx_mixx_remcnt_s cn56xxp1; 1398232812Sjmallett struct cvmx_mixx_remcnt_s cn61xx; 1399215976Sjmallett struct cvmx_mixx_remcnt_s cn63xx; 1400215976Sjmallett struct cvmx_mixx_remcnt_s cn63xxp1; 1401232812Sjmallett struct cvmx_mixx_remcnt_s cn66xx; 1402232812Sjmallett struct cvmx_mixx_remcnt_s cn68xx; 1403232812Sjmallett struct cvmx_mixx_remcnt_s cn68xxp1; 1404215976Sjmallett}; 1405215976Sjmalletttypedef union cvmx_mixx_remcnt cvmx_mixx_remcnt_t; 1406215976Sjmallett 1407215976Sjmallett/** 1408215976Sjmallett * cvmx_mix#_tsctl 1409215976Sjmallett * 1410215976Sjmallett * MIX_TSCTL = MIX TimeStamp Control Register 1411215976Sjmallett * 1412215976Sjmallett * Description: 1413215976Sjmallett * NOTE: To read the MIX_TSCTL register, a device would issue an IOBLD64 directed at the MIO. 1414215976Sjmallett * 1415215976Sjmallett * Notes: 1416215976Sjmallett * SW can read the MIX_TSCTL register to determine the \#pending timestamp interrupts(TSCNT) 1417215976Sjmallett * as well as the \#outstanding timestamp requests in flight(TSTOT), as well as the \#of available 1418215976Sjmallett * timestamp entries (TSAVL) in the timestamp fifo. 1419215976Sjmallett * A write to the MIX_TSCTL register will advance the MIX*_TSTAMP fifo head ptr by 1, and 1420215976Sjmallett * also decrements the MIX*_TSCTL[TSCNT] and MIX*_TSCTL[TSTOT] pending count(s) by 1. 1421215976Sjmallett * For example, if SW reads MIX*_TSCTL[TSCNT]=2 (2 pending timestamp interrupts), it would immediately 1422215976Sjmallett * issue this sequence: 1423215976Sjmallett * 1) MIX*_TSTAMP[TSTAMP] read followed by MIX*_TSCTL write 1424215976Sjmallett * [gets timestamp value/pops timestamp fifo and decrements pending count(s) by 1] 1425215976Sjmallett * 2) MIX*_TSTAMP[TSTAMP] read followed by MIX*_TSCTL write 1426215976Sjmallett * [gets timestamp value/pops timestamp fifo and decrements pending count(s) by 1] 1427215976Sjmallett * 1428215976Sjmallett * SWNOTE: A MIX_TSCTL write when MIX_TSCTL[TSCNT]=0 (ie: TimeStamp Fifo empty), then the write is ignored. 1429215976Sjmallett */ 1430232812Sjmallettunion cvmx_mixx_tsctl { 1431215976Sjmallett uint64_t u64; 1432232812Sjmallett struct cvmx_mixx_tsctl_s { 1433232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1434215976Sjmallett uint64_t reserved_21_63 : 43; 1435215976Sjmallett uint64_t tsavl : 5; /**< # of MIX TimeStamp Entries Available for use 1436215976Sjmallett For o63: TSAVL MAX=4 (implementation 1437215976Sjmallett depth of timestamp fifo) 1438215976Sjmallett TSAVL = [IMPLEMENTATION_DEPTH=4(MAX) - TSCNT] */ 1439215976Sjmallett uint64_t reserved_13_15 : 3; 1440215976Sjmallett uint64_t tstot : 5; /**< # of pending MIX TimeStamp Requests in-flight 1441215976Sjmallett For o63: TSTOT must never exceed MAX=4 (implementation 1442215976Sjmallett depth of timestamp fifo) */ 1443215976Sjmallett uint64_t reserved_5_7 : 3; 1444215976Sjmallett uint64_t tscnt : 5; /**< # of pending MIX TimeStamp Interrupts 1445215976Sjmallett For o63: TSCNT must never exceed MAX=4 (implementation 1446215976Sjmallett depth of timestamp fifo) */ 1447215976Sjmallett#else 1448215976Sjmallett uint64_t tscnt : 5; 1449215976Sjmallett uint64_t reserved_5_7 : 3; 1450215976Sjmallett uint64_t tstot : 5; 1451215976Sjmallett uint64_t reserved_13_15 : 3; 1452215976Sjmallett uint64_t tsavl : 5; 1453215976Sjmallett uint64_t reserved_21_63 : 43; 1454215976Sjmallett#endif 1455215976Sjmallett } s; 1456232812Sjmallett struct cvmx_mixx_tsctl_s cn61xx; 1457215976Sjmallett struct cvmx_mixx_tsctl_s cn63xx; 1458215976Sjmallett struct cvmx_mixx_tsctl_s cn63xxp1; 1459232812Sjmallett struct cvmx_mixx_tsctl_s cn66xx; 1460232812Sjmallett struct cvmx_mixx_tsctl_s cn68xx; 1461232812Sjmallett struct cvmx_mixx_tsctl_s cn68xxp1; 1462215976Sjmallett}; 1463215976Sjmalletttypedef union cvmx_mixx_tsctl cvmx_mixx_tsctl_t; 1464215976Sjmallett 1465215976Sjmallett/** 1466215976Sjmallett * cvmx_mix#_tstamp 1467215976Sjmallett * 1468215976Sjmallett * MIX_TSTAMP = MIX TimeStamp Register 1469215976Sjmallett * 1470215976Sjmallett * Description: 1471215976Sjmallett * NOTE: To read the MIX_TSTAMP register, a device would issue an IOBLD64 directed at the MIO. 1472215976Sjmallett */ 1473232812Sjmallettunion cvmx_mixx_tstamp { 1474215976Sjmallett uint64_t u64; 1475232812Sjmallett struct cvmx_mixx_tstamp_s { 1476232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1477215976Sjmallett uint64_t tstamp : 64; /**< MIX TimeStamp Value 1478215976Sjmallett When SW sets up an ORING Entry with [47]=1(TSTAMP), 1479215976Sjmallett The packet is tagged with a specal SOP w/TSTAMP flag 1480215976Sjmallett as it is sent to the AGL. 1481215976Sjmallett Later the AGL will send "sample" strobe(s) to capture 1482215976Sjmallett a global 64bit timestamp value followed by a "commit" 1483215976Sjmallett strobe which writes the last sampled value into the 1484215976Sjmallett outbound Timestamp fifo (max depth=4) and increments 1485215976Sjmallett the MIX_TSCTL[TSCNT] register to indicate the total 1486215976Sjmallett \#of pending Timestamp interrupts. 1487215976Sjmallett If the \#pending Timestamp interrupts (MIX_TSCTL[TSCNT]) 1488215976Sjmallett is greater than the MIX_CTL[TS_THRESH] value, then 1489215976Sjmallett a programmable interrupt is also triggered (see: 1490215976Sjmallett MIX_ISR[TS] MIX_INTENA[TSENA]). 1491215976Sjmallett SW will then read the MIX*_TSTAMP[TSTAMP] 1492215976Sjmallett register value, and MUST THEN write the MIX_TSCTL 1493215976Sjmallett register, which will decrement MIX_TSCTL[TSCNT] register, 1494215976Sjmallett to indicate that a single timestamp interrupt has 1495215976Sjmallett been serviced. 1496215976Sjmallett NOTE: The MIO-MIX HW tracks upto MAX=4 outstanding 1497215976Sjmallett timestamped outbound packets at a time. All subsequent 1498215976Sjmallett ORING Entries w/SOP-TSTAMP will be stalled until 1499215976Sjmallett SW can service the 4 outstanding interrupts. 1500215976Sjmallett SW can read the MIX_TSCTL register to determine the 1501215976Sjmallett \#pending timestamp interrupts(TSCNT) as well as the 1502215976Sjmallett \#outstanding timestamp requests in flight(TSTOT), as 1503215976Sjmallett well as the \#of available timestamp entries (TSAVL). 1504215976Sjmallett SW NOTE: A MIX_TSTAMP read when MIX_TSCTL[TSCNT]=0, will 1505215976Sjmallett result in a return value of all zeroes. SW should only 1506215976Sjmallett read this register when MIX_ISR[TS]=1 (or when 1507215976Sjmallett MIX_TSCTL[TSCNT] != 0) to retrieve the timestamp value 1508215976Sjmallett recorded by HW. If SW reads the TSTAMP when HW has not 1509215976Sjmallett recorded a valid timestamp, then an all zeroes value is 1510215976Sjmallett returned. */ 1511215976Sjmallett#else 1512215976Sjmallett uint64_t tstamp : 64; 1513215976Sjmallett#endif 1514215976Sjmallett } s; 1515232812Sjmallett struct cvmx_mixx_tstamp_s cn61xx; 1516215976Sjmallett struct cvmx_mixx_tstamp_s cn63xx; 1517215976Sjmallett struct cvmx_mixx_tstamp_s cn63xxp1; 1518232812Sjmallett struct cvmx_mixx_tstamp_s cn66xx; 1519232812Sjmallett struct cvmx_mixx_tstamp_s cn68xx; 1520232812Sjmallett struct cvmx_mixx_tstamp_s cn68xxp1; 1521215976Sjmallett}; 1522215976Sjmalletttypedef union cvmx_mixx_tstamp cvmx_mixx_tstamp_t; 1523215976Sjmallett 1524215976Sjmallett#endif 1525