1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-mio-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon mio. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_MIO_DEFS_H__ 53#define __CVMX_MIO_DEFS_H__ 54 55#define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull)) 56#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 57#define CVMX_MIO_BOOT_COMP CVMX_MIO_BOOT_COMP_FUNC() 58static inline uint64_t CVMX_MIO_BOOT_COMP_FUNC(void) 59{ 60 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 61 cvmx_warn("CVMX_MIO_BOOT_COMP not supported on this chip\n"); 62 return CVMX_ADD_IO_SEG(0x00011800000000B8ull); 63} 64#else 65#define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull)) 66#endif 67#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68static inline uint64_t CVMX_MIO_BOOT_DMA_CFGX(unsigned long offset) 69{ 70 if (!( 71 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 72 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) || 73 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 74 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 75 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 76 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 77 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 78 cvmx_warn("CVMX_MIO_BOOT_DMA_CFGX(%lu) is invalid on this chip\n", offset); 79 return CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8; 80} 81#else 82#define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8) 83#endif 84#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 85static inline uint64_t CVMX_MIO_BOOT_DMA_INTX(unsigned long offset) 86{ 87 if (!( 88 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 89 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) || 90 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 91 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 92 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 93 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 94 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 95 cvmx_warn("CVMX_MIO_BOOT_DMA_INTX(%lu) is invalid on this chip\n", offset); 96 return CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8; 97} 98#else 99#define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8) 100#endif 101#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 102static inline uint64_t CVMX_MIO_BOOT_DMA_INT_ENX(unsigned long offset) 103{ 104 if (!( 105 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 106 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) || 107 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 108 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 109 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 110 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 111 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 112 cvmx_warn("CVMX_MIO_BOOT_DMA_INT_ENX(%lu) is invalid on this chip\n", offset); 113 return CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8; 114} 115#else 116#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8) 117#endif 118#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 119static inline uint64_t CVMX_MIO_BOOT_DMA_TIMX(unsigned long offset) 120{ 121 if (!( 122 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 123 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) || 124 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 125 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 126 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 127 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 128 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 129 cvmx_warn("CVMX_MIO_BOOT_DMA_TIMX(%lu) is invalid on this chip\n", offset); 130 return CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8; 131} 132#else 133#define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8) 134#endif 135#define CVMX_MIO_BOOT_ERR (CVMX_ADD_IO_SEG(0x00011800000000A0ull)) 136#define CVMX_MIO_BOOT_INT (CVMX_ADD_IO_SEG(0x00011800000000A8ull)) 137#define CVMX_MIO_BOOT_LOC_ADR (CVMX_ADD_IO_SEG(0x0001180000000090ull)) 138#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 139static inline uint64_t CVMX_MIO_BOOT_LOC_CFGX(unsigned long offset) 140{ 141 if (!( 142 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 143 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 144 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 145 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 146 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 147 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 148 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 149 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 150 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 151 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 152 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 153 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 154 cvmx_warn("CVMX_MIO_BOOT_LOC_CFGX(%lu) is invalid on this chip\n", offset); 155 return CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8; 156} 157#else 158#define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8) 159#endif 160#define CVMX_MIO_BOOT_LOC_DAT (CVMX_ADD_IO_SEG(0x0001180000000098ull)) 161#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 162#define CVMX_MIO_BOOT_PIN_DEFS CVMX_MIO_BOOT_PIN_DEFS_FUNC() 163static inline uint64_t CVMX_MIO_BOOT_PIN_DEFS_FUNC(void) 164{ 165 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 166 cvmx_warn("CVMX_MIO_BOOT_PIN_DEFS not supported on this chip\n"); 167 return CVMX_ADD_IO_SEG(0x00011800000000C0ull); 168} 169#else 170#define CVMX_MIO_BOOT_PIN_DEFS (CVMX_ADD_IO_SEG(0x00011800000000C0ull)) 171#endif 172#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 173static inline uint64_t CVMX_MIO_BOOT_REG_CFGX(unsigned long offset) 174{ 175 if (!( 176 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 177 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 178 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 179 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 180 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 181 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 182 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 183 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 184 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 185 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 186 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 187 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 188 cvmx_warn("CVMX_MIO_BOOT_REG_CFGX(%lu) is invalid on this chip\n", offset); 189 return CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8; 190} 191#else 192#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8) 193#endif 194#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 195static inline uint64_t CVMX_MIO_BOOT_REG_TIMX(unsigned long offset) 196{ 197 if (!( 198 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 199 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 200 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 201 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 202 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 203 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 204 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 205 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 206 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 207 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 208 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 209 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 210 cvmx_warn("CVMX_MIO_BOOT_REG_TIMX(%lu) is invalid on this chip\n", offset); 211 return CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8; 212} 213#else 214#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8) 215#endif 216#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull)) 217#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 218#define CVMX_MIO_EMM_BUF_DAT CVMX_MIO_EMM_BUF_DAT_FUNC() 219static inline uint64_t CVMX_MIO_EMM_BUF_DAT_FUNC(void) 220{ 221 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 222 cvmx_warn("CVMX_MIO_EMM_BUF_DAT not supported on this chip\n"); 223 return CVMX_ADD_IO_SEG(0x00011800000020E8ull); 224} 225#else 226#define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull)) 227#endif 228#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 229#define CVMX_MIO_EMM_BUF_IDX CVMX_MIO_EMM_BUF_IDX_FUNC() 230static inline uint64_t CVMX_MIO_EMM_BUF_IDX_FUNC(void) 231{ 232 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 233 cvmx_warn("CVMX_MIO_EMM_BUF_IDX not supported on this chip\n"); 234 return CVMX_ADD_IO_SEG(0x00011800000020E0ull); 235} 236#else 237#define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull)) 238#endif 239#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 240#define CVMX_MIO_EMM_CFG CVMX_MIO_EMM_CFG_FUNC() 241static inline uint64_t CVMX_MIO_EMM_CFG_FUNC(void) 242{ 243 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 244 cvmx_warn("CVMX_MIO_EMM_CFG not supported on this chip\n"); 245 return CVMX_ADD_IO_SEG(0x0001180000002000ull); 246} 247#else 248#define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull)) 249#endif 250#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 251#define CVMX_MIO_EMM_CMD CVMX_MIO_EMM_CMD_FUNC() 252static inline uint64_t CVMX_MIO_EMM_CMD_FUNC(void) 253{ 254 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 255 cvmx_warn("CVMX_MIO_EMM_CMD not supported on this chip\n"); 256 return CVMX_ADD_IO_SEG(0x0001180000002058ull); 257} 258#else 259#define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull)) 260#endif 261#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 262#define CVMX_MIO_EMM_DMA CVMX_MIO_EMM_DMA_FUNC() 263static inline uint64_t CVMX_MIO_EMM_DMA_FUNC(void) 264{ 265 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 266 cvmx_warn("CVMX_MIO_EMM_DMA not supported on this chip\n"); 267 return CVMX_ADD_IO_SEG(0x0001180000002050ull); 268} 269#else 270#define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull)) 271#endif 272#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 273#define CVMX_MIO_EMM_INT CVMX_MIO_EMM_INT_FUNC() 274static inline uint64_t CVMX_MIO_EMM_INT_FUNC(void) 275{ 276 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 277 cvmx_warn("CVMX_MIO_EMM_INT not supported on this chip\n"); 278 return CVMX_ADD_IO_SEG(0x0001180000002078ull); 279} 280#else 281#define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull)) 282#endif 283#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 284#define CVMX_MIO_EMM_INT_EN CVMX_MIO_EMM_INT_EN_FUNC() 285static inline uint64_t CVMX_MIO_EMM_INT_EN_FUNC(void) 286{ 287 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 288 cvmx_warn("CVMX_MIO_EMM_INT_EN not supported on this chip\n"); 289 return CVMX_ADD_IO_SEG(0x0001180000002080ull); 290} 291#else 292#define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull)) 293#endif 294#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 295static inline uint64_t CVMX_MIO_EMM_MODEX(unsigned long offset) 296{ 297 if (!( 298 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 299 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 300 cvmx_warn("CVMX_MIO_EMM_MODEX(%lu) is invalid on this chip\n", offset); 301 return CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8; 302} 303#else 304#define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8) 305#endif 306#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 307#define CVMX_MIO_EMM_RCA CVMX_MIO_EMM_RCA_FUNC() 308static inline uint64_t CVMX_MIO_EMM_RCA_FUNC(void) 309{ 310 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 311 cvmx_warn("CVMX_MIO_EMM_RCA not supported on this chip\n"); 312 return CVMX_ADD_IO_SEG(0x00011800000020A0ull); 313} 314#else 315#define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull)) 316#endif 317#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 318#define CVMX_MIO_EMM_RSP_HI CVMX_MIO_EMM_RSP_HI_FUNC() 319static inline uint64_t CVMX_MIO_EMM_RSP_HI_FUNC(void) 320{ 321 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 322 cvmx_warn("CVMX_MIO_EMM_RSP_HI not supported on this chip\n"); 323 return CVMX_ADD_IO_SEG(0x0001180000002070ull); 324} 325#else 326#define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull)) 327#endif 328#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 329#define CVMX_MIO_EMM_RSP_LO CVMX_MIO_EMM_RSP_LO_FUNC() 330static inline uint64_t CVMX_MIO_EMM_RSP_LO_FUNC(void) 331{ 332 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 333 cvmx_warn("CVMX_MIO_EMM_RSP_LO not supported on this chip\n"); 334 return CVMX_ADD_IO_SEG(0x0001180000002068ull); 335} 336#else 337#define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull)) 338#endif 339#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 340#define CVMX_MIO_EMM_RSP_STS CVMX_MIO_EMM_RSP_STS_FUNC() 341static inline uint64_t CVMX_MIO_EMM_RSP_STS_FUNC(void) 342{ 343 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 344 cvmx_warn("CVMX_MIO_EMM_RSP_STS not supported on this chip\n"); 345 return CVMX_ADD_IO_SEG(0x0001180000002060ull); 346} 347#else 348#define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull)) 349#endif 350#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 351#define CVMX_MIO_EMM_SAMPLE CVMX_MIO_EMM_SAMPLE_FUNC() 352static inline uint64_t CVMX_MIO_EMM_SAMPLE_FUNC(void) 353{ 354 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 355 cvmx_warn("CVMX_MIO_EMM_SAMPLE not supported on this chip\n"); 356 return CVMX_ADD_IO_SEG(0x0001180000002090ull); 357} 358#else 359#define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull)) 360#endif 361#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 362#define CVMX_MIO_EMM_STS_MASK CVMX_MIO_EMM_STS_MASK_FUNC() 363static inline uint64_t CVMX_MIO_EMM_STS_MASK_FUNC(void) 364{ 365 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 366 cvmx_warn("CVMX_MIO_EMM_STS_MASK not supported on this chip\n"); 367 return CVMX_ADD_IO_SEG(0x0001180000002098ull); 368} 369#else 370#define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull)) 371#endif 372#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 373#define CVMX_MIO_EMM_SWITCH CVMX_MIO_EMM_SWITCH_FUNC() 374static inline uint64_t CVMX_MIO_EMM_SWITCH_FUNC(void) 375{ 376 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 377 cvmx_warn("CVMX_MIO_EMM_SWITCH not supported on this chip\n"); 378 return CVMX_ADD_IO_SEG(0x0001180000002048ull); 379} 380#else 381#define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull)) 382#endif 383#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 384#define CVMX_MIO_EMM_WDOG CVMX_MIO_EMM_WDOG_FUNC() 385static inline uint64_t CVMX_MIO_EMM_WDOG_FUNC(void) 386{ 387 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 388 cvmx_warn("CVMX_MIO_EMM_WDOG not supported on this chip\n"); 389 return CVMX_ADD_IO_SEG(0x0001180000002088ull); 390} 391#else 392#define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull)) 393#endif 394#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 395static inline uint64_t CVMX_MIO_FUS_BNK_DATX(unsigned long offset) 396{ 397 if (!( 398 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 399 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 400 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) || 401 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) || 402 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 403 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 404 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 405 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 406 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 407 cvmx_warn("CVMX_MIO_FUS_BNK_DATX(%lu) is invalid on this chip\n", offset); 408 return CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8; 409} 410#else 411#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8) 412#endif 413#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull)) 414#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull)) 415#define CVMX_MIO_FUS_DAT2 (CVMX_ADD_IO_SEG(0x0001180000001410ull)) 416#define CVMX_MIO_FUS_DAT3 (CVMX_ADD_IO_SEG(0x0001180000001418ull)) 417#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 418#define CVMX_MIO_FUS_EMA CVMX_MIO_FUS_EMA_FUNC() 419static inline uint64_t CVMX_MIO_FUS_EMA_FUNC(void) 420{ 421 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 422 cvmx_warn("CVMX_MIO_FUS_EMA not supported on this chip\n"); 423 return CVMX_ADD_IO_SEG(0x0001180000001550ull); 424} 425#else 426#define CVMX_MIO_FUS_EMA (CVMX_ADD_IO_SEG(0x0001180000001550ull)) 427#endif 428#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 429#define CVMX_MIO_FUS_PDF CVMX_MIO_FUS_PDF_FUNC() 430static inline uint64_t CVMX_MIO_FUS_PDF_FUNC(void) 431{ 432 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 433 cvmx_warn("CVMX_MIO_FUS_PDF not supported on this chip\n"); 434 return CVMX_ADD_IO_SEG(0x0001180000001420ull); 435} 436#else 437#define CVMX_MIO_FUS_PDF (CVMX_ADD_IO_SEG(0x0001180000001420ull)) 438#endif 439#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 440#define CVMX_MIO_FUS_PLL CVMX_MIO_FUS_PLL_FUNC() 441static inline uint64_t CVMX_MIO_FUS_PLL_FUNC(void) 442{ 443 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 444 cvmx_warn("CVMX_MIO_FUS_PLL not supported on this chip\n"); 445 return CVMX_ADD_IO_SEG(0x0001180000001580ull); 446} 447#else 448#define CVMX_MIO_FUS_PLL (CVMX_ADD_IO_SEG(0x0001180000001580ull)) 449#endif 450#define CVMX_MIO_FUS_PROG (CVMX_ADD_IO_SEG(0x0001180000001510ull)) 451#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452#define CVMX_MIO_FUS_PROG_TIMES CVMX_MIO_FUS_PROG_TIMES_FUNC() 453static inline uint64_t CVMX_MIO_FUS_PROG_TIMES_FUNC(void) 454{ 455 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 456 cvmx_warn("CVMX_MIO_FUS_PROG_TIMES not supported on this chip\n"); 457 return CVMX_ADD_IO_SEG(0x0001180000001518ull); 458} 459#else 460#define CVMX_MIO_FUS_PROG_TIMES (CVMX_ADD_IO_SEG(0x0001180000001518ull)) 461#endif 462#define CVMX_MIO_FUS_RCMD (CVMX_ADD_IO_SEG(0x0001180000001500ull)) 463#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 464#define CVMX_MIO_FUS_READ_TIMES CVMX_MIO_FUS_READ_TIMES_FUNC() 465static inline uint64_t CVMX_MIO_FUS_READ_TIMES_FUNC(void) 466{ 467 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 468 cvmx_warn("CVMX_MIO_FUS_READ_TIMES not supported on this chip\n"); 469 return CVMX_ADD_IO_SEG(0x0001180000001570ull); 470} 471#else 472#define CVMX_MIO_FUS_READ_TIMES (CVMX_ADD_IO_SEG(0x0001180000001570ull)) 473#endif 474#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 475#define CVMX_MIO_FUS_REPAIR_RES0 CVMX_MIO_FUS_REPAIR_RES0_FUNC() 476static inline uint64_t CVMX_MIO_FUS_REPAIR_RES0_FUNC(void) 477{ 478 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 479 cvmx_warn("CVMX_MIO_FUS_REPAIR_RES0 not supported on this chip\n"); 480 return CVMX_ADD_IO_SEG(0x0001180000001558ull); 481} 482#else 483#define CVMX_MIO_FUS_REPAIR_RES0 (CVMX_ADD_IO_SEG(0x0001180000001558ull)) 484#endif 485#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 486#define CVMX_MIO_FUS_REPAIR_RES1 CVMX_MIO_FUS_REPAIR_RES1_FUNC() 487static inline uint64_t CVMX_MIO_FUS_REPAIR_RES1_FUNC(void) 488{ 489 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 490 cvmx_warn("CVMX_MIO_FUS_REPAIR_RES1 not supported on this chip\n"); 491 return CVMX_ADD_IO_SEG(0x0001180000001560ull); 492} 493#else 494#define CVMX_MIO_FUS_REPAIR_RES1 (CVMX_ADD_IO_SEG(0x0001180000001560ull)) 495#endif 496#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 497#define CVMX_MIO_FUS_REPAIR_RES2 CVMX_MIO_FUS_REPAIR_RES2_FUNC() 498static inline uint64_t CVMX_MIO_FUS_REPAIR_RES2_FUNC(void) 499{ 500 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 501 cvmx_warn("CVMX_MIO_FUS_REPAIR_RES2 not supported on this chip\n"); 502 return CVMX_ADD_IO_SEG(0x0001180000001568ull); 503} 504#else 505#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull)) 506#endif 507#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull)) 508#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull)) 509#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 510#define CVMX_MIO_FUS_TGG CVMX_MIO_FUS_TGG_FUNC() 511static inline uint64_t CVMX_MIO_FUS_TGG_FUNC(void) 512{ 513 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 514 cvmx_warn("CVMX_MIO_FUS_TGG not supported on this chip\n"); 515 return CVMX_ADD_IO_SEG(0x0001180000001428ull); 516} 517#else 518#define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull)) 519#endif 520#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 521#define CVMX_MIO_FUS_UNLOCK CVMX_MIO_FUS_UNLOCK_FUNC() 522static inline uint64_t CVMX_MIO_FUS_UNLOCK_FUNC(void) 523{ 524 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX))) 525 cvmx_warn("CVMX_MIO_FUS_UNLOCK not supported on this chip\n"); 526 return CVMX_ADD_IO_SEG(0x0001180000001578ull); 527} 528#else 529#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull)) 530#endif 531#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull)) 532#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 533#define CVMX_MIO_GPIO_COMP CVMX_MIO_GPIO_COMP_FUNC() 534static inline uint64_t CVMX_MIO_GPIO_COMP_FUNC(void) 535{ 536 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 537 cvmx_warn("CVMX_MIO_GPIO_COMP not supported on this chip\n"); 538 return CVMX_ADD_IO_SEG(0x00011800000000C8ull); 539} 540#else 541#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull)) 542#endif 543#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 544#define CVMX_MIO_NDF_DMA_CFG CVMX_MIO_NDF_DMA_CFG_FUNC() 545static inline uint64_t CVMX_MIO_NDF_DMA_CFG_FUNC(void) 546{ 547 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 548 cvmx_warn("CVMX_MIO_NDF_DMA_CFG not supported on this chip\n"); 549 return CVMX_ADD_IO_SEG(0x0001180000000168ull); 550} 551#else 552#define CVMX_MIO_NDF_DMA_CFG (CVMX_ADD_IO_SEG(0x0001180000000168ull)) 553#endif 554#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 555#define CVMX_MIO_NDF_DMA_INT CVMX_MIO_NDF_DMA_INT_FUNC() 556static inline uint64_t CVMX_MIO_NDF_DMA_INT_FUNC(void) 557{ 558 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 559 cvmx_warn("CVMX_MIO_NDF_DMA_INT not supported on this chip\n"); 560 return CVMX_ADD_IO_SEG(0x0001180000000170ull); 561} 562#else 563#define CVMX_MIO_NDF_DMA_INT (CVMX_ADD_IO_SEG(0x0001180000000170ull)) 564#endif 565#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 566#define CVMX_MIO_NDF_DMA_INT_EN CVMX_MIO_NDF_DMA_INT_EN_FUNC() 567static inline uint64_t CVMX_MIO_NDF_DMA_INT_EN_FUNC(void) 568{ 569 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 570 cvmx_warn("CVMX_MIO_NDF_DMA_INT_EN not supported on this chip\n"); 571 return CVMX_ADD_IO_SEG(0x0001180000000178ull); 572} 573#else 574#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull)) 575#endif 576#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 577#define CVMX_MIO_PLL_CTL CVMX_MIO_PLL_CTL_FUNC() 578static inline uint64_t CVMX_MIO_PLL_CTL_FUNC(void) 579{ 580 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX))) 581 cvmx_warn("CVMX_MIO_PLL_CTL not supported on this chip\n"); 582 return CVMX_ADD_IO_SEG(0x0001180000001448ull); 583} 584#else 585#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull)) 586#endif 587#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 588#define CVMX_MIO_PLL_SETTING CVMX_MIO_PLL_SETTING_FUNC() 589static inline uint64_t CVMX_MIO_PLL_SETTING_FUNC(void) 590{ 591 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX))) 592 cvmx_warn("CVMX_MIO_PLL_SETTING not supported on this chip\n"); 593 return CVMX_ADD_IO_SEG(0x0001180000001440ull); 594} 595#else 596#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull)) 597#endif 598#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 599#define CVMX_MIO_PTP_CKOUT_HI_INCR CVMX_MIO_PTP_CKOUT_HI_INCR_FUNC() 600static inline uint64_t CVMX_MIO_PTP_CKOUT_HI_INCR_FUNC(void) 601{ 602 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 603 cvmx_warn("CVMX_MIO_PTP_CKOUT_HI_INCR not supported on this chip\n"); 604 return CVMX_ADD_IO_SEG(0x0001070000000F40ull); 605} 606#else 607#define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull)) 608#endif 609#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 610#define CVMX_MIO_PTP_CKOUT_LO_INCR CVMX_MIO_PTP_CKOUT_LO_INCR_FUNC() 611static inline uint64_t CVMX_MIO_PTP_CKOUT_LO_INCR_FUNC(void) 612{ 613 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 614 cvmx_warn("CVMX_MIO_PTP_CKOUT_LO_INCR not supported on this chip\n"); 615 return CVMX_ADD_IO_SEG(0x0001070000000F48ull); 616} 617#else 618#define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull)) 619#endif 620#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 621#define CVMX_MIO_PTP_CKOUT_THRESH_HI CVMX_MIO_PTP_CKOUT_THRESH_HI_FUNC() 622static inline uint64_t CVMX_MIO_PTP_CKOUT_THRESH_HI_FUNC(void) 623{ 624 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 625 cvmx_warn("CVMX_MIO_PTP_CKOUT_THRESH_HI not supported on this chip\n"); 626 return CVMX_ADD_IO_SEG(0x0001070000000F38ull); 627} 628#else 629#define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull)) 630#endif 631#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 632#define CVMX_MIO_PTP_CKOUT_THRESH_LO CVMX_MIO_PTP_CKOUT_THRESH_LO_FUNC() 633static inline uint64_t CVMX_MIO_PTP_CKOUT_THRESH_LO_FUNC(void) 634{ 635 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 636 cvmx_warn("CVMX_MIO_PTP_CKOUT_THRESH_LO not supported on this chip\n"); 637 return CVMX_ADD_IO_SEG(0x0001070000000F30ull); 638} 639#else 640#define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull)) 641#endif 642#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 643#define CVMX_MIO_PTP_CLOCK_CFG CVMX_MIO_PTP_CLOCK_CFG_FUNC() 644static inline uint64_t CVMX_MIO_PTP_CLOCK_CFG_FUNC(void) 645{ 646 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 647 cvmx_warn("CVMX_MIO_PTP_CLOCK_CFG not supported on this chip\n"); 648 return CVMX_ADD_IO_SEG(0x0001070000000F00ull); 649} 650#else 651#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull)) 652#endif 653#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 654#define CVMX_MIO_PTP_CLOCK_COMP CVMX_MIO_PTP_CLOCK_COMP_FUNC() 655static inline uint64_t CVMX_MIO_PTP_CLOCK_COMP_FUNC(void) 656{ 657 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 658 cvmx_warn("CVMX_MIO_PTP_CLOCK_COMP not supported on this chip\n"); 659 return CVMX_ADD_IO_SEG(0x0001070000000F18ull); 660} 661#else 662#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull)) 663#endif 664#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 665#define CVMX_MIO_PTP_CLOCK_HI CVMX_MIO_PTP_CLOCK_HI_FUNC() 666static inline uint64_t CVMX_MIO_PTP_CLOCK_HI_FUNC(void) 667{ 668 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 669 cvmx_warn("CVMX_MIO_PTP_CLOCK_HI not supported on this chip\n"); 670 return CVMX_ADD_IO_SEG(0x0001070000000F10ull); 671} 672#else 673#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull)) 674#endif 675#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 676#define CVMX_MIO_PTP_CLOCK_LO CVMX_MIO_PTP_CLOCK_LO_FUNC() 677static inline uint64_t CVMX_MIO_PTP_CLOCK_LO_FUNC(void) 678{ 679 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 680 cvmx_warn("CVMX_MIO_PTP_CLOCK_LO not supported on this chip\n"); 681 return CVMX_ADD_IO_SEG(0x0001070000000F08ull); 682} 683#else 684#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull)) 685#endif 686#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 687#define CVMX_MIO_PTP_EVT_CNT CVMX_MIO_PTP_EVT_CNT_FUNC() 688static inline uint64_t CVMX_MIO_PTP_EVT_CNT_FUNC(void) 689{ 690 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 691 cvmx_warn("CVMX_MIO_PTP_EVT_CNT not supported on this chip\n"); 692 return CVMX_ADD_IO_SEG(0x0001070000000F28ull); 693} 694#else 695#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull)) 696#endif 697#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 698#define CVMX_MIO_PTP_PHY_1PPS_IN CVMX_MIO_PTP_PHY_1PPS_IN_FUNC() 699static inline uint64_t CVMX_MIO_PTP_PHY_1PPS_IN_FUNC(void) 700{ 701 if (!(OCTEON_IS_MODEL(OCTEON_CNF71XX))) 702 cvmx_warn("CVMX_MIO_PTP_PHY_1PPS_IN not supported on this chip\n"); 703 return CVMX_ADD_IO_SEG(0x0001070000000F70ull); 704} 705#else 706#define CVMX_MIO_PTP_PHY_1PPS_IN (CVMX_ADD_IO_SEG(0x0001070000000F70ull)) 707#endif 708#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 709#define CVMX_MIO_PTP_PPS_HI_INCR CVMX_MIO_PTP_PPS_HI_INCR_FUNC() 710static inline uint64_t CVMX_MIO_PTP_PPS_HI_INCR_FUNC(void) 711{ 712 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 713 cvmx_warn("CVMX_MIO_PTP_PPS_HI_INCR not supported on this chip\n"); 714 return CVMX_ADD_IO_SEG(0x0001070000000F60ull); 715} 716#else 717#define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull)) 718#endif 719#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 720#define CVMX_MIO_PTP_PPS_LO_INCR CVMX_MIO_PTP_PPS_LO_INCR_FUNC() 721static inline uint64_t CVMX_MIO_PTP_PPS_LO_INCR_FUNC(void) 722{ 723 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 724 cvmx_warn("CVMX_MIO_PTP_PPS_LO_INCR not supported on this chip\n"); 725 return CVMX_ADD_IO_SEG(0x0001070000000F68ull); 726} 727#else 728#define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull)) 729#endif 730#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 731#define CVMX_MIO_PTP_PPS_THRESH_HI CVMX_MIO_PTP_PPS_THRESH_HI_FUNC() 732static inline uint64_t CVMX_MIO_PTP_PPS_THRESH_HI_FUNC(void) 733{ 734 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 735 cvmx_warn("CVMX_MIO_PTP_PPS_THRESH_HI not supported on this chip\n"); 736 return CVMX_ADD_IO_SEG(0x0001070000000F58ull); 737} 738#else 739#define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull)) 740#endif 741#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 742#define CVMX_MIO_PTP_PPS_THRESH_LO CVMX_MIO_PTP_PPS_THRESH_LO_FUNC() 743static inline uint64_t CVMX_MIO_PTP_PPS_THRESH_LO_FUNC(void) 744{ 745 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 746 cvmx_warn("CVMX_MIO_PTP_PPS_THRESH_LO not supported on this chip\n"); 747 return CVMX_ADD_IO_SEG(0x0001070000000F50ull); 748} 749#else 750#define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull)) 751#endif 752#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 753#define CVMX_MIO_PTP_TIMESTAMP CVMX_MIO_PTP_TIMESTAMP_FUNC() 754static inline uint64_t CVMX_MIO_PTP_TIMESTAMP_FUNC(void) 755{ 756 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 757 cvmx_warn("CVMX_MIO_PTP_TIMESTAMP not supported on this chip\n"); 758 return CVMX_ADD_IO_SEG(0x0001070000000F20ull); 759} 760#else 761#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull)) 762#endif 763#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 764static inline uint64_t CVMX_MIO_QLMX_CFG(unsigned long offset) 765{ 766 if (!( 767 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 2))) || 768 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 2))) || 769 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 4))) || 770 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 771 cvmx_warn("CVMX_MIO_QLMX_CFG(%lu) is invalid on this chip\n", offset); 772 return CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8; 773} 774#else 775#define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8) 776#endif 777#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 778#define CVMX_MIO_RST_BOOT CVMX_MIO_RST_BOOT_FUNC() 779static inline uint64_t CVMX_MIO_RST_BOOT_FUNC(void) 780{ 781 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 782 cvmx_warn("CVMX_MIO_RST_BOOT not supported on this chip\n"); 783 return CVMX_ADD_IO_SEG(0x0001180000001600ull); 784} 785#else 786#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull)) 787#endif 788#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 789#define CVMX_MIO_RST_CFG CVMX_MIO_RST_CFG_FUNC() 790static inline uint64_t CVMX_MIO_RST_CFG_FUNC(void) 791{ 792 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 793 cvmx_warn("CVMX_MIO_RST_CFG not supported on this chip\n"); 794 return CVMX_ADD_IO_SEG(0x0001180000001610ull); 795} 796#else 797#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull)) 798#endif 799#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 800#define CVMX_MIO_RST_CKILL CVMX_MIO_RST_CKILL_FUNC() 801static inline uint64_t CVMX_MIO_RST_CKILL_FUNC(void) 802{ 803 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 804 cvmx_warn("CVMX_MIO_RST_CKILL not supported on this chip\n"); 805 return CVMX_ADD_IO_SEG(0x0001180000001638ull); 806} 807#else 808#define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull)) 809#endif 810#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 811static inline uint64_t CVMX_MIO_RST_CNTLX(unsigned long offset) 812{ 813 if (!( 814 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 815 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) || 816 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 817 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 818 cvmx_warn("CVMX_MIO_RST_CNTLX(%lu) is invalid on this chip\n", offset); 819 return CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8; 820} 821#else 822#define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8) 823#endif 824#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 825static inline uint64_t CVMX_MIO_RST_CTLX(unsigned long offset) 826{ 827 if (!( 828 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 829 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 830 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 831 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 832 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 833 cvmx_warn("CVMX_MIO_RST_CTLX(%lu) is invalid on this chip\n", offset); 834 return CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8; 835} 836#else 837#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8) 838#endif 839#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 840#define CVMX_MIO_RST_DELAY CVMX_MIO_RST_DELAY_FUNC() 841static inline uint64_t CVMX_MIO_RST_DELAY_FUNC(void) 842{ 843 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 844 cvmx_warn("CVMX_MIO_RST_DELAY not supported on this chip\n"); 845 return CVMX_ADD_IO_SEG(0x0001180000001608ull); 846} 847#else 848#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull)) 849#endif 850#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 851#define CVMX_MIO_RST_INT CVMX_MIO_RST_INT_FUNC() 852static inline uint64_t CVMX_MIO_RST_INT_FUNC(void) 853{ 854 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 855 cvmx_warn("CVMX_MIO_RST_INT not supported on this chip\n"); 856 return CVMX_ADD_IO_SEG(0x0001180000001628ull); 857} 858#else 859#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull)) 860#endif 861#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 862#define CVMX_MIO_RST_INT_EN CVMX_MIO_RST_INT_EN_FUNC() 863static inline uint64_t CVMX_MIO_RST_INT_EN_FUNC(void) 864{ 865 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 866 cvmx_warn("CVMX_MIO_RST_INT_EN not supported on this chip\n"); 867 return CVMX_ADD_IO_SEG(0x0001180000001630ull); 868} 869#else 870#define CVMX_MIO_RST_INT_EN (CVMX_ADD_IO_SEG(0x0001180000001630ull)) 871#endif 872#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 873static inline uint64_t CVMX_MIO_TWSX_INT(unsigned long offset) 874{ 875 if (!( 876 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 877 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) || 878 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) || 879 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) || 880 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 881 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 882 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) || 883 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 884 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 885 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 886 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 887 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 888 cvmx_warn("CVMX_MIO_TWSX_INT(%lu) is invalid on this chip\n", offset); 889 return CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512; 890} 891#else 892#define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512) 893#endif 894#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 895static inline uint64_t CVMX_MIO_TWSX_SW_TWSI(unsigned long offset) 896{ 897 if (!( 898 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 899 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) || 900 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) || 901 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) || 902 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 903 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 904 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) || 905 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 906 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 907 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 908 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 909 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 910 cvmx_warn("CVMX_MIO_TWSX_SW_TWSI(%lu) is invalid on this chip\n", offset); 911 return CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512; 912} 913#else 914#define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512) 915#endif 916#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 917static inline uint64_t CVMX_MIO_TWSX_SW_TWSI_EXT(unsigned long offset) 918{ 919 if (!( 920 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 921 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) || 922 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) || 923 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) || 924 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 925 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 926 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) || 927 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 928 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 929 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 930 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 931 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 932 cvmx_warn("CVMX_MIO_TWSX_SW_TWSI_EXT(%lu) is invalid on this chip\n", offset); 933 return CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512; 934} 935#else 936#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512) 937#endif 938#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 939static inline uint64_t CVMX_MIO_TWSX_TWSI_SW(unsigned long offset) 940{ 941 if (!( 942 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 943 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) || 944 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) || 945 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) || 946 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 947 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 948 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) || 949 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 950 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 951 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 952 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 953 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 954 cvmx_warn("CVMX_MIO_TWSX_TWSI_SW(%lu) is invalid on this chip\n", offset); 955 return CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512; 956} 957#else 958#define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512) 959#endif 960#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 961#define CVMX_MIO_UART2_DLH CVMX_MIO_UART2_DLH_FUNC() 962static inline uint64_t CVMX_MIO_UART2_DLH_FUNC(void) 963{ 964 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 965 cvmx_warn("CVMX_MIO_UART2_DLH not supported on this chip\n"); 966 return CVMX_ADD_IO_SEG(0x0001180000000488ull); 967} 968#else 969#define CVMX_MIO_UART2_DLH (CVMX_ADD_IO_SEG(0x0001180000000488ull)) 970#endif 971#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 972#define CVMX_MIO_UART2_DLL CVMX_MIO_UART2_DLL_FUNC() 973static inline uint64_t CVMX_MIO_UART2_DLL_FUNC(void) 974{ 975 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 976 cvmx_warn("CVMX_MIO_UART2_DLL not supported on this chip\n"); 977 return CVMX_ADD_IO_SEG(0x0001180000000480ull); 978} 979#else 980#define CVMX_MIO_UART2_DLL (CVMX_ADD_IO_SEG(0x0001180000000480ull)) 981#endif 982#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 983#define CVMX_MIO_UART2_FAR CVMX_MIO_UART2_FAR_FUNC() 984static inline uint64_t CVMX_MIO_UART2_FAR_FUNC(void) 985{ 986 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 987 cvmx_warn("CVMX_MIO_UART2_FAR not supported on this chip\n"); 988 return CVMX_ADD_IO_SEG(0x0001180000000520ull); 989} 990#else 991#define CVMX_MIO_UART2_FAR (CVMX_ADD_IO_SEG(0x0001180000000520ull)) 992#endif 993#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 994#define CVMX_MIO_UART2_FCR CVMX_MIO_UART2_FCR_FUNC() 995static inline uint64_t CVMX_MIO_UART2_FCR_FUNC(void) 996{ 997 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 998 cvmx_warn("CVMX_MIO_UART2_FCR not supported on this chip\n"); 999 return CVMX_ADD_IO_SEG(0x0001180000000450ull); 1000} 1001#else 1002#define CVMX_MIO_UART2_FCR (CVMX_ADD_IO_SEG(0x0001180000000450ull)) 1003#endif 1004#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1005#define CVMX_MIO_UART2_HTX CVMX_MIO_UART2_HTX_FUNC() 1006static inline uint64_t CVMX_MIO_UART2_HTX_FUNC(void) 1007{ 1008 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1009 cvmx_warn("CVMX_MIO_UART2_HTX not supported on this chip\n"); 1010 return CVMX_ADD_IO_SEG(0x0001180000000708ull); 1011} 1012#else 1013#define CVMX_MIO_UART2_HTX (CVMX_ADD_IO_SEG(0x0001180000000708ull)) 1014#endif 1015#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1016#define CVMX_MIO_UART2_IER CVMX_MIO_UART2_IER_FUNC() 1017static inline uint64_t CVMX_MIO_UART2_IER_FUNC(void) 1018{ 1019 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1020 cvmx_warn("CVMX_MIO_UART2_IER not supported on this chip\n"); 1021 return CVMX_ADD_IO_SEG(0x0001180000000408ull); 1022} 1023#else 1024#define CVMX_MIO_UART2_IER (CVMX_ADD_IO_SEG(0x0001180000000408ull)) 1025#endif 1026#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1027#define CVMX_MIO_UART2_IIR CVMX_MIO_UART2_IIR_FUNC() 1028static inline uint64_t CVMX_MIO_UART2_IIR_FUNC(void) 1029{ 1030 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1031 cvmx_warn("CVMX_MIO_UART2_IIR not supported on this chip\n"); 1032 return CVMX_ADD_IO_SEG(0x0001180000000410ull); 1033} 1034#else 1035#define CVMX_MIO_UART2_IIR (CVMX_ADD_IO_SEG(0x0001180000000410ull)) 1036#endif 1037#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1038#define CVMX_MIO_UART2_LCR CVMX_MIO_UART2_LCR_FUNC() 1039static inline uint64_t CVMX_MIO_UART2_LCR_FUNC(void) 1040{ 1041 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1042 cvmx_warn("CVMX_MIO_UART2_LCR not supported on this chip\n"); 1043 return CVMX_ADD_IO_SEG(0x0001180000000418ull); 1044} 1045#else 1046#define CVMX_MIO_UART2_LCR (CVMX_ADD_IO_SEG(0x0001180000000418ull)) 1047#endif 1048#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1049#define CVMX_MIO_UART2_LSR CVMX_MIO_UART2_LSR_FUNC() 1050static inline uint64_t CVMX_MIO_UART2_LSR_FUNC(void) 1051{ 1052 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1053 cvmx_warn("CVMX_MIO_UART2_LSR not supported on this chip\n"); 1054 return CVMX_ADD_IO_SEG(0x0001180000000428ull); 1055} 1056#else 1057#define CVMX_MIO_UART2_LSR (CVMX_ADD_IO_SEG(0x0001180000000428ull)) 1058#endif 1059#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1060#define CVMX_MIO_UART2_MCR CVMX_MIO_UART2_MCR_FUNC() 1061static inline uint64_t CVMX_MIO_UART2_MCR_FUNC(void) 1062{ 1063 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1064 cvmx_warn("CVMX_MIO_UART2_MCR not supported on this chip\n"); 1065 return CVMX_ADD_IO_SEG(0x0001180000000420ull); 1066} 1067#else 1068#define CVMX_MIO_UART2_MCR (CVMX_ADD_IO_SEG(0x0001180000000420ull)) 1069#endif 1070#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1071#define CVMX_MIO_UART2_MSR CVMX_MIO_UART2_MSR_FUNC() 1072static inline uint64_t CVMX_MIO_UART2_MSR_FUNC(void) 1073{ 1074 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1075 cvmx_warn("CVMX_MIO_UART2_MSR not supported on this chip\n"); 1076 return CVMX_ADD_IO_SEG(0x0001180000000430ull); 1077} 1078#else 1079#define CVMX_MIO_UART2_MSR (CVMX_ADD_IO_SEG(0x0001180000000430ull)) 1080#endif 1081#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1082#define CVMX_MIO_UART2_RBR CVMX_MIO_UART2_RBR_FUNC() 1083static inline uint64_t CVMX_MIO_UART2_RBR_FUNC(void) 1084{ 1085 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1086 cvmx_warn("CVMX_MIO_UART2_RBR not supported on this chip\n"); 1087 return CVMX_ADD_IO_SEG(0x0001180000000400ull); 1088} 1089#else 1090#define CVMX_MIO_UART2_RBR (CVMX_ADD_IO_SEG(0x0001180000000400ull)) 1091#endif 1092#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1093#define CVMX_MIO_UART2_RFL CVMX_MIO_UART2_RFL_FUNC() 1094static inline uint64_t CVMX_MIO_UART2_RFL_FUNC(void) 1095{ 1096 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1097 cvmx_warn("CVMX_MIO_UART2_RFL not supported on this chip\n"); 1098 return CVMX_ADD_IO_SEG(0x0001180000000608ull); 1099} 1100#else 1101#define CVMX_MIO_UART2_RFL (CVMX_ADD_IO_SEG(0x0001180000000608ull)) 1102#endif 1103#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1104#define CVMX_MIO_UART2_RFW CVMX_MIO_UART2_RFW_FUNC() 1105static inline uint64_t CVMX_MIO_UART2_RFW_FUNC(void) 1106{ 1107 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1108 cvmx_warn("CVMX_MIO_UART2_RFW not supported on this chip\n"); 1109 return CVMX_ADD_IO_SEG(0x0001180000000530ull); 1110} 1111#else 1112#define CVMX_MIO_UART2_RFW (CVMX_ADD_IO_SEG(0x0001180000000530ull)) 1113#endif 1114#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1115#define CVMX_MIO_UART2_SBCR CVMX_MIO_UART2_SBCR_FUNC() 1116static inline uint64_t CVMX_MIO_UART2_SBCR_FUNC(void) 1117{ 1118 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1119 cvmx_warn("CVMX_MIO_UART2_SBCR not supported on this chip\n"); 1120 return CVMX_ADD_IO_SEG(0x0001180000000620ull); 1121} 1122#else 1123#define CVMX_MIO_UART2_SBCR (CVMX_ADD_IO_SEG(0x0001180000000620ull)) 1124#endif 1125#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1126#define CVMX_MIO_UART2_SCR CVMX_MIO_UART2_SCR_FUNC() 1127static inline uint64_t CVMX_MIO_UART2_SCR_FUNC(void) 1128{ 1129 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1130 cvmx_warn("CVMX_MIO_UART2_SCR not supported on this chip\n"); 1131 return CVMX_ADD_IO_SEG(0x0001180000000438ull); 1132} 1133#else 1134#define CVMX_MIO_UART2_SCR (CVMX_ADD_IO_SEG(0x0001180000000438ull)) 1135#endif 1136#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1137#define CVMX_MIO_UART2_SFE CVMX_MIO_UART2_SFE_FUNC() 1138static inline uint64_t CVMX_MIO_UART2_SFE_FUNC(void) 1139{ 1140 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1141 cvmx_warn("CVMX_MIO_UART2_SFE not supported on this chip\n"); 1142 return CVMX_ADD_IO_SEG(0x0001180000000630ull); 1143} 1144#else 1145#define CVMX_MIO_UART2_SFE (CVMX_ADD_IO_SEG(0x0001180000000630ull)) 1146#endif 1147#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1148#define CVMX_MIO_UART2_SRR CVMX_MIO_UART2_SRR_FUNC() 1149static inline uint64_t CVMX_MIO_UART2_SRR_FUNC(void) 1150{ 1151 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1152 cvmx_warn("CVMX_MIO_UART2_SRR not supported on this chip\n"); 1153 return CVMX_ADD_IO_SEG(0x0001180000000610ull); 1154} 1155#else 1156#define CVMX_MIO_UART2_SRR (CVMX_ADD_IO_SEG(0x0001180000000610ull)) 1157#endif 1158#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1159#define CVMX_MIO_UART2_SRT CVMX_MIO_UART2_SRT_FUNC() 1160static inline uint64_t CVMX_MIO_UART2_SRT_FUNC(void) 1161{ 1162 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1163 cvmx_warn("CVMX_MIO_UART2_SRT not supported on this chip\n"); 1164 return CVMX_ADD_IO_SEG(0x0001180000000638ull); 1165} 1166#else 1167#define CVMX_MIO_UART2_SRT (CVMX_ADD_IO_SEG(0x0001180000000638ull)) 1168#endif 1169#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1170#define CVMX_MIO_UART2_SRTS CVMX_MIO_UART2_SRTS_FUNC() 1171static inline uint64_t CVMX_MIO_UART2_SRTS_FUNC(void) 1172{ 1173 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1174 cvmx_warn("CVMX_MIO_UART2_SRTS not supported on this chip\n"); 1175 return CVMX_ADD_IO_SEG(0x0001180000000618ull); 1176} 1177#else 1178#define CVMX_MIO_UART2_SRTS (CVMX_ADD_IO_SEG(0x0001180000000618ull)) 1179#endif 1180#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1181#define CVMX_MIO_UART2_STT CVMX_MIO_UART2_STT_FUNC() 1182static inline uint64_t CVMX_MIO_UART2_STT_FUNC(void) 1183{ 1184 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1185 cvmx_warn("CVMX_MIO_UART2_STT not supported on this chip\n"); 1186 return CVMX_ADD_IO_SEG(0x0001180000000700ull); 1187} 1188#else 1189#define CVMX_MIO_UART2_STT (CVMX_ADD_IO_SEG(0x0001180000000700ull)) 1190#endif 1191#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1192#define CVMX_MIO_UART2_TFL CVMX_MIO_UART2_TFL_FUNC() 1193static inline uint64_t CVMX_MIO_UART2_TFL_FUNC(void) 1194{ 1195 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1196 cvmx_warn("CVMX_MIO_UART2_TFL not supported on this chip\n"); 1197 return CVMX_ADD_IO_SEG(0x0001180000000600ull); 1198} 1199#else 1200#define CVMX_MIO_UART2_TFL (CVMX_ADD_IO_SEG(0x0001180000000600ull)) 1201#endif 1202#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1203#define CVMX_MIO_UART2_TFR CVMX_MIO_UART2_TFR_FUNC() 1204static inline uint64_t CVMX_MIO_UART2_TFR_FUNC(void) 1205{ 1206 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1207 cvmx_warn("CVMX_MIO_UART2_TFR not supported on this chip\n"); 1208 return CVMX_ADD_IO_SEG(0x0001180000000528ull); 1209} 1210#else 1211#define CVMX_MIO_UART2_TFR (CVMX_ADD_IO_SEG(0x0001180000000528ull)) 1212#endif 1213#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1214#define CVMX_MIO_UART2_THR CVMX_MIO_UART2_THR_FUNC() 1215static inline uint64_t CVMX_MIO_UART2_THR_FUNC(void) 1216{ 1217 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1218 cvmx_warn("CVMX_MIO_UART2_THR not supported on this chip\n"); 1219 return CVMX_ADD_IO_SEG(0x0001180000000440ull); 1220} 1221#else 1222#define CVMX_MIO_UART2_THR (CVMX_ADD_IO_SEG(0x0001180000000440ull)) 1223#endif 1224#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1225#define CVMX_MIO_UART2_USR CVMX_MIO_UART2_USR_FUNC() 1226static inline uint64_t CVMX_MIO_UART2_USR_FUNC(void) 1227{ 1228 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 1229 cvmx_warn("CVMX_MIO_UART2_USR not supported on this chip\n"); 1230 return CVMX_ADD_IO_SEG(0x0001180000000538ull); 1231} 1232#else 1233#define CVMX_MIO_UART2_USR (CVMX_ADD_IO_SEG(0x0001180000000538ull)) 1234#endif 1235#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1236static inline uint64_t CVMX_MIO_UARTX_DLH(unsigned long offset) 1237{ 1238 if (!( 1239 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1240 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1241 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1242 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1243 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1244 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1245 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1246 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1247 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1248 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1249 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1250 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1251 cvmx_warn("CVMX_MIO_UARTX_DLH(%lu) is invalid on this chip\n", offset); 1252 return CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024; 1253} 1254#else 1255#define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024) 1256#endif 1257#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1258static inline uint64_t CVMX_MIO_UARTX_DLL(unsigned long offset) 1259{ 1260 if (!( 1261 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1262 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1263 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1264 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1265 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1266 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1267 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1268 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1269 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1270 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1271 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1272 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1273 cvmx_warn("CVMX_MIO_UARTX_DLL(%lu) is invalid on this chip\n", offset); 1274 return CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024; 1275} 1276#else 1277#define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024) 1278#endif 1279#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1280static inline uint64_t CVMX_MIO_UARTX_FAR(unsigned long offset) 1281{ 1282 if (!( 1283 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1284 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1285 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1286 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1287 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1288 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1289 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1290 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1291 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1292 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1293 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1294 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1295 cvmx_warn("CVMX_MIO_UARTX_FAR(%lu) is invalid on this chip\n", offset); 1296 return CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024; 1297} 1298#else 1299#define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024) 1300#endif 1301#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1302static inline uint64_t CVMX_MIO_UARTX_FCR(unsigned long offset) 1303{ 1304 if (!( 1305 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1306 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1307 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1308 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1309 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1310 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1311 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1312 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1313 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1314 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1315 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1316 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1317 cvmx_warn("CVMX_MIO_UARTX_FCR(%lu) is invalid on this chip\n", offset); 1318 return CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024; 1319} 1320#else 1321#define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024) 1322#endif 1323#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1324static inline uint64_t CVMX_MIO_UARTX_HTX(unsigned long offset) 1325{ 1326 if (!( 1327 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1328 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1329 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1330 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1331 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1332 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1333 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1334 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1335 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1336 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1337 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1338 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1339 cvmx_warn("CVMX_MIO_UARTX_HTX(%lu) is invalid on this chip\n", offset); 1340 return CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024; 1341} 1342#else 1343#define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024) 1344#endif 1345#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1346static inline uint64_t CVMX_MIO_UARTX_IER(unsigned long offset) 1347{ 1348 if (!( 1349 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1350 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1351 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1352 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1353 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1354 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1355 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1356 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1357 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1358 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1359 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1360 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1361 cvmx_warn("CVMX_MIO_UARTX_IER(%lu) is invalid on this chip\n", offset); 1362 return CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024; 1363} 1364#else 1365#define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024) 1366#endif 1367#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1368static inline uint64_t CVMX_MIO_UARTX_IIR(unsigned long offset) 1369{ 1370 if (!( 1371 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1372 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1373 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1374 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1375 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1376 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1377 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1378 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1379 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1380 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1381 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1382 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1383 cvmx_warn("CVMX_MIO_UARTX_IIR(%lu) is invalid on this chip\n", offset); 1384 return CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024; 1385} 1386#else 1387#define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024) 1388#endif 1389#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1390static inline uint64_t CVMX_MIO_UARTX_LCR(unsigned long offset) 1391{ 1392 if (!( 1393 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1394 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1395 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1396 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1397 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1398 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1399 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1400 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1401 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1402 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1403 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1404 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1405 cvmx_warn("CVMX_MIO_UARTX_LCR(%lu) is invalid on this chip\n", offset); 1406 return CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024; 1407} 1408#else 1409#define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024) 1410#endif 1411#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1412static inline uint64_t CVMX_MIO_UARTX_LSR(unsigned long offset) 1413{ 1414 if (!( 1415 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1416 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1417 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1418 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1419 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1420 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1421 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1422 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1423 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1424 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1425 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1426 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1427 cvmx_warn("CVMX_MIO_UARTX_LSR(%lu) is invalid on this chip\n", offset); 1428 return CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024; 1429} 1430#else 1431#define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024) 1432#endif 1433#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1434static inline uint64_t CVMX_MIO_UARTX_MCR(unsigned long offset) 1435{ 1436 if (!( 1437 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1438 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1439 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1440 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1441 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1442 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1443 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1444 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1445 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1446 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1447 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1448 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1449 cvmx_warn("CVMX_MIO_UARTX_MCR(%lu) is invalid on this chip\n", offset); 1450 return CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024; 1451} 1452#else 1453#define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024) 1454#endif 1455#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1456static inline uint64_t CVMX_MIO_UARTX_MSR(unsigned long offset) 1457{ 1458 if (!( 1459 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1460 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1461 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1462 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1463 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1464 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1465 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1466 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1467 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1468 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1469 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1470 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1471 cvmx_warn("CVMX_MIO_UARTX_MSR(%lu) is invalid on this chip\n", offset); 1472 return CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024; 1473} 1474#else 1475#define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024) 1476#endif 1477#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1478static inline uint64_t CVMX_MIO_UARTX_RBR(unsigned long offset) 1479{ 1480 if (!( 1481 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1482 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1483 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1484 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1485 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1486 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1487 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1488 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1489 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1490 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1491 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1492 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1493 cvmx_warn("CVMX_MIO_UARTX_RBR(%lu) is invalid on this chip\n", offset); 1494 return CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024; 1495} 1496#else 1497#define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024) 1498#endif 1499#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1500static inline uint64_t CVMX_MIO_UARTX_RFL(unsigned long offset) 1501{ 1502 if (!( 1503 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1504 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1505 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1506 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1507 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1508 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1509 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1510 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1511 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1512 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1513 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1514 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1515 cvmx_warn("CVMX_MIO_UARTX_RFL(%lu) is invalid on this chip\n", offset); 1516 return CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024; 1517} 1518#else 1519#define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024) 1520#endif 1521#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1522static inline uint64_t CVMX_MIO_UARTX_RFW(unsigned long offset) 1523{ 1524 if (!( 1525 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1526 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1527 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1528 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1529 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1530 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1531 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1532 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1533 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1534 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1535 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1536 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1537 cvmx_warn("CVMX_MIO_UARTX_RFW(%lu) is invalid on this chip\n", offset); 1538 return CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024; 1539} 1540#else 1541#define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024) 1542#endif 1543#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1544static inline uint64_t CVMX_MIO_UARTX_SBCR(unsigned long offset) 1545{ 1546 if (!( 1547 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1548 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1549 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1550 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1551 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1552 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1553 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1554 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1555 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1556 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1557 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1558 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1559 cvmx_warn("CVMX_MIO_UARTX_SBCR(%lu) is invalid on this chip\n", offset); 1560 return CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024; 1561} 1562#else 1563#define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024) 1564#endif 1565#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1566static inline uint64_t CVMX_MIO_UARTX_SCR(unsigned long offset) 1567{ 1568 if (!( 1569 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1570 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1571 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1572 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1573 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1574 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1575 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1576 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1577 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1578 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1579 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1580 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1581 cvmx_warn("CVMX_MIO_UARTX_SCR(%lu) is invalid on this chip\n", offset); 1582 return CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024; 1583} 1584#else 1585#define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024) 1586#endif 1587#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1588static inline uint64_t CVMX_MIO_UARTX_SFE(unsigned long offset) 1589{ 1590 if (!( 1591 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1592 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1593 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1594 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1595 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1596 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1597 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1598 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1599 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1600 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1601 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1602 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1603 cvmx_warn("CVMX_MIO_UARTX_SFE(%lu) is invalid on this chip\n", offset); 1604 return CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024; 1605} 1606#else 1607#define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024) 1608#endif 1609#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1610static inline uint64_t CVMX_MIO_UARTX_SRR(unsigned long offset) 1611{ 1612 if (!( 1613 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1614 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1615 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1616 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1617 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1618 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1619 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1620 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1621 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1622 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1623 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1624 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1625 cvmx_warn("CVMX_MIO_UARTX_SRR(%lu) is invalid on this chip\n", offset); 1626 return CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024; 1627} 1628#else 1629#define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024) 1630#endif 1631#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1632static inline uint64_t CVMX_MIO_UARTX_SRT(unsigned long offset) 1633{ 1634 if (!( 1635 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1636 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1637 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1638 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1639 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1640 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1641 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1642 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1643 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1644 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1645 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1646 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1647 cvmx_warn("CVMX_MIO_UARTX_SRT(%lu) is invalid on this chip\n", offset); 1648 return CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024; 1649} 1650#else 1651#define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024) 1652#endif 1653#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1654static inline uint64_t CVMX_MIO_UARTX_SRTS(unsigned long offset) 1655{ 1656 if (!( 1657 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1658 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1659 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1660 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1661 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1662 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1663 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1664 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1665 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1666 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1667 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1668 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1669 cvmx_warn("CVMX_MIO_UARTX_SRTS(%lu) is invalid on this chip\n", offset); 1670 return CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024; 1671} 1672#else 1673#define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024) 1674#endif 1675#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1676static inline uint64_t CVMX_MIO_UARTX_STT(unsigned long offset) 1677{ 1678 if (!( 1679 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1680 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1681 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1682 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1683 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1684 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1685 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1686 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1687 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1688 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1689 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1690 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1691 cvmx_warn("CVMX_MIO_UARTX_STT(%lu) is invalid on this chip\n", offset); 1692 return CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024; 1693} 1694#else 1695#define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024) 1696#endif 1697#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1698static inline uint64_t CVMX_MIO_UARTX_TFL(unsigned long offset) 1699{ 1700 if (!( 1701 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1702 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1703 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1704 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1705 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1706 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1707 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1708 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1709 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1710 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1711 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1712 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1713 cvmx_warn("CVMX_MIO_UARTX_TFL(%lu) is invalid on this chip\n", offset); 1714 return CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024; 1715} 1716#else 1717#define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024) 1718#endif 1719#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1720static inline uint64_t CVMX_MIO_UARTX_TFR(unsigned long offset) 1721{ 1722 if (!( 1723 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1724 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1725 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1726 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1727 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1728 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1729 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1730 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1731 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1732 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1733 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1734 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1735 cvmx_warn("CVMX_MIO_UARTX_TFR(%lu) is invalid on this chip\n", offset); 1736 return CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024; 1737} 1738#else 1739#define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024) 1740#endif 1741#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1742static inline uint64_t CVMX_MIO_UARTX_THR(unsigned long offset) 1743{ 1744 if (!( 1745 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1746 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1747 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1748 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1749 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1750 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1751 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1752 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1753 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1754 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1755 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1756 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1757 cvmx_warn("CVMX_MIO_UARTX_THR(%lu) is invalid on this chip\n", offset); 1758 return CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024; 1759} 1760#else 1761#define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024) 1762#endif 1763#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1764static inline uint64_t CVMX_MIO_UARTX_USR(unsigned long offset) 1765{ 1766 if (!( 1767 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 1768 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 1769 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 1770 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1771 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 1772 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 1773 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) || 1774 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1775 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1776 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1777 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1778 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1779 cvmx_warn("CVMX_MIO_UARTX_USR(%lu) is invalid on this chip\n", offset); 1780 return CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024; 1781} 1782#else 1783#define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024) 1784#endif 1785 1786/** 1787 * cvmx_mio_boot_bist_stat 1788 * 1789 * MIO_BOOT_BIST_STAT = MIO Boot BIST Status Register 1790 * 1791 * Contains the BIST status for the MIO boot memories. '0' = pass, '1' = fail. 1792 */ 1793union cvmx_mio_boot_bist_stat { 1794 uint64_t u64; 1795 struct cvmx_mio_boot_bist_stat_s { 1796#ifdef __BIG_ENDIAN_BITFIELD 1797 uint64_t reserved_0_63 : 64; 1798#else 1799 uint64_t reserved_0_63 : 64; 1800#endif 1801 } s; 1802 struct cvmx_mio_boot_bist_stat_cn30xx { 1803#ifdef __BIG_ENDIAN_BITFIELD 1804 uint64_t reserved_4_63 : 60; 1805 uint64_t ncbo_1 : 1; /**< NCB output FIFO 1 BIST status */ 1806 uint64_t ncbo_0 : 1; /**< NCB output FIFO 0 BIST status */ 1807 uint64_t loc : 1; /**< Local memory BIST status */ 1808 uint64_t ncbi : 1; /**< NCB input FIFO BIST status */ 1809#else 1810 uint64_t ncbi : 1; 1811 uint64_t loc : 1; 1812 uint64_t ncbo_0 : 1; 1813 uint64_t ncbo_1 : 1; 1814 uint64_t reserved_4_63 : 60; 1815#endif 1816 } cn30xx; 1817 struct cvmx_mio_boot_bist_stat_cn30xx cn31xx; 1818 struct cvmx_mio_boot_bist_stat_cn38xx { 1819#ifdef __BIG_ENDIAN_BITFIELD 1820 uint64_t reserved_3_63 : 61; 1821 uint64_t ncbo_0 : 1; /**< NCB output FIFO BIST status */ 1822 uint64_t loc : 1; /**< Local memory BIST status */ 1823 uint64_t ncbi : 1; /**< NCB input FIFO BIST status */ 1824#else 1825 uint64_t ncbi : 1; 1826 uint64_t loc : 1; 1827 uint64_t ncbo_0 : 1; 1828 uint64_t reserved_3_63 : 61; 1829#endif 1830 } cn38xx; 1831 struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2; 1832 struct cvmx_mio_boot_bist_stat_cn50xx { 1833#ifdef __BIG_ENDIAN_BITFIELD 1834 uint64_t reserved_6_63 : 58; 1835 uint64_t pcm_1 : 1; /**< PCM memory 1 BIST status */ 1836 uint64_t pcm_0 : 1; /**< PCM memory 0 BIST status */ 1837 uint64_t ncbo_1 : 1; /**< NCB output FIFO 1 BIST status */ 1838 uint64_t ncbo_0 : 1; /**< NCB output FIFO 0 BIST status */ 1839 uint64_t loc : 1; /**< Local memory region BIST status */ 1840 uint64_t ncbi : 1; /**< NCB input FIFO BIST status */ 1841#else 1842 uint64_t ncbi : 1; 1843 uint64_t loc : 1; 1844 uint64_t ncbo_0 : 1; 1845 uint64_t ncbo_1 : 1; 1846 uint64_t pcm_0 : 1; 1847 uint64_t pcm_1 : 1; 1848 uint64_t reserved_6_63 : 58; 1849#endif 1850 } cn50xx; 1851 struct cvmx_mio_boot_bist_stat_cn52xx { 1852#ifdef __BIG_ENDIAN_BITFIELD 1853 uint64_t reserved_6_63 : 58; 1854 uint64_t ndf : 2; /**< NAND flash BIST status */ 1855 uint64_t ncbo_0 : 1; /**< NCB output FIFO BIST status */ 1856 uint64_t dma : 1; /**< DMA memory BIST status */ 1857 uint64_t loc : 1; /**< Local memory BIST status */ 1858 uint64_t ncbi : 1; /**< NCB input FIFO BIST status */ 1859#else 1860 uint64_t ncbi : 1; 1861 uint64_t loc : 1; 1862 uint64_t dma : 1; 1863 uint64_t ncbo_0 : 1; 1864 uint64_t ndf : 2; 1865 uint64_t reserved_6_63 : 58; 1866#endif 1867 } cn52xx; 1868 struct cvmx_mio_boot_bist_stat_cn52xxp1 { 1869#ifdef __BIG_ENDIAN_BITFIELD 1870 uint64_t reserved_4_63 : 60; 1871 uint64_t ncbo_0 : 1; /**< NCB output FIFO BIST status */ 1872 uint64_t dma : 1; /**< DMA memory BIST status */ 1873 uint64_t loc : 1; /**< Local memory region BIST status */ 1874 uint64_t ncbi : 1; /**< NCB input FIFO BIST status */ 1875#else 1876 uint64_t ncbi : 1; 1877 uint64_t loc : 1; 1878 uint64_t dma : 1; 1879 uint64_t ncbo_0 : 1; 1880 uint64_t reserved_4_63 : 60; 1881#endif 1882 } cn52xxp1; 1883 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx; 1884 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1; 1885 struct cvmx_mio_boot_bist_stat_cn38xx cn58xx; 1886 struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1; 1887 struct cvmx_mio_boot_bist_stat_cn61xx { 1888#ifdef __BIG_ENDIAN_BITFIELD 1889 uint64_t reserved_12_63 : 52; 1890 uint64_t stat : 12; /**< BIST status */ 1891#else 1892 uint64_t stat : 12; 1893 uint64_t reserved_12_63 : 52; 1894#endif 1895 } cn61xx; 1896 struct cvmx_mio_boot_bist_stat_cn63xx { 1897#ifdef __BIG_ENDIAN_BITFIELD 1898 uint64_t reserved_9_63 : 55; 1899 uint64_t stat : 9; /**< BIST status */ 1900#else 1901 uint64_t stat : 9; 1902 uint64_t reserved_9_63 : 55; 1903#endif 1904 } cn63xx; 1905 struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1; 1906 struct cvmx_mio_boot_bist_stat_cn66xx { 1907#ifdef __BIG_ENDIAN_BITFIELD 1908 uint64_t reserved_10_63 : 54; 1909 uint64_t stat : 10; /**< BIST status */ 1910#else 1911 uint64_t stat : 10; 1912 uint64_t reserved_10_63 : 54; 1913#endif 1914 } cn66xx; 1915 struct cvmx_mio_boot_bist_stat_cn66xx cn68xx; 1916 struct cvmx_mio_boot_bist_stat_cn66xx cn68xxp1; 1917 struct cvmx_mio_boot_bist_stat_cn61xx cnf71xx; 1918}; 1919typedef union cvmx_mio_boot_bist_stat cvmx_mio_boot_bist_stat_t; 1920 1921/** 1922 * cvmx_mio_boot_comp 1923 * 1924 * MIO_BOOT_COMP = MIO Boot Compensation Register 1925 * 1926 * Reset value is as follows: 1927 * 1928 * no pullups, PCTL=38, NCTL=30 (25 ohm termination) 1929 * pullup on boot_ad[9], PCTL=19, NCTL=15 (50 ohm termination) 1930 * pullup on boot_ad[10], PCTL=15, NCTL=12 (65 ohm termination) 1931 * pullups on boot_ad[10:9], PCTL=15, NCTL=12 (65 ohm termination) 1932 */ 1933union cvmx_mio_boot_comp { 1934 uint64_t u64; 1935 struct cvmx_mio_boot_comp_s { 1936#ifdef __BIG_ENDIAN_BITFIELD 1937 uint64_t reserved_0_63 : 64; 1938#else 1939 uint64_t reserved_0_63 : 64; 1940#endif 1941 } s; 1942 struct cvmx_mio_boot_comp_cn50xx { 1943#ifdef __BIG_ENDIAN_BITFIELD 1944 uint64_t reserved_10_63 : 54; 1945 uint64_t pctl : 5; /**< Boot bus PCTL */ 1946 uint64_t nctl : 5; /**< Boot bus NCTL */ 1947#else 1948 uint64_t nctl : 5; 1949 uint64_t pctl : 5; 1950 uint64_t reserved_10_63 : 54; 1951#endif 1952 } cn50xx; 1953 struct cvmx_mio_boot_comp_cn50xx cn52xx; 1954 struct cvmx_mio_boot_comp_cn50xx cn52xxp1; 1955 struct cvmx_mio_boot_comp_cn50xx cn56xx; 1956 struct cvmx_mio_boot_comp_cn50xx cn56xxp1; 1957 struct cvmx_mio_boot_comp_cn61xx { 1958#ifdef __BIG_ENDIAN_BITFIELD 1959 uint64_t reserved_12_63 : 52; 1960 uint64_t pctl : 6; /**< Boot bus PCTL */ 1961 uint64_t nctl : 6; /**< Boot bus NCTL */ 1962#else 1963 uint64_t nctl : 6; 1964 uint64_t pctl : 6; 1965 uint64_t reserved_12_63 : 52; 1966#endif 1967 } cn61xx; 1968 struct cvmx_mio_boot_comp_cn61xx cn63xx; 1969 struct cvmx_mio_boot_comp_cn61xx cn63xxp1; 1970 struct cvmx_mio_boot_comp_cn61xx cn66xx; 1971 struct cvmx_mio_boot_comp_cn61xx cn68xx; 1972 struct cvmx_mio_boot_comp_cn61xx cn68xxp1; 1973 struct cvmx_mio_boot_comp_cn61xx cnf71xx; 1974}; 1975typedef union cvmx_mio_boot_comp cvmx_mio_boot_comp_t; 1976 1977/** 1978 * cvmx_mio_boot_dma_cfg# 1979 * 1980 * MIO_BOOT_DMA_CFG = MIO Boot DMA Config Register (1 per engine * 2 engines) 1981 * 1982 * SIZE is specified in number of bus transfers, where one transfer is equal to the following number 1983 * of bytes dependent on MIO_BOOT_DMA_TIMn[WIDTH] and MIO_BOOT_DMA_TIMn[DDR]: 1984 * 1985 * WIDTH DDR Transfer Size (bytes) 1986 * ---------------------------------------- 1987 * 0 0 2 1988 * 0 1 4 1989 * 1 0 4 1990 * 1 1 8 1991 * 1992 * Note: ADR must be aligned to the bus width (i.e. 16 bit aligned if WIDTH=0, 32 bit aligned if WIDTH=1). 1993 */ 1994union cvmx_mio_boot_dma_cfgx { 1995 uint64_t u64; 1996 struct cvmx_mio_boot_dma_cfgx_s { 1997#ifdef __BIG_ENDIAN_BITFIELD 1998 uint64_t en : 1; /**< DMA Engine X enable */ 1999 uint64_t rw : 1; /**< DMA Engine X R/W bit (0 = read, 1 = write) */ 2000 uint64_t clr : 1; /**< DMA Engine X clear EN on device terminated burst */ 2001 uint64_t reserved_60_60 : 1; 2002 uint64_t swap32 : 1; /**< DMA Engine X 32 bit swap */ 2003 uint64_t swap16 : 1; /**< DMA Engine X 16 bit swap */ 2004 uint64_t swap8 : 1; /**< DMA Engine X 8 bit swap */ 2005 uint64_t endian : 1; /**< DMA Engine X NCB endian mode (0 = big, 1 = little) */ 2006 uint64_t size : 20; /**< DMA Engine X size */ 2007 uint64_t adr : 36; /**< DMA Engine X address */ 2008#else 2009 uint64_t adr : 36; 2010 uint64_t size : 20; 2011 uint64_t endian : 1; 2012 uint64_t swap8 : 1; 2013 uint64_t swap16 : 1; 2014 uint64_t swap32 : 1; 2015 uint64_t reserved_60_60 : 1; 2016 uint64_t clr : 1; 2017 uint64_t rw : 1; 2018 uint64_t en : 1; 2019#endif 2020 } s; 2021 struct cvmx_mio_boot_dma_cfgx_s cn52xx; 2022 struct cvmx_mio_boot_dma_cfgx_s cn52xxp1; 2023 struct cvmx_mio_boot_dma_cfgx_s cn56xx; 2024 struct cvmx_mio_boot_dma_cfgx_s cn56xxp1; 2025 struct cvmx_mio_boot_dma_cfgx_s cn61xx; 2026 struct cvmx_mio_boot_dma_cfgx_s cn63xx; 2027 struct cvmx_mio_boot_dma_cfgx_s cn63xxp1; 2028 struct cvmx_mio_boot_dma_cfgx_s cn66xx; 2029 struct cvmx_mio_boot_dma_cfgx_s cn68xx; 2030 struct cvmx_mio_boot_dma_cfgx_s cn68xxp1; 2031 struct cvmx_mio_boot_dma_cfgx_s cnf71xx; 2032}; 2033typedef union cvmx_mio_boot_dma_cfgx cvmx_mio_boot_dma_cfgx_t; 2034 2035/** 2036 * cvmx_mio_boot_dma_int# 2037 * 2038 * MIO_BOOT_DMA_INT = MIO Boot DMA Interrupt Register (1 per engine * 2 engines) 2039 * 2040 */ 2041union cvmx_mio_boot_dma_intx { 2042 uint64_t u64; 2043 struct cvmx_mio_boot_dma_intx_s { 2044#ifdef __BIG_ENDIAN_BITFIELD 2045 uint64_t reserved_2_63 : 62; 2046 uint64_t dmarq : 1; /**< DMA Engine X DMARQ asserted interrupt */ 2047 uint64_t done : 1; /**< DMA Engine X request completion interrupt */ 2048#else 2049 uint64_t done : 1; 2050 uint64_t dmarq : 1; 2051 uint64_t reserved_2_63 : 62; 2052#endif 2053 } s; 2054 struct cvmx_mio_boot_dma_intx_s cn52xx; 2055 struct cvmx_mio_boot_dma_intx_s cn52xxp1; 2056 struct cvmx_mio_boot_dma_intx_s cn56xx; 2057 struct cvmx_mio_boot_dma_intx_s cn56xxp1; 2058 struct cvmx_mio_boot_dma_intx_s cn61xx; 2059 struct cvmx_mio_boot_dma_intx_s cn63xx; 2060 struct cvmx_mio_boot_dma_intx_s cn63xxp1; 2061 struct cvmx_mio_boot_dma_intx_s cn66xx; 2062 struct cvmx_mio_boot_dma_intx_s cn68xx; 2063 struct cvmx_mio_boot_dma_intx_s cn68xxp1; 2064 struct cvmx_mio_boot_dma_intx_s cnf71xx; 2065}; 2066typedef union cvmx_mio_boot_dma_intx cvmx_mio_boot_dma_intx_t; 2067 2068/** 2069 * cvmx_mio_boot_dma_int_en# 2070 * 2071 * MIO_BOOT_DMA_INT_EN = MIO Boot DMA Interrupt Enable Register (1 per engine * 2 engines) 2072 * 2073 */ 2074union cvmx_mio_boot_dma_int_enx { 2075 uint64_t u64; 2076 struct cvmx_mio_boot_dma_int_enx_s { 2077#ifdef __BIG_ENDIAN_BITFIELD 2078 uint64_t reserved_2_63 : 62; 2079 uint64_t dmarq : 1; /**< DMA Engine X DMARQ asserted interrupt enable */ 2080 uint64_t done : 1; /**< DMA Engine X request completion interrupt enable */ 2081#else 2082 uint64_t done : 1; 2083 uint64_t dmarq : 1; 2084 uint64_t reserved_2_63 : 62; 2085#endif 2086 } s; 2087 struct cvmx_mio_boot_dma_int_enx_s cn52xx; 2088 struct cvmx_mio_boot_dma_int_enx_s cn52xxp1; 2089 struct cvmx_mio_boot_dma_int_enx_s cn56xx; 2090 struct cvmx_mio_boot_dma_int_enx_s cn56xxp1; 2091 struct cvmx_mio_boot_dma_int_enx_s cn61xx; 2092 struct cvmx_mio_boot_dma_int_enx_s cn63xx; 2093 struct cvmx_mio_boot_dma_int_enx_s cn63xxp1; 2094 struct cvmx_mio_boot_dma_int_enx_s cn66xx; 2095 struct cvmx_mio_boot_dma_int_enx_s cn68xx; 2096 struct cvmx_mio_boot_dma_int_enx_s cn68xxp1; 2097 struct cvmx_mio_boot_dma_int_enx_s cnf71xx; 2098}; 2099typedef union cvmx_mio_boot_dma_int_enx cvmx_mio_boot_dma_int_enx_t; 2100 2101/** 2102 * cvmx_mio_boot_dma_tim# 2103 * 2104 * MIO_BOOT_DMA_TIM = MIO Boot DMA Timing Register (1 per engine * 2 engines) 2105 * 2106 * DMACK_PI inverts the assertion level of boot_dmack[n]. The default polarity of boot_dmack[1:0] is 2107 * selected on the first de-assertion of reset by the values on boot_ad[12:11], where 0 is active high 2108 * and 1 is active low (see MIO_BOOT_PIN_DEFS for a read-only copy of the default polarity). 2109 * boot_ad[12:11] have internal pulldowns, so place a pullup on boot_ad[n+11] for active low default 2110 * polarity on engine n. To interface with CF cards in True IDE Mode, either a pullup should be placed 2111 * on boot_ad[n+11] OR the corresponding DMACK_PI[n] should be set. 2112 * 2113 * DMARQ_PI inverts the assertion level of boot_dmarq[n]. The default polarity of boot_dmarq[1:0] is 2114 * active high, thus setting the polarity inversion bits changes the polarity to active low. To 2115 * interface with CF cards in True IDE Mode, the corresponding DMARQ_PI[n] should be clear. 2116 * 2117 * TIM_MULT specifies the timing multiplier for an engine. The timing multiplier applies to all timing 2118 * parameters, except for DMARQ and RD_DLY, which simply count eclks. TIM_MULT is encoded as follows: 2119 * 0 = 4x, 1 = 1x, 2 = 2x, 3 = 8x. 2120 * 2121 * RD_DLY specifies the read sample delay in eclk cycles for an engine. For reads, the data bus is 2122 * normally sampled on the same eclk edge that drives boot_oe_n high (and also low in DDR mode). 2123 * This parameter can delay that sampling edge by up to 7 eclks. Note: the number of eclk cycles 2124 * counted by the OE_A and DMACK_H + PAUSE timing parameters must be greater than RD_DLY. 2125 * 2126 * If DDR is set, then WE_N must be less than WE_A. 2127 */ 2128union cvmx_mio_boot_dma_timx { 2129 uint64_t u64; 2130 struct cvmx_mio_boot_dma_timx_s { 2131#ifdef __BIG_ENDIAN_BITFIELD 2132 uint64_t dmack_pi : 1; /**< DMA Engine X DMA ack polarity inversion */ 2133 uint64_t dmarq_pi : 1; /**< DMA Engine X DMA request polarity inversion */ 2134 uint64_t tim_mult : 2; /**< DMA Engine X timing multiplier */ 2135 uint64_t rd_dly : 3; /**< DMA Engine X read sample delay */ 2136 uint64_t ddr : 1; /**< DMA Engine X DDR mode */ 2137 uint64_t width : 1; /**< DMA Engine X bus width (0 = 16 bits, 1 = 32 bits) */ 2138 uint64_t reserved_48_54 : 7; 2139 uint64_t pause : 6; /**< DMA Engine X pause count */ 2140 uint64_t dmack_h : 6; /**< DMA Engine X DMA ack hold count */ 2141 uint64_t we_n : 6; /**< DMA Engine X write enable negated count */ 2142 uint64_t we_a : 6; /**< DMA Engine X write enable asserted count */ 2143 uint64_t oe_n : 6; /**< DMA Engine X output enable negated count */ 2144 uint64_t oe_a : 6; /**< DMA Engine X output enable asserted count */ 2145 uint64_t dmack_s : 6; /**< DMA Engine X DMA ack setup count */ 2146 uint64_t dmarq : 6; /**< DMA Engine X DMA request count (must be non-zero) */ 2147#else 2148 uint64_t dmarq : 6; 2149 uint64_t dmack_s : 6; 2150 uint64_t oe_a : 6; 2151 uint64_t oe_n : 6; 2152 uint64_t we_a : 6; 2153 uint64_t we_n : 6; 2154 uint64_t dmack_h : 6; 2155 uint64_t pause : 6; 2156 uint64_t reserved_48_54 : 7; 2157 uint64_t width : 1; 2158 uint64_t ddr : 1; 2159 uint64_t rd_dly : 3; 2160 uint64_t tim_mult : 2; 2161 uint64_t dmarq_pi : 1; 2162 uint64_t dmack_pi : 1; 2163#endif 2164 } s; 2165 struct cvmx_mio_boot_dma_timx_s cn52xx; 2166 struct cvmx_mio_boot_dma_timx_s cn52xxp1; 2167 struct cvmx_mio_boot_dma_timx_s cn56xx; 2168 struct cvmx_mio_boot_dma_timx_s cn56xxp1; 2169 struct cvmx_mio_boot_dma_timx_s cn61xx; 2170 struct cvmx_mio_boot_dma_timx_s cn63xx; 2171 struct cvmx_mio_boot_dma_timx_s cn63xxp1; 2172 struct cvmx_mio_boot_dma_timx_s cn66xx; 2173 struct cvmx_mio_boot_dma_timx_s cn68xx; 2174 struct cvmx_mio_boot_dma_timx_s cn68xxp1; 2175 struct cvmx_mio_boot_dma_timx_s cnf71xx; 2176}; 2177typedef union cvmx_mio_boot_dma_timx cvmx_mio_boot_dma_timx_t; 2178 2179/** 2180 * cvmx_mio_boot_err 2181 * 2182 * MIO_BOOT_ERR = MIO Boot Error Register 2183 * 2184 * Contains the address decode error and wait mode error bits. Address decode error is set when a 2185 * boot bus access does not hit in any of the 8 remote regions or 2 local memory regions. Wait mode error is 2186 * set when wait mode is enabled and the external wait signal is not de-asserted after 32k eclk cycles. 2187 */ 2188union cvmx_mio_boot_err { 2189 uint64_t u64; 2190 struct cvmx_mio_boot_err_s { 2191#ifdef __BIG_ENDIAN_BITFIELD 2192 uint64_t reserved_2_63 : 62; 2193 uint64_t wait_err : 1; /**< Wait mode error */ 2194 uint64_t adr_err : 1; /**< Address decode error */ 2195#else 2196 uint64_t adr_err : 1; 2197 uint64_t wait_err : 1; 2198 uint64_t reserved_2_63 : 62; 2199#endif 2200 } s; 2201 struct cvmx_mio_boot_err_s cn30xx; 2202 struct cvmx_mio_boot_err_s cn31xx; 2203 struct cvmx_mio_boot_err_s cn38xx; 2204 struct cvmx_mio_boot_err_s cn38xxp2; 2205 struct cvmx_mio_boot_err_s cn50xx; 2206 struct cvmx_mio_boot_err_s cn52xx; 2207 struct cvmx_mio_boot_err_s cn52xxp1; 2208 struct cvmx_mio_boot_err_s cn56xx; 2209 struct cvmx_mio_boot_err_s cn56xxp1; 2210 struct cvmx_mio_boot_err_s cn58xx; 2211 struct cvmx_mio_boot_err_s cn58xxp1; 2212 struct cvmx_mio_boot_err_s cn61xx; 2213 struct cvmx_mio_boot_err_s cn63xx; 2214 struct cvmx_mio_boot_err_s cn63xxp1; 2215 struct cvmx_mio_boot_err_s cn66xx; 2216 struct cvmx_mio_boot_err_s cn68xx; 2217 struct cvmx_mio_boot_err_s cn68xxp1; 2218 struct cvmx_mio_boot_err_s cnf71xx; 2219}; 2220typedef union cvmx_mio_boot_err cvmx_mio_boot_err_t; 2221 2222/** 2223 * cvmx_mio_boot_int 2224 * 2225 * MIO_BOOT_INT = MIO Boot Interrupt Register 2226 * 2227 * Contains the interrupt enable bits for address decode error and wait mode error. 2228 */ 2229union cvmx_mio_boot_int { 2230 uint64_t u64; 2231 struct cvmx_mio_boot_int_s { 2232#ifdef __BIG_ENDIAN_BITFIELD 2233 uint64_t reserved_2_63 : 62; 2234 uint64_t wait_int : 1; /**< Wait mode error interrupt enable */ 2235 uint64_t adr_int : 1; /**< Address decode error interrupt enable */ 2236#else 2237 uint64_t adr_int : 1; 2238 uint64_t wait_int : 1; 2239 uint64_t reserved_2_63 : 62; 2240#endif 2241 } s; 2242 struct cvmx_mio_boot_int_s cn30xx; 2243 struct cvmx_mio_boot_int_s cn31xx; 2244 struct cvmx_mio_boot_int_s cn38xx; 2245 struct cvmx_mio_boot_int_s cn38xxp2; 2246 struct cvmx_mio_boot_int_s cn50xx; 2247 struct cvmx_mio_boot_int_s cn52xx; 2248 struct cvmx_mio_boot_int_s cn52xxp1; 2249 struct cvmx_mio_boot_int_s cn56xx; 2250 struct cvmx_mio_boot_int_s cn56xxp1; 2251 struct cvmx_mio_boot_int_s cn58xx; 2252 struct cvmx_mio_boot_int_s cn58xxp1; 2253 struct cvmx_mio_boot_int_s cn61xx; 2254 struct cvmx_mio_boot_int_s cn63xx; 2255 struct cvmx_mio_boot_int_s cn63xxp1; 2256 struct cvmx_mio_boot_int_s cn66xx; 2257 struct cvmx_mio_boot_int_s cn68xx; 2258 struct cvmx_mio_boot_int_s cn68xxp1; 2259 struct cvmx_mio_boot_int_s cnf71xx; 2260}; 2261typedef union cvmx_mio_boot_int cvmx_mio_boot_int_t; 2262 2263/** 2264 * cvmx_mio_boot_loc_adr 2265 * 2266 * MIO_BOOT_LOC_ADR = MIO Boot Local Memory Region Address Register 2267 * 2268 * Specifies the address for reading or writing the local memory region. This address will post-increment 2269 * following an access to the MIO Boot Local Memory Region Data Register (MIO_BOOT_LOC_DAT). 2270 * 2271 * Local memory region 0 exists from addresses 0x00 - 0x78. 2272 * Local memory region 1 exists from addresses 0x80 - 0xf8. 2273 */ 2274union cvmx_mio_boot_loc_adr { 2275 uint64_t u64; 2276 struct cvmx_mio_boot_loc_adr_s { 2277#ifdef __BIG_ENDIAN_BITFIELD 2278 uint64_t reserved_8_63 : 56; 2279 uint64_t adr : 5; /**< Local memory region address */ 2280 uint64_t reserved_0_2 : 3; 2281#else 2282 uint64_t reserved_0_2 : 3; 2283 uint64_t adr : 5; 2284 uint64_t reserved_8_63 : 56; 2285#endif 2286 } s; 2287 struct cvmx_mio_boot_loc_adr_s cn30xx; 2288 struct cvmx_mio_boot_loc_adr_s cn31xx; 2289 struct cvmx_mio_boot_loc_adr_s cn38xx; 2290 struct cvmx_mio_boot_loc_adr_s cn38xxp2; 2291 struct cvmx_mio_boot_loc_adr_s cn50xx; 2292 struct cvmx_mio_boot_loc_adr_s cn52xx; 2293 struct cvmx_mio_boot_loc_adr_s cn52xxp1; 2294 struct cvmx_mio_boot_loc_adr_s cn56xx; 2295 struct cvmx_mio_boot_loc_adr_s cn56xxp1; 2296 struct cvmx_mio_boot_loc_adr_s cn58xx; 2297 struct cvmx_mio_boot_loc_adr_s cn58xxp1; 2298 struct cvmx_mio_boot_loc_adr_s cn61xx; 2299 struct cvmx_mio_boot_loc_adr_s cn63xx; 2300 struct cvmx_mio_boot_loc_adr_s cn63xxp1; 2301 struct cvmx_mio_boot_loc_adr_s cn66xx; 2302 struct cvmx_mio_boot_loc_adr_s cn68xx; 2303 struct cvmx_mio_boot_loc_adr_s cn68xxp1; 2304 struct cvmx_mio_boot_loc_adr_s cnf71xx; 2305}; 2306typedef union cvmx_mio_boot_loc_adr cvmx_mio_boot_loc_adr_t; 2307 2308/** 2309 * cvmx_mio_boot_loc_cfg# 2310 * 2311 * MIO_BOOT_LOC_CFG = MIO Boot Local Memory Region Config Register (1 per region * 2 regions) 2312 * 2313 * Contains local memory region enable and local memory region base address parameters. Each local memory region is 128 2314 * bytes organized as 16 entries x 8 bytes. 2315 * 2316 * Base address specifies address bits [31:7] of the region. 2317 */ 2318union cvmx_mio_boot_loc_cfgx { 2319 uint64_t u64; 2320 struct cvmx_mio_boot_loc_cfgx_s { 2321#ifdef __BIG_ENDIAN_BITFIELD 2322 uint64_t reserved_32_63 : 32; 2323 uint64_t en : 1; /**< Local memory region X enable */ 2324 uint64_t reserved_28_30 : 3; 2325 uint64_t base : 25; /**< Local memory region X base address */ 2326 uint64_t reserved_0_2 : 3; 2327#else 2328 uint64_t reserved_0_2 : 3; 2329 uint64_t base : 25; 2330 uint64_t reserved_28_30 : 3; 2331 uint64_t en : 1; 2332 uint64_t reserved_32_63 : 32; 2333#endif 2334 } s; 2335 struct cvmx_mio_boot_loc_cfgx_s cn30xx; 2336 struct cvmx_mio_boot_loc_cfgx_s cn31xx; 2337 struct cvmx_mio_boot_loc_cfgx_s cn38xx; 2338 struct cvmx_mio_boot_loc_cfgx_s cn38xxp2; 2339 struct cvmx_mio_boot_loc_cfgx_s cn50xx; 2340 struct cvmx_mio_boot_loc_cfgx_s cn52xx; 2341 struct cvmx_mio_boot_loc_cfgx_s cn52xxp1; 2342 struct cvmx_mio_boot_loc_cfgx_s cn56xx; 2343 struct cvmx_mio_boot_loc_cfgx_s cn56xxp1; 2344 struct cvmx_mio_boot_loc_cfgx_s cn58xx; 2345 struct cvmx_mio_boot_loc_cfgx_s cn58xxp1; 2346 struct cvmx_mio_boot_loc_cfgx_s cn61xx; 2347 struct cvmx_mio_boot_loc_cfgx_s cn63xx; 2348 struct cvmx_mio_boot_loc_cfgx_s cn63xxp1; 2349 struct cvmx_mio_boot_loc_cfgx_s cn66xx; 2350 struct cvmx_mio_boot_loc_cfgx_s cn68xx; 2351 struct cvmx_mio_boot_loc_cfgx_s cn68xxp1; 2352 struct cvmx_mio_boot_loc_cfgx_s cnf71xx; 2353}; 2354typedef union cvmx_mio_boot_loc_cfgx cvmx_mio_boot_loc_cfgx_t; 2355 2356/** 2357 * cvmx_mio_boot_loc_dat 2358 * 2359 * MIO_BOOT_LOC_DAT = MIO Boot Local Memory Region Data Register 2360 * 2361 * This is a pseudo-register that will read/write the local memory region at the address specified by the MIO 2362 * Boot Local Memory Region Address Register (MIO_BOOT_LOC_ADR) when accessed. 2363 */ 2364union cvmx_mio_boot_loc_dat { 2365 uint64_t u64; 2366 struct cvmx_mio_boot_loc_dat_s { 2367#ifdef __BIG_ENDIAN_BITFIELD 2368 uint64_t data : 64; /**< Local memory region data */ 2369#else 2370 uint64_t data : 64; 2371#endif 2372 } s; 2373 struct cvmx_mio_boot_loc_dat_s cn30xx; 2374 struct cvmx_mio_boot_loc_dat_s cn31xx; 2375 struct cvmx_mio_boot_loc_dat_s cn38xx; 2376 struct cvmx_mio_boot_loc_dat_s cn38xxp2; 2377 struct cvmx_mio_boot_loc_dat_s cn50xx; 2378 struct cvmx_mio_boot_loc_dat_s cn52xx; 2379 struct cvmx_mio_boot_loc_dat_s cn52xxp1; 2380 struct cvmx_mio_boot_loc_dat_s cn56xx; 2381 struct cvmx_mio_boot_loc_dat_s cn56xxp1; 2382 struct cvmx_mio_boot_loc_dat_s cn58xx; 2383 struct cvmx_mio_boot_loc_dat_s cn58xxp1; 2384 struct cvmx_mio_boot_loc_dat_s cn61xx; 2385 struct cvmx_mio_boot_loc_dat_s cn63xx; 2386 struct cvmx_mio_boot_loc_dat_s cn63xxp1; 2387 struct cvmx_mio_boot_loc_dat_s cn66xx; 2388 struct cvmx_mio_boot_loc_dat_s cn68xx; 2389 struct cvmx_mio_boot_loc_dat_s cn68xxp1; 2390 struct cvmx_mio_boot_loc_dat_s cnf71xx; 2391}; 2392typedef union cvmx_mio_boot_loc_dat cvmx_mio_boot_loc_dat_t; 2393 2394/** 2395 * cvmx_mio_boot_pin_defs 2396 * 2397 * MIO_BOOT_PIN_DEFS = MIO Boot Pin Defaults Register 2398 * 2399 */ 2400union cvmx_mio_boot_pin_defs { 2401 uint64_t u64; 2402 struct cvmx_mio_boot_pin_defs_s { 2403#ifdef __BIG_ENDIAN_BITFIELD 2404 uint64_t reserved_32_63 : 32; 2405 uint64_t user1 : 16; /**< BOOT_AD [31:16] latched during power up */ 2406 uint64_t ale : 1; /**< Region 0 default ALE mode */ 2407 uint64_t width : 1; /**< Region 0 default bus width */ 2408 uint64_t dmack_p2 : 1; /**< boot_dmack[2] default polarity */ 2409 uint64_t dmack_p1 : 1; /**< boot_dmack[1] default polarity */ 2410 uint64_t dmack_p0 : 1; /**< boot_dmack[0] default polarity */ 2411 uint64_t term : 2; /**< Selects default driver termination */ 2412 uint64_t nand : 1; /**< Region 0 is NAND flash */ 2413 uint64_t user0 : 8; /**< BOOT_AD [7:0] latched during power up */ 2414#else 2415 uint64_t user0 : 8; 2416 uint64_t nand : 1; 2417 uint64_t term : 2; 2418 uint64_t dmack_p0 : 1; 2419 uint64_t dmack_p1 : 1; 2420 uint64_t dmack_p2 : 1; 2421 uint64_t width : 1; 2422 uint64_t ale : 1; 2423 uint64_t user1 : 16; 2424 uint64_t reserved_32_63 : 32; 2425#endif 2426 } s; 2427 struct cvmx_mio_boot_pin_defs_cn52xx { 2428#ifdef __BIG_ENDIAN_BITFIELD 2429 uint64_t reserved_16_63 : 48; 2430 uint64_t ale : 1; /**< Region 0 default ALE mode */ 2431 uint64_t width : 1; /**< Region 0 default bus width */ 2432 uint64_t reserved_13_13 : 1; 2433 uint64_t dmack_p1 : 1; /**< boot_dmack[1] default polarity */ 2434 uint64_t dmack_p0 : 1; /**< boot_dmack[0] default polarity */ 2435 uint64_t term : 2; /**< Selects default driver termination */ 2436 uint64_t nand : 1; /**< Region 0 is NAND flash */ 2437 uint64_t reserved_0_7 : 8; 2438#else 2439 uint64_t reserved_0_7 : 8; 2440 uint64_t nand : 1; 2441 uint64_t term : 2; 2442 uint64_t dmack_p0 : 1; 2443 uint64_t dmack_p1 : 1; 2444 uint64_t reserved_13_13 : 1; 2445 uint64_t width : 1; 2446 uint64_t ale : 1; 2447 uint64_t reserved_16_63 : 48; 2448#endif 2449 } cn52xx; 2450 struct cvmx_mio_boot_pin_defs_cn56xx { 2451#ifdef __BIG_ENDIAN_BITFIELD 2452 uint64_t reserved_16_63 : 48; 2453 uint64_t ale : 1; /**< Region 0 default ALE mode */ 2454 uint64_t width : 1; /**< Region 0 default bus width */ 2455 uint64_t dmack_p2 : 1; /**< boot_dmack[2] default polarity */ 2456 uint64_t dmack_p1 : 1; /**< boot_dmack[1] default polarity */ 2457 uint64_t dmack_p0 : 1; /**< boot_dmack[0] default polarity */ 2458 uint64_t term : 2; /**< Selects default driver termination */ 2459 uint64_t reserved_0_8 : 9; 2460#else 2461 uint64_t reserved_0_8 : 9; 2462 uint64_t term : 2; 2463 uint64_t dmack_p0 : 1; 2464 uint64_t dmack_p1 : 1; 2465 uint64_t dmack_p2 : 1; 2466 uint64_t width : 1; 2467 uint64_t ale : 1; 2468 uint64_t reserved_16_63 : 48; 2469#endif 2470 } cn56xx; 2471 struct cvmx_mio_boot_pin_defs_cn61xx { 2472#ifdef __BIG_ENDIAN_BITFIELD 2473 uint64_t reserved_32_63 : 32; 2474 uint64_t user1 : 16; /**< BOOT_AD [31:16] latched during power up */ 2475 uint64_t ale : 1; /**< Region 0 default ALE mode */ 2476 uint64_t width : 1; /**< Region 0 default bus width */ 2477 uint64_t reserved_13_13 : 1; 2478 uint64_t dmack_p1 : 1; /**< boot_dmack[1] default polarity */ 2479 uint64_t dmack_p0 : 1; /**< boot_dmack[0] default polarity */ 2480 uint64_t term : 2; /**< Selects default driver termination */ 2481 uint64_t nand : 1; /**< Region 0 is NAND flash */ 2482 uint64_t user0 : 8; /**< BOOT_AD [7:0] latched during power up */ 2483#else 2484 uint64_t user0 : 8; 2485 uint64_t nand : 1; 2486 uint64_t term : 2; 2487 uint64_t dmack_p0 : 1; 2488 uint64_t dmack_p1 : 1; 2489 uint64_t reserved_13_13 : 1; 2490 uint64_t width : 1; 2491 uint64_t ale : 1; 2492 uint64_t user1 : 16; 2493 uint64_t reserved_32_63 : 32; 2494#endif 2495 } cn61xx; 2496 struct cvmx_mio_boot_pin_defs_cn52xx cn63xx; 2497 struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1; 2498 struct cvmx_mio_boot_pin_defs_cn52xx cn66xx; 2499 struct cvmx_mio_boot_pin_defs_cn52xx cn68xx; 2500 struct cvmx_mio_boot_pin_defs_cn52xx cn68xxp1; 2501 struct cvmx_mio_boot_pin_defs_cn61xx cnf71xx; 2502}; 2503typedef union cvmx_mio_boot_pin_defs cvmx_mio_boot_pin_defs_t; 2504 2505/** 2506 * cvmx_mio_boot_reg_cfg# 2507 */ 2508union cvmx_mio_boot_reg_cfgx { 2509 uint64_t u64; 2510 struct cvmx_mio_boot_reg_cfgx_s { 2511#ifdef __BIG_ENDIAN_BITFIELD 2512 uint64_t reserved_44_63 : 20; 2513 uint64_t dmack : 2; /**< Region X DMACK */ 2514 uint64_t tim_mult : 2; /**< Region X timing multiplier */ 2515 uint64_t rd_dly : 3; /**< Region X read sample delay */ 2516 uint64_t sam : 1; /**< Region X SAM mode */ 2517 uint64_t we_ext : 2; /**< Region X write enable count extension */ 2518 uint64_t oe_ext : 2; /**< Region X output enable count extension */ 2519 uint64_t en : 1; /**< Region X enable */ 2520 uint64_t orbit : 1; /**< Region X or bit */ 2521 uint64_t ale : 1; /**< Region X ALE mode */ 2522 uint64_t width : 1; /**< Region X bus width */ 2523 uint64_t size : 12; /**< Region X size */ 2524 uint64_t base : 16; /**< Region X base address */ 2525#else 2526 uint64_t base : 16; 2527 uint64_t size : 12; 2528 uint64_t width : 1; 2529 uint64_t ale : 1; 2530 uint64_t orbit : 1; 2531 uint64_t en : 1; 2532 uint64_t oe_ext : 2; 2533 uint64_t we_ext : 2; 2534 uint64_t sam : 1; 2535 uint64_t rd_dly : 3; 2536 uint64_t tim_mult : 2; 2537 uint64_t dmack : 2; 2538 uint64_t reserved_44_63 : 20; 2539#endif 2540 } s; 2541 struct cvmx_mio_boot_reg_cfgx_cn30xx { 2542#ifdef __BIG_ENDIAN_BITFIELD 2543 uint64_t reserved_37_63 : 27; 2544 uint64_t sam : 1; /**< Region X SAM mode */ 2545 uint64_t we_ext : 2; /**< Region X write enable count extension */ 2546 uint64_t oe_ext : 2; /**< Region X output enable count extension */ 2547 uint64_t en : 1; /**< Region X enable */ 2548 uint64_t orbit : 1; /**< Region X or bit */ 2549 uint64_t ale : 1; /**< Region X ALE mode */ 2550 uint64_t width : 1; /**< Region X bus width */ 2551 uint64_t size : 12; /**< Region X size */ 2552 uint64_t base : 16; /**< Region X base address */ 2553#else 2554 uint64_t base : 16; 2555 uint64_t size : 12; 2556 uint64_t width : 1; 2557 uint64_t ale : 1; 2558 uint64_t orbit : 1; 2559 uint64_t en : 1; 2560 uint64_t oe_ext : 2; 2561 uint64_t we_ext : 2; 2562 uint64_t sam : 1; 2563 uint64_t reserved_37_63 : 27; 2564#endif 2565 } cn30xx; 2566 struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx; 2567 struct cvmx_mio_boot_reg_cfgx_cn38xx { 2568#ifdef __BIG_ENDIAN_BITFIELD 2569 uint64_t reserved_32_63 : 32; 2570 uint64_t en : 1; /**< Region X enable */ 2571 uint64_t orbit : 1; /**< Region X or bit */ 2572 uint64_t reserved_28_29 : 2; 2573 uint64_t size : 12; /**< Region X size */ 2574 uint64_t base : 16; /**< Region X base address */ 2575#else 2576 uint64_t base : 16; 2577 uint64_t size : 12; 2578 uint64_t reserved_28_29 : 2; 2579 uint64_t orbit : 1; 2580 uint64_t en : 1; 2581 uint64_t reserved_32_63 : 32; 2582#endif 2583 } cn38xx; 2584 struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2; 2585 struct cvmx_mio_boot_reg_cfgx_cn50xx { 2586#ifdef __BIG_ENDIAN_BITFIELD 2587 uint64_t reserved_42_63 : 22; 2588 uint64_t tim_mult : 2; /**< Region X timing multiplier */ 2589 uint64_t rd_dly : 3; /**< Region X read sample delay */ 2590 uint64_t sam : 1; /**< Region X SAM mode */ 2591 uint64_t we_ext : 2; /**< Region X write enable count extension */ 2592 uint64_t oe_ext : 2; /**< Region X output enable count extension */ 2593 uint64_t en : 1; /**< Region X enable */ 2594 uint64_t orbit : 1; /**< Region X or bit */ 2595 uint64_t ale : 1; /**< Region X ALE mode */ 2596 uint64_t width : 1; /**< Region X bus width */ 2597 uint64_t size : 12; /**< Region X size */ 2598 uint64_t base : 16; /**< Region X base address */ 2599#else 2600 uint64_t base : 16; 2601 uint64_t size : 12; 2602 uint64_t width : 1; 2603 uint64_t ale : 1; 2604 uint64_t orbit : 1; 2605 uint64_t en : 1; 2606 uint64_t oe_ext : 2; 2607 uint64_t we_ext : 2; 2608 uint64_t sam : 1; 2609 uint64_t rd_dly : 3; 2610 uint64_t tim_mult : 2; 2611 uint64_t reserved_42_63 : 22; 2612#endif 2613 } cn50xx; 2614 struct cvmx_mio_boot_reg_cfgx_s cn52xx; 2615 struct cvmx_mio_boot_reg_cfgx_s cn52xxp1; 2616 struct cvmx_mio_boot_reg_cfgx_s cn56xx; 2617 struct cvmx_mio_boot_reg_cfgx_s cn56xxp1; 2618 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx; 2619 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1; 2620 struct cvmx_mio_boot_reg_cfgx_s cn61xx; 2621 struct cvmx_mio_boot_reg_cfgx_s cn63xx; 2622 struct cvmx_mio_boot_reg_cfgx_s cn63xxp1; 2623 struct cvmx_mio_boot_reg_cfgx_s cn66xx; 2624 struct cvmx_mio_boot_reg_cfgx_s cn68xx; 2625 struct cvmx_mio_boot_reg_cfgx_s cn68xxp1; 2626 struct cvmx_mio_boot_reg_cfgx_s cnf71xx; 2627}; 2628typedef union cvmx_mio_boot_reg_cfgx cvmx_mio_boot_reg_cfgx_t; 2629 2630/** 2631 * cvmx_mio_boot_reg_tim# 2632 */ 2633union cvmx_mio_boot_reg_timx { 2634 uint64_t u64; 2635 struct cvmx_mio_boot_reg_timx_s { 2636#ifdef __BIG_ENDIAN_BITFIELD 2637 uint64_t pagem : 1; /**< Region X page mode */ 2638 uint64_t waitm : 1; /**< Region X wait mode */ 2639 uint64_t pages : 2; /**< Region X page size */ 2640 uint64_t ale : 6; /**< Region X ALE count */ 2641 uint64_t page : 6; /**< Region X page count */ 2642 uint64_t wait : 6; /**< Region X wait count */ 2643 uint64_t pause : 6; /**< Region X pause count */ 2644 uint64_t wr_hld : 6; /**< Region X write hold count */ 2645 uint64_t rd_hld : 6; /**< Region X read hold count */ 2646 uint64_t we : 6; /**< Region X write enable count */ 2647 uint64_t oe : 6; /**< Region X output enable count */ 2648 uint64_t ce : 6; /**< Region X chip enable count */ 2649 uint64_t adr : 6; /**< Region X address count */ 2650#else 2651 uint64_t adr : 6; 2652 uint64_t ce : 6; 2653 uint64_t oe : 6; 2654 uint64_t we : 6; 2655 uint64_t rd_hld : 6; 2656 uint64_t wr_hld : 6; 2657 uint64_t pause : 6; 2658 uint64_t wait : 6; 2659 uint64_t page : 6; 2660 uint64_t ale : 6; 2661 uint64_t pages : 2; 2662 uint64_t waitm : 1; 2663 uint64_t pagem : 1; 2664#endif 2665 } s; 2666 struct cvmx_mio_boot_reg_timx_s cn30xx; 2667 struct cvmx_mio_boot_reg_timx_s cn31xx; 2668 struct cvmx_mio_boot_reg_timx_cn38xx { 2669#ifdef __BIG_ENDIAN_BITFIELD 2670 uint64_t pagem : 1; /**< Region X page mode */ 2671 uint64_t waitm : 1; /**< Region X wait mode */ 2672 uint64_t pages : 2; /**< Region X page size (NOT IN PASS 1) */ 2673 uint64_t reserved_54_59 : 6; 2674 uint64_t page : 6; /**< Region X page count */ 2675 uint64_t wait : 6; /**< Region X wait count */ 2676 uint64_t pause : 6; /**< Region X pause count */ 2677 uint64_t wr_hld : 6; /**< Region X write hold count */ 2678 uint64_t rd_hld : 6; /**< Region X read hold count */ 2679 uint64_t we : 6; /**< Region X write enable count */ 2680 uint64_t oe : 6; /**< Region X output enable count */ 2681 uint64_t ce : 6; /**< Region X chip enable count */ 2682 uint64_t adr : 6; /**< Region X address count */ 2683#else 2684 uint64_t adr : 6; 2685 uint64_t ce : 6; 2686 uint64_t oe : 6; 2687 uint64_t we : 6; 2688 uint64_t rd_hld : 6; 2689 uint64_t wr_hld : 6; 2690 uint64_t pause : 6; 2691 uint64_t wait : 6; 2692 uint64_t page : 6; 2693 uint64_t reserved_54_59 : 6; 2694 uint64_t pages : 2; 2695 uint64_t waitm : 1; 2696 uint64_t pagem : 1; 2697#endif 2698 } cn38xx; 2699 struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2; 2700 struct cvmx_mio_boot_reg_timx_s cn50xx; 2701 struct cvmx_mio_boot_reg_timx_s cn52xx; 2702 struct cvmx_mio_boot_reg_timx_s cn52xxp1; 2703 struct cvmx_mio_boot_reg_timx_s cn56xx; 2704 struct cvmx_mio_boot_reg_timx_s cn56xxp1; 2705 struct cvmx_mio_boot_reg_timx_s cn58xx; 2706 struct cvmx_mio_boot_reg_timx_s cn58xxp1; 2707 struct cvmx_mio_boot_reg_timx_s cn61xx; 2708 struct cvmx_mio_boot_reg_timx_s cn63xx; 2709 struct cvmx_mio_boot_reg_timx_s cn63xxp1; 2710 struct cvmx_mio_boot_reg_timx_s cn66xx; 2711 struct cvmx_mio_boot_reg_timx_s cn68xx; 2712 struct cvmx_mio_boot_reg_timx_s cn68xxp1; 2713 struct cvmx_mio_boot_reg_timx_s cnf71xx; 2714}; 2715typedef union cvmx_mio_boot_reg_timx cvmx_mio_boot_reg_timx_t; 2716 2717/** 2718 * cvmx_mio_boot_thr 2719 * 2720 * MIO_BOOT_THR = MIO Boot Threshold Register 2721 * 2722 * Contains MIO Boot threshold values: 2723 * 2724 * FIF_THR = Assert ncb__busy when the Boot NCB input FIFO reaches this level (not typically for 2725 * customer use). 2726 * 2727 * DMA_THR = When non-DMA accesses are pending, perform a DMA access after this value of non-DMA 2728 * accesses have completed. If set to zero, only perform a DMA access when non-DMA 2729 * accesses are not pending. 2730 */ 2731union cvmx_mio_boot_thr { 2732 uint64_t u64; 2733 struct cvmx_mio_boot_thr_s { 2734#ifdef __BIG_ENDIAN_BITFIELD 2735 uint64_t reserved_22_63 : 42; 2736 uint64_t dma_thr : 6; /**< DMA threshold */ 2737 uint64_t reserved_14_15 : 2; 2738 uint64_t fif_cnt : 6; /**< Current NCB FIFO count */ 2739 uint64_t reserved_6_7 : 2; 2740 uint64_t fif_thr : 6; /**< NCB busy threshold */ 2741#else 2742 uint64_t fif_thr : 6; 2743 uint64_t reserved_6_7 : 2; 2744 uint64_t fif_cnt : 6; 2745 uint64_t reserved_14_15 : 2; 2746 uint64_t dma_thr : 6; 2747 uint64_t reserved_22_63 : 42; 2748#endif 2749 } s; 2750 struct cvmx_mio_boot_thr_cn30xx { 2751#ifdef __BIG_ENDIAN_BITFIELD 2752 uint64_t reserved_14_63 : 50; 2753 uint64_t fif_cnt : 6; /**< Current NCB FIFO count */ 2754 uint64_t reserved_6_7 : 2; 2755 uint64_t fif_thr : 6; /**< NCB busy threshold */ 2756#else 2757 uint64_t fif_thr : 6; 2758 uint64_t reserved_6_7 : 2; 2759 uint64_t fif_cnt : 6; 2760 uint64_t reserved_14_63 : 50; 2761#endif 2762 } cn30xx; 2763 struct cvmx_mio_boot_thr_cn30xx cn31xx; 2764 struct cvmx_mio_boot_thr_cn30xx cn38xx; 2765 struct cvmx_mio_boot_thr_cn30xx cn38xxp2; 2766 struct cvmx_mio_boot_thr_cn30xx cn50xx; 2767 struct cvmx_mio_boot_thr_s cn52xx; 2768 struct cvmx_mio_boot_thr_s cn52xxp1; 2769 struct cvmx_mio_boot_thr_s cn56xx; 2770 struct cvmx_mio_boot_thr_s cn56xxp1; 2771 struct cvmx_mio_boot_thr_cn30xx cn58xx; 2772 struct cvmx_mio_boot_thr_cn30xx cn58xxp1; 2773 struct cvmx_mio_boot_thr_s cn61xx; 2774 struct cvmx_mio_boot_thr_s cn63xx; 2775 struct cvmx_mio_boot_thr_s cn63xxp1; 2776 struct cvmx_mio_boot_thr_s cn66xx; 2777 struct cvmx_mio_boot_thr_s cn68xx; 2778 struct cvmx_mio_boot_thr_s cn68xxp1; 2779 struct cvmx_mio_boot_thr_s cnf71xx; 2780}; 2781typedef union cvmx_mio_boot_thr cvmx_mio_boot_thr_t; 2782 2783/** 2784 * cvmx_mio_emm_buf_dat 2785 * 2786 * MIO_EMM_BUF_DAT = MIO EMMC Data buffer access Register 2787 * 2788 */ 2789union cvmx_mio_emm_buf_dat { 2790 uint64_t u64; 2791 struct cvmx_mio_emm_buf_dat_s { 2792#ifdef __BIG_ENDIAN_BITFIELD 2793 uint64_t dat : 64; /**< Direct access to the 1KB data buffer memory. Address 2794 specified by MIO_EMM_BUF_IDX */ 2795#else 2796 uint64_t dat : 64; 2797#endif 2798 } s; 2799 struct cvmx_mio_emm_buf_dat_s cn61xx; 2800 struct cvmx_mio_emm_buf_dat_s cnf71xx; 2801}; 2802typedef union cvmx_mio_emm_buf_dat cvmx_mio_emm_buf_dat_t; 2803 2804/** 2805 * cvmx_mio_emm_buf_idx 2806 * 2807 * MIO_EMM_BUF_IDX = MIO EMMC Data buffer address Register 2808 * 2809 */ 2810union cvmx_mio_emm_buf_idx { 2811 uint64_t u64; 2812 struct cvmx_mio_emm_buf_idx_s { 2813#ifdef __BIG_ENDIAN_BITFIELD 2814 uint64_t reserved_17_63 : 47; 2815 uint64_t inc : 1; /**< Automatically advance BUF_SEL/OFFSET after each access to 2816 MIO_EMM_BUF_DAT. Wraps after last offset of last data buffer. */ 2817 uint64_t reserved_7_15 : 9; 2818 uint64_t buf_num : 1; /**< Specify the data buffer for the next access to MIO_EMM_BUF_DAT */ 2819 uint64_t offset : 6; /**< Specify the 8B data buffer offset for the next access to 2820 MIO_EMM_BUF_DAT */ 2821#else 2822 uint64_t offset : 6; 2823 uint64_t buf_num : 1; 2824 uint64_t reserved_7_15 : 9; 2825 uint64_t inc : 1; 2826 uint64_t reserved_17_63 : 47; 2827#endif 2828 } s; 2829 struct cvmx_mio_emm_buf_idx_s cn61xx; 2830 struct cvmx_mio_emm_buf_idx_s cnf71xx; 2831}; 2832typedef union cvmx_mio_emm_buf_idx cvmx_mio_emm_buf_idx_t; 2833 2834/** 2835 * cvmx_mio_emm_cfg 2836 * 2837 * MIO_EMM_CFG = MIO EMMC Configuration Register 2838 * 2839 */ 2840union cvmx_mio_emm_cfg { 2841 uint64_t u64; 2842 struct cvmx_mio_emm_cfg_s { 2843#ifdef __BIG_ENDIAN_BITFIELD 2844 uint64_t reserved_17_63 : 47; 2845 uint64_t boot_fail : 1; /**< SW should set BOOT_FAIL when an unrecoverable error occurs 2846 while attempt to boot from eMMC or NOR Flash. When set, the 2847 following pattern will be output: 2848 BOOT_AD[7:0] pulled up to 1 2849 BOOT_CE_N[7:0] driven to 1 2850 BOOT_ALE driven to 0 2851 BOOT_OE_L driven to 1 2852 BOOT_WE_L driven to 1 */ 2853 uint64_t reserved_4_15 : 12; 2854 uint64_t bus_ena : 4; /**< eMMC bus enable mask. 2855 2856 Setting bit0 of BUS_ENA causes BOOT_CE[1] to become dedicated 2857 eMMC bus 0 command (ie. disabling any NOR use) 2858 2859 Setting bit1 of BUS_ENA causes BOOT_CE[2] to become dedicated 2860 eMMC bus 1 command (ie. disabling any NOR use). 2861 2862 Setting bit2 of BUS_ENA causes BOOT_CE[3] to become dedicated 2863 eMMC bus 2 command (ie. disabling any NOR use). 2864 2865 Setting bit3 of BUS_ENA causes BOOT_CE[4] to become dedicated 2866 eMMC bus 3 command (ie. disabling any NOR use). 2867 2868 Setting any bit of BUS_ENA causes BOOT_CE[5] to become the eMMC 2869 clock for both bus0 and bus1. */ 2870#else 2871 uint64_t bus_ena : 4; 2872 uint64_t reserved_4_15 : 12; 2873 uint64_t boot_fail : 1; 2874 uint64_t reserved_17_63 : 47; 2875#endif 2876 } s; 2877 struct cvmx_mio_emm_cfg_s cn61xx; 2878 struct cvmx_mio_emm_cfg_s cnf71xx; 2879}; 2880typedef union cvmx_mio_emm_cfg cvmx_mio_emm_cfg_t; 2881 2882/** 2883 * cvmx_mio_emm_cmd 2884 * 2885 * MIO_EMM_CMD = MIO EMMC Command Register 2886 * 2887 */ 2888union cvmx_mio_emm_cmd { 2889 uint64_t u64; 2890 struct cvmx_mio_emm_cmd_s { 2891#ifdef __BIG_ENDIAN_BITFIELD 2892 uint64_t reserved_62_63 : 2; 2893 uint64_t bus_id : 2; /**< Specify the eMMC bus */ 2894 uint64_t cmd_val : 1; /**< Request valid. SW writes this bit to a 1. HW clears it when 2895 the operation completes. */ 2896 uint64_t reserved_56_58 : 3; 2897 uint64_t dbuf : 1; /**< Specify the data buffer to be used for a block transfer. */ 2898 uint64_t offset : 6; /**< Debug only. Specify the number of 8 byte transfers in the 2899 used in the command. Value is 64-OFFSET. The block transfer 2900 will still start at the first btye in the 512B data buffer. 2901 SW must ensure CMD16 has updated the card block length. */ 2902 uint64_t reserved_43_48 : 6; 2903 uint64_t ctype_xor : 2; /**< Reserved. Must be zero */ 2904 uint64_t rtype_xor : 3; /**< Reserved. Must be zero */ 2905 uint64_t cmd_idx : 6; /**< eMMC command */ 2906 uint64_t arg : 32; /**< eMMC command argument */ 2907#else 2908 uint64_t arg : 32; 2909 uint64_t cmd_idx : 6; 2910 uint64_t rtype_xor : 3; 2911 uint64_t ctype_xor : 2; 2912 uint64_t reserved_43_48 : 6; 2913 uint64_t offset : 6; 2914 uint64_t dbuf : 1; 2915 uint64_t reserved_56_58 : 3; 2916 uint64_t cmd_val : 1; 2917 uint64_t bus_id : 2; 2918 uint64_t reserved_62_63 : 2; 2919#endif 2920 } s; 2921 struct cvmx_mio_emm_cmd_s cn61xx; 2922 struct cvmx_mio_emm_cmd_s cnf71xx; 2923}; 2924typedef union cvmx_mio_emm_cmd cvmx_mio_emm_cmd_t; 2925 2926/** 2927 * cvmx_mio_emm_dma 2928 * 2929 * MIO_EMM_DMA = MIO EMMC DMA config Register 2930 * 2931 */ 2932union cvmx_mio_emm_dma { 2933 uint64_t u64; 2934 struct cvmx_mio_emm_dma_s { 2935#ifdef __BIG_ENDIAN_BITFIELD 2936 uint64_t reserved_62_63 : 2; 2937 uint64_t bus_id : 2; /**< Specify the eMMC bus */ 2938 uint64_t dma_val : 1; /**< SW writes this bit to a 1 to indicate that HW should perform 2939 the DMA transfer. HW clears when DMA operation completes or 2940 is terminated. */ 2941 uint64_t sector : 1; /**< Specify CARD_ADDR and eMMC are using sector (512B) addressing. */ 2942 uint64_t dat_null : 1; /**< Do not perform any eMMC commands. A DMA read will return all 2943 0s. A DMA write tosses the data. In the case of a failure, 2944 this can be used to unwind the DMA engine. */ 2945 uint64_t thres : 6; /**< Number of 8B blocks of data that must exist in the DBUF before 2946 the starting the 512B block transfer. 0 indicates to wait for 2947 the entire block. */ 2948 uint64_t rel_wr : 1; /**< Set the reliable write parameter when performing CMD23 2949 (SET_BLOCK_COUNT) for a multiple block */ 2950 uint64_t rw : 1; /**< R/W bit (0 = read, 1 = write) */ 2951 uint64_t multi : 1; /**< Perform operation using a multiple block command instead of a 2952 series of single block commands. */ 2953 uint64_t block_cnt : 16; /**< Number of blocks to read/write. Hardware decrements the block 2954 count after each successful block transfer. */ 2955 uint64_t card_addr : 32; /**< Data address for media =<2GB is a 32bit byte address and data 2956 address for media > 2GB is a 32bit sector (512B) address. 2957 Hardware advances the card address after each successful block 2958 transfer by 512 for byte addressing and by 1 for sector 2959 addressing. */ 2960#else 2961 uint64_t card_addr : 32; 2962 uint64_t block_cnt : 16; 2963 uint64_t multi : 1; 2964 uint64_t rw : 1; 2965 uint64_t rel_wr : 1; 2966 uint64_t thres : 6; 2967 uint64_t dat_null : 1; 2968 uint64_t sector : 1; 2969 uint64_t dma_val : 1; 2970 uint64_t bus_id : 2; 2971 uint64_t reserved_62_63 : 2; 2972#endif 2973 } s; 2974 struct cvmx_mio_emm_dma_s cn61xx; 2975 struct cvmx_mio_emm_dma_s cnf71xx; 2976}; 2977typedef union cvmx_mio_emm_dma cvmx_mio_emm_dma_t; 2978 2979/** 2980 * cvmx_mio_emm_int 2981 * 2982 * MIO_EMM_INT = MIO EMMC Interrupt Register 2983 * 2984 */ 2985union cvmx_mio_emm_int { 2986 uint64_t u64; 2987 struct cvmx_mio_emm_int_s { 2988#ifdef __BIG_ENDIAN_BITFIELD 2989 uint64_t reserved_7_63 : 57; 2990 uint64_t switch_err : 1; /**< Switch operation encountered an error. */ 2991 uint64_t switch_done : 1; /**< Switch operation completed successfully */ 2992 uint64_t dma_err : 1; /**< DMA transfer encountered an error. See MIO_EMM_RSP. */ 2993 uint64_t cmd_err : 1; /**< Operation specified by MIO_EMM_CMD encountered an error. See 2994 MIO_EMM_RSP. */ 2995 uint64_t dma_done : 1; /**< DMA transfer completed successfully */ 2996 uint64_t cmd_done : 1; /**< Operation specified by MIO_EMM_CMD completed successfully */ 2997 uint64_t buf_done : 1; /**< The next 512B block transfer of a multi-block transfer has 2998 completed. */ 2999#else 3000 uint64_t buf_done : 1; 3001 uint64_t cmd_done : 1; 3002 uint64_t dma_done : 1; 3003 uint64_t cmd_err : 1; 3004 uint64_t dma_err : 1; 3005 uint64_t switch_done : 1; 3006 uint64_t switch_err : 1; 3007 uint64_t reserved_7_63 : 57; 3008#endif 3009 } s; 3010 struct cvmx_mio_emm_int_s cn61xx; 3011 struct cvmx_mio_emm_int_s cnf71xx; 3012}; 3013typedef union cvmx_mio_emm_int cvmx_mio_emm_int_t; 3014 3015/** 3016 * cvmx_mio_emm_int_en 3017 * 3018 * MIO_EMM_INT_EN = MIO EMMC Interrupt enable Register 3019 * 3020 */ 3021union cvmx_mio_emm_int_en { 3022 uint64_t u64; 3023 struct cvmx_mio_emm_int_en_s { 3024#ifdef __BIG_ENDIAN_BITFIELD 3025 uint64_t reserved_7_63 : 57; 3026 uint64_t switch_err : 1; /**< Switch operation encountered an error. */ 3027 uint64_t switch_done : 1; /**< Switch operation completed. */ 3028 uint64_t dma_err : 1; /**< DMA transfer encountered an error. See MIO_EMM_RSP. */ 3029 uint64_t cmd_err : 1; /**< Operation specified by MIO_EMM_CMD encountered an error. See 3030 MIO_EMM_RSP. */ 3031 uint64_t dma_done : 1; /**< DMA transfer completed */ 3032 uint64_t cmd_done : 1; /**< Operation specified by MIO_EMM_CMD completed */ 3033 uint64_t buf_done : 1; /**< The next 512B block transfer of a multi-block transfer has 3034 completed. */ 3035#else 3036 uint64_t buf_done : 1; 3037 uint64_t cmd_done : 1; 3038 uint64_t dma_done : 1; 3039 uint64_t cmd_err : 1; 3040 uint64_t dma_err : 1; 3041 uint64_t switch_done : 1; 3042 uint64_t switch_err : 1; 3043 uint64_t reserved_7_63 : 57; 3044#endif 3045 } s; 3046 struct cvmx_mio_emm_int_en_s cn61xx; 3047 struct cvmx_mio_emm_int_en_s cnf71xx; 3048}; 3049typedef union cvmx_mio_emm_int_en cvmx_mio_emm_int_en_t; 3050 3051/** 3052 * cvmx_mio_emm_mode# 3053 * 3054 * MIO_EMM_MODE = MIO EMMC Operating mode Register 3055 * 3056 */ 3057union cvmx_mio_emm_modex { 3058 uint64_t u64; 3059 struct cvmx_mio_emm_modex_s { 3060#ifdef __BIG_ENDIAN_BITFIELD 3061 uint64_t reserved_49_63 : 15; 3062 uint64_t hs_timing : 1; /**< Current high speed timing mode. Required when CLK frequency 3063 higher than 20MHz. */ 3064 uint64_t reserved_43_47 : 5; 3065 uint64_t bus_width : 3; /**< Current card bus mode. Out of reset, the card is in 1 bit data 3066 bus mode. Select bus width. 3067 3068 0 - 1 bit data bus (power on) 3069 1 - 4 bit data bus 3070 2 - 8 bit data bus 3071 5 - 4 bit data bus (dual data rate) 3072 6 - 8 bit data bus (dual data rate) */ 3073 uint64_t reserved_36_39 : 4; 3074 uint64_t power_class : 4; /**< Out of reset, the card power class is 0, which is the minimum 3075 current consumption class for the card. EXT_CSD bytes 3076 [203:200] and [239:238] contain the power class for different 3077 BUS_WITDH and CLK frequencies. Software should write this 3078 field with the 4-bit field from the EXT_CSD bytes 3079 corresponding to the selected operating mode. */ 3080 uint64_t clk_hi : 16; /**< Current number of sclk cycles to hold the eMMC CLK pin high */ 3081 uint64_t clk_lo : 16; /**< Current number of sclk cycles to hold the eMMC CLK pin low. */ 3082#else 3083 uint64_t clk_lo : 16; 3084 uint64_t clk_hi : 16; 3085 uint64_t power_class : 4; 3086 uint64_t reserved_36_39 : 4; 3087 uint64_t bus_width : 3; 3088 uint64_t reserved_43_47 : 5; 3089 uint64_t hs_timing : 1; 3090 uint64_t reserved_49_63 : 15; 3091#endif 3092 } s; 3093 struct cvmx_mio_emm_modex_s cn61xx; 3094 struct cvmx_mio_emm_modex_s cnf71xx; 3095}; 3096typedef union cvmx_mio_emm_modex cvmx_mio_emm_modex_t; 3097 3098/** 3099 * cvmx_mio_emm_rca 3100 */ 3101union cvmx_mio_emm_rca { 3102 uint64_t u64; 3103 struct cvmx_mio_emm_rca_s { 3104#ifdef __BIG_ENDIAN_BITFIELD 3105 uint64_t reserved_16_63 : 48; 3106 uint64_t card_rca : 16; /**< Whenever SW performs CMD7, HW will update CARD_RCA with the 3107 relative card address from the MIO_EMM_CMD[ARG] unless the 3108 operations encounters an error. */ 3109#else 3110 uint64_t card_rca : 16; 3111 uint64_t reserved_16_63 : 48; 3112#endif 3113 } s; 3114 struct cvmx_mio_emm_rca_s cn61xx; 3115 struct cvmx_mio_emm_rca_s cnf71xx; 3116}; 3117typedef union cvmx_mio_emm_rca cvmx_mio_emm_rca_t; 3118 3119/** 3120 * cvmx_mio_emm_rsp_hi 3121 * 3122 * MIO_EMM_RSP_HI = MIO EMMC Response data high Register 3123 * 3124 */ 3125union cvmx_mio_emm_rsp_hi { 3126 uint64_t u64; 3127 struct cvmx_mio_emm_rsp_hi_s { 3128#ifdef __BIG_ENDIAN_BITFIELD 3129 uint64_t dat : 64; /**< Command response (as per JEDEC eMMC spec) 3130 3131 RSP_TYPE=1 - DAT[63:0] - 0x0 3132 RSP_TYPE=2 - DAT[63:0] - CID[127:64] or CSD[127:64] 3133 RSP_TYPE=3 - DAT[63:0] - 0x0 3134 RSP_TYPE=4 - DAT[63:0] - 0x0 3135 RSP_TYPE=5 - DAT[63:0] - 0x0 */ 3136#else 3137 uint64_t dat : 64; 3138#endif 3139 } s; 3140 struct cvmx_mio_emm_rsp_hi_s cn61xx; 3141 struct cvmx_mio_emm_rsp_hi_s cnf71xx; 3142}; 3143typedef union cvmx_mio_emm_rsp_hi cvmx_mio_emm_rsp_hi_t; 3144 3145/** 3146 * cvmx_mio_emm_rsp_lo 3147 * 3148 * MIO_EMM_RSP_LO = MIO EMMC Response data low Register 3149 * 3150 */ 3151union cvmx_mio_emm_rsp_lo { 3152 uint64_t u64; 3153 struct cvmx_mio_emm_rsp_lo_s { 3154#ifdef __BIG_ENDIAN_BITFIELD 3155 uint64_t dat : 64; /**< Command response (as per JEDEC eMMC spec) 3156 3157 RSP_TYPE = 1 3158 DAT[63:46] - 0x0 3159 DAT[45:40] - Command index 3160 DAT[39: 8] - Card status 3161 DAT[ 7: 1] - CRC7 3162 DAT[ 0] - End bit 3163 3164 RSP_TYPE = 2 3165 DAT[63: 1] - CID[63:1] or CSD[63:1] including CRC 3166 DAT[ 0] - End bit 3167 3168 RSP_TYPE = 3 3169 DAT[63:46] - 0x0 3170 DAT[45:40] - Check bits (0x3f) 3171 DAT[39: 8] - OCR register 3172 DAT[ 7: 1] - Check bits (0x7f) 3173 DAT[ 0] - End bit 3174 3175 RSP_TYPE = 4 3176 DAT[63:46] - 0x0 3177 DAT[45:40] - CMD39 ('10111') 3178 DAT[39:24] - RCA[31:16] 3179 DAT[ 23] - Status 3180 DAT[22:16] - Register address 3181 DAT[15: 8] - Register contents 3182 DAT[ 7: 1] - CRC7 3183 DAT[ 0] - End bit 3184 3185 RSP_TYPE = 5 3186 DAT[63:46] - 0x0 3187 DAT[45:40] - CMD40 ('10100') 3188 DAT[39:24] - RCA[31:16] 3189 DAT[ 23] - Status 3190 DAT[22:16] - Register address 3191 DAT[15: 8] - Not defined. May be used for IRQ data 3192 DAT[ 7: 1] - CRC7 3193 DAT[ 0] - End bit */ 3194#else 3195 uint64_t dat : 64; 3196#endif 3197 } s; 3198 struct cvmx_mio_emm_rsp_lo_s cn61xx; 3199 struct cvmx_mio_emm_rsp_lo_s cnf71xx; 3200}; 3201typedef union cvmx_mio_emm_rsp_lo cvmx_mio_emm_rsp_lo_t; 3202 3203/** 3204 * cvmx_mio_emm_rsp_sts 3205 * 3206 * MIO_EMM_RSP_STS = MIO EMMC Response status Register 3207 * 3208 */ 3209union cvmx_mio_emm_rsp_sts { 3210 uint64_t u64; 3211 struct cvmx_mio_emm_rsp_sts_s { 3212#ifdef __BIG_ENDIAN_BITFIELD 3213 uint64_t reserved_62_63 : 2; 3214 uint64_t bus_id : 2; /**< eMMC bus id to which the response status corresponds. */ 3215 uint64_t cmd_val : 1; /**< Read-only copy of MIO_EMM_CMD[CMD_VAL]. CMD_VAL=1 indicates a 3216 direct operation is in progress. */ 3217 uint64_t switch_val : 1; /**< Read-only copy of MIO_EMM_SWITCH[SWITCH_EXE]. SWITCH_VAL=1 3218 indicates a switch operation is in progress. */ 3219 uint64_t dma_val : 1; /**< Read-only copy of MIO_EMM_DMA[DMA_VAL]. DMA_VAL=1 indicates a 3220 DMA operation is in progress. */ 3221 uint64_t dma_pend : 1; /**< The DMA engine has a pending transfer resulting from an error. 3222 SW can resume the transfer by writing MIO_EMM_DMA[DMA_VAL]=1. 3223 SW can terminate the transfer by writing MIO_EMM_DMA[DMA_VAL]=1 3224 and MIO_EMM_DMA[NULL]=1. HW will clear DMA_PEND and perform 3225 the DMA operation */ 3226 uint64_t reserved_29_55 : 27; 3227 uint64_t dbuf_err : 1; /**< For CMD_TYPE=1, indicates a DMA read data arrived from card 3228 without a free DBUF. 3229 3230 For CMD_TYPE=2, indicates a DBUF underflow occurred during a 3231 DMA write. See MIO_EMM_DMA[THRES]. */ 3232 uint64_t reserved_24_27 : 4; 3233 uint64_t dbuf : 1; /**< DBUF corresponding to the most recently attempted block 3234 transfer. */ 3235 uint64_t blk_timeout : 1; /**< Timeout waiting for read data or 3bit CRC token */ 3236 uint64_t blk_crc_err : 1; /**< For CMD_TYPE=1, indicates a card read data CRC mismatch. 3237 MIO_EMM_RSP_STS[DBUF] indicates the failing data buffer. 3238 3239 For CMD_TYPE=2, indicates card returned 3-bit CRC status token 3240 indicating the card encountered a write data CRC check 3241 mismatch. MIO_EMM_RSP_STS[DBUF] indicates the failing data 3242 buffer. */ 3243 uint64_t rsp_busybit : 1; /**< Debug only. eMMC protocol utilizes DAT0 as a busy signal 3244 during block writes and R1b responses. */ 3245 uint64_t stp_timeout : 1; /**< Stop transmission response timeout. */ 3246 uint64_t stp_crc_err : 1; /**< Stop transmission response had a CRC error */ 3247 uint64_t stp_bad_sts : 1; /**< Stop transmission response had bad status. */ 3248 uint64_t stp_val : 1; /**< Stop transmission response valid. */ 3249 uint64_t rsp_timeout : 1; /**< Response timeout */ 3250 uint64_t rsp_crc_err : 1; /**< Response CRC error */ 3251 uint64_t rsp_bad_sts : 1; /**< Response bad status */ 3252 uint64_t rsp_val : 1; /**< Response id. See MIO_EMM_RSP_HI/LO */ 3253 uint64_t rsp_type : 3; /**< Indicates the response type. See MIO_EMM_RSP_HI/LO */ 3254 uint64_t cmd_type : 2; /**< eMMC command type (0=no data, 1=read, 2=write) */ 3255 uint64_t cmd_idx : 6; /**< eMMC command index most recently attempted */ 3256 uint64_t cmd_done : 1; /**< eMMC command completed. Once the command has complete, the 3257 status is final and can be examined by SW. */ 3258#else 3259 uint64_t cmd_done : 1; 3260 uint64_t cmd_idx : 6; 3261 uint64_t cmd_type : 2; 3262 uint64_t rsp_type : 3; 3263 uint64_t rsp_val : 1; 3264 uint64_t rsp_bad_sts : 1; 3265 uint64_t rsp_crc_err : 1; 3266 uint64_t rsp_timeout : 1; 3267 uint64_t stp_val : 1; 3268 uint64_t stp_bad_sts : 1; 3269 uint64_t stp_crc_err : 1; 3270 uint64_t stp_timeout : 1; 3271 uint64_t rsp_busybit : 1; 3272 uint64_t blk_crc_err : 1; 3273 uint64_t blk_timeout : 1; 3274 uint64_t dbuf : 1; 3275 uint64_t reserved_24_27 : 4; 3276 uint64_t dbuf_err : 1; 3277 uint64_t reserved_29_55 : 27; 3278 uint64_t dma_pend : 1; 3279 uint64_t dma_val : 1; 3280 uint64_t switch_val : 1; 3281 uint64_t cmd_val : 1; 3282 uint64_t bus_id : 2; 3283 uint64_t reserved_62_63 : 2; 3284#endif 3285 } s; 3286 struct cvmx_mio_emm_rsp_sts_s cn61xx; 3287 struct cvmx_mio_emm_rsp_sts_s cnf71xx; 3288}; 3289typedef union cvmx_mio_emm_rsp_sts cvmx_mio_emm_rsp_sts_t; 3290 3291/** 3292 * cvmx_mio_emm_sample 3293 */ 3294union cvmx_mio_emm_sample { 3295 uint64_t u64; 3296 struct cvmx_mio_emm_sample_s { 3297#ifdef __BIG_ENDIAN_BITFIELD 3298 uint64_t reserved_26_63 : 38; 3299 uint64_t cmd_cnt : 10; /**< Number of SCLK cycles before the eMMC clock edge to sample the 3300 command pin. */ 3301 uint64_t reserved_10_15 : 6; 3302 uint64_t dat_cnt : 10; /**< Number of SCLK cycles before the eMMC clock rising edge to 3303 sample the data pin. */ 3304#else 3305 uint64_t dat_cnt : 10; 3306 uint64_t reserved_10_15 : 6; 3307 uint64_t cmd_cnt : 10; 3308 uint64_t reserved_26_63 : 38; 3309#endif 3310 } s; 3311 struct cvmx_mio_emm_sample_s cn61xx; 3312 struct cvmx_mio_emm_sample_s cnf71xx; 3313}; 3314typedef union cvmx_mio_emm_sample cvmx_mio_emm_sample_t; 3315 3316/** 3317 * cvmx_mio_emm_sts_mask 3318 */ 3319union cvmx_mio_emm_sts_mask { 3320 uint64_t u64; 3321 struct cvmx_mio_emm_sts_mask_s { 3322#ifdef __BIG_ENDIAN_BITFIELD 3323 uint64_t reserved_32_63 : 32; 3324 uint64_t sts_msk : 32; /**< Any bit set in STS_MSK causes the corresponding bit in the card 3325 status to be considered when computing response bad status. */ 3326#else 3327 uint64_t sts_msk : 32; 3328 uint64_t reserved_32_63 : 32; 3329#endif 3330 } s; 3331 struct cvmx_mio_emm_sts_mask_s cn61xx; 3332 struct cvmx_mio_emm_sts_mask_s cnf71xx; 3333}; 3334typedef union cvmx_mio_emm_sts_mask cvmx_mio_emm_sts_mask_t; 3335 3336/** 3337 * cvmx_mio_emm_switch 3338 * 3339 * MIO_EMM_SWITCH = MIO EMMC Operating mode switch Register 3340 * 3341 */ 3342union cvmx_mio_emm_switch { 3343 uint64_t u64; 3344 struct cvmx_mio_emm_switch_s { 3345#ifdef __BIG_ENDIAN_BITFIELD 3346 uint64_t reserved_62_63 : 2; 3347 uint64_t bus_id : 2; /**< Specify the eMMC bus */ 3348 uint64_t switch_exe : 1; /**< When SWITCH_EXE is 0, the operating modes will be update 3349 directly without performing any SWITCH operations. This 3350 allows SW to perform the SWITCH operations manually, then 3351 update the HW. 3352 3353 SW writes this bit to a 1 to indicate that HW should perform 3354 the necessary SWITCH operations. First, the POWER_CLASS 3355 switch will be performed. If it fails, SWITCH_ERR0 will be 3356 and the remaining SWITCH operations will not be performed. If 3357 is succeeds, the POWER_CLASS field will be updated and the 3358 HS_TIMING switch will be performed. If it fails, SWITCH_ERR1 3359 will be set and the remaining SWITCH operations will not be 3360 performed. If is succeeds, the HS_TIMING field will be 3361 updated and the BUS_WITDH switch operation will be performed. 3362 If it fails, SWITCH_ERR2 will be set. If it succeeds, the 3363 BUS_WITDH will be updated. 3364 3365 Changes to CLK_HI and CLK_LO are discarded if any switch error 3366 occurs. */ 3367 uint64_t switch_err0 : 1; /**< Error encounter while performing POWER_CLASS switch . See 3368 MIO_EMM_RSP_STS */ 3369 uint64_t switch_err1 : 1; /**< Error encounter while performing HS_TIMING switch . See 3370 MIO_EMM_RSP_STS */ 3371 uint64_t switch_err2 : 1; /**< Error encounter while performing BUS_WIDTH switch . See 3372 MIO_EMM_RSP_STS */ 3373 uint64_t reserved_49_55 : 7; 3374 uint64_t hs_timing : 1; /**< Requested update to HS_TIMING */ 3375 uint64_t reserved_43_47 : 5; 3376 uint64_t bus_width : 3; /**< Requested update to BUS_WIDTH */ 3377 uint64_t reserved_36_39 : 4; 3378 uint64_t power_class : 4; /**< Requested update to POWER_CLASS */ 3379 uint64_t clk_hi : 16; /**< Requested update to CLK_HI */ 3380 uint64_t clk_lo : 16; /**< Requested update to CLK_LO */ 3381#else 3382 uint64_t clk_lo : 16; 3383 uint64_t clk_hi : 16; 3384 uint64_t power_class : 4; 3385 uint64_t reserved_36_39 : 4; 3386 uint64_t bus_width : 3; 3387 uint64_t reserved_43_47 : 5; 3388 uint64_t hs_timing : 1; 3389 uint64_t reserved_49_55 : 7; 3390 uint64_t switch_err2 : 1; 3391 uint64_t switch_err1 : 1; 3392 uint64_t switch_err0 : 1; 3393 uint64_t switch_exe : 1; 3394 uint64_t bus_id : 2; 3395 uint64_t reserved_62_63 : 2; 3396#endif 3397 } s; 3398 struct cvmx_mio_emm_switch_s cn61xx; 3399 struct cvmx_mio_emm_switch_s cnf71xx; 3400}; 3401typedef union cvmx_mio_emm_switch cvmx_mio_emm_switch_t; 3402 3403/** 3404 * cvmx_mio_emm_wdog 3405 * 3406 * MIO_EMM_WDOG = MIO EMMC Watchdog Register 3407 * 3408 */ 3409union cvmx_mio_emm_wdog { 3410 uint64_t u64; 3411 struct cvmx_mio_emm_wdog_s { 3412#ifdef __BIG_ENDIAN_BITFIELD 3413 uint64_t reserved_26_63 : 38; 3414 uint64_t clk_cnt : 26; /**< Number of CLK_CNT cycles to wait for the card to return a 3415 response, read data, or the 3-bit CRC status token. */ 3416#else 3417 uint64_t clk_cnt : 26; 3418 uint64_t reserved_26_63 : 38; 3419#endif 3420 } s; 3421 struct cvmx_mio_emm_wdog_s cn61xx; 3422 struct cvmx_mio_emm_wdog_s cnf71xx; 3423}; 3424typedef union cvmx_mio_emm_wdog cvmx_mio_emm_wdog_t; 3425 3426/** 3427 * cvmx_mio_fus_bnk_dat# 3428 * 3429 * Notes: 3430 * The intial state of MIO_FUS_BNK_DAT* is as if bank6 was just read i.e. DAT* = fus[895:768] 3431 * 3432 */ 3433union cvmx_mio_fus_bnk_datx { 3434 uint64_t u64; 3435 struct cvmx_mio_fus_bnk_datx_s { 3436#ifdef __BIG_ENDIAN_BITFIELD 3437 uint64_t dat : 64; /**< Efuse bank store 3438 For reads, the DAT gets the fus bank last read 3439 For write, the DAT determines which fuses to blow */ 3440#else 3441 uint64_t dat : 64; 3442#endif 3443 } s; 3444 struct cvmx_mio_fus_bnk_datx_s cn50xx; 3445 struct cvmx_mio_fus_bnk_datx_s cn52xx; 3446 struct cvmx_mio_fus_bnk_datx_s cn52xxp1; 3447 struct cvmx_mio_fus_bnk_datx_s cn56xx; 3448 struct cvmx_mio_fus_bnk_datx_s cn56xxp1; 3449 struct cvmx_mio_fus_bnk_datx_s cn58xx; 3450 struct cvmx_mio_fus_bnk_datx_s cn58xxp1; 3451 struct cvmx_mio_fus_bnk_datx_s cn61xx; 3452 struct cvmx_mio_fus_bnk_datx_s cn63xx; 3453 struct cvmx_mio_fus_bnk_datx_s cn63xxp1; 3454 struct cvmx_mio_fus_bnk_datx_s cn66xx; 3455 struct cvmx_mio_fus_bnk_datx_s cn68xx; 3456 struct cvmx_mio_fus_bnk_datx_s cn68xxp1; 3457 struct cvmx_mio_fus_bnk_datx_s cnf71xx; 3458}; 3459typedef union cvmx_mio_fus_bnk_datx cvmx_mio_fus_bnk_datx_t; 3460 3461/** 3462 * cvmx_mio_fus_dat0 3463 */ 3464union cvmx_mio_fus_dat0 { 3465 uint64_t u64; 3466 struct cvmx_mio_fus_dat0_s { 3467#ifdef __BIG_ENDIAN_BITFIELD 3468 uint64_t reserved_32_63 : 32; 3469 uint64_t man_info : 32; /**< Fuse information - manufacturing info [31:0] */ 3470#else 3471 uint64_t man_info : 32; 3472 uint64_t reserved_32_63 : 32; 3473#endif 3474 } s; 3475 struct cvmx_mio_fus_dat0_s cn30xx; 3476 struct cvmx_mio_fus_dat0_s cn31xx; 3477 struct cvmx_mio_fus_dat0_s cn38xx; 3478 struct cvmx_mio_fus_dat0_s cn38xxp2; 3479 struct cvmx_mio_fus_dat0_s cn50xx; 3480 struct cvmx_mio_fus_dat0_s cn52xx; 3481 struct cvmx_mio_fus_dat0_s cn52xxp1; 3482 struct cvmx_mio_fus_dat0_s cn56xx; 3483 struct cvmx_mio_fus_dat0_s cn56xxp1; 3484 struct cvmx_mio_fus_dat0_s cn58xx; 3485 struct cvmx_mio_fus_dat0_s cn58xxp1; 3486 struct cvmx_mio_fus_dat0_s cn61xx; 3487 struct cvmx_mio_fus_dat0_s cn63xx; 3488 struct cvmx_mio_fus_dat0_s cn63xxp1; 3489 struct cvmx_mio_fus_dat0_s cn66xx; 3490 struct cvmx_mio_fus_dat0_s cn68xx; 3491 struct cvmx_mio_fus_dat0_s cn68xxp1; 3492 struct cvmx_mio_fus_dat0_s cnf71xx; 3493}; 3494typedef union cvmx_mio_fus_dat0 cvmx_mio_fus_dat0_t; 3495 3496/** 3497 * cvmx_mio_fus_dat1 3498 */ 3499union cvmx_mio_fus_dat1 { 3500 uint64_t u64; 3501 struct cvmx_mio_fus_dat1_s { 3502#ifdef __BIG_ENDIAN_BITFIELD 3503 uint64_t reserved_32_63 : 32; 3504 uint64_t man_info : 32; /**< Fuse information - manufacturing info [63:32] */ 3505#else 3506 uint64_t man_info : 32; 3507 uint64_t reserved_32_63 : 32; 3508#endif 3509 } s; 3510 struct cvmx_mio_fus_dat1_s cn30xx; 3511 struct cvmx_mio_fus_dat1_s cn31xx; 3512 struct cvmx_mio_fus_dat1_s cn38xx; 3513 struct cvmx_mio_fus_dat1_s cn38xxp2; 3514 struct cvmx_mio_fus_dat1_s cn50xx; 3515 struct cvmx_mio_fus_dat1_s cn52xx; 3516 struct cvmx_mio_fus_dat1_s cn52xxp1; 3517 struct cvmx_mio_fus_dat1_s cn56xx; 3518 struct cvmx_mio_fus_dat1_s cn56xxp1; 3519 struct cvmx_mio_fus_dat1_s cn58xx; 3520 struct cvmx_mio_fus_dat1_s cn58xxp1; 3521 struct cvmx_mio_fus_dat1_s cn61xx; 3522 struct cvmx_mio_fus_dat1_s cn63xx; 3523 struct cvmx_mio_fus_dat1_s cn63xxp1; 3524 struct cvmx_mio_fus_dat1_s cn66xx; 3525 struct cvmx_mio_fus_dat1_s cn68xx; 3526 struct cvmx_mio_fus_dat1_s cn68xxp1; 3527 struct cvmx_mio_fus_dat1_s cnf71xx; 3528}; 3529typedef union cvmx_mio_fus_dat1 cvmx_mio_fus_dat1_t; 3530 3531/** 3532 * cvmx_mio_fus_dat2 3533 * 3534 * Notes: 3535 * CHIP_ID is consumed in several places within Octeon. 3536 * 3537 * * Core COP0 ProcessorIdentification[Revision] 3538 * * Core EJTAG DeviceIdentification[Version] 3539 * * PCI_CFG02[RID] 3540 * * JTAG controller 3541 * 3542 * Note: The JTAG controller gets CHIP_ID[3:0] solely from the laser fuses. 3543 * Modification to the efuses will not change what the JTAG controller reports 3544 * for CHIP_ID. 3545 */ 3546union cvmx_mio_fus_dat2 { 3547 uint64_t u64; 3548 struct cvmx_mio_fus_dat2_s { 3549#ifdef __BIG_ENDIAN_BITFIELD 3550 uint64_t reserved_48_63 : 16; 3551 uint64_t fus118 : 1; /**< Ignore Authentik disable */ 3552 uint64_t rom_info : 10; /**< Fuse information - ROM info */ 3553 uint64_t power_limit : 2; /**< Fuse information - Power limit */ 3554 uint64_t dorm_crypto : 1; /**< Fuse information - See NOCRYPTO */ 3555 uint64_t fus318 : 1; /**< Reserved */ 3556 uint64_t raid_en : 1; /**< Fuse information - RAID enabled */ 3557 uint64_t reserved_30_31 : 2; 3558 uint64_t nokasu : 1; /**< Fuse information - Disable Kasumi */ 3559 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3560 uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3561 uint64_t nocrypto : 1; /**< Fuse information - DORM_CRYPTO and NOCRYPTO 3562 together to select 1 of 4 mutually-exclusive 3563 modes: 3564 3565 DORM_CRYPT=0,NOCRYPTO=0 AES/DES/HASH enabled 3566 DORM_CRYPT=0,NOCRYPTO=1 AES/DES/HASH disable 3567 DORM_CRYPT=1,NOCRYPTO=0 Dormant Encryption enable 3568 DORM_CRYPT=1,NOCRYPTO=1 Authenik mode */ 3569 uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */ 3570 uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */ 3571 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3572 uint64_t reserved_0_15 : 16; 3573#else 3574 uint64_t reserved_0_15 : 16; 3575 uint64_t chip_id : 8; 3576 uint64_t bist_dis : 1; 3577 uint64_t rst_sht : 1; 3578 uint64_t nocrypto : 1; 3579 uint64_t nomul : 1; 3580 uint64_t nodfa_cp2 : 1; 3581 uint64_t nokasu : 1; 3582 uint64_t reserved_30_31 : 2; 3583 uint64_t raid_en : 1; 3584 uint64_t fus318 : 1; 3585 uint64_t dorm_crypto : 1; 3586 uint64_t power_limit : 2; 3587 uint64_t rom_info : 10; 3588 uint64_t fus118 : 1; 3589 uint64_t reserved_48_63 : 16; 3590#endif 3591 } s; 3592 struct cvmx_mio_fus_dat2_cn30xx { 3593#ifdef __BIG_ENDIAN_BITFIELD 3594 uint64_t reserved_29_63 : 35; 3595 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3596 uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3597 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */ 3598 uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */ 3599 uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */ 3600 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3601 uint64_t pll_off : 4; /**< Fuse information - core pll offset 3602 Used to compute the base offset for the core pll. 3603 the offset will be (PLL_OFF ^ 8) 3604 Note, these fuses can only be set from laser fuse */ 3605 uint64_t reserved_1_11 : 11; 3606 uint64_t pp_dis : 1; /**< Fuse information - PP_DISABLES */ 3607#else 3608 uint64_t pp_dis : 1; 3609 uint64_t reserved_1_11 : 11; 3610 uint64_t pll_off : 4; 3611 uint64_t chip_id : 8; 3612 uint64_t bist_dis : 1; 3613 uint64_t rst_sht : 1; 3614 uint64_t nocrypto : 1; 3615 uint64_t nomul : 1; 3616 uint64_t nodfa_cp2 : 1; 3617 uint64_t reserved_29_63 : 35; 3618#endif 3619 } cn30xx; 3620 struct cvmx_mio_fus_dat2_cn31xx { 3621#ifdef __BIG_ENDIAN_BITFIELD 3622 uint64_t reserved_29_63 : 35; 3623 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3624 uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3625 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */ 3626 uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */ 3627 uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */ 3628 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3629 uint64_t pll_off : 4; /**< Fuse information - core pll offset 3630 Used to compute the base offset for the core pll. 3631 the offset will be (PLL_OFF ^ 8) 3632 Note, these fuses can only be set from laser fuse */ 3633 uint64_t reserved_2_11 : 10; 3634 uint64_t pp_dis : 2; /**< Fuse information - PP_DISABLES */ 3635#else 3636 uint64_t pp_dis : 2; 3637 uint64_t reserved_2_11 : 10; 3638 uint64_t pll_off : 4; 3639 uint64_t chip_id : 8; 3640 uint64_t bist_dis : 1; 3641 uint64_t rst_sht : 1; 3642 uint64_t nocrypto : 1; 3643 uint64_t nomul : 1; 3644 uint64_t nodfa_cp2 : 1; 3645 uint64_t reserved_29_63 : 35; 3646#endif 3647 } cn31xx; 3648 struct cvmx_mio_fus_dat2_cn38xx { 3649#ifdef __BIG_ENDIAN_BITFIELD 3650 uint64_t reserved_29_63 : 35; 3651 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) 3652 (PASS2 Only) */ 3653 uint64_t nomul : 1; /**< Fuse information - VMUL disable 3654 (PASS2 Only) */ 3655 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable 3656 (PASS2 Only) */ 3657 uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */ 3658 uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */ 3659 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3660 uint64_t pp_dis : 16; /**< Fuse information - PP_DISABLES */ 3661#else 3662 uint64_t pp_dis : 16; 3663 uint64_t chip_id : 8; 3664 uint64_t bist_dis : 1; 3665 uint64_t rst_sht : 1; 3666 uint64_t nocrypto : 1; 3667 uint64_t nomul : 1; 3668 uint64_t nodfa_cp2 : 1; 3669 uint64_t reserved_29_63 : 35; 3670#endif 3671 } cn38xx; 3672 struct cvmx_mio_fus_dat2_cn38xx cn38xxp2; 3673 struct cvmx_mio_fus_dat2_cn50xx { 3674#ifdef __BIG_ENDIAN_BITFIELD 3675 uint64_t reserved_34_63 : 30; 3676 uint64_t fus318 : 1; /**< Fuse information - a copy of fuse318 */ 3677 uint64_t raid_en : 1; /**< Fuse information - RAID enabled 3678 (5020 does not have RAID co-processor) */ 3679 uint64_t reserved_30_31 : 2; 3680 uint64_t nokasu : 1; /**< Fuse information - Disable Kasumi */ 3681 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) 3682 (5020 does not have DFA co-processor) */ 3683 uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3684 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */ 3685 uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */ 3686 uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */ 3687 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3688 uint64_t reserved_2_15 : 14; 3689 uint64_t pp_dis : 2; /**< Fuse information - PP_DISABLES */ 3690#else 3691 uint64_t pp_dis : 2; 3692 uint64_t reserved_2_15 : 14; 3693 uint64_t chip_id : 8; 3694 uint64_t bist_dis : 1; 3695 uint64_t rst_sht : 1; 3696 uint64_t nocrypto : 1; 3697 uint64_t nomul : 1; 3698 uint64_t nodfa_cp2 : 1; 3699 uint64_t nokasu : 1; 3700 uint64_t reserved_30_31 : 2; 3701 uint64_t raid_en : 1; 3702 uint64_t fus318 : 1; 3703 uint64_t reserved_34_63 : 30; 3704#endif 3705 } cn50xx; 3706 struct cvmx_mio_fus_dat2_cn52xx { 3707#ifdef __BIG_ENDIAN_BITFIELD 3708 uint64_t reserved_34_63 : 30; 3709 uint64_t fus318 : 1; /**< Fuse information - a copy of fuse318 */ 3710 uint64_t raid_en : 1; /**< Fuse information - RAID enabled */ 3711 uint64_t reserved_30_31 : 2; 3712 uint64_t nokasu : 1; /**< Fuse information - Disable Kasumi */ 3713 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3714 uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3715 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */ 3716 uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */ 3717 uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */ 3718 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3719 uint64_t reserved_4_15 : 12; 3720 uint64_t pp_dis : 4; /**< Fuse information - PP_DISABLES */ 3721#else 3722 uint64_t pp_dis : 4; 3723 uint64_t reserved_4_15 : 12; 3724 uint64_t chip_id : 8; 3725 uint64_t bist_dis : 1; 3726 uint64_t rst_sht : 1; 3727 uint64_t nocrypto : 1; 3728 uint64_t nomul : 1; 3729 uint64_t nodfa_cp2 : 1; 3730 uint64_t nokasu : 1; 3731 uint64_t reserved_30_31 : 2; 3732 uint64_t raid_en : 1; 3733 uint64_t fus318 : 1; 3734 uint64_t reserved_34_63 : 30; 3735#endif 3736 } cn52xx; 3737 struct cvmx_mio_fus_dat2_cn52xx cn52xxp1; 3738 struct cvmx_mio_fus_dat2_cn56xx { 3739#ifdef __BIG_ENDIAN_BITFIELD 3740 uint64_t reserved_34_63 : 30; 3741 uint64_t fus318 : 1; /**< Fuse information - a copy of fuse318 */ 3742 uint64_t raid_en : 1; /**< Fuse information - RAID enabled */ 3743 uint64_t reserved_30_31 : 2; 3744 uint64_t nokasu : 1; /**< Fuse information - Disable Kasumi */ 3745 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3746 uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3747 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */ 3748 uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */ 3749 uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */ 3750 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3751 uint64_t reserved_12_15 : 4; 3752 uint64_t pp_dis : 12; /**< Fuse information - PP_DISABLES */ 3753#else 3754 uint64_t pp_dis : 12; 3755 uint64_t reserved_12_15 : 4; 3756 uint64_t chip_id : 8; 3757 uint64_t bist_dis : 1; 3758 uint64_t rst_sht : 1; 3759 uint64_t nocrypto : 1; 3760 uint64_t nomul : 1; 3761 uint64_t nodfa_cp2 : 1; 3762 uint64_t nokasu : 1; 3763 uint64_t reserved_30_31 : 2; 3764 uint64_t raid_en : 1; 3765 uint64_t fus318 : 1; 3766 uint64_t reserved_34_63 : 30; 3767#endif 3768 } cn56xx; 3769 struct cvmx_mio_fus_dat2_cn56xx cn56xxp1; 3770 struct cvmx_mio_fus_dat2_cn58xx { 3771#ifdef __BIG_ENDIAN_BITFIELD 3772 uint64_t reserved_30_63 : 34; 3773 uint64_t nokasu : 1; /**< Fuse information - Disable Kasumi */ 3774 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3775 uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3776 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */ 3777 uint64_t rst_sht : 1; /**< Fuse information - When set, use short reset count */ 3778 uint64_t bist_dis : 1; /**< Fuse information - BIST Disable */ 3779 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3780 uint64_t pp_dis : 16; /**< Fuse information - PP_DISABLES */ 3781#else 3782 uint64_t pp_dis : 16; 3783 uint64_t chip_id : 8; 3784 uint64_t bist_dis : 1; 3785 uint64_t rst_sht : 1; 3786 uint64_t nocrypto : 1; 3787 uint64_t nomul : 1; 3788 uint64_t nodfa_cp2 : 1; 3789 uint64_t nokasu : 1; 3790 uint64_t reserved_30_63 : 34; 3791#endif 3792 } cn58xx; 3793 struct cvmx_mio_fus_dat2_cn58xx cn58xxp1; 3794 struct cvmx_mio_fus_dat2_cn61xx { 3795#ifdef __BIG_ENDIAN_BITFIELD 3796 uint64_t reserved_48_63 : 16; 3797 uint64_t fus118 : 1; /**< Ignore Authentik disable */ 3798 uint64_t rom_info : 10; /**< Fuse information - ROM info */ 3799 uint64_t power_limit : 2; /**< Fuse information - Power limit */ 3800 uint64_t dorm_crypto : 1; /**< Fuse information - See NOCRYPTO */ 3801 uint64_t fus318 : 1; /**< Reserved */ 3802 uint64_t raid_en : 1; /**< Fuse information - RAID enabled */ 3803 uint64_t reserved_29_31 : 3; 3804 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3805 uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3806 uint64_t nocrypto : 1; /**< Fuse information - DORM_CRYPTO and NOCRYPTO 3807 together to select 1 of 4 mutually-exclusive 3808 modes: 3809 3810 DORM_CRYPT=0,NOCRYPTO=0 AES/DES/HASH enabled 3811 DORM_CRYPT=0,NOCRYPTO=1 AES/DES/HASH disable 3812 DORM_CRYPT=1,NOCRYPTO=0 Dormant Encryption enable 3813 DORM_CRYPT=1,NOCRYPTO=1 Authenik mode */ 3814 uint64_t reserved_24_25 : 2; 3815 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3816 uint64_t reserved_4_15 : 12; 3817 uint64_t pp_dis : 4; /**< Fuse information - PP_DISABLES */ 3818#else 3819 uint64_t pp_dis : 4; 3820 uint64_t reserved_4_15 : 12; 3821 uint64_t chip_id : 8; 3822 uint64_t reserved_24_25 : 2; 3823 uint64_t nocrypto : 1; 3824 uint64_t nomul : 1; 3825 uint64_t nodfa_cp2 : 1; 3826 uint64_t reserved_29_31 : 3; 3827 uint64_t raid_en : 1; 3828 uint64_t fus318 : 1; 3829 uint64_t dorm_crypto : 1; 3830 uint64_t power_limit : 2; 3831 uint64_t rom_info : 10; 3832 uint64_t fus118 : 1; 3833 uint64_t reserved_48_63 : 16; 3834#endif 3835 } cn61xx; 3836 struct cvmx_mio_fus_dat2_cn63xx { 3837#ifdef __BIG_ENDIAN_BITFIELD 3838 uint64_t reserved_35_63 : 29; 3839 uint64_t dorm_crypto : 1; /**< Fuse information - Dormant Encryption enable */ 3840 uint64_t fus318 : 1; /**< Reserved */ 3841 uint64_t raid_en : 1; /**< Fuse information - RAID enabled */ 3842 uint64_t reserved_29_31 : 3; 3843 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3844 uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3845 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */ 3846 uint64_t reserved_24_25 : 2; 3847 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3848 uint64_t reserved_6_15 : 10; 3849 uint64_t pp_dis : 6; /**< Fuse information - PP_DISABLES */ 3850#else 3851 uint64_t pp_dis : 6; 3852 uint64_t reserved_6_15 : 10; 3853 uint64_t chip_id : 8; 3854 uint64_t reserved_24_25 : 2; 3855 uint64_t nocrypto : 1; 3856 uint64_t nomul : 1; 3857 uint64_t nodfa_cp2 : 1; 3858 uint64_t reserved_29_31 : 3; 3859 uint64_t raid_en : 1; 3860 uint64_t fus318 : 1; 3861 uint64_t dorm_crypto : 1; 3862 uint64_t reserved_35_63 : 29; 3863#endif 3864 } cn63xx; 3865 struct cvmx_mio_fus_dat2_cn63xx cn63xxp1; 3866 struct cvmx_mio_fus_dat2_cn66xx { 3867#ifdef __BIG_ENDIAN_BITFIELD 3868 uint64_t reserved_48_63 : 16; 3869 uint64_t fus118 : 1; /**< Ignore Authentik disable */ 3870 uint64_t rom_info : 10; /**< Fuse information - ROM info */ 3871 uint64_t power_limit : 2; /**< Fuse information - Power limit */ 3872 uint64_t dorm_crypto : 1; /**< Fuse information - See NOCRYPTO */ 3873 uint64_t fus318 : 1; /**< Reserved */ 3874 uint64_t raid_en : 1; /**< Fuse information - RAID enabled */ 3875 uint64_t reserved_29_31 : 3; 3876 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3877 uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3878 uint64_t nocrypto : 1; /**< Fuse information - DORM_CRYPTO and NOCRYPTO 3879 together to select 1 of 4 mutually-exclusive 3880 modes: 3881 3882 DORM_CRYPT=0,NOCRYPTO=0 AES/DES/HASH enabled 3883 DORM_CRYPT=0,NOCRYPTO=1 AES/DES/HASH disable 3884 DORM_CRYPT=1,NOCRYPTO=0 Dormant Encryption enable 3885 DORM_CRYPT=1,NOCRYPTO=1 Authenik mode */ 3886 uint64_t reserved_24_25 : 2; 3887 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3888 uint64_t reserved_10_15 : 6; 3889 uint64_t pp_dis : 10; /**< Fuse information - PP_DISABLES */ 3890#else 3891 uint64_t pp_dis : 10; 3892 uint64_t reserved_10_15 : 6; 3893 uint64_t chip_id : 8; 3894 uint64_t reserved_24_25 : 2; 3895 uint64_t nocrypto : 1; 3896 uint64_t nomul : 1; 3897 uint64_t nodfa_cp2 : 1; 3898 uint64_t reserved_29_31 : 3; 3899 uint64_t raid_en : 1; 3900 uint64_t fus318 : 1; 3901 uint64_t dorm_crypto : 1; 3902 uint64_t power_limit : 2; 3903 uint64_t rom_info : 10; 3904 uint64_t fus118 : 1; 3905 uint64_t reserved_48_63 : 16; 3906#endif 3907 } cn66xx; 3908 struct cvmx_mio_fus_dat2_cn68xx { 3909#ifdef __BIG_ENDIAN_BITFIELD 3910 uint64_t reserved_37_63 : 27; 3911 uint64_t power_limit : 2; /**< Fuse information - Power limit */ 3912 uint64_t dorm_crypto : 1; /**< Fuse information - Dormant Encryption enable */ 3913 uint64_t fus318 : 1; /**< Reserved */ 3914 uint64_t raid_en : 1; /**< Fuse information - RAID enabled */ 3915 uint64_t reserved_29_31 : 3; 3916 uint64_t nodfa_cp2 : 1; /**< Fuse information - DFA Disable (CP2) */ 3917 uint64_t nomul : 1; /**< Fuse information - VMUL disable */ 3918 uint64_t nocrypto : 1; /**< Fuse information - AES/DES/HASH disable */ 3919 uint64_t reserved_24_25 : 2; 3920 uint64_t chip_id : 8; /**< Fuse information - CHIP_ID */ 3921 uint64_t reserved_0_15 : 16; 3922#else 3923 uint64_t reserved_0_15 : 16; 3924 uint64_t chip_id : 8; 3925 uint64_t reserved_24_25 : 2; 3926 uint64_t nocrypto : 1; 3927 uint64_t nomul : 1; 3928 uint64_t nodfa_cp2 : 1; 3929 uint64_t reserved_29_31 : 3; 3930 uint64_t raid_en : 1; 3931 uint64_t fus318 : 1; 3932 uint64_t dorm_crypto : 1; 3933 uint64_t power_limit : 2; 3934 uint64_t reserved_37_63 : 27; 3935#endif 3936 } cn68xx; 3937 struct cvmx_mio_fus_dat2_cn68xx cn68xxp1; 3938 struct cvmx_mio_fus_dat2_cn61xx cnf71xx; 3939}; 3940typedef union cvmx_mio_fus_dat2 cvmx_mio_fus_dat2_t; 3941 3942/** 3943 * cvmx_mio_fus_dat3 3944 */ 3945union cvmx_mio_fus_dat3 { 3946 uint64_t u64; 3947 struct cvmx_mio_fus_dat3_s { 3948#ifdef __BIG_ENDIAN_BITFIELD 3949 uint64_t reserved_58_63 : 6; 3950 uint64_t pll_ctl : 10; /**< Fuse information - PLL control */ 3951 uint64_t dfa_info_dte : 3; /**< Fuse information - DFA information (DTE) */ 3952 uint64_t dfa_info_clm : 4; /**< Fuse information - DFA information (Cluster mask) */ 3953 uint64_t reserved_40_40 : 1; 3954 uint64_t ema : 2; /**< Fuse information - EMA */ 3955 uint64_t efus_lck_rsv : 1; /**< Fuse information - efuse lockdown */ 3956 uint64_t efus_lck_man : 1; /**< Fuse information - efuse lockdown */ 3957 uint64_t pll_half_dis : 1; /**< Fuse information - RCLK PLL control */ 3958 uint64_t l2c_crip : 3; /**< Fuse information - L2C Cripple (1/8, 1/4, 1/2) */ 3959 uint64_t pll_div4 : 1; /**< Fuse information - PLL DIV4 mode 3960 (laser fuse only) */ 3961 uint64_t reserved_29_30 : 2; 3962 uint64_t bar2_en : 1; /**< Fuse information - BAR2 Present (when blown '1') */ 3963 uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown */ 3964 uint64_t efus_ign : 1; /**< Fuse information - efuse ignore */ 3965 uint64_t nozip : 1; /**< Fuse information - ZIP disable */ 3966 uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE) */ 3967 uint64_t icache : 24; /**< Fuse information - ICACHE Hard Repair Data */ 3968#else 3969 uint64_t icache : 24; 3970 uint64_t nodfa_dte : 1; 3971 uint64_t nozip : 1; 3972 uint64_t efus_ign : 1; 3973 uint64_t efus_lck : 1; 3974 uint64_t bar2_en : 1; 3975 uint64_t reserved_29_30 : 2; 3976 uint64_t pll_div4 : 1; 3977 uint64_t l2c_crip : 3; 3978 uint64_t pll_half_dis : 1; 3979 uint64_t efus_lck_man : 1; 3980 uint64_t efus_lck_rsv : 1; 3981 uint64_t ema : 2; 3982 uint64_t reserved_40_40 : 1; 3983 uint64_t dfa_info_clm : 4; 3984 uint64_t dfa_info_dte : 3; 3985 uint64_t pll_ctl : 10; 3986 uint64_t reserved_58_63 : 6; 3987#endif 3988 } s; 3989 struct cvmx_mio_fus_dat3_cn30xx { 3990#ifdef __BIG_ENDIAN_BITFIELD 3991 uint64_t reserved_32_63 : 32; 3992 uint64_t pll_div4 : 1; /**< Fuse information - PLL DIV4 mode 3993 (laser fuse only) */ 3994 uint64_t reserved_29_30 : 2; 3995 uint64_t bar2_en : 1; /**< Fuse information - BAR2 Enable (when blown '1') */ 3996 uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown */ 3997 uint64_t efus_ign : 1; /**< Fuse information - efuse ignore 3998 This bit only has side effects when blown in 3999 the laser fuses. It is ignore if only set in 4000 efuse store. */ 4001 uint64_t nozip : 1; /**< Fuse information - ZIP disable */ 4002 uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE) */ 4003 uint64_t icache : 24; /**< Fuse information - ICACHE Hard Repair Data */ 4004#else 4005 uint64_t icache : 24; 4006 uint64_t nodfa_dte : 1; 4007 uint64_t nozip : 1; 4008 uint64_t efus_ign : 1; 4009 uint64_t efus_lck : 1; 4010 uint64_t bar2_en : 1; 4011 uint64_t reserved_29_30 : 2; 4012 uint64_t pll_div4 : 1; 4013 uint64_t reserved_32_63 : 32; 4014#endif 4015 } cn30xx; 4016 struct cvmx_mio_fus_dat3_cn31xx { 4017#ifdef __BIG_ENDIAN_BITFIELD 4018 uint64_t reserved_32_63 : 32; 4019 uint64_t pll_div4 : 1; /**< Fuse information - PLL DIV4 mode 4020 (laser fuse only) */ 4021 uint64_t zip_crip : 2; /**< Fuse information - Zip Cripple 4022 (O2P Only) */ 4023 uint64_t bar2_en : 1; /**< Fuse information - BAR2 Enable (when blown '1') */ 4024 uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown */ 4025 uint64_t efus_ign : 1; /**< Fuse information - efuse ignore 4026 This bit only has side effects when blown in 4027 the laser fuses. It is ignore if only set in 4028 efuse store. */ 4029 uint64_t nozip : 1; /**< Fuse information - ZIP disable */ 4030 uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE) */ 4031 uint64_t icache : 24; /**< Fuse information - ICACHE Hard Repair Data */ 4032#else 4033 uint64_t icache : 24; 4034 uint64_t nodfa_dte : 1; 4035 uint64_t nozip : 1; 4036 uint64_t efus_ign : 1; 4037 uint64_t efus_lck : 1; 4038 uint64_t bar2_en : 1; 4039 uint64_t zip_crip : 2; 4040 uint64_t pll_div4 : 1; 4041 uint64_t reserved_32_63 : 32; 4042#endif 4043 } cn31xx; 4044 struct cvmx_mio_fus_dat3_cn38xx { 4045#ifdef __BIG_ENDIAN_BITFIELD 4046 uint64_t reserved_31_63 : 33; 4047 uint64_t zip_crip : 2; /**< Fuse information - Zip Cripple 4048 (PASS3 Only) */ 4049 uint64_t bar2_en : 1; /**< Fuse information - BAR2 Enable (when blown '1') 4050 (PASS2 Only) */ 4051 uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown 4052 (PASS2 Only) */ 4053 uint64_t efus_ign : 1; /**< Fuse information - efuse ignore 4054 This bit only has side effects when blown in 4055 the laser fuses. It is ignore if only set in 4056 efuse store. 4057 (PASS2 Only) */ 4058 uint64_t nozip : 1; /**< Fuse information - ZIP disable 4059 (PASS2 Only) */ 4060 uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE) 4061 (PASS2 Only) */ 4062 uint64_t icache : 24; /**< Fuse information - ICACHE Hard Repair Data */ 4063#else 4064 uint64_t icache : 24; 4065 uint64_t nodfa_dte : 1; 4066 uint64_t nozip : 1; 4067 uint64_t efus_ign : 1; 4068 uint64_t efus_lck : 1; 4069 uint64_t bar2_en : 1; 4070 uint64_t zip_crip : 2; 4071 uint64_t reserved_31_63 : 33; 4072#endif 4073 } cn38xx; 4074 struct cvmx_mio_fus_dat3_cn38xxp2 { 4075#ifdef __BIG_ENDIAN_BITFIELD 4076 uint64_t reserved_29_63 : 35; 4077 uint64_t bar2_en : 1; /**< Fuse information - BAR2 Enable (when blown '1') 4078 (PASS2 Only) */ 4079 uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown 4080 (PASS2 Only) */ 4081 uint64_t efus_ign : 1; /**< Fuse information - efuse ignore 4082 This bit only has side effects when blown in 4083 the laser fuses. It is ignore if only set in 4084 efuse store. 4085 (PASS2 Only) */ 4086 uint64_t nozip : 1; /**< Fuse information - ZIP disable 4087 (PASS2 Only) */ 4088 uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE) 4089 (PASS2 Only) */ 4090 uint64_t icache : 24; /**< Fuse information - ICACHE Hard Repair Data */ 4091#else 4092 uint64_t icache : 24; 4093 uint64_t nodfa_dte : 1; 4094 uint64_t nozip : 1; 4095 uint64_t efus_ign : 1; 4096 uint64_t efus_lck : 1; 4097 uint64_t bar2_en : 1; 4098 uint64_t reserved_29_63 : 35; 4099#endif 4100 } cn38xxp2; 4101 struct cvmx_mio_fus_dat3_cn38xx cn50xx; 4102 struct cvmx_mio_fus_dat3_cn38xx cn52xx; 4103 struct cvmx_mio_fus_dat3_cn38xx cn52xxp1; 4104 struct cvmx_mio_fus_dat3_cn38xx cn56xx; 4105 struct cvmx_mio_fus_dat3_cn38xx cn56xxp1; 4106 struct cvmx_mio_fus_dat3_cn38xx cn58xx; 4107 struct cvmx_mio_fus_dat3_cn38xx cn58xxp1; 4108 struct cvmx_mio_fus_dat3_cn61xx { 4109#ifdef __BIG_ENDIAN_BITFIELD 4110 uint64_t reserved_58_63 : 6; 4111 uint64_t pll_ctl : 10; /**< Fuse information - PLL control */ 4112 uint64_t dfa_info_dte : 3; /**< Fuse information - DFA information (DTE) */ 4113 uint64_t dfa_info_clm : 4; /**< Fuse information - DFA information (Cluster mask) */ 4114 uint64_t reserved_40_40 : 1; 4115 uint64_t ema : 2; /**< Fuse information - EMA */ 4116 uint64_t efus_lck_rsv : 1; /**< Fuse information - efuse lockdown */ 4117 uint64_t efus_lck_man : 1; /**< Fuse information - efuse lockdown */ 4118 uint64_t pll_half_dis : 1; /**< Fuse information - RCLK PLL control */ 4119 uint64_t l2c_crip : 3; /**< Fuse information - L2C Cripple (1/8, 1/4, 1/2) */ 4120 uint64_t reserved_31_31 : 1; 4121 uint64_t zip_info : 2; /**< Fuse information - Zip information */ 4122 uint64_t bar2_en : 1; /**< Fuse information - BAR2 Present (when blown '1') */ 4123 uint64_t efus_lck : 1; /**< Fuse information - efuse lockdown */ 4124 uint64_t efus_ign : 1; /**< Fuse information - efuse ignore */ 4125 uint64_t nozip : 1; /**< Fuse information - ZIP disable */ 4126 uint64_t nodfa_dte : 1; /**< Fuse information - DFA Disable (DTE) */ 4127 uint64_t reserved_0_23 : 24; 4128#else 4129 uint64_t reserved_0_23 : 24; 4130 uint64_t nodfa_dte : 1; 4131 uint64_t nozip : 1; 4132 uint64_t efus_ign : 1; 4133 uint64_t efus_lck : 1; 4134 uint64_t bar2_en : 1; 4135 uint64_t zip_info : 2; 4136 uint64_t reserved_31_31 : 1; 4137 uint64_t l2c_crip : 3; 4138 uint64_t pll_half_dis : 1; 4139 uint64_t efus_lck_man : 1; 4140 uint64_t efus_lck_rsv : 1; 4141 uint64_t ema : 2; 4142 uint64_t reserved_40_40 : 1; 4143 uint64_t dfa_info_clm : 4; 4144 uint64_t dfa_info_dte : 3; 4145 uint64_t pll_ctl : 10; 4146 uint64_t reserved_58_63 : 6; 4147#endif 4148 } cn61xx; 4149 struct cvmx_mio_fus_dat3_cn61xx cn63xx; 4150 struct cvmx_mio_fus_dat3_cn61xx cn63xxp1; 4151 struct cvmx_mio_fus_dat3_cn61xx cn66xx; 4152 struct cvmx_mio_fus_dat3_cn61xx cn68xx; 4153 struct cvmx_mio_fus_dat3_cn61xx cn68xxp1; 4154 struct cvmx_mio_fus_dat3_cn61xx cnf71xx; 4155}; 4156typedef union cvmx_mio_fus_dat3 cvmx_mio_fus_dat3_t; 4157 4158/** 4159 * cvmx_mio_fus_ema 4160 * 4161 * DON'T PUT IN HRM* 4162 * 4163 */ 4164union cvmx_mio_fus_ema { 4165 uint64_t u64; 4166 struct cvmx_mio_fus_ema_s { 4167#ifdef __BIG_ENDIAN_BITFIELD 4168 uint64_t reserved_7_63 : 57; 4169 uint64_t eff_ema : 3; /**< Reserved */ 4170 uint64_t reserved_3_3 : 1; 4171 uint64_t ema : 3; /**< Reserved */ 4172#else 4173 uint64_t ema : 3; 4174 uint64_t reserved_3_3 : 1; 4175 uint64_t eff_ema : 3; 4176 uint64_t reserved_7_63 : 57; 4177#endif 4178 } s; 4179 struct cvmx_mio_fus_ema_s cn50xx; 4180 struct cvmx_mio_fus_ema_s cn52xx; 4181 struct cvmx_mio_fus_ema_s cn52xxp1; 4182 struct cvmx_mio_fus_ema_s cn56xx; 4183 struct cvmx_mio_fus_ema_s cn56xxp1; 4184 struct cvmx_mio_fus_ema_cn58xx { 4185#ifdef __BIG_ENDIAN_BITFIELD 4186 uint64_t reserved_2_63 : 62; 4187 uint64_t ema : 2; /**< EMA Settings */ 4188#else 4189 uint64_t ema : 2; 4190 uint64_t reserved_2_63 : 62; 4191#endif 4192 } cn58xx; 4193 struct cvmx_mio_fus_ema_cn58xx cn58xxp1; 4194 struct cvmx_mio_fus_ema_s cn61xx; 4195 struct cvmx_mio_fus_ema_s cn63xx; 4196 struct cvmx_mio_fus_ema_s cn63xxp1; 4197 struct cvmx_mio_fus_ema_s cn66xx; 4198 struct cvmx_mio_fus_ema_s cn68xx; 4199 struct cvmx_mio_fus_ema_s cn68xxp1; 4200 struct cvmx_mio_fus_ema_s cnf71xx; 4201}; 4202typedef union cvmx_mio_fus_ema cvmx_mio_fus_ema_t; 4203 4204/** 4205 * cvmx_mio_fus_pdf 4206 */ 4207union cvmx_mio_fus_pdf { 4208 uint64_t u64; 4209 struct cvmx_mio_fus_pdf_s { 4210#ifdef __BIG_ENDIAN_BITFIELD 4211 uint64_t pdf : 64; /**< Fuse information - Product Definition Field */ 4212#else 4213 uint64_t pdf : 64; 4214#endif 4215 } s; 4216 struct cvmx_mio_fus_pdf_s cn50xx; 4217 struct cvmx_mio_fus_pdf_s cn52xx; 4218 struct cvmx_mio_fus_pdf_s cn52xxp1; 4219 struct cvmx_mio_fus_pdf_s cn56xx; 4220 struct cvmx_mio_fus_pdf_s cn56xxp1; 4221 struct cvmx_mio_fus_pdf_s cn58xx; 4222 struct cvmx_mio_fus_pdf_s cn61xx; 4223 struct cvmx_mio_fus_pdf_s cn63xx; 4224 struct cvmx_mio_fus_pdf_s cn63xxp1; 4225 struct cvmx_mio_fus_pdf_s cn66xx; 4226 struct cvmx_mio_fus_pdf_s cn68xx; 4227 struct cvmx_mio_fus_pdf_s cn68xxp1; 4228 struct cvmx_mio_fus_pdf_s cnf71xx; 4229}; 4230typedef union cvmx_mio_fus_pdf cvmx_mio_fus_pdf_t; 4231 4232/** 4233 * cvmx_mio_fus_pll 4234 * 4235 * Notes: 4236 * The core clkout postscaler should be placed in reset at least 10 ref clocks prior to changing 4237 * the core clkout select. The core clkout postscaler should remain under reset for at least 10 4238 * ref clocks after the core clkout select changes. 4239 * 4240 * The pnr clkout postscaler should be placed in reset at least 10 ref clocks prior to changing 4241 * the pnr clkout select. The pnr clkout postscaler should remain under reset for at least 10 4242 * ref clocks after the pnr clkout select changes. 4243 */ 4244union cvmx_mio_fus_pll { 4245 uint64_t u64; 4246 struct cvmx_mio_fus_pll_s { 4247#ifdef __BIG_ENDIAN_BITFIELD 4248 uint64_t reserved_48_63 : 16; 4249 uint64_t rclk_align_r : 8; /**< RCLK right alignment settings */ 4250 uint64_t rclk_align_l : 8; /**< RCLK left alignment settings */ 4251 uint64_t reserved_8_31 : 24; 4252 uint64_t c_cout_rst : 1; /**< Core clkout postscaler reset */ 4253 uint64_t c_cout_sel : 2; /**< Core clkout select 4254 0=RCLK,1=PS output,2=PLL output,3=undivided RCLK | $PR 4255 (***Pass 1.x: 3=GND) */ 4256 uint64_t pnr_cout_rst : 1; /**< PNR clkout postscaler reset */ 4257 uint64_t pnr_cout_sel : 2; /**< PNR clkout select 4258 0=SCLK,1=PS output,2=PLL output,3=undivided RCLK | $PR 4259 (***Pass 1.x: 3=GND) */ 4260 uint64_t rfslip : 1; /**< Reserved */ 4261 uint64_t fbslip : 1; /**< Reserved */ 4262#else 4263 uint64_t fbslip : 1; 4264 uint64_t rfslip : 1; 4265 uint64_t pnr_cout_sel : 2; 4266 uint64_t pnr_cout_rst : 1; 4267 uint64_t c_cout_sel : 2; 4268 uint64_t c_cout_rst : 1; 4269 uint64_t reserved_8_31 : 24; 4270 uint64_t rclk_align_l : 8; 4271 uint64_t rclk_align_r : 8; 4272 uint64_t reserved_48_63 : 16; 4273#endif 4274 } s; 4275 struct cvmx_mio_fus_pll_cn50xx { 4276#ifdef __BIG_ENDIAN_BITFIELD 4277 uint64_t reserved_2_63 : 62; 4278 uint64_t rfslip : 1; /**< PLL reference clock slip */ 4279 uint64_t fbslip : 1; /**< PLL feedback clock slip */ 4280#else 4281 uint64_t fbslip : 1; 4282 uint64_t rfslip : 1; 4283 uint64_t reserved_2_63 : 62; 4284#endif 4285 } cn50xx; 4286 struct cvmx_mio_fus_pll_cn50xx cn52xx; 4287 struct cvmx_mio_fus_pll_cn50xx cn52xxp1; 4288 struct cvmx_mio_fus_pll_cn50xx cn56xx; 4289 struct cvmx_mio_fus_pll_cn50xx cn56xxp1; 4290 struct cvmx_mio_fus_pll_cn50xx cn58xx; 4291 struct cvmx_mio_fus_pll_cn50xx cn58xxp1; 4292 struct cvmx_mio_fus_pll_cn61xx { 4293#ifdef __BIG_ENDIAN_BITFIELD 4294 uint64_t reserved_8_63 : 56; 4295 uint64_t c_cout_rst : 1; /**< Core clkout postscaler reset */ 4296 uint64_t c_cout_sel : 2; /**< Core clkout select 4297 0=RCLK,1=PS output,2=PLL output,3=undivided RCLK | $PR 4298 (***Pass 1.x: 3=GND) */ 4299 uint64_t pnr_cout_rst : 1; /**< PNR clkout postscaler reset */ 4300 uint64_t pnr_cout_sel : 2; /**< PNR clkout select 4301 0=SCLK,1=PS output,2=PLL output,3=undivided RCLK | $PR 4302 (***Pass 1.x: 3=GND) */ 4303 uint64_t rfslip : 1; /**< Reserved */ 4304 uint64_t fbslip : 1; /**< Reserved */ 4305#else 4306 uint64_t fbslip : 1; 4307 uint64_t rfslip : 1; 4308 uint64_t pnr_cout_sel : 2; 4309 uint64_t pnr_cout_rst : 1; 4310 uint64_t c_cout_sel : 2; 4311 uint64_t c_cout_rst : 1; 4312 uint64_t reserved_8_63 : 56; 4313#endif 4314 } cn61xx; 4315 struct cvmx_mio_fus_pll_cn61xx cn63xx; 4316 struct cvmx_mio_fus_pll_cn61xx cn63xxp1; 4317 struct cvmx_mio_fus_pll_cn61xx cn66xx; 4318 struct cvmx_mio_fus_pll_s cn68xx; 4319 struct cvmx_mio_fus_pll_s cn68xxp1; 4320 struct cvmx_mio_fus_pll_cn61xx cnf71xx; 4321}; 4322typedef union cvmx_mio_fus_pll cvmx_mio_fus_pll_t; 4323 4324/** 4325 * cvmx_mio_fus_prog 4326 * 4327 * DON'T PUT IN HRM* 4328 * 4329 * 4330 * Notes: 4331 * This CSR is not present in the HRM. 4332 * 4333 * To write a bank of fuses, SW must set MIO_FUS_WADR[ADDR] to the bank to be 4334 * programmed and then set each bit within MIO_FUS_BNK_DATX to indicate which 4335 * fuses to blow. Once ADDR, and DAT are setup, SW can write to 4336 * MIO_FUS_PROG[PROG] to start the bank write and poll on PROG. Once PROG is 4337 * clear, the bank write is complete. 4338 * 4339 * A soft blow is still subject to lockdown fuses. After a soft/warm reset, the 4340 * chip will behave as though the fuses were actually blown. A cold reset restores 4341 * the actual fuse valuse. 4342 */ 4343union cvmx_mio_fus_prog { 4344 uint64_t u64; 4345 struct cvmx_mio_fus_prog_s { 4346#ifdef __BIG_ENDIAN_BITFIELD 4347 uint64_t reserved_2_63 : 62; 4348 uint64_t soft : 1; /**< When set with PROG, causes only the local storeage 4349 to change. Will not really blow any fuses. HW 4350 will clear when the program operation is complete */ 4351 uint64_t prog : 1; /**< Blow the fuse bank 4352 SW will set PROG, and then the HW will clear 4353 when the program operation is complete */ 4354#else 4355 uint64_t prog : 1; 4356 uint64_t soft : 1; 4357 uint64_t reserved_2_63 : 62; 4358#endif 4359 } s; 4360 struct cvmx_mio_fus_prog_cn30xx { 4361#ifdef __BIG_ENDIAN_BITFIELD 4362 uint64_t reserved_1_63 : 63; 4363 uint64_t prog : 1; /**< Blow the fuse 4364 SW will set PROG, hold it for 10us, then clear it */ 4365#else 4366 uint64_t prog : 1; 4367 uint64_t reserved_1_63 : 63; 4368#endif 4369 } cn30xx; 4370 struct cvmx_mio_fus_prog_cn30xx cn31xx; 4371 struct cvmx_mio_fus_prog_cn30xx cn38xx; 4372 struct cvmx_mio_fus_prog_cn30xx cn38xxp2; 4373 struct cvmx_mio_fus_prog_cn30xx cn50xx; 4374 struct cvmx_mio_fus_prog_cn30xx cn52xx; 4375 struct cvmx_mio_fus_prog_cn30xx cn52xxp1; 4376 struct cvmx_mio_fus_prog_cn30xx cn56xx; 4377 struct cvmx_mio_fus_prog_cn30xx cn56xxp1; 4378 struct cvmx_mio_fus_prog_cn30xx cn58xx; 4379 struct cvmx_mio_fus_prog_cn30xx cn58xxp1; 4380 struct cvmx_mio_fus_prog_s cn61xx; 4381 struct cvmx_mio_fus_prog_s cn63xx; 4382 struct cvmx_mio_fus_prog_s cn63xxp1; 4383 struct cvmx_mio_fus_prog_s cn66xx; 4384 struct cvmx_mio_fus_prog_s cn68xx; 4385 struct cvmx_mio_fus_prog_s cn68xxp1; 4386 struct cvmx_mio_fus_prog_s cnf71xx; 4387}; 4388typedef union cvmx_mio_fus_prog cvmx_mio_fus_prog_t; 4389 4390/** 4391 * cvmx_mio_fus_prog_times 4392 * 4393 * DON'T PUT IN HRM* 4394 * 4395 * 4396 * Notes: 4397 * This CSR is not present in the HRM. 4398 * 4399 * All values must be > 0 for correct electrical operation. 4400 * 4401 * IFB fuses are 0..1791 4402 * L6G fuses are 1792 to 2047 4403 * 4404 * The reset values are for IFB fuses for ref_clk of 100MHZ 4405 */ 4406union cvmx_mio_fus_prog_times { 4407 uint64_t u64; 4408 struct cvmx_mio_fus_prog_times_s { 4409#ifdef __BIG_ENDIAN_BITFIELD 4410 uint64_t reserved_35_63 : 29; 4411 uint64_t vgate_pin : 1; /**< efuse vgate pin (L6G) */ 4412 uint64_t fsrc_pin : 1; /**< efuse fsource pin (L6G) */ 4413 uint64_t prog_pin : 1; /**< efuse program pin (IFB) */ 4414 uint64_t reserved_6_31 : 26; 4415 uint64_t setup : 6; /**< efuse timing param 4416 4417 SETUP = (tWRS/refclk period)-1 4418 4419 For IFB: tWRS = 20ns 4420 For L6G: tWRS = 20ns */ 4421#else 4422 uint64_t setup : 6; 4423 uint64_t reserved_6_31 : 26; 4424 uint64_t prog_pin : 1; 4425 uint64_t fsrc_pin : 1; 4426 uint64_t vgate_pin : 1; 4427 uint64_t reserved_35_63 : 29; 4428#endif 4429 } s; 4430 struct cvmx_mio_fus_prog_times_cn50xx { 4431#ifdef __BIG_ENDIAN_BITFIELD 4432 uint64_t reserved_33_63 : 31; 4433 uint64_t prog_pin : 1; /**< efuse program pin */ 4434 uint64_t out : 8; /**< efuse timing param (ref_clks to delay 10ns) */ 4435 uint64_t sclk_lo : 4; /**< efuse timing param (ref_clks to delay 5ns) */ 4436 uint64_t sclk_hi : 12; /**< efuse timing param (ref_clks to delay 1000ns) */ 4437 uint64_t setup : 8; /**< efuse timing param (ref_clks to delay 10ns) */ 4438#else 4439 uint64_t setup : 8; 4440 uint64_t sclk_hi : 12; 4441 uint64_t sclk_lo : 4; 4442 uint64_t out : 8; 4443 uint64_t prog_pin : 1; 4444 uint64_t reserved_33_63 : 31; 4445#endif 4446 } cn50xx; 4447 struct cvmx_mio_fus_prog_times_cn50xx cn52xx; 4448 struct cvmx_mio_fus_prog_times_cn50xx cn52xxp1; 4449 struct cvmx_mio_fus_prog_times_cn50xx cn56xx; 4450 struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1; 4451 struct cvmx_mio_fus_prog_times_cn50xx cn58xx; 4452 struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1; 4453 struct cvmx_mio_fus_prog_times_cn61xx { 4454#ifdef __BIG_ENDIAN_BITFIELD 4455 uint64_t reserved_35_63 : 29; 4456 uint64_t vgate_pin : 1; /**< efuse vgate pin (L6G) */ 4457 uint64_t fsrc_pin : 1; /**< efuse fsource pin (L6G) */ 4458 uint64_t prog_pin : 1; /**< efuse program pin (IFB) */ 4459 uint64_t out : 7; /**< efuse timing param 4460 4461 OUT = (tOUT/refclk period)-1 4462 4463 For IFB: tOUT = 20ns 4464 For L6G: tOUT = 20ns */ 4465 uint64_t sclk_lo : 4; /**< efuse timing param 4466 4467 SCLK_LO=(tSLO/refclk period)-1 4468 4469 For IFB: tSLO = 20ns 4470 For L6G: tSLO = 20ns */ 4471 uint64_t sclk_hi : 15; /**< efuse timing param 4472 ***NOTE: Pass 1.x reset value is 20000 4473 4474 SCLK_HI=(tSHI/refclk period)-1 4475 4476 For IFB: tSHI = 200us 4477 For L6G: tSHI = 25us */ 4478 uint64_t setup : 6; /**< efuse timing param 4479 4480 SETUP = (tWRS/refclk period)-1 4481 4482 For IFB: tWRS = 20ns 4483 For L6G: tWRS = 20ns */ 4484#else 4485 uint64_t setup : 6; 4486 uint64_t sclk_hi : 15; 4487 uint64_t sclk_lo : 4; 4488 uint64_t out : 7; 4489 uint64_t prog_pin : 1; 4490 uint64_t fsrc_pin : 1; 4491 uint64_t vgate_pin : 1; 4492 uint64_t reserved_35_63 : 29; 4493#endif 4494 } cn61xx; 4495 struct cvmx_mio_fus_prog_times_cn61xx cn63xx; 4496 struct cvmx_mio_fus_prog_times_cn61xx cn63xxp1; 4497 struct cvmx_mio_fus_prog_times_cn61xx cn66xx; 4498 struct cvmx_mio_fus_prog_times_cn61xx cn68xx; 4499 struct cvmx_mio_fus_prog_times_cn61xx cn68xxp1; 4500 struct cvmx_mio_fus_prog_times_cn61xx cnf71xx; 4501}; 4502typedef union cvmx_mio_fus_prog_times cvmx_mio_fus_prog_times_t; 4503 4504/** 4505 * cvmx_mio_fus_rcmd 4506 * 4507 * Notes: 4508 * To read an efuse, SW writes MIO_FUS_RCMD[ADDR,PEND] with the byte address of 4509 * the fuse in question, then SW can poll MIO_FUS_RCMD[PEND]. When PEND is 4510 * clear, then MIO_FUS_RCMD[DAT] is valid. In addition, if the efuse read went 4511 * to the efuse banks (eg. ((ADDR/16) not [0,1,7]) || EFUSE) SW can read 4512 * MIO_FUS_BNK_DATX which contains all 128 fuses in the bank associated in 4513 * ADDR. 4514 */ 4515union cvmx_mio_fus_rcmd { 4516 uint64_t u64; 4517 struct cvmx_mio_fus_rcmd_s { 4518#ifdef __BIG_ENDIAN_BITFIELD 4519 uint64_t reserved_24_63 : 40; 4520 uint64_t dat : 8; /**< 8bits of fuse data */ 4521 uint64_t reserved_13_15 : 3; 4522 uint64_t pend : 1; /**< SW sets this bit on a write to start FUSE read 4523 operation. HW clears when read is complete and 4524 the DAT is valid */ 4525 uint64_t reserved_9_11 : 3; 4526 uint64_t efuse : 1; /**< When set, return data from the efuse storage 4527 rather than the local storage */ 4528 uint64_t addr : 8; /**< The byte address of the fuse to read */ 4529#else 4530 uint64_t addr : 8; 4531 uint64_t efuse : 1; 4532 uint64_t reserved_9_11 : 3; 4533 uint64_t pend : 1; 4534 uint64_t reserved_13_15 : 3; 4535 uint64_t dat : 8; 4536 uint64_t reserved_24_63 : 40; 4537#endif 4538 } s; 4539 struct cvmx_mio_fus_rcmd_cn30xx { 4540#ifdef __BIG_ENDIAN_BITFIELD 4541 uint64_t reserved_24_63 : 40; 4542 uint64_t dat : 8; /**< 8bits of fuse data */ 4543 uint64_t reserved_13_15 : 3; 4544 uint64_t pend : 1; /**< SW sets this bit on a write to start FUSE read 4545 operation. HW clears when read is complete and 4546 the DAT is valid */ 4547 uint64_t reserved_9_11 : 3; 4548 uint64_t efuse : 1; /**< When set, return data from the efuse storage 4549 rather than the local storage for the 320 HW fuses */ 4550 uint64_t reserved_7_7 : 1; 4551 uint64_t addr : 7; /**< The byte address of the fuse to read */ 4552#else 4553 uint64_t addr : 7; 4554 uint64_t reserved_7_7 : 1; 4555 uint64_t efuse : 1; 4556 uint64_t reserved_9_11 : 3; 4557 uint64_t pend : 1; 4558 uint64_t reserved_13_15 : 3; 4559 uint64_t dat : 8; 4560 uint64_t reserved_24_63 : 40; 4561#endif 4562 } cn30xx; 4563 struct cvmx_mio_fus_rcmd_cn30xx cn31xx; 4564 struct cvmx_mio_fus_rcmd_cn30xx cn38xx; 4565 struct cvmx_mio_fus_rcmd_cn30xx cn38xxp2; 4566 struct cvmx_mio_fus_rcmd_cn30xx cn50xx; 4567 struct cvmx_mio_fus_rcmd_s cn52xx; 4568 struct cvmx_mio_fus_rcmd_s cn52xxp1; 4569 struct cvmx_mio_fus_rcmd_s cn56xx; 4570 struct cvmx_mio_fus_rcmd_s cn56xxp1; 4571 struct cvmx_mio_fus_rcmd_cn30xx cn58xx; 4572 struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1; 4573 struct cvmx_mio_fus_rcmd_s cn61xx; 4574 struct cvmx_mio_fus_rcmd_s cn63xx; 4575 struct cvmx_mio_fus_rcmd_s cn63xxp1; 4576 struct cvmx_mio_fus_rcmd_s cn66xx; 4577 struct cvmx_mio_fus_rcmd_s cn68xx; 4578 struct cvmx_mio_fus_rcmd_s cn68xxp1; 4579 struct cvmx_mio_fus_rcmd_s cnf71xx; 4580}; 4581typedef union cvmx_mio_fus_rcmd cvmx_mio_fus_rcmd_t; 4582 4583/** 4584 * cvmx_mio_fus_read_times 4585 * 4586 * Notes: 4587 * IFB fuses are 0..1791 4588 * L6G fuses are 1792 to 2047 4589 * 4590 * The reset values are for IFB fuses for refclk up to 100MHZ when core PLL is enagaged 4591 * 4592 * If any of the formulas above result in a value less than zero, the corresponding 4593 * timing parameter should be set to zero. 4594 * 4595 * Prior to issuing a read to the fuse banks (via. MIO_FUS_RCMD), this register 4596 * should be written with the timing parameters which correspond to the fuse bank type (IFB vs L6G) 4597 * that will be read. 4598 * 4599 * This register should not be written while MIO_FUS_RCMD[PEND]=1. 4600 */ 4601union cvmx_mio_fus_read_times { 4602 uint64_t u64; 4603 struct cvmx_mio_fus_read_times_s { 4604#ifdef __BIG_ENDIAN_BITFIELD 4605 uint64_t reserved_26_63 : 38; 4606 uint64_t sch : 4; /**< Hold CS for (SCH+1) refclks after FSET desserts 4607 4608 SCH = (tSCH/refclk period)-1 4609 4610 For IFB: tSCH = 160ns 4611 For L6G: tSCH = 10ns */ 4612 uint64_t fsh : 4; /**< Hold FSET for (FSH+1) refclks after PRCHG deasserts 4613 4614 FSH = (tFSH/refclk period)-1 4615 4616 For IFB: tFSH = 160ns 4617 For L6G: tFSH = 10ns */ 4618 uint64_t prh : 4; /**< Assert PRCHG (PRH+1) refclks after SIGDEV deasserts 4619 4620 PRH = (tPRH/refclk period)-1 4621 4622 For IFB: tPRH = 70ns 4623 For L6G: tPRH = 10ns */ 4624 uint64_t sdh : 4; /**< Hold SIGDEV for (SDH+1) refclks after FSET asserts 4625 4626 SDH = (tSDH/refclk period)-1 4627 4628 For IFB: tPRH = 10ns 4629 For L6G: tPRH = 10ns */ 4630 uint64_t setup : 10; /**< Assert CS for (SETUP+1) refclks before asserting 4631 SIGDEV, FSET, or PRCHG 4632 4633 SETUP=(tRDS/refclk period)-1 4634 4635 For IFB: tRDS = 10000ns 4636 For L6G: tRDS = max(tSCS,tSDS,tPRS) 4637 where tSCS = 10ns 4638 tSDS = 10ns 4639 tPRS = 10ns */ 4640#else 4641 uint64_t setup : 10; 4642 uint64_t sdh : 4; 4643 uint64_t prh : 4; 4644 uint64_t fsh : 4; 4645 uint64_t sch : 4; 4646 uint64_t reserved_26_63 : 38; 4647#endif 4648 } s; 4649 struct cvmx_mio_fus_read_times_s cn61xx; 4650 struct cvmx_mio_fus_read_times_s cn63xx; 4651 struct cvmx_mio_fus_read_times_s cn63xxp1; 4652 struct cvmx_mio_fus_read_times_s cn66xx; 4653 struct cvmx_mio_fus_read_times_s cn68xx; 4654 struct cvmx_mio_fus_read_times_s cn68xxp1; 4655 struct cvmx_mio_fus_read_times_s cnf71xx; 4656}; 4657typedef union cvmx_mio_fus_read_times cvmx_mio_fus_read_times_t; 4658 4659/** 4660 * cvmx_mio_fus_repair_res0 4661 */ 4662union cvmx_mio_fus_repair_res0 { 4663 uint64_t u64; 4664 struct cvmx_mio_fus_repair_res0_s { 4665#ifdef __BIG_ENDIAN_BITFIELD 4666 uint64_t reserved_55_63 : 9; 4667 uint64_t too_many : 1; /**< Too many defects */ 4668 uint64_t repair2 : 18; /**< BISR Results */ 4669 uint64_t repair1 : 18; /**< BISR Results */ 4670 uint64_t repair0 : 18; /**< BISR Results */ 4671#else 4672 uint64_t repair0 : 18; 4673 uint64_t repair1 : 18; 4674 uint64_t repair2 : 18; 4675 uint64_t too_many : 1; 4676 uint64_t reserved_55_63 : 9; 4677#endif 4678 } s; 4679 struct cvmx_mio_fus_repair_res0_s cn61xx; 4680 struct cvmx_mio_fus_repair_res0_s cn63xx; 4681 struct cvmx_mio_fus_repair_res0_s cn63xxp1; 4682 struct cvmx_mio_fus_repair_res0_s cn66xx; 4683 struct cvmx_mio_fus_repair_res0_s cn68xx; 4684 struct cvmx_mio_fus_repair_res0_s cn68xxp1; 4685 struct cvmx_mio_fus_repair_res0_s cnf71xx; 4686}; 4687typedef union cvmx_mio_fus_repair_res0 cvmx_mio_fus_repair_res0_t; 4688 4689/** 4690 * cvmx_mio_fus_repair_res1 4691 */ 4692union cvmx_mio_fus_repair_res1 { 4693 uint64_t u64; 4694 struct cvmx_mio_fus_repair_res1_s { 4695#ifdef __BIG_ENDIAN_BITFIELD 4696 uint64_t reserved_54_63 : 10; 4697 uint64_t repair5 : 18; /**< BISR Results */ 4698 uint64_t repair4 : 18; /**< BISR Results */ 4699 uint64_t repair3 : 18; /**< BISR Results */ 4700#else 4701 uint64_t repair3 : 18; 4702 uint64_t repair4 : 18; 4703 uint64_t repair5 : 18; 4704 uint64_t reserved_54_63 : 10; 4705#endif 4706 } s; 4707 struct cvmx_mio_fus_repair_res1_s cn61xx; 4708 struct cvmx_mio_fus_repair_res1_s cn63xx; 4709 struct cvmx_mio_fus_repair_res1_s cn63xxp1; 4710 struct cvmx_mio_fus_repair_res1_s cn66xx; 4711 struct cvmx_mio_fus_repair_res1_s cn68xx; 4712 struct cvmx_mio_fus_repair_res1_s cn68xxp1; 4713 struct cvmx_mio_fus_repair_res1_s cnf71xx; 4714}; 4715typedef union cvmx_mio_fus_repair_res1 cvmx_mio_fus_repair_res1_t; 4716 4717/** 4718 * cvmx_mio_fus_repair_res2 4719 */ 4720union cvmx_mio_fus_repair_res2 { 4721 uint64_t u64; 4722 struct cvmx_mio_fus_repair_res2_s { 4723#ifdef __BIG_ENDIAN_BITFIELD 4724 uint64_t reserved_18_63 : 46; 4725 uint64_t repair6 : 18; /**< BISR Results */ 4726#else 4727 uint64_t repair6 : 18; 4728 uint64_t reserved_18_63 : 46; 4729#endif 4730 } s; 4731 struct cvmx_mio_fus_repair_res2_s cn61xx; 4732 struct cvmx_mio_fus_repair_res2_s cn63xx; 4733 struct cvmx_mio_fus_repair_res2_s cn63xxp1; 4734 struct cvmx_mio_fus_repair_res2_s cn66xx; 4735 struct cvmx_mio_fus_repair_res2_s cn68xx; 4736 struct cvmx_mio_fus_repair_res2_s cn68xxp1; 4737 struct cvmx_mio_fus_repair_res2_s cnf71xx; 4738}; 4739typedef union cvmx_mio_fus_repair_res2 cvmx_mio_fus_repair_res2_t; 4740 4741/** 4742 * cvmx_mio_fus_spr_repair_res 4743 * 4744 * DON'T PUT IN HRM* 4745 * 4746 */ 4747union cvmx_mio_fus_spr_repair_res { 4748 uint64_t u64; 4749 struct cvmx_mio_fus_spr_repair_res_s { 4750#ifdef __BIG_ENDIAN_BITFIELD 4751 uint64_t reserved_42_63 : 22; 4752 uint64_t repair2 : 14; /**< Reserved (see MIO_FUS_REPAIR_RES*) */ 4753 uint64_t repair1 : 14; /**< Reserved (see MIO_FUS_REPAIR_RES*) */ 4754 uint64_t repair0 : 14; /**< Reserved (see MIO_FUS_REPAIR_RES*) */ 4755#else 4756 uint64_t repair0 : 14; 4757 uint64_t repair1 : 14; 4758 uint64_t repair2 : 14; 4759 uint64_t reserved_42_63 : 22; 4760#endif 4761 } s; 4762 struct cvmx_mio_fus_spr_repair_res_s cn30xx; 4763 struct cvmx_mio_fus_spr_repair_res_s cn31xx; 4764 struct cvmx_mio_fus_spr_repair_res_s cn38xx; 4765 struct cvmx_mio_fus_spr_repair_res_s cn50xx; 4766 struct cvmx_mio_fus_spr_repair_res_s cn52xx; 4767 struct cvmx_mio_fus_spr_repair_res_s cn52xxp1; 4768 struct cvmx_mio_fus_spr_repair_res_s cn56xx; 4769 struct cvmx_mio_fus_spr_repair_res_s cn56xxp1; 4770 struct cvmx_mio_fus_spr_repair_res_s cn58xx; 4771 struct cvmx_mio_fus_spr_repair_res_s cn58xxp1; 4772 struct cvmx_mio_fus_spr_repair_res_s cn61xx; 4773 struct cvmx_mio_fus_spr_repair_res_s cn63xx; 4774 struct cvmx_mio_fus_spr_repair_res_s cn63xxp1; 4775 struct cvmx_mio_fus_spr_repair_res_s cn66xx; 4776 struct cvmx_mio_fus_spr_repair_res_s cn68xx; 4777 struct cvmx_mio_fus_spr_repair_res_s cn68xxp1; 4778 struct cvmx_mio_fus_spr_repair_res_s cnf71xx; 4779}; 4780typedef union cvmx_mio_fus_spr_repair_res cvmx_mio_fus_spr_repair_res_t; 4781 4782/** 4783 * cvmx_mio_fus_spr_repair_sum 4784 * 4785 * DON'T PUT IN HRM* 4786 * 4787 */ 4788union cvmx_mio_fus_spr_repair_sum { 4789 uint64_t u64; 4790 struct cvmx_mio_fus_spr_repair_sum_s { 4791#ifdef __BIG_ENDIAN_BITFIELD 4792 uint64_t reserved_1_63 : 63; 4793 uint64_t too_many : 1; /**< Reserved (see MIO_FUS_REPAIR_RES*) */ 4794#else 4795 uint64_t too_many : 1; 4796 uint64_t reserved_1_63 : 63; 4797#endif 4798 } s; 4799 struct cvmx_mio_fus_spr_repair_sum_s cn30xx; 4800 struct cvmx_mio_fus_spr_repair_sum_s cn31xx; 4801 struct cvmx_mio_fus_spr_repair_sum_s cn38xx; 4802 struct cvmx_mio_fus_spr_repair_sum_s cn50xx; 4803 struct cvmx_mio_fus_spr_repair_sum_s cn52xx; 4804 struct cvmx_mio_fus_spr_repair_sum_s cn52xxp1; 4805 struct cvmx_mio_fus_spr_repair_sum_s cn56xx; 4806 struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1; 4807 struct cvmx_mio_fus_spr_repair_sum_s cn58xx; 4808 struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1; 4809 struct cvmx_mio_fus_spr_repair_sum_s cn61xx; 4810 struct cvmx_mio_fus_spr_repair_sum_s cn63xx; 4811 struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1; 4812 struct cvmx_mio_fus_spr_repair_sum_s cn66xx; 4813 struct cvmx_mio_fus_spr_repair_sum_s cn68xx; 4814 struct cvmx_mio_fus_spr_repair_sum_s cn68xxp1; 4815 struct cvmx_mio_fus_spr_repair_sum_s cnf71xx; 4816}; 4817typedef union cvmx_mio_fus_spr_repair_sum cvmx_mio_fus_spr_repair_sum_t; 4818 4819/** 4820 * cvmx_mio_fus_tgg 4821 * 4822 * Notes: 4823 * The TGG fuses are fuses[831:768]. The valid bit (TGG[63]) is fuse[831]. 4824 * 4825 */ 4826union cvmx_mio_fus_tgg { 4827 uint64_t u64; 4828 struct cvmx_mio_fus_tgg_s { 4829#ifdef __BIG_ENDIAN_BITFIELD 4830 uint64_t val : 1; /**< Out of reset, VAL will return the TGG[63] fuse. 4831 Software may write this CSR bit to zero (to hide 4832 the value of the TGG fuses). Software cannot write 4833 the valid bit to a one, so it is not possible to 4834 read the value of the TGG fuses after the valid 4835 bit is clear. 4836 4837 It is never possible to read the value of the TGG 4838 fuses directly (ie. the only way to read the value 4839 of the TGG fuses is via the MIO_FUS_TGG CSR.) 4840 4841 Whenever the fuse corresponding to the valid bit 4842 (ie. TGG[63]) is blown, it is not possible to blow 4843 the other 63 TGG fuses. (ie. only when the TGG[63] 4844 fuse is not blown, the other 63 TGG fuses can be 4845 blown. The TGG[63] fuse is the one and only fuse 4846 lockdown bit for the other 63 fuses TGG fuses. No 4847 other fuse lockdown bits can prevent blowing the 63 4848 fuses. */ 4849 uint64_t dat : 63; /**< Whenever VAL is clear, DAT will always read as 4850 zero, regardless of the value of the TGG[62:0] 4851 fuses. 4852 4853 Whenever VAL is set, DAT will match the value of 4854 other 63 TGG fuses (ie. TGG[62:0]) */ 4855#else 4856 uint64_t dat : 63; 4857 uint64_t val : 1; 4858#endif 4859 } s; 4860 struct cvmx_mio_fus_tgg_s cn61xx; 4861 struct cvmx_mio_fus_tgg_s cn66xx; 4862 struct cvmx_mio_fus_tgg_s cnf71xx; 4863}; 4864typedef union cvmx_mio_fus_tgg cvmx_mio_fus_tgg_t; 4865 4866/** 4867 * cvmx_mio_fus_unlock 4868 */ 4869union cvmx_mio_fus_unlock { 4870 uint64_t u64; 4871 struct cvmx_mio_fus_unlock_s { 4872#ifdef __BIG_ENDIAN_BITFIELD 4873 uint64_t reserved_24_63 : 40; 4874 uint64_t key : 24; /**< When set to the typical value, allows SW to 4875 program the efuses */ 4876#else 4877 uint64_t key : 24; 4878 uint64_t reserved_24_63 : 40; 4879#endif 4880 } s; 4881 struct cvmx_mio_fus_unlock_s cn30xx; 4882 struct cvmx_mio_fus_unlock_s cn31xx; 4883}; 4884typedef union cvmx_mio_fus_unlock cvmx_mio_fus_unlock_t; 4885 4886/** 4887 * cvmx_mio_fus_wadr 4888 */ 4889union cvmx_mio_fus_wadr { 4890 uint64_t u64; 4891 struct cvmx_mio_fus_wadr_s { 4892#ifdef __BIG_ENDIAN_BITFIELD 4893 uint64_t reserved_10_63 : 54; 4894 uint64_t addr : 10; /**< Which of the banks of 128 fuses to blow */ 4895#else 4896 uint64_t addr : 10; 4897 uint64_t reserved_10_63 : 54; 4898#endif 4899 } s; 4900 struct cvmx_mio_fus_wadr_s cn30xx; 4901 struct cvmx_mio_fus_wadr_s cn31xx; 4902 struct cvmx_mio_fus_wadr_s cn38xx; 4903 struct cvmx_mio_fus_wadr_s cn38xxp2; 4904 struct cvmx_mio_fus_wadr_cn50xx { 4905#ifdef __BIG_ENDIAN_BITFIELD 4906 uint64_t reserved_2_63 : 62; 4907 uint64_t addr : 2; /**< Which of the four banks of 256 fuses to blow */ 4908#else 4909 uint64_t addr : 2; 4910 uint64_t reserved_2_63 : 62; 4911#endif 4912 } cn50xx; 4913 struct cvmx_mio_fus_wadr_cn52xx { 4914#ifdef __BIG_ENDIAN_BITFIELD 4915 uint64_t reserved_3_63 : 61; 4916 uint64_t addr : 3; /**< Which of the four banks of 256 fuses to blow */ 4917#else 4918 uint64_t addr : 3; 4919 uint64_t reserved_3_63 : 61; 4920#endif 4921 } cn52xx; 4922 struct cvmx_mio_fus_wadr_cn52xx cn52xxp1; 4923 struct cvmx_mio_fus_wadr_cn52xx cn56xx; 4924 struct cvmx_mio_fus_wadr_cn52xx cn56xxp1; 4925 struct cvmx_mio_fus_wadr_cn50xx cn58xx; 4926 struct cvmx_mio_fus_wadr_cn50xx cn58xxp1; 4927 struct cvmx_mio_fus_wadr_cn61xx { 4928#ifdef __BIG_ENDIAN_BITFIELD 4929 uint64_t reserved_4_63 : 60; 4930 uint64_t addr : 4; /**< Which of the banks of 128 fuses to blow */ 4931#else 4932 uint64_t addr : 4; 4933 uint64_t reserved_4_63 : 60; 4934#endif 4935 } cn61xx; 4936 struct cvmx_mio_fus_wadr_cn61xx cn63xx; 4937 struct cvmx_mio_fus_wadr_cn61xx cn63xxp1; 4938 struct cvmx_mio_fus_wadr_cn61xx cn66xx; 4939 struct cvmx_mio_fus_wadr_cn61xx cn68xx; 4940 struct cvmx_mio_fus_wadr_cn61xx cn68xxp1; 4941 struct cvmx_mio_fus_wadr_cn61xx cnf71xx; 4942}; 4943typedef union cvmx_mio_fus_wadr cvmx_mio_fus_wadr_t; 4944 4945/** 4946 * cvmx_mio_gpio_comp 4947 * 4948 * MIO_GPIO_COMP = MIO GPIO Compensation Register 4949 * 4950 */ 4951union cvmx_mio_gpio_comp { 4952 uint64_t u64; 4953 struct cvmx_mio_gpio_comp_s { 4954#ifdef __BIG_ENDIAN_BITFIELD 4955 uint64_t reserved_12_63 : 52; 4956 uint64_t pctl : 6; /**< GPIO bus PCTL */ 4957 uint64_t nctl : 6; /**< GPIO bus NCTL */ 4958#else 4959 uint64_t nctl : 6; 4960 uint64_t pctl : 6; 4961 uint64_t reserved_12_63 : 52; 4962#endif 4963 } s; 4964 struct cvmx_mio_gpio_comp_s cn61xx; 4965 struct cvmx_mio_gpio_comp_s cn63xx; 4966 struct cvmx_mio_gpio_comp_s cn63xxp1; 4967 struct cvmx_mio_gpio_comp_s cn66xx; 4968 struct cvmx_mio_gpio_comp_s cn68xx; 4969 struct cvmx_mio_gpio_comp_s cn68xxp1; 4970 struct cvmx_mio_gpio_comp_s cnf71xx; 4971}; 4972typedef union cvmx_mio_gpio_comp cvmx_mio_gpio_comp_t; 4973 4974/** 4975 * cvmx_mio_ndf_dma_cfg 4976 * 4977 * MIO_NDF_DMA_CFG = MIO NAND Flash DMA Config Register 4978 * 4979 * SIZE is specified in number of 64 bit transfers (encoded in -1 notation). 4980 * 4981 * ADR must be 64 bit aligned. 4982 */ 4983union cvmx_mio_ndf_dma_cfg { 4984 uint64_t u64; 4985 struct cvmx_mio_ndf_dma_cfg_s { 4986#ifdef __BIG_ENDIAN_BITFIELD 4987 uint64_t en : 1; /**< DMA Engine enable */ 4988 uint64_t rw : 1; /**< DMA Engine R/W bit (0 = read, 1 = write) */ 4989 uint64_t clr : 1; /**< DMA Engine clear EN on device terminated burst */ 4990 uint64_t reserved_60_60 : 1; 4991 uint64_t swap32 : 1; /**< DMA Engine 32 bit swap */ 4992 uint64_t swap16 : 1; /**< DMA Engine 16 bit swap */ 4993 uint64_t swap8 : 1; /**< DMA Engine 8 bit swap */ 4994 uint64_t endian : 1; /**< DMA Engine NCB endian mode (0 = big, 1 = little) */ 4995 uint64_t size : 20; /**< DMA Engine size */ 4996 uint64_t adr : 36; /**< DMA Engine address */ 4997#else 4998 uint64_t adr : 36; 4999 uint64_t size : 20; 5000 uint64_t endian : 1; 5001 uint64_t swap8 : 1; 5002 uint64_t swap16 : 1; 5003 uint64_t swap32 : 1; 5004 uint64_t reserved_60_60 : 1; 5005 uint64_t clr : 1; 5006 uint64_t rw : 1; 5007 uint64_t en : 1; 5008#endif 5009 } s; 5010 struct cvmx_mio_ndf_dma_cfg_s cn52xx; 5011 struct cvmx_mio_ndf_dma_cfg_s cn61xx; 5012 struct cvmx_mio_ndf_dma_cfg_s cn63xx; 5013 struct cvmx_mio_ndf_dma_cfg_s cn63xxp1; 5014 struct cvmx_mio_ndf_dma_cfg_s cn66xx; 5015 struct cvmx_mio_ndf_dma_cfg_s cn68xx; 5016 struct cvmx_mio_ndf_dma_cfg_s cn68xxp1; 5017 struct cvmx_mio_ndf_dma_cfg_s cnf71xx; 5018}; 5019typedef union cvmx_mio_ndf_dma_cfg cvmx_mio_ndf_dma_cfg_t; 5020 5021/** 5022 * cvmx_mio_ndf_dma_int 5023 * 5024 * MIO_NDF_DMA_INT = MIO NAND Flash DMA Interrupt Register 5025 * 5026 */ 5027union cvmx_mio_ndf_dma_int { 5028 uint64_t u64; 5029 struct cvmx_mio_ndf_dma_int_s { 5030#ifdef __BIG_ENDIAN_BITFIELD 5031 uint64_t reserved_1_63 : 63; 5032 uint64_t done : 1; /**< DMA Engine request completion interrupt */ 5033#else 5034 uint64_t done : 1; 5035 uint64_t reserved_1_63 : 63; 5036#endif 5037 } s; 5038 struct cvmx_mio_ndf_dma_int_s cn52xx; 5039 struct cvmx_mio_ndf_dma_int_s cn61xx; 5040 struct cvmx_mio_ndf_dma_int_s cn63xx; 5041 struct cvmx_mio_ndf_dma_int_s cn63xxp1; 5042 struct cvmx_mio_ndf_dma_int_s cn66xx; 5043 struct cvmx_mio_ndf_dma_int_s cn68xx; 5044 struct cvmx_mio_ndf_dma_int_s cn68xxp1; 5045 struct cvmx_mio_ndf_dma_int_s cnf71xx; 5046}; 5047typedef union cvmx_mio_ndf_dma_int cvmx_mio_ndf_dma_int_t; 5048 5049/** 5050 * cvmx_mio_ndf_dma_int_en 5051 * 5052 * MIO_NDF_DMA_INT_EN = MIO NAND Flash DMA Interrupt Enable Register 5053 * 5054 */ 5055union cvmx_mio_ndf_dma_int_en { 5056 uint64_t u64; 5057 struct cvmx_mio_ndf_dma_int_en_s { 5058#ifdef __BIG_ENDIAN_BITFIELD 5059 uint64_t reserved_1_63 : 63; 5060 uint64_t done : 1; /**< DMA Engine request completion interrupt enable */ 5061#else 5062 uint64_t done : 1; 5063 uint64_t reserved_1_63 : 63; 5064#endif 5065 } s; 5066 struct cvmx_mio_ndf_dma_int_en_s cn52xx; 5067 struct cvmx_mio_ndf_dma_int_en_s cn61xx; 5068 struct cvmx_mio_ndf_dma_int_en_s cn63xx; 5069 struct cvmx_mio_ndf_dma_int_en_s cn63xxp1; 5070 struct cvmx_mio_ndf_dma_int_en_s cn66xx; 5071 struct cvmx_mio_ndf_dma_int_en_s cn68xx; 5072 struct cvmx_mio_ndf_dma_int_en_s cn68xxp1; 5073 struct cvmx_mio_ndf_dma_int_en_s cnf71xx; 5074}; 5075typedef union cvmx_mio_ndf_dma_int_en cvmx_mio_ndf_dma_int_en_t; 5076 5077/** 5078 * cvmx_mio_pll_ctl 5079 */ 5080union cvmx_mio_pll_ctl { 5081 uint64_t u64; 5082 struct cvmx_mio_pll_ctl_s { 5083#ifdef __BIG_ENDIAN_BITFIELD 5084 uint64_t reserved_5_63 : 59; 5085 uint64_t bw_ctl : 5; /**< Core PLL bandwidth control */ 5086#else 5087 uint64_t bw_ctl : 5; 5088 uint64_t reserved_5_63 : 59; 5089#endif 5090 } s; 5091 struct cvmx_mio_pll_ctl_s cn30xx; 5092 struct cvmx_mio_pll_ctl_s cn31xx; 5093}; 5094typedef union cvmx_mio_pll_ctl cvmx_mio_pll_ctl_t; 5095 5096/** 5097 * cvmx_mio_pll_setting 5098 */ 5099union cvmx_mio_pll_setting { 5100 uint64_t u64; 5101 struct cvmx_mio_pll_setting_s { 5102#ifdef __BIG_ENDIAN_BITFIELD 5103 uint64_t reserved_17_63 : 47; 5104 uint64_t setting : 17; /**< Core PLL setting */ 5105#else 5106 uint64_t setting : 17; 5107 uint64_t reserved_17_63 : 47; 5108#endif 5109 } s; 5110 struct cvmx_mio_pll_setting_s cn30xx; 5111 struct cvmx_mio_pll_setting_s cn31xx; 5112}; 5113typedef union cvmx_mio_pll_setting cvmx_mio_pll_setting_t; 5114 5115/** 5116 * cvmx_mio_ptp_ckout_hi_incr 5117 * 5118 * MIO_PTP_CKOUT_HI_INCR = PTP Clock Out Hi Increment 5119 * 5120 */ 5121union cvmx_mio_ptp_ckout_hi_incr { 5122 uint64_t u64; 5123 struct cvmx_mio_ptp_ckout_hi_incr_s { 5124#ifdef __BIG_ENDIAN_BITFIELD 5125 uint64_t nanosec : 32; /**< Nanoseconds */ 5126 uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */ 5127#else 5128 uint64_t frnanosec : 32; 5129 uint64_t nanosec : 32; 5130#endif 5131 } s; 5132 struct cvmx_mio_ptp_ckout_hi_incr_s cn61xx; 5133 struct cvmx_mio_ptp_ckout_hi_incr_s cn66xx; 5134 struct cvmx_mio_ptp_ckout_hi_incr_s cn68xx; 5135 struct cvmx_mio_ptp_ckout_hi_incr_s cnf71xx; 5136}; 5137typedef union cvmx_mio_ptp_ckout_hi_incr cvmx_mio_ptp_ckout_hi_incr_t; 5138 5139/** 5140 * cvmx_mio_ptp_ckout_lo_incr 5141 * 5142 * MIO_PTP_CKOUT_LO_INCR = PTP Clock Out Lo Increment 5143 * 5144 */ 5145union cvmx_mio_ptp_ckout_lo_incr { 5146 uint64_t u64; 5147 struct cvmx_mio_ptp_ckout_lo_incr_s { 5148#ifdef __BIG_ENDIAN_BITFIELD 5149 uint64_t nanosec : 32; /**< Nanoseconds */ 5150 uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */ 5151#else 5152 uint64_t frnanosec : 32; 5153 uint64_t nanosec : 32; 5154#endif 5155 } s; 5156 struct cvmx_mio_ptp_ckout_lo_incr_s cn61xx; 5157 struct cvmx_mio_ptp_ckout_lo_incr_s cn66xx; 5158 struct cvmx_mio_ptp_ckout_lo_incr_s cn68xx; 5159 struct cvmx_mio_ptp_ckout_lo_incr_s cnf71xx; 5160}; 5161typedef union cvmx_mio_ptp_ckout_lo_incr cvmx_mio_ptp_ckout_lo_incr_t; 5162 5163/** 5164 * cvmx_mio_ptp_ckout_thresh_hi 5165 * 5166 * MIO_PTP_CKOUT_THRESH_HI = Hi bytes of PTP Clock Out 5167 * 5168 * Writes to MIO_PTP_CKOUT_THRESH_HI also clear MIO_PTP_CKOUT_THRESH_LO. To update all 96 bits, write MIO_PTP_CKOUT_THRESH_HI followed 5169 * by MIO_PTP_CKOUT_THRESH_LO 5170 */ 5171union cvmx_mio_ptp_ckout_thresh_hi { 5172 uint64_t u64; 5173 struct cvmx_mio_ptp_ckout_thresh_hi_s { 5174#ifdef __BIG_ENDIAN_BITFIELD 5175 uint64_t nanosec : 64; /**< Nanoseconds */ 5176#else 5177 uint64_t nanosec : 64; 5178#endif 5179 } s; 5180 struct cvmx_mio_ptp_ckout_thresh_hi_s cn61xx; 5181 struct cvmx_mio_ptp_ckout_thresh_hi_s cn66xx; 5182 struct cvmx_mio_ptp_ckout_thresh_hi_s cn68xx; 5183 struct cvmx_mio_ptp_ckout_thresh_hi_s cnf71xx; 5184}; 5185typedef union cvmx_mio_ptp_ckout_thresh_hi cvmx_mio_ptp_ckout_thresh_hi_t; 5186 5187/** 5188 * cvmx_mio_ptp_ckout_thresh_lo 5189 * 5190 * MIO_PTP_CKOUT_THRESH_LO = Lo bytes of PTP Clock Out 5191 * 5192 */ 5193union cvmx_mio_ptp_ckout_thresh_lo { 5194 uint64_t u64; 5195 struct cvmx_mio_ptp_ckout_thresh_lo_s { 5196#ifdef __BIG_ENDIAN_BITFIELD 5197 uint64_t reserved_32_63 : 32; 5198 uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */ 5199#else 5200 uint64_t frnanosec : 32; 5201 uint64_t reserved_32_63 : 32; 5202#endif 5203 } s; 5204 struct cvmx_mio_ptp_ckout_thresh_lo_s cn61xx; 5205 struct cvmx_mio_ptp_ckout_thresh_lo_s cn66xx; 5206 struct cvmx_mio_ptp_ckout_thresh_lo_s cn68xx; 5207 struct cvmx_mio_ptp_ckout_thresh_lo_s cnf71xx; 5208}; 5209typedef union cvmx_mio_ptp_ckout_thresh_lo cvmx_mio_ptp_ckout_thresh_lo_t; 5210 5211/** 5212 * cvmx_mio_ptp_clock_cfg 5213 * 5214 * MIO_PTP_CLOCK_CFG = Configuration 5215 * 5216 */ 5217union cvmx_mio_ptp_clock_cfg { 5218 uint64_t u64; 5219 struct cvmx_mio_ptp_clock_cfg_s { 5220#ifdef __BIG_ENDIAN_BITFIELD 5221 uint64_t reserved_42_63 : 22; 5222 uint64_t pps : 1; /**< PTP PPS Output 5223 reflects ptp__pps after PPS_INV inverter */ 5224 uint64_t ckout : 1; /**< PTP Clock Output 5225 reflects ptp__ckout after CKOUT_INV inverter */ 5226 uint64_t ext_clk_edge : 2; /**< External Clock input edge 5227 00 = rising edge 5228 01 = falling edge 5229 10 = both rising & falling edge 5230 11 = reserved */ 5231 uint64_t ckout_out4 : 1; /**< Destination for PTP Clock Out output 5232 See CKOUT_OUT */ 5233 uint64_t pps_out : 5; /**< Destination for PTP PPS output to GPIO 5234 0-19 : GPIO[PPS_OUT[4:0]] 5235 - 20:30: Reserved 5236 31 : Disabled 5237 This should be different from CKOUT_OUT */ 5238 uint64_t pps_inv : 1; /**< Invert PTP PPS 5239 0 = don't invert 5240 1 = invert */ 5241 uint64_t pps_en : 1; /**< Enable PTP PPS */ 5242 uint64_t ckout_out : 4; /**< Destination for PTP Clock Out output to GPIO 5243 0-19 : GPIO[[CKOUT_OUT4,CKOUT_OUT[3:0]]] 5244 - 20:30: Reserved 5245 31 : Disabled 5246 This should be different from PPS_OUT */ 5247 uint64_t ckout_inv : 1; /**< Invert PTP Clock Out 5248 0 = don't invert 5249 1 = invert */ 5250 uint64_t ckout_en : 1; /**< Enable PTP Clock Out */ 5251 uint64_t evcnt_in : 6; /**< Source for event counter input 5252 0x00-0x0f : GPIO[EVCNT_IN[3:0]] 5253 0x20 : GPIO[16] 5254 0x21 : GPIO[17] 5255 0x22 : GPIO[18] 5256 0x23 : GPIO[19] 5257 0x10 : QLM0_REF_CLK 5258 0x11 : QLM1_REF_CLK 5259 0x18 : RF_MCLK (PHY pin) 5260 0x12-0x17 : Reserved 5261 0x19-0x1f : Reserved 5262 0x24-0x3f : Reserved */ 5263 uint64_t evcnt_edge : 1; /**< Event counter input edge 5264 0 = falling edge 5265 1 = rising edge */ 5266 uint64_t evcnt_en : 1; /**< Enable event counter */ 5267 uint64_t tstmp_in : 6; /**< Source for timestamp input 5268 0x00-0x0f : GPIO[TSTMP_IN[3:0]] 5269 0x20 : GPIO[16] 5270 0x21 : GPIO[17] 5271 0x22 : GPIO[18] 5272 0x23 : GPIO[19] 5273 0x10 : QLM0_REF_CLK 5274 0x11 : QLM1_REF_CLK 5275 0x18 : RF_MCLK (PHY pin) 5276 0x12-0x17 : Reserved 5277 0x19-0x1f : Reserved 5278 0x24-0x3f : Reserved */ 5279 uint64_t tstmp_edge : 1; /**< External timestamp input edge 5280 0 = falling edge 5281 1 = rising edge */ 5282 uint64_t tstmp_en : 1; /**< Enable external timestamp */ 5283 uint64_t ext_clk_in : 6; /**< Source for external clock 5284 0x00-0x0f : GPIO[EXT_CLK_IN[3:0]] 5285 0x20 : GPIO[16] 5286 0x21 : GPIO[17] 5287 0x22 : GPIO[18] 5288 0x23 : GPIO[19] 5289 0x10 : QLM0_REF_CLK 5290 0x11 : QLM1_REF_CLK 5291 0x18 : RF_MCLK (PHY pin) 5292 0x12-0x17 : Reserved 5293 0x19-0x1f : Reserved 5294 0x24-0x3f : Reserved */ 5295 uint64_t ext_clk_en : 1; /**< Use external clock */ 5296 uint64_t ptp_en : 1; /**< Enable PTP Module */ 5297#else 5298 uint64_t ptp_en : 1; 5299 uint64_t ext_clk_en : 1; 5300 uint64_t ext_clk_in : 6; 5301 uint64_t tstmp_en : 1; 5302 uint64_t tstmp_edge : 1; 5303 uint64_t tstmp_in : 6; 5304 uint64_t evcnt_en : 1; 5305 uint64_t evcnt_edge : 1; 5306 uint64_t evcnt_in : 6; 5307 uint64_t ckout_en : 1; 5308 uint64_t ckout_inv : 1; 5309 uint64_t ckout_out : 4; 5310 uint64_t pps_en : 1; 5311 uint64_t pps_inv : 1; 5312 uint64_t pps_out : 5; 5313 uint64_t ckout_out4 : 1; 5314 uint64_t ext_clk_edge : 2; 5315 uint64_t ckout : 1; 5316 uint64_t pps : 1; 5317 uint64_t reserved_42_63 : 22; 5318#endif 5319 } s; 5320 struct cvmx_mio_ptp_clock_cfg_s cn61xx; 5321 struct cvmx_mio_ptp_clock_cfg_cn63xx { 5322#ifdef __BIG_ENDIAN_BITFIELD 5323 uint64_t reserved_24_63 : 40; 5324 uint64_t evcnt_in : 6; /**< Source for event counter input 5325 0x00-0x0f : GPIO[EVCNT_IN[3:0]] 5326 0x10 : QLM0_REF_CLK 5327 0x11 : QLM1_REF_CLK 5328 0x12 : QLM2_REF_CLK 5329 0x13-0x3f : Reserved */ 5330 uint64_t evcnt_edge : 1; /**< Event counter input edge 5331 0 = falling edge 5332 1 = rising edge */ 5333 uint64_t evcnt_en : 1; /**< Enable event counter */ 5334 uint64_t tstmp_in : 6; /**< Source for timestamp input 5335 0x00-0x0f : GPIO[TSTMP_IN[3:0]] 5336 0x10 : QLM0_REF_CLK 5337 0x11 : QLM1_REF_CLK 5338 0x12 : QLM2_REF_CLK 5339 0x13-0x3f : Reserved */ 5340 uint64_t tstmp_edge : 1; /**< External timestamp input edge 5341 0 = falling edge 5342 1 = rising edge */ 5343 uint64_t tstmp_en : 1; /**< Enable external timestamp */ 5344 uint64_t ext_clk_in : 6; /**< Source for external clock 5345 0x00-0x0f : GPIO[EXT_CLK_IN[3:0]] 5346 0x10 : QLM0_REF_CLK 5347 0x11 : QLM1_REF_CLK 5348 0x12 : QLM2_REF_CLK 5349 0x13-0x3f : Reserved */ 5350 uint64_t ext_clk_en : 1; /**< Use positive edge of external clock */ 5351 uint64_t ptp_en : 1; /**< Enable PTP Module */ 5352#else 5353 uint64_t ptp_en : 1; 5354 uint64_t ext_clk_en : 1; 5355 uint64_t ext_clk_in : 6; 5356 uint64_t tstmp_en : 1; 5357 uint64_t tstmp_edge : 1; 5358 uint64_t tstmp_in : 6; 5359 uint64_t evcnt_en : 1; 5360 uint64_t evcnt_edge : 1; 5361 uint64_t evcnt_in : 6; 5362 uint64_t reserved_24_63 : 40; 5363#endif 5364 } cn63xx; 5365 struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1; 5366 struct cvmx_mio_ptp_clock_cfg_cn66xx { 5367#ifdef __BIG_ENDIAN_BITFIELD 5368 uint64_t reserved_40_63 : 24; 5369 uint64_t ext_clk_edge : 2; /**< External Clock input edge 5370 00 = rising edge 5371 01 = falling edge 5372 10 = both rising & falling edge 5373 11 = reserved */ 5374 uint64_t ckout_out4 : 1; /**< Destination for PTP Clock Out output 5375 0-19 : GPIO[[CKOUT_OUT4,CKOUT_OUT[3:0]]] 5376 This should be different from PPS_OUT */ 5377 uint64_t pps_out : 5; /**< Destination for PTP PPS output 5378 0-19 : GPIO[PPS_OUT[4:0]] 5379 This should be different from CKOUT_OUT */ 5380 uint64_t pps_inv : 1; /**< Invert PTP PPS 5381 0 = don't invert 5382 1 = invert */ 5383 uint64_t pps_en : 1; /**< Enable PTP PPS */ 5384 uint64_t ckout_out : 4; /**< Destination for PTP Clock Out output 5385 0-19 : GPIO[[CKOUT_OUT4,CKOUT_OUT[3:0]]] 5386 This should be different from PPS_OUT */ 5387 uint64_t ckout_inv : 1; /**< Invert PTP Clock Out 5388 0 = don't invert 5389 1 = invert */ 5390 uint64_t ckout_en : 1; /**< Enable PTP Clock Out */ 5391 uint64_t evcnt_in : 6; /**< Source for event counter input 5392 0x00-0x0f : GPIO[EVCNT_IN[3:0]] 5393 0x20 : GPIO[16] 5394 0x21 : GPIO[17] 5395 0x22 : GPIO[18] 5396 0x23 : GPIO[19] 5397 0x10 : QLM0_REF_CLK 5398 0x11 : QLM1_REF_CLK 5399 0x12 : QLM2_REF_CLK 5400 0x13-0x1f : Reserved 5401 0x24-0x3f : Reserved */ 5402 uint64_t evcnt_edge : 1; /**< Event counter input edge 5403 0 = falling edge 5404 1 = rising edge */ 5405 uint64_t evcnt_en : 1; /**< Enable event counter */ 5406 uint64_t tstmp_in : 6; /**< Source for timestamp input 5407 0x00-0x0f : GPIO[TSTMP_IN[3:0]] 5408 0x20 : GPIO[16] 5409 0x21 : GPIO[17] 5410 0x22 : GPIO[18] 5411 0x23 : GPIO[19] 5412 0x10 : QLM0_REF_CLK 5413 0x11 : QLM1_REF_CLK 5414 0x12 : QLM2_REF_CLK 5415 0x13-0x1f : Reserved 5416 0x24-0x3f : Reserved */ 5417 uint64_t tstmp_edge : 1; /**< External timestamp input edge 5418 0 = falling edge 5419 1 = rising edge */ 5420 uint64_t tstmp_en : 1; /**< Enable external timestamp */ 5421 uint64_t ext_clk_in : 6; /**< Source for external clock 5422 0x00-0x0f : GPIO[EXT_CLK_IN[3:0]] 5423 0x20 : GPIO[16] 5424 0x21 : GPIO[17] 5425 0x22 : GPIO[18] 5426 0x23 : GPIO[19] 5427 0x10 : QLM0_REF_CLK 5428 0x11 : QLM1_REF_CLK 5429 0x12 : QLM2_REF_CLK 5430 0x13-0x1f : Reserved 5431 0x24-0x3f : Reserved */ 5432 uint64_t ext_clk_en : 1; /**< Use external clock */ 5433 uint64_t ptp_en : 1; /**< Enable PTP Module */ 5434#else 5435 uint64_t ptp_en : 1; 5436 uint64_t ext_clk_en : 1; 5437 uint64_t ext_clk_in : 6; 5438 uint64_t tstmp_en : 1; 5439 uint64_t tstmp_edge : 1; 5440 uint64_t tstmp_in : 6; 5441 uint64_t evcnt_en : 1; 5442 uint64_t evcnt_edge : 1; 5443 uint64_t evcnt_in : 6; 5444 uint64_t ckout_en : 1; 5445 uint64_t ckout_inv : 1; 5446 uint64_t ckout_out : 4; 5447 uint64_t pps_en : 1; 5448 uint64_t pps_inv : 1; 5449 uint64_t pps_out : 5; 5450 uint64_t ckout_out4 : 1; 5451 uint64_t ext_clk_edge : 2; 5452 uint64_t reserved_40_63 : 24; 5453#endif 5454 } cn66xx; 5455 struct cvmx_mio_ptp_clock_cfg_s cn68xx; 5456 struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1; 5457 struct cvmx_mio_ptp_clock_cfg_s cnf71xx; 5458}; 5459typedef union cvmx_mio_ptp_clock_cfg cvmx_mio_ptp_clock_cfg_t; 5460 5461/** 5462 * cvmx_mio_ptp_clock_comp 5463 * 5464 * MIO_PTP_CLOCK_COMP = Compensator 5465 * 5466 */ 5467union cvmx_mio_ptp_clock_comp { 5468 uint64_t u64; 5469 struct cvmx_mio_ptp_clock_comp_s { 5470#ifdef __BIG_ENDIAN_BITFIELD 5471 uint64_t nanosec : 32; /**< Nanoseconds */ 5472 uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */ 5473#else 5474 uint64_t frnanosec : 32; 5475 uint64_t nanosec : 32; 5476#endif 5477 } s; 5478 struct cvmx_mio_ptp_clock_comp_s cn61xx; 5479 struct cvmx_mio_ptp_clock_comp_s cn63xx; 5480 struct cvmx_mio_ptp_clock_comp_s cn63xxp1; 5481 struct cvmx_mio_ptp_clock_comp_s cn66xx; 5482 struct cvmx_mio_ptp_clock_comp_s cn68xx; 5483 struct cvmx_mio_ptp_clock_comp_s cn68xxp1; 5484 struct cvmx_mio_ptp_clock_comp_s cnf71xx; 5485}; 5486typedef union cvmx_mio_ptp_clock_comp cvmx_mio_ptp_clock_comp_t; 5487 5488/** 5489 * cvmx_mio_ptp_clock_hi 5490 * 5491 * MIO_PTP_CLOCK_HI = Hi bytes of CLOCK 5492 * 5493 * Writes to MIO_PTP_CLOCK_HI also clear MIO_PTP_CLOCK_LO. To update all 96 bits, write MIO_PTP_CLOCK_HI followed 5494 * by MIO_PTP_CLOCK_LO 5495 */ 5496union cvmx_mio_ptp_clock_hi { 5497 uint64_t u64; 5498 struct cvmx_mio_ptp_clock_hi_s { 5499#ifdef __BIG_ENDIAN_BITFIELD 5500 uint64_t nanosec : 64; /**< Nanoseconds */ 5501#else 5502 uint64_t nanosec : 64; 5503#endif 5504 } s; 5505 struct cvmx_mio_ptp_clock_hi_s cn61xx; 5506 struct cvmx_mio_ptp_clock_hi_s cn63xx; 5507 struct cvmx_mio_ptp_clock_hi_s cn63xxp1; 5508 struct cvmx_mio_ptp_clock_hi_s cn66xx; 5509 struct cvmx_mio_ptp_clock_hi_s cn68xx; 5510 struct cvmx_mio_ptp_clock_hi_s cn68xxp1; 5511 struct cvmx_mio_ptp_clock_hi_s cnf71xx; 5512}; 5513typedef union cvmx_mio_ptp_clock_hi cvmx_mio_ptp_clock_hi_t; 5514 5515/** 5516 * cvmx_mio_ptp_clock_lo 5517 * 5518 * MIO_PTP_CLOCK_LO = Lo bytes of CLOCK 5519 * 5520 */ 5521union cvmx_mio_ptp_clock_lo { 5522 uint64_t u64; 5523 struct cvmx_mio_ptp_clock_lo_s { 5524#ifdef __BIG_ENDIAN_BITFIELD 5525 uint64_t reserved_32_63 : 32; 5526 uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */ 5527#else 5528 uint64_t frnanosec : 32; 5529 uint64_t reserved_32_63 : 32; 5530#endif 5531 } s; 5532 struct cvmx_mio_ptp_clock_lo_s cn61xx; 5533 struct cvmx_mio_ptp_clock_lo_s cn63xx; 5534 struct cvmx_mio_ptp_clock_lo_s cn63xxp1; 5535 struct cvmx_mio_ptp_clock_lo_s cn66xx; 5536 struct cvmx_mio_ptp_clock_lo_s cn68xx; 5537 struct cvmx_mio_ptp_clock_lo_s cn68xxp1; 5538 struct cvmx_mio_ptp_clock_lo_s cnf71xx; 5539}; 5540typedef union cvmx_mio_ptp_clock_lo cvmx_mio_ptp_clock_lo_t; 5541 5542/** 5543 * cvmx_mio_ptp_evt_cnt 5544 * 5545 * MIO_PTP_EVT_CNT = Event Counter 5546 * 5547 * Writes to MIO_PTP_EVT_CNT increment this register by the written data. The register counts down by 5548 * 1 for every MIO_PTP_CLOCK_CFG[EVCNT_EDGE] edge of MIO_PTP_CLOCK_CFG[EVCNT_IN]. When register equals 5549 * 0, an interrupt gets gerated 5550 */ 5551union cvmx_mio_ptp_evt_cnt { 5552 uint64_t u64; 5553 struct cvmx_mio_ptp_evt_cnt_s { 5554#ifdef __BIG_ENDIAN_BITFIELD 5555 uint64_t cntr : 64; /**< Nanoseconds */ 5556#else 5557 uint64_t cntr : 64; 5558#endif 5559 } s; 5560 struct cvmx_mio_ptp_evt_cnt_s cn61xx; 5561 struct cvmx_mio_ptp_evt_cnt_s cn63xx; 5562 struct cvmx_mio_ptp_evt_cnt_s cn63xxp1; 5563 struct cvmx_mio_ptp_evt_cnt_s cn66xx; 5564 struct cvmx_mio_ptp_evt_cnt_s cn68xx; 5565 struct cvmx_mio_ptp_evt_cnt_s cn68xxp1; 5566 struct cvmx_mio_ptp_evt_cnt_s cnf71xx; 5567}; 5568typedef union cvmx_mio_ptp_evt_cnt cvmx_mio_ptp_evt_cnt_t; 5569 5570/** 5571 * cvmx_mio_ptp_phy_1pps_in 5572 * 5573 * MIO_PTP_PHY_1PPS_IN = PHY 1PPS input mux selection 5574 * 5575 */ 5576union cvmx_mio_ptp_phy_1pps_in { 5577 uint64_t u64; 5578 struct cvmx_mio_ptp_phy_1pps_in_s { 5579#ifdef __BIG_ENDIAN_BITFIELD 5580 uint64_t reserved_5_63 : 59; 5581 uint64_t sel : 5; /**< Source for PHY 1pps input signal 5582 0-19 : GPIO[SEL[4:0]], for AGPS_1PPS 5583 24 : PPS_OUT (Enabled by PPS_EN and PPS_INV, 5584 reflects ptp_pps after PPS_INV inverter) 5585 - 20-23: Reserved 5586 - 25-30: Reserved 5587 31 : Disabled */ 5588#else 5589 uint64_t sel : 5; 5590 uint64_t reserved_5_63 : 59; 5591#endif 5592 } s; 5593 struct cvmx_mio_ptp_phy_1pps_in_s cnf71xx; 5594}; 5595typedef union cvmx_mio_ptp_phy_1pps_in cvmx_mio_ptp_phy_1pps_in_t; 5596 5597/** 5598 * cvmx_mio_ptp_pps_hi_incr 5599 * 5600 * MIO_PTP_PPS_HI_INCR = PTP PPS Hi Increment 5601 * 5602 */ 5603union cvmx_mio_ptp_pps_hi_incr { 5604 uint64_t u64; 5605 struct cvmx_mio_ptp_pps_hi_incr_s { 5606#ifdef __BIG_ENDIAN_BITFIELD 5607 uint64_t nanosec : 32; /**< Nanoseconds */ 5608 uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */ 5609#else 5610 uint64_t frnanosec : 32; 5611 uint64_t nanosec : 32; 5612#endif 5613 } s; 5614 struct cvmx_mio_ptp_pps_hi_incr_s cn61xx; 5615 struct cvmx_mio_ptp_pps_hi_incr_s cn66xx; 5616 struct cvmx_mio_ptp_pps_hi_incr_s cn68xx; 5617 struct cvmx_mio_ptp_pps_hi_incr_s cnf71xx; 5618}; 5619typedef union cvmx_mio_ptp_pps_hi_incr cvmx_mio_ptp_pps_hi_incr_t; 5620 5621/** 5622 * cvmx_mio_ptp_pps_lo_incr 5623 * 5624 * MIO_PTP_PPS_LO_INCR = PTP PPS Lo Increment 5625 * 5626 */ 5627union cvmx_mio_ptp_pps_lo_incr { 5628 uint64_t u64; 5629 struct cvmx_mio_ptp_pps_lo_incr_s { 5630#ifdef __BIG_ENDIAN_BITFIELD 5631 uint64_t nanosec : 32; /**< Nanoseconds */ 5632 uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */ 5633#else 5634 uint64_t frnanosec : 32; 5635 uint64_t nanosec : 32; 5636#endif 5637 } s; 5638 struct cvmx_mio_ptp_pps_lo_incr_s cn61xx; 5639 struct cvmx_mio_ptp_pps_lo_incr_s cn66xx; 5640 struct cvmx_mio_ptp_pps_lo_incr_s cn68xx; 5641 struct cvmx_mio_ptp_pps_lo_incr_s cnf71xx; 5642}; 5643typedef union cvmx_mio_ptp_pps_lo_incr cvmx_mio_ptp_pps_lo_incr_t; 5644 5645/** 5646 * cvmx_mio_ptp_pps_thresh_hi 5647 * 5648 * MIO_PTP_PPS_THRESH_HI = Hi bytes of PTP PPS 5649 * 5650 * Writes to MIO_PTP_PPS_THRESH_HI also clear MIO_PTP_PPS_THRESH_LO. To update all 96 bits, write MIO_PTP_PPS_THRESH_HI followed 5651 * by MIO_PTP_PPS_THRESH_LO 5652 */ 5653union cvmx_mio_ptp_pps_thresh_hi { 5654 uint64_t u64; 5655 struct cvmx_mio_ptp_pps_thresh_hi_s { 5656#ifdef __BIG_ENDIAN_BITFIELD 5657 uint64_t nanosec : 64; /**< Nanoseconds */ 5658#else 5659 uint64_t nanosec : 64; 5660#endif 5661 } s; 5662 struct cvmx_mio_ptp_pps_thresh_hi_s cn61xx; 5663 struct cvmx_mio_ptp_pps_thresh_hi_s cn66xx; 5664 struct cvmx_mio_ptp_pps_thresh_hi_s cn68xx; 5665 struct cvmx_mio_ptp_pps_thresh_hi_s cnf71xx; 5666}; 5667typedef union cvmx_mio_ptp_pps_thresh_hi cvmx_mio_ptp_pps_thresh_hi_t; 5668 5669/** 5670 * cvmx_mio_ptp_pps_thresh_lo 5671 * 5672 * MIO_PTP_PPS_THRESH_LO = Lo bytes of PTP PPS 5673 * 5674 */ 5675union cvmx_mio_ptp_pps_thresh_lo { 5676 uint64_t u64; 5677 struct cvmx_mio_ptp_pps_thresh_lo_s { 5678#ifdef __BIG_ENDIAN_BITFIELD 5679 uint64_t reserved_32_63 : 32; 5680 uint64_t frnanosec : 32; /**< Fractions of Nanoseconds */ 5681#else 5682 uint64_t frnanosec : 32; 5683 uint64_t reserved_32_63 : 32; 5684#endif 5685 } s; 5686 struct cvmx_mio_ptp_pps_thresh_lo_s cn61xx; 5687 struct cvmx_mio_ptp_pps_thresh_lo_s cn66xx; 5688 struct cvmx_mio_ptp_pps_thresh_lo_s cn68xx; 5689 struct cvmx_mio_ptp_pps_thresh_lo_s cnf71xx; 5690}; 5691typedef union cvmx_mio_ptp_pps_thresh_lo cvmx_mio_ptp_pps_thresh_lo_t; 5692 5693/** 5694 * cvmx_mio_ptp_timestamp 5695 * 5696 * MIO_PTP_TIMESTAMP = Timestamp latched on MIO_PTP_CLOCK_CFG[TSTMP_EDGE] edge of MIO_PTP_CLOCK_CFG[TSTMP_IN] 5697 * 5698 */ 5699union cvmx_mio_ptp_timestamp { 5700 uint64_t u64; 5701 struct cvmx_mio_ptp_timestamp_s { 5702#ifdef __BIG_ENDIAN_BITFIELD 5703 uint64_t nanosec : 64; /**< Nanoseconds */ 5704#else 5705 uint64_t nanosec : 64; 5706#endif 5707 } s; 5708 struct cvmx_mio_ptp_timestamp_s cn61xx; 5709 struct cvmx_mio_ptp_timestamp_s cn63xx; 5710 struct cvmx_mio_ptp_timestamp_s cn63xxp1; 5711 struct cvmx_mio_ptp_timestamp_s cn66xx; 5712 struct cvmx_mio_ptp_timestamp_s cn68xx; 5713 struct cvmx_mio_ptp_timestamp_s cn68xxp1; 5714 struct cvmx_mio_ptp_timestamp_s cnf71xx; 5715}; 5716typedef union cvmx_mio_ptp_timestamp cvmx_mio_ptp_timestamp_t; 5717 5718/** 5719 * cvmx_mio_qlm#_cfg 5720 * 5721 * Notes: 5722 * Certain QLM_SPD is valid only for certain QLM_CFG configuration, refer to HRM for valid 5723 * combinations. These csrs are reset only on COLD_RESET. The Reset values for QLM_SPD and QLM_CFG 5724 * are as follows: MIO_QLM0_CFG SPD=F, CFG=2 SGMII (AGX0) 5725 * MIO_QLM1_CFG SPD=0, CFG=1 PCIE 2x1 (PEM0/PEM1) 5726 */ 5727union cvmx_mio_qlmx_cfg { 5728 uint64_t u64; 5729 struct cvmx_mio_qlmx_cfg_s { 5730#ifdef __BIG_ENDIAN_BITFIELD 5731 uint64_t reserved_15_63 : 49; 5732 uint64_t prtmode : 1; /**< Port Mode, value of MIO_RST_CNTLX.PRTMODE[0] 5733 0 = port is EP mode 5734 1 = port is RC mode */ 5735 uint64_t reserved_12_13 : 2; 5736 uint64_t qlm_spd : 4; /**< QLM0 speed for SGMii 5737 0 = 5 Gbaud 100.00 MHz Ref 5738 1 = 2.5 Gbaud 100.00 MHz Ref 5739 2 = 2.5 Gbaud 100.00 MHz Ref 5740 3 = 1.25 Gbaud 100.00 MHz Ref 5741 4 = 1.25 Gbaud 156.25 MHz Ref 5742 5 = 6.25 Gbaud 125.00 MHz Ref 5743 6 = 5 Gbaud 125.00 MHz Ref 5744 7 = 2.5 Gbaud 156.25 MHz Ref 5745 8 = 3.125 Gbaud 125.00 MHz Ref 5746 9 = 2.5 Gbaud 125.00 MHz Ref 5747 10 = 1.25 Gbaud 125.00 MHz Ref 5748 11 = 5 Gbaud 156.25 MHz Ref 5749 12 = 6.25 Gbaud 156.25 MHz Ref 5750 13 = 3.75 Gbaud 156.25 MHz Ref 5751 14 = 3.125 Gbaud 156.25 MHz Ref 5752 15 = QLM Disabled 5753 5754 QLM1 speed PEM0 PEM1 5755 0 = 2.5/5 2.5/5 Gbaud 100.00 MHz Ref 5756 1 = 2.5 2.5/5 Gbaud 100.00 MHz Ref 5757 2 = 2.5/5 2.5 Gbaud 100.00 MHz Ref 5758 3 = 2.5 2.5 Gbaud 100.00 MHz Ref 5759 4 = 2.5/5 2.5/5 Gbaud 125.00 MHz Ref 5760 6 = 2.5/5 2.5 Gbaud 125.00 MHz Ref 5761 7 = 2.5 2.5 Gbaud 125.00 MHz Ref 5762 9 = 2.5 2.5/5 Gbaud 125.00 MHz Ref 5763 15 = QLM Disabled 5764 5,8,10-14 are reserved */ 5765 uint64_t reserved_4_7 : 4; 5766 uint64_t qlm_cfg : 4; /**< QLM configuration mode 5767 For Interface 0: 5768 00 Reserved 5769 01 Reserved 5770 10 SGMII (AGX0) 5771 11 Reserved 5772 For Interface 1: 5773 00 PCIE 1x2 (PEM1) 5774 01 PCIE 2x1 (PEM0/PEM1) 5775 1x Reserved */ 5776#else 5777 uint64_t qlm_cfg : 4; 5778 uint64_t reserved_4_7 : 4; 5779 uint64_t qlm_spd : 4; 5780 uint64_t reserved_12_13 : 2; 5781 uint64_t prtmode : 1; 5782 uint64_t reserved_15_63 : 49; 5783#endif 5784 } s; 5785 struct cvmx_mio_qlmx_cfg_cn61xx { 5786#ifdef __BIG_ENDIAN_BITFIELD 5787 uint64_t reserved_15_63 : 49; 5788 uint64_t prtmode : 1; /**< Port Mode, value of MIO_RST_CNTLX.PRTMODE[0] 5789 0 = port is EP mode 5790 1 = port is RC mode 5791 For QLM2, HOST_MODE is always '0' because PCIe 5792 is not supported. */ 5793 uint64_t reserved_12_13 : 2; 5794 uint64_t qlm_spd : 4; /**< QLM speed for SGMii/XAUI 5795 0 = 5 Gbaud 100.00 MHz Ref 5796 1 = 2.5 Gbaud 100.00 MHz Ref 5797 2 = 2.5 Gbaud 100.00 MHz Ref 5798 3 = 1.25 Gbaud 100.00 MHz Ref 5799 4 = 1.25 Gbaud 156.25 MHz Ref 5800 5 = 6.25 Gbaud 125.00 MHz Ref 5801 6 = 5 Gbaud 125.00 MHz Ref 5802 7 = 2.5 Gbaud 156.25 MHz Ref 5803 8 = 3.125 Gbaud 125.00 MHz Ref 5804 9 = 2.5 Gbaud 125.00 MHz Ref 5805 10 = 1.25 Gbaud 125.00 MHz Ref 5806 11 = 5 Gbaud 156.25 MHz Ref 5807 12 = 6.25 Gbaud 156.25 MHz Ref 5808 13 = 3.75 Gbaud 156.25 MHz Ref 5809 14 = 3.125 Gbaud 156.25 MHz Ref 5810 15 = QLM Disabled 5811 5812 QLM speed PEM0 PEM1 5813 0 = 2.5/5 2.5/5 Gbaud 100.00 MHz Ref 5814 1 = 2.5 2.5/5 Gbaud 100.00 MHz Ref 5815 2 = 2.5/5 2.5 Gbaud 100.00 MHz Ref 5816 3 = 2.5 2.5 Gbaud 100.00 MHz Ref 5817 4 = 2.5/5 2.5/5 Gbaud 125.00 MHz Ref 5818 6 = 2.5/5 2.5 Gbaud 125.00 MHz Ref 5819 7 = 2.5 2.5 Gbaud 125.00 MHz Ref 5820 9 = 2.5 2.5/5 Gbaud 125.00 MHz Ref 5821 15 = QLM Disabled 5822 5,8,10-14 are reserved */ 5823 uint64_t reserved_2_7 : 6; 5824 uint64_t qlm_cfg : 2; /**< QLM configuration mode 5825 For Interface 0: 5826 00 PCIE 1x4 (PEM0) 5827 01 Reserved 5828 10 SGMII (AGX1) 5829 11 XAUI (AGX1) 5830 For Interface 1: 5831 00 PCIE 1x2 (PEM1) 5832 01 PCIE 2x1 (PEM0/PEM1) 5833 10 Reserved 5834 11 Reserved 5835 For Interface 2: 5836 00 Reserved 5837 01 Reserved 5838 10 SGMII (AGX0) 5839 11 XAUI (AGX0) */ 5840#else 5841 uint64_t qlm_cfg : 2; 5842 uint64_t reserved_2_7 : 6; 5843 uint64_t qlm_spd : 4; 5844 uint64_t reserved_12_13 : 2; 5845 uint64_t prtmode : 1; 5846 uint64_t reserved_15_63 : 49; 5847#endif 5848 } cn61xx; 5849 struct cvmx_mio_qlmx_cfg_cn66xx { 5850#ifdef __BIG_ENDIAN_BITFIELD 5851 uint64_t reserved_12_63 : 52; 5852 uint64_t qlm_spd : 4; /**< QLM speed 5853 0 = 5 Gbaud 5854 1 = 2.5 Gbaud 5855 2 = 2.5 Gbaud 5856 3 = 1.25 Gbaud 5857 4 = 1.25 Gbaud 5858 5 = 6.25 Gbaud 5859 6 = 5 Gbaud 5860 7 = 2.5 Gbaud 5861 8 = 3.125 Gbaud 5862 9 = 2.5 Gbaud 5863 10 = 1.25 Gbaud 5864 11 = 5 Gbaud 5865 12 = 6.25 Gbaud 5866 13 = 3.75 Gbaud 5867 14 = 3.125 Gbaud 5868 15 = QLM Disabled */ 5869 uint64_t reserved_4_7 : 4; 5870 uint64_t qlm_cfg : 4; /**< QLM configuration mode 5871 0000 PCIE gen2 5872 0001 SRIO 1x4 short 5873 0010 PCIE gen1 only 5874 0011 SRIO 1x4 long 5875 0100 SRIO 2x2 short 5876 0101 SRIO 4x1 short 5877 0110 SRIO 2x2 long 5878 0111 SRIO 4x1 long 5879 1000 PCIE gen2 (alias) 5880 1001 SGMII 5881 1010 PCIE gen1 only (alias) 5882 1011 XAUI 5883 1100 RESERVED 5884 1101 RESERVED 5885 1110 RESERVED 5886 1111 RESERVED 5887 NOTE: Internal encodings differ from QLM_MODE 5888 pins encodings */ 5889#else 5890 uint64_t qlm_cfg : 4; 5891 uint64_t reserved_4_7 : 4; 5892 uint64_t qlm_spd : 4; 5893 uint64_t reserved_12_63 : 52; 5894#endif 5895 } cn66xx; 5896 struct cvmx_mio_qlmx_cfg_cn68xx { 5897#ifdef __BIG_ENDIAN_BITFIELD 5898 uint64_t reserved_12_63 : 52; 5899 uint64_t qlm_spd : 4; /**< QLM speed 5900 0 = 5 Gbaud 100.00 MHz Ref 5901 1 = 2.5 Gbaud 100.00 MHz Ref 5902 2 = 2.5 Gbaud 100.00 MHz Ref 5903 3 = 1.25 Gbaud 100.00 MHz Ref 5904 4 = 1.25 Gbaud 156.25 MHz Ref 5905 5 = 6.25 Gbaud 125.00 MHz Ref 5906 6 = 5 Gbaud 125.00 MHz Ref 5907 7 = 2.5 Gbaud 156.25 MHz Ref 5908 8 = 3.125 Gbaud 125.00 MHz Ref 5909 9 = 2.5 Gbaud 125.00 MHz Ref 5910 10 = 1.25 Gbaud 125.00 MHz Ref 5911 11 = 5 Gbaud 156.25 MHz Ref 5912 12 = 6.25 Gbaud 156.25 MHz Ref 5913 13 = 3.75 Gbaud 156.25 MHz Ref 5914 14 = 3.125 Gbaud 156.25 MHz Ref 5915 15 = QLM Disabled */ 5916 uint64_t reserved_3_7 : 5; 5917 uint64_t qlm_cfg : 3; /**< QLM configuration mode 5918 000 = PCIE 5919 001 = ILK 5920 010 = SGMII 5921 011 = XAUI 5922 100 = RESERVED 5923 101 = RESERVED 5924 110 = RESERVED 5925 111 = RXAUI 5926 NOTE: Internal encodings differ from QLM_MODE 5927 pins encodings */ 5928#else 5929 uint64_t qlm_cfg : 3; 5930 uint64_t reserved_3_7 : 5; 5931 uint64_t qlm_spd : 4; 5932 uint64_t reserved_12_63 : 52; 5933#endif 5934 } cn68xx; 5935 struct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1; 5936 struct cvmx_mio_qlmx_cfg_cn61xx cnf71xx; 5937}; 5938typedef union cvmx_mio_qlmx_cfg cvmx_mio_qlmx_cfg_t; 5939 5940/** 5941 * cvmx_mio_rst_boot 5942 * 5943 * Notes: 5944 * JTCSRDIS, EJTAGDIS, ROMEN reset to 1 in authentik mode; in all other modes they reset to 0. 5945 * 5946 */ 5947union cvmx_mio_rst_boot { 5948 uint64_t u64; 5949 struct cvmx_mio_rst_boot_s { 5950#ifdef __BIG_ENDIAN_BITFIELD 5951 uint64_t chipkill : 1; /**< A 0->1 transition of CHIPKILL starts the CHIPKILL 5952 timer. When CHIPKILL=1 and the timer expires, 5953 internal chip reset is asserted forever until the 5954 next chip reset. The CHIPKILL timer can be 5955 stopped only by a chip (cold, warm, soft) reset. 5956 The length of the CHIPKILL timer is specified by 5957 MIO_RST_CKILL[TIMER]. */ 5958 uint64_t jtcsrdis : 1; /**< If JTCSRDIS=1, internal CSR access via JTAG TAP 5959 controller is disabled */ 5960 uint64_t ejtagdis : 1; /**< If EJTAGDIS=1, external EJTAG access is disabled */ 5961 uint64_t romen : 1; /**< If ROMEN=1, Authentik/eMMC boot ROM is visible 5962 in the boot bus address space. */ 5963 uint64_t ckill_ppdis : 1; /**< If CK_PPDIS=1, PPs other than 0 are disabled 5964 during a CHIPKILL. Writes have no effect when 5965 MIO_RST_BOOT[CHIPKILL]=1. */ 5966 uint64_t jt_tstmode : 1; /**< JTAG test mode */ 5967 uint64_t reserved_50_57 : 8; 5968 uint64_t lboot_ext : 2; /**< Reserved */ 5969 uint64_t reserved_44_47 : 4; 5970 uint64_t qlm4_spd : 4; /**< QLM4_SPD pins sampled at DCOK assertion */ 5971 uint64_t qlm3_spd : 4; /**< QLM3_SPD pins sampled at DCOK assertion */ 5972 uint64_t c_mul : 6; /**< Core clock multiplier: 5973 C_MUL = (core clk speed) / (ref clock speed) 5974 "ref clock speed" should always be 50MHz. 5975 If PLL_QLM_REF_CLK_EN=0, "ref clock" comes 5976 from PLL_REF_CLK pin. 5977 If PLL_QLM_REF_CLK_EN=1, "ref clock" is 5978 1/2 speed of QLMC_REF_CLK_* pins. */ 5979 uint64_t pnr_mul : 6; /**< Coprocessor clock multiplier: 5980 PNR_MUL = (coprocessor clk speed) / 5981 (ref clock speed) 5982 See C_MUL comments about ref clock. */ 5983 uint64_t qlm2_spd : 4; /**< QLM2_SPD, report MIO_QLM2_CFG[SPD] */ 5984 uint64_t qlm1_spd : 4; /**< QLM1_SPD, report MIO_QLM1_CFG[SPD] */ 5985 uint64_t qlm0_spd : 4; /**< QLM0_SPD, report MIO_QLM0_CFG[SPD] */ 5986 uint64_t lboot : 10; /**< Last boot cause mask, resets only with dcok. 5987 5988 bit9 - Soft reset due to watchdog 5989 bit8 - Soft reset due to CIU_SOFT_RST write 5990 bit7 - Warm reset due to cntl0 link-down or 5991 hot-reset 5992 bit6 - Warm reset due to cntl1 link-down or 5993 hot-reset 5994 bit5 - Cntl1 reset due to PERST1_L pin 5995 bit4 - Cntl0 reset due to PERST0_L pin 5996 bit3 - Warm reset due to PERST1_L pin 5997 bit2 - Warm reset due to PERST0_L pin 5998 bit1 - Warm reset due to CHIP_RESET_L pin 5999 bit0 - Cold reset due to DCOK pin */ 6000 uint64_t rboot : 1; /**< Determines whether core 0 remains in reset after 6001 after chip cold/warm/soft reset. */ 6002 uint64_t rboot_pin : 1; /**< Read-only access to REMOTE_BOOT pin */ 6003#else 6004 uint64_t rboot_pin : 1; 6005 uint64_t rboot : 1; 6006 uint64_t lboot : 10; 6007 uint64_t qlm0_spd : 4; 6008 uint64_t qlm1_spd : 4; 6009 uint64_t qlm2_spd : 4; 6010 uint64_t pnr_mul : 6; 6011 uint64_t c_mul : 6; 6012 uint64_t qlm3_spd : 4; 6013 uint64_t qlm4_spd : 4; 6014 uint64_t reserved_44_47 : 4; 6015 uint64_t lboot_ext : 2; 6016 uint64_t reserved_50_57 : 8; 6017 uint64_t jt_tstmode : 1; 6018 uint64_t ckill_ppdis : 1; 6019 uint64_t romen : 1; 6020 uint64_t ejtagdis : 1; 6021 uint64_t jtcsrdis : 1; 6022 uint64_t chipkill : 1; 6023#endif 6024 } s; 6025 struct cvmx_mio_rst_boot_cn61xx { 6026#ifdef __BIG_ENDIAN_BITFIELD 6027 uint64_t chipkill : 1; /**< A 0->1 transition of CHIPKILL starts the CHIPKILL 6028 timer. When CHIPKILL=1 and the timer expires, 6029 internal chip reset is asserted forever until the 6030 next chip reset. The CHIPKILL timer can be 6031 stopped only by a chip (cold, warm, soft) reset. 6032 The length of the CHIPKILL timer is specified by 6033 MIO_RST_CKILL[TIMER]. */ 6034 uint64_t jtcsrdis : 1; /**< If JTCSRDIS=1, internal CSR access via JTAG TAP 6035 controller is disabled */ 6036 uint64_t ejtagdis : 1; /**< If EJTAGDIS=1, external EJTAG access is disabled */ 6037 uint64_t romen : 1; /**< If ROMEN=1, Authentik/eMMC boot ROM is visible 6038 in the boot bus address space. */ 6039 uint64_t ckill_ppdis : 1; /**< If CK_PPDIS=1, PPs other than 0 are disabled 6040 during a CHIPKILL. Writes have no effect when 6041 MIO_RST_BOOT[CHIPKILL]=1. */ 6042 uint64_t jt_tstmode : 1; /**< JTAG test mode */ 6043 uint64_t reserved_50_57 : 8; 6044 uint64_t lboot_ext : 2; /**< Reserved */ 6045 uint64_t reserved_36_47 : 12; 6046 uint64_t c_mul : 6; /**< Core clock multiplier: 6047 C_MUL = (core clk speed) / (ref clock speed) 6048 "ref clock speed" should always be 50MHz. 6049 If PLL_QLM_REF_CLK_EN=0, "ref clock" comes 6050 from PLL_REF_CLK pin. 6051 If PLL_QLM_REF_CLK_EN=1, "ref clock" is 6052 1/2 speed of QLMC_REF_CLK_* pins. */ 6053 uint64_t pnr_mul : 6; /**< Coprocessor clock multiplier: 6054 PNR_MUL = (coprocessor clk speed) / 6055 (ref clock speed) 6056 See C_MUL comments about ref clock. */ 6057 uint64_t qlm2_spd : 4; /**< QLM2_SPD, report MIO_QLM2_CFG[SPD] */ 6058 uint64_t qlm1_spd : 4; /**< QLM1_SPD, report MIO_QLM1_CFG[SPD] */ 6059 uint64_t qlm0_spd : 4; /**< QLM0_SPD, report MIO_QLM0_CFG[SPD] */ 6060 uint64_t lboot : 10; /**< Last boot cause mask, resets only with dcok. 6061 6062 bit9 - Soft reset due to watchdog 6063 bit8 - Soft reset due to CIU_SOFT_RST write 6064 bit7 - Warm reset due to cntl0 link-down or 6065 hot-reset 6066 bit6 - Warm reset due to cntl1 link-down or 6067 hot-reset 6068 bit5 - Cntl1 reset due to PERST1_L pin 6069 bit4 - Cntl0 reset due to PERST0_L pin 6070 bit3 - Warm reset due to PERST1_L pin 6071 bit2 - Warm reset due to PERST0_L pin 6072 bit1 - Warm reset due to CHIP_RESET_L pin 6073 bit0 - Cold reset due to DCOK pin */ 6074 uint64_t rboot : 1; /**< Determines whether core 0 remains in reset after 6075 after chip cold/warm/soft reset. */ 6076 uint64_t rboot_pin : 1; /**< Read-only access to REMOTE_BOOT pin */ 6077#else 6078 uint64_t rboot_pin : 1; 6079 uint64_t rboot : 1; 6080 uint64_t lboot : 10; 6081 uint64_t qlm0_spd : 4; 6082 uint64_t qlm1_spd : 4; 6083 uint64_t qlm2_spd : 4; 6084 uint64_t pnr_mul : 6; 6085 uint64_t c_mul : 6; 6086 uint64_t reserved_36_47 : 12; 6087 uint64_t lboot_ext : 2; 6088 uint64_t reserved_50_57 : 8; 6089 uint64_t jt_tstmode : 1; 6090 uint64_t ckill_ppdis : 1; 6091 uint64_t romen : 1; 6092 uint64_t ejtagdis : 1; 6093 uint64_t jtcsrdis : 1; 6094 uint64_t chipkill : 1; 6095#endif 6096 } cn61xx; 6097 struct cvmx_mio_rst_boot_cn63xx { 6098#ifdef __BIG_ENDIAN_BITFIELD 6099 uint64_t reserved_36_63 : 28; 6100 uint64_t c_mul : 6; /**< Core clock multiplier: 6101 C_MUL = (core clk speed) / (ref clock speed) 6102 "ref clock speed" should always be 50MHz. 6103 If PLL_QLM_REF_CLK_EN=0, "ref clock" comes 6104 from PLL_REF_CLK pin. 6105 If PLL_QLM_REF_CLK_EN=1, "ref clock" is 6106 1/2 speed of QLMC_REF_CLK_* pins. */ 6107 uint64_t pnr_mul : 6; /**< Coprocessor clock multiplier: 6108 PNR_MUL = (coprocessor clk speed) / 6109 (ref clock speed) 6110 See C_MUL comments about ref clock. */ 6111 uint64_t qlm2_spd : 4; /**< QLM2_SPD pins sampled at DCOK assertion */ 6112 uint64_t qlm1_spd : 4; /**< QLM1_SPD pins sampled at DCOK assertion */ 6113 uint64_t qlm0_spd : 4; /**< QLM0_SPD pins sampled at DCOK assertion */ 6114 uint64_t lboot : 10; /**< Last boot cause mask, resets only with dock. 6115 6116 bit9 - Soft reset due to watchdog 6117 bit8 - Soft reset due to CIU_SOFT_RST write 6118 bit7 - Warm reset due to cntl0 link-down or 6119 hot-reset 6120 bit6 - Warm reset due to cntl1 link-down or 6121 hot-reset 6122 bit5 - Cntl1 reset due to PERST1_L pin 6123 bit4 - Cntl0 reset due to PERST0_L pin 6124 bit3 - Warm reset due to PERST1_L pin 6125 bit2 - Warm reset due to PERST0_L pin 6126 bit1 - Warm reset due to CHIP_RESET_L pin 6127 bit0 - Cold reset due to DCOK pin */ 6128 uint64_t rboot : 1; /**< Determines whether core 0 remains in reset after 6129 after chip cold/warm/soft reset. */ 6130 uint64_t rboot_pin : 1; /**< Read-only access to REMOTE_BOOT pin */ 6131#else 6132 uint64_t rboot_pin : 1; 6133 uint64_t rboot : 1; 6134 uint64_t lboot : 10; 6135 uint64_t qlm0_spd : 4; 6136 uint64_t qlm1_spd : 4; 6137 uint64_t qlm2_spd : 4; 6138 uint64_t pnr_mul : 6; 6139 uint64_t c_mul : 6; 6140 uint64_t reserved_36_63 : 28; 6141#endif 6142 } cn63xx; 6143 struct cvmx_mio_rst_boot_cn63xx cn63xxp1; 6144 struct cvmx_mio_rst_boot_cn66xx { 6145#ifdef __BIG_ENDIAN_BITFIELD 6146 uint64_t chipkill : 1; /**< A 0->1 transition of CHIPKILL starts the CHIPKILL 6147 timer. When CHIPKILL=1 and the timer expires, 6148 internal chip reset is asserted forever until the 6149 next chip reset. The CHIPKILL timer can be 6150 stopped only by a chip (cold, warm, soft) reset. 6151 The length of the CHIPKILL timer is specified by 6152 MIO_RST_CKILL[TIMER]. */ 6153 uint64_t jtcsrdis : 1; /**< If JTCSRDIS=1, internal CSR access via JTAG TAP 6154 controller is disabled */ 6155 uint64_t ejtagdis : 1; /**< If EJTAGDIS=1, external EJTAG access is disabled */ 6156 uint64_t romen : 1; /**< If ROMEN=1, Authentik ROM is visible in the boot 6157 bus address space. */ 6158 uint64_t ckill_ppdis : 1; /**< If CK_PPDIS=1, PPs other than 0 are disabled 6159 during a CHIPKILL. Writes have no effect when 6160 MIO_RST_BOOT[CHIPKILL]=1. */ 6161 uint64_t reserved_50_58 : 9; 6162 uint64_t lboot_ext : 2; /**< Extended Last boot cause mask, resets only with 6163 dock. 6164 6165 bit1 - Warm reset due to cntl3 link-down or 6166 hot-reset 6167 bit0 - Warm reset due to cntl2 link-down or 6168 hot-reset */ 6169 uint64_t reserved_36_47 : 12; 6170 uint64_t c_mul : 6; /**< Core clock multiplier: 6171 C_MUL = (core clk speed) / (ref clock speed) 6172 "ref clock speed" should always be 50MHz. 6173 If PLL_QLM_REF_CLK_EN=0, "ref clock" comes 6174 from PLL_REF_CLK pin. 6175 If PLL_QLM_REF_CLK_EN=1, "ref clock" is 6176 1/2 speed of QLMC_REF_CLK_* pins. */ 6177 uint64_t pnr_mul : 6; /**< Coprocessor clock multiplier: 6178 PNR_MUL = (coprocessor clk speed) / 6179 (ref clock speed) 6180 See C_MUL comments about ref clock. */ 6181 uint64_t qlm2_spd : 4; /**< QLM2_SPD pins sampled at DCOK assertion */ 6182 uint64_t qlm1_spd : 4; /**< QLM1_SPD pins sampled at DCOK assertion */ 6183 uint64_t qlm0_spd : 4; /**< QLM0_SPD pins sampled at DCOK assertion */ 6184 uint64_t lboot : 10; /**< Last boot cause mask, resets only with dock. 6185 6186 bit9 - Soft reset due to watchdog 6187 bit8 - Soft reset due to CIU_SOFT_RST write 6188 bit7 - Warm reset due to cntl0 link-down or 6189 hot-reset 6190 bit6 - Warm reset due to cntl1 link-down or 6191 hot-reset 6192 bit5 - Cntl1 reset due to PERST1_L pin 6193 bit4 - Cntl0 reset due to PERST0_L pin 6194 bit3 - Warm reset due to PERST1_L pin 6195 bit2 - Warm reset due to PERST0_L pin 6196 bit1 - Warm reset due to CHIP_RESET_L pin 6197 bit0 - Cold reset due to DCOK pin */ 6198 uint64_t rboot : 1; /**< Determines whether core 0 remains in reset after 6199 after chip cold/warm/soft reset. */ 6200 uint64_t rboot_pin : 1; /**< Read-only access to REMOTE_BOOT pin */ 6201#else 6202 uint64_t rboot_pin : 1; 6203 uint64_t rboot : 1; 6204 uint64_t lboot : 10; 6205 uint64_t qlm0_spd : 4; 6206 uint64_t qlm1_spd : 4; 6207 uint64_t qlm2_spd : 4; 6208 uint64_t pnr_mul : 6; 6209 uint64_t c_mul : 6; 6210 uint64_t reserved_36_47 : 12; 6211 uint64_t lboot_ext : 2; 6212 uint64_t reserved_50_58 : 9; 6213 uint64_t ckill_ppdis : 1; 6214 uint64_t romen : 1; 6215 uint64_t ejtagdis : 1; 6216 uint64_t jtcsrdis : 1; 6217 uint64_t chipkill : 1; 6218#endif 6219 } cn66xx; 6220 struct cvmx_mio_rst_boot_cn68xx { 6221#ifdef __BIG_ENDIAN_BITFIELD 6222 uint64_t reserved_59_63 : 5; 6223 uint64_t jt_tstmode : 1; /**< JTAG test mode */ 6224 uint64_t reserved_44_57 : 14; 6225 uint64_t qlm4_spd : 4; /**< QLM4_SPD pins sampled at DCOK assertion */ 6226 uint64_t qlm3_spd : 4; /**< QLM3_SPD pins sampled at DCOK assertion */ 6227 uint64_t c_mul : 6; /**< Core clock multiplier: 6228 C_MUL = (core clk speed) / (ref clock speed) 6229 "ref clock" is PLL_REF_CLK pin, which should 6230 always be 50 MHz. */ 6231 uint64_t pnr_mul : 6; /**< Coprocessor clock multiplier: 6232 PNR_MUL = (coprocessor clk speed) 6233 (ref clock speed) 6234 See C_MUL comments about ref clock. */ 6235 uint64_t qlm2_spd : 4; /**< QLM2_SPD pins sampled at DCOK assertion */ 6236 uint64_t qlm1_spd : 4; /**< QLM1_SPD pins sampled at DCOK assertion */ 6237 uint64_t qlm0_spd : 4; /**< QLM0_SPD pins sampled at DCOK assertion */ 6238 uint64_t lboot : 10; /**< Last boot cause mask, resets only with dock. 6239 6240 bit9 - Soft reset due to watchdog 6241 bit8 - Soft reset due to CIU_SOFT_RST write 6242 bit7 - Warm reset due to cntl0 link-down or 6243 hot-reset 6244 bit6 - Warm reset due to cntl1 link-down or 6245 hot-reset 6246 bit5 - Cntl1 reset due to PERST1_L pin 6247 bit4 - Cntl0 reset due to PERST0_L pin 6248 bit3 - Warm reset due to PERST1_L pin 6249 bit2 - Warm reset due to PERST0_L pin 6250 bit1 - Warm reset due to CHIP_RESET_L pin 6251 bit0 - Cold reset due to DCOK pin */ 6252 uint64_t rboot : 1; /**< Determines whether core 0 remains in reset after 6253 after chip cold/warm/soft reset. */ 6254 uint64_t rboot_pin : 1; /**< Read-only access to REMOTE_BOOT pin */ 6255#else 6256 uint64_t rboot_pin : 1; 6257 uint64_t rboot : 1; 6258 uint64_t lboot : 10; 6259 uint64_t qlm0_spd : 4; 6260 uint64_t qlm1_spd : 4; 6261 uint64_t qlm2_spd : 4; 6262 uint64_t pnr_mul : 6; 6263 uint64_t c_mul : 6; 6264 uint64_t qlm3_spd : 4; 6265 uint64_t qlm4_spd : 4; 6266 uint64_t reserved_44_57 : 14; 6267 uint64_t jt_tstmode : 1; 6268 uint64_t reserved_59_63 : 5; 6269#endif 6270 } cn68xx; 6271 struct cvmx_mio_rst_boot_cn68xxp1 { 6272#ifdef __BIG_ENDIAN_BITFIELD 6273 uint64_t reserved_44_63 : 20; 6274 uint64_t qlm4_spd : 4; /**< QLM4_SPD pins sampled at DCOK assertion */ 6275 uint64_t qlm3_spd : 4; /**< QLM3_SPD pins sampled at DCOK assertion */ 6276 uint64_t c_mul : 6; /**< Core clock multiplier: 6277 C_MUL = (core clk speed) / (ref clock speed) 6278 "ref clock" is PLL_REF_CLK pin, which should 6279 always be 50 MHz. */ 6280 uint64_t pnr_mul : 6; /**< Coprocessor clock multiplier: 6281 PNR_MUL = (coprocessor clk speed) 6282 (ref clock speed) 6283 See C_MUL comments about ref clock. */ 6284 uint64_t qlm2_spd : 4; /**< QLM2_SPD pins sampled at DCOK assertion */ 6285 uint64_t qlm1_spd : 4; /**< QLM1_SPD pins sampled at DCOK assertion */ 6286 uint64_t qlm0_spd : 4; /**< QLM0_SPD pins sampled at DCOK assertion */ 6287 uint64_t lboot : 10; /**< Last boot cause mask, resets only with dock. 6288 6289 bit9 - Soft reset due to watchdog 6290 bit8 - Soft reset due to CIU_SOFT_RST write 6291 bit7 - Warm reset due to cntl0 link-down or 6292 hot-reset 6293 bit6 - Warm reset due to cntl1 link-down or 6294 hot-reset 6295 bit5 - Cntl1 reset due to PERST1_L pin 6296 bit4 - Cntl0 reset due to PERST0_L pin 6297 bit3 - Warm reset due to PERST1_L pin 6298 bit2 - Warm reset due to PERST0_L pin 6299 bit1 - Warm reset due to CHIP_RESET_L pin 6300 bit0 - Cold reset due to DCOK pin */ 6301 uint64_t rboot : 1; /**< Determines whether core 0 remains in reset after 6302 after chip cold/warm/soft reset. */ 6303 uint64_t rboot_pin : 1; /**< Read-only access to REMOTE_BOOT pin */ 6304#else 6305 uint64_t rboot_pin : 1; 6306 uint64_t rboot : 1; 6307 uint64_t lboot : 10; 6308 uint64_t qlm0_spd : 4; 6309 uint64_t qlm1_spd : 4; 6310 uint64_t qlm2_spd : 4; 6311 uint64_t pnr_mul : 6; 6312 uint64_t c_mul : 6; 6313 uint64_t qlm3_spd : 4; 6314 uint64_t qlm4_spd : 4; 6315 uint64_t reserved_44_63 : 20; 6316#endif 6317 } cn68xxp1; 6318 struct cvmx_mio_rst_boot_cn61xx cnf71xx; 6319}; 6320typedef union cvmx_mio_rst_boot cvmx_mio_rst_boot_t; 6321 6322/** 6323 * cvmx_mio_rst_cfg 6324 * 6325 * Notes: 6326 * Cold reset will always performs a full bist. 6327 * 6328 */ 6329union cvmx_mio_rst_cfg { 6330 uint64_t u64; 6331 struct cvmx_mio_rst_cfg_s { 6332#ifdef __BIG_ENDIAN_BITFIELD 6333 uint64_t reserved_3_63 : 61; 6334 uint64_t cntl_clr_bist : 1; /**< Peform clear bist during cntl only reset, 6335 instead of a full bist. A warm/soft reset will 6336 not change this field. */ 6337 uint64_t warm_clr_bist : 1; /**< Peform clear bist during warm reset, instead 6338 of a full bist. A warm/soft reset will not 6339 change this field. */ 6340 uint64_t soft_clr_bist : 1; /**< Peform clear bist during soft reset, instead 6341 of a full bist. A warm/soft reset will not 6342 change this field. */ 6343#else 6344 uint64_t soft_clr_bist : 1; 6345 uint64_t warm_clr_bist : 1; 6346 uint64_t cntl_clr_bist : 1; 6347 uint64_t reserved_3_63 : 61; 6348#endif 6349 } s; 6350 struct cvmx_mio_rst_cfg_cn61xx { 6351#ifdef __BIG_ENDIAN_BITFIELD 6352 uint64_t bist_delay : 58; /**< Reserved */ 6353 uint64_t reserved_3_5 : 3; 6354 uint64_t cntl_clr_bist : 1; /**< Peform clear bist during cntl only reset, 6355 instead of a full bist. A warm/soft reset will 6356 not change this field. */ 6357 uint64_t warm_clr_bist : 1; /**< Peform clear bist during warm reset, instead 6358 of a full bist. A warm/soft reset will not 6359 change this field. */ 6360 uint64_t soft_clr_bist : 1; /**< Peform clear bist during soft reset, instead 6361 of a full bist. A warm/soft reset will not 6362 change this field. */ 6363#else 6364 uint64_t soft_clr_bist : 1; 6365 uint64_t warm_clr_bist : 1; 6366 uint64_t cntl_clr_bist : 1; 6367 uint64_t reserved_3_5 : 3; 6368 uint64_t bist_delay : 58; 6369#endif 6370 } cn61xx; 6371 struct cvmx_mio_rst_cfg_cn61xx cn63xx; 6372 struct cvmx_mio_rst_cfg_cn63xxp1 { 6373#ifdef __BIG_ENDIAN_BITFIELD 6374 uint64_t bist_delay : 58; /**< Reserved */ 6375 uint64_t reserved_2_5 : 4; 6376 uint64_t warm_clr_bist : 1; /**< Peform clear bist during warm reset, instead 6377 of a full bist. A warm/soft reset will not 6378 change this field. */ 6379 uint64_t soft_clr_bist : 1; /**< Peform clear bist during soft reset, instead 6380 of a full bist. A warm/soft reset will not 6381 change this field. */ 6382#else 6383 uint64_t soft_clr_bist : 1; 6384 uint64_t warm_clr_bist : 1; 6385 uint64_t reserved_2_5 : 4; 6386 uint64_t bist_delay : 58; 6387#endif 6388 } cn63xxp1; 6389 struct cvmx_mio_rst_cfg_cn61xx cn66xx; 6390 struct cvmx_mio_rst_cfg_cn68xx { 6391#ifdef __BIG_ENDIAN_BITFIELD 6392 uint64_t bist_delay : 56; /**< Reserved */ 6393 uint64_t reserved_3_7 : 5; 6394 uint64_t cntl_clr_bist : 1; /**< Peform clear bist during cntl only reset, 6395 instead of a full bist. A warm/soft reset will 6396 not change this field. */ 6397 uint64_t warm_clr_bist : 1; /**< Peform clear bist during warm reset, instead 6398 of a full bist. A warm/soft reset will not 6399 change this field. */ 6400 uint64_t soft_clr_bist : 1; /**< Peform clear bist during soft reset, instead 6401 of a full bist. A warm/soft reset will not 6402 change this field. */ 6403#else 6404 uint64_t soft_clr_bist : 1; 6405 uint64_t warm_clr_bist : 1; 6406 uint64_t cntl_clr_bist : 1; 6407 uint64_t reserved_3_7 : 5; 6408 uint64_t bist_delay : 56; 6409#endif 6410 } cn68xx; 6411 struct cvmx_mio_rst_cfg_cn68xx cn68xxp1; 6412 struct cvmx_mio_rst_cfg_cn61xx cnf71xx; 6413}; 6414typedef union cvmx_mio_rst_cfg cvmx_mio_rst_cfg_t; 6415 6416/** 6417 * cvmx_mio_rst_ckill 6418 * 6419 * MIO_RST_CKILL = MIO Chipkill Timer Register 6420 * 6421 */ 6422union cvmx_mio_rst_ckill { 6423 uint64_t u64; 6424 struct cvmx_mio_rst_ckill_s { 6425#ifdef __BIG_ENDIAN_BITFIELD 6426 uint64_t reserved_47_63 : 17; 6427 uint64_t timer : 47; /**< CHIPKILL timer measured in SCLKs. Reads return 6428 the current CHIPKILL timer. Writes have no 6429 effect when MIO_RST_BOOT[CHIPKILL]=1. */ 6430#else 6431 uint64_t timer : 47; 6432 uint64_t reserved_47_63 : 17; 6433#endif 6434 } s; 6435 struct cvmx_mio_rst_ckill_s cn61xx; 6436 struct cvmx_mio_rst_ckill_s cn66xx; 6437 struct cvmx_mio_rst_ckill_s cnf71xx; 6438}; 6439typedef union cvmx_mio_rst_ckill cvmx_mio_rst_ckill_t; 6440 6441/** 6442 * cvmx_mio_rst_cntl# 6443 * 6444 * Notes: 6445 * GEN1_Only mode is enabled for PEM0 when QLM1_SPD[0] is set or when sclk < 550Mhz. 6446 * GEN1_Only mode is enabled for PEM1 when QLM1_SPD[1] is set or when sclk < 550Mhz. 6447 */ 6448union cvmx_mio_rst_cntlx { 6449 uint64_t u64; 6450 struct cvmx_mio_rst_cntlx_s { 6451#ifdef __BIG_ENDIAN_BITFIELD 6452 uint64_t reserved_13_63 : 51; 6453 uint64_t in_rev_ln : 1; /**< RO access to corresponding pin PCIE*_REV_LANES 6454 which is used for initial value for REV_LANES 6455 For INT0/CNTL0: pin PCIE0_REV_LANES 6456 For INT1/CNTL1: always zero as no PCIE1 pin */ 6457 uint64_t rev_lanes : 1; /**< Reverse the lanes for INT*. 6458 A warm/soft reset will not change this field. 6459 On cold reset, this field is initialized to 6460 IN_REVLANE value. 6461 When QLM1_CFG=1, INT0(PEM0) REV_LANES internal 6462 setting will be always forced to '0', INT1(PEM1) 6463 will be forced to '1' regardless CSR value. */ 6464 uint64_t gen1_only : 1; /**< Disable PCIE GEN2 Capability. This bit is 6465 always unpredictable whenever the controller 6466 is not attached to any SerDes lanes, and is 6467 otherwise always set when SCLK is slower than 6468 550Mhz. 6469 The MIO_RST_CNTL*[GEN1_ONLY] value is based on 6470 the MIO_QLM1_CFG[QLM_SPD] value. */ 6471 uint64_t prst_link : 1; /**< Controls whether corresponding controller 6472 link-down or hot-reset causes the assertion of 6473 CIU_SOFT_PRST*[SOFT_PRST] 6474 6475 A warm/soft reset will not change this field. 6476 On cold reset, this field is initialized to 0 */ 6477 uint64_t rst_done : 1; /**< Read-only access to controller reset status 6478 6479 RESET_DONE is always zero (i.e. the controller 6480 is held in reset) when: 6481 - CIU_SOFT_PRST*[SOFT_PRST]=1, or 6482 - RST_RCV==1 and PERST*_L pin is asserted */ 6483 uint64_t rst_link : 1; /**< Controls whether corresponding controller 6484 link-down or hot-reset causes a warm chip reset 6485 On cold reset, this field is initialized as 6486 follows: 6487 0 = when corresponding HOST_MODE=1 6488 1 = when corresponding HOST_MODE=0 6489 6490 Note that a link-down or hot-reset event can 6491 never cause a warm chip reset when the 6492 controller is in reset (i.e. can never cause a 6493 warm reset when RST_DONE==0). */ 6494 uint64_t host_mode : 1; /**< RO access to corresponding strap PCIE*_HOST_MODE 6495 For CNTL1/INT1, HOST_MODE is always '1' because 6496 there is no PCIE1_HOST_MODE pin. */ 6497 uint64_t prtmode : 2; /**< Port mode 6498 0 = port is EP mode 6499 1 = port is RC mode 6500 2,3 = Reserved 6501 A warm/soft reset will not change this field. 6502 On cold reset, this field is initialized as 6503 HOST_MODE (corresponding strap PCIE*_HOST_MODE) */ 6504 uint64_t rst_drv : 1; /**< Controls whether corresponding PERST*_L chip pin 6505 is driven by the OCTEON. A warm/soft reset 6506 will not change this field. On cold reset, 6507 this field is initialized as follows: 6508 0 = when corresponding HOST_MODE=0 6509 1 = when corresponding HOST_MODE=1 6510 6511 When set, OCTEON drives the corresponding 6512 PERST*_L pin. Otherwise, OCTEON does not drive 6513 the corresponding PERST*_L pin. */ 6514 uint64_t rst_rcv : 1; /**< Controls whether corresponding PERST*_L chip pin 6515 is recieved by OCTEON. A warm/soft reset 6516 will not change this field. On cold reset, 6517 this field is initialized as follows: 6518 0 = when corresponding HOST_MODE=1 6519 1 = when corresponding HOST_MODE=0 6520 6521 When RST_RCV==1, the PERST*_L value is 6522 received and may be used to reset the 6523 controller and (optionally, based on RST_CHIP) 6524 warm reset the chip. 6525 6526 When RST_RCV==1 (and RST_CHIP=0), 6527 MIO_RST_INT[PERST*] gets set when the PERST*_L 6528 pin asserts. (This interrupt can alert SW 6529 whenever the external reset pin initiates a 6530 controller reset sequence.) 6531 6532 RST_VAL gives the PERST*_L pin value when 6533 RST_RCV==1. 6534 6535 When RST_RCV==0, the PERST*_L pin value is 6536 ignored. */ 6537 uint64_t rst_chip : 1; /**< Controls whether corresponding PERST*_L chip 6538 pin causes a chip warm reset like CHIP_RESET_L. 6539 A warm/soft reset will not change this field. 6540 On cold reset, this field is initialized to 0. 6541 6542 RST_CHIP is not used when RST_RCV==0. 6543 6544 When RST_RCV==0, RST_CHIP is ignored. 6545 6546 When RST_RCV==1, RST_CHIP==1, and PERST*_L 6547 asserts, a chip warm reset will be generated. */ 6548 uint64_t rst_val : 1; /**< Read-only access to corresponding PERST*_L pin 6549 Unpredictable when RST_RCV==0. Reads as 1 when 6550 RST_RCV==1 and the PERST*_L pin is asserted. 6551 Reads as 0 when RST_RCV==1 and the PERST*_L 6552 pin is not asserted. */ 6553#else 6554 uint64_t rst_val : 1; 6555 uint64_t rst_chip : 1; 6556 uint64_t rst_rcv : 1; 6557 uint64_t rst_drv : 1; 6558 uint64_t prtmode : 2; 6559 uint64_t host_mode : 1; 6560 uint64_t rst_link : 1; 6561 uint64_t rst_done : 1; 6562 uint64_t prst_link : 1; 6563 uint64_t gen1_only : 1; 6564 uint64_t rev_lanes : 1; 6565 uint64_t in_rev_ln : 1; 6566 uint64_t reserved_13_63 : 51; 6567#endif 6568 } s; 6569 struct cvmx_mio_rst_cntlx_s cn61xx; 6570 struct cvmx_mio_rst_cntlx_cn66xx { 6571#ifdef __BIG_ENDIAN_BITFIELD 6572 uint64_t reserved_10_63 : 54; 6573 uint64_t prst_link : 1; /**< Controls whether corresponding controller 6574 link-down or hot-reset causes the assertion of 6575 CIU_SOFT_PRST*[SOFT_PRST] 6576 6577 A warm/soft reset will not change this field. 6578 On cold reset, this field is initialized to 0 */ 6579 uint64_t rst_done : 1; /**< Read-only access to controller reset status 6580 6581 RESET_DONE is always zero (i.e. the controller 6582 is held in reset) when: 6583 - CIU_SOFT_PRST*[SOFT_PRST]=1, or 6584 - RST_RCV==1 and PERST*_L pin is asserted */ 6585 uint64_t rst_link : 1; /**< Controls whether corresponding controller 6586 link-down or hot-reset causes a warm chip reset 6587 On cold reset, this field is initialized as 6588 follows: 6589 0 = when corresponding strap QLM*_HOST_MODE=1 6590 1 = when corresponding strap QLM*_HOST_MODE=0 6591 6592 For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field 6593 is initialized to 1 on cold reset. 6594 6595 Note that a link-down or hot-reset event can 6596 never cause a warm chip reset when the 6597 controller is in reset (i.e. can never cause a 6598 warm reset when RST_DONE==0). */ 6599 uint64_t host_mode : 1; /**< RO access to corresponding strap QLM*_HOST_MODE 6600 6601 For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field 6602 is reserved/RAZ. 6603 6604 QLM0_HOST_MODE corresponds to PCIe0/sRIO0 6605 QLM1_HOST_MODE corresponds to PCIe1/sRIO1 */ 6606 uint64_t prtmode : 2; /**< Port mode 6607 0 = port is EP mode 6608 1 = port is RC mode 6609 2,3 = Reserved 6610 A warm/soft reset will not change this field. 6611 On cold reset, this field is initialized as 6612 follows: 6613 0 = when corresponding strap QLM*_HOST_MODE=0 6614 1 = when corresponding strap QLM*_HOST_MODE=1 6615 6616 For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field 6617 is initialized to 0 on cold reset. */ 6618 uint64_t rst_drv : 1; /**< Controls whether corresponding PERST*_L chip pin 6619 is driven by the OCTEON. A warm/soft reset 6620 will not change this field. On cold reset, 6621 this field is initialized as follows: 6622 0 = when corresponding strap QLM*_HOST_MODE=0 6623 1 = when corresponding strap QLM*_HOST_MODE=1 6624 6625 When set, OCTEON drives the corresponding 6626 PERST*_L pin. Otherwise, OCTEON does not drive 6627 the corresponding PERST*_L pin. 6628 6629 For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field 6630 is reserved/RAZ. */ 6631 uint64_t rst_rcv : 1; /**< Controls whether corresponding PERST*_L chip pin 6632 is recieved by OCTEON. A warm/soft reset 6633 will not change this field. On cold reset, 6634 this field is initialized as follows: 6635 0 = when corresponding strap QLM*_HOST_MODE=1 6636 1 = when corresponding strap QLM*_HOST_MODE=0 6637 6638 When RST_RCV==1, the PERST*_L value is 6639 received and may be used to reset the 6640 controller and (optionally, based on RST_CHIP) 6641 warm reset the chip. 6642 6643 When RST_RCV==1 (and RST_CHIP=0), 6644 MIO_RST_INT[PERST*] gets set when the PERST*_L 6645 pin asserts. (This interrupt can alert SW 6646 whenever the external reset pin initiates a 6647 controller reset sequence.) 6648 6649 RST_VAL gives the PERST*_L pin value when 6650 RST_RCV==1. 6651 6652 When RST_RCV==0, the PERST*_L pin value is 6653 ignored. 6654 6655 For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field 6656 is reserved/RAZ. */ 6657 uint64_t rst_chip : 1; /**< Controls whether corresponding PERST*_L chip 6658 pin causes a chip warm reset like CHIP_RESET_L. 6659 A warm/soft reset will not change this field. 6660 On cold reset, this field is initialized to 0. 6661 6662 RST_CHIP is not used when RST_RCV==0. 6663 6664 When RST_RCV==0, RST_CHIP is ignored. 6665 6666 When RST_RCV==1, RST_CHIP==1, and PERST*_L 6667 asserts, a chip warm reset will be generated. 6668 6669 For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field 6670 is reserved/RAZ. */ 6671 uint64_t rst_val : 1; /**< Read-only access to corresponding PERST*_L pin 6672 Unpredictable when RST_RCV==0. Reads as 1 when 6673 RST_RCV==1 and the PERST*_L pin is asserted. 6674 Reads as 0 when RST_RCV==1 and the PERST*_L 6675 pin is not asserted. 6676 6677 For MIO_RST_CNTL2 and MIO_RST_CNTL3, this field 6678 is reserved/RAZ. */ 6679#else 6680 uint64_t rst_val : 1; 6681 uint64_t rst_chip : 1; 6682 uint64_t rst_rcv : 1; 6683 uint64_t rst_drv : 1; 6684 uint64_t prtmode : 2; 6685 uint64_t host_mode : 1; 6686 uint64_t rst_link : 1; 6687 uint64_t rst_done : 1; 6688 uint64_t prst_link : 1; 6689 uint64_t reserved_10_63 : 54; 6690#endif 6691 } cn66xx; 6692 struct cvmx_mio_rst_cntlx_cn66xx cn68xx; 6693 struct cvmx_mio_rst_cntlx_s cnf71xx; 6694}; 6695typedef union cvmx_mio_rst_cntlx cvmx_mio_rst_cntlx_t; 6696 6697/** 6698 * cvmx_mio_rst_ctl# 6699 * 6700 * Notes: 6701 * GEN1_Only mode is enabled for PEM0 when QLM1_SPD[0] is set or when sclk < 550Mhz. 6702 * GEN1_Only mode is enabled for PEM1 when QLM1_SPD[1] is set or when sclk < 550Mhz. 6703 */ 6704union cvmx_mio_rst_ctlx { 6705 uint64_t u64; 6706 struct cvmx_mio_rst_ctlx_s { 6707#ifdef __BIG_ENDIAN_BITFIELD 6708 uint64_t reserved_13_63 : 51; 6709 uint64_t in_rev_ln : 1; /**< RO access to corresponding pin PCIE*_REV_LANES 6710 which is used for initial value for REV_LANES 6711 For INT0/CNTL0: pin PCIE0_REV_LANES 6712 For INT1/CNTL1: always zero as no PCIE1 pin */ 6713 uint64_t rev_lanes : 1; /**< Reverse the lanes for INT*. 6714 A warm/soft reset will not change this field. 6715 On cold reset, this field is initialized to 6716 IN_REVLANE value. 6717 When QLM1_CFG=1, INT0(PEM0) REV_LANES internal 6718 setting will be always forced to '0', INT1(PEM1) 6719 will be forced to '1' regardless CSR value. */ 6720 uint64_t gen1_only : 1; /**< Disable PCIE GEN2 Capability. This bit is 6721 always unpredictable whenever the controller 6722 is not attached to any SerDes lanes, and is 6723 otherwise always set when SCLK is slower than 6724 550Mhz. 6725 The MIO_RST_CNTL*[GEN1_ONLY] value is based on 6726 the MIO_QLM1_CFG[QLM_SPD] value. */ 6727 uint64_t prst_link : 1; /**< Controls whether corresponding controller 6728 link-down or hot-reset causes the assertion of 6729 CIU_SOFT_PRST*[SOFT_PRST] 6730 6731 A warm/soft reset will not change this field. 6732 On cold reset, this field is initialized to 0 */ 6733 uint64_t rst_done : 1; /**< Read-only access to controller reset status 6734 6735 RESET_DONE is always zero (i.e. the controller 6736 is held in reset) when: 6737 - CIU_SOFT_PRST*[SOFT_PRST]=1, or 6738 - RST_RCV==1 and PERST*_L pin is asserted */ 6739 uint64_t rst_link : 1; /**< Controls whether corresponding controller 6740 link-down or hot-reset causes a warm chip reset 6741 On cold reset, this field is initialized as 6742 follows: 6743 0 = when corresponding HOST_MODE=1 6744 1 = when corresponding HOST_MODE=0 6745 6746 Note that a link-down or hot-reset event can 6747 never cause a warm chip reset when the 6748 controller is in reset (i.e. can never cause a 6749 warm reset when RST_DONE==0). */ 6750 uint64_t host_mode : 1; /**< RO access to corresponding strap PCIE*_HOST_MODE 6751 For CNTL1/INT1, HOST_MODE is always '1' because 6752 there is no PCIE1_HOST_MODE pin. */ 6753 uint64_t prtmode : 2; /**< Port mode 6754 0 = port is EP mode 6755 1 = port is RC mode 6756 2,3 = Reserved 6757 A warm/soft reset will not change this field. 6758 On cold reset, this field is initialized as 6759 HOST_MODE (corresponding strap PCIE*_HOST_MODE) */ 6760 uint64_t rst_drv : 1; /**< Controls whether corresponding PERST*_L chip pin 6761 is driven by the OCTEON. A warm/soft reset 6762 will not change this field. On cold reset, 6763 this field is initialized as follows: 6764 0 = when corresponding HOST_MODE=0 6765 1 = when corresponding HOST_MODE=1 6766 6767 When set, OCTEON drives the corresponding 6768 PERST*_L pin. Otherwise, OCTEON does not drive 6769 the corresponding PERST*_L pin. */ 6770 uint64_t rst_rcv : 1; /**< Controls whether corresponding PERST*_L chip pin 6771 is recieved by OCTEON. A warm/soft reset 6772 will not change this field. On cold reset, 6773 this field is initialized as follows: 6774 0 = when corresponding HOST_MODE=1 6775 1 = when corresponding HOST_MODE=0 6776 6777 When RST_RCV==1, the PERST*_L value is 6778 received and may be used to reset the 6779 controller and (optionally, based on RST_CHIP) 6780 warm reset the chip. 6781 6782 When RST_RCV==1 (and RST_CHIP=0), 6783 MIO_RST_INT[PERST*] gets set when the PERST*_L 6784 pin asserts. (This interrupt can alert SW 6785 whenever the external reset pin initiates a 6786 controller reset sequence.) 6787 6788 RST_VAL gives the PERST*_L pin value when 6789 RST_RCV==1. 6790 6791 When RST_RCV==0, the PERST*_L pin value is 6792 ignored. */ 6793 uint64_t rst_chip : 1; /**< Controls whether corresponding PERST*_L chip 6794 pin causes a chip warm reset like CHIP_RESET_L. 6795 A warm/soft reset will not change this field. 6796 On cold reset, this field is initialized to 0. 6797 6798 RST_CHIP is not used when RST_RCV==0. 6799 6800 When RST_RCV==0, RST_CHIP is ignored. 6801 6802 When RST_RCV==1, RST_CHIP==1, and PERST*_L 6803 asserts, a chip warm reset will be generated. */ 6804 uint64_t rst_val : 1; /**< Read-only access to corresponding PERST*_L pin 6805 Unpredictable when RST_RCV==0. Reads as 1 when 6806 RST_RCV==1 and the PERST*_L pin is asserted. 6807 Reads as 0 when RST_RCV==1 and the PERST*_L 6808 pin is not asserted. */ 6809#else 6810 uint64_t rst_val : 1; 6811 uint64_t rst_chip : 1; 6812 uint64_t rst_rcv : 1; 6813 uint64_t rst_drv : 1; 6814 uint64_t prtmode : 2; 6815 uint64_t host_mode : 1; 6816 uint64_t rst_link : 1; 6817 uint64_t rst_done : 1; 6818 uint64_t prst_link : 1; 6819 uint64_t gen1_only : 1; 6820 uint64_t rev_lanes : 1; 6821 uint64_t in_rev_ln : 1; 6822 uint64_t reserved_13_63 : 51; 6823#endif 6824 } s; 6825 struct cvmx_mio_rst_ctlx_s cn61xx; 6826 struct cvmx_mio_rst_ctlx_cn63xx { 6827#ifdef __BIG_ENDIAN_BITFIELD 6828 uint64_t reserved_10_63 : 54; 6829 uint64_t prst_link : 1; /**< Controls whether corresponding controller 6830 link-down or hot-reset causes the assertion of 6831 CIU_SOFT_PRST*[SOFT_PRST] 6832 6833 A warm/soft reset will not change this field. 6834 On cold reset, this field is initialized to 0 6835 6836 ***NOTE: Added in pass 2.0 */ 6837 uint64_t rst_done : 1; /**< Read-only access to controller reset status 6838 6839 RESET_DONE is always zero (i.e. the controller 6840 is held in reset) when: 6841 - CIU_SOFT_PRST*[SOFT_PRST]=1, or 6842 - RST_RCV==1 and PERST*_L pin is asserted */ 6843 uint64_t rst_link : 1; /**< Controls whether corresponding controller 6844 link-down or hot-reset causes a warm chip reset 6845 On cold reset, this field is initialized as 6846 follows: 6847 0 = when corresponding strap QLM*_HOST_MODE=1 6848 1 = when corresponding strap QLM*_HOST_MODE=0 6849 6850 Note that a link-down or hot-reset event can 6851 never cause a warm chip reset when the 6852 controller is in reset (i.e. can never cause a 6853 warm reset when RST_DONE==0). */ 6854 uint64_t host_mode : 1; /**< RO access to corresponding strap QLM*_HOST_MODE */ 6855 uint64_t prtmode : 2; /**< Port mode 6856 0 = port is EP mode 6857 1 = port is RC mode 6858 2,3 = Reserved 6859 A warm/soft reset will not change this field. 6860 On cold reset, this field is initialized as 6861 follows: 6862 0 = when corresponding strap QLM*_HOST_MODE=0 6863 1 = when corresponding strap QLM*_HOST_MODE=1 */ 6864 uint64_t rst_drv : 1; /**< Controls whether corresponding PERST*_L chip pin 6865 is driven by the OCTEON. A warm/soft reset 6866 will not change this field. On cold reset, 6867 this field is initialized as follows: 6868 0 = when corresponding strap QLM*_HOST_MODE=0 6869 1 = when corresponding strap QLM*_HOST_MODE=1 6870 6871 When set, OCTEON drives the corresponding 6872 PERST*_L pin. Otherwise, OCTEON does not drive 6873 the corresponding PERST*_L pin. */ 6874 uint64_t rst_rcv : 1; /**< Controls whether corresponding PERST*_L chip pin 6875 is recieved by OCTEON. A warm/soft reset 6876 will not change this field. On cold reset, 6877 this field is initialized as follows: 6878 0 = when corresponding strap QLM*_HOST_MODE=1 6879 1 = when corresponding strap QLM*_HOST_MODE=0 6880 6881 When RST_RCV==1, the PERST*_L value is 6882 received and may be used to reset the 6883 controller and (optionally, based on RST_CHIP) 6884 warm reset the chip. 6885 6886 When RST_RCV==1 (and RST_CHIP=0), 6887 MIO_RST_INT[PERST*] gets set when the PERST*_L 6888 pin asserts. (This interrupt can alert SW 6889 whenever the external reset pin initiates a 6890 controller reset sequence.) 6891 6892 RST_VAL gives the PERST*_L pin value when 6893 RST_RCV==1. 6894 6895 When RST_RCV==0, the PERST*_L pin value is 6896 ignored. */ 6897 uint64_t rst_chip : 1; /**< Controls whether corresponding PERST*_L chip 6898 pin causes a chip warm reset like CHIP_RESET_L. 6899 A warm/soft reset will not change this field. 6900 On cold reset, this field is initialized to 0. 6901 6902 RST_CHIP is not used when RST_RCV==0. 6903 6904 When RST_RCV==0, RST_CHIP is ignored. 6905 6906 When RST_RCV==1, RST_CHIP==1, and PERST*_L 6907 asserts, a chip warm reset will be generated. */ 6908 uint64_t rst_val : 1; /**< Read-only access to corresponding PERST*_L pin 6909 Unpredictable when RST_RCV==0. Reads as 1 when 6910 RST_RCV==1 and the PERST*_L pin is asserted. 6911 Reads as 0 when RST_RCV==1 and the PERST*_L 6912 pin is not asserted. */ 6913#else 6914 uint64_t rst_val : 1; 6915 uint64_t rst_chip : 1; 6916 uint64_t rst_rcv : 1; 6917 uint64_t rst_drv : 1; 6918 uint64_t prtmode : 2; 6919 uint64_t host_mode : 1; 6920 uint64_t rst_link : 1; 6921 uint64_t rst_done : 1; 6922 uint64_t prst_link : 1; 6923 uint64_t reserved_10_63 : 54; 6924#endif 6925 } cn63xx; 6926 struct cvmx_mio_rst_ctlx_cn63xxp1 { 6927#ifdef __BIG_ENDIAN_BITFIELD 6928 uint64_t reserved_9_63 : 55; 6929 uint64_t rst_done : 1; /**< Read-only access to controller reset status 6930 6931 RESET_DONE is always zero (i.e. the controller 6932 is held in reset) when: 6933 - CIU_SOFT_PRST*[SOFT_PRST]=1, or 6934 - RST_RCV==1 and PERST*_L pin is asserted */ 6935 uint64_t rst_link : 1; /**< Controls whether corresponding controller 6936 link-down or hot-reset causes a warm chip reset 6937 On cold reset, this field is initialized as 6938 follows: 6939 0 = when corresponding strap QLM*_HOST_MODE=1 6940 1 = when corresponding strap QLM*_HOST_MODE=0 6941 6942 Note that a link-down or hot-reset event can 6943 never cause a warm chip reset when the 6944 controller is in reset (i.e. can never cause a 6945 warm reset when RST_DONE==0). */ 6946 uint64_t host_mode : 1; /**< RO access to corresponding strap QLM*_HOST_MODE */ 6947 uint64_t prtmode : 2; /**< Port mode 6948 0 = port is EP mode 6949 1 = port is RC mode 6950 2,3 = Reserved 6951 A warm/soft reset will not change this field. 6952 On cold reset, this field is initialized as 6953 follows: 6954 0 = when corresponding strap QLM*_HOST_MODE=0 6955 1 = when corresponding strap QLM*_HOST_MODE=1 */ 6956 uint64_t rst_drv : 1; /**< Controls whether corresponding PERST*_L chip pin 6957 is driven by the OCTEON. A warm/soft reset 6958 will not change this field. On cold reset, 6959 this field is initialized as follows: 6960 0 = when corresponding strap QLM*_HOST_MODE=0 6961 1 = when corresponding strap QLM*_HOST_MODE=1 6962 6963 When set, OCTEON drives the corresponding 6964 PERST*_L pin. Otherwise, OCTEON does not drive 6965 the corresponding PERST*_L pin. */ 6966 uint64_t rst_rcv : 1; /**< Controls whether corresponding PERST*_L chip pin 6967 is recieved by OCTEON. A warm/soft reset 6968 will not change this field. On cold reset, 6969 this field is initialized as follows: 6970 0 = when corresponding strap QLM*_HOST_MODE=1 6971 1 = when corresponding strap QLM*_HOST_MODE=0 6972 6973 When RST_RCV==1, the PERST*_L value is 6974 received and may be used to reset the 6975 controller and (optionally, based on RST_CHIP) 6976 warm reset the chip. 6977 6978 When RST_RCV==1 (and RST_CHIP=0), 6979 MIO_RST_INT[PERST*] gets set when the PERST*_L 6980 pin asserts. (This interrupt can alert SW 6981 whenever the external reset pin initiates a 6982 controller reset sequence.) 6983 6984 RST_VAL gives the PERST*_L pin value when 6985 RST_RCV==1. 6986 6987 When RST_RCV==0, the PERST*_L pin value is 6988 ignored. */ 6989 uint64_t rst_chip : 1; /**< Controls whether corresponding PERST*_L chip 6990 pin causes a chip warm reset like CHIP_RESET_L. 6991 A warm/soft reset will not change this field. 6992 On cold reset, this field is initialized to 0. 6993 6994 RST_CHIP is not used when RST_RCV==0. 6995 6996 When RST_RCV==0, RST_CHIP is ignored. 6997 6998 When RST_RCV==1, RST_CHIP==1, and PERST*_L 6999 asserts, a chip warm reset will be generated. */ 7000 uint64_t rst_val : 1; /**< Read-only access to corresponding PERST*_L pin 7001 Unpredictable when RST_RCV==0. Reads as 1 when 7002 RST_RCV==1 and the PERST*_L pin is asserted. 7003 Reads as 0 when RST_RCV==1 and the PERST*_L 7004 pin is not asserted. */ 7005#else 7006 uint64_t rst_val : 1; 7007 uint64_t rst_chip : 1; 7008 uint64_t rst_rcv : 1; 7009 uint64_t rst_drv : 1; 7010 uint64_t prtmode : 2; 7011 uint64_t host_mode : 1; 7012 uint64_t rst_link : 1; 7013 uint64_t rst_done : 1; 7014 uint64_t reserved_9_63 : 55; 7015#endif 7016 } cn63xxp1; 7017 struct cvmx_mio_rst_ctlx_cn63xx cn66xx; 7018 struct cvmx_mio_rst_ctlx_cn63xx cn68xx; 7019 struct cvmx_mio_rst_ctlx_cn63xx cn68xxp1; 7020 struct cvmx_mio_rst_ctlx_s cnf71xx; 7021}; 7022typedef union cvmx_mio_rst_ctlx cvmx_mio_rst_ctlx_t; 7023 7024/** 7025 * cvmx_mio_rst_delay 7026 */ 7027union cvmx_mio_rst_delay { 7028 uint64_t u64; 7029 struct cvmx_mio_rst_delay_s { 7030#ifdef __BIG_ENDIAN_BITFIELD 7031 uint64_t reserved_32_63 : 32; 7032 uint64_t warm_rst_dly : 16; /**< A warm reset immediately causes an early warm 7033 reset notification. However, the assertion of 7034 warm reset will be delayed this many sclks. 7035 A warm/soft reset will not change this field. 7036 NOTE: This must be at least 500 dclks */ 7037 uint64_t soft_rst_dly : 16; /**< A soft reset immediately causes an early soft 7038 reset notification. However, the assertion of 7039 soft reset will be delayed this many sclks. 7040 A warm/soft reset will not change this field. 7041 NOTE: This must be at least 500 dclks */ 7042#else 7043 uint64_t soft_rst_dly : 16; 7044 uint64_t warm_rst_dly : 16; 7045 uint64_t reserved_32_63 : 32; 7046#endif 7047 } s; 7048 struct cvmx_mio_rst_delay_s cn61xx; 7049 struct cvmx_mio_rst_delay_s cn63xx; 7050 struct cvmx_mio_rst_delay_s cn63xxp1; 7051 struct cvmx_mio_rst_delay_s cn66xx; 7052 struct cvmx_mio_rst_delay_s cn68xx; 7053 struct cvmx_mio_rst_delay_s cn68xxp1; 7054 struct cvmx_mio_rst_delay_s cnf71xx; 7055}; 7056typedef union cvmx_mio_rst_delay cvmx_mio_rst_delay_t; 7057 7058/** 7059 * cvmx_mio_rst_int 7060 * 7061 * MIO_RST_INT = MIO Reset Interrupt Register 7062 * 7063 */ 7064union cvmx_mio_rst_int { 7065 uint64_t u64; 7066 struct cvmx_mio_rst_int_s { 7067#ifdef __BIG_ENDIAN_BITFIELD 7068 uint64_t reserved_10_63 : 54; 7069 uint64_t perst1 : 1; /**< PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1 7070 and MIO_RST_CTL1[RST_CHIP]=0 */ 7071 uint64_t perst0 : 1; /**< PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1 7072 and MIO_RST_CTL0[RST_CHIP]=0 */ 7073 uint64_t reserved_4_7 : 4; 7074 uint64_t rst_link3 : 1; /**< A controller3 link-down/hot-reset occurred while 7075 MIO_RST_CNTL3[RST_LINK]=0. Software must assert 7076 then de-assert CIU_SOFT_PRST3[SOFT_PRST] */ 7077 uint64_t rst_link2 : 1; /**< A controller2 link-down/hot-reset occurred while 7078 MIO_RST_CNTL2[RST_LINK]=0. Software must assert 7079 then de-assert CIU_SOFT_PRST2[SOFT_PRST] */ 7080 uint64_t rst_link1 : 1; /**< A controller1 link-down/hot-reset occurred while 7081 MIO_RST_CTL1[RST_LINK]=0. Software must assert 7082 then de-assert CIU_SOFT_PRST1[SOFT_PRST] */ 7083 uint64_t rst_link0 : 1; /**< A controller0 link-down/hot-reset occurred while 7084 MIO_RST_CTL0[RST_LINK]=0. Software must assert 7085 then de-assert CIU_SOFT_PRST[SOFT_PRST] */ 7086#else 7087 uint64_t rst_link0 : 1; 7088 uint64_t rst_link1 : 1; 7089 uint64_t rst_link2 : 1; 7090 uint64_t rst_link3 : 1; 7091 uint64_t reserved_4_7 : 4; 7092 uint64_t perst0 : 1; 7093 uint64_t perst1 : 1; 7094 uint64_t reserved_10_63 : 54; 7095#endif 7096 } s; 7097 struct cvmx_mio_rst_int_cn61xx { 7098#ifdef __BIG_ENDIAN_BITFIELD 7099 uint64_t reserved_10_63 : 54; 7100 uint64_t perst1 : 1; /**< PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1 7101 and MIO_RST_CTL1[RST_CHIP]=0 */ 7102 uint64_t perst0 : 1; /**< PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1 7103 and MIO_RST_CTL0[RST_CHIP]=0 */ 7104 uint64_t reserved_2_7 : 6; 7105 uint64_t rst_link1 : 1; /**< A controller1 link-down/hot-reset occurred while 7106 MIO_RST_CTL1[RST_LINK]=0. Software must assert 7107 then de-assert CIU_SOFT_PRST1[SOFT_PRST] */ 7108 uint64_t rst_link0 : 1; /**< A controller0 link-down/hot-reset occurred while 7109 MIO_RST_CTL0[RST_LINK]=0. Software must assert 7110 then de-assert CIU_SOFT_PRST[SOFT_PRST] */ 7111#else 7112 uint64_t rst_link0 : 1; 7113 uint64_t rst_link1 : 1; 7114 uint64_t reserved_2_7 : 6; 7115 uint64_t perst0 : 1; 7116 uint64_t perst1 : 1; 7117 uint64_t reserved_10_63 : 54; 7118#endif 7119 } cn61xx; 7120 struct cvmx_mio_rst_int_cn61xx cn63xx; 7121 struct cvmx_mio_rst_int_cn61xx cn63xxp1; 7122 struct cvmx_mio_rst_int_s cn66xx; 7123 struct cvmx_mio_rst_int_cn61xx cn68xx; 7124 struct cvmx_mio_rst_int_cn61xx cn68xxp1; 7125 struct cvmx_mio_rst_int_cn61xx cnf71xx; 7126}; 7127typedef union cvmx_mio_rst_int cvmx_mio_rst_int_t; 7128 7129/** 7130 * cvmx_mio_rst_int_en 7131 * 7132 * MIO_RST_INT_EN = MIO Reset Interrupt Enable Register 7133 * 7134 */ 7135union cvmx_mio_rst_int_en { 7136 uint64_t u64; 7137 struct cvmx_mio_rst_int_en_s { 7138#ifdef __BIG_ENDIAN_BITFIELD 7139 uint64_t reserved_10_63 : 54; 7140 uint64_t perst1 : 1; /**< Controller1 PERST reset interrupt enable */ 7141 uint64_t perst0 : 1; /**< Controller0 PERST reset interrupt enable */ 7142 uint64_t reserved_4_7 : 4; 7143 uint64_t rst_link3 : 1; /**< Controller3 link-down/hot reset interrupt enable */ 7144 uint64_t rst_link2 : 1; /**< Controller2 link-down/hot reset interrupt enable */ 7145 uint64_t rst_link1 : 1; /**< Controller1 link-down/hot reset interrupt enable */ 7146 uint64_t rst_link0 : 1; /**< Controller0 link-down/hot reset interrupt enable */ 7147#else 7148 uint64_t rst_link0 : 1; 7149 uint64_t rst_link1 : 1; 7150 uint64_t rst_link2 : 1; 7151 uint64_t rst_link3 : 1; 7152 uint64_t reserved_4_7 : 4; 7153 uint64_t perst0 : 1; 7154 uint64_t perst1 : 1; 7155 uint64_t reserved_10_63 : 54; 7156#endif 7157 } s; 7158 struct cvmx_mio_rst_int_en_cn61xx { 7159#ifdef __BIG_ENDIAN_BITFIELD 7160 uint64_t reserved_10_63 : 54; 7161 uint64_t perst1 : 1; /**< Controller1 PERST reset interrupt enable */ 7162 uint64_t perst0 : 1; /**< Controller0 PERST reset interrupt enable */ 7163 uint64_t reserved_2_7 : 6; 7164 uint64_t rst_link1 : 1; /**< Controller1 link-down/hot reset interrupt enable */ 7165 uint64_t rst_link0 : 1; /**< Controller0 link-down/hot reset interrupt enable */ 7166#else 7167 uint64_t rst_link0 : 1; 7168 uint64_t rst_link1 : 1; 7169 uint64_t reserved_2_7 : 6; 7170 uint64_t perst0 : 1; 7171 uint64_t perst1 : 1; 7172 uint64_t reserved_10_63 : 54; 7173#endif 7174 } cn61xx; 7175 struct cvmx_mio_rst_int_en_cn61xx cn63xx; 7176 struct cvmx_mio_rst_int_en_cn61xx cn63xxp1; 7177 struct cvmx_mio_rst_int_en_s cn66xx; 7178 struct cvmx_mio_rst_int_en_cn61xx cn68xx; 7179 struct cvmx_mio_rst_int_en_cn61xx cn68xxp1; 7180 struct cvmx_mio_rst_int_en_cn61xx cnf71xx; 7181}; 7182typedef union cvmx_mio_rst_int_en cvmx_mio_rst_int_en_t; 7183 7184/** 7185 * cvmx_mio_tws#_int 7186 * 7187 * MIO_TWSX_INT = TWSX Interrupt Register 7188 * 7189 * This register contains the TWSI interrupt enable mask and the interrupt source bits. Note: the 7190 * interrupt source bit for the TWSI core interrupt (CORE_INT) is read-only, the appropriate sequence 7191 * must be written to the TWSI core to clear this interrupt. The other interrupt source bits are write- 7192 * one-to-clear. TS_INT is set on the update of the MIO_TWS_TWSI_SW register (i.e. when it is written 7193 * by a TWSI device). ST_INT is set whenever the valid bit of the MIO_TWS_SW_TWSI is cleared (see above 7194 * for reasons). 7195 * 7196 * Note: When using the high-level controller, CORE_EN should be clear and CORE_INT should be ignored. 7197 * Conversely, when the high-level controller is disabled, ST_EN / TS_EN should be clear and ST_INT / 7198 * TS_INT should be ignored. 7199 * 7200 * This register also contains a read-only copy of the TWSI bus (SCL and SDA) as well as control bits to 7201 * override the current state of the TWSI bus (SCL_OVR and SDA_OVR). Setting an override bit high will 7202 * result in the open drain driver being activated, thus driving the corresponding signal low. 7203 */ 7204union cvmx_mio_twsx_int { 7205 uint64_t u64; 7206 struct cvmx_mio_twsx_int_s { 7207#ifdef __BIG_ENDIAN_BITFIELD 7208 uint64_t reserved_12_63 : 52; 7209 uint64_t scl : 1; /**< SCL */ 7210 uint64_t sda : 1; /**< SDA */ 7211 uint64_t scl_ovr : 1; /**< SCL override */ 7212 uint64_t sda_ovr : 1; /**< SDA override */ 7213 uint64_t reserved_7_7 : 1; 7214 uint64_t core_en : 1; /**< TWSI core interrupt enable */ 7215 uint64_t ts_en : 1; /**< MIO_TWS_TWSI_SW register update interrupt enable */ 7216 uint64_t st_en : 1; /**< MIO_TWS_SW_TWSI register update interrupt enable */ 7217 uint64_t reserved_3_3 : 1; 7218 uint64_t core_int : 1; /**< TWSI core interrupt */ 7219 uint64_t ts_int : 1; /**< MIO_TWS_TWSI_SW register update interrupt */ 7220 uint64_t st_int : 1; /**< MIO_TWS_SW_TWSI register update interrupt */ 7221#else 7222 uint64_t st_int : 1; 7223 uint64_t ts_int : 1; 7224 uint64_t core_int : 1; 7225 uint64_t reserved_3_3 : 1; 7226 uint64_t st_en : 1; 7227 uint64_t ts_en : 1; 7228 uint64_t core_en : 1; 7229 uint64_t reserved_7_7 : 1; 7230 uint64_t sda_ovr : 1; 7231 uint64_t scl_ovr : 1; 7232 uint64_t sda : 1; 7233 uint64_t scl : 1; 7234 uint64_t reserved_12_63 : 52; 7235#endif 7236 } s; 7237 struct cvmx_mio_twsx_int_s cn30xx; 7238 struct cvmx_mio_twsx_int_s cn31xx; 7239 struct cvmx_mio_twsx_int_s cn38xx; 7240 struct cvmx_mio_twsx_int_cn38xxp2 { 7241#ifdef __BIG_ENDIAN_BITFIELD 7242 uint64_t reserved_7_63 : 57; 7243 uint64_t core_en : 1; /**< TWSI core interrupt enable */ 7244 uint64_t ts_en : 1; /**< MIO_TWS_TWSI_SW register update interrupt enable */ 7245 uint64_t st_en : 1; /**< MIO_TWS_SW_TWSI register update interrupt enable */ 7246 uint64_t reserved_3_3 : 1; 7247 uint64_t core_int : 1; /**< TWSI core interrupt */ 7248 uint64_t ts_int : 1; /**< MIO_TWS_TWSI_SW register update interrupt */ 7249 uint64_t st_int : 1; /**< MIO_TWS_SW_TWSI register update interrupt */ 7250#else 7251 uint64_t st_int : 1; 7252 uint64_t ts_int : 1; 7253 uint64_t core_int : 1; 7254 uint64_t reserved_3_3 : 1; 7255 uint64_t st_en : 1; 7256 uint64_t ts_en : 1; 7257 uint64_t core_en : 1; 7258 uint64_t reserved_7_63 : 57; 7259#endif 7260 } cn38xxp2; 7261 struct cvmx_mio_twsx_int_s cn50xx; 7262 struct cvmx_mio_twsx_int_s cn52xx; 7263 struct cvmx_mio_twsx_int_s cn52xxp1; 7264 struct cvmx_mio_twsx_int_s cn56xx; 7265 struct cvmx_mio_twsx_int_s cn56xxp1; 7266 struct cvmx_mio_twsx_int_s cn58xx; 7267 struct cvmx_mio_twsx_int_s cn58xxp1; 7268 struct cvmx_mio_twsx_int_s cn61xx; 7269 struct cvmx_mio_twsx_int_s cn63xx; 7270 struct cvmx_mio_twsx_int_s cn63xxp1; 7271 struct cvmx_mio_twsx_int_s cn66xx; 7272 struct cvmx_mio_twsx_int_s cn68xx; 7273 struct cvmx_mio_twsx_int_s cn68xxp1; 7274 struct cvmx_mio_twsx_int_s cnf71xx; 7275}; 7276typedef union cvmx_mio_twsx_int cvmx_mio_twsx_int_t; 7277 7278/** 7279 * cvmx_mio_tws#_sw_twsi 7280 * 7281 * MIO_TWSX_SW_TWSI = TWSX Software to TWSI Register 7282 * 7283 * This register allows software to 7284 * - initiate TWSI interface master-mode operations with a write and read the result with a read 7285 * - load four bytes for later retrieval (slave mode) with a write and check validity with a read 7286 * - launch a TWSI controller configuration read/write with a write and read the result with a read 7287 * 7288 * This register should be read or written by software, and read by the TWSI device. The TWSI device can 7289 * use either two-byte or five-byte reads to reference this register. 7290 * 7291 * The TWSI device considers this register valid when V==1 and SLONLY==1. 7292 */ 7293union cvmx_mio_twsx_sw_twsi { 7294 uint64_t u64; 7295 struct cvmx_mio_twsx_sw_twsi_s { 7296#ifdef __BIG_ENDIAN_BITFIELD 7297 uint64_t v : 1; /**< Valid bit 7298 - Set on a write (should always be written with 7299 a 1) 7300 - Cleared when a TWSI master mode op completes 7301 - Cleared when a TWSI configuration register 7302 access completes 7303 - Cleared when the TWSI device reads the 7304 register if SLONLY==1 */ 7305 uint64_t slonly : 1; /**< Slave Only Mode 7306 - No operation is initiated with a write when 7307 this bit is set - only D field is updated in 7308 this case 7309 - When clear, a write initiates either a TWSI 7310 master-mode operation or a TWSI configuration 7311 register access */ 7312 uint64_t eia : 1; /**< Extended Internal Address - send additional 7313 internal address byte (MSB of IA is from IA field 7314 of MIO_TWS_SW_TWSI_EXT) */ 7315 uint64_t op : 4; /**< Opcode field - When the register is written with 7316 SLONLY==0, initiate a read or write: 7317 0000 => 7-bit Byte Master Mode TWSI Op 7318 0001 => 7-bit Byte Combined Read Master Mode Op 7319 7-bit Byte Write w/ IA Master Mode Op 7320 0010 => 10-bit Byte Master Mode TWSI Op 7321 0011 => 10-bit Byte Combined Read Master Mode Op 7322 10-bit Byte Write w/ IA Master Mode Op 7323 0100 => TWSI Master Clock Register 7324 0110 => See EOP field 7325 1000 => 7-bit 4-byte Master Mode TWSI Op 7326 1001 => 7-bit 4-byte Comb. Read Master Mode Op 7327 7-bit 4-byte Write w/ IA Master Mode Op 7328 1010 => 10-bit 4-byte Master Mode TWSI Op 7329 1011 => 10-bit 4-byte Comb. Read Master Mode Op 7330 10-bit 4-byte Write w/ IA Master Mode Op */ 7331 uint64_t r : 1; /**< Read bit or result 7332 - If set on a write when SLONLY==0, the 7333 operation is a read 7334 - On a read, this bit returns the result 7335 indication for the most recent master mode 7336 operation (1 = success, 0 = fail) */ 7337 uint64_t sovr : 1; /**< Size Override - if set, use the SIZE field to 7338 determine Master Mode Op size rather than what 7339 the Opcode field specifies. For operations 7340 greater than 4 bytes, the additional data will be 7341 contained in the D field of MIO_TWS_SW_TWSI_EXT */ 7342 uint64_t size : 3; /**< Size in bytes of Master Mode Op if the Size 7343 Override bit is set. Specified in -1 notation 7344 (i.e. 0 = 1 byte, 1 = 2 bytes ... 7 = 8 bytes) */ 7345 uint64_t scr : 2; /**< Scratch - unused, but retain state */ 7346 uint64_t a : 10; /**< Address field 7347 - the address of the remote device for a master 7348 mode operation 7349 - A<9:7> are only used for 10-bit addressing 7350 Note that when mastering a 7-bit OP, A<6:0> should 7351 not take any of the values 0x78, 0x79, 0x7A nor 7352 0x7B (these 7-bit addresses are reserved to 7353 extend to 10-bit addressing). */ 7354 uint64_t ia : 5; /**< Internal Address - Used when launching a master 7355 mode combined read / write with internal address 7356 (lower 3 bits are contained in the EOP_IA field) */ 7357 uint64_t eop_ia : 3; /**< Extra opcode (when OP<3:0> == 0110 and SLONLY==0): 7358 000 => TWSI Slave Address Register 7359 001 => TWSI Data Register 7360 010 => TWSI Control Register 7361 011 => TWSI Clock Control Register (when R == 0) 7362 011 => TWSI Status Register (when R == 1) 7363 100 => TWSI Extended Slave Register 7364 111 => TWSI Soft Reset Register 7365 Also the lower 3 bits of Internal Address when 7366 launching a master mode combined read / write 7367 with internal address */ 7368 uint64_t d : 32; /**< Data Field 7369 Used on a write when 7370 - initiating a master-mode write (SLONLY==0) 7371 - writing a TWSI config register (SLONLY==0) 7372 - a slave mode write (SLONLY==1) 7373 The read value is updated by 7374 - a write to this register 7375 - master mode completion (contains result or 7376 error code) 7377 - TWSI config register read (contains result) */ 7378#else 7379 uint64_t d : 32; 7380 uint64_t eop_ia : 3; 7381 uint64_t ia : 5; 7382 uint64_t a : 10; 7383 uint64_t scr : 2; 7384 uint64_t size : 3; 7385 uint64_t sovr : 1; 7386 uint64_t r : 1; 7387 uint64_t op : 4; 7388 uint64_t eia : 1; 7389 uint64_t slonly : 1; 7390 uint64_t v : 1; 7391#endif 7392 } s; 7393 struct cvmx_mio_twsx_sw_twsi_s cn30xx; 7394 struct cvmx_mio_twsx_sw_twsi_s cn31xx; 7395 struct cvmx_mio_twsx_sw_twsi_s cn38xx; 7396 struct cvmx_mio_twsx_sw_twsi_s cn38xxp2; 7397 struct cvmx_mio_twsx_sw_twsi_s cn50xx; 7398 struct cvmx_mio_twsx_sw_twsi_s cn52xx; 7399 struct cvmx_mio_twsx_sw_twsi_s cn52xxp1; 7400 struct cvmx_mio_twsx_sw_twsi_s cn56xx; 7401 struct cvmx_mio_twsx_sw_twsi_s cn56xxp1; 7402 struct cvmx_mio_twsx_sw_twsi_s cn58xx; 7403 struct cvmx_mio_twsx_sw_twsi_s cn58xxp1; 7404 struct cvmx_mio_twsx_sw_twsi_s cn61xx; 7405 struct cvmx_mio_twsx_sw_twsi_s cn63xx; 7406 struct cvmx_mio_twsx_sw_twsi_s cn63xxp1; 7407 struct cvmx_mio_twsx_sw_twsi_s cn66xx; 7408 struct cvmx_mio_twsx_sw_twsi_s cn68xx; 7409 struct cvmx_mio_twsx_sw_twsi_s cn68xxp1; 7410 struct cvmx_mio_twsx_sw_twsi_s cnf71xx; 7411}; 7412typedef union cvmx_mio_twsx_sw_twsi cvmx_mio_twsx_sw_twsi_t; 7413 7414/** 7415 * cvmx_mio_tws#_sw_twsi_ext 7416 * 7417 * MIO_TWSX_SW_TWSI_EXT = TWSX Software to TWSI Extension Register 7418 * 7419 * This register contains an additional byte of internal address and 4 additional bytes of data to be 7420 * used with TWSI master mode operations. IA will be sent as the first byte of internal address when 7421 * performing master mode combined read / write with internal address operations and the EIA bit of 7422 * MIO_TWS_SW_TWSI is set. D extends the data field of MIO_TWS_SW_TWSI for a total of 8 bytes (SOVR 7423 * must be set to perform operations greater than 4 bytes). 7424 */ 7425union cvmx_mio_twsx_sw_twsi_ext { 7426 uint64_t u64; 7427 struct cvmx_mio_twsx_sw_twsi_ext_s { 7428#ifdef __BIG_ENDIAN_BITFIELD 7429 uint64_t reserved_40_63 : 24; 7430 uint64_t ia : 8; /**< Extended Internal Address */ 7431 uint64_t d : 32; /**< Extended Data Field */ 7432#else 7433 uint64_t d : 32; 7434 uint64_t ia : 8; 7435 uint64_t reserved_40_63 : 24; 7436#endif 7437 } s; 7438 struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx; 7439 struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx; 7440 struct cvmx_mio_twsx_sw_twsi_ext_s cn38xx; 7441 struct cvmx_mio_twsx_sw_twsi_ext_s cn38xxp2; 7442 struct cvmx_mio_twsx_sw_twsi_ext_s cn50xx; 7443 struct cvmx_mio_twsx_sw_twsi_ext_s cn52xx; 7444 struct cvmx_mio_twsx_sw_twsi_ext_s cn52xxp1; 7445 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xx; 7446 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1; 7447 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx; 7448 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1; 7449 struct cvmx_mio_twsx_sw_twsi_ext_s cn61xx; 7450 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx; 7451 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1; 7452 struct cvmx_mio_twsx_sw_twsi_ext_s cn66xx; 7453 struct cvmx_mio_twsx_sw_twsi_ext_s cn68xx; 7454 struct cvmx_mio_twsx_sw_twsi_ext_s cn68xxp1; 7455 struct cvmx_mio_twsx_sw_twsi_ext_s cnf71xx; 7456}; 7457typedef union cvmx_mio_twsx_sw_twsi_ext cvmx_mio_twsx_sw_twsi_ext_t; 7458 7459/** 7460 * cvmx_mio_tws#_twsi_sw 7461 * 7462 * MIO_TWSX_TWSI_SW = TWSX TWSI to Software Register 7463 * 7464 * This register allows the TWSI device to transfer data to software and later check that software has 7465 * received the information. 7466 * 7467 * This register should be read or written by the TWSI device, and read by software. The TWSI device can 7468 * use one-byte or four-byte payload writes, and two-byte payload reads. 7469 * 7470 * The TWSI device considers this register valid when V==1. 7471 */ 7472union cvmx_mio_twsx_twsi_sw { 7473 uint64_t u64; 7474 struct cvmx_mio_twsx_twsi_sw_s { 7475#ifdef __BIG_ENDIAN_BITFIELD 7476 uint64_t v : 2; /**< Valid Bits 7477 - Not directly writable 7478 - Set to 1 on any write by the TWSI device 7479 - Cleared on any read by software */ 7480 uint64_t reserved_32_61 : 30; 7481 uint64_t d : 32; /**< Data Field - updated on a write by the TWSI device */ 7482#else 7483 uint64_t d : 32; 7484 uint64_t reserved_32_61 : 30; 7485 uint64_t v : 2; 7486#endif 7487 } s; 7488 struct cvmx_mio_twsx_twsi_sw_s cn30xx; 7489 struct cvmx_mio_twsx_twsi_sw_s cn31xx; 7490 struct cvmx_mio_twsx_twsi_sw_s cn38xx; 7491 struct cvmx_mio_twsx_twsi_sw_s cn38xxp2; 7492 struct cvmx_mio_twsx_twsi_sw_s cn50xx; 7493 struct cvmx_mio_twsx_twsi_sw_s cn52xx; 7494 struct cvmx_mio_twsx_twsi_sw_s cn52xxp1; 7495 struct cvmx_mio_twsx_twsi_sw_s cn56xx; 7496 struct cvmx_mio_twsx_twsi_sw_s cn56xxp1; 7497 struct cvmx_mio_twsx_twsi_sw_s cn58xx; 7498 struct cvmx_mio_twsx_twsi_sw_s cn58xxp1; 7499 struct cvmx_mio_twsx_twsi_sw_s cn61xx; 7500 struct cvmx_mio_twsx_twsi_sw_s cn63xx; 7501 struct cvmx_mio_twsx_twsi_sw_s cn63xxp1; 7502 struct cvmx_mio_twsx_twsi_sw_s cn66xx; 7503 struct cvmx_mio_twsx_twsi_sw_s cn68xx; 7504 struct cvmx_mio_twsx_twsi_sw_s cn68xxp1; 7505 struct cvmx_mio_twsx_twsi_sw_s cnf71xx; 7506}; 7507typedef union cvmx_mio_twsx_twsi_sw cvmx_mio_twsx_twsi_sw_t; 7508 7509/** 7510 * cvmx_mio_uart#_dlh 7511 * 7512 * MIO_UARTX_DLH = MIO UARTX Divisor Latch High Register 7513 * 7514 * The DLH (Divisor Latch High) register in conjunction with DLL (Divisor Latch Low) register form a 7515 * 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. It is 7516 * accessed by first setting the DLAB bit (bit 7) in the Line Control Register (LCR). The output baud 7517 * rate is equal to eclk frequency divided by sixteen times the value of the baud rate divisor, as 7518 * follows: baud rate = eclk / (16 * divisor). 7519 * 7520 * Note that the BUSY bit (bit 0) of the UART Status Register (USR) must be clear before writing this 7521 * register. BUSY bit is always clear in PASS3. 7522 * 7523 * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled 7524 * and no serial communications will occur. Also, once the DLL or DLH is set, at least 8 clock cycles 7525 * of eclk should be allowed to pass before transmitting or receiving data. 7526 * 7527 * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the 7528 * IER and DLH registers are the same. 7529 */ 7530union cvmx_mio_uartx_dlh { 7531 uint64_t u64; 7532 struct cvmx_mio_uartx_dlh_s { 7533#ifdef __BIG_ENDIAN_BITFIELD 7534 uint64_t reserved_8_63 : 56; 7535 uint64_t dlh : 8; /**< Divisor Latch High Register */ 7536#else 7537 uint64_t dlh : 8; 7538 uint64_t reserved_8_63 : 56; 7539#endif 7540 } s; 7541 struct cvmx_mio_uartx_dlh_s cn30xx; 7542 struct cvmx_mio_uartx_dlh_s cn31xx; 7543 struct cvmx_mio_uartx_dlh_s cn38xx; 7544 struct cvmx_mio_uartx_dlh_s cn38xxp2; 7545 struct cvmx_mio_uartx_dlh_s cn50xx; 7546 struct cvmx_mio_uartx_dlh_s cn52xx; 7547 struct cvmx_mio_uartx_dlh_s cn52xxp1; 7548 struct cvmx_mio_uartx_dlh_s cn56xx; 7549 struct cvmx_mio_uartx_dlh_s cn56xxp1; 7550 struct cvmx_mio_uartx_dlh_s cn58xx; 7551 struct cvmx_mio_uartx_dlh_s cn58xxp1; 7552 struct cvmx_mio_uartx_dlh_s cn61xx; 7553 struct cvmx_mio_uartx_dlh_s cn63xx; 7554 struct cvmx_mio_uartx_dlh_s cn63xxp1; 7555 struct cvmx_mio_uartx_dlh_s cn66xx; 7556 struct cvmx_mio_uartx_dlh_s cn68xx; 7557 struct cvmx_mio_uartx_dlh_s cn68xxp1; 7558 struct cvmx_mio_uartx_dlh_s cnf71xx; 7559}; 7560typedef union cvmx_mio_uartx_dlh cvmx_mio_uartx_dlh_t; 7561typedef cvmx_mio_uartx_dlh_t cvmx_uart_dlh_t; 7562 7563/** 7564 * cvmx_mio_uart#_dll 7565 * 7566 * MIO_UARTX_DLL = MIO UARTX Divisor Latch Low Register 7567 * 7568 * The DLH (Divisor Latch High) register in conjunction with DLL (Divisor Latch Low) register form a 7569 * 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. It is 7570 * accessed by first setting the DLAB bit (bit 7) in the Line Control Register (LCR). The output baud 7571 * rate is equal to eclk frequency divided by sixteen times the value of the baud rate divisor, as 7572 * follows: baud rate = eclk / (16 * divisor). 7573 * 7574 * Note that the BUSY bit (bit 0) of the UART Status Register (USR) must be clear before writing this 7575 * register. BUSY bit is always clear in PASS3. 7576 * 7577 * Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled 7578 * and no serial communications will occur. Also, once the DLL or DLH is set, at least 8 clock cycles 7579 * of eclk should be allowed to pass before transmitting or receiving data. 7580 * 7581 * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the 7582 * RBR, THR, and DLL registers are the same. 7583 */ 7584union cvmx_mio_uartx_dll { 7585 uint64_t u64; 7586 struct cvmx_mio_uartx_dll_s { 7587#ifdef __BIG_ENDIAN_BITFIELD 7588 uint64_t reserved_8_63 : 56; 7589 uint64_t dll : 8; /**< Divisor Latch Low Register */ 7590#else 7591 uint64_t dll : 8; 7592 uint64_t reserved_8_63 : 56; 7593#endif 7594 } s; 7595 struct cvmx_mio_uartx_dll_s cn30xx; 7596 struct cvmx_mio_uartx_dll_s cn31xx; 7597 struct cvmx_mio_uartx_dll_s cn38xx; 7598 struct cvmx_mio_uartx_dll_s cn38xxp2; 7599 struct cvmx_mio_uartx_dll_s cn50xx; 7600 struct cvmx_mio_uartx_dll_s cn52xx; 7601 struct cvmx_mio_uartx_dll_s cn52xxp1; 7602 struct cvmx_mio_uartx_dll_s cn56xx; 7603 struct cvmx_mio_uartx_dll_s cn56xxp1; 7604 struct cvmx_mio_uartx_dll_s cn58xx; 7605 struct cvmx_mio_uartx_dll_s cn58xxp1; 7606 struct cvmx_mio_uartx_dll_s cn61xx; 7607 struct cvmx_mio_uartx_dll_s cn63xx; 7608 struct cvmx_mio_uartx_dll_s cn63xxp1; 7609 struct cvmx_mio_uartx_dll_s cn66xx; 7610 struct cvmx_mio_uartx_dll_s cn68xx; 7611 struct cvmx_mio_uartx_dll_s cn68xxp1; 7612 struct cvmx_mio_uartx_dll_s cnf71xx; 7613}; 7614typedef union cvmx_mio_uartx_dll cvmx_mio_uartx_dll_t; 7615typedef cvmx_mio_uartx_dll_t cvmx_uart_dll_t; 7616 7617/** 7618 * cvmx_mio_uart#_far 7619 * 7620 * MIO_UARTX_FAR = MIO UARTX FIFO Access Register 7621 * 7622 * The FIFO Access Register (FAR) is used to enable a FIFO access mode for testing, so that the receive 7623 * FIFO can be written by software and the transmit FIFO can be read by software when the FIFOs are 7624 * enabled. When FIFOs are not enabled it allows the RBR to be written by software and the THR to be read 7625 * by software. Note, that when the FIFO access mode is enabled/disabled, the control portion of the 7626 * receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty. 7627 */ 7628union cvmx_mio_uartx_far { 7629 uint64_t u64; 7630 struct cvmx_mio_uartx_far_s { 7631#ifdef __BIG_ENDIAN_BITFIELD 7632 uint64_t reserved_1_63 : 63; 7633 uint64_t far : 1; /**< FIFO Access Register */ 7634#else 7635 uint64_t far : 1; 7636 uint64_t reserved_1_63 : 63; 7637#endif 7638 } s; 7639 struct cvmx_mio_uartx_far_s cn30xx; 7640 struct cvmx_mio_uartx_far_s cn31xx; 7641 struct cvmx_mio_uartx_far_s cn38xx; 7642 struct cvmx_mio_uartx_far_s cn38xxp2; 7643 struct cvmx_mio_uartx_far_s cn50xx; 7644 struct cvmx_mio_uartx_far_s cn52xx; 7645 struct cvmx_mio_uartx_far_s cn52xxp1; 7646 struct cvmx_mio_uartx_far_s cn56xx; 7647 struct cvmx_mio_uartx_far_s cn56xxp1; 7648 struct cvmx_mio_uartx_far_s cn58xx; 7649 struct cvmx_mio_uartx_far_s cn58xxp1; 7650 struct cvmx_mio_uartx_far_s cn61xx; 7651 struct cvmx_mio_uartx_far_s cn63xx; 7652 struct cvmx_mio_uartx_far_s cn63xxp1; 7653 struct cvmx_mio_uartx_far_s cn66xx; 7654 struct cvmx_mio_uartx_far_s cn68xx; 7655 struct cvmx_mio_uartx_far_s cn68xxp1; 7656 struct cvmx_mio_uartx_far_s cnf71xx; 7657}; 7658typedef union cvmx_mio_uartx_far cvmx_mio_uartx_far_t; 7659typedef cvmx_mio_uartx_far_t cvmx_uart_far_t; 7660 7661/** 7662 * cvmx_mio_uart#_fcr 7663 * 7664 * MIO_UARTX_FCR = MIO UARTX FIFO Control Register 7665 * 7666 * The FIFO Control Register (FCR) is a write-only register that controls the read and write data FIFO 7667 * operation. When FIFOs and Programmable THRE Interrupt mode are enabled, this register also controls 7668 * the THRE Interrupt empty threshold level. 7669 * 7670 * Setting bit 0 of the FCR enables the transmit and receive FIFOs. Whenever the value of this bit is 7671 * changed both the TX and RX FIFOs will be reset. 7672 * 7673 * Writing a '1' to bit 1 of the FCR resets and flushes data in the receive FIFO. Note that this bit is 7674 * self-clearing and it is not necessary to clear this bit. 7675 * 7676 * Writing a '1' to bit 2 of the FCR resets and flushes data in the transmit FIFO. Note that this bit is 7677 * self-clearing and it is not necessary to clear this bit. 7678 * 7679 * If the FIFOs and Programmable THRE Interrupt mode are enabled, bits 4 and 5 control the empty 7680 * threshold level at which THRE Interrupts are generated when the mode is active. See the following 7681 * table for encodings: 7682 * 7683 * TX Trigger 7684 * ---------- 7685 * 00 = empty FIFO 7686 * 01 = 2 chars in FIFO 7687 * 10 = FIFO 1/4 full 7688 * 11 = FIFO 1/2 full 7689 * 7690 * If the FIFO mode is enabled (bit 0 of the FCR is set to '1') bits 6 and 7 are active. Bit 6 and bit 7 7691 * set the trigger level in the receiver FIFO for the Enable Received Data Available Interrupt (ERBFI). 7692 * In auto flow control mode the trigger is used to determine when the rts_n signal will be deasserted. 7693 * See the following table for encodings: 7694 * 7695 * RX Trigger 7696 * ---------- 7697 * 00 = 1 char in FIFO 7698 * 01 = FIFO 1/4 full 7699 * 10 = FIFO 1/2 full 7700 * 11 = FIFO 2 chars less than full 7701 * 7702 * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the 7703 * IIR and FCR registers are the same. 7704 */ 7705union cvmx_mio_uartx_fcr { 7706 uint64_t u64; 7707 struct cvmx_mio_uartx_fcr_s { 7708#ifdef __BIG_ENDIAN_BITFIELD 7709 uint64_t reserved_8_63 : 56; 7710 uint64_t rxtrig : 2; /**< RX Trigger */ 7711 uint64_t txtrig : 2; /**< TX Trigger */ 7712 uint64_t reserved_3_3 : 1; 7713 uint64_t txfr : 1; /**< TX FIFO reset */ 7714 uint64_t rxfr : 1; /**< RX FIFO reset */ 7715 uint64_t en : 1; /**< FIFO enable */ 7716#else 7717 uint64_t en : 1; 7718 uint64_t rxfr : 1; 7719 uint64_t txfr : 1; 7720 uint64_t reserved_3_3 : 1; 7721 uint64_t txtrig : 2; 7722 uint64_t rxtrig : 2; 7723 uint64_t reserved_8_63 : 56; 7724#endif 7725 } s; 7726 struct cvmx_mio_uartx_fcr_s cn30xx; 7727 struct cvmx_mio_uartx_fcr_s cn31xx; 7728 struct cvmx_mio_uartx_fcr_s cn38xx; 7729 struct cvmx_mio_uartx_fcr_s cn38xxp2; 7730 struct cvmx_mio_uartx_fcr_s cn50xx; 7731 struct cvmx_mio_uartx_fcr_s cn52xx; 7732 struct cvmx_mio_uartx_fcr_s cn52xxp1; 7733 struct cvmx_mio_uartx_fcr_s cn56xx; 7734 struct cvmx_mio_uartx_fcr_s cn56xxp1; 7735 struct cvmx_mio_uartx_fcr_s cn58xx; 7736 struct cvmx_mio_uartx_fcr_s cn58xxp1; 7737 struct cvmx_mio_uartx_fcr_s cn61xx; 7738 struct cvmx_mio_uartx_fcr_s cn63xx; 7739 struct cvmx_mio_uartx_fcr_s cn63xxp1; 7740 struct cvmx_mio_uartx_fcr_s cn66xx; 7741 struct cvmx_mio_uartx_fcr_s cn68xx; 7742 struct cvmx_mio_uartx_fcr_s cn68xxp1; 7743 struct cvmx_mio_uartx_fcr_s cnf71xx; 7744}; 7745typedef union cvmx_mio_uartx_fcr cvmx_mio_uartx_fcr_t; 7746typedef cvmx_mio_uartx_fcr_t cvmx_uart_fcr_t; 7747 7748/** 7749 * cvmx_mio_uart#_htx 7750 * 7751 * MIO_UARTX_HTX = MIO UARTX Halt TX Register 7752 * 7753 * The Halt TX Register (HTX) is used to halt transmissions for testing, so that the transmit FIFO can be 7754 * filled by software when FIFOs are enabled. If FIFOs are not enabled, setting the HTX register will 7755 * have no effect. 7756 */ 7757union cvmx_mio_uartx_htx { 7758 uint64_t u64; 7759 struct cvmx_mio_uartx_htx_s { 7760#ifdef __BIG_ENDIAN_BITFIELD 7761 uint64_t reserved_1_63 : 63; 7762 uint64_t htx : 1; /**< Halt TX */ 7763#else 7764 uint64_t htx : 1; 7765 uint64_t reserved_1_63 : 63; 7766#endif 7767 } s; 7768 struct cvmx_mio_uartx_htx_s cn30xx; 7769 struct cvmx_mio_uartx_htx_s cn31xx; 7770 struct cvmx_mio_uartx_htx_s cn38xx; 7771 struct cvmx_mio_uartx_htx_s cn38xxp2; 7772 struct cvmx_mio_uartx_htx_s cn50xx; 7773 struct cvmx_mio_uartx_htx_s cn52xx; 7774 struct cvmx_mio_uartx_htx_s cn52xxp1; 7775 struct cvmx_mio_uartx_htx_s cn56xx; 7776 struct cvmx_mio_uartx_htx_s cn56xxp1; 7777 struct cvmx_mio_uartx_htx_s cn58xx; 7778 struct cvmx_mio_uartx_htx_s cn58xxp1; 7779 struct cvmx_mio_uartx_htx_s cn61xx; 7780 struct cvmx_mio_uartx_htx_s cn63xx; 7781 struct cvmx_mio_uartx_htx_s cn63xxp1; 7782 struct cvmx_mio_uartx_htx_s cn66xx; 7783 struct cvmx_mio_uartx_htx_s cn68xx; 7784 struct cvmx_mio_uartx_htx_s cn68xxp1; 7785 struct cvmx_mio_uartx_htx_s cnf71xx; 7786}; 7787typedef union cvmx_mio_uartx_htx cvmx_mio_uartx_htx_t; 7788typedef cvmx_mio_uartx_htx_t cvmx_uart_htx_t; 7789 7790/** 7791 * cvmx_mio_uart#_ier 7792 * 7793 * MIO_UARTX_IER = MIO UARTX Interrupt Enable Register 7794 * 7795 * Interrupt Enable Register (IER) is a read/write register that contains four bits that enable 7796 * the generation of interrupts. These four bits are the Enable Received Data Available Interrupt 7797 * (ERBFI), the Enable Transmitter Holding Register Empty Interrupt (ETBEI), the Enable Receiver Line 7798 * Status Interrupt (ELSI), and the Enable Modem Status Interrupt (EDSSI). 7799 * 7800 * The IER also contains an enable bit (PTIME) for the Programmable THRE Interrupt mode. 7801 * 7802 * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access 7803 * this register. 7804 * 7805 * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the 7806 * IER and DLH registers are the same. 7807 */ 7808union cvmx_mio_uartx_ier { 7809 uint64_t u64; 7810 struct cvmx_mio_uartx_ier_s { 7811#ifdef __BIG_ENDIAN_BITFIELD 7812 uint64_t reserved_8_63 : 56; 7813 uint64_t ptime : 1; /**< Programmable THRE Interrupt mode enable */ 7814 uint64_t reserved_4_6 : 3; 7815 uint64_t edssi : 1; /**< Enable Modem Status Interrupt */ 7816 uint64_t elsi : 1; /**< Enable Receiver Line Status Interrupt */ 7817 uint64_t etbei : 1; /**< Enable Transmitter Holding Register Empty Interrupt */ 7818 uint64_t erbfi : 1; /**< Enable Received Data Available Interrupt */ 7819#else 7820 uint64_t erbfi : 1; 7821 uint64_t etbei : 1; 7822 uint64_t elsi : 1; 7823 uint64_t edssi : 1; 7824 uint64_t reserved_4_6 : 3; 7825 uint64_t ptime : 1; 7826 uint64_t reserved_8_63 : 56; 7827#endif 7828 } s; 7829 struct cvmx_mio_uartx_ier_s cn30xx; 7830 struct cvmx_mio_uartx_ier_s cn31xx; 7831 struct cvmx_mio_uartx_ier_s cn38xx; 7832 struct cvmx_mio_uartx_ier_s cn38xxp2; 7833 struct cvmx_mio_uartx_ier_s cn50xx; 7834 struct cvmx_mio_uartx_ier_s cn52xx; 7835 struct cvmx_mio_uartx_ier_s cn52xxp1; 7836 struct cvmx_mio_uartx_ier_s cn56xx; 7837 struct cvmx_mio_uartx_ier_s cn56xxp1; 7838 struct cvmx_mio_uartx_ier_s cn58xx; 7839 struct cvmx_mio_uartx_ier_s cn58xxp1; 7840 struct cvmx_mio_uartx_ier_s cn61xx; 7841 struct cvmx_mio_uartx_ier_s cn63xx; 7842 struct cvmx_mio_uartx_ier_s cn63xxp1; 7843 struct cvmx_mio_uartx_ier_s cn66xx; 7844 struct cvmx_mio_uartx_ier_s cn68xx; 7845 struct cvmx_mio_uartx_ier_s cn68xxp1; 7846 struct cvmx_mio_uartx_ier_s cnf71xx; 7847}; 7848typedef union cvmx_mio_uartx_ier cvmx_mio_uartx_ier_t; 7849typedef cvmx_mio_uartx_ier_t cvmx_uart_ier_t; 7850 7851/** 7852 * cvmx_mio_uart#_iir 7853 * 7854 * MIO_UARTX_IIR = MIO UARTX Interrupt Identity Register 7855 * 7856 * The Interrupt Identity Register (IIR) is a read-only register that identifies the source of an 7857 * interrupt. The upper two bits of the register are FIFO-enabled bits. These bits are '00' if the FIFOs 7858 * are disabled, and '11' if they are enabled. The lower four bits identify the highest priority pending 7859 * interrupt. The following table defines interrupt source decoding, interrupt priority, and interrupt 7860 * reset control: 7861 * 7862 * Interrupt Priority Interrupt Interrupt Interrupt 7863 * ID Level Type Source Reset By 7864 * --------------------------------------------------------------------------------------------------------------------------------- 7865 * 0001 - None None - 7866 * 7867 * 0110 Highest Receiver Line Overrun, parity, or framing errors or break Reading the Line Status Register 7868 * Status interrupt 7869 * 7870 * 0100 Second Received Data Receiver data available (FIFOs disabled) or Reading the Receiver Buffer Register 7871 * Available RX FIFO trigger level reached (FIFOs (FIFOs disabled) or the FIFO drops below 7872 * enabled) the trigger level (FIFOs enabled) 7873 * 7874 * 1100 Second Character No characters in or out of the RX FIFO Reading the Receiver Buffer Register 7875 * Timeout during the last 4 character times and there 7876 * Indication is at least 1 character in it during this 7877 * time 7878 * 7879 * 0010 Third Transmitter Transmitter Holding Register Empty Reading the Interrupt Identity Register 7880 * Holding (Programmable THRE Mode disabled) or TX (if source of interrupt) or writing into 7881 * Register FIFO at or below threshold (Programmable THR (FIFOs or THRE Mode disabled) or TX 7882 * Empty THRE Mode enabled) FIFO above threshold (FIFOs and THRE 7883 * Mode enabled) 7884 * 7885 * 0000 Fourth Modem Status Clear To Send (CTS) or Data Set Ready (DSR) Reading the Modem Status Register 7886 * Changed or Ring Indicator (RI) or Data Carrier 7887 * Detect (DCD) changed (note: if auto flow 7888 * control mode is enabled, a change in CTS 7889 * will not cause an interrupt) 7890 * 7891 * 0111 Fifth Busy Detect Software has tried to write to the Line Reading the UART Status Register 7892 * Indication Control Register while the BUSY bit of the 7893 * UART Status Register was set 7894 * 7895 * Note: The Busy Detect Indication interrupt has been removed from PASS3 and will never assert. 7896 * 7897 * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the 7898 * IIR and FCR registers are the same. 7899 */ 7900union cvmx_mio_uartx_iir { 7901 uint64_t u64; 7902 struct cvmx_mio_uartx_iir_s { 7903#ifdef __BIG_ENDIAN_BITFIELD 7904 uint64_t reserved_8_63 : 56; 7905 uint64_t fen : 2; /**< FIFO-enabled bits */ 7906 uint64_t reserved_4_5 : 2; 7907 cvmx_uart_iid_t iid : 4; /**< Interrupt ID */ 7908#else 7909 cvmx_uart_iid_t iid : 4; 7910 uint64_t reserved_4_5 : 2; 7911 uint64_t fen : 2; 7912 uint64_t reserved_8_63 : 56; 7913#endif 7914 } s; 7915 struct cvmx_mio_uartx_iir_s cn30xx; 7916 struct cvmx_mio_uartx_iir_s cn31xx; 7917 struct cvmx_mio_uartx_iir_s cn38xx; 7918 struct cvmx_mio_uartx_iir_s cn38xxp2; 7919 struct cvmx_mio_uartx_iir_s cn50xx; 7920 struct cvmx_mio_uartx_iir_s cn52xx; 7921 struct cvmx_mio_uartx_iir_s cn52xxp1; 7922 struct cvmx_mio_uartx_iir_s cn56xx; 7923 struct cvmx_mio_uartx_iir_s cn56xxp1; 7924 struct cvmx_mio_uartx_iir_s cn58xx; 7925 struct cvmx_mio_uartx_iir_s cn58xxp1; 7926 struct cvmx_mio_uartx_iir_s cn61xx; 7927 struct cvmx_mio_uartx_iir_s cn63xx; 7928 struct cvmx_mio_uartx_iir_s cn63xxp1; 7929 struct cvmx_mio_uartx_iir_s cn66xx; 7930 struct cvmx_mio_uartx_iir_s cn68xx; 7931 struct cvmx_mio_uartx_iir_s cn68xxp1; 7932 struct cvmx_mio_uartx_iir_s cnf71xx; 7933}; 7934typedef union cvmx_mio_uartx_iir cvmx_mio_uartx_iir_t; 7935typedef cvmx_mio_uartx_iir_t cvmx_uart_iir_t; 7936 7937/** 7938 * cvmx_mio_uart#_lcr 7939 * 7940 * MIO_UARTX_LCR = MIO UARTX Line Control Register 7941 * 7942 * The Line Control Register (LCR) controls the format of the data that is transmitted and received by 7943 * the UART. 7944 * 7945 * LCR bits 0 and 1 are the Character Length Select field. This field is used to select the number of 7946 * data bits per character that are transmitted and received. See the following table for encodings: 7947 * 7948 * CLS 7949 * --- 7950 * 00 = 5 bits (bits 0-4 sent) 7951 * 01 = 6 bits (bits 0-5 sent) 7952 * 10 = 7 bits (bits 0-6 sent) 7953 * 11 = 8 bits (all bits sent) 7954 * 7955 * LCR bit 2 controls the number of stop bits transmitted. If bit 2 is a '0', one stop bit is transmitted 7956 * in the serial data. If bit 2 is a '1' and the data bits are set to '00', one and a half stop bits are 7957 * generated. Otherwise, two stop bits are generated and transmitted in the serial data out. Note that 7958 * regardless of the number of stop bits selected the receiver will only check the first stop bit. 7959 * 7960 * LCR bit 3 is the Parity Enable bit. This bit is used to enable and disable parity generation and 7961 * detection in transmitted and received serial character respectively. 7962 * 7963 * LCR bit 4 is the Even Parity Select bit. If parity is enabled, bit 4 selects between even and odd 7964 * parity. If bit 4 is a '1', an even number of ones is transmitted or checked. If bit 4 is a '0', an odd 7965 * number of ones is transmitted or checked. 7966 * 7967 * LCR bit 6 is the Break Control bit. Setting the Break bit sends a break signal by holding the sout 7968 * line low (when not in Loopback mode, as determined by Modem Control Register bit 4). When in Loopback 7969 * mode, the break condition is internally looped back to the receiver. 7970 * 7971 * LCR bit 7 is the Divisor Latch Address bit. Setting this bit enables reading and writing of the 7972 * Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after 7973 * initial baud rate setup in order to access other registers. 7974 * 7975 * Note: The LCR is writeable only when the UART is not busy (when the BUSY bit (bit 0) of the UART 7976 * Status Register (USR) is clear). The LCR is always readable. In PASS3, the LCR is always writable 7977 * because the BUSY bit is always clear. 7978 */ 7979union cvmx_mio_uartx_lcr { 7980 uint64_t u64; 7981 struct cvmx_mio_uartx_lcr_s { 7982#ifdef __BIG_ENDIAN_BITFIELD 7983 uint64_t reserved_8_63 : 56; 7984 uint64_t dlab : 1; /**< Divisor Latch Address bit */ 7985 uint64_t brk : 1; /**< Break Control bit */ 7986 uint64_t reserved_5_5 : 1; 7987 uint64_t eps : 1; /**< Even Parity Select bit */ 7988 uint64_t pen : 1; /**< Parity Enable bit */ 7989 uint64_t stop : 1; /**< Stop Control bit */ 7990 cvmx_uart_bits_t cls : 2; /**< Character Length Select */ 7991#else 7992 cvmx_uart_bits_t cls : 2; 7993 uint64_t stop : 1; 7994 uint64_t pen : 1; 7995 uint64_t eps : 1; 7996 uint64_t reserved_5_5 : 1; 7997 uint64_t brk : 1; 7998 uint64_t dlab : 1; 7999 uint64_t reserved_8_63 : 56; 8000#endif 8001 } s; 8002 struct cvmx_mio_uartx_lcr_s cn30xx; 8003 struct cvmx_mio_uartx_lcr_s cn31xx; 8004 struct cvmx_mio_uartx_lcr_s cn38xx; 8005 struct cvmx_mio_uartx_lcr_s cn38xxp2; 8006 struct cvmx_mio_uartx_lcr_s cn50xx; 8007 struct cvmx_mio_uartx_lcr_s cn52xx; 8008 struct cvmx_mio_uartx_lcr_s cn52xxp1; 8009 struct cvmx_mio_uartx_lcr_s cn56xx; 8010 struct cvmx_mio_uartx_lcr_s cn56xxp1; 8011 struct cvmx_mio_uartx_lcr_s cn58xx; 8012 struct cvmx_mio_uartx_lcr_s cn58xxp1; 8013 struct cvmx_mio_uartx_lcr_s cn61xx; 8014 struct cvmx_mio_uartx_lcr_s cn63xx; 8015 struct cvmx_mio_uartx_lcr_s cn63xxp1; 8016 struct cvmx_mio_uartx_lcr_s cn66xx; 8017 struct cvmx_mio_uartx_lcr_s cn68xx; 8018 struct cvmx_mio_uartx_lcr_s cn68xxp1; 8019 struct cvmx_mio_uartx_lcr_s cnf71xx; 8020}; 8021typedef union cvmx_mio_uartx_lcr cvmx_mio_uartx_lcr_t; 8022typedef cvmx_mio_uartx_lcr_t cvmx_uart_lcr_t; 8023 8024/** 8025 * cvmx_mio_uart#_lsr 8026 * 8027 * MIO_UARTX_LSR = MIO UARTX Line Status Register 8028 * 8029 * The Line Status Register (LSR) contains status of the receiver and transmitter data transfers. This 8030 * status can be read by the user at anytime. 8031 * 8032 * LSR bit 0 is the Data Ready (DR) bit. When set, this bit indicates the receiver contains at least one 8033 * character in the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the non-FIFO 8034 * mode, or when the receiver FIFO is empty, in FIFO mode. 8035 * 8036 * LSR bit 1 is the Overrun Error (OE) bit. When set, this bit indicates an overrun error has occurred 8037 * because a new data character was received before the previous data was read. In the non-FIFO mode, the 8038 * OE bit is set when a new character arrives in the receiver before the previous character was read from 8039 * the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error 8040 * occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is 8041 * retained and the data in the receive shift register is lost. 8042 * 8043 * LSR bit 2 is the Parity Error (PE) bit. This bit is set whenever there is a parity error in the 8044 * receiver if the Parity Enable (PEN) bit in the LCR is set. In the FIFO mode, since the parity error is 8045 * associated with a character received, it is revealed when the character with the parity error arrives 8046 * at the top of the FIFO. It should be noted that the Parity Error (PE) bit will be set if a break 8047 * interrupt has occurred, as indicated by the Break Interrupt (BI) bit. 8048 * 8049 * LSR bit 3 is the Framing Error (FE) bit. This bit is set whenever there is a framing error in the 8050 * receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received 8051 * data. In the FIFO mode, since the framing error is associated with a character received, it is 8052 * revealed when the character with the framing error is at the top of the FIFO. When a framing error 8053 * occurs the UART will try resynchronize. It does this by assuming that the error was due to the start 8054 * bit of the next character and then continues receiving the other bits (i.e. data and/or parity and 8055 * stop). It should be noted that the Framing Error (FE) bit will be set if a break interrupt has 8056 * occurred, as indicated by the Break Interrupt (BI) bit. 8057 * 8058 * Note: The OE, PE, and FE bits are reset when a read of the LSR is performed. 8059 * 8060 * LSR bit 4 is the Break Interrupt (BI) bit. This bit is set whenever the serial input (sin) is held in 8061 * a 0 state for longer than the sum of start time + data bits + parity + stop bits. A break condition on 8062 * sin causes one and only one character, consisting of all zeros, to be received by the UART. In the 8063 * FIFO mode, the character associated with the break condition is carried through the FIFO and is 8064 * revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non- 8065 * FIFO mode, the BI indication occurs immediately and persists until the LSR is read. 8066 * 8067 * LSR bit 5 is the Transmitter Holding Register Empty (THRE) bit. When Programmable THRE Interrupt mode 8068 * is disabled, this bit indicates that the UART can accept a new character for transmission. This bit is 8069 * set whenever data is transferred from the THR (or TX FIFO) to the transmitter shift register and no 8070 * new data has been written to the THR (or TX FIFO). This also causes a THRE Interrupt to occur, if the 8071 * THRE Interrupt is enabled. When FIFOs and Programmable THRE Interrupt mode are enabled, LSR bit 5 8072 * functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE 8073 * Interrupts, which are then controlled by the FCR[5:4] threshold setting. 8074 * 8075 * LSR bit 6 is the Transmitter Empty (TEMT) bit. In the FIFO mode, this bit is set whenever the 8076 * Transmitter Shift Register and the FIFO are both empty. In the non-FIFO mode, this bit is set whenever 8077 * the Transmitter Holding Register and the Transmitter Shift Register are both empty. This bit is 8078 * typically used to make sure it is safe to change control registers. Changing control registers while 8079 * the transmitter is busy can result in corrupt data being transmitted. 8080 * 8081 * LSR bit 7 is the Error in Receiver FIFO (FERR) bit. This bit is active only when FIFOs are enabled. It 8082 * is set when there is at least one parity error, framing error, or break indication in the FIFO. This 8083 * bit is cleared when the LSR is read and the character with the error is at the top of the receiver 8084 * FIFO and there are no subsequent errors in the FIFO. 8085 */ 8086union cvmx_mio_uartx_lsr { 8087 uint64_t u64; 8088 struct cvmx_mio_uartx_lsr_s { 8089#ifdef __BIG_ENDIAN_BITFIELD 8090 uint64_t reserved_8_63 : 56; 8091 uint64_t ferr : 1; /**< Error in Receiver FIFO bit */ 8092 uint64_t temt : 1; /**< Transmitter Empty bit */ 8093 uint64_t thre : 1; /**< Transmitter Holding Register Empty bit */ 8094 uint64_t bi : 1; /**< Break Interrupt bit */ 8095 uint64_t fe : 1; /**< Framing Error bit */ 8096 uint64_t pe : 1; /**< Parity Error bit */ 8097 uint64_t oe : 1; /**< Overrun Error bit */ 8098 uint64_t dr : 1; /**< Data Ready bit */ 8099#else 8100 uint64_t dr : 1; 8101 uint64_t oe : 1; 8102 uint64_t pe : 1; 8103 uint64_t fe : 1; 8104 uint64_t bi : 1; 8105 uint64_t thre : 1; 8106 uint64_t temt : 1; 8107 uint64_t ferr : 1; 8108 uint64_t reserved_8_63 : 56; 8109#endif 8110 } s; 8111 struct cvmx_mio_uartx_lsr_s cn30xx; 8112 struct cvmx_mio_uartx_lsr_s cn31xx; 8113 struct cvmx_mio_uartx_lsr_s cn38xx; 8114 struct cvmx_mio_uartx_lsr_s cn38xxp2; 8115 struct cvmx_mio_uartx_lsr_s cn50xx; 8116 struct cvmx_mio_uartx_lsr_s cn52xx; 8117 struct cvmx_mio_uartx_lsr_s cn52xxp1; 8118 struct cvmx_mio_uartx_lsr_s cn56xx; 8119 struct cvmx_mio_uartx_lsr_s cn56xxp1; 8120 struct cvmx_mio_uartx_lsr_s cn58xx; 8121 struct cvmx_mio_uartx_lsr_s cn58xxp1; 8122 struct cvmx_mio_uartx_lsr_s cn61xx; 8123 struct cvmx_mio_uartx_lsr_s cn63xx; 8124 struct cvmx_mio_uartx_lsr_s cn63xxp1; 8125 struct cvmx_mio_uartx_lsr_s cn66xx; 8126 struct cvmx_mio_uartx_lsr_s cn68xx; 8127 struct cvmx_mio_uartx_lsr_s cn68xxp1; 8128 struct cvmx_mio_uartx_lsr_s cnf71xx; 8129}; 8130typedef union cvmx_mio_uartx_lsr cvmx_mio_uartx_lsr_t; 8131typedef cvmx_mio_uartx_lsr_t cvmx_uart_lsr_t; 8132 8133/** 8134 * cvmx_mio_uart#_mcr 8135 * 8136 * MIO_UARTX_MCR = MIO UARTX Modem Control Register 8137 * 8138 * The lower four bits of the Modem Control Register (MCR) directly manipulate the outputs of the UART. 8139 * The DTR (bit 0), RTS (bit 1), OUT1 (bit 2), and OUT2 (bit 3) bits are inverted and then drive the 8140 * corresponding UART outputs, dtr_n, rts_n, out1_n, and out2_n. In loopback mode, these outputs are 8141 * driven inactive high while the values in these locations are internally looped back to the inputs. 8142 * 8143 * Note: When Auto RTS is enabled, the rts_n output is controlled in the same way, but is also gated 8144 * with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The 8145 * rts_n output will be de-asserted whenever RTS (bit 1) is set low. 8146 * 8147 * Note: The UART0 out1_n and out2_n outputs are not present on the pins of the chip, but the UART0 OUT1 8148 * and OUT2 bits still function in Loopback mode. The UART1 dtr_n, out1_n, and out2_n outputs are not 8149 * present on the pins of the chip, but the UART1 DTR, OUT1, and OUT2 bits still function in Loopback 8150 * mode. 8151 * 8152 * MCR bit 4 is the Loopback bit. When set, data on the sout line is held high, while serial data output 8153 * is looped back to the sin line, internally. In this mode all the interrupts are fully functional. This 8154 * feature is used for diagnostic purposes. Also, in loopback mode, the modem control inputs (dsr_n, 8155 * cts_n, ri_n, dcd_n) are disconnected and the four modem control outputs (dtr_n, rts_n, out1_n, out1_n) 8156 * are looped back to the inputs, internally. 8157 * 8158 * MCR bit 5 is the Auto Flow Control Enable (AFCE) bit. When FIFOs are enabled and this bit is set, 8159 * 16750-compatible Auto RTS and Auto CTS serial data flow control features are enabled. 8160 * 8161 * Auto RTS becomes active when the following occurs: 8162 * 1. MCR bit 1 is set 8163 * 2. FIFOs are enabled by setting FIFO Control Register (FCR) bit 0 8164 * 3. MCR bit 5 is set (must be set after FCR bit 0) 8165 * 8166 * When active, the rts_n output is forced inactive-high when the receiver FIFO level reaches the 8167 * threshold set by FCR[7:6]. When rts_n is connected to the cts_n input of another UART device, the 8168 * other UART stops sending serial data until the receiver FIFO has available space. 8169 * 8170 * The selectable receiver FIFO threshold values are: 1, 1/4, 1/2, and 2 less than full. Since one 8171 * additional character may be transmitted to the UART after rts_n has become inactive (due to data 8172 * already having entered the transmitter block in the other UART), setting the threshold to 2 less 8173 * than full allows maximum use of the FIFO with a safety zone of one character. 8174 * 8175 * Once the receiver FIFO becomes completely empty by reading the Receiver Buffer Register (RBR), rts_n 8176 * again becomes active-low, signalling the other UART to continue sending data. It is important to note 8177 * that, even if everything else is set to Enabled and the correct MCR bits are set, if the FIFOs are 8178 * disabled through FCR[0], Auto Flow Control is also disabled. When Auto RTS is disabled or inactive, 8179 * rts_n is controlled solely by MCR[1]. 8180 * 8181 * Auto CTS becomes active when the following occurs: 8182 * 1. FIFOs are enabled by setting FIFO Control Register (FCR) bit 0 8183 * 2. MCR bit 5 is set (must be set after FCR bit 0) 8184 * 8185 * When active, the UART transmitter is disabled whenever the cts_n input becomes inactive-high. This 8186 * prevents overflowing the FIFO of the receiving UART. 8187 * 8188 * Note that, if the cts_n input is not inactivated before the middle of the last stop bit, another 8189 * character is transmitted before the transmitter is disabled. While the transmitter is disabled, the 8190 * transmitter FIFO can still be written to, and even overflowed. Therefore, when using this mode, either 8191 * the true FIFO depth (64 characters) must be known to software, or the Programmable THRE Interrupt mode 8192 * must be enabled to access the FIFO full status through the Line Status Register. When using the FIFO 8193 * full status, software can poll this before each write to the Transmitter FIFO. 8194 * 8195 * Note: FIFO full status is also available in the UART Status Register (USR) or the actual level of the 8196 * FIFO may be read through the Transmit FIFO Level (TFL) register. 8197 * 8198 * When the cts_n input becomes active-low again, transmission resumes. It is important to note that, 8199 * even if everything else is set to Enabled, Auto Flow Control is also disabled if the FIFOs are 8200 * disabled through FCR[0]. When Auto CTS is disabled or inactive, the transmitter is unaffected by 8201 * cts_n. 8202 */ 8203union cvmx_mio_uartx_mcr { 8204 uint64_t u64; 8205 struct cvmx_mio_uartx_mcr_s { 8206#ifdef __BIG_ENDIAN_BITFIELD 8207 uint64_t reserved_6_63 : 58; 8208 uint64_t afce : 1; /**< Auto Flow Control Enable bit */ 8209 uint64_t loop : 1; /**< Loopback bit */ 8210 uint64_t out2 : 1; /**< OUT2 output bit */ 8211 uint64_t out1 : 1; /**< OUT1 output bit */ 8212 uint64_t rts : 1; /**< Request To Send output bit */ 8213 uint64_t dtr : 1; /**< Data Terminal Ready output bit */ 8214#else 8215 uint64_t dtr : 1; 8216 uint64_t rts : 1; 8217 uint64_t out1 : 1; 8218 uint64_t out2 : 1; 8219 uint64_t loop : 1; 8220 uint64_t afce : 1; 8221 uint64_t reserved_6_63 : 58; 8222#endif 8223 } s; 8224 struct cvmx_mio_uartx_mcr_s cn30xx; 8225 struct cvmx_mio_uartx_mcr_s cn31xx; 8226 struct cvmx_mio_uartx_mcr_s cn38xx; 8227 struct cvmx_mio_uartx_mcr_s cn38xxp2; 8228 struct cvmx_mio_uartx_mcr_s cn50xx; 8229 struct cvmx_mio_uartx_mcr_s cn52xx; 8230 struct cvmx_mio_uartx_mcr_s cn52xxp1; 8231 struct cvmx_mio_uartx_mcr_s cn56xx; 8232 struct cvmx_mio_uartx_mcr_s cn56xxp1; 8233 struct cvmx_mio_uartx_mcr_s cn58xx; 8234 struct cvmx_mio_uartx_mcr_s cn58xxp1; 8235 struct cvmx_mio_uartx_mcr_s cn61xx; 8236 struct cvmx_mio_uartx_mcr_s cn63xx; 8237 struct cvmx_mio_uartx_mcr_s cn63xxp1; 8238 struct cvmx_mio_uartx_mcr_s cn66xx; 8239 struct cvmx_mio_uartx_mcr_s cn68xx; 8240 struct cvmx_mio_uartx_mcr_s cn68xxp1; 8241 struct cvmx_mio_uartx_mcr_s cnf71xx; 8242}; 8243typedef union cvmx_mio_uartx_mcr cvmx_mio_uartx_mcr_t; 8244typedef cvmx_mio_uartx_mcr_t cvmx_uart_mcr_t; 8245 8246/** 8247 * cvmx_mio_uart#_msr 8248 * 8249 * MIO_UARTX_MSR = MIO UARTX Modem Status Register 8250 * 8251 * The Modem Status Register (MSR) contains the current status of the modem control input lines and if 8252 * they changed. 8253 * 8254 * DCTS (bit 0), DDSR (bit 1), and DDCD (bit 3) bits record whether the modem control lines (cts_n, 8255 * dsr_n, and dcd_n) have changed since the last time the user read the MSR. TERI (bit 2) indicates ri_n 8256 * has changed from an active-low, to an inactive-high state since the last time the MSR was read. In 8257 * Loopback mode, DCTS reflects changes on MCR bit 1 (RTS), DDSR reflects changes on MCR bit 0 (DTR), and 8258 * DDCD reflects changes on MCR bit 3 (Out2), while TERI reflects when MCR bit 2 (Out1) has changed state 8259 * from a high to a low. 8260 * 8261 * Note: if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software 8262 * or otherwise), then the DCTS bit will get set when the reset is removed if the cts_n signal remains 8263 * asserted. 8264 * 8265 * The CTS, DSR, RI, and DCD Modem Status bits contain information on the current state of the modem 8266 * control lines. CTS (bit 4) is the compliment of cts_n, DSR (bit 5) is the compliment of dsr_n, RI 8267 * (bit 6) is the compliment of ri_n, and DCD (bit 7) is the compliment of dcd_n. In Loopback mode, CTS 8268 * is the same as MCR bit 1 (RTS), DSR is the same as MCR bit 0 (DTR), RI is the same as MCR bit 2 8269 * (Out1), and DCD is the same as MCR bit 3 (Out2). 8270 * 8271 * Note: The UART0 dsr_n and ri_n inputs are internally tied to power and not present on the pins of chip. 8272 * Thus the UART0 DSR and RI bits will be '0' when not in Loopback mode. The UART1 dsr_n, ri_n, and dcd_n 8273 * inputs are internally tied to power and not present on the pins of chip. Thus the UART1 DSR, RI, and 8274 * DCD bits will be '0' when not in Loopback mode. 8275 */ 8276union cvmx_mio_uartx_msr { 8277 uint64_t u64; 8278 struct cvmx_mio_uartx_msr_s { 8279#ifdef __BIG_ENDIAN_BITFIELD 8280 uint64_t reserved_8_63 : 56; 8281 uint64_t dcd : 1; /**< Data Carrier Detect input bit */ 8282 uint64_t ri : 1; /**< Ring Indicator input bit */ 8283 uint64_t dsr : 1; /**< Data Set Ready input bit */ 8284 uint64_t cts : 1; /**< Clear To Send input bit */ 8285 uint64_t ddcd : 1; /**< Delta Data Carrier Detect bit */ 8286 uint64_t teri : 1; /**< Trailing Edge of Ring Indicator bit */ 8287 uint64_t ddsr : 1; /**< Delta Data Set Ready bit */ 8288 uint64_t dcts : 1; /**< Delta Clear To Send bit */ 8289#else 8290 uint64_t dcts : 1; 8291 uint64_t ddsr : 1; 8292 uint64_t teri : 1; 8293 uint64_t ddcd : 1; 8294 uint64_t cts : 1; 8295 uint64_t dsr : 1; 8296 uint64_t ri : 1; 8297 uint64_t dcd : 1; 8298 uint64_t reserved_8_63 : 56; 8299#endif 8300 } s; 8301 struct cvmx_mio_uartx_msr_s cn30xx; 8302 struct cvmx_mio_uartx_msr_s cn31xx; 8303 struct cvmx_mio_uartx_msr_s cn38xx; 8304 struct cvmx_mio_uartx_msr_s cn38xxp2; 8305 struct cvmx_mio_uartx_msr_s cn50xx; 8306 struct cvmx_mio_uartx_msr_s cn52xx; 8307 struct cvmx_mio_uartx_msr_s cn52xxp1; 8308 struct cvmx_mio_uartx_msr_s cn56xx; 8309 struct cvmx_mio_uartx_msr_s cn56xxp1; 8310 struct cvmx_mio_uartx_msr_s cn58xx; 8311 struct cvmx_mio_uartx_msr_s cn58xxp1; 8312 struct cvmx_mio_uartx_msr_s cn61xx; 8313 struct cvmx_mio_uartx_msr_s cn63xx; 8314 struct cvmx_mio_uartx_msr_s cn63xxp1; 8315 struct cvmx_mio_uartx_msr_s cn66xx; 8316 struct cvmx_mio_uartx_msr_s cn68xx; 8317 struct cvmx_mio_uartx_msr_s cn68xxp1; 8318 struct cvmx_mio_uartx_msr_s cnf71xx; 8319}; 8320typedef union cvmx_mio_uartx_msr cvmx_mio_uartx_msr_t; 8321typedef cvmx_mio_uartx_msr_t cvmx_uart_msr_t; 8322 8323/** 8324 * cvmx_mio_uart#_rbr 8325 * 8326 * MIO_UARTX_RBR = MIO UARTX Receive Buffer Register 8327 * 8328 * The Receive Buffer Register (RBR) is a read-only register that contains the data byte received on the 8329 * serial input port (sin). The data in this register is valid only if the Data Ready (DR) bit in the 8330 * Line status Register (LSR) is set. When the FIFOs are programmed OFF, the data in the RBR must be 8331 * read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. When 8332 * the FIFOs are programmed ON, this register accesses the head of the receive FIFO. If the receive FIFO 8333 * is full (64 characters) and this register is not read before the next data character arrives, then the 8334 * data already in the FIFO is preserved, but any incoming data is lost. An overrun error also occurs. 8335 * 8336 * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access 8337 * this register. 8338 * 8339 * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the 8340 * RBR, THR, and DLL registers are the same. 8341 */ 8342union cvmx_mio_uartx_rbr { 8343 uint64_t u64; 8344 struct cvmx_mio_uartx_rbr_s { 8345#ifdef __BIG_ENDIAN_BITFIELD 8346 uint64_t reserved_8_63 : 56; 8347 uint64_t rbr : 8; /**< Receive Buffer Register */ 8348#else 8349 uint64_t rbr : 8; 8350 uint64_t reserved_8_63 : 56; 8351#endif 8352 } s; 8353 struct cvmx_mio_uartx_rbr_s cn30xx; 8354 struct cvmx_mio_uartx_rbr_s cn31xx; 8355 struct cvmx_mio_uartx_rbr_s cn38xx; 8356 struct cvmx_mio_uartx_rbr_s cn38xxp2; 8357 struct cvmx_mio_uartx_rbr_s cn50xx; 8358 struct cvmx_mio_uartx_rbr_s cn52xx; 8359 struct cvmx_mio_uartx_rbr_s cn52xxp1; 8360 struct cvmx_mio_uartx_rbr_s cn56xx; 8361 struct cvmx_mio_uartx_rbr_s cn56xxp1; 8362 struct cvmx_mio_uartx_rbr_s cn58xx; 8363 struct cvmx_mio_uartx_rbr_s cn58xxp1; 8364 struct cvmx_mio_uartx_rbr_s cn61xx; 8365 struct cvmx_mio_uartx_rbr_s cn63xx; 8366 struct cvmx_mio_uartx_rbr_s cn63xxp1; 8367 struct cvmx_mio_uartx_rbr_s cn66xx; 8368 struct cvmx_mio_uartx_rbr_s cn68xx; 8369 struct cvmx_mio_uartx_rbr_s cn68xxp1; 8370 struct cvmx_mio_uartx_rbr_s cnf71xx; 8371}; 8372typedef union cvmx_mio_uartx_rbr cvmx_mio_uartx_rbr_t; 8373typedef cvmx_mio_uartx_rbr_t cvmx_uart_rbr_t; 8374 8375/** 8376 * cvmx_mio_uart#_rfl 8377 * 8378 * MIO_UARTX_RFL = MIO UARTX Receive FIFO Level Register 8379 * 8380 * The Receive FIFO Level Register (RFL) indicates the number of data entries in the receive FIFO. 8381 */ 8382union cvmx_mio_uartx_rfl { 8383 uint64_t u64; 8384 struct cvmx_mio_uartx_rfl_s { 8385#ifdef __BIG_ENDIAN_BITFIELD 8386 uint64_t reserved_7_63 : 57; 8387 uint64_t rfl : 7; /**< Receive FIFO Level Register */ 8388#else 8389 uint64_t rfl : 7; 8390 uint64_t reserved_7_63 : 57; 8391#endif 8392 } s; 8393 struct cvmx_mio_uartx_rfl_s cn30xx; 8394 struct cvmx_mio_uartx_rfl_s cn31xx; 8395 struct cvmx_mio_uartx_rfl_s cn38xx; 8396 struct cvmx_mio_uartx_rfl_s cn38xxp2; 8397 struct cvmx_mio_uartx_rfl_s cn50xx; 8398 struct cvmx_mio_uartx_rfl_s cn52xx; 8399 struct cvmx_mio_uartx_rfl_s cn52xxp1; 8400 struct cvmx_mio_uartx_rfl_s cn56xx; 8401 struct cvmx_mio_uartx_rfl_s cn56xxp1; 8402 struct cvmx_mio_uartx_rfl_s cn58xx; 8403 struct cvmx_mio_uartx_rfl_s cn58xxp1; 8404 struct cvmx_mio_uartx_rfl_s cn61xx; 8405 struct cvmx_mio_uartx_rfl_s cn63xx; 8406 struct cvmx_mio_uartx_rfl_s cn63xxp1; 8407 struct cvmx_mio_uartx_rfl_s cn66xx; 8408 struct cvmx_mio_uartx_rfl_s cn68xx; 8409 struct cvmx_mio_uartx_rfl_s cn68xxp1; 8410 struct cvmx_mio_uartx_rfl_s cnf71xx; 8411}; 8412typedef union cvmx_mio_uartx_rfl cvmx_mio_uartx_rfl_t; 8413typedef cvmx_mio_uartx_rfl_t cvmx_uart_rfl_t; 8414 8415/** 8416 * cvmx_mio_uart#_rfw 8417 * 8418 * MIO_UARTX_RFW = MIO UARTX Receive FIFO Write Register 8419 * 8420 * The Receive FIFO Write Register (RFW) is only valid when FIFO access mode is enabled (FAR bit 0 is 8421 * set). When FIFOs are enabled, this register is used to write data to the receive FIFO. Each 8422 * consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are 8423 * not enabled, this register is used to write data to the RBR. 8424 */ 8425union cvmx_mio_uartx_rfw { 8426 uint64_t u64; 8427 struct cvmx_mio_uartx_rfw_s { 8428#ifdef __BIG_ENDIAN_BITFIELD 8429 uint64_t reserved_10_63 : 54; 8430 uint64_t rffe : 1; /**< Receive FIFO Framing Error */ 8431 uint64_t rfpe : 1; /**< Receive FIFO Parity Error */ 8432 uint64_t rfwd : 8; /**< Receive FIFO Write Data */ 8433#else 8434 uint64_t rfwd : 8; 8435 uint64_t rfpe : 1; 8436 uint64_t rffe : 1; 8437 uint64_t reserved_10_63 : 54; 8438#endif 8439 } s; 8440 struct cvmx_mio_uartx_rfw_s cn30xx; 8441 struct cvmx_mio_uartx_rfw_s cn31xx; 8442 struct cvmx_mio_uartx_rfw_s cn38xx; 8443 struct cvmx_mio_uartx_rfw_s cn38xxp2; 8444 struct cvmx_mio_uartx_rfw_s cn50xx; 8445 struct cvmx_mio_uartx_rfw_s cn52xx; 8446 struct cvmx_mio_uartx_rfw_s cn52xxp1; 8447 struct cvmx_mio_uartx_rfw_s cn56xx; 8448 struct cvmx_mio_uartx_rfw_s cn56xxp1; 8449 struct cvmx_mio_uartx_rfw_s cn58xx; 8450 struct cvmx_mio_uartx_rfw_s cn58xxp1; 8451 struct cvmx_mio_uartx_rfw_s cn61xx; 8452 struct cvmx_mio_uartx_rfw_s cn63xx; 8453 struct cvmx_mio_uartx_rfw_s cn63xxp1; 8454 struct cvmx_mio_uartx_rfw_s cn66xx; 8455 struct cvmx_mio_uartx_rfw_s cn68xx; 8456 struct cvmx_mio_uartx_rfw_s cn68xxp1; 8457 struct cvmx_mio_uartx_rfw_s cnf71xx; 8458}; 8459typedef union cvmx_mio_uartx_rfw cvmx_mio_uartx_rfw_t; 8460typedef cvmx_mio_uartx_rfw_t cvmx_uart_rfw_t; 8461 8462/** 8463 * cvmx_mio_uart#_sbcr 8464 * 8465 * MIO_UARTX_SBCR = MIO UARTX Shadow Break Control Register 8466 * 8467 * The Shadow Break Control Register (SBCR) is a shadow register for the BREAK bit (LCR bit 6) that can 8468 * be used to remove the burden of having to perform a read-modify-write on the LCR. 8469 */ 8470union cvmx_mio_uartx_sbcr { 8471 uint64_t u64; 8472 struct cvmx_mio_uartx_sbcr_s { 8473#ifdef __BIG_ENDIAN_BITFIELD 8474 uint64_t reserved_1_63 : 63; 8475 uint64_t sbcr : 1; /**< Shadow Break Control */ 8476#else 8477 uint64_t sbcr : 1; 8478 uint64_t reserved_1_63 : 63; 8479#endif 8480 } s; 8481 struct cvmx_mio_uartx_sbcr_s cn30xx; 8482 struct cvmx_mio_uartx_sbcr_s cn31xx; 8483 struct cvmx_mio_uartx_sbcr_s cn38xx; 8484 struct cvmx_mio_uartx_sbcr_s cn38xxp2; 8485 struct cvmx_mio_uartx_sbcr_s cn50xx; 8486 struct cvmx_mio_uartx_sbcr_s cn52xx; 8487 struct cvmx_mio_uartx_sbcr_s cn52xxp1; 8488 struct cvmx_mio_uartx_sbcr_s cn56xx; 8489 struct cvmx_mio_uartx_sbcr_s cn56xxp1; 8490 struct cvmx_mio_uartx_sbcr_s cn58xx; 8491 struct cvmx_mio_uartx_sbcr_s cn58xxp1; 8492 struct cvmx_mio_uartx_sbcr_s cn61xx; 8493 struct cvmx_mio_uartx_sbcr_s cn63xx; 8494 struct cvmx_mio_uartx_sbcr_s cn63xxp1; 8495 struct cvmx_mio_uartx_sbcr_s cn66xx; 8496 struct cvmx_mio_uartx_sbcr_s cn68xx; 8497 struct cvmx_mio_uartx_sbcr_s cn68xxp1; 8498 struct cvmx_mio_uartx_sbcr_s cnf71xx; 8499}; 8500typedef union cvmx_mio_uartx_sbcr cvmx_mio_uartx_sbcr_t; 8501typedef cvmx_mio_uartx_sbcr_t cvmx_uart_sbcr_t; 8502 8503/** 8504 * cvmx_mio_uart#_scr 8505 * 8506 * MIO_UARTX_SCR = MIO UARTX Scratchpad Register 8507 * 8508 * The Scratchpad Register (SCR) is an 8-bit read/write register for programmers to use as a temporary 8509 * storage space. 8510 */ 8511union cvmx_mio_uartx_scr { 8512 uint64_t u64; 8513 struct cvmx_mio_uartx_scr_s { 8514#ifdef __BIG_ENDIAN_BITFIELD 8515 uint64_t reserved_8_63 : 56; 8516 uint64_t scr : 8; /**< Scratchpad Register */ 8517#else 8518 uint64_t scr : 8; 8519 uint64_t reserved_8_63 : 56; 8520#endif 8521 } s; 8522 struct cvmx_mio_uartx_scr_s cn30xx; 8523 struct cvmx_mio_uartx_scr_s cn31xx; 8524 struct cvmx_mio_uartx_scr_s cn38xx; 8525 struct cvmx_mio_uartx_scr_s cn38xxp2; 8526 struct cvmx_mio_uartx_scr_s cn50xx; 8527 struct cvmx_mio_uartx_scr_s cn52xx; 8528 struct cvmx_mio_uartx_scr_s cn52xxp1; 8529 struct cvmx_mio_uartx_scr_s cn56xx; 8530 struct cvmx_mio_uartx_scr_s cn56xxp1; 8531 struct cvmx_mio_uartx_scr_s cn58xx; 8532 struct cvmx_mio_uartx_scr_s cn58xxp1; 8533 struct cvmx_mio_uartx_scr_s cn61xx; 8534 struct cvmx_mio_uartx_scr_s cn63xx; 8535 struct cvmx_mio_uartx_scr_s cn63xxp1; 8536 struct cvmx_mio_uartx_scr_s cn66xx; 8537 struct cvmx_mio_uartx_scr_s cn68xx; 8538 struct cvmx_mio_uartx_scr_s cn68xxp1; 8539 struct cvmx_mio_uartx_scr_s cnf71xx; 8540}; 8541typedef union cvmx_mio_uartx_scr cvmx_mio_uartx_scr_t; 8542typedef cvmx_mio_uartx_scr_t cvmx_uart_scr_t; 8543 8544/** 8545 * cvmx_mio_uart#_sfe 8546 * 8547 * MIO_UARTX_SFE = MIO UARTX Shadow FIFO Enable Register 8548 * 8549 * The Shadow FIFO Enable Register (SFE) is a shadow register for the FIFO enable bit (FCR bit 0) that 8550 * can be used to remove the burden of having to store the previously written value to the FCR in memory 8551 * and having to mask this value so that only the FIFO enable bit gets updated. 8552 */ 8553union cvmx_mio_uartx_sfe { 8554 uint64_t u64; 8555 struct cvmx_mio_uartx_sfe_s { 8556#ifdef __BIG_ENDIAN_BITFIELD 8557 uint64_t reserved_1_63 : 63; 8558 uint64_t sfe : 1; /**< Shadow FIFO Enable */ 8559#else 8560 uint64_t sfe : 1; 8561 uint64_t reserved_1_63 : 63; 8562#endif 8563 } s; 8564 struct cvmx_mio_uartx_sfe_s cn30xx; 8565 struct cvmx_mio_uartx_sfe_s cn31xx; 8566 struct cvmx_mio_uartx_sfe_s cn38xx; 8567 struct cvmx_mio_uartx_sfe_s cn38xxp2; 8568 struct cvmx_mio_uartx_sfe_s cn50xx; 8569 struct cvmx_mio_uartx_sfe_s cn52xx; 8570 struct cvmx_mio_uartx_sfe_s cn52xxp1; 8571 struct cvmx_mio_uartx_sfe_s cn56xx; 8572 struct cvmx_mio_uartx_sfe_s cn56xxp1; 8573 struct cvmx_mio_uartx_sfe_s cn58xx; 8574 struct cvmx_mio_uartx_sfe_s cn58xxp1; 8575 struct cvmx_mio_uartx_sfe_s cn61xx; 8576 struct cvmx_mio_uartx_sfe_s cn63xx; 8577 struct cvmx_mio_uartx_sfe_s cn63xxp1; 8578 struct cvmx_mio_uartx_sfe_s cn66xx; 8579 struct cvmx_mio_uartx_sfe_s cn68xx; 8580 struct cvmx_mio_uartx_sfe_s cn68xxp1; 8581 struct cvmx_mio_uartx_sfe_s cnf71xx; 8582}; 8583typedef union cvmx_mio_uartx_sfe cvmx_mio_uartx_sfe_t; 8584typedef cvmx_mio_uartx_sfe_t cvmx_uart_sfe_t; 8585 8586/** 8587 * cvmx_mio_uart#_srr 8588 * 8589 * MIO_UARTX_SRR = MIO UARTX Software Reset Register 8590 * 8591 * The Software Reset Register (SRR) is a write-only register that resets the UART and/or the receive 8592 * FIFO and/or the transmit FIFO. 8593 * 8594 * Bit 0 of the SRR is the UART Soft Reset (USR) bit. Setting this bit resets the UART. 8595 * 8596 * Bit 1 of the SRR is a shadow copy of the RX FIFO Reset bit (FCR bit 1). This can be used to remove 8597 * the burden on software having to store previously written FCR values (which are pretty static) just 8598 * to reset the receive FIFO. 8599 * 8600 * Bit 2 of the SRR is a shadow copy of the TX FIFO Reset bit (FCR bit 2). This can be used to remove 8601 * the burden on software having to store previously written FCR values (which are pretty static) just 8602 * to reset the transmit FIFO. 8603 */ 8604union cvmx_mio_uartx_srr { 8605 uint64_t u64; 8606 struct cvmx_mio_uartx_srr_s { 8607#ifdef __BIG_ENDIAN_BITFIELD 8608 uint64_t reserved_3_63 : 61; 8609 uint64_t stfr : 1; /**< Shadow TX FIFO Reset */ 8610 uint64_t srfr : 1; /**< Shadow RX FIFO Reset */ 8611 uint64_t usr : 1; /**< UART Soft Reset */ 8612#else 8613 uint64_t usr : 1; 8614 uint64_t srfr : 1; 8615 uint64_t stfr : 1; 8616 uint64_t reserved_3_63 : 61; 8617#endif 8618 } s; 8619 struct cvmx_mio_uartx_srr_s cn30xx; 8620 struct cvmx_mio_uartx_srr_s cn31xx; 8621 struct cvmx_mio_uartx_srr_s cn38xx; 8622 struct cvmx_mio_uartx_srr_s cn38xxp2; 8623 struct cvmx_mio_uartx_srr_s cn50xx; 8624 struct cvmx_mio_uartx_srr_s cn52xx; 8625 struct cvmx_mio_uartx_srr_s cn52xxp1; 8626 struct cvmx_mio_uartx_srr_s cn56xx; 8627 struct cvmx_mio_uartx_srr_s cn56xxp1; 8628 struct cvmx_mio_uartx_srr_s cn58xx; 8629 struct cvmx_mio_uartx_srr_s cn58xxp1; 8630 struct cvmx_mio_uartx_srr_s cn61xx; 8631 struct cvmx_mio_uartx_srr_s cn63xx; 8632 struct cvmx_mio_uartx_srr_s cn63xxp1; 8633 struct cvmx_mio_uartx_srr_s cn66xx; 8634 struct cvmx_mio_uartx_srr_s cn68xx; 8635 struct cvmx_mio_uartx_srr_s cn68xxp1; 8636 struct cvmx_mio_uartx_srr_s cnf71xx; 8637}; 8638typedef union cvmx_mio_uartx_srr cvmx_mio_uartx_srr_t; 8639typedef cvmx_mio_uartx_srr_t cvmx_uart_srr_t; 8640 8641/** 8642 * cvmx_mio_uart#_srt 8643 * 8644 * MIO_UARTX_SRT = MIO UARTX Shadow RX Trigger Register 8645 * 8646 * The Shadow RX Trigger Register (SRT) is a shadow register for the RX Trigger bits (FCR bits 7:6) that 8647 * can be used to remove the burden of having to store the previously written value to the FCR in memory 8648 * and having to mask this value so that only the RX Trigger bits get updated. 8649 */ 8650union cvmx_mio_uartx_srt { 8651 uint64_t u64; 8652 struct cvmx_mio_uartx_srt_s { 8653#ifdef __BIG_ENDIAN_BITFIELD 8654 uint64_t reserved_2_63 : 62; 8655 uint64_t srt : 2; /**< Shadow RX Trigger */ 8656#else 8657 uint64_t srt : 2; 8658 uint64_t reserved_2_63 : 62; 8659#endif 8660 } s; 8661 struct cvmx_mio_uartx_srt_s cn30xx; 8662 struct cvmx_mio_uartx_srt_s cn31xx; 8663 struct cvmx_mio_uartx_srt_s cn38xx; 8664 struct cvmx_mio_uartx_srt_s cn38xxp2; 8665 struct cvmx_mio_uartx_srt_s cn50xx; 8666 struct cvmx_mio_uartx_srt_s cn52xx; 8667 struct cvmx_mio_uartx_srt_s cn52xxp1; 8668 struct cvmx_mio_uartx_srt_s cn56xx; 8669 struct cvmx_mio_uartx_srt_s cn56xxp1; 8670 struct cvmx_mio_uartx_srt_s cn58xx; 8671 struct cvmx_mio_uartx_srt_s cn58xxp1; 8672 struct cvmx_mio_uartx_srt_s cn61xx; 8673 struct cvmx_mio_uartx_srt_s cn63xx; 8674 struct cvmx_mio_uartx_srt_s cn63xxp1; 8675 struct cvmx_mio_uartx_srt_s cn66xx; 8676 struct cvmx_mio_uartx_srt_s cn68xx; 8677 struct cvmx_mio_uartx_srt_s cn68xxp1; 8678 struct cvmx_mio_uartx_srt_s cnf71xx; 8679}; 8680typedef union cvmx_mio_uartx_srt cvmx_mio_uartx_srt_t; 8681typedef cvmx_mio_uartx_srt_t cvmx_uart_srt_t; 8682 8683/** 8684 * cvmx_mio_uart#_srts 8685 * 8686 * MIO_UARTX_SRTS = MIO UARTX Shadow Request To Send Register 8687 * 8688 * The Shadow Request To Send Register (SRTS) is a shadow register for the RTS bit (MCR bit 1) that can 8689 * be used to remove the burden of having to perform a read-modify-write on the MCR. 8690 */ 8691union cvmx_mio_uartx_srts { 8692 uint64_t u64; 8693 struct cvmx_mio_uartx_srts_s { 8694#ifdef __BIG_ENDIAN_BITFIELD 8695 uint64_t reserved_1_63 : 63; 8696 uint64_t srts : 1; /**< Shadow Request To Send */ 8697#else 8698 uint64_t srts : 1; 8699 uint64_t reserved_1_63 : 63; 8700#endif 8701 } s; 8702 struct cvmx_mio_uartx_srts_s cn30xx; 8703 struct cvmx_mio_uartx_srts_s cn31xx; 8704 struct cvmx_mio_uartx_srts_s cn38xx; 8705 struct cvmx_mio_uartx_srts_s cn38xxp2; 8706 struct cvmx_mio_uartx_srts_s cn50xx; 8707 struct cvmx_mio_uartx_srts_s cn52xx; 8708 struct cvmx_mio_uartx_srts_s cn52xxp1; 8709 struct cvmx_mio_uartx_srts_s cn56xx; 8710 struct cvmx_mio_uartx_srts_s cn56xxp1; 8711 struct cvmx_mio_uartx_srts_s cn58xx; 8712 struct cvmx_mio_uartx_srts_s cn58xxp1; 8713 struct cvmx_mio_uartx_srts_s cn61xx; 8714 struct cvmx_mio_uartx_srts_s cn63xx; 8715 struct cvmx_mio_uartx_srts_s cn63xxp1; 8716 struct cvmx_mio_uartx_srts_s cn66xx; 8717 struct cvmx_mio_uartx_srts_s cn68xx; 8718 struct cvmx_mio_uartx_srts_s cn68xxp1; 8719 struct cvmx_mio_uartx_srts_s cnf71xx; 8720}; 8721typedef union cvmx_mio_uartx_srts cvmx_mio_uartx_srts_t; 8722typedef cvmx_mio_uartx_srts_t cvmx_uart_srts_t; 8723 8724/** 8725 * cvmx_mio_uart#_stt 8726 * 8727 * MIO_UARTX_STT = MIO UARTX Shadow TX Trigger Register 8728 * 8729 * The Shadow TX Trigger Register (STT) is a shadow register for the TX Trigger bits (FCR bits 5:4) that 8730 * can be used to remove the burden of having to store the previously written value to the FCR in memory 8731 * and having to mask this value so that only the TX Trigger bits get updated. 8732 */ 8733union cvmx_mio_uartx_stt { 8734 uint64_t u64; 8735 struct cvmx_mio_uartx_stt_s { 8736#ifdef __BIG_ENDIAN_BITFIELD 8737 uint64_t reserved_2_63 : 62; 8738 uint64_t stt : 2; /**< Shadow TX Trigger */ 8739#else 8740 uint64_t stt : 2; 8741 uint64_t reserved_2_63 : 62; 8742#endif 8743 } s; 8744 struct cvmx_mio_uartx_stt_s cn30xx; 8745 struct cvmx_mio_uartx_stt_s cn31xx; 8746 struct cvmx_mio_uartx_stt_s cn38xx; 8747 struct cvmx_mio_uartx_stt_s cn38xxp2; 8748 struct cvmx_mio_uartx_stt_s cn50xx; 8749 struct cvmx_mio_uartx_stt_s cn52xx; 8750 struct cvmx_mio_uartx_stt_s cn52xxp1; 8751 struct cvmx_mio_uartx_stt_s cn56xx; 8752 struct cvmx_mio_uartx_stt_s cn56xxp1; 8753 struct cvmx_mio_uartx_stt_s cn58xx; 8754 struct cvmx_mio_uartx_stt_s cn58xxp1; 8755 struct cvmx_mio_uartx_stt_s cn61xx; 8756 struct cvmx_mio_uartx_stt_s cn63xx; 8757 struct cvmx_mio_uartx_stt_s cn63xxp1; 8758 struct cvmx_mio_uartx_stt_s cn66xx; 8759 struct cvmx_mio_uartx_stt_s cn68xx; 8760 struct cvmx_mio_uartx_stt_s cn68xxp1; 8761 struct cvmx_mio_uartx_stt_s cnf71xx; 8762}; 8763typedef union cvmx_mio_uartx_stt cvmx_mio_uartx_stt_t; 8764typedef cvmx_mio_uartx_stt_t cvmx_uart_stt_t; 8765 8766/** 8767 * cvmx_mio_uart#_tfl 8768 * 8769 * MIO_UARTX_TFL = MIO UARTX Transmit FIFO Level Register 8770 * 8771 * The Transmit FIFO Level Register (TFL) indicates the number of data entries in the transmit FIFO. 8772 */ 8773union cvmx_mio_uartx_tfl { 8774 uint64_t u64; 8775 struct cvmx_mio_uartx_tfl_s { 8776#ifdef __BIG_ENDIAN_BITFIELD 8777 uint64_t reserved_7_63 : 57; 8778 uint64_t tfl : 7; /**< Transmit FIFO Level Register */ 8779#else 8780 uint64_t tfl : 7; 8781 uint64_t reserved_7_63 : 57; 8782#endif 8783 } s; 8784 struct cvmx_mio_uartx_tfl_s cn30xx; 8785 struct cvmx_mio_uartx_tfl_s cn31xx; 8786 struct cvmx_mio_uartx_tfl_s cn38xx; 8787 struct cvmx_mio_uartx_tfl_s cn38xxp2; 8788 struct cvmx_mio_uartx_tfl_s cn50xx; 8789 struct cvmx_mio_uartx_tfl_s cn52xx; 8790 struct cvmx_mio_uartx_tfl_s cn52xxp1; 8791 struct cvmx_mio_uartx_tfl_s cn56xx; 8792 struct cvmx_mio_uartx_tfl_s cn56xxp1; 8793 struct cvmx_mio_uartx_tfl_s cn58xx; 8794 struct cvmx_mio_uartx_tfl_s cn58xxp1; 8795 struct cvmx_mio_uartx_tfl_s cn61xx; 8796 struct cvmx_mio_uartx_tfl_s cn63xx; 8797 struct cvmx_mio_uartx_tfl_s cn63xxp1; 8798 struct cvmx_mio_uartx_tfl_s cn66xx; 8799 struct cvmx_mio_uartx_tfl_s cn68xx; 8800 struct cvmx_mio_uartx_tfl_s cn68xxp1; 8801 struct cvmx_mio_uartx_tfl_s cnf71xx; 8802}; 8803typedef union cvmx_mio_uartx_tfl cvmx_mio_uartx_tfl_t; 8804typedef cvmx_mio_uartx_tfl_t cvmx_uart_tfl_t; 8805 8806/** 8807 * cvmx_mio_uart#_tfr 8808 * 8809 * MIO_UARTX_TFR = MIO UARTX Transmit FIFO Read Register 8810 * 8811 * The Transmit FIFO Read Register (TFR) is only valid when FIFO access mode is enabled (FAR bit 0 is 8812 * set). When FIFOs are enabled, reading this register gives the data at the top of the transmit FIFO. 8813 * Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the 8814 * top of the FIFO. When FIFOs are not enabled, reading this register gives the data in the THR. 8815 */ 8816union cvmx_mio_uartx_tfr { 8817 uint64_t u64; 8818 struct cvmx_mio_uartx_tfr_s { 8819#ifdef __BIG_ENDIAN_BITFIELD 8820 uint64_t reserved_8_63 : 56; 8821 uint64_t tfr : 8; /**< Transmit FIFO Read Register */ 8822#else 8823 uint64_t tfr : 8; 8824 uint64_t reserved_8_63 : 56; 8825#endif 8826 } s; 8827 struct cvmx_mio_uartx_tfr_s cn30xx; 8828 struct cvmx_mio_uartx_tfr_s cn31xx; 8829 struct cvmx_mio_uartx_tfr_s cn38xx; 8830 struct cvmx_mio_uartx_tfr_s cn38xxp2; 8831 struct cvmx_mio_uartx_tfr_s cn50xx; 8832 struct cvmx_mio_uartx_tfr_s cn52xx; 8833 struct cvmx_mio_uartx_tfr_s cn52xxp1; 8834 struct cvmx_mio_uartx_tfr_s cn56xx; 8835 struct cvmx_mio_uartx_tfr_s cn56xxp1; 8836 struct cvmx_mio_uartx_tfr_s cn58xx; 8837 struct cvmx_mio_uartx_tfr_s cn58xxp1; 8838 struct cvmx_mio_uartx_tfr_s cn61xx; 8839 struct cvmx_mio_uartx_tfr_s cn63xx; 8840 struct cvmx_mio_uartx_tfr_s cn63xxp1; 8841 struct cvmx_mio_uartx_tfr_s cn66xx; 8842 struct cvmx_mio_uartx_tfr_s cn68xx; 8843 struct cvmx_mio_uartx_tfr_s cn68xxp1; 8844 struct cvmx_mio_uartx_tfr_s cnf71xx; 8845}; 8846typedef union cvmx_mio_uartx_tfr cvmx_mio_uartx_tfr_t; 8847typedef cvmx_mio_uartx_tfr_t cvmx_uart_tfr_t; 8848 8849/** 8850 * cvmx_mio_uart#_thr 8851 * 8852 * MIO_UARTX_THR = MIO UARTX Transmit Holding Register 8853 * 8854 * Transmit Holding Register (THR) is a write-only register that contains data to be transmitted on the 8855 * serial output port (sout). Data can be written to the THR any time that the THR Empty (THRE) bit of 8856 * the Line Status Register (LSR) is set. 8857 * 8858 * If FIFOs are not enabled and THRE is set, writing a single character to the THR clears the THRE. Any 8859 * additional writes to the THR before the THRE is set again causes the THR data to be overwritten. 8860 * 8861 * If FIFOs are enabled and THRE is set (and Programmable THRE mode disabled), 64 characters of data may 8862 * be written to the THR before the FIFO is full. Any attempt to write data when the FIFO is full results 8863 * in the write data being lost. 8864 * 8865 * Note: The Divisor Latch Address Bit (DLAB) of the Line Control Register (LCR) must be clear to access 8866 * this register. 8867 * 8868 * Note: The address below is an alias to simplify these CSR descriptions. It should be known that the 8869 * RBR, THR, and DLL registers are the same. 8870 */ 8871union cvmx_mio_uartx_thr { 8872 uint64_t u64; 8873 struct cvmx_mio_uartx_thr_s { 8874#ifdef __BIG_ENDIAN_BITFIELD 8875 uint64_t reserved_8_63 : 56; 8876 uint64_t thr : 8; /**< Transmit Holding Register */ 8877#else 8878 uint64_t thr : 8; 8879 uint64_t reserved_8_63 : 56; 8880#endif 8881 } s; 8882 struct cvmx_mio_uartx_thr_s cn30xx; 8883 struct cvmx_mio_uartx_thr_s cn31xx; 8884 struct cvmx_mio_uartx_thr_s cn38xx; 8885 struct cvmx_mio_uartx_thr_s cn38xxp2; 8886 struct cvmx_mio_uartx_thr_s cn50xx; 8887 struct cvmx_mio_uartx_thr_s cn52xx; 8888 struct cvmx_mio_uartx_thr_s cn52xxp1; 8889 struct cvmx_mio_uartx_thr_s cn56xx; 8890 struct cvmx_mio_uartx_thr_s cn56xxp1; 8891 struct cvmx_mio_uartx_thr_s cn58xx; 8892 struct cvmx_mio_uartx_thr_s cn58xxp1; 8893 struct cvmx_mio_uartx_thr_s cn61xx; 8894 struct cvmx_mio_uartx_thr_s cn63xx; 8895 struct cvmx_mio_uartx_thr_s cn63xxp1; 8896 struct cvmx_mio_uartx_thr_s cn66xx; 8897 struct cvmx_mio_uartx_thr_s cn68xx; 8898 struct cvmx_mio_uartx_thr_s cn68xxp1; 8899 struct cvmx_mio_uartx_thr_s cnf71xx; 8900}; 8901typedef union cvmx_mio_uartx_thr cvmx_mio_uartx_thr_t; 8902typedef cvmx_mio_uartx_thr_t cvmx_uart_thr_t; 8903 8904/** 8905 * cvmx_mio_uart#_usr 8906 * 8907 * MIO_UARTX_USR = MIO UARTX UART Status Register 8908 * 8909 * The UART Status Register (USR) contains UART status information. 8910 * 8911 * USR bit 0 is the BUSY bit. When set this bit indicates that a serial transfer is in progress, when 8912 * clear it indicates that the UART is idle or inactive. 8913 * 8914 * Note: In PASS3, the BUSY bit will always be clear. 8915 * 8916 * USR bits 1-4 indicate the following FIFO status: TX FIFO Not Full (TFNF), TX FIFO Empty (TFE), RX 8917 * FIFO Not Empty (RFNE), and RX FIFO Full (RFF). 8918 */ 8919union cvmx_mio_uartx_usr { 8920 uint64_t u64; 8921 struct cvmx_mio_uartx_usr_s { 8922#ifdef __BIG_ENDIAN_BITFIELD 8923 uint64_t reserved_5_63 : 59; 8924 uint64_t rff : 1; /**< RX FIFO Full */ 8925 uint64_t rfne : 1; /**< RX FIFO Not Empty */ 8926 uint64_t tfe : 1; /**< TX FIFO Empty */ 8927 uint64_t tfnf : 1; /**< TX FIFO Not Full */ 8928 uint64_t busy : 1; /**< Busy bit (always 0 in PASS3) */ 8929#else 8930 uint64_t busy : 1; 8931 uint64_t tfnf : 1; 8932 uint64_t tfe : 1; 8933 uint64_t rfne : 1; 8934 uint64_t rff : 1; 8935 uint64_t reserved_5_63 : 59; 8936#endif 8937 } s; 8938 struct cvmx_mio_uartx_usr_s cn30xx; 8939 struct cvmx_mio_uartx_usr_s cn31xx; 8940 struct cvmx_mio_uartx_usr_s cn38xx; 8941 struct cvmx_mio_uartx_usr_s cn38xxp2; 8942 struct cvmx_mio_uartx_usr_s cn50xx; 8943 struct cvmx_mio_uartx_usr_s cn52xx; 8944 struct cvmx_mio_uartx_usr_s cn52xxp1; 8945 struct cvmx_mio_uartx_usr_s cn56xx; 8946 struct cvmx_mio_uartx_usr_s cn56xxp1; 8947 struct cvmx_mio_uartx_usr_s cn58xx; 8948 struct cvmx_mio_uartx_usr_s cn58xxp1; 8949 struct cvmx_mio_uartx_usr_s cn61xx; 8950 struct cvmx_mio_uartx_usr_s cn63xx; 8951 struct cvmx_mio_uartx_usr_s cn63xxp1; 8952 struct cvmx_mio_uartx_usr_s cn66xx; 8953 struct cvmx_mio_uartx_usr_s cn68xx; 8954 struct cvmx_mio_uartx_usr_s cn68xxp1; 8955 struct cvmx_mio_uartx_usr_s cnf71xx; 8956}; 8957typedef union cvmx_mio_uartx_usr cvmx_mio_uartx_usr_t; 8958typedef cvmx_mio_uartx_usr_t cvmx_uart_usr_t; 8959 8960/** 8961 * cvmx_mio_uart2_dlh 8962 */ 8963union cvmx_mio_uart2_dlh { 8964 uint64_t u64; 8965 struct cvmx_mio_uart2_dlh_s { 8966#ifdef __BIG_ENDIAN_BITFIELD 8967 uint64_t reserved_8_63 : 56; 8968 uint64_t dlh : 8; /**< Divisor Latch High Register */ 8969#else 8970 uint64_t dlh : 8; 8971 uint64_t reserved_8_63 : 56; 8972#endif 8973 } s; 8974 struct cvmx_mio_uart2_dlh_s cn52xx; 8975 struct cvmx_mio_uart2_dlh_s cn52xxp1; 8976}; 8977typedef union cvmx_mio_uart2_dlh cvmx_mio_uart2_dlh_t; 8978 8979/** 8980 * cvmx_mio_uart2_dll 8981 */ 8982union cvmx_mio_uart2_dll { 8983 uint64_t u64; 8984 struct cvmx_mio_uart2_dll_s { 8985#ifdef __BIG_ENDIAN_BITFIELD 8986 uint64_t reserved_8_63 : 56; 8987 uint64_t dll : 8; /**< Divisor Latch Low Register */ 8988#else 8989 uint64_t dll : 8; 8990 uint64_t reserved_8_63 : 56; 8991#endif 8992 } s; 8993 struct cvmx_mio_uart2_dll_s cn52xx; 8994 struct cvmx_mio_uart2_dll_s cn52xxp1; 8995}; 8996typedef union cvmx_mio_uart2_dll cvmx_mio_uart2_dll_t; 8997 8998/** 8999 * cvmx_mio_uart2_far 9000 */ 9001union cvmx_mio_uart2_far { 9002 uint64_t u64; 9003 struct cvmx_mio_uart2_far_s { 9004#ifdef __BIG_ENDIAN_BITFIELD 9005 uint64_t reserved_1_63 : 63; 9006 uint64_t far : 1; /**< FIFO Access Register */ 9007#else 9008 uint64_t far : 1; 9009 uint64_t reserved_1_63 : 63; 9010#endif 9011 } s; 9012 struct cvmx_mio_uart2_far_s cn52xx; 9013 struct cvmx_mio_uart2_far_s cn52xxp1; 9014}; 9015typedef union cvmx_mio_uart2_far cvmx_mio_uart2_far_t; 9016 9017/** 9018 * cvmx_mio_uart2_fcr 9019 */ 9020union cvmx_mio_uart2_fcr { 9021 uint64_t u64; 9022 struct cvmx_mio_uart2_fcr_s { 9023#ifdef __BIG_ENDIAN_BITFIELD 9024 uint64_t reserved_8_63 : 56; 9025 uint64_t rxtrig : 2; /**< RX Trigger */ 9026 uint64_t txtrig : 2; /**< TX Trigger */ 9027 uint64_t reserved_3_3 : 1; 9028 uint64_t txfr : 1; /**< TX FIFO reset */ 9029 uint64_t rxfr : 1; /**< RX FIFO reset */ 9030 uint64_t en : 1; /**< FIFO enable */ 9031#else 9032 uint64_t en : 1; 9033 uint64_t rxfr : 1; 9034 uint64_t txfr : 1; 9035 uint64_t reserved_3_3 : 1; 9036 uint64_t txtrig : 2; 9037 uint64_t rxtrig : 2; 9038 uint64_t reserved_8_63 : 56; 9039#endif 9040 } s; 9041 struct cvmx_mio_uart2_fcr_s cn52xx; 9042 struct cvmx_mio_uart2_fcr_s cn52xxp1; 9043}; 9044typedef union cvmx_mio_uart2_fcr cvmx_mio_uart2_fcr_t; 9045 9046/** 9047 * cvmx_mio_uart2_htx 9048 */ 9049union cvmx_mio_uart2_htx { 9050 uint64_t u64; 9051 struct cvmx_mio_uart2_htx_s { 9052#ifdef __BIG_ENDIAN_BITFIELD 9053 uint64_t reserved_1_63 : 63; 9054 uint64_t htx : 1; /**< Halt TX */ 9055#else 9056 uint64_t htx : 1; 9057 uint64_t reserved_1_63 : 63; 9058#endif 9059 } s; 9060 struct cvmx_mio_uart2_htx_s cn52xx; 9061 struct cvmx_mio_uart2_htx_s cn52xxp1; 9062}; 9063typedef union cvmx_mio_uart2_htx cvmx_mio_uart2_htx_t; 9064 9065/** 9066 * cvmx_mio_uart2_ier 9067 */ 9068union cvmx_mio_uart2_ier { 9069 uint64_t u64; 9070 struct cvmx_mio_uart2_ier_s { 9071#ifdef __BIG_ENDIAN_BITFIELD 9072 uint64_t reserved_8_63 : 56; 9073 uint64_t ptime : 1; /**< Programmable THRE Interrupt mode enable */ 9074 uint64_t reserved_4_6 : 3; 9075 uint64_t edssi : 1; /**< Enable Modem Status Interrupt */ 9076 uint64_t elsi : 1; /**< Enable Receiver Line Status Interrupt */ 9077 uint64_t etbei : 1; /**< Enable Transmitter Holding Register Empty Interrupt */ 9078 uint64_t erbfi : 1; /**< Enable Received Data Available Interrupt */ 9079#else 9080 uint64_t erbfi : 1; 9081 uint64_t etbei : 1; 9082 uint64_t elsi : 1; 9083 uint64_t edssi : 1; 9084 uint64_t reserved_4_6 : 3; 9085 uint64_t ptime : 1; 9086 uint64_t reserved_8_63 : 56; 9087#endif 9088 } s; 9089 struct cvmx_mio_uart2_ier_s cn52xx; 9090 struct cvmx_mio_uart2_ier_s cn52xxp1; 9091}; 9092typedef union cvmx_mio_uart2_ier cvmx_mio_uart2_ier_t; 9093 9094/** 9095 * cvmx_mio_uart2_iir 9096 */ 9097union cvmx_mio_uart2_iir { 9098 uint64_t u64; 9099 struct cvmx_mio_uart2_iir_s { 9100#ifdef __BIG_ENDIAN_BITFIELD 9101 uint64_t reserved_8_63 : 56; 9102 uint64_t fen : 2; /**< FIFO-enabled bits */ 9103 uint64_t reserved_4_5 : 2; 9104 uint64_t iid : 4; /**< Interrupt ID */ 9105#else 9106 uint64_t iid : 4; 9107 uint64_t reserved_4_5 : 2; 9108 uint64_t fen : 2; 9109 uint64_t reserved_8_63 : 56; 9110#endif 9111 } s; 9112 struct cvmx_mio_uart2_iir_s cn52xx; 9113 struct cvmx_mio_uart2_iir_s cn52xxp1; 9114}; 9115typedef union cvmx_mio_uart2_iir cvmx_mio_uart2_iir_t; 9116 9117/** 9118 * cvmx_mio_uart2_lcr 9119 */ 9120union cvmx_mio_uart2_lcr { 9121 uint64_t u64; 9122 struct cvmx_mio_uart2_lcr_s { 9123#ifdef __BIG_ENDIAN_BITFIELD 9124 uint64_t reserved_8_63 : 56; 9125 uint64_t dlab : 1; /**< Divisor Latch Address bit */ 9126 uint64_t brk : 1; /**< Break Control bit */ 9127 uint64_t reserved_5_5 : 1; 9128 uint64_t eps : 1; /**< Even Parity Select bit */ 9129 uint64_t pen : 1; /**< Parity Enable bit */ 9130 uint64_t stop : 1; /**< Stop Control bit */ 9131 uint64_t cls : 2; /**< Character Length Select */ 9132#else 9133 uint64_t cls : 2; 9134 uint64_t stop : 1; 9135 uint64_t pen : 1; 9136 uint64_t eps : 1; 9137 uint64_t reserved_5_5 : 1; 9138 uint64_t brk : 1; 9139 uint64_t dlab : 1; 9140 uint64_t reserved_8_63 : 56; 9141#endif 9142 } s; 9143 struct cvmx_mio_uart2_lcr_s cn52xx; 9144 struct cvmx_mio_uart2_lcr_s cn52xxp1; 9145}; 9146typedef union cvmx_mio_uart2_lcr cvmx_mio_uart2_lcr_t; 9147 9148/** 9149 * cvmx_mio_uart2_lsr 9150 */ 9151union cvmx_mio_uart2_lsr { 9152 uint64_t u64; 9153 struct cvmx_mio_uart2_lsr_s { 9154#ifdef __BIG_ENDIAN_BITFIELD 9155 uint64_t reserved_8_63 : 56; 9156 uint64_t ferr : 1; /**< Error in Receiver FIFO bit */ 9157 uint64_t temt : 1; /**< Transmitter Empty bit */ 9158 uint64_t thre : 1; /**< Transmitter Holding Register Empty bit */ 9159 uint64_t bi : 1; /**< Break Interrupt bit */ 9160 uint64_t fe : 1; /**< Framing Error bit */ 9161 uint64_t pe : 1; /**< Parity Error bit */ 9162 uint64_t oe : 1; /**< Overrun Error bit */ 9163 uint64_t dr : 1; /**< Data Ready bit */ 9164#else 9165 uint64_t dr : 1; 9166 uint64_t oe : 1; 9167 uint64_t pe : 1; 9168 uint64_t fe : 1; 9169 uint64_t bi : 1; 9170 uint64_t thre : 1; 9171 uint64_t temt : 1; 9172 uint64_t ferr : 1; 9173 uint64_t reserved_8_63 : 56; 9174#endif 9175 } s; 9176 struct cvmx_mio_uart2_lsr_s cn52xx; 9177 struct cvmx_mio_uart2_lsr_s cn52xxp1; 9178}; 9179typedef union cvmx_mio_uart2_lsr cvmx_mio_uart2_lsr_t; 9180 9181/** 9182 * cvmx_mio_uart2_mcr 9183 */ 9184union cvmx_mio_uart2_mcr { 9185 uint64_t u64; 9186 struct cvmx_mio_uart2_mcr_s { 9187#ifdef __BIG_ENDIAN_BITFIELD 9188 uint64_t reserved_6_63 : 58; 9189 uint64_t afce : 1; /**< Auto Flow Control Enable bit */ 9190 uint64_t loop : 1; /**< Loopback bit */ 9191 uint64_t out2 : 1; /**< OUT2 output bit */ 9192 uint64_t out1 : 1; /**< OUT1 output bit */ 9193 uint64_t rts : 1; /**< Request To Send output bit */ 9194 uint64_t dtr : 1; /**< Data Terminal Ready output bit */ 9195#else 9196 uint64_t dtr : 1; 9197 uint64_t rts : 1; 9198 uint64_t out1 : 1; 9199 uint64_t out2 : 1; 9200 uint64_t loop : 1; 9201 uint64_t afce : 1; 9202 uint64_t reserved_6_63 : 58; 9203#endif 9204 } s; 9205 struct cvmx_mio_uart2_mcr_s cn52xx; 9206 struct cvmx_mio_uart2_mcr_s cn52xxp1; 9207}; 9208typedef union cvmx_mio_uart2_mcr cvmx_mio_uart2_mcr_t; 9209 9210/** 9211 * cvmx_mio_uart2_msr 9212 */ 9213union cvmx_mio_uart2_msr { 9214 uint64_t u64; 9215 struct cvmx_mio_uart2_msr_s { 9216#ifdef __BIG_ENDIAN_BITFIELD 9217 uint64_t reserved_8_63 : 56; 9218 uint64_t dcd : 1; /**< Data Carrier Detect input bit */ 9219 uint64_t ri : 1; /**< Ring Indicator input bit */ 9220 uint64_t dsr : 1; /**< Data Set Ready input bit */ 9221 uint64_t cts : 1; /**< Clear To Send input bit */ 9222 uint64_t ddcd : 1; /**< Delta Data Carrier Detect bit */ 9223 uint64_t teri : 1; /**< Trailing Edge of Ring Indicator bit */ 9224 uint64_t ddsr : 1; /**< Delta Data Set Ready bit */ 9225 uint64_t dcts : 1; /**< Delta Clear To Send bit */ 9226#else 9227 uint64_t dcts : 1; 9228 uint64_t ddsr : 1; 9229 uint64_t teri : 1; 9230 uint64_t ddcd : 1; 9231 uint64_t cts : 1; 9232 uint64_t dsr : 1; 9233 uint64_t ri : 1; 9234 uint64_t dcd : 1; 9235 uint64_t reserved_8_63 : 56; 9236#endif 9237 } s; 9238 struct cvmx_mio_uart2_msr_s cn52xx; 9239 struct cvmx_mio_uart2_msr_s cn52xxp1; 9240}; 9241typedef union cvmx_mio_uart2_msr cvmx_mio_uart2_msr_t; 9242 9243/** 9244 * cvmx_mio_uart2_rbr 9245 */ 9246union cvmx_mio_uart2_rbr { 9247 uint64_t u64; 9248 struct cvmx_mio_uart2_rbr_s { 9249#ifdef __BIG_ENDIAN_BITFIELD 9250 uint64_t reserved_8_63 : 56; 9251 uint64_t rbr : 8; /**< Receive Buffer Register */ 9252#else 9253 uint64_t rbr : 8; 9254 uint64_t reserved_8_63 : 56; 9255#endif 9256 } s; 9257 struct cvmx_mio_uart2_rbr_s cn52xx; 9258 struct cvmx_mio_uart2_rbr_s cn52xxp1; 9259}; 9260typedef union cvmx_mio_uart2_rbr cvmx_mio_uart2_rbr_t; 9261 9262/** 9263 * cvmx_mio_uart2_rfl 9264 */ 9265union cvmx_mio_uart2_rfl { 9266 uint64_t u64; 9267 struct cvmx_mio_uart2_rfl_s { 9268#ifdef __BIG_ENDIAN_BITFIELD 9269 uint64_t reserved_7_63 : 57; 9270 uint64_t rfl : 7; /**< Receive FIFO Level Register */ 9271#else 9272 uint64_t rfl : 7; 9273 uint64_t reserved_7_63 : 57; 9274#endif 9275 } s; 9276 struct cvmx_mio_uart2_rfl_s cn52xx; 9277 struct cvmx_mio_uart2_rfl_s cn52xxp1; 9278}; 9279typedef union cvmx_mio_uart2_rfl cvmx_mio_uart2_rfl_t; 9280 9281/** 9282 * cvmx_mio_uart2_rfw 9283 */ 9284union cvmx_mio_uart2_rfw { 9285 uint64_t u64; 9286 struct cvmx_mio_uart2_rfw_s { 9287#ifdef __BIG_ENDIAN_BITFIELD 9288 uint64_t reserved_10_63 : 54; 9289 uint64_t rffe : 1; /**< Receive FIFO Framing Error */ 9290 uint64_t rfpe : 1; /**< Receive FIFO Parity Error */ 9291 uint64_t rfwd : 8; /**< Receive FIFO Write Data */ 9292#else 9293 uint64_t rfwd : 8; 9294 uint64_t rfpe : 1; 9295 uint64_t rffe : 1; 9296 uint64_t reserved_10_63 : 54; 9297#endif 9298 } s; 9299 struct cvmx_mio_uart2_rfw_s cn52xx; 9300 struct cvmx_mio_uart2_rfw_s cn52xxp1; 9301}; 9302typedef union cvmx_mio_uart2_rfw cvmx_mio_uart2_rfw_t; 9303 9304/** 9305 * cvmx_mio_uart2_sbcr 9306 */ 9307union cvmx_mio_uart2_sbcr { 9308 uint64_t u64; 9309 struct cvmx_mio_uart2_sbcr_s { 9310#ifdef __BIG_ENDIAN_BITFIELD 9311 uint64_t reserved_1_63 : 63; 9312 uint64_t sbcr : 1; /**< Shadow Break Control */ 9313#else 9314 uint64_t sbcr : 1; 9315 uint64_t reserved_1_63 : 63; 9316#endif 9317 } s; 9318 struct cvmx_mio_uart2_sbcr_s cn52xx; 9319 struct cvmx_mio_uart2_sbcr_s cn52xxp1; 9320}; 9321typedef union cvmx_mio_uart2_sbcr cvmx_mio_uart2_sbcr_t; 9322 9323/** 9324 * cvmx_mio_uart2_scr 9325 */ 9326union cvmx_mio_uart2_scr { 9327 uint64_t u64; 9328 struct cvmx_mio_uart2_scr_s { 9329#ifdef __BIG_ENDIAN_BITFIELD 9330 uint64_t reserved_8_63 : 56; 9331 uint64_t scr : 8; /**< Scratchpad Register */ 9332#else 9333 uint64_t scr : 8; 9334 uint64_t reserved_8_63 : 56; 9335#endif 9336 } s; 9337 struct cvmx_mio_uart2_scr_s cn52xx; 9338 struct cvmx_mio_uart2_scr_s cn52xxp1; 9339}; 9340typedef union cvmx_mio_uart2_scr cvmx_mio_uart2_scr_t; 9341 9342/** 9343 * cvmx_mio_uart2_sfe 9344 */ 9345union cvmx_mio_uart2_sfe { 9346 uint64_t u64; 9347 struct cvmx_mio_uart2_sfe_s { 9348#ifdef __BIG_ENDIAN_BITFIELD 9349 uint64_t reserved_1_63 : 63; 9350 uint64_t sfe : 1; /**< Shadow FIFO Enable */ 9351#else 9352 uint64_t sfe : 1; 9353 uint64_t reserved_1_63 : 63; 9354#endif 9355 } s; 9356 struct cvmx_mio_uart2_sfe_s cn52xx; 9357 struct cvmx_mio_uart2_sfe_s cn52xxp1; 9358}; 9359typedef union cvmx_mio_uart2_sfe cvmx_mio_uart2_sfe_t; 9360 9361/** 9362 * cvmx_mio_uart2_srr 9363 */ 9364union cvmx_mio_uart2_srr { 9365 uint64_t u64; 9366 struct cvmx_mio_uart2_srr_s { 9367#ifdef __BIG_ENDIAN_BITFIELD 9368 uint64_t reserved_3_63 : 61; 9369 uint64_t stfr : 1; /**< Shadow TX FIFO Reset */ 9370 uint64_t srfr : 1; /**< Shadow RX FIFO Reset */ 9371 uint64_t usr : 1; /**< UART Soft Reset */ 9372#else 9373 uint64_t usr : 1; 9374 uint64_t srfr : 1; 9375 uint64_t stfr : 1; 9376 uint64_t reserved_3_63 : 61; 9377#endif 9378 } s; 9379 struct cvmx_mio_uart2_srr_s cn52xx; 9380 struct cvmx_mio_uart2_srr_s cn52xxp1; 9381}; 9382typedef union cvmx_mio_uart2_srr cvmx_mio_uart2_srr_t; 9383 9384/** 9385 * cvmx_mio_uart2_srt 9386 */ 9387union cvmx_mio_uart2_srt { 9388 uint64_t u64; 9389 struct cvmx_mio_uart2_srt_s { 9390#ifdef __BIG_ENDIAN_BITFIELD 9391 uint64_t reserved_2_63 : 62; 9392 uint64_t srt : 2; /**< Shadow RX Trigger */ 9393#else 9394 uint64_t srt : 2; 9395 uint64_t reserved_2_63 : 62; 9396#endif 9397 } s; 9398 struct cvmx_mio_uart2_srt_s cn52xx; 9399 struct cvmx_mio_uart2_srt_s cn52xxp1; 9400}; 9401typedef union cvmx_mio_uart2_srt cvmx_mio_uart2_srt_t; 9402 9403/** 9404 * cvmx_mio_uart2_srts 9405 */ 9406union cvmx_mio_uart2_srts { 9407 uint64_t u64; 9408 struct cvmx_mio_uart2_srts_s { 9409#ifdef __BIG_ENDIAN_BITFIELD 9410 uint64_t reserved_1_63 : 63; 9411 uint64_t srts : 1; /**< Shadow Request To Send */ 9412#else 9413 uint64_t srts : 1; 9414 uint64_t reserved_1_63 : 63; 9415#endif 9416 } s; 9417 struct cvmx_mio_uart2_srts_s cn52xx; 9418 struct cvmx_mio_uart2_srts_s cn52xxp1; 9419}; 9420typedef union cvmx_mio_uart2_srts cvmx_mio_uart2_srts_t; 9421 9422/** 9423 * cvmx_mio_uart2_stt 9424 */ 9425union cvmx_mio_uart2_stt { 9426 uint64_t u64; 9427 struct cvmx_mio_uart2_stt_s { 9428#ifdef __BIG_ENDIAN_BITFIELD 9429 uint64_t reserved_2_63 : 62; 9430 uint64_t stt : 2; /**< Shadow TX Trigger */ 9431#else 9432 uint64_t stt : 2; 9433 uint64_t reserved_2_63 : 62; 9434#endif 9435 } s; 9436 struct cvmx_mio_uart2_stt_s cn52xx; 9437 struct cvmx_mio_uart2_stt_s cn52xxp1; 9438}; 9439typedef union cvmx_mio_uart2_stt cvmx_mio_uart2_stt_t; 9440 9441/** 9442 * cvmx_mio_uart2_tfl 9443 */ 9444union cvmx_mio_uart2_tfl { 9445 uint64_t u64; 9446 struct cvmx_mio_uart2_tfl_s { 9447#ifdef __BIG_ENDIAN_BITFIELD 9448 uint64_t reserved_7_63 : 57; 9449 uint64_t tfl : 7; /**< Transmit FIFO Level Register */ 9450#else 9451 uint64_t tfl : 7; 9452 uint64_t reserved_7_63 : 57; 9453#endif 9454 } s; 9455 struct cvmx_mio_uart2_tfl_s cn52xx; 9456 struct cvmx_mio_uart2_tfl_s cn52xxp1; 9457}; 9458typedef union cvmx_mio_uart2_tfl cvmx_mio_uart2_tfl_t; 9459 9460/** 9461 * cvmx_mio_uart2_tfr 9462 */ 9463union cvmx_mio_uart2_tfr { 9464 uint64_t u64; 9465 struct cvmx_mio_uart2_tfr_s { 9466#ifdef __BIG_ENDIAN_BITFIELD 9467 uint64_t reserved_8_63 : 56; 9468 uint64_t tfr : 8; /**< Transmit FIFO Read Register */ 9469#else 9470 uint64_t tfr : 8; 9471 uint64_t reserved_8_63 : 56; 9472#endif 9473 } s; 9474 struct cvmx_mio_uart2_tfr_s cn52xx; 9475 struct cvmx_mio_uart2_tfr_s cn52xxp1; 9476}; 9477typedef union cvmx_mio_uart2_tfr cvmx_mio_uart2_tfr_t; 9478 9479/** 9480 * cvmx_mio_uart2_thr 9481 */ 9482union cvmx_mio_uart2_thr { 9483 uint64_t u64; 9484 struct cvmx_mio_uart2_thr_s { 9485#ifdef __BIG_ENDIAN_BITFIELD 9486 uint64_t reserved_8_63 : 56; 9487 uint64_t thr : 8; /**< Transmit Holding Register */ 9488#else 9489 uint64_t thr : 8; 9490 uint64_t reserved_8_63 : 56; 9491#endif 9492 } s; 9493 struct cvmx_mio_uart2_thr_s cn52xx; 9494 struct cvmx_mio_uart2_thr_s cn52xxp1; 9495}; 9496typedef union cvmx_mio_uart2_thr cvmx_mio_uart2_thr_t; 9497 9498/** 9499 * cvmx_mio_uart2_usr 9500 */ 9501union cvmx_mio_uart2_usr { 9502 uint64_t u64; 9503 struct cvmx_mio_uart2_usr_s { 9504#ifdef __BIG_ENDIAN_BITFIELD 9505 uint64_t reserved_5_63 : 59; 9506 uint64_t rff : 1; /**< RX FIFO Full */ 9507 uint64_t rfne : 1; /**< RX FIFO Not Empty */ 9508 uint64_t tfe : 1; /**< TX FIFO Empty */ 9509 uint64_t tfnf : 1; /**< TX FIFO Not Full */ 9510 uint64_t busy : 1; /**< Busy bit (always 0 in PASS3) */ 9511#else 9512 uint64_t busy : 1; 9513 uint64_t tfnf : 1; 9514 uint64_t tfe : 1; 9515 uint64_t rfne : 1; 9516 uint64_t rff : 1; 9517 uint64_t reserved_5_63 : 59; 9518#endif 9519 } s; 9520 struct cvmx_mio_uart2_usr_s cn52xx; 9521 struct cvmx_mio_uart2_usr_s cn52xxp1; 9522}; 9523typedef union cvmx_mio_uart2_usr cvmx_mio_uart2_usr_t; 9524 9525#endif 9526