cvmx-key-defs.h revision 215976
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-key-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon key. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_KEY_TYPEDEFS_H__ 53#define __CVMX_KEY_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_KEY_BIST_REG CVMX_KEY_BIST_REG_FUNC() 57static inline uint64_t CVMX_KEY_BIST_REG_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 60 cvmx_warn("CVMX_KEY_BIST_REG not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x0001180020000018ull); 62} 63#else 64#define CVMX_KEY_BIST_REG (CVMX_ADD_IO_SEG(0x0001180020000018ull)) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67#define CVMX_KEY_CTL_STATUS CVMX_KEY_CTL_STATUS_FUNC() 68static inline uint64_t CVMX_KEY_CTL_STATUS_FUNC(void) 69{ 70 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 71 cvmx_warn("CVMX_KEY_CTL_STATUS not supported on this chip\n"); 72 return CVMX_ADD_IO_SEG(0x0001180020000010ull); 73} 74#else 75#define CVMX_KEY_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180020000010ull)) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78#define CVMX_KEY_INT_ENB CVMX_KEY_INT_ENB_FUNC() 79static inline uint64_t CVMX_KEY_INT_ENB_FUNC(void) 80{ 81 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 82 cvmx_warn("CVMX_KEY_INT_ENB not supported on this chip\n"); 83 return CVMX_ADD_IO_SEG(0x0001180020000008ull); 84} 85#else 86#define CVMX_KEY_INT_ENB (CVMX_ADD_IO_SEG(0x0001180020000008ull)) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89#define CVMX_KEY_INT_SUM CVMX_KEY_INT_SUM_FUNC() 90static inline uint64_t CVMX_KEY_INT_SUM_FUNC(void) 91{ 92 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 93 cvmx_warn("CVMX_KEY_INT_SUM not supported on this chip\n"); 94 return CVMX_ADD_IO_SEG(0x0001180020000000ull); 95} 96#else 97#define CVMX_KEY_INT_SUM (CVMX_ADD_IO_SEG(0x0001180020000000ull)) 98#endif 99 100/** 101 * cvmx_key_bist_reg 102 * 103 * KEY_BIST_REG = KEY's BIST Status Register 104 * 105 * The KEY's BIST status for memories. 106 */ 107union cvmx_key_bist_reg 108{ 109 uint64_t u64; 110 struct cvmx_key_bist_reg_s 111 { 112#if __BYTE_ORDER == __BIG_ENDIAN 113 uint64_t reserved_3_63 : 61; 114 uint64_t rrc : 1; /**< RRC bist status. */ 115 uint64_t mem1 : 1; /**< MEM - 1 bist status. */ 116 uint64_t mem0 : 1; /**< MEM - 0 bist status. */ 117#else 118 uint64_t mem0 : 1; 119 uint64_t mem1 : 1; 120 uint64_t rrc : 1; 121 uint64_t reserved_3_63 : 61; 122#endif 123 } s; 124 struct cvmx_key_bist_reg_s cn38xx; 125 struct cvmx_key_bist_reg_s cn38xxp2; 126 struct cvmx_key_bist_reg_s cn56xx; 127 struct cvmx_key_bist_reg_s cn56xxp1; 128 struct cvmx_key_bist_reg_s cn58xx; 129 struct cvmx_key_bist_reg_s cn58xxp1; 130 struct cvmx_key_bist_reg_s cn63xx; 131 struct cvmx_key_bist_reg_s cn63xxp1; 132}; 133typedef union cvmx_key_bist_reg cvmx_key_bist_reg_t; 134 135/** 136 * cvmx_key_ctl_status 137 * 138 * KEY_CTL_STATUS = KEY's Control/Status Register 139 * 140 * The KEY's interrupt enable register. 141 */ 142union cvmx_key_ctl_status 143{ 144 uint64_t u64; 145 struct cvmx_key_ctl_status_s 146 { 147#if __BYTE_ORDER == __BIG_ENDIAN 148 uint64_t reserved_14_63 : 50; 149 uint64_t mem1_err : 7; /**< Causes a flip of the ECC bit associated 38:32 150 respective to bit 13:7 of this field, for FPF 151 FIFO 1. */ 152 uint64_t mem0_err : 7; /**< Causes a flip of the ECC bit associated 38:32 153 respective to bit 6:0 of this field, for FPF 154 FIFO 0. */ 155#else 156 uint64_t mem0_err : 7; 157 uint64_t mem1_err : 7; 158 uint64_t reserved_14_63 : 50; 159#endif 160 } s; 161 struct cvmx_key_ctl_status_s cn38xx; 162 struct cvmx_key_ctl_status_s cn38xxp2; 163 struct cvmx_key_ctl_status_s cn56xx; 164 struct cvmx_key_ctl_status_s cn56xxp1; 165 struct cvmx_key_ctl_status_s cn58xx; 166 struct cvmx_key_ctl_status_s cn58xxp1; 167 struct cvmx_key_ctl_status_s cn63xx; 168 struct cvmx_key_ctl_status_s cn63xxp1; 169}; 170typedef union cvmx_key_ctl_status cvmx_key_ctl_status_t; 171 172/** 173 * cvmx_key_int_enb 174 * 175 * KEY_INT_ENB = KEY's Interrupt Enable 176 * 177 * The KEY's interrupt enable register. 178 */ 179union cvmx_key_int_enb 180{ 181 uint64_t u64; 182 struct cvmx_key_int_enb_s 183 { 184#if __BYTE_ORDER == __BIG_ENDIAN 185 uint64_t reserved_4_63 : 60; 186 uint64_t ked1_dbe : 1; /**< When set (1) and bit 3 of the KEY_INT_SUM 187 register is asserted the KEY will assert an 188 interrupt. */ 189 uint64_t ked1_sbe : 1; /**< When set (1) and bit 2 of the KEY_INT_SUM 190 register is asserted the KEY will assert an 191 interrupt. */ 192 uint64_t ked0_dbe : 1; /**< When set (1) and bit 1 of the KEY_INT_SUM 193 register is asserted the KEY will assert an 194 interrupt. */ 195 uint64_t ked0_sbe : 1; /**< When set (1) and bit 0 of the KEY_INT_SUM 196 register is asserted the KEY will assert an 197 interrupt. */ 198#else 199 uint64_t ked0_sbe : 1; 200 uint64_t ked0_dbe : 1; 201 uint64_t ked1_sbe : 1; 202 uint64_t ked1_dbe : 1; 203 uint64_t reserved_4_63 : 60; 204#endif 205 } s; 206 struct cvmx_key_int_enb_s cn38xx; 207 struct cvmx_key_int_enb_s cn38xxp2; 208 struct cvmx_key_int_enb_s cn56xx; 209 struct cvmx_key_int_enb_s cn56xxp1; 210 struct cvmx_key_int_enb_s cn58xx; 211 struct cvmx_key_int_enb_s cn58xxp1; 212 struct cvmx_key_int_enb_s cn63xx; 213 struct cvmx_key_int_enb_s cn63xxp1; 214}; 215typedef union cvmx_key_int_enb cvmx_key_int_enb_t; 216 217/** 218 * cvmx_key_int_sum 219 * 220 * KEY_INT_SUM = KEY's Interrupt Summary Register 221 * 222 * Contains the diffrent interrupt summary bits of the KEY. 223 */ 224union cvmx_key_int_sum 225{ 226 uint64_t u64; 227 struct cvmx_key_int_sum_s 228 { 229#if __BYTE_ORDER == __BIG_ENDIAN 230 uint64_t reserved_4_63 : 60; 231 uint64_t ked1_dbe : 1; 232 uint64_t ked1_sbe : 1; 233 uint64_t ked0_dbe : 1; 234 uint64_t ked0_sbe : 1; 235#else 236 uint64_t ked0_sbe : 1; 237 uint64_t ked0_dbe : 1; 238 uint64_t ked1_sbe : 1; 239 uint64_t ked1_dbe : 1; 240 uint64_t reserved_4_63 : 60; 241#endif 242 } s; 243 struct cvmx_key_int_sum_s cn38xx; 244 struct cvmx_key_int_sum_s cn38xxp2; 245 struct cvmx_key_int_sum_s cn56xx; 246 struct cvmx_key_int_sum_s cn56xxp1; 247 struct cvmx_key_int_sum_s cn58xx; 248 struct cvmx_key_int_sum_s cn58xxp1; 249 struct cvmx_key_int_sum_s cn63xx; 250 struct cvmx_key_int_sum_s cn63xxp1; 251}; 252typedef union cvmx_key_int_sum cvmx_key_int_sum_t; 253 254#endif 255