1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-ipd-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon ipd. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_IPD_DEFS_H__ 53232812Sjmallett#define __CVMX_IPD_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull)) 56215976Sjmallett#define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull)) 57215976Sjmallett#define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull)) 58215976Sjmallett#define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull)) 59232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 60232812Sjmallettstatic inline uint64_t CVMX_IPD_BPIDX_MBUF_TH(unsigned long offset) 61232812Sjmallett{ 62232812Sjmallett if (!( 63232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 64232812Sjmallett cvmx_warn("CVMX_IPD_BPIDX_MBUF_TH(%lu) is invalid on this chip\n", offset); 65232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8; 66232812Sjmallett} 67232812Sjmallett#else 68232812Sjmallett#define CVMX_IPD_BPIDX_MBUF_TH(offset) (CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8) 69232812Sjmallett#endif 70232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71232812Sjmallettstatic inline uint64_t CVMX_IPD_BPID_BP_COUNTERX(unsigned long offset) 72232812Sjmallett{ 73232812Sjmallett if (!( 74232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 75232812Sjmallett cvmx_warn("CVMX_IPD_BPID_BP_COUNTERX(%lu) is invalid on this chip\n", offset); 76232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8; 77232812Sjmallett} 78232812Sjmallett#else 79232812Sjmallett#define CVMX_IPD_BPID_BP_COUNTERX(offset) (CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8) 80232812Sjmallett#endif 81232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82232812Sjmallett#define CVMX_IPD_BP_PRT_RED_END CVMX_IPD_BP_PRT_RED_END_FUNC() 83232812Sjmallettstatic inline uint64_t CVMX_IPD_BP_PRT_RED_END_FUNC(void) 84232812Sjmallett{ 85232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 86232812Sjmallett cvmx_warn("CVMX_IPD_BP_PRT_RED_END not supported on this chip\n"); 87232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000328ull); 88232812Sjmallett} 89232812Sjmallett#else 90215976Sjmallett#define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull)) 91232812Sjmallett#endif 92215976Sjmallett#define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull)) 93232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 94232812Sjmallett#define CVMX_IPD_CREDITS CVMX_IPD_CREDITS_FUNC() 95232812Sjmallettstatic inline uint64_t CVMX_IPD_CREDITS_FUNC(void) 96232812Sjmallett{ 97232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 98232812Sjmallett cvmx_warn("CVMX_IPD_CREDITS not supported on this chip\n"); 99232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000004410ull); 100232812Sjmallett} 101232812Sjmallett#else 102232812Sjmallett#define CVMX_IPD_CREDITS (CVMX_ADD_IO_SEG(0x00014F0000004410ull)) 103232812Sjmallett#endif 104215976Sjmallett#define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull)) 105232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 106232812Sjmallett#define CVMX_IPD_ECC_CTL CVMX_IPD_ECC_CTL_FUNC() 107232812Sjmallettstatic inline uint64_t CVMX_IPD_ECC_CTL_FUNC(void) 108232812Sjmallett{ 109232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 110232812Sjmallett cvmx_warn("CVMX_IPD_ECC_CTL not supported on this chip\n"); 111232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000004408ull); 112232812Sjmallett} 113232812Sjmallett#else 114232812Sjmallett#define CVMX_IPD_ECC_CTL (CVMX_ADD_IO_SEG(0x00014F0000004408ull)) 115232812Sjmallett#endif 116232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 117232812Sjmallett#define CVMX_IPD_FREE_PTR_FIFO_CTL CVMX_IPD_FREE_PTR_FIFO_CTL_FUNC() 118232812Sjmallettstatic inline uint64_t CVMX_IPD_FREE_PTR_FIFO_CTL_FUNC(void) 119232812Sjmallett{ 120232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 121232812Sjmallett cvmx_warn("CVMX_IPD_FREE_PTR_FIFO_CTL not supported on this chip\n"); 122232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000780ull); 123232812Sjmallett} 124232812Sjmallett#else 125232812Sjmallett#define CVMX_IPD_FREE_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000780ull)) 126232812Sjmallett#endif 127232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 128232812Sjmallett#define CVMX_IPD_FREE_PTR_VALUE CVMX_IPD_FREE_PTR_VALUE_FUNC() 129232812Sjmallettstatic inline uint64_t CVMX_IPD_FREE_PTR_VALUE_FUNC(void) 130232812Sjmallett{ 131232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 132232812Sjmallett cvmx_warn("CVMX_IPD_FREE_PTR_VALUE not supported on this chip\n"); 133232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000788ull); 134232812Sjmallett} 135232812Sjmallett#else 136232812Sjmallett#define CVMX_IPD_FREE_PTR_VALUE (CVMX_ADD_IO_SEG(0x00014F0000000788ull)) 137232812Sjmallett#endif 138232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 139232812Sjmallett#define CVMX_IPD_HOLD_PTR_FIFO_CTL CVMX_IPD_HOLD_PTR_FIFO_CTL_FUNC() 140232812Sjmallettstatic inline uint64_t CVMX_IPD_HOLD_PTR_FIFO_CTL_FUNC(void) 141232812Sjmallett{ 142232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 143232812Sjmallett cvmx_warn("CVMX_IPD_HOLD_PTR_FIFO_CTL not supported on this chip\n"); 144232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000790ull); 145232812Sjmallett} 146232812Sjmallett#else 147232812Sjmallett#define CVMX_IPD_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000790ull)) 148232812Sjmallett#endif 149215976Sjmallett#define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull)) 150215976Sjmallett#define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull)) 151232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 152232812Sjmallett#define CVMX_IPD_NEXT_PKT_PTR CVMX_IPD_NEXT_PKT_PTR_FUNC() 153232812Sjmallettstatic inline uint64_t CVMX_IPD_NEXT_PKT_PTR_FUNC(void) 154232812Sjmallett{ 155232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 156232812Sjmallett cvmx_warn("CVMX_IPD_NEXT_PKT_PTR not supported on this chip\n"); 157232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F00000007A0ull); 158232812Sjmallett} 159232812Sjmallett#else 160232812Sjmallett#define CVMX_IPD_NEXT_PKT_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A0ull)) 161232812Sjmallett#endif 162232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 163232812Sjmallett#define CVMX_IPD_NEXT_WQE_PTR CVMX_IPD_NEXT_WQE_PTR_FUNC() 164232812Sjmallettstatic inline uint64_t CVMX_IPD_NEXT_WQE_PTR_FUNC(void) 165232812Sjmallett{ 166232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 167232812Sjmallett cvmx_warn("CVMX_IPD_NEXT_WQE_PTR not supported on this chip\n"); 168232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F00000007A8ull); 169232812Sjmallett} 170232812Sjmallett#else 171232812Sjmallett#define CVMX_IPD_NEXT_WQE_PTR (CVMX_ADD_IO_SEG(0x00014F00000007A8ull)) 172232812Sjmallett#endif 173215976Sjmallett#define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull)) 174232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 175232812Sjmallettstatic inline uint64_t CVMX_IPD_ON_BP_DROP_PKTX(unsigned long block_id) 176232812Sjmallett{ 177232812Sjmallett if (!( 178232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))))) 179232812Sjmallett cvmx_warn("CVMX_IPD_ON_BP_DROP_PKTX(%lu) is invalid on this chip\n", block_id); 180232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000004100ull); 181232812Sjmallett} 182232812Sjmallett#else 183232812Sjmallett#define CVMX_IPD_ON_BP_DROP_PKTX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004100ull)) 184232812Sjmallett#endif 185215976Sjmallett#define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull)) 186232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 187232812Sjmallett#define CVMX_IPD_PKT_ERR CVMX_IPD_PKT_ERR_FUNC() 188232812Sjmallettstatic inline uint64_t CVMX_IPD_PKT_ERR_FUNC(void) 189232812Sjmallett{ 190232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 191232812Sjmallett cvmx_warn("CVMX_IPD_PKT_ERR not supported on this chip\n"); 192232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F00000003F0ull); 193232812Sjmallett} 194232812Sjmallett#else 195232812Sjmallett#define CVMX_IPD_PKT_ERR (CVMX_ADD_IO_SEG(0x00014F00000003F0ull)) 196232812Sjmallett#endif 197232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 198232812Sjmallett#define CVMX_IPD_PKT_PTR_VALID CVMX_IPD_PKT_PTR_VALID_FUNC() 199232812Sjmallettstatic inline uint64_t CVMX_IPD_PKT_PTR_VALID_FUNC(void) 200232812Sjmallett{ 201232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 202232812Sjmallett cvmx_warn("CVMX_IPD_PKT_PTR_VALID not supported on this chip\n"); 203232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000358ull); 204232812Sjmallett} 205232812Sjmallett#else 206215976Sjmallett#define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull)) 207232812Sjmallett#endif 208215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 209215976Sjmallettstatic inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT(unsigned long offset) 210215976Sjmallett{ 211215976Sjmallett if (!( 212215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || (offset == 32))) || 213215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 214215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 215215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 216215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) || 217215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) || 218215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 219232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) || 220232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) || 221232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) || 222232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))))) 223215976Sjmallett cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT(%lu) is invalid on this chip\n", offset); 224215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8; 225215976Sjmallett} 226215976Sjmallett#else 227215976Sjmallett#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8) 228215976Sjmallett#endif 229215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 230215976Sjmallettstatic inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT2(unsigned long offset) 231215976Sjmallett{ 232215976Sjmallett if (!( 233215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39)))) || 234215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) || 235232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 36) && (offset <= 39)))) || 236232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 36) && (offset <= 39)))) || 237232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 36) && (offset <= 39)))) || 238232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 36) && (offset <= 39)))))) 239215976Sjmallett cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT2(%lu) is invalid on this chip\n", offset); 240215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36; 241215976Sjmallett} 242215976Sjmallett#else 243215976Sjmallett#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36) 244215976Sjmallett#endif 245215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 246215976Sjmallettstatic inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT3(unsigned long offset) 247215976Sjmallett{ 248215976Sjmallett if (!( 249232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 40) && (offset <= 47)))) || 250232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) || 251232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) || 252232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 40) && (offset <= 47)))))) 253215976Sjmallett cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT3(%lu) is invalid on this chip\n", offset); 254215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40; 255215976Sjmallett} 256215976Sjmallett#else 257215976Sjmallett#define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40) 258215976Sjmallett#endif 259215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 260215976Sjmallettstatic inline uint64_t CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(unsigned long offset) 261215976Sjmallett{ 262215976Sjmallett if (!( 263215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39)))) || 264215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) || 265232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 36) && (offset <= 39)))) || 266232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 36) && (offset <= 39)))) || 267232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 36) && (offset <= 39)))) || 268232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 36) && (offset <= 39)))))) 269215976Sjmallett cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(%lu) is invalid on this chip\n", offset); 270215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36; 271215976Sjmallett} 272215976Sjmallett#else 273215976Sjmallett#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36) 274215976Sjmallett#endif 275215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276215976Sjmallettstatic inline uint64_t CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(unsigned long offset) 277215976Sjmallett{ 278215976Sjmallett if (!( 279232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 40) && (offset <= 43)))) || 280232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) || 281232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 43)))) || 282232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 40) && (offset <= 43)))))) 283215976Sjmallett cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(%lu) is invalid on this chip\n", offset); 284215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40; 285215976Sjmallett} 286215976Sjmallett#else 287215976Sjmallett#define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40) 288215976Sjmallett#endif 289215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 290232812Sjmallettstatic inline uint64_t CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(unsigned long offset) 291232812Sjmallett{ 292232812Sjmallett if (!( 293232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 44) && (offset <= 47)))) || 294232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 44) && (offset <= 47)))) || 295232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 44) && (offset <= 47)))))) 296232812Sjmallett cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(%lu) is invalid on this chip\n", offset); 297232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44; 298232812Sjmallett} 299232812Sjmallett#else 300232812Sjmallett#define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44) 301232812Sjmallett#endif 302232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 303215976Sjmallettstatic inline uint64_t CVMX_IPD_PORT_BP_COUNTERS_PAIRX(unsigned long offset) 304215976Sjmallett{ 305215976Sjmallett if (!( 306215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || (offset == 32))) || 307215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 308215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 309215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 310215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) || 311215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) || 312215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 313232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) || 314232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) || 315232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) || 316232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))))) 317215976Sjmallett cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS_PAIRX(%lu) is invalid on this chip\n", offset); 318215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8; 319215976Sjmallett} 320215976Sjmallett#else 321215976Sjmallett#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8) 322215976Sjmallett#endif 323215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 324232812Sjmallett#define CVMX_IPD_PORT_PTR_FIFO_CTL CVMX_IPD_PORT_PTR_FIFO_CTL_FUNC() 325232812Sjmallettstatic inline uint64_t CVMX_IPD_PORT_PTR_FIFO_CTL_FUNC(void) 326232812Sjmallett{ 327232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 328232812Sjmallett cvmx_warn("CVMX_IPD_PORT_PTR_FIFO_CTL not supported on this chip\n"); 329232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000798ull); 330232812Sjmallett} 331232812Sjmallett#else 332232812Sjmallett#define CVMX_IPD_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000798ull)) 333232812Sjmallett#endif 334232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 335215976Sjmallettstatic inline uint64_t CVMX_IPD_PORT_QOS_INTX(unsigned long offset) 336215976Sjmallett{ 337215976Sjmallett if (!( 338215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4))) || 339215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) || 340232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))) || 341232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0) || (offset == 4) || (offset == 5))) || 342232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))) || 343232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 344232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))))) 345215976Sjmallett cvmx_warn("CVMX_IPD_PORT_QOS_INTX(%lu) is invalid on this chip\n", offset); 346215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8; 347215976Sjmallett} 348215976Sjmallett#else 349215976Sjmallett#define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8) 350215976Sjmallett#endif 351215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 352215976Sjmallettstatic inline uint64_t CVMX_IPD_PORT_QOS_INT_ENBX(unsigned long offset) 353215976Sjmallett{ 354215976Sjmallett if (!( 355215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4))) || 356215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) || 357232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))) || 358232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0) || (offset == 4) || (offset == 5))) || 359232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))) || 360232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 361232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))))) 362215976Sjmallett cvmx_warn("CVMX_IPD_PORT_QOS_INT_ENBX(%lu) is invalid on this chip\n", offset); 363215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8; 364215976Sjmallett} 365215976Sjmallett#else 366215976Sjmallett#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8) 367215976Sjmallett#endif 368215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 369215976Sjmallettstatic inline uint64_t CVMX_IPD_PORT_QOS_X_CNT(unsigned long offset) 370215976Sjmallett{ 371215976Sjmallett if (!( 372215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31) || ((offset >= 256) && (offset <= 319)))) || 373215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 319)))) || 374232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 383)))) || 375232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31) || ((offset >= 256) && (offset <= 351)))) || 376232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 335)) || ((offset >= 352) && (offset <= 383)))) || 377232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 511))) || 378232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 383)))))) 379215976Sjmallett cvmx_warn("CVMX_IPD_PORT_QOS_X_CNT(%lu) is invalid on this chip\n", offset); 380215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8; 381215976Sjmallett} 382215976Sjmallett#else 383215976Sjmallett#define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8) 384215976Sjmallett#endif 385232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386232812Sjmallettstatic inline uint64_t CVMX_IPD_PORT_SOPX(unsigned long block_id) 387232812Sjmallett{ 388232812Sjmallett if (!( 389232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))))) 390232812Sjmallett cvmx_warn("CVMX_IPD_PORT_SOPX(%lu) is invalid on this chip\n", block_id); 391232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000004400ull); 392232812Sjmallett} 393232812Sjmallett#else 394232812Sjmallett#define CVMX_IPD_PORT_SOPX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004400ull)) 395232812Sjmallett#endif 396232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 397232812Sjmallett#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL_FUNC() 398232812Sjmallettstatic inline uint64_t CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL_FUNC(void) 399232812Sjmallett{ 400232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 401232812Sjmallett cvmx_warn("CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL not supported on this chip\n"); 402232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000348ull); 403232812Sjmallett} 404232812Sjmallett#else 405215976Sjmallett#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull)) 406232812Sjmallett#endif 407232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 408232812Sjmallett#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL CVMX_IPD_PRC_PORT_PTR_FIFO_CTL_FUNC() 409232812Sjmallettstatic inline uint64_t CVMX_IPD_PRC_PORT_PTR_FIFO_CTL_FUNC(void) 410232812Sjmallett{ 411232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 412232812Sjmallett cvmx_warn("CVMX_IPD_PRC_PORT_PTR_FIFO_CTL not supported on this chip\n"); 413232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000350ull); 414232812Sjmallett} 415232812Sjmallett#else 416215976Sjmallett#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull)) 417232812Sjmallett#endif 418215976Sjmallett#define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull)) 419232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 420232812Sjmallett#define CVMX_IPD_PWP_PTR_FIFO_CTL CVMX_IPD_PWP_PTR_FIFO_CTL_FUNC() 421232812Sjmallettstatic inline uint64_t CVMX_IPD_PWP_PTR_FIFO_CTL_FUNC(void) 422232812Sjmallett{ 423232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 424232812Sjmallett cvmx_warn("CVMX_IPD_PWP_PTR_FIFO_CTL not supported on this chip\n"); 425232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000340ull); 426232812Sjmallett} 427232812Sjmallett#else 428215976Sjmallett#define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull)) 429232812Sjmallett#endif 430215976Sjmallett#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0) 431215976Sjmallett#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1) 432215976Sjmallett#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2) 433215976Sjmallett#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3) 434215976Sjmallett#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4) 435215976Sjmallett#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5) 436215976Sjmallett#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6) 437215976Sjmallett#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7) 438215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 439215976Sjmallettstatic inline uint64_t CVMX_IPD_QOSX_RED_MARKS(unsigned long offset) 440215976Sjmallett{ 441215976Sjmallett if (!( 442215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 443215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 444215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 445215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 446215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 447215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 448215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 449232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 450232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 451232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 452232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 453232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 454215976Sjmallett cvmx_warn("CVMX_IPD_QOSX_RED_MARKS(%lu) is invalid on this chip\n", offset); 455215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8; 456215976Sjmallett} 457215976Sjmallett#else 458215976Sjmallett#define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8) 459215976Sjmallett#endif 460215976Sjmallett#define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull)) 461232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 462232812Sjmallettstatic inline uint64_t CVMX_IPD_RED_BPID_ENABLEX(unsigned long block_id) 463232812Sjmallett{ 464232812Sjmallett if (!( 465232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))))) 466232812Sjmallett cvmx_warn("CVMX_IPD_RED_BPID_ENABLEX(%lu) is invalid on this chip\n", block_id); 467232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000004200ull); 468232812Sjmallett} 469232812Sjmallett#else 470232812Sjmallett#define CVMX_IPD_RED_BPID_ENABLEX(block_id) (CVMX_ADD_IO_SEG(0x00014F0000004200ull)) 471232812Sjmallett#endif 472232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 473232812Sjmallett#define CVMX_IPD_RED_DELAY CVMX_IPD_RED_DELAY_FUNC() 474232812Sjmallettstatic inline uint64_t CVMX_IPD_RED_DELAY_FUNC(void) 475232812Sjmallett{ 476232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 477232812Sjmallett cvmx_warn("CVMX_IPD_RED_DELAY not supported on this chip\n"); 478232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000004300ull); 479232812Sjmallett} 480232812Sjmallett#else 481232812Sjmallett#define CVMX_IPD_RED_DELAY (CVMX_ADD_IO_SEG(0x00014F0000004300ull)) 482232812Sjmallett#endif 483232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 484232812Sjmallett#define CVMX_IPD_RED_PORT_ENABLE CVMX_IPD_RED_PORT_ENABLE_FUNC() 485232812Sjmallettstatic inline uint64_t CVMX_IPD_RED_PORT_ENABLE_FUNC(void) 486232812Sjmallett{ 487232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 488232812Sjmallett cvmx_warn("CVMX_IPD_RED_PORT_ENABLE not supported on this chip\n"); 489232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F00000002D8ull); 490232812Sjmallett} 491232812Sjmallett#else 492215976Sjmallett#define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull)) 493232812Sjmallett#endif 494215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 495215976Sjmallett#define CVMX_IPD_RED_PORT_ENABLE2 CVMX_IPD_RED_PORT_ENABLE2_FUNC() 496215976Sjmallettstatic inline uint64_t CVMX_IPD_RED_PORT_ENABLE2_FUNC(void) 497215976Sjmallett{ 498232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 499215976Sjmallett cvmx_warn("CVMX_IPD_RED_PORT_ENABLE2 not supported on this chip\n"); 500215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F00000003A8ull); 501215976Sjmallett} 502215976Sjmallett#else 503215976Sjmallett#define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull)) 504215976Sjmallett#endif 505215976Sjmallett#define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0) 506215976Sjmallett#define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1) 507215976Sjmallett#define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2) 508215976Sjmallett#define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3) 509215976Sjmallett#define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4) 510215976Sjmallett#define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5) 511215976Sjmallett#define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6) 512215976Sjmallett#define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7) 513215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 514215976Sjmallettstatic inline uint64_t CVMX_IPD_RED_QUEX_PARAM(unsigned long offset) 515215976Sjmallett{ 516215976Sjmallett if (!( 517215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 518215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 519215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 520215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 521215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 522215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 523215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 524232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 525232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 526232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 527232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 528232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 529215976Sjmallett cvmx_warn("CVMX_IPD_RED_QUEX_PARAM(%lu) is invalid on this chip\n", offset); 530215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8; 531215976Sjmallett} 532215976Sjmallett#else 533215976Sjmallett#define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8) 534215976Sjmallett#endif 535232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 536232812Sjmallett#define CVMX_IPD_REQ_WGT CVMX_IPD_REQ_WGT_FUNC() 537232812Sjmallettstatic inline uint64_t CVMX_IPD_REQ_WGT_FUNC(void) 538232812Sjmallett{ 539232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 540232812Sjmallett cvmx_warn("CVMX_IPD_REQ_WGT not supported on this chip\n"); 541232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000004418ull); 542232812Sjmallett} 543232812Sjmallett#else 544232812Sjmallett#define CVMX_IPD_REQ_WGT (CVMX_ADD_IO_SEG(0x00014F0000004418ull)) 545232812Sjmallett#endif 546215976Sjmallett#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull)) 547232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 548232812Sjmallett#define CVMX_IPD_SUB_PORT_FCS CVMX_IPD_SUB_PORT_FCS_FUNC() 549232812Sjmallettstatic inline uint64_t CVMX_IPD_SUB_PORT_FCS_FUNC(void) 550232812Sjmallett{ 551232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 552232812Sjmallett cvmx_warn("CVMX_IPD_SUB_PORT_FCS not supported on this chip\n"); 553232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000170ull); 554232812Sjmallett} 555232812Sjmallett#else 556215976Sjmallett#define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull)) 557232812Sjmallett#endif 558215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 559215976Sjmallett#define CVMX_IPD_SUB_PORT_QOS_CNT CVMX_IPD_SUB_PORT_QOS_CNT_FUNC() 560215976Sjmallettstatic inline uint64_t CVMX_IPD_SUB_PORT_QOS_CNT_FUNC(void) 561215976Sjmallett{ 562232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 563215976Sjmallett cvmx_warn("CVMX_IPD_SUB_PORT_QOS_CNT not supported on this chip\n"); 564215976Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000800ull); 565215976Sjmallett} 566215976Sjmallett#else 567215976Sjmallett#define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull)) 568215976Sjmallett#endif 569215976Sjmallett#define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull)) 570232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 571232812Sjmallett#define CVMX_IPD_WQE_PTR_VALID CVMX_IPD_WQE_PTR_VALID_FUNC() 572232812Sjmallettstatic inline uint64_t CVMX_IPD_WQE_PTR_VALID_FUNC(void) 573232812Sjmallett{ 574232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 575232812Sjmallett cvmx_warn("CVMX_IPD_WQE_PTR_VALID not supported on this chip\n"); 576232812Sjmallett return CVMX_ADD_IO_SEG(0x00014F0000000360ull); 577232812Sjmallett} 578232812Sjmallett#else 579215976Sjmallett#define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull)) 580232812Sjmallett#endif 581215976Sjmallett 582215976Sjmallett/** 583215976Sjmallett * cvmx_ipd_1st_mbuff_skip 584215976Sjmallett * 585215976Sjmallett * IPD_1ST_MBUFF_SKIP = IPD First MBUFF Word Skip Size 586215976Sjmallett * 587215976Sjmallett * The number of words that the IPD will skip when writing the first MBUFF. 588215976Sjmallett */ 589232812Sjmallettunion cvmx_ipd_1st_mbuff_skip { 590215976Sjmallett uint64_t u64; 591232812Sjmallett struct cvmx_ipd_1st_mbuff_skip_s { 592232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 593215976Sjmallett uint64_t reserved_6_63 : 58; 594215976Sjmallett uint64_t skip_sz : 6; /**< The number of 8-byte words from the top of the 595215976Sjmallett 1st MBUFF that the IPD will store the next-pointer. 596215976Sjmallett Legal values are 0 to 32, where the MAX value 597215976Sjmallett is also limited to: 598215976Sjmallett IPD_PACKET_MBUFF_SIZE[MB_SIZE] - 18. 599215976Sjmallett Must be at least 16 when IPD_CTL_STATUS[NO_WPTR] 600215976Sjmallett is set. */ 601215976Sjmallett#else 602215976Sjmallett uint64_t skip_sz : 6; 603215976Sjmallett uint64_t reserved_6_63 : 58; 604215976Sjmallett#endif 605215976Sjmallett } s; 606215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn30xx; 607215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn31xx; 608215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn38xx; 609215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn38xxp2; 610215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn50xx; 611215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn52xx; 612215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn52xxp1; 613215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn56xx; 614215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1; 615215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn58xx; 616215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1; 617232812Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn61xx; 618215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn63xx; 619215976Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn63xxp1; 620232812Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn66xx; 621232812Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn68xx; 622232812Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cn68xxp1; 623232812Sjmallett struct cvmx_ipd_1st_mbuff_skip_s cnf71xx; 624215976Sjmallett}; 625215976Sjmalletttypedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_1st_mbuff_skip_t; 626215976Sjmallett 627215976Sjmallett/** 628215976Sjmallett * cvmx_ipd_1st_next_ptr_back 629215976Sjmallett * 630215976Sjmallett * IPD_1st_NEXT_PTR_BACK = IPD First Next Pointer Back Values 631215976Sjmallett * 632215976Sjmallett * Contains the Back Field for use in creating the Next Pointer Header for the First MBUF 633215976Sjmallett */ 634232812Sjmallettunion cvmx_ipd_1st_next_ptr_back { 635215976Sjmallett uint64_t u64; 636232812Sjmallett struct cvmx_ipd_1st_next_ptr_back_s { 637232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 638215976Sjmallett uint64_t reserved_4_63 : 60; 639215976Sjmallett uint64_t back : 4; /**< Used to find head of buffer from the nxt-hdr-ptr. */ 640215976Sjmallett#else 641215976Sjmallett uint64_t back : 4; 642215976Sjmallett uint64_t reserved_4_63 : 60; 643215976Sjmallett#endif 644215976Sjmallett } s; 645215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn30xx; 646215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn31xx; 647215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn38xx; 648215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn38xxp2; 649215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn50xx; 650215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn52xx; 651215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn52xxp1; 652215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn56xx; 653215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1; 654215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn58xx; 655215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1; 656232812Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn61xx; 657215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn63xx; 658215976Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn63xxp1; 659232812Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn66xx; 660232812Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn68xx; 661232812Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cn68xxp1; 662232812Sjmallett struct cvmx_ipd_1st_next_ptr_back_s cnf71xx; 663215976Sjmallett}; 664215976Sjmalletttypedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_1st_next_ptr_back_t; 665215976Sjmallett 666215976Sjmallett/** 667215976Sjmallett * cvmx_ipd_2nd_next_ptr_back 668215976Sjmallett * 669215976Sjmallett * IPD_2nd_NEXT_PTR_BACK = IPD Second Next Pointer Back Value 670215976Sjmallett * 671215976Sjmallett * Contains the Back Field for use in creating the Next Pointer Header for the First MBUF 672215976Sjmallett */ 673232812Sjmallettunion cvmx_ipd_2nd_next_ptr_back { 674215976Sjmallett uint64_t u64; 675232812Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s { 676232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 677215976Sjmallett uint64_t reserved_4_63 : 60; 678215976Sjmallett uint64_t back : 4; /**< Used to find head of buffer from the nxt-hdr-ptr. */ 679215976Sjmallett#else 680215976Sjmallett uint64_t back : 4; 681215976Sjmallett uint64_t reserved_4_63 : 60; 682215976Sjmallett#endif 683215976Sjmallett } s; 684215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn30xx; 685215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn31xx; 686215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn38xx; 687215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn38xxp2; 688215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn50xx; 689215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn52xx; 690215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn52xxp1; 691215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn56xx; 692215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1; 693215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn58xx; 694215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1; 695232812Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn61xx; 696215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn63xx; 697215976Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn63xxp1; 698232812Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn66xx; 699232812Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn68xx; 700232812Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cn68xxp1; 701232812Sjmallett struct cvmx_ipd_2nd_next_ptr_back_s cnf71xx; 702215976Sjmallett}; 703215976Sjmalletttypedef union cvmx_ipd_2nd_next_ptr_back cvmx_ipd_2nd_next_ptr_back_t; 704215976Sjmallett 705215976Sjmallett/** 706215976Sjmallett * cvmx_ipd_bist_status 707215976Sjmallett * 708215976Sjmallett * IPD_BIST_STATUS = IPD BIST STATUS 709215976Sjmallett * 710215976Sjmallett * BIST Status for IPD's Memories. 711215976Sjmallett */ 712232812Sjmallettunion cvmx_ipd_bist_status { 713215976Sjmallett uint64_t u64; 714232812Sjmallett struct cvmx_ipd_bist_status_s { 715232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 716232812Sjmallett uint64_t reserved_23_63 : 41; 717232812Sjmallett uint64_t iiwo1 : 1; /**< IPD IOB WQE Dataout MEM1 Bist Status. */ 718232812Sjmallett uint64_t iiwo0 : 1; /**< IPD IOB WQE Dataout MEM0 Bist Status. */ 719232812Sjmallett uint64_t iio1 : 1; /**< IPD IOB Dataout MEM1 Bist Status. */ 720232812Sjmallett uint64_t iio0 : 1; /**< IPD IOB Dataout MEM0 Bist Status. */ 721232812Sjmallett uint64_t pbm4 : 1; /**< PBM4Memory Bist Status. */ 722215976Sjmallett uint64_t csr_mem : 1; /**< CSR Register Memory Bist Status. */ 723215976Sjmallett uint64_t csr_ncmd : 1; /**< CSR NCB Commands Memory Bist Status. */ 724215976Sjmallett uint64_t pwq_wqed : 1; /**< PWQ PIP WQE DONE Memory Bist Status. */ 725215976Sjmallett uint64_t pwq_wp1 : 1; /**< PWQ WQE PAGE1 PTR Memory Bist Status. */ 726215976Sjmallett uint64_t pwq_pow : 1; /**< PWQ POW MEM Memory Bist Status. */ 727215976Sjmallett uint64_t ipq_pbe1 : 1; /**< IPQ PBE1 Memory Bist Status. */ 728215976Sjmallett uint64_t ipq_pbe0 : 1; /**< IPQ PBE0 Memory Bist Status. */ 729215976Sjmallett uint64_t pbm3 : 1; /**< PBM3 Memory Bist Status. */ 730215976Sjmallett uint64_t pbm2 : 1; /**< PBM2 Memory Bist Status. */ 731215976Sjmallett uint64_t pbm1 : 1; /**< PBM1 Memory Bist Status. */ 732215976Sjmallett uint64_t pbm0 : 1; /**< PBM0 Memory Bist Status. */ 733215976Sjmallett uint64_t pbm_word : 1; /**< PBM_WORD Memory Bist Status. */ 734215976Sjmallett uint64_t pwq1 : 1; /**< PWQ1 Memory Bist Status. */ 735215976Sjmallett uint64_t pwq0 : 1; /**< PWQ0 Memory Bist Status. */ 736215976Sjmallett uint64_t prc_off : 1; /**< PRC_OFF Memory Bist Status. */ 737215976Sjmallett uint64_t ipd_old : 1; /**< IPD_OLD Memory Bist Status. */ 738215976Sjmallett uint64_t ipd_new : 1; /**< IPD_NEW Memory Bist Status. */ 739215976Sjmallett uint64_t pwp : 1; /**< PWP Memory Bist Status. */ 740215976Sjmallett#else 741215976Sjmallett uint64_t pwp : 1; 742215976Sjmallett uint64_t ipd_new : 1; 743215976Sjmallett uint64_t ipd_old : 1; 744215976Sjmallett uint64_t prc_off : 1; 745215976Sjmallett uint64_t pwq0 : 1; 746215976Sjmallett uint64_t pwq1 : 1; 747215976Sjmallett uint64_t pbm_word : 1; 748215976Sjmallett uint64_t pbm0 : 1; 749215976Sjmallett uint64_t pbm1 : 1; 750215976Sjmallett uint64_t pbm2 : 1; 751215976Sjmallett uint64_t pbm3 : 1; 752215976Sjmallett uint64_t ipq_pbe0 : 1; 753215976Sjmallett uint64_t ipq_pbe1 : 1; 754215976Sjmallett uint64_t pwq_pow : 1; 755215976Sjmallett uint64_t pwq_wp1 : 1; 756215976Sjmallett uint64_t pwq_wqed : 1; 757215976Sjmallett uint64_t csr_ncmd : 1; 758215976Sjmallett uint64_t csr_mem : 1; 759232812Sjmallett uint64_t pbm4 : 1; 760232812Sjmallett uint64_t iio0 : 1; 761232812Sjmallett uint64_t iio1 : 1; 762232812Sjmallett uint64_t iiwo0 : 1; 763232812Sjmallett uint64_t iiwo1 : 1; 764232812Sjmallett uint64_t reserved_23_63 : 41; 765215976Sjmallett#endif 766215976Sjmallett } s; 767232812Sjmallett struct cvmx_ipd_bist_status_cn30xx { 768232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 769215976Sjmallett uint64_t reserved_16_63 : 48; 770215976Sjmallett uint64_t pwq_wqed : 1; /**< PWQ PIP WQE DONE Memory Bist Status. */ 771215976Sjmallett uint64_t pwq_wp1 : 1; /**< PWQ WQE PAGE1 PTR Memory Bist Status. */ 772215976Sjmallett uint64_t pwq_pow : 1; /**< PWQ POW MEM Memory Bist Status. */ 773215976Sjmallett uint64_t ipq_pbe1 : 1; /**< IPQ PBE1 Memory Bist Status. */ 774215976Sjmallett uint64_t ipq_pbe0 : 1; /**< IPQ PBE0 Memory Bist Status. */ 775215976Sjmallett uint64_t pbm3 : 1; /**< PBM3 Memory Bist Status. */ 776215976Sjmallett uint64_t pbm2 : 1; /**< PBM2 Memory Bist Status. */ 777215976Sjmallett uint64_t pbm1 : 1; /**< PBM1 Memory Bist Status. */ 778215976Sjmallett uint64_t pbm0 : 1; /**< PBM0 Memory Bist Status. */ 779215976Sjmallett uint64_t pbm_word : 1; /**< PBM_WORD Memory Bist Status. */ 780215976Sjmallett uint64_t pwq1 : 1; /**< PWQ1 Memory Bist Status. */ 781215976Sjmallett uint64_t pwq0 : 1; /**< PWQ0 Memory Bist Status. */ 782215976Sjmallett uint64_t prc_off : 1; /**< PRC_OFF Memory Bist Status. */ 783215976Sjmallett uint64_t ipd_old : 1; /**< IPD_OLD Memory Bist Status. */ 784215976Sjmallett uint64_t ipd_new : 1; /**< IPD_NEW Memory Bist Status. */ 785215976Sjmallett uint64_t pwp : 1; /**< PWP Memory Bist Status. */ 786215976Sjmallett#else 787215976Sjmallett uint64_t pwp : 1; 788215976Sjmallett uint64_t ipd_new : 1; 789215976Sjmallett uint64_t ipd_old : 1; 790215976Sjmallett uint64_t prc_off : 1; 791215976Sjmallett uint64_t pwq0 : 1; 792215976Sjmallett uint64_t pwq1 : 1; 793215976Sjmallett uint64_t pbm_word : 1; 794215976Sjmallett uint64_t pbm0 : 1; 795215976Sjmallett uint64_t pbm1 : 1; 796215976Sjmallett uint64_t pbm2 : 1; 797215976Sjmallett uint64_t pbm3 : 1; 798215976Sjmallett uint64_t ipq_pbe0 : 1; 799215976Sjmallett uint64_t ipq_pbe1 : 1; 800215976Sjmallett uint64_t pwq_pow : 1; 801215976Sjmallett uint64_t pwq_wp1 : 1; 802215976Sjmallett uint64_t pwq_wqed : 1; 803215976Sjmallett uint64_t reserved_16_63 : 48; 804215976Sjmallett#endif 805215976Sjmallett } cn30xx; 806215976Sjmallett struct cvmx_ipd_bist_status_cn30xx cn31xx; 807215976Sjmallett struct cvmx_ipd_bist_status_cn30xx cn38xx; 808215976Sjmallett struct cvmx_ipd_bist_status_cn30xx cn38xxp2; 809215976Sjmallett struct cvmx_ipd_bist_status_cn30xx cn50xx; 810232812Sjmallett struct cvmx_ipd_bist_status_cn52xx { 811232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 812232812Sjmallett uint64_t reserved_18_63 : 46; 813232812Sjmallett uint64_t csr_mem : 1; /**< CSR Register Memory Bist Status. */ 814232812Sjmallett uint64_t csr_ncmd : 1; /**< CSR NCB Commands Memory Bist Status. */ 815232812Sjmallett uint64_t pwq_wqed : 1; /**< PWQ PIP WQE DONE Memory Bist Status. */ 816232812Sjmallett uint64_t pwq_wp1 : 1; /**< PWQ WQE PAGE1 PTR Memory Bist Status. */ 817232812Sjmallett uint64_t pwq_pow : 1; /**< PWQ POW MEM Memory Bist Status. */ 818232812Sjmallett uint64_t ipq_pbe1 : 1; /**< IPQ PBE1 Memory Bist Status. */ 819232812Sjmallett uint64_t ipq_pbe0 : 1; /**< IPQ PBE0 Memory Bist Status. */ 820232812Sjmallett uint64_t pbm3 : 1; /**< PBM3 Memory Bist Status. */ 821232812Sjmallett uint64_t pbm2 : 1; /**< PBM2 Memory Bist Status. */ 822232812Sjmallett uint64_t pbm1 : 1; /**< PBM1 Memory Bist Status. */ 823232812Sjmallett uint64_t pbm0 : 1; /**< PBM0 Memory Bist Status. */ 824232812Sjmallett uint64_t pbm_word : 1; /**< PBM_WORD Memory Bist Status. */ 825232812Sjmallett uint64_t pwq1 : 1; /**< PWQ1 Memory Bist Status. */ 826232812Sjmallett uint64_t pwq0 : 1; /**< PWQ0 Memory Bist Status. */ 827232812Sjmallett uint64_t prc_off : 1; /**< PRC_OFF Memory Bist Status. */ 828232812Sjmallett uint64_t ipd_old : 1; /**< IPD_OLD Memory Bist Status. */ 829232812Sjmallett uint64_t ipd_new : 1; /**< IPD_NEW Memory Bist Status. */ 830232812Sjmallett uint64_t pwp : 1; /**< PWP Memory Bist Status. */ 831232812Sjmallett#else 832232812Sjmallett uint64_t pwp : 1; 833232812Sjmallett uint64_t ipd_new : 1; 834232812Sjmallett uint64_t ipd_old : 1; 835232812Sjmallett uint64_t prc_off : 1; 836232812Sjmallett uint64_t pwq0 : 1; 837232812Sjmallett uint64_t pwq1 : 1; 838232812Sjmallett uint64_t pbm_word : 1; 839232812Sjmallett uint64_t pbm0 : 1; 840232812Sjmallett uint64_t pbm1 : 1; 841232812Sjmallett uint64_t pbm2 : 1; 842232812Sjmallett uint64_t pbm3 : 1; 843232812Sjmallett uint64_t ipq_pbe0 : 1; 844232812Sjmallett uint64_t ipq_pbe1 : 1; 845232812Sjmallett uint64_t pwq_pow : 1; 846232812Sjmallett uint64_t pwq_wp1 : 1; 847232812Sjmallett uint64_t pwq_wqed : 1; 848232812Sjmallett uint64_t csr_ncmd : 1; 849232812Sjmallett uint64_t csr_mem : 1; 850232812Sjmallett uint64_t reserved_18_63 : 46; 851232812Sjmallett#endif 852232812Sjmallett } cn52xx; 853232812Sjmallett struct cvmx_ipd_bist_status_cn52xx cn52xxp1; 854232812Sjmallett struct cvmx_ipd_bist_status_cn52xx cn56xx; 855232812Sjmallett struct cvmx_ipd_bist_status_cn52xx cn56xxp1; 856215976Sjmallett struct cvmx_ipd_bist_status_cn30xx cn58xx; 857215976Sjmallett struct cvmx_ipd_bist_status_cn30xx cn58xxp1; 858232812Sjmallett struct cvmx_ipd_bist_status_cn52xx cn61xx; 859232812Sjmallett struct cvmx_ipd_bist_status_cn52xx cn63xx; 860232812Sjmallett struct cvmx_ipd_bist_status_cn52xx cn63xxp1; 861232812Sjmallett struct cvmx_ipd_bist_status_cn52xx cn66xx; 862232812Sjmallett struct cvmx_ipd_bist_status_s cn68xx; 863232812Sjmallett struct cvmx_ipd_bist_status_s cn68xxp1; 864232812Sjmallett struct cvmx_ipd_bist_status_cn52xx cnf71xx; 865215976Sjmallett}; 866215976Sjmalletttypedef union cvmx_ipd_bist_status cvmx_ipd_bist_status_t; 867215976Sjmallett 868215976Sjmallett/** 869215976Sjmallett * cvmx_ipd_bp_prt_red_end 870215976Sjmallett * 871215976Sjmallett * IPD_BP_PRT_RED_END = IPD Backpressure Port RED Enable 872215976Sjmallett * 873215976Sjmallett * When IPD applies backpressure to a PORT and the corresponding bit in this register is set, 874215976Sjmallett * the RED Unit will drop packets for that port. 875215976Sjmallett */ 876232812Sjmallettunion cvmx_ipd_bp_prt_red_end { 877215976Sjmallett uint64_t u64; 878232812Sjmallett struct cvmx_ipd_bp_prt_red_end_s { 879232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 880232812Sjmallett uint64_t reserved_48_63 : 16; 881232812Sjmallett uint64_t prt_enb : 48; /**< The port corresponding to the bit position in this 882215976Sjmallett field will drop all NON-RAW packets to that port 883215976Sjmallett when port level backpressure is applied to that 884215976Sjmallett port. The applying of port-level backpressure for 885215976Sjmallett this dropping does not take into consideration the 886215976Sjmallett value of IPD_PORTX_BP_PAGE_CNT[BP_ENB], nor 887215976Sjmallett IPD_RED_PORT_ENABLE[PRT_ENB]. */ 888215976Sjmallett#else 889232812Sjmallett uint64_t prt_enb : 48; 890232812Sjmallett uint64_t reserved_48_63 : 16; 891215976Sjmallett#endif 892215976Sjmallett } s; 893232812Sjmallett struct cvmx_ipd_bp_prt_red_end_cn30xx { 894232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 895215976Sjmallett uint64_t reserved_36_63 : 28; 896215976Sjmallett uint64_t prt_enb : 36; /**< The port corresponding to the bit position in this 897215976Sjmallett field, will allow RED to drop back when port level 898215976Sjmallett backpressure is applied to the port. The applying 899215976Sjmallett of port-level backpressure for this RED dropping 900215976Sjmallett does not take into consideration the value of 901215976Sjmallett IPD_PORTX_BP_PAGE_CNT[BP_ENB]. */ 902215976Sjmallett#else 903215976Sjmallett uint64_t prt_enb : 36; 904215976Sjmallett uint64_t reserved_36_63 : 28; 905215976Sjmallett#endif 906215976Sjmallett } cn30xx; 907215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx; 908215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx; 909215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2; 910215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx; 911232812Sjmallett struct cvmx_ipd_bp_prt_red_end_cn52xx { 912232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 913215976Sjmallett uint64_t reserved_40_63 : 24; 914215976Sjmallett uint64_t prt_enb : 40; /**< The port corresponding to the bit position in this 915215976Sjmallett field, will allow RED to drop back when port level 916215976Sjmallett backpressure is applied to the port. The applying 917215976Sjmallett of port-level backpressure for this RED dropping 918215976Sjmallett does not take into consideration the value of 919215976Sjmallett IPD_PORTX_BP_PAGE_CNT[BP_ENB]. */ 920215976Sjmallett#else 921215976Sjmallett uint64_t prt_enb : 40; 922215976Sjmallett uint64_t reserved_40_63 : 24; 923215976Sjmallett#endif 924215976Sjmallett } cn52xx; 925215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn52xx cn52xxp1; 926215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xx; 927215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xxp1; 928215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx; 929215976Sjmallett struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1; 930232812Sjmallett struct cvmx_ipd_bp_prt_red_end_s cn61xx; 931232812Sjmallett struct cvmx_ipd_bp_prt_red_end_cn63xx { 932232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 933232812Sjmallett uint64_t reserved_44_63 : 20; 934232812Sjmallett uint64_t prt_enb : 44; /**< The port corresponding to the bit position in this 935232812Sjmallett field will drop all NON-RAW packets to that port 936232812Sjmallett when port level backpressure is applied to that 937232812Sjmallett port. The applying of port-level backpressure for 938232812Sjmallett this dropping does not take into consideration the 939232812Sjmallett value of IPD_PORTX_BP_PAGE_CNT[BP_ENB], nor 940232812Sjmallett IPD_RED_PORT_ENABLE[PRT_ENB]. */ 941232812Sjmallett#else 942232812Sjmallett uint64_t prt_enb : 44; 943232812Sjmallett uint64_t reserved_44_63 : 20; 944232812Sjmallett#endif 945232812Sjmallett } cn63xx; 946232812Sjmallett struct cvmx_ipd_bp_prt_red_end_cn63xx cn63xxp1; 947232812Sjmallett struct cvmx_ipd_bp_prt_red_end_s cn66xx; 948232812Sjmallett struct cvmx_ipd_bp_prt_red_end_s cnf71xx; 949215976Sjmallett}; 950215976Sjmalletttypedef union cvmx_ipd_bp_prt_red_end cvmx_ipd_bp_prt_red_end_t; 951215976Sjmallett 952215976Sjmallett/** 953232812Sjmallett * cvmx_ipd_bpid#_mbuf_th 954232812Sjmallett * 955232812Sjmallett * 0x2000 2FFF 956232812Sjmallett * 957232812Sjmallett * IPD_BPIDX_MBUF_TH = IPD BPID MBUFF Threshold 958232812Sjmallett * 959232812Sjmallett * The number of MBUFFs in use by the BPID, that when exceeded, backpressure will be applied to the BPID. 960232812Sjmallett */ 961232812Sjmallettunion cvmx_ipd_bpidx_mbuf_th { 962232812Sjmallett uint64_t u64; 963232812Sjmallett struct cvmx_ipd_bpidx_mbuf_th_s { 964232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 965232812Sjmallett uint64_t reserved_18_63 : 46; 966232812Sjmallett uint64_t bp_enb : 1; /**< When set '1' BP will be applied, if '0' BP will 967232812Sjmallett not be applied to bpid. */ 968232812Sjmallett uint64_t page_cnt : 17; /**< The number of page pointers assigned to 969232812Sjmallett the BPID, that when exceeded will cause 970232812Sjmallett back-pressure to be applied to the BPID. 971232812Sjmallett This value is in 256 page-pointer increments, 972232812Sjmallett (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */ 973232812Sjmallett#else 974232812Sjmallett uint64_t page_cnt : 17; 975232812Sjmallett uint64_t bp_enb : 1; 976232812Sjmallett uint64_t reserved_18_63 : 46; 977232812Sjmallett#endif 978232812Sjmallett } s; 979232812Sjmallett struct cvmx_ipd_bpidx_mbuf_th_s cn68xx; 980232812Sjmallett struct cvmx_ipd_bpidx_mbuf_th_s cn68xxp1; 981232812Sjmallett}; 982232812Sjmalletttypedef union cvmx_ipd_bpidx_mbuf_th cvmx_ipd_bpidx_mbuf_th_t; 983232812Sjmallett 984232812Sjmallett/** 985232812Sjmallett * cvmx_ipd_bpid_bp_counter# 986232812Sjmallett * 987232812Sjmallett * RESERVE SPACE UPTO 0x2FFF 988232812Sjmallett * 989232812Sjmallett * 0x3000 0x3ffff 990232812Sjmallett * 991232812Sjmallett * IPD_BPID_BP_COUNTERX = MBUF BPID Counters used to generate Back Pressure Per BPID. 992232812Sjmallett */ 993232812Sjmallettunion cvmx_ipd_bpid_bp_counterx { 994232812Sjmallett uint64_t u64; 995232812Sjmallett struct cvmx_ipd_bpid_bp_counterx_s { 996232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 997232812Sjmallett uint64_t reserved_25_63 : 39; 998232812Sjmallett uint64_t cnt_val : 25; /**< Number of MBUFs being used by data on this BPID. */ 999232812Sjmallett#else 1000232812Sjmallett uint64_t cnt_val : 25; 1001232812Sjmallett uint64_t reserved_25_63 : 39; 1002232812Sjmallett#endif 1003232812Sjmallett } s; 1004232812Sjmallett struct cvmx_ipd_bpid_bp_counterx_s cn68xx; 1005232812Sjmallett struct cvmx_ipd_bpid_bp_counterx_s cn68xxp1; 1006232812Sjmallett}; 1007232812Sjmalletttypedef union cvmx_ipd_bpid_bp_counterx cvmx_ipd_bpid_bp_counterx_t; 1008232812Sjmallett 1009232812Sjmallett/** 1010215976Sjmallett * cvmx_ipd_clk_count 1011215976Sjmallett * 1012215976Sjmallett * IPD_CLK_COUNT = IPD Clock Count 1013215976Sjmallett * 1014215976Sjmallett * Counts the number of core clocks periods since the de-asserition of reset. 1015215976Sjmallett */ 1016232812Sjmallettunion cvmx_ipd_clk_count { 1017215976Sjmallett uint64_t u64; 1018232812Sjmallett struct cvmx_ipd_clk_count_s { 1019232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1020215976Sjmallett uint64_t clk_cnt : 64; /**< This counter will be zeroed when reset is applied 1021215976Sjmallett and will increment every rising edge of the 1022215976Sjmallett core-clock. */ 1023215976Sjmallett#else 1024215976Sjmallett uint64_t clk_cnt : 64; 1025215976Sjmallett#endif 1026215976Sjmallett } s; 1027215976Sjmallett struct cvmx_ipd_clk_count_s cn30xx; 1028215976Sjmallett struct cvmx_ipd_clk_count_s cn31xx; 1029215976Sjmallett struct cvmx_ipd_clk_count_s cn38xx; 1030215976Sjmallett struct cvmx_ipd_clk_count_s cn38xxp2; 1031215976Sjmallett struct cvmx_ipd_clk_count_s cn50xx; 1032215976Sjmallett struct cvmx_ipd_clk_count_s cn52xx; 1033215976Sjmallett struct cvmx_ipd_clk_count_s cn52xxp1; 1034215976Sjmallett struct cvmx_ipd_clk_count_s cn56xx; 1035215976Sjmallett struct cvmx_ipd_clk_count_s cn56xxp1; 1036215976Sjmallett struct cvmx_ipd_clk_count_s cn58xx; 1037215976Sjmallett struct cvmx_ipd_clk_count_s cn58xxp1; 1038232812Sjmallett struct cvmx_ipd_clk_count_s cn61xx; 1039215976Sjmallett struct cvmx_ipd_clk_count_s cn63xx; 1040215976Sjmallett struct cvmx_ipd_clk_count_s cn63xxp1; 1041232812Sjmallett struct cvmx_ipd_clk_count_s cn66xx; 1042232812Sjmallett struct cvmx_ipd_clk_count_s cn68xx; 1043232812Sjmallett struct cvmx_ipd_clk_count_s cn68xxp1; 1044232812Sjmallett struct cvmx_ipd_clk_count_s cnf71xx; 1045215976Sjmallett}; 1046215976Sjmalletttypedef union cvmx_ipd_clk_count cvmx_ipd_clk_count_t; 1047215976Sjmallett 1048215976Sjmallett/** 1049232812Sjmallett * cvmx_ipd_credits 1050232812Sjmallett * 1051232812Sjmallett * IPD_CREDITS = IPD Credits 1052232812Sjmallett * 1053232812Sjmallett * The credits allowed for IPD. 1054232812Sjmallett */ 1055232812Sjmallettunion cvmx_ipd_credits { 1056232812Sjmallett uint64_t u64; 1057232812Sjmallett struct cvmx_ipd_credits_s { 1058232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1059232812Sjmallett uint64_t reserved_16_63 : 48; 1060232812Sjmallett uint64_t iob_wrc : 8; /**< The present number of credits available for 1061232812Sjmallett stores to the IOB. */ 1062232812Sjmallett uint64_t iob_wr : 8; /**< The number of command credits the IPD has to send 1063232812Sjmallett stores to the IOB. Legal values for this field 1064232812Sjmallett are 1-8 (a value of 0 will be treated as a 1 and 1065232812Sjmallett a value greater than 8 will be treated as an 8. */ 1066232812Sjmallett#else 1067232812Sjmallett uint64_t iob_wr : 8; 1068232812Sjmallett uint64_t iob_wrc : 8; 1069232812Sjmallett uint64_t reserved_16_63 : 48; 1070232812Sjmallett#endif 1071232812Sjmallett } s; 1072232812Sjmallett struct cvmx_ipd_credits_s cn68xx; 1073232812Sjmallett struct cvmx_ipd_credits_s cn68xxp1; 1074232812Sjmallett}; 1075232812Sjmalletttypedef union cvmx_ipd_credits cvmx_ipd_credits_t; 1076232812Sjmallett 1077232812Sjmallett/** 1078215976Sjmallett * cvmx_ipd_ctl_status 1079215976Sjmallett * 1080215976Sjmallett * IPD_CTL_STATUS = IPD's Control Status Register 1081215976Sjmallett * 1082215976Sjmallett * The number of words in a MBUFF used for packet data store. 1083215976Sjmallett */ 1084232812Sjmallettunion cvmx_ipd_ctl_status { 1085215976Sjmallett uint64_t u64; 1086232812Sjmallett struct cvmx_ipd_ctl_status_s { 1087232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1088215976Sjmallett uint64_t reserved_18_63 : 46; 1089215976Sjmallett uint64_t use_sop : 1; /**< When '1' the SOP sent by the MAC will be used in 1090215976Sjmallett place of the SOP generated by the IPD. */ 1091215976Sjmallett uint64_t rst_done : 1; /**< When '0' IPD has finished reset. No access 1092215976Sjmallett except the reading of this bit should occur to the 1093215976Sjmallett IPD until this is asserted. Or a 1000 core clock 1094215976Sjmallett cycles has passed after the de-assertion of reset. */ 1095215976Sjmallett uint64_t clken : 1; /**< Controls the conditional clocking within IPD 1096215976Sjmallett 0=Allow HW to control the clocks 1097215976Sjmallett 1=Force the clocks to be always on */ 1098215976Sjmallett uint64_t no_wptr : 1; /**< When set '1' the WQE pointers will not be used and 1099215976Sjmallett the WQE will be located at the front of the packet. 1100215976Sjmallett When set: 1101215976Sjmallett - IPD_WQE_FPA_QUEUE[WQE_QUE] is not used 1102215976Sjmallett - IPD_1ST_MBUFF_SKIP[SKIP_SZ] must be at least 16 1103215976Sjmallett - If 16 <= IPD_1ST_MBUFF_SKIP[SKIP_SZ] <= 31 then 1104215976Sjmallett the WQE will be written into the first 128B 1105215976Sjmallett cache block in the first buffer that contains 1106215976Sjmallett the packet. 1107215976Sjmallett - If IPD_1ST_MBUFF_SKIP[SKIP_SZ] == 32 then 1108215976Sjmallett the WQE will be written into the second 128B 1109215976Sjmallett cache block in the first buffer that contains 1110215976Sjmallett the packet. */ 1111215976Sjmallett uint64_t pq_apkt : 1; /**< When set IPD_PORT_QOS_X_CNT WILL be incremented 1112215976Sjmallett by one for every work queue entry that is sent to 1113215976Sjmallett POW. */ 1114215976Sjmallett uint64_t pq_nabuf : 1; /**< When set IPD_PORT_QOS_X_CNT WILL NOT be 1115215976Sjmallett incremented when IPD allocates a buffer for a 1116215976Sjmallett packet. */ 1117215976Sjmallett uint64_t ipd_full : 1; /**< When clear '0' the IPD acts normaly. 1118215976Sjmallett When set '1' the IPD drive the IPD_BUFF_FULL line to 1119215976Sjmallett the IOB-arbiter, telling it to not give grants to 1120215976Sjmallett NCB devices sending packet data. */ 1121215976Sjmallett uint64_t pkt_off : 1; /**< When clear '0' the IPD working normaly, 1122215976Sjmallett buffering the received packet data. When set '1' 1123215976Sjmallett the IPD will not buffer the received packet data. */ 1124215976Sjmallett uint64_t len_m8 : 1; /**< Setting of this bit will subtract 8 from the 1125215976Sjmallett data-length field in the header written to the 1126215976Sjmallett POW and the top of a MBUFF. 1127215976Sjmallett OCTEAN generates a length that includes the 1128215976Sjmallett length of the data + 8 for the header-field. By 1129215976Sjmallett setting this bit the 8 for the instr-field will 1130215976Sjmallett not be included in the length field of the header. 1131215976Sjmallett NOTE: IPD is compliant with the spec when this 1132215976Sjmallett field is '1'. */ 1133215976Sjmallett uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 1134215976Sjmallett RSL. */ 1135215976Sjmallett uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 1136215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL], 1137215976Sjmallett IPD_PORT_BP_COUNTERS2_PAIR(port)[CNT_VAL] and 1138215976Sjmallett IPD_PORT_BP_COUNTERS3_PAIR(port)[CNT_VAL] 1139215976Sjmallett WILL be incremented by one for every work 1140215976Sjmallett queue entry that is sent to POW. */ 1141215976Sjmallett uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 1142215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL], 1143215976Sjmallett IPD_PORT_BP_COUNTERS2_PAIR(port)[CNT_VAL] and 1144215976Sjmallett IPD_PORT_BP_COUNTERS3_PAIR(port)[CNT_VAL] 1145215976Sjmallett WILL NOT be incremented when IPD allocates a 1146215976Sjmallett buffer for a packet on the port. */ 1147215976Sjmallett uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 1148215976Sjmallett uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 1149215976Sjmallett uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 1150215976Sjmallett the sending of port level backpressure to the 1151215976Sjmallett Octane input-ports. The application should NOT 1152215976Sjmallett de-assert this bit after asserting it. The 1153215976Sjmallett receivers of this bit may have been put into 1154215976Sjmallett backpressure mode and can only be released by 1155215976Sjmallett IPD informing them that the backpressure has 1156215976Sjmallett been released. 1157215976Sjmallett GMXX_INF_MODE[EN] must be set to '1' for each 1158215976Sjmallett packet interface which requires port back pressure 1159215976Sjmallett prior to setting PBP_EN to '1'. */ 1160215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 1161215976Sjmallett is written through to memory. 1162215976Sjmallett 1 ==> All packet data (and next buffer pointers) is 1163215976Sjmallett written into the cache. 1164215976Sjmallett 2 ==> The first aligned cache block holding the 1165215976Sjmallett packet data (and initial next buffer pointer) is 1166215976Sjmallett written to the L2 cache, all remaining cache blocks 1167215976Sjmallett are not written to the L2 cache. 1168215976Sjmallett 3 ==> The first two aligned cache blocks holding 1169215976Sjmallett the packet data (and initial next buffer pointer) 1170215976Sjmallett are written to the L2 cache, all remaining cache 1171215976Sjmallett blocks are not written to the L2 cache. */ 1172215976Sjmallett uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. 1173215976Sjmallett When clear '0', the IPD will appear to the 1174215976Sjmallett IOB-arbiter to be applying backpressure, this 1175215976Sjmallett causes the IOB-Arbiter to not send grants to NCB 1176215976Sjmallett devices requesting to send packet data to the IPD. */ 1177215976Sjmallett#else 1178215976Sjmallett uint64_t ipd_en : 1; 1179215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; 1180215976Sjmallett uint64_t pbp_en : 1; 1181215976Sjmallett uint64_t wqe_lend : 1; 1182215976Sjmallett uint64_t pkt_lend : 1; 1183215976Sjmallett uint64_t naddbuf : 1; 1184215976Sjmallett uint64_t addpkt : 1; 1185215976Sjmallett uint64_t reset : 1; 1186215976Sjmallett uint64_t len_m8 : 1; 1187215976Sjmallett uint64_t pkt_off : 1; 1188215976Sjmallett uint64_t ipd_full : 1; 1189215976Sjmallett uint64_t pq_nabuf : 1; 1190215976Sjmallett uint64_t pq_apkt : 1; 1191215976Sjmallett uint64_t no_wptr : 1; 1192215976Sjmallett uint64_t clken : 1; 1193215976Sjmallett uint64_t rst_done : 1; 1194215976Sjmallett uint64_t use_sop : 1; 1195215976Sjmallett uint64_t reserved_18_63 : 46; 1196215976Sjmallett#endif 1197215976Sjmallett } s; 1198232812Sjmallett struct cvmx_ipd_ctl_status_cn30xx { 1199232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1200215976Sjmallett uint64_t reserved_10_63 : 54; 1201215976Sjmallett uint64_t len_m8 : 1; /**< Setting of this bit will subtract 8 from the 1202215976Sjmallett data-length field in the header written wo the 1203215976Sjmallett POW and the top of a MBUFF. 1204215976Sjmallett OCTEAN generates a length that includes the 1205215976Sjmallett length of the data + 8 for the header-field. By 1206215976Sjmallett setting this bit the 8 for the instr-field will 1207215976Sjmallett not be included in the length field of the header. 1208215976Sjmallett NOTE: IPD is compliant with the spec when this 1209215976Sjmallett field is '1'. */ 1210215976Sjmallett uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 1211215976Sjmallett RSL. */ 1212215976Sjmallett uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 1213215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 1214215976Sjmallett WILL be incremented by one for every work 1215215976Sjmallett queue entry that is sent to POW. */ 1216215976Sjmallett uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 1217215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 1218215976Sjmallett WILL NOT be incremented when IPD allocates a 1219215976Sjmallett buffer for a packet on the port. */ 1220215976Sjmallett uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 1221215976Sjmallett uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 1222215976Sjmallett uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 1223215976Sjmallett the sending of port level backpressure to the 1224215976Sjmallett Octane input-ports. Once enabled the sending of 1225215976Sjmallett port-level-backpressure can not be disabled by 1226215976Sjmallett changing the value of this bit. 1227215976Sjmallett GMXX_INF_MODE[EN] must be set to '1' for each 1228215976Sjmallett packet interface which requires port back pressure 1229215976Sjmallett prior to setting PBP_EN to '1'. */ 1230215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 1231215976Sjmallett is written through to memory. 1232215976Sjmallett 1 ==> All packet data (and next buffer pointers) is 1233215976Sjmallett written into the cache. 1234215976Sjmallett 2 ==> The first aligned cache block holding the 1235215976Sjmallett packet data (and initial next buffer pointer) is 1236215976Sjmallett written to the L2 cache, all remaining cache blocks 1237215976Sjmallett are not written to the L2 cache. 1238215976Sjmallett 3 ==> The first two aligned cache blocks holding 1239215976Sjmallett the packet data (and initial next buffer pointer) 1240215976Sjmallett are written to the L2 cache, all remaining cache 1241215976Sjmallett blocks are not written to the L2 cache. */ 1242215976Sjmallett uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. */ 1243215976Sjmallett#else 1244215976Sjmallett uint64_t ipd_en : 1; 1245215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; 1246215976Sjmallett uint64_t pbp_en : 1; 1247215976Sjmallett uint64_t wqe_lend : 1; 1248215976Sjmallett uint64_t pkt_lend : 1; 1249215976Sjmallett uint64_t naddbuf : 1; 1250215976Sjmallett uint64_t addpkt : 1; 1251215976Sjmallett uint64_t reset : 1; 1252215976Sjmallett uint64_t len_m8 : 1; 1253215976Sjmallett uint64_t reserved_10_63 : 54; 1254215976Sjmallett#endif 1255215976Sjmallett } cn30xx; 1256215976Sjmallett struct cvmx_ipd_ctl_status_cn30xx cn31xx; 1257215976Sjmallett struct cvmx_ipd_ctl_status_cn30xx cn38xx; 1258232812Sjmallett struct cvmx_ipd_ctl_status_cn38xxp2 { 1259232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1260215976Sjmallett uint64_t reserved_9_63 : 55; 1261215976Sjmallett uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 1262215976Sjmallett RSL. */ 1263215976Sjmallett uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 1264215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 1265215976Sjmallett WILL be incremented by one for every work 1266215976Sjmallett queue entry that is sent to POW. 1267215976Sjmallett PASS-2 Field. */ 1268215976Sjmallett uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 1269215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 1270215976Sjmallett WILL NOT be incremented when IPD allocates a 1271215976Sjmallett buffer for a packet on the port. 1272215976Sjmallett PASS-2 Field. */ 1273215976Sjmallett uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 1274215976Sjmallett uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 1275215976Sjmallett uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 1276215976Sjmallett the sending of port level backpressure to the 1277215976Sjmallett Octane input-ports. Once enabled the sending of 1278215976Sjmallett port-level-backpressure can not be disabled by 1279215976Sjmallett changing the value of this bit. */ 1280215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 1281215976Sjmallett is written through to memory. 1282215976Sjmallett 1 ==> All packet data (and next buffer pointers) is 1283215976Sjmallett written into the cache. 1284215976Sjmallett 2 ==> The first aligned cache block holding the 1285215976Sjmallett packet data (and initial next buffer pointer) is 1286215976Sjmallett written to the L2 cache, all remaining cache blocks 1287215976Sjmallett are not written to the L2 cache. 1288215976Sjmallett 3 ==> The first two aligned cache blocks holding 1289215976Sjmallett the packet data (and initial next buffer pointer) 1290215976Sjmallett are written to the L2 cache, all remaining cache 1291215976Sjmallett blocks are not written to the L2 cache. */ 1292215976Sjmallett uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. */ 1293215976Sjmallett#else 1294215976Sjmallett uint64_t ipd_en : 1; 1295215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; 1296215976Sjmallett uint64_t pbp_en : 1; 1297215976Sjmallett uint64_t wqe_lend : 1; 1298215976Sjmallett uint64_t pkt_lend : 1; 1299215976Sjmallett uint64_t naddbuf : 1; 1300215976Sjmallett uint64_t addpkt : 1; 1301215976Sjmallett uint64_t reset : 1; 1302215976Sjmallett uint64_t reserved_9_63 : 55; 1303215976Sjmallett#endif 1304215976Sjmallett } cn38xxp2; 1305232812Sjmallett struct cvmx_ipd_ctl_status_cn50xx { 1306232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1307215976Sjmallett uint64_t reserved_15_63 : 49; 1308215976Sjmallett uint64_t no_wptr : 1; /**< When set '1' the WQE pointers will not be used and 1309215976Sjmallett the WQE will be located at the front of the packet. */ 1310215976Sjmallett uint64_t pq_apkt : 1; /**< Reserved. */ 1311215976Sjmallett uint64_t pq_nabuf : 1; /**< Reserved. */ 1312215976Sjmallett uint64_t ipd_full : 1; /**< When clear '0' the IPD acts normaly. 1313215976Sjmallett When set '1' the IPD drive the IPD_BUFF_FULL line to 1314215976Sjmallett the IOB-arbiter, telling it to not give grants to 1315215976Sjmallett NCB devices sending packet data. */ 1316215976Sjmallett uint64_t pkt_off : 1; /**< When clear '0' the IPD working normaly, 1317215976Sjmallett buffering the received packet data. When set '1' 1318215976Sjmallett the IPD will not buffer the received packet data. */ 1319215976Sjmallett uint64_t len_m8 : 1; /**< Setting of this bit will subtract 8 from the 1320215976Sjmallett data-length field in the header written wo the 1321215976Sjmallett POW and the top of a MBUFF. 1322215976Sjmallett OCTEAN generates a length that includes the 1323215976Sjmallett length of the data + 8 for the header-field. By 1324215976Sjmallett setting this bit the 8 for the instr-field will 1325215976Sjmallett not be included in the length field of the header. 1326215976Sjmallett NOTE: IPD is compliant with the spec when this 1327215976Sjmallett field is '1'. */ 1328215976Sjmallett uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 1329215976Sjmallett RSL. */ 1330215976Sjmallett uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 1331215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 1332215976Sjmallett WILL be incremented by one for every work 1333215976Sjmallett queue entry that is sent to POW. */ 1334215976Sjmallett uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 1335215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 1336215976Sjmallett WILL NOT be incremented when IPD allocates a 1337215976Sjmallett buffer for a packet on the port. */ 1338215976Sjmallett uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 1339215976Sjmallett uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 1340215976Sjmallett uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 1341215976Sjmallett the sending of port level backpressure to the 1342215976Sjmallett Octane input-ports. Once enabled the sending of 1343215976Sjmallett port-level-backpressure can not be disabled by 1344215976Sjmallett changing the value of this bit. 1345215976Sjmallett GMXX_INF_MODE[EN] must be set to '1' for each 1346215976Sjmallett packet interface which requires port back pressure 1347215976Sjmallett prior to setting PBP_EN to '1'. */ 1348215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 1349215976Sjmallett is written through to memory. 1350215976Sjmallett 1 ==> All packet data (and next buffer pointers) is 1351215976Sjmallett written into the cache. 1352215976Sjmallett 2 ==> The first aligned cache block holding the 1353215976Sjmallett packet data (and initial next buffer pointer) is 1354215976Sjmallett written to the L2 cache, all remaining cache blocks 1355215976Sjmallett are not written to the L2 cache. 1356215976Sjmallett 3 ==> The first two aligned cache blocks holding 1357215976Sjmallett the packet data (and initial next buffer pointer) 1358215976Sjmallett are written to the L2 cache, all remaining cache 1359215976Sjmallett blocks are not written to the L2 cache. */ 1360215976Sjmallett uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. 1361215976Sjmallett When clear '0', the IPD will appear to the 1362215976Sjmallett IOB-arbiter to be applying backpressure, this 1363215976Sjmallett causes the IOB-Arbiter to not send grants to NCB 1364215976Sjmallett devices requesting to send packet data to the IPD. */ 1365215976Sjmallett#else 1366215976Sjmallett uint64_t ipd_en : 1; 1367215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; 1368215976Sjmallett uint64_t pbp_en : 1; 1369215976Sjmallett uint64_t wqe_lend : 1; 1370215976Sjmallett uint64_t pkt_lend : 1; 1371215976Sjmallett uint64_t naddbuf : 1; 1372215976Sjmallett uint64_t addpkt : 1; 1373215976Sjmallett uint64_t reset : 1; 1374215976Sjmallett uint64_t len_m8 : 1; 1375215976Sjmallett uint64_t pkt_off : 1; 1376215976Sjmallett uint64_t ipd_full : 1; 1377215976Sjmallett uint64_t pq_nabuf : 1; 1378215976Sjmallett uint64_t pq_apkt : 1; 1379215976Sjmallett uint64_t no_wptr : 1; 1380215976Sjmallett uint64_t reserved_15_63 : 49; 1381215976Sjmallett#endif 1382215976Sjmallett } cn50xx; 1383215976Sjmallett struct cvmx_ipd_ctl_status_cn50xx cn52xx; 1384215976Sjmallett struct cvmx_ipd_ctl_status_cn50xx cn52xxp1; 1385215976Sjmallett struct cvmx_ipd_ctl_status_cn50xx cn56xx; 1386215976Sjmallett struct cvmx_ipd_ctl_status_cn50xx cn56xxp1; 1387232812Sjmallett struct cvmx_ipd_ctl_status_cn58xx { 1388232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1389215976Sjmallett uint64_t reserved_12_63 : 52; 1390215976Sjmallett uint64_t ipd_full : 1; /**< When clear '0' the IPD acts normaly. 1391215976Sjmallett When set '1' the IPD drive the IPD_BUFF_FULL line to 1392215976Sjmallett the IOB-arbiter, telling it to not give grants to 1393215976Sjmallett NCB devices sending packet data. */ 1394215976Sjmallett uint64_t pkt_off : 1; /**< When clear '0' the IPD working normaly, 1395215976Sjmallett buffering the received packet data. When set '1' 1396215976Sjmallett the IPD will not buffer the received packet data. */ 1397215976Sjmallett uint64_t len_m8 : 1; /**< Setting of this bit will subtract 8 from the 1398215976Sjmallett data-length field in the header written wo the 1399215976Sjmallett POW and the top of a MBUFF. 1400215976Sjmallett OCTEAN PASS2 generates a length that includes the 1401215976Sjmallett length of the data + 8 for the header-field. By 1402215976Sjmallett setting this bit the 8 for the instr-field will 1403215976Sjmallett not be included in the length field of the header. 1404215976Sjmallett NOTE: IPD is compliant with the spec when this 1405215976Sjmallett field is '1'. */ 1406215976Sjmallett uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 1407215976Sjmallett RSL. */ 1408215976Sjmallett uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 1409215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 1410215976Sjmallett WILL be incremented by one for every work 1411215976Sjmallett queue entry that is sent to POW. 1412215976Sjmallett PASS-2 Field. */ 1413215976Sjmallett uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 1414215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL] 1415215976Sjmallett WILL NOT be incremented when IPD allocates a 1416215976Sjmallett buffer for a packet on the port. 1417215976Sjmallett PASS-2 Field. */ 1418215976Sjmallett uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 1419215976Sjmallett uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 1420215976Sjmallett uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 1421215976Sjmallett the sending of port level backpressure to the 1422215976Sjmallett Octane input-ports. Once enabled the sending of 1423215976Sjmallett port-level-backpressure can not be disabled by 1424215976Sjmallett changing the value of this bit. */ 1425215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 1426215976Sjmallett is written through to memory. 1427215976Sjmallett 1 ==> All packet data (and next buffer pointers) is 1428215976Sjmallett written into the cache. 1429215976Sjmallett 2 ==> The first aligned cache block holding the 1430215976Sjmallett packet data (and initial next buffer pointer) is 1431215976Sjmallett written to the L2 cache, all remaining cache blocks 1432215976Sjmallett are not written to the L2 cache. 1433215976Sjmallett 3 ==> The first two aligned cache blocks holding 1434215976Sjmallett the packet data (and initial next buffer pointer) 1435215976Sjmallett are written to the L2 cache, all remaining cache 1436215976Sjmallett blocks are not written to the L2 cache. */ 1437215976Sjmallett uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. 1438215976Sjmallett When clear '0', the IPD will appear to the 1439215976Sjmallett IOB-arbiter to be applying backpressure, this 1440215976Sjmallett causes the IOB-Arbiter to not send grants to NCB 1441215976Sjmallett devices requesting to send packet data to the IPD. */ 1442215976Sjmallett#else 1443215976Sjmallett uint64_t ipd_en : 1; 1444215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; 1445215976Sjmallett uint64_t pbp_en : 1; 1446215976Sjmallett uint64_t wqe_lend : 1; 1447215976Sjmallett uint64_t pkt_lend : 1; 1448215976Sjmallett uint64_t naddbuf : 1; 1449215976Sjmallett uint64_t addpkt : 1; 1450215976Sjmallett uint64_t reset : 1; 1451215976Sjmallett uint64_t len_m8 : 1; 1452215976Sjmallett uint64_t pkt_off : 1; 1453215976Sjmallett uint64_t ipd_full : 1; 1454215976Sjmallett uint64_t reserved_12_63 : 52; 1455215976Sjmallett#endif 1456215976Sjmallett } cn58xx; 1457215976Sjmallett struct cvmx_ipd_ctl_status_cn58xx cn58xxp1; 1458232812Sjmallett struct cvmx_ipd_ctl_status_s cn61xx; 1459215976Sjmallett struct cvmx_ipd_ctl_status_s cn63xx; 1460232812Sjmallett struct cvmx_ipd_ctl_status_cn63xxp1 { 1461232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1462215976Sjmallett uint64_t reserved_16_63 : 48; 1463215976Sjmallett uint64_t clken : 1; /**< Controls the conditional clocking within IPD 1464215976Sjmallett 0=Allow HW to control the clocks 1465215976Sjmallett 1=Force the clocks to be always on */ 1466215976Sjmallett uint64_t no_wptr : 1; /**< When set '1' the WQE pointers will not be used and 1467215976Sjmallett the WQE will be located at the front of the packet. 1468215976Sjmallett When set: 1469215976Sjmallett - IPD_WQE_FPA_QUEUE[WQE_QUE] is not used 1470215976Sjmallett - IPD_1ST_MBUFF_SKIP[SKIP_SZ] must be at least 16 1471215976Sjmallett - If 16 <= IPD_1ST_MBUFF_SKIP[SKIP_SZ] <= 31 then 1472215976Sjmallett the WQE will be written into the first 128B 1473215976Sjmallett cache block in the first buffer that contains 1474215976Sjmallett the packet. 1475215976Sjmallett - If IPD_1ST_MBUFF_SKIP[SKIP_SZ] == 32 then 1476215976Sjmallett the WQE will be written into the second 128B 1477215976Sjmallett cache block in the first buffer that contains 1478215976Sjmallett the packet. */ 1479215976Sjmallett uint64_t pq_apkt : 1; /**< When set IPD_PORT_QOS_X_CNT WILL be incremented 1480215976Sjmallett by one for every work queue entry that is sent to 1481215976Sjmallett POW. */ 1482215976Sjmallett uint64_t pq_nabuf : 1; /**< When set IPD_PORT_QOS_X_CNT WILL NOT be 1483215976Sjmallett incremented when IPD allocates a buffer for a 1484215976Sjmallett packet. */ 1485215976Sjmallett uint64_t ipd_full : 1; /**< When clear '0' the IPD acts normaly. 1486215976Sjmallett When set '1' the IPD drive the IPD_BUFF_FULL line to 1487215976Sjmallett the IOB-arbiter, telling it to not give grants to 1488215976Sjmallett NCB devices sending packet data. */ 1489215976Sjmallett uint64_t pkt_off : 1; /**< When clear '0' the IPD working normaly, 1490215976Sjmallett buffering the received packet data. When set '1' 1491215976Sjmallett the IPD will not buffer the received packet data. */ 1492215976Sjmallett uint64_t len_m8 : 1; /**< Setting of this bit will subtract 8 from the 1493215976Sjmallett data-length field in the header written to the 1494215976Sjmallett POW and the top of a MBUFF. 1495215976Sjmallett OCTEAN generates a length that includes the 1496215976Sjmallett length of the data + 8 for the header-field. By 1497215976Sjmallett setting this bit the 8 for the instr-field will 1498215976Sjmallett not be included in the length field of the header. 1499215976Sjmallett NOTE: IPD is compliant with the spec when this 1500215976Sjmallett field is '1'. */ 1501215976Sjmallett uint64_t reset : 1; /**< When set '1' causes a reset of the IPD, except 1502215976Sjmallett RSL. */ 1503215976Sjmallett uint64_t addpkt : 1; /**< When IPD_CTL_STATUS[ADDPKT] is set, 1504215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL], 1505215976Sjmallett IPD_PORT_BP_COUNTERS2_PAIR(port)[CNT_VAL] and 1506215976Sjmallett IPD_PORT_BP_COUNTERS3_PAIR(port)[CNT_VAL] 1507215976Sjmallett WILL be incremented by one for every work 1508215976Sjmallett queue entry that is sent to POW. */ 1509215976Sjmallett uint64_t naddbuf : 1; /**< When IPD_CTL_STATUS[NADDBUF] is set, 1510215976Sjmallett IPD_PORT_BP_COUNTERS_PAIR(port)[CNT_VAL], 1511215976Sjmallett IPD_PORT_BP_COUNTERS2_PAIR(port)[CNT_VAL] and 1512215976Sjmallett IPD_PORT_BP_COUNTERS3_PAIR(port)[CNT_VAL] 1513215976Sjmallett WILL NOT be incremented when IPD allocates a 1514215976Sjmallett buffer for a packet on the port. */ 1515215976Sjmallett uint64_t pkt_lend : 1; /**< Changes PKT to little endian writes to L2C */ 1516215976Sjmallett uint64_t wqe_lend : 1; /**< Changes WQE to little endian writes to L2C */ 1517215976Sjmallett uint64_t pbp_en : 1; /**< Port back pressure enable. When set '1' enables 1518215976Sjmallett the sending of port level backpressure to the 1519215976Sjmallett Octane input-ports. The application should NOT 1520215976Sjmallett de-assert this bit after asserting it. The 1521215976Sjmallett receivers of this bit may have been put into 1522215976Sjmallett backpressure mode and can only be released by 1523215976Sjmallett IPD informing them that the backpressure has 1524215976Sjmallett been released. 1525215976Sjmallett GMXX_INF_MODE[EN] must be set to '1' for each 1526215976Sjmallett packet interface which requires port back pressure 1527215976Sjmallett prior to setting PBP_EN to '1'. */ 1528215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; /**< 0 ==> All packet data (and next buffer pointers) 1529215976Sjmallett is written through to memory. 1530215976Sjmallett 1 ==> All packet data (and next buffer pointers) is 1531215976Sjmallett written into the cache. 1532215976Sjmallett 2 ==> The first aligned cache block holding the 1533215976Sjmallett packet data (and initial next buffer pointer) is 1534215976Sjmallett written to the L2 cache, all remaining cache blocks 1535215976Sjmallett are not written to the L2 cache. 1536215976Sjmallett 3 ==> The first two aligned cache blocks holding 1537215976Sjmallett the packet data (and initial next buffer pointer) 1538215976Sjmallett are written to the L2 cache, all remaining cache 1539215976Sjmallett blocks are not written to the L2 cache. */ 1540215976Sjmallett uint64_t ipd_en : 1; /**< When set '1' enable the operation of the IPD. 1541215976Sjmallett When clear '0', the IPD will appear to the 1542215976Sjmallett IOB-arbiter to be applying backpressure, this 1543215976Sjmallett causes the IOB-Arbiter to not send grants to NCB 1544215976Sjmallett devices requesting to send packet data to the IPD. */ 1545215976Sjmallett#else 1546215976Sjmallett uint64_t ipd_en : 1; 1547215976Sjmallett cvmx_ipd_mode_t opc_mode : 2; 1548215976Sjmallett uint64_t pbp_en : 1; 1549215976Sjmallett uint64_t wqe_lend : 1; 1550215976Sjmallett uint64_t pkt_lend : 1; 1551215976Sjmallett uint64_t naddbuf : 1; 1552215976Sjmallett uint64_t addpkt : 1; 1553215976Sjmallett uint64_t reset : 1; 1554215976Sjmallett uint64_t len_m8 : 1; 1555215976Sjmallett uint64_t pkt_off : 1; 1556215976Sjmallett uint64_t ipd_full : 1; 1557215976Sjmallett uint64_t pq_nabuf : 1; 1558215976Sjmallett uint64_t pq_apkt : 1; 1559215976Sjmallett uint64_t no_wptr : 1; 1560215976Sjmallett uint64_t clken : 1; 1561215976Sjmallett uint64_t reserved_16_63 : 48; 1562215976Sjmallett#endif 1563215976Sjmallett } cn63xxp1; 1564232812Sjmallett struct cvmx_ipd_ctl_status_s cn66xx; 1565232812Sjmallett struct cvmx_ipd_ctl_status_s cn68xx; 1566232812Sjmallett struct cvmx_ipd_ctl_status_s cn68xxp1; 1567232812Sjmallett struct cvmx_ipd_ctl_status_s cnf71xx; 1568215976Sjmallett}; 1569215976Sjmalletttypedef union cvmx_ipd_ctl_status cvmx_ipd_ctl_status_t; 1570215976Sjmallett 1571215976Sjmallett/** 1572232812Sjmallett * cvmx_ipd_ecc_ctl 1573232812Sjmallett * 1574232812Sjmallett * IPD_ECC_CTL = IPD ECC Control 1575232812Sjmallett * 1576232812Sjmallett * Allows inserting ECC errors for testing. 1577232812Sjmallett */ 1578232812Sjmallettunion cvmx_ipd_ecc_ctl { 1579232812Sjmallett uint64_t u64; 1580232812Sjmallett struct cvmx_ipd_ecc_ctl_s { 1581232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1582232812Sjmallett uint64_t reserved_8_63 : 56; 1583232812Sjmallett uint64_t pm3_syn : 2; /**< Flip the syndrom to generate 1-bit/2-bits error 1584232812Sjmallett for testing of Packet Memory 3. 1585232812Sjmallett 2'b00 : No Error Generation 1586232812Sjmallett 2'b10, 2'b01: Flip 1 bit 1587232812Sjmallett 2'b11 : Flip 2 bits */ 1588232812Sjmallett uint64_t pm2_syn : 2; /**< Flip the syndrom to generate 1-bit/2-bits error 1589232812Sjmallett for testing of Packet Memory 2. 1590232812Sjmallett 2'b00 : No Error Generation 1591232812Sjmallett 2'b10, 2'b01: Flip 1 bit 1592232812Sjmallett 2'b11 : Flip 2 bits */ 1593232812Sjmallett uint64_t pm1_syn : 2; /**< Flip the syndrom to generate 1-bit/2-bits error 1594232812Sjmallett for testing of Packet Memory 1. 1595232812Sjmallett 2'b00 : No Error Generation 1596232812Sjmallett 2'b10, 2'b01: Flip 1 bit 1597232812Sjmallett 2'b11 : Flip 2 bits */ 1598232812Sjmallett uint64_t pm0_syn : 2; /**< Flip the syndrom to generate 1-bit/2-bits error 1599232812Sjmallett for testing of Packet Memory 0. 1600232812Sjmallett 2'b00 : No Error Generation 1601232812Sjmallett 2'b10, 2'b01: Flip 1 bit 1602232812Sjmallett 2'b11 : Flip 2 bits */ 1603232812Sjmallett#else 1604232812Sjmallett uint64_t pm0_syn : 2; 1605232812Sjmallett uint64_t pm1_syn : 2; 1606232812Sjmallett uint64_t pm2_syn : 2; 1607232812Sjmallett uint64_t pm3_syn : 2; 1608232812Sjmallett uint64_t reserved_8_63 : 56; 1609232812Sjmallett#endif 1610232812Sjmallett } s; 1611232812Sjmallett struct cvmx_ipd_ecc_ctl_s cn68xx; 1612232812Sjmallett struct cvmx_ipd_ecc_ctl_s cn68xxp1; 1613232812Sjmallett}; 1614232812Sjmalletttypedef union cvmx_ipd_ecc_ctl cvmx_ipd_ecc_ctl_t; 1615232812Sjmallett 1616232812Sjmallett/** 1617232812Sjmallett * cvmx_ipd_free_ptr_fifo_ctl 1618232812Sjmallett * 1619232812Sjmallett * IPD_FREE_PTR_FIFO_CTL = IPD's FREE Pointer FIFO Control 1620232812Sjmallett * 1621232812Sjmallett * Allows reading of the Page-Pointers stored in the IPD's FREE Fifo. 1622232812Sjmallett * See also the IPD_FREE_PTR_VALUE 1623232812Sjmallett */ 1624232812Sjmallettunion cvmx_ipd_free_ptr_fifo_ctl { 1625232812Sjmallett uint64_t u64; 1626232812Sjmallett struct cvmx_ipd_free_ptr_fifo_ctl_s { 1627232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1628232812Sjmallett uint64_t reserved_32_63 : 32; 1629232812Sjmallett uint64_t max_cnts : 7; /**< Maximum number of Packet-Pointers or WQE-Pointers 1630232812Sjmallett that COULD be in the FIFO. 1631232812Sjmallett When IPD_CTL_STATUS[NO_WPTR] is set '1' this field 1632232812Sjmallett only represents the Max number of Packet-Pointers, 1633232812Sjmallett WQE-Pointers are not used in this mode. */ 1634232812Sjmallett uint64_t wraddr : 8; /**< Present FIFO WQE Read address. */ 1635232812Sjmallett uint64_t praddr : 8; /**< Present FIFO Packet Read address. */ 1636232812Sjmallett uint64_t cena : 1; /**< Active low Chip Enable to the read the 1637232812Sjmallett pwp_fifo. This bit also controls the MUX-select 1638232812Sjmallett that steers [RADDR] to the pwp_fifo. 1639232812Sjmallett *WARNING - Setting this field to '0' will allow 1640232812Sjmallett reading of the memories thorugh the PTR field, 1641232812Sjmallett but will cause unpredictable operation of the IPD 1642232812Sjmallett under normal operation. */ 1643232812Sjmallett uint64_t raddr : 8; /**< Sets the address to read from in the pwp_fifo. 1644232812Sjmallett Addresses 0 through 63 contain Packet-Pointers and 1645232812Sjmallett addresses 64 through 127 contain WQE-Pointers. 1646232812Sjmallett When IPD_CTL_STATUS[NO_WPTR] is set '1' addresses 1647232812Sjmallett 64 through 127 are not valid. */ 1648232812Sjmallett#else 1649232812Sjmallett uint64_t raddr : 8; 1650232812Sjmallett uint64_t cena : 1; 1651232812Sjmallett uint64_t praddr : 8; 1652232812Sjmallett uint64_t wraddr : 8; 1653232812Sjmallett uint64_t max_cnts : 7; 1654232812Sjmallett uint64_t reserved_32_63 : 32; 1655232812Sjmallett#endif 1656232812Sjmallett } s; 1657232812Sjmallett struct cvmx_ipd_free_ptr_fifo_ctl_s cn68xx; 1658232812Sjmallett struct cvmx_ipd_free_ptr_fifo_ctl_s cn68xxp1; 1659232812Sjmallett}; 1660232812Sjmalletttypedef union cvmx_ipd_free_ptr_fifo_ctl cvmx_ipd_free_ptr_fifo_ctl_t; 1661232812Sjmallett 1662232812Sjmallett/** 1663232812Sjmallett * cvmx_ipd_free_ptr_value 1664232812Sjmallett * 1665232812Sjmallett * IPD_FREE_PTR_VALUE = IPD's FREE Pointer Value 1666232812Sjmallett * 1667232812Sjmallett * The value of the pointer selected through the IPD_FREE_PTR_FIFO_CTL 1668232812Sjmallett */ 1669232812Sjmallettunion cvmx_ipd_free_ptr_value { 1670232812Sjmallett uint64_t u64; 1671232812Sjmallett struct cvmx_ipd_free_ptr_value_s { 1672232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1673232812Sjmallett uint64_t reserved_33_63 : 31; 1674232812Sjmallett uint64_t ptr : 33; /**< The output of the pwp_fifo. */ 1675232812Sjmallett#else 1676232812Sjmallett uint64_t ptr : 33; 1677232812Sjmallett uint64_t reserved_33_63 : 31; 1678232812Sjmallett#endif 1679232812Sjmallett } s; 1680232812Sjmallett struct cvmx_ipd_free_ptr_value_s cn68xx; 1681232812Sjmallett struct cvmx_ipd_free_ptr_value_s cn68xxp1; 1682232812Sjmallett}; 1683232812Sjmalletttypedef union cvmx_ipd_free_ptr_value cvmx_ipd_free_ptr_value_t; 1684232812Sjmallett 1685232812Sjmallett/** 1686232812Sjmallett * cvmx_ipd_hold_ptr_fifo_ctl 1687232812Sjmallett * 1688232812Sjmallett * IPD_HOLD_PTR_FIFO_CTL = IPD's Holding Pointer FIFO Control 1689232812Sjmallett * 1690232812Sjmallett * Allows reading of the Page-Pointers stored in the IPD's Holding Fifo. 1691232812Sjmallett */ 1692232812Sjmallettunion cvmx_ipd_hold_ptr_fifo_ctl { 1693232812Sjmallett uint64_t u64; 1694232812Sjmallett struct cvmx_ipd_hold_ptr_fifo_ctl_s { 1695232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1696232812Sjmallett uint64_t reserved_43_63 : 21; 1697232812Sjmallett uint64_t ptr : 33; /**< The output of the holding-fifo. */ 1698232812Sjmallett uint64_t max_pkt : 3; /**< Maximum number of Packet-Pointers that COULD be 1699232812Sjmallett in the FIFO. */ 1700232812Sjmallett uint64_t praddr : 3; /**< Present Packet-Pointer read address. */ 1701232812Sjmallett uint64_t cena : 1; /**< Active low Chip Enable that controls the 1702232812Sjmallett MUX-select that steers [RADDR] to the fifo. 1703232812Sjmallett *WARNING - Setting this field to '0' will allow 1704232812Sjmallett reading of the memories thorugh the PTR field, 1705232812Sjmallett but will cause unpredictable operation of the IPD 1706232812Sjmallett under normal operation. */ 1707232812Sjmallett uint64_t raddr : 3; /**< Sets the address to read from in the holding. 1708232812Sjmallett fifo in the IPD. This FIFO holds Packet-Pointers 1709232812Sjmallett to be used for packet data storage. */ 1710232812Sjmallett#else 1711232812Sjmallett uint64_t raddr : 3; 1712232812Sjmallett uint64_t cena : 1; 1713232812Sjmallett uint64_t praddr : 3; 1714232812Sjmallett uint64_t max_pkt : 3; 1715232812Sjmallett uint64_t ptr : 33; 1716232812Sjmallett uint64_t reserved_43_63 : 21; 1717232812Sjmallett#endif 1718232812Sjmallett } s; 1719232812Sjmallett struct cvmx_ipd_hold_ptr_fifo_ctl_s cn68xx; 1720232812Sjmallett struct cvmx_ipd_hold_ptr_fifo_ctl_s cn68xxp1; 1721232812Sjmallett}; 1722232812Sjmalletttypedef union cvmx_ipd_hold_ptr_fifo_ctl cvmx_ipd_hold_ptr_fifo_ctl_t; 1723232812Sjmallett 1724232812Sjmallett/** 1725215976Sjmallett * cvmx_ipd_int_enb 1726215976Sjmallett * 1727215976Sjmallett * IPD_INTERRUPT_ENB = IPD Interrupt Enable Register 1728215976Sjmallett * 1729215976Sjmallett * Used to enable the various interrupting conditions of IPD 1730215976Sjmallett */ 1731232812Sjmallettunion cvmx_ipd_int_enb { 1732215976Sjmallett uint64_t u64; 1733232812Sjmallett struct cvmx_ipd_int_enb_s { 1734232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1735232812Sjmallett uint64_t reserved_23_63 : 41; 1736232812Sjmallett uint64_t pw3_dbe : 1; /**< Allows an interrupt to be sent when the 1737232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1738232812Sjmallett uint64_t pw3_sbe : 1; /**< Allows an interrupt to be sent when the 1739232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1740232812Sjmallett uint64_t pw2_dbe : 1; /**< Allows an interrupt to be sent when the 1741232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1742232812Sjmallett uint64_t pw2_sbe : 1; /**< Allows an interrupt to be sent when the 1743232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1744232812Sjmallett uint64_t pw1_dbe : 1; /**< Allows an interrupt to be sent when the 1745232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1746232812Sjmallett uint64_t pw1_sbe : 1; /**< Allows an interrupt to be sent when the 1747232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1748232812Sjmallett uint64_t pw0_dbe : 1; /**< Allows an interrupt to be sent when the 1749232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1750232812Sjmallett uint64_t pw0_sbe : 1; /**< Allows an interrupt to be sent when the 1751232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1752232812Sjmallett uint64_t dat : 1; /**< Allows an interrupt to be sent when the 1753232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1754232812Sjmallett uint64_t eop : 1; /**< Allows an interrupt to be sent when the 1755232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1756232812Sjmallett uint64_t sop : 1; /**< Allows an interrupt to be sent when the 1757232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1758215976Sjmallett uint64_t pq_sub : 1; /**< Allows an interrupt to be sent when the 1759215976Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1760215976Sjmallett uint64_t pq_add : 1; /**< Allows an interrupt to be sent when the 1761215976Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1762215976Sjmallett uint64_t bc_ovr : 1; /**< Allows an interrupt to be sent when the 1763215976Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1764215976Sjmallett uint64_t d_coll : 1; /**< Allows an interrupt to be sent when the 1765215976Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1766215976Sjmallett uint64_t c_coll : 1; /**< Allows an interrupt to be sent when the 1767215976Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1768215976Sjmallett uint64_t cc_ovr : 1; /**< Allows an interrupt to be sent when the 1769215976Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1770215976Sjmallett uint64_t dc_ovr : 1; /**< Allows an interrupt to be sent when the 1771215976Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1772215976Sjmallett uint64_t bp_sub : 1; /**< Enables interrupts when a backpressure subtract 1773215976Sjmallett has an illegal value. */ 1774215976Sjmallett uint64_t prc_par3 : 1; /**< Enable parity error interrupts for bits 1775215976Sjmallett [127:96] of the PBM memory. */ 1776215976Sjmallett uint64_t prc_par2 : 1; /**< Enable parity error interrupts for bits 1777215976Sjmallett [95:64] of the PBM memory. */ 1778215976Sjmallett uint64_t prc_par1 : 1; /**< Enable parity error interrupts for bits 1779215976Sjmallett [63:32] of the PBM memory. */ 1780215976Sjmallett uint64_t prc_par0 : 1; /**< Enable parity error interrupts for bits 1781215976Sjmallett [31:0] of the PBM memory. */ 1782215976Sjmallett#else 1783215976Sjmallett uint64_t prc_par0 : 1; 1784215976Sjmallett uint64_t prc_par1 : 1; 1785215976Sjmallett uint64_t prc_par2 : 1; 1786215976Sjmallett uint64_t prc_par3 : 1; 1787215976Sjmallett uint64_t bp_sub : 1; 1788215976Sjmallett uint64_t dc_ovr : 1; 1789215976Sjmallett uint64_t cc_ovr : 1; 1790215976Sjmallett uint64_t c_coll : 1; 1791215976Sjmallett uint64_t d_coll : 1; 1792215976Sjmallett uint64_t bc_ovr : 1; 1793215976Sjmallett uint64_t pq_add : 1; 1794215976Sjmallett uint64_t pq_sub : 1; 1795232812Sjmallett uint64_t sop : 1; 1796232812Sjmallett uint64_t eop : 1; 1797232812Sjmallett uint64_t dat : 1; 1798232812Sjmallett uint64_t pw0_sbe : 1; 1799232812Sjmallett uint64_t pw0_dbe : 1; 1800232812Sjmallett uint64_t pw1_sbe : 1; 1801232812Sjmallett uint64_t pw1_dbe : 1; 1802232812Sjmallett uint64_t pw2_sbe : 1; 1803232812Sjmallett uint64_t pw2_dbe : 1; 1804232812Sjmallett uint64_t pw3_sbe : 1; 1805232812Sjmallett uint64_t pw3_dbe : 1; 1806232812Sjmallett uint64_t reserved_23_63 : 41; 1807215976Sjmallett#endif 1808215976Sjmallett } s; 1809232812Sjmallett struct cvmx_ipd_int_enb_cn30xx { 1810232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1811215976Sjmallett uint64_t reserved_5_63 : 59; 1812215976Sjmallett uint64_t bp_sub : 1; /**< Enables interrupts when a backpressure subtract 1813215976Sjmallett has an illegal value. */ 1814215976Sjmallett uint64_t prc_par3 : 1; /**< Enable parity error interrupts for bits 1815215976Sjmallett [127:96] of the PBM memory. */ 1816215976Sjmallett uint64_t prc_par2 : 1; /**< Enable parity error interrupts for bits 1817215976Sjmallett [95:64] of the PBM memory. */ 1818215976Sjmallett uint64_t prc_par1 : 1; /**< Enable parity error interrupts for bits 1819215976Sjmallett [63:32] of the PBM memory. */ 1820215976Sjmallett uint64_t prc_par0 : 1; /**< Enable parity error interrupts for bits 1821215976Sjmallett [31:0] of the PBM memory. */ 1822215976Sjmallett#else 1823215976Sjmallett uint64_t prc_par0 : 1; 1824215976Sjmallett uint64_t prc_par1 : 1; 1825215976Sjmallett uint64_t prc_par2 : 1; 1826215976Sjmallett uint64_t prc_par3 : 1; 1827215976Sjmallett uint64_t bp_sub : 1; 1828215976Sjmallett uint64_t reserved_5_63 : 59; 1829215976Sjmallett#endif 1830215976Sjmallett } cn30xx; 1831215976Sjmallett struct cvmx_ipd_int_enb_cn30xx cn31xx; 1832232812Sjmallett struct cvmx_ipd_int_enb_cn38xx { 1833232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1834215976Sjmallett uint64_t reserved_10_63 : 54; 1835215976Sjmallett uint64_t bc_ovr : 1; /**< Allows an interrupt to be sent when the 1836215976Sjmallett corresponding bit in the IPD_INT_SUM is set. 1837215976Sjmallett This is a PASS-3 Field. */ 1838215976Sjmallett uint64_t d_coll : 1; /**< Allows an interrupt to be sent when the 1839215976Sjmallett corresponding bit in the IPD_INT_SUM is set. 1840215976Sjmallett This is a PASS-3 Field. */ 1841215976Sjmallett uint64_t c_coll : 1; /**< Allows an interrupt to be sent when the 1842215976Sjmallett corresponding bit in the IPD_INT_SUM is set. 1843215976Sjmallett This is a PASS-3 Field. */ 1844215976Sjmallett uint64_t cc_ovr : 1; /**< Allows an interrupt to be sent when the 1845215976Sjmallett corresponding bit in the IPD_INT_SUM is set. 1846215976Sjmallett This is a PASS-3 Field. */ 1847215976Sjmallett uint64_t dc_ovr : 1; /**< Allows an interrupt to be sent when the 1848215976Sjmallett corresponding bit in the IPD_INT_SUM is set. 1849215976Sjmallett This is a PASS-3 Field. */ 1850215976Sjmallett uint64_t bp_sub : 1; /**< Enables interrupts when a backpressure subtract 1851215976Sjmallett has an illegal value. */ 1852215976Sjmallett uint64_t prc_par3 : 1; /**< Enable parity error interrupts for bits 1853215976Sjmallett [127:96] of the PBM memory. */ 1854215976Sjmallett uint64_t prc_par2 : 1; /**< Enable parity error interrupts for bits 1855215976Sjmallett [95:64] of the PBM memory. */ 1856215976Sjmallett uint64_t prc_par1 : 1; /**< Enable parity error interrupts for bits 1857215976Sjmallett [63:32] of the PBM memory. */ 1858215976Sjmallett uint64_t prc_par0 : 1; /**< Enable parity error interrupts for bits 1859215976Sjmallett [31:0] of the PBM memory. */ 1860215976Sjmallett#else 1861215976Sjmallett uint64_t prc_par0 : 1; 1862215976Sjmallett uint64_t prc_par1 : 1; 1863215976Sjmallett uint64_t prc_par2 : 1; 1864215976Sjmallett uint64_t prc_par3 : 1; 1865215976Sjmallett uint64_t bp_sub : 1; 1866215976Sjmallett uint64_t dc_ovr : 1; 1867215976Sjmallett uint64_t cc_ovr : 1; 1868215976Sjmallett uint64_t c_coll : 1; 1869215976Sjmallett uint64_t d_coll : 1; 1870215976Sjmallett uint64_t bc_ovr : 1; 1871215976Sjmallett uint64_t reserved_10_63 : 54; 1872215976Sjmallett#endif 1873215976Sjmallett } cn38xx; 1874215976Sjmallett struct cvmx_ipd_int_enb_cn30xx cn38xxp2; 1875215976Sjmallett struct cvmx_ipd_int_enb_cn38xx cn50xx; 1876232812Sjmallett struct cvmx_ipd_int_enb_cn52xx { 1877232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1878232812Sjmallett uint64_t reserved_12_63 : 52; 1879232812Sjmallett uint64_t pq_sub : 1; /**< Allows an interrupt to be sent when the 1880232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1881232812Sjmallett uint64_t pq_add : 1; /**< Allows an interrupt to be sent when the 1882232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1883232812Sjmallett uint64_t bc_ovr : 1; /**< Allows an interrupt to be sent when the 1884232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1885232812Sjmallett uint64_t d_coll : 1; /**< Allows an interrupt to be sent when the 1886232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1887232812Sjmallett uint64_t c_coll : 1; /**< Allows an interrupt to be sent when the 1888232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1889232812Sjmallett uint64_t cc_ovr : 1; /**< Allows an interrupt to be sent when the 1890232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1891232812Sjmallett uint64_t dc_ovr : 1; /**< Allows an interrupt to be sent when the 1892232812Sjmallett corresponding bit in the IPD_INT_SUM is set. */ 1893232812Sjmallett uint64_t bp_sub : 1; /**< Enables interrupts when a backpressure subtract 1894232812Sjmallett has an illegal value. */ 1895232812Sjmallett uint64_t prc_par3 : 1; /**< Enable parity error interrupts for bits 1896232812Sjmallett [127:96] of the PBM memory. */ 1897232812Sjmallett uint64_t prc_par2 : 1; /**< Enable parity error interrupts for bits 1898232812Sjmallett [95:64] of the PBM memory. */ 1899232812Sjmallett uint64_t prc_par1 : 1; /**< Enable parity error interrupts for bits 1900232812Sjmallett [63:32] of the PBM memory. */ 1901232812Sjmallett uint64_t prc_par0 : 1; /**< Enable parity error interrupts for bits 1902232812Sjmallett [31:0] of the PBM memory. */ 1903232812Sjmallett#else 1904232812Sjmallett uint64_t prc_par0 : 1; 1905232812Sjmallett uint64_t prc_par1 : 1; 1906232812Sjmallett uint64_t prc_par2 : 1; 1907232812Sjmallett uint64_t prc_par3 : 1; 1908232812Sjmallett uint64_t bp_sub : 1; 1909232812Sjmallett uint64_t dc_ovr : 1; 1910232812Sjmallett uint64_t cc_ovr : 1; 1911232812Sjmallett uint64_t c_coll : 1; 1912232812Sjmallett uint64_t d_coll : 1; 1913232812Sjmallett uint64_t bc_ovr : 1; 1914232812Sjmallett uint64_t pq_add : 1; 1915232812Sjmallett uint64_t pq_sub : 1; 1916232812Sjmallett uint64_t reserved_12_63 : 52; 1917232812Sjmallett#endif 1918232812Sjmallett } cn52xx; 1919232812Sjmallett struct cvmx_ipd_int_enb_cn52xx cn52xxp1; 1920232812Sjmallett struct cvmx_ipd_int_enb_cn52xx cn56xx; 1921232812Sjmallett struct cvmx_ipd_int_enb_cn52xx cn56xxp1; 1922215976Sjmallett struct cvmx_ipd_int_enb_cn38xx cn58xx; 1923215976Sjmallett struct cvmx_ipd_int_enb_cn38xx cn58xxp1; 1924232812Sjmallett struct cvmx_ipd_int_enb_cn52xx cn61xx; 1925232812Sjmallett struct cvmx_ipd_int_enb_cn52xx cn63xx; 1926232812Sjmallett struct cvmx_ipd_int_enb_cn52xx cn63xxp1; 1927232812Sjmallett struct cvmx_ipd_int_enb_cn52xx cn66xx; 1928232812Sjmallett struct cvmx_ipd_int_enb_s cn68xx; 1929232812Sjmallett struct cvmx_ipd_int_enb_s cn68xxp1; 1930232812Sjmallett struct cvmx_ipd_int_enb_cn52xx cnf71xx; 1931215976Sjmallett}; 1932215976Sjmalletttypedef union cvmx_ipd_int_enb cvmx_ipd_int_enb_t; 1933215976Sjmallett 1934215976Sjmallett/** 1935215976Sjmallett * cvmx_ipd_int_sum 1936215976Sjmallett * 1937215976Sjmallett * IPD_INTERRUPT_SUM = IPD Interrupt Summary Register 1938215976Sjmallett * 1939215976Sjmallett * Set when an interrupt condition occurs, write '1' to clear. 1940215976Sjmallett */ 1941232812Sjmallettunion cvmx_ipd_int_sum { 1942215976Sjmallett uint64_t u64; 1943232812Sjmallett struct cvmx_ipd_int_sum_s { 1944232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1945232812Sjmallett uint64_t reserved_23_63 : 41; 1946232812Sjmallett uint64_t pw3_dbe : 1; /**< Packet memory 3 had ECC DBE. */ 1947232812Sjmallett uint64_t pw3_sbe : 1; /**< Packet memory 3 had ECC SBE. */ 1948232812Sjmallett uint64_t pw2_dbe : 1; /**< Packet memory 2 had ECC DBE. */ 1949232812Sjmallett uint64_t pw2_sbe : 1; /**< Packet memory 2 had ECC SBE. */ 1950232812Sjmallett uint64_t pw1_dbe : 1; /**< Packet memory 1 had ECC DBE. */ 1951232812Sjmallett uint64_t pw1_sbe : 1; /**< Packet memory 1 had ECC SBE. */ 1952232812Sjmallett uint64_t pw0_dbe : 1; /**< Packet memory 0 had ECC DBE. */ 1953232812Sjmallett uint64_t pw0_sbe : 1; /**< Packet memory 0 had ECC SBE. */ 1954232812Sjmallett uint64_t dat : 1; /**< Set when a data arrives before a SOP for the same 1955232812Sjmallett reasm-id for a packet. 1956232812Sjmallett The first detected error associated with bits [14:12] 1957232812Sjmallett of this register will only be set here. A new bit 1958232812Sjmallett can be set when the previous reported bit is cleared. 1959232812Sjmallett Also see IPD_PKT_ERR. */ 1960232812Sjmallett uint64_t eop : 1; /**< Set when a EOP is followed by an EOP for the same 1961232812Sjmallett reasm-id for a packet. 1962232812Sjmallett The first detected error associated with bits [14:12] 1963232812Sjmallett of this register will only be set here. A new bit 1964232812Sjmallett can be set when the previous reported bit is cleared. 1965232812Sjmallett Also see IPD_PKT_ERR. */ 1966232812Sjmallett uint64_t sop : 1; /**< Set when a SOP is followed by an SOP for the same 1967232812Sjmallett reasm-id for a packet. 1968232812Sjmallett The first detected error associated with bits [14:12] 1969232812Sjmallett of this register will only be set here. A new bit 1970232812Sjmallett can be set when the previous reported bit is cleared. 1971232812Sjmallett Also see IPD_PKT_ERR. */ 1972215976Sjmallett uint64_t pq_sub : 1; /**< Set when a port-qos does an sub to the count 1973215976Sjmallett that causes the counter to wrap. */ 1974215976Sjmallett uint64_t pq_add : 1; /**< Set when a port-qos does an add to the count 1975215976Sjmallett that causes the counter to wrap. */ 1976215976Sjmallett uint64_t bc_ovr : 1; /**< Set when the byte-count to send to IOB overflows. */ 1977215976Sjmallett uint64_t d_coll : 1; /**< Set when the packet/WQE data to be sent to IOB 1978215976Sjmallett collides. */ 1979215976Sjmallett uint64_t c_coll : 1; /**< Set when the packet/WQE commands to be sent to IOB 1980215976Sjmallett collides. */ 1981215976Sjmallett uint64_t cc_ovr : 1; /**< Set when the command credits to the IOB overflow. */ 1982215976Sjmallett uint64_t dc_ovr : 1; /**< Set when the data credits to the IOB overflow. */ 1983215976Sjmallett uint64_t bp_sub : 1; /**< Set when a backpressure subtract is done with a 1984215976Sjmallett supplied illegal value. */ 1985215976Sjmallett uint64_t prc_par3 : 1; /**< Set when a parity error is dected for bits 1986215976Sjmallett [127:96] of the PBM memory. */ 1987215976Sjmallett uint64_t prc_par2 : 1; /**< Set when a parity error is dected for bits 1988215976Sjmallett [95:64] of the PBM memory. */ 1989215976Sjmallett uint64_t prc_par1 : 1; /**< Set when a parity error is dected for bits 1990215976Sjmallett [63:32] of the PBM memory. */ 1991215976Sjmallett uint64_t prc_par0 : 1; /**< Set when a parity error is dected for bits 1992215976Sjmallett [31:0] of the PBM memory. */ 1993215976Sjmallett#else 1994215976Sjmallett uint64_t prc_par0 : 1; 1995215976Sjmallett uint64_t prc_par1 : 1; 1996215976Sjmallett uint64_t prc_par2 : 1; 1997215976Sjmallett uint64_t prc_par3 : 1; 1998215976Sjmallett uint64_t bp_sub : 1; 1999215976Sjmallett uint64_t dc_ovr : 1; 2000215976Sjmallett uint64_t cc_ovr : 1; 2001215976Sjmallett uint64_t c_coll : 1; 2002215976Sjmallett uint64_t d_coll : 1; 2003215976Sjmallett uint64_t bc_ovr : 1; 2004215976Sjmallett uint64_t pq_add : 1; 2005215976Sjmallett uint64_t pq_sub : 1; 2006232812Sjmallett uint64_t sop : 1; 2007232812Sjmallett uint64_t eop : 1; 2008232812Sjmallett uint64_t dat : 1; 2009232812Sjmallett uint64_t pw0_sbe : 1; 2010232812Sjmallett uint64_t pw0_dbe : 1; 2011232812Sjmallett uint64_t pw1_sbe : 1; 2012232812Sjmallett uint64_t pw1_dbe : 1; 2013232812Sjmallett uint64_t pw2_sbe : 1; 2014232812Sjmallett uint64_t pw2_dbe : 1; 2015232812Sjmallett uint64_t pw3_sbe : 1; 2016232812Sjmallett uint64_t pw3_dbe : 1; 2017232812Sjmallett uint64_t reserved_23_63 : 41; 2018215976Sjmallett#endif 2019215976Sjmallett } s; 2020232812Sjmallett struct cvmx_ipd_int_sum_cn30xx { 2021232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2022215976Sjmallett uint64_t reserved_5_63 : 59; 2023215976Sjmallett uint64_t bp_sub : 1; /**< Set when a backpressure subtract is done with a 2024215976Sjmallett supplied illegal value. */ 2025215976Sjmallett uint64_t prc_par3 : 1; /**< Set when a parity error is dected for bits 2026215976Sjmallett [127:96] of the PBM memory. */ 2027215976Sjmallett uint64_t prc_par2 : 1; /**< Set when a parity error is dected for bits 2028215976Sjmallett [95:64] of the PBM memory. */ 2029215976Sjmallett uint64_t prc_par1 : 1; /**< Set when a parity error is dected for bits 2030215976Sjmallett [63:32] of the PBM memory. */ 2031215976Sjmallett uint64_t prc_par0 : 1; /**< Set when a parity error is dected for bits 2032215976Sjmallett [31:0] of the PBM memory. */ 2033215976Sjmallett#else 2034215976Sjmallett uint64_t prc_par0 : 1; 2035215976Sjmallett uint64_t prc_par1 : 1; 2036215976Sjmallett uint64_t prc_par2 : 1; 2037215976Sjmallett uint64_t prc_par3 : 1; 2038215976Sjmallett uint64_t bp_sub : 1; 2039215976Sjmallett uint64_t reserved_5_63 : 59; 2040215976Sjmallett#endif 2041215976Sjmallett } cn30xx; 2042215976Sjmallett struct cvmx_ipd_int_sum_cn30xx cn31xx; 2043232812Sjmallett struct cvmx_ipd_int_sum_cn38xx { 2044232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2045215976Sjmallett uint64_t reserved_10_63 : 54; 2046215976Sjmallett uint64_t bc_ovr : 1; /**< Set when the byte-count to send to IOB overflows. 2047215976Sjmallett This is a PASS-3 Field. */ 2048215976Sjmallett uint64_t d_coll : 1; /**< Set when the packet/WQE data to be sent to IOB 2049215976Sjmallett collides. 2050215976Sjmallett This is a PASS-3 Field. */ 2051215976Sjmallett uint64_t c_coll : 1; /**< Set when the packet/WQE commands to be sent to IOB 2052215976Sjmallett collides. 2053215976Sjmallett This is a PASS-3 Field. */ 2054215976Sjmallett uint64_t cc_ovr : 1; /**< Set when the command credits to the IOB overflow. 2055215976Sjmallett This is a PASS-3 Field. */ 2056215976Sjmallett uint64_t dc_ovr : 1; /**< Set when the data credits to the IOB overflow. 2057215976Sjmallett This is a PASS-3 Field. */ 2058215976Sjmallett uint64_t bp_sub : 1; /**< Set when a backpressure subtract is done with a 2059215976Sjmallett supplied illegal value. */ 2060215976Sjmallett uint64_t prc_par3 : 1; /**< Set when a parity error is dected for bits 2061215976Sjmallett [127:96] of the PBM memory. */ 2062215976Sjmallett uint64_t prc_par2 : 1; /**< Set when a parity error is dected for bits 2063215976Sjmallett [95:64] of the PBM memory. */ 2064215976Sjmallett uint64_t prc_par1 : 1; /**< Set when a parity error is dected for bits 2065215976Sjmallett [63:32] of the PBM memory. */ 2066215976Sjmallett uint64_t prc_par0 : 1; /**< Set when a parity error is dected for bits 2067215976Sjmallett [31:0] of the PBM memory. */ 2068215976Sjmallett#else 2069215976Sjmallett uint64_t prc_par0 : 1; 2070215976Sjmallett uint64_t prc_par1 : 1; 2071215976Sjmallett uint64_t prc_par2 : 1; 2072215976Sjmallett uint64_t prc_par3 : 1; 2073215976Sjmallett uint64_t bp_sub : 1; 2074215976Sjmallett uint64_t dc_ovr : 1; 2075215976Sjmallett uint64_t cc_ovr : 1; 2076215976Sjmallett uint64_t c_coll : 1; 2077215976Sjmallett uint64_t d_coll : 1; 2078215976Sjmallett uint64_t bc_ovr : 1; 2079215976Sjmallett uint64_t reserved_10_63 : 54; 2080215976Sjmallett#endif 2081215976Sjmallett } cn38xx; 2082215976Sjmallett struct cvmx_ipd_int_sum_cn30xx cn38xxp2; 2083215976Sjmallett struct cvmx_ipd_int_sum_cn38xx cn50xx; 2084232812Sjmallett struct cvmx_ipd_int_sum_cn52xx { 2085232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2086232812Sjmallett uint64_t reserved_12_63 : 52; 2087232812Sjmallett uint64_t pq_sub : 1; /**< Set when a port-qos does an sub to the count 2088232812Sjmallett that causes the counter to wrap. */ 2089232812Sjmallett uint64_t pq_add : 1; /**< Set when a port-qos does an add to the count 2090232812Sjmallett that causes the counter to wrap. */ 2091232812Sjmallett uint64_t bc_ovr : 1; /**< Set when the byte-count to send to IOB overflows. */ 2092232812Sjmallett uint64_t d_coll : 1; /**< Set when the packet/WQE data to be sent to IOB 2093232812Sjmallett collides. */ 2094232812Sjmallett uint64_t c_coll : 1; /**< Set when the packet/WQE commands to be sent to IOB 2095232812Sjmallett collides. */ 2096232812Sjmallett uint64_t cc_ovr : 1; /**< Set when the command credits to the IOB overflow. */ 2097232812Sjmallett uint64_t dc_ovr : 1; /**< Set when the data credits to the IOB overflow. */ 2098232812Sjmallett uint64_t bp_sub : 1; /**< Set when a backpressure subtract is done with a 2099232812Sjmallett supplied illegal value. */ 2100232812Sjmallett uint64_t prc_par3 : 1; /**< Set when a parity error is dected for bits 2101232812Sjmallett [127:96] of the PBM memory. */ 2102232812Sjmallett uint64_t prc_par2 : 1; /**< Set when a parity error is dected for bits 2103232812Sjmallett [95:64] of the PBM memory. */ 2104232812Sjmallett uint64_t prc_par1 : 1; /**< Set when a parity error is dected for bits 2105232812Sjmallett [63:32] of the PBM memory. */ 2106232812Sjmallett uint64_t prc_par0 : 1; /**< Set when a parity error is dected for bits 2107232812Sjmallett [31:0] of the PBM memory. */ 2108232812Sjmallett#else 2109232812Sjmallett uint64_t prc_par0 : 1; 2110232812Sjmallett uint64_t prc_par1 : 1; 2111232812Sjmallett uint64_t prc_par2 : 1; 2112232812Sjmallett uint64_t prc_par3 : 1; 2113232812Sjmallett uint64_t bp_sub : 1; 2114232812Sjmallett uint64_t dc_ovr : 1; 2115232812Sjmallett uint64_t cc_ovr : 1; 2116232812Sjmallett uint64_t c_coll : 1; 2117232812Sjmallett uint64_t d_coll : 1; 2118232812Sjmallett uint64_t bc_ovr : 1; 2119232812Sjmallett uint64_t pq_add : 1; 2120232812Sjmallett uint64_t pq_sub : 1; 2121232812Sjmallett uint64_t reserved_12_63 : 52; 2122232812Sjmallett#endif 2123232812Sjmallett } cn52xx; 2124232812Sjmallett struct cvmx_ipd_int_sum_cn52xx cn52xxp1; 2125232812Sjmallett struct cvmx_ipd_int_sum_cn52xx cn56xx; 2126232812Sjmallett struct cvmx_ipd_int_sum_cn52xx cn56xxp1; 2127215976Sjmallett struct cvmx_ipd_int_sum_cn38xx cn58xx; 2128215976Sjmallett struct cvmx_ipd_int_sum_cn38xx cn58xxp1; 2129232812Sjmallett struct cvmx_ipd_int_sum_cn52xx cn61xx; 2130232812Sjmallett struct cvmx_ipd_int_sum_cn52xx cn63xx; 2131232812Sjmallett struct cvmx_ipd_int_sum_cn52xx cn63xxp1; 2132232812Sjmallett struct cvmx_ipd_int_sum_cn52xx cn66xx; 2133232812Sjmallett struct cvmx_ipd_int_sum_s cn68xx; 2134232812Sjmallett struct cvmx_ipd_int_sum_s cn68xxp1; 2135232812Sjmallett struct cvmx_ipd_int_sum_cn52xx cnf71xx; 2136215976Sjmallett}; 2137215976Sjmalletttypedef union cvmx_ipd_int_sum cvmx_ipd_int_sum_t; 2138215976Sjmallett 2139215976Sjmallett/** 2140232812Sjmallett * cvmx_ipd_next_pkt_ptr 2141232812Sjmallett * 2142232812Sjmallett * IPD_NEXT_PKT_PTR = IPD's Next Packet Pointer 2143232812Sjmallett * 2144232812Sjmallett * The value of the packet-pointer fetched and in the valid register. 2145232812Sjmallett */ 2146232812Sjmallettunion cvmx_ipd_next_pkt_ptr { 2147232812Sjmallett uint64_t u64; 2148232812Sjmallett struct cvmx_ipd_next_pkt_ptr_s { 2149232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2150232812Sjmallett uint64_t reserved_33_63 : 31; 2151232812Sjmallett uint64_t ptr : 33; /**< Pointer value. */ 2152232812Sjmallett#else 2153232812Sjmallett uint64_t ptr : 33; 2154232812Sjmallett uint64_t reserved_33_63 : 31; 2155232812Sjmallett#endif 2156232812Sjmallett } s; 2157232812Sjmallett struct cvmx_ipd_next_pkt_ptr_s cn68xx; 2158232812Sjmallett struct cvmx_ipd_next_pkt_ptr_s cn68xxp1; 2159232812Sjmallett}; 2160232812Sjmalletttypedef union cvmx_ipd_next_pkt_ptr cvmx_ipd_next_pkt_ptr_t; 2161232812Sjmallett 2162232812Sjmallett/** 2163232812Sjmallett * cvmx_ipd_next_wqe_ptr 2164232812Sjmallett * 2165232812Sjmallett * IPD_NEXT_WQE_PTR = IPD's NEXT_WQE Pointer 2166232812Sjmallett * 2167232812Sjmallett * The value of the WQE-pointer fetched and in the valid register. 2168232812Sjmallett */ 2169232812Sjmallettunion cvmx_ipd_next_wqe_ptr { 2170232812Sjmallett uint64_t u64; 2171232812Sjmallett struct cvmx_ipd_next_wqe_ptr_s { 2172232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2173232812Sjmallett uint64_t reserved_33_63 : 31; 2174232812Sjmallett uint64_t ptr : 33; /**< Pointer value. 2175232812Sjmallett When IPD_CTL_STATUS[NO_WPTR] is set '1' this field 2176232812Sjmallett represents a Packet-Pointer NOT a WQE pointer. */ 2177232812Sjmallett#else 2178232812Sjmallett uint64_t ptr : 33; 2179232812Sjmallett uint64_t reserved_33_63 : 31; 2180232812Sjmallett#endif 2181232812Sjmallett } s; 2182232812Sjmallett struct cvmx_ipd_next_wqe_ptr_s cn68xx; 2183232812Sjmallett struct cvmx_ipd_next_wqe_ptr_s cn68xxp1; 2184232812Sjmallett}; 2185232812Sjmalletttypedef union cvmx_ipd_next_wqe_ptr cvmx_ipd_next_wqe_ptr_t; 2186232812Sjmallett 2187232812Sjmallett/** 2188215976Sjmallett * cvmx_ipd_not_1st_mbuff_skip 2189215976Sjmallett * 2190215976Sjmallett * IPD_NOT_1ST_MBUFF_SKIP = IPD Not First MBUFF Word Skip Size 2191215976Sjmallett * 2192215976Sjmallett * The number of words that the IPD will skip when writing any MBUFF that is not the first. 2193215976Sjmallett */ 2194232812Sjmallettunion cvmx_ipd_not_1st_mbuff_skip { 2195215976Sjmallett uint64_t u64; 2196232812Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s { 2197232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2198215976Sjmallett uint64_t reserved_6_63 : 58; 2199215976Sjmallett uint64_t skip_sz : 6; /**< The number of 8-byte words from the top of any 2200215976Sjmallett MBUFF, that is not the 1st MBUFF, that the IPD 2201215976Sjmallett will write the next-pointer. 2202215976Sjmallett Legal values are 0 to 32, where the MAX value 2203215976Sjmallett is also limited to: 2204215976Sjmallett IPD_PACKET_MBUFF_SIZE[MB_SIZE] - 16. */ 2205215976Sjmallett#else 2206215976Sjmallett uint64_t skip_sz : 6; 2207215976Sjmallett uint64_t reserved_6_63 : 58; 2208215976Sjmallett#endif 2209215976Sjmallett } s; 2210215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn30xx; 2211215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn31xx; 2212215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn38xx; 2213215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn38xxp2; 2214215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn50xx; 2215215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn52xx; 2216215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn52xxp1; 2217215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn56xx; 2218215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1; 2219215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx; 2220215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1; 2221232812Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn61xx; 2222215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn63xx; 2223215976Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn63xxp1; 2224232812Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn66xx; 2225232812Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn68xx; 2226232812Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cn68xxp1; 2227232812Sjmallett struct cvmx_ipd_not_1st_mbuff_skip_s cnf71xx; 2228215976Sjmallett}; 2229215976Sjmalletttypedef union cvmx_ipd_not_1st_mbuff_skip cvmx_ipd_not_1st_mbuff_skip_t; 2230215976Sjmallett 2231215976Sjmallett/** 2232232812Sjmallett * cvmx_ipd_on_bp_drop_pkt# 2233232812Sjmallett * 2234232812Sjmallett * RESERVE SPACE UPTO 0x3FFF 2235232812Sjmallett * 2236232812Sjmallett * 2237232812Sjmallett * RESERVED FOR FORMER IPD_SUB_PKIND_FCS - MOVED TO PIP 2238232812Sjmallett * 2239232812Sjmallett * RESERVE 4008 - 40FF 2240232812Sjmallett * 2241232812Sjmallett * 2242232812Sjmallett * IPD_ON_BP_DROP_PKT = IPD On Backpressure Drop Packet 2243232812Sjmallett * 2244232812Sjmallett * When IPD applies backpressure to a BPID and the corresponding bit in this register is set, 2245232812Sjmallett * then previously received packets will be dropped when processed. 2246232812Sjmallett */ 2247232812Sjmallettunion cvmx_ipd_on_bp_drop_pktx { 2248232812Sjmallett uint64_t u64; 2249232812Sjmallett struct cvmx_ipd_on_bp_drop_pktx_s { 2250232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2251232812Sjmallett uint64_t prt_enb : 64; /**< The BPID corresponding to the bit position in this 2252232812Sjmallett field will drop all NON-RAW packets to that BPID 2253232812Sjmallett when BPID level backpressure is applied to that 2254232812Sjmallett BPID. The applying of BPID-level backpressure for 2255232812Sjmallett this dropping does not take into consideration the 2256232812Sjmallett value of IPD_BPIDX_MBUF_TH[BP_ENB], nor 2257232812Sjmallett IPD_RED_BPID_ENABLE[PRT_ENB]. */ 2258232812Sjmallett#else 2259232812Sjmallett uint64_t prt_enb : 64; 2260232812Sjmallett#endif 2261232812Sjmallett } s; 2262232812Sjmallett struct cvmx_ipd_on_bp_drop_pktx_s cn68xx; 2263232812Sjmallett struct cvmx_ipd_on_bp_drop_pktx_s cn68xxp1; 2264232812Sjmallett}; 2265232812Sjmalletttypedef union cvmx_ipd_on_bp_drop_pktx cvmx_ipd_on_bp_drop_pktx_t; 2266232812Sjmallett 2267232812Sjmallett/** 2268215976Sjmallett * cvmx_ipd_packet_mbuff_size 2269215976Sjmallett * 2270215976Sjmallett * IPD_PACKET_MBUFF_SIZE = IPD's PACKET MUBUF Size In Words 2271215976Sjmallett * 2272215976Sjmallett * The number of words in a MBUFF used for packet data store. 2273215976Sjmallett */ 2274232812Sjmallettunion cvmx_ipd_packet_mbuff_size { 2275215976Sjmallett uint64_t u64; 2276232812Sjmallett struct cvmx_ipd_packet_mbuff_size_s { 2277232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2278215976Sjmallett uint64_t reserved_12_63 : 52; 2279215976Sjmallett uint64_t mb_size : 12; /**< The number of 8-byte words in a MBUF. 2280215976Sjmallett This must be a number in the range of 32 to 2281215976Sjmallett 2048. 2282215976Sjmallett This is also the size of the FPA's 2283215976Sjmallett Queue-0 Free-Page. */ 2284215976Sjmallett#else 2285215976Sjmallett uint64_t mb_size : 12; 2286215976Sjmallett uint64_t reserved_12_63 : 52; 2287215976Sjmallett#endif 2288215976Sjmallett } s; 2289215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn30xx; 2290215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn31xx; 2291215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn38xx; 2292215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn38xxp2; 2293215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn50xx; 2294215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn52xx; 2295215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn52xxp1; 2296215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn56xx; 2297215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn56xxp1; 2298215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn58xx; 2299215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn58xxp1; 2300232812Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn61xx; 2301215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn63xx; 2302215976Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn63xxp1; 2303232812Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn66xx; 2304232812Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn68xx; 2305232812Sjmallett struct cvmx_ipd_packet_mbuff_size_s cn68xxp1; 2306232812Sjmallett struct cvmx_ipd_packet_mbuff_size_s cnf71xx; 2307215976Sjmallett}; 2308215976Sjmalletttypedef union cvmx_ipd_packet_mbuff_size cvmx_ipd_packet_mbuff_size_t; 2309215976Sjmallett 2310215976Sjmallett/** 2311232812Sjmallett * cvmx_ipd_pkt_err 2312232812Sjmallett * 2313232812Sjmallett * IPD_PKT_ERR = IPD Packet Error Register 2314232812Sjmallett * 2315232812Sjmallett * Provides status about the failing packet recevie error. 2316232812Sjmallett */ 2317232812Sjmallettunion cvmx_ipd_pkt_err { 2318232812Sjmallett uint64_t u64; 2319232812Sjmallett struct cvmx_ipd_pkt_err_s { 2320232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2321232812Sjmallett uint64_t reserved_6_63 : 58; 2322232812Sjmallett uint64_t reasm : 6; /**< When IPD_INT_SUM[14:12] bit is set, this field 2323232812Sjmallett latches the failing reasm number associated with 2324232812Sjmallett the IPD_INT_SUM[14:12] bit set. 2325232812Sjmallett Values 0-62 can be seen here, reasm-id 63 is not 2326232812Sjmallett used. */ 2327232812Sjmallett#else 2328232812Sjmallett uint64_t reasm : 6; 2329232812Sjmallett uint64_t reserved_6_63 : 58; 2330232812Sjmallett#endif 2331232812Sjmallett } s; 2332232812Sjmallett struct cvmx_ipd_pkt_err_s cn68xx; 2333232812Sjmallett struct cvmx_ipd_pkt_err_s cn68xxp1; 2334232812Sjmallett}; 2335232812Sjmalletttypedef union cvmx_ipd_pkt_err cvmx_ipd_pkt_err_t; 2336232812Sjmallett 2337232812Sjmallett/** 2338215976Sjmallett * cvmx_ipd_pkt_ptr_valid 2339215976Sjmallett * 2340215976Sjmallett * IPD_PKT_PTR_VALID = IPD's Packet Pointer Valid 2341215976Sjmallett * 2342215976Sjmallett * The value of the packet-pointer fetched and in the valid register. 2343215976Sjmallett */ 2344232812Sjmallettunion cvmx_ipd_pkt_ptr_valid { 2345215976Sjmallett uint64_t u64; 2346232812Sjmallett struct cvmx_ipd_pkt_ptr_valid_s { 2347232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2348215976Sjmallett uint64_t reserved_29_63 : 35; 2349215976Sjmallett uint64_t ptr : 29; /**< Pointer value. */ 2350215976Sjmallett#else 2351215976Sjmallett uint64_t ptr : 29; 2352215976Sjmallett uint64_t reserved_29_63 : 35; 2353215976Sjmallett#endif 2354215976Sjmallett } s; 2355215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn30xx; 2356215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn31xx; 2357215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn38xx; 2358215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn50xx; 2359215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn52xx; 2360215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn52xxp1; 2361215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn56xx; 2362215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1; 2363215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn58xx; 2364215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1; 2365232812Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn61xx; 2366215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn63xx; 2367215976Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn63xxp1; 2368232812Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cn66xx; 2369232812Sjmallett struct cvmx_ipd_pkt_ptr_valid_s cnf71xx; 2370215976Sjmallett}; 2371215976Sjmalletttypedef union cvmx_ipd_pkt_ptr_valid cvmx_ipd_pkt_ptr_valid_t; 2372215976Sjmallett 2373215976Sjmallett/** 2374215976Sjmallett * cvmx_ipd_port#_bp_page_cnt 2375215976Sjmallett * 2376215976Sjmallett * IPD_PORTX_BP_PAGE_CNT = IPD Port Backpressure Page Count 2377215976Sjmallett * 2378215976Sjmallett * The number of pages in use by the port that when exceeded, backpressure will be applied to the port. 2379215976Sjmallett * See also IPD_PORTX_BP_PAGE_CNT2 2380215976Sjmallett * See also IPD_PORTX_BP_PAGE_CNT3 2381215976Sjmallett */ 2382232812Sjmallettunion cvmx_ipd_portx_bp_page_cnt { 2383215976Sjmallett uint64_t u64; 2384232812Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s { 2385232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2386215976Sjmallett uint64_t reserved_18_63 : 46; 2387215976Sjmallett uint64_t bp_enb : 1; /**< When set '1' BP will be applied, if '0' BP will 2388215976Sjmallett not be applied to port. */ 2389215976Sjmallett uint64_t page_cnt : 17; /**< The number of page pointers assigned to 2390215976Sjmallett the port, that when exceeded will cause 2391215976Sjmallett back-pressure to be applied to the port. 2392215976Sjmallett This value is in 256 page-pointer increments, 2393215976Sjmallett (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */ 2394215976Sjmallett#else 2395215976Sjmallett uint64_t page_cnt : 17; 2396215976Sjmallett uint64_t bp_enb : 1; 2397215976Sjmallett uint64_t reserved_18_63 : 46; 2398215976Sjmallett#endif 2399215976Sjmallett } s; 2400215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn30xx; 2401215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn31xx; 2402215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn38xx; 2403215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn38xxp2; 2404215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn50xx; 2405215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn52xx; 2406215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn52xxp1; 2407215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn56xx; 2408215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1; 2409215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn58xx; 2410215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1; 2411232812Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn61xx; 2412215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn63xx; 2413215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn63xxp1; 2414232812Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cn66xx; 2415232812Sjmallett struct cvmx_ipd_portx_bp_page_cnt_s cnf71xx; 2416215976Sjmallett}; 2417215976Sjmalletttypedef union cvmx_ipd_portx_bp_page_cnt cvmx_ipd_portx_bp_page_cnt_t; 2418215976Sjmallett 2419215976Sjmallett/** 2420215976Sjmallett * cvmx_ipd_port#_bp_page_cnt2 2421215976Sjmallett * 2422215976Sjmallett * IPD_PORTX_BP_PAGE_CNT2 = IPD Port Backpressure Page Count 2423215976Sjmallett * 2424215976Sjmallett * The number of pages in use by the port that when exceeded, backpressure will be applied to the port. 2425215976Sjmallett * See also IPD_PORTX_BP_PAGE_CNT 2426215976Sjmallett * See also IPD_PORTX_BP_PAGE_CNT3 2427232812Sjmallett * 0x368-0x380 2428215976Sjmallett */ 2429232812Sjmallettunion cvmx_ipd_portx_bp_page_cnt2 { 2430215976Sjmallett uint64_t u64; 2431232812Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s { 2432232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2433215976Sjmallett uint64_t reserved_18_63 : 46; 2434215976Sjmallett uint64_t bp_enb : 1; /**< When set '1' BP will be applied, if '0' BP will 2435215976Sjmallett not be applied to port. */ 2436215976Sjmallett uint64_t page_cnt : 17; /**< The number of page pointers assigned to 2437215976Sjmallett the port, that when exceeded will cause 2438215976Sjmallett back-pressure to be applied to the port. 2439215976Sjmallett This value is in 256 page-pointer increments, 2440215976Sjmallett (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */ 2441215976Sjmallett#else 2442215976Sjmallett uint64_t page_cnt : 17; 2443215976Sjmallett uint64_t bp_enb : 1; 2444215976Sjmallett uint64_t reserved_18_63 : 46; 2445215976Sjmallett#endif 2446215976Sjmallett } s; 2447215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s cn52xx; 2448215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1; 2449215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx; 2450215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1; 2451232812Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s cn61xx; 2452215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s cn63xx; 2453215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s cn63xxp1; 2454232812Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s cn66xx; 2455232812Sjmallett struct cvmx_ipd_portx_bp_page_cnt2_s cnf71xx; 2456215976Sjmallett}; 2457215976Sjmalletttypedef union cvmx_ipd_portx_bp_page_cnt2 cvmx_ipd_portx_bp_page_cnt2_t; 2458215976Sjmallett 2459215976Sjmallett/** 2460215976Sjmallett * cvmx_ipd_port#_bp_page_cnt3 2461215976Sjmallett * 2462215976Sjmallett * IPD_PORTX_BP_PAGE_CNT3 = IPD Port Backpressure Page Count 2463215976Sjmallett * 2464215976Sjmallett * The number of pages in use by the port that when exceeded, backpressure will be applied to the port. 2465215976Sjmallett * See also IPD_PORTX_BP_PAGE_CNT 2466215976Sjmallett * See also IPD_PORTX_BP_PAGE_CNT2 2467232812Sjmallett * 0x3d0-408 2468215976Sjmallett */ 2469232812Sjmallettunion cvmx_ipd_portx_bp_page_cnt3 { 2470215976Sjmallett uint64_t u64; 2471232812Sjmallett struct cvmx_ipd_portx_bp_page_cnt3_s { 2472232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2473215976Sjmallett uint64_t reserved_18_63 : 46; 2474215976Sjmallett uint64_t bp_enb : 1; /**< When set '1' BP will be applied, if '0' BP will 2475215976Sjmallett not be applied to port. */ 2476215976Sjmallett uint64_t page_cnt : 17; /**< The number of page pointers assigned to 2477215976Sjmallett the port, that when exceeded will cause 2478215976Sjmallett back-pressure to be applied to the port. 2479215976Sjmallett This value is in 256 page-pointer increments, 2480215976Sjmallett (i.e. 0 = 0-page-ptrs, 1 = 256-page-ptrs,..) */ 2481215976Sjmallett#else 2482215976Sjmallett uint64_t page_cnt : 17; 2483215976Sjmallett uint64_t bp_enb : 1; 2484215976Sjmallett uint64_t reserved_18_63 : 46; 2485215976Sjmallett#endif 2486215976Sjmallett } s; 2487232812Sjmallett struct cvmx_ipd_portx_bp_page_cnt3_s cn61xx; 2488215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt3_s cn63xx; 2489215976Sjmallett struct cvmx_ipd_portx_bp_page_cnt3_s cn63xxp1; 2490232812Sjmallett struct cvmx_ipd_portx_bp_page_cnt3_s cn66xx; 2491232812Sjmallett struct cvmx_ipd_portx_bp_page_cnt3_s cnf71xx; 2492215976Sjmallett}; 2493215976Sjmalletttypedef union cvmx_ipd_portx_bp_page_cnt3 cvmx_ipd_portx_bp_page_cnt3_t; 2494215976Sjmallett 2495215976Sjmallett/** 2496215976Sjmallett * cvmx_ipd_port_bp_counters2_pair# 2497215976Sjmallett * 2498215976Sjmallett * IPD_PORT_BP_COUNTERS2_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port. 2499215976Sjmallett * See also IPD_PORT_BP_COUNTERS_PAIRX 2500215976Sjmallett * See also IPD_PORT_BP_COUNTERS3_PAIRX 2501232812Sjmallett * 0x388-0x3a0 2502215976Sjmallett */ 2503232812Sjmallettunion cvmx_ipd_port_bp_counters2_pairx { 2504215976Sjmallett uint64_t u64; 2505232812Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s { 2506232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2507215976Sjmallett uint64_t reserved_25_63 : 39; 2508215976Sjmallett uint64_t cnt_val : 25; /**< Number of MBUFs being used by data on this port. */ 2509215976Sjmallett#else 2510215976Sjmallett uint64_t cnt_val : 25; 2511215976Sjmallett uint64_t reserved_25_63 : 39; 2512215976Sjmallett#endif 2513215976Sjmallett } s; 2514215976Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx; 2515215976Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1; 2516215976Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx; 2517215976Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1; 2518232812Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s cn61xx; 2519215976Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s cn63xx; 2520215976Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s cn63xxp1; 2521232812Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s cn66xx; 2522232812Sjmallett struct cvmx_ipd_port_bp_counters2_pairx_s cnf71xx; 2523215976Sjmallett}; 2524215976Sjmalletttypedef union cvmx_ipd_port_bp_counters2_pairx cvmx_ipd_port_bp_counters2_pairx_t; 2525215976Sjmallett 2526215976Sjmallett/** 2527215976Sjmallett * cvmx_ipd_port_bp_counters3_pair# 2528215976Sjmallett * 2529215976Sjmallett * IPD_PORT_BP_COUNTERS3_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port. 2530215976Sjmallett * See also IPD_PORT_BP_COUNTERS_PAIRX 2531215976Sjmallett * See also IPD_PORT_BP_COUNTERS2_PAIRX 2532232812Sjmallett * 0x3b0-0x3c8 2533215976Sjmallett */ 2534232812Sjmallettunion cvmx_ipd_port_bp_counters3_pairx { 2535215976Sjmallett uint64_t u64; 2536232812Sjmallett struct cvmx_ipd_port_bp_counters3_pairx_s { 2537232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2538215976Sjmallett uint64_t reserved_25_63 : 39; 2539215976Sjmallett uint64_t cnt_val : 25; /**< Number of MBUFs being used by data on this port. */ 2540215976Sjmallett#else 2541215976Sjmallett uint64_t cnt_val : 25; 2542215976Sjmallett uint64_t reserved_25_63 : 39; 2543215976Sjmallett#endif 2544215976Sjmallett } s; 2545232812Sjmallett struct cvmx_ipd_port_bp_counters3_pairx_s cn61xx; 2546215976Sjmallett struct cvmx_ipd_port_bp_counters3_pairx_s cn63xx; 2547215976Sjmallett struct cvmx_ipd_port_bp_counters3_pairx_s cn63xxp1; 2548232812Sjmallett struct cvmx_ipd_port_bp_counters3_pairx_s cn66xx; 2549232812Sjmallett struct cvmx_ipd_port_bp_counters3_pairx_s cnf71xx; 2550215976Sjmallett}; 2551215976Sjmalletttypedef union cvmx_ipd_port_bp_counters3_pairx cvmx_ipd_port_bp_counters3_pairx_t; 2552215976Sjmallett 2553215976Sjmallett/** 2554232812Sjmallett * cvmx_ipd_port_bp_counters4_pair# 2555232812Sjmallett * 2556232812Sjmallett * IPD_PORT_BP_COUNTERS4_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port. 2557232812Sjmallett * See also IPD_PORT_BP_COUNTERS_PAIRX 2558232812Sjmallett * See also IPD_PORT_BP_COUNTERS2_PAIRX 2559232812Sjmallett * 0x410-0x3c8 2560232812Sjmallett */ 2561232812Sjmallettunion cvmx_ipd_port_bp_counters4_pairx { 2562232812Sjmallett uint64_t u64; 2563232812Sjmallett struct cvmx_ipd_port_bp_counters4_pairx_s { 2564232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2565232812Sjmallett uint64_t reserved_25_63 : 39; 2566232812Sjmallett uint64_t cnt_val : 25; /**< Number of MBUFs being used by data on this port. */ 2567232812Sjmallett#else 2568232812Sjmallett uint64_t cnt_val : 25; 2569232812Sjmallett uint64_t reserved_25_63 : 39; 2570232812Sjmallett#endif 2571232812Sjmallett } s; 2572232812Sjmallett struct cvmx_ipd_port_bp_counters4_pairx_s cn61xx; 2573232812Sjmallett struct cvmx_ipd_port_bp_counters4_pairx_s cn66xx; 2574232812Sjmallett struct cvmx_ipd_port_bp_counters4_pairx_s cnf71xx; 2575232812Sjmallett}; 2576232812Sjmalletttypedef union cvmx_ipd_port_bp_counters4_pairx cvmx_ipd_port_bp_counters4_pairx_t; 2577232812Sjmallett 2578232812Sjmallett/** 2579215976Sjmallett * cvmx_ipd_port_bp_counters_pair# 2580215976Sjmallett * 2581215976Sjmallett * IPD_PORT_BP_COUNTERS_PAIRX = MBUF Counters port Ports used to generate Back Pressure Per Port. 2582215976Sjmallett * See also IPD_PORT_BP_COUNTERS2_PAIRX 2583215976Sjmallett * See also IPD_PORT_BP_COUNTERS3_PAIRX 2584232812Sjmallett * 0x1b8-0x2d0 2585215976Sjmallett */ 2586232812Sjmallettunion cvmx_ipd_port_bp_counters_pairx { 2587215976Sjmallett uint64_t u64; 2588232812Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s { 2589232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2590215976Sjmallett uint64_t reserved_25_63 : 39; 2591215976Sjmallett uint64_t cnt_val : 25; /**< Number of MBUFs being used by data on this port. */ 2592215976Sjmallett#else 2593215976Sjmallett uint64_t cnt_val : 25; 2594215976Sjmallett uint64_t reserved_25_63 : 39; 2595215976Sjmallett#endif 2596215976Sjmallett } s; 2597215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn30xx; 2598215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn31xx; 2599215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn38xx; 2600215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn38xxp2; 2601215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn50xx; 2602215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn52xx; 2603215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn52xxp1; 2604215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn56xx; 2605215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1; 2606215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn58xx; 2607215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1; 2608232812Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn61xx; 2609215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn63xx; 2610215976Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn63xxp1; 2611232812Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cn66xx; 2612232812Sjmallett struct cvmx_ipd_port_bp_counters_pairx_s cnf71xx; 2613215976Sjmallett}; 2614215976Sjmalletttypedef union cvmx_ipd_port_bp_counters_pairx cvmx_ipd_port_bp_counters_pairx_t; 2615215976Sjmallett 2616215976Sjmallett/** 2617232812Sjmallett * cvmx_ipd_port_ptr_fifo_ctl 2618232812Sjmallett * 2619232812Sjmallett * IPD_PORT_PTR_FIFO_CTL = IPD's Reasm-Id Pointer FIFO Control 2620232812Sjmallett * 2621232812Sjmallett * Allows reading of the Page-Pointers stored in the IPD's Reasm-Id Fifo. 2622232812Sjmallett */ 2623232812Sjmallettunion cvmx_ipd_port_ptr_fifo_ctl { 2624232812Sjmallett uint64_t u64; 2625232812Sjmallett struct cvmx_ipd_port_ptr_fifo_ctl_s { 2626232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2627232812Sjmallett uint64_t reserved_48_63 : 16; 2628232812Sjmallett uint64_t ptr : 33; /**< The output of the reasm-id-ptr-fifo. */ 2629232812Sjmallett uint64_t max_pkt : 7; /**< Maximum number of Packet-Pointers that are in 2630232812Sjmallett in the FIFO. */ 2631232812Sjmallett uint64_t cena : 1; /**< Active low Chip Enable to the read the 2632232812Sjmallett pwp_fifo. This bit also controls the MUX-select 2633232812Sjmallett that steers [RADDR] to the pwp_fifo. 2634232812Sjmallett *WARNING - Setting this field to '0' will allow 2635232812Sjmallett reading of the memories thorugh the PTR field, 2636232812Sjmallett but will cause unpredictable operation of the IPD 2637232812Sjmallett under normal operation. */ 2638232812Sjmallett uint64_t raddr : 7; /**< Sets the address to read from in the reasm-id 2639232812Sjmallett fifo in the IPD. This FIFO holds Packet-Pointers 2640232812Sjmallett to be used for packet data storage. */ 2641232812Sjmallett#else 2642232812Sjmallett uint64_t raddr : 7; 2643232812Sjmallett uint64_t cena : 1; 2644232812Sjmallett uint64_t max_pkt : 7; 2645232812Sjmallett uint64_t ptr : 33; 2646232812Sjmallett uint64_t reserved_48_63 : 16; 2647232812Sjmallett#endif 2648232812Sjmallett } s; 2649232812Sjmallett struct cvmx_ipd_port_ptr_fifo_ctl_s cn68xx; 2650232812Sjmallett struct cvmx_ipd_port_ptr_fifo_ctl_s cn68xxp1; 2651232812Sjmallett}; 2652232812Sjmalletttypedef union cvmx_ipd_port_ptr_fifo_ctl cvmx_ipd_port_ptr_fifo_ctl_t; 2653232812Sjmallett 2654232812Sjmallett/** 2655215976Sjmallett * cvmx_ipd_port_qos_#_cnt 2656215976Sjmallett * 2657215976Sjmallett * IPD_PORT_QOS_X_CNT = IPD PortX QOS-0 Count 2658215976Sjmallett * 2659215976Sjmallett * A counter per port/qos. Counter are originzed in sequence where the first 8 counter (0-7) belong to Port-0 2660215976Sjmallett * QOS 0-7 respectively followed by port 1 at (8-15), etc 2661215976Sjmallett * Ports 0-3, 32-43 2662215976Sjmallett */ 2663232812Sjmallettunion cvmx_ipd_port_qos_x_cnt { 2664215976Sjmallett uint64_t u64; 2665232812Sjmallett struct cvmx_ipd_port_qos_x_cnt_s { 2666232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2667215976Sjmallett uint64_t wmark : 32; /**< When the field CNT after being modified is equal to 2668215976Sjmallett or crosses this value (i.e. value was greater than 2669215976Sjmallett then becomes less then, or value was less than and 2670215976Sjmallett becomes greater than) the corresponding bit in 2671215976Sjmallett IPD_PORT_QOS_INTX is set. */ 2672215976Sjmallett uint64_t cnt : 32; /**< The packet related count that is incremented as 2673215976Sjmallett specified by IPD_SUB_PORT_QOS_CNT. */ 2674215976Sjmallett#else 2675215976Sjmallett uint64_t cnt : 32; 2676215976Sjmallett uint64_t wmark : 32; 2677215976Sjmallett#endif 2678215976Sjmallett } s; 2679215976Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cn52xx; 2680215976Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1; 2681215976Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cn56xx; 2682215976Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1; 2683232812Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cn61xx; 2684215976Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cn63xx; 2685215976Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cn63xxp1; 2686232812Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cn66xx; 2687232812Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cn68xx; 2688232812Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cn68xxp1; 2689232812Sjmallett struct cvmx_ipd_port_qos_x_cnt_s cnf71xx; 2690215976Sjmallett}; 2691215976Sjmalletttypedef union cvmx_ipd_port_qos_x_cnt cvmx_ipd_port_qos_x_cnt_t; 2692215976Sjmallett 2693215976Sjmallett/** 2694215976Sjmallett * cvmx_ipd_port_qos_int# 2695215976Sjmallett * 2696215976Sjmallett * IPD_PORT_QOS_INTX = IPD PORT-QOS Interrupt 2697215976Sjmallett * 2698215976Sjmallett * See the description for IPD_PORT_QOS_X_CNT 2699215976Sjmallett * 2700215976Sjmallett * 0=P0-7; 1=P8-15; 2=P16-23; 3=P24-31; 4=P32-39; 5=P40-47; 6=P48-55; 7=P56-63 2701215976Sjmallett * 2702232812Sjmallett * Only ports used are: P0-3, P32-39, and P40-47. Therefore only IPD_PORT_QOS_INT0, IPD_PORT_QOS_INT4, 2703232812Sjmallett * and IPD_PORT_QOS_INT5 exist and, furthermore: <63:32> of IPD_PORT_QOS_INT0, 2704215976Sjmallett * are reserved. 2705215976Sjmallett */ 2706232812Sjmallettunion cvmx_ipd_port_qos_intx { 2707215976Sjmallett uint64_t u64; 2708232812Sjmallett struct cvmx_ipd_port_qos_intx_s { 2709232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2710215976Sjmallett uint64_t intr : 64; /**< Interrupt bits. */ 2711215976Sjmallett#else 2712215976Sjmallett uint64_t intr : 64; 2713215976Sjmallett#endif 2714215976Sjmallett } s; 2715215976Sjmallett struct cvmx_ipd_port_qos_intx_s cn52xx; 2716215976Sjmallett struct cvmx_ipd_port_qos_intx_s cn52xxp1; 2717215976Sjmallett struct cvmx_ipd_port_qos_intx_s cn56xx; 2718215976Sjmallett struct cvmx_ipd_port_qos_intx_s cn56xxp1; 2719232812Sjmallett struct cvmx_ipd_port_qos_intx_s cn61xx; 2720215976Sjmallett struct cvmx_ipd_port_qos_intx_s cn63xx; 2721215976Sjmallett struct cvmx_ipd_port_qos_intx_s cn63xxp1; 2722232812Sjmallett struct cvmx_ipd_port_qos_intx_s cn66xx; 2723232812Sjmallett struct cvmx_ipd_port_qos_intx_s cn68xx; 2724232812Sjmallett struct cvmx_ipd_port_qos_intx_s cn68xxp1; 2725232812Sjmallett struct cvmx_ipd_port_qos_intx_s cnf71xx; 2726215976Sjmallett}; 2727215976Sjmalletttypedef union cvmx_ipd_port_qos_intx cvmx_ipd_port_qos_intx_t; 2728215976Sjmallett 2729215976Sjmallett/** 2730215976Sjmallett * cvmx_ipd_port_qos_int_enb# 2731215976Sjmallett * 2732215976Sjmallett * IPD_PORT_QOS_INT_ENBX = IPD PORT-QOS Interrupt Enable 2733215976Sjmallett * 2734215976Sjmallett * When the IPD_PORT_QOS_INTX[\#] is '1' and IPD_PORT_QOS_INT_ENBX[\#] is '1' a interrupt will be generated. 2735215976Sjmallett */ 2736232812Sjmallettunion cvmx_ipd_port_qos_int_enbx { 2737215976Sjmallett uint64_t u64; 2738232812Sjmallett struct cvmx_ipd_port_qos_int_enbx_s { 2739232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2740215976Sjmallett uint64_t enb : 64; /**< Enable bits. */ 2741215976Sjmallett#else 2742215976Sjmallett uint64_t enb : 64; 2743215976Sjmallett#endif 2744215976Sjmallett } s; 2745215976Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cn52xx; 2746215976Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1; 2747215976Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cn56xx; 2748215976Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1; 2749232812Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cn61xx; 2750215976Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cn63xx; 2751215976Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cn63xxp1; 2752232812Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cn66xx; 2753232812Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cn68xx; 2754232812Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cn68xxp1; 2755232812Sjmallett struct cvmx_ipd_port_qos_int_enbx_s cnf71xx; 2756215976Sjmallett}; 2757215976Sjmalletttypedef union cvmx_ipd_port_qos_int_enbx cvmx_ipd_port_qos_int_enbx_t; 2758215976Sjmallett 2759215976Sjmallett/** 2760232812Sjmallett * cvmx_ipd_port_sop# 2761232812Sjmallett * 2762232812Sjmallett * IPD_PORT_SOP = IPD Reasm-Id SOP 2763232812Sjmallett * 2764232812Sjmallett * Set when a SOP is detected on a reasm-num. Where the reasm-num value set the bit vector of this register. 2765232812Sjmallett */ 2766232812Sjmallettunion cvmx_ipd_port_sopx { 2767232812Sjmallett uint64_t u64; 2768232812Sjmallett struct cvmx_ipd_port_sopx_s { 2769232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2770232812Sjmallett uint64_t sop : 64; /**< When set '1' a SOP was detected on a reasm-num, 2771232812Sjmallett When clear '0' no SOP was yet received or an EOP 2772232812Sjmallett was received on the reasm-num. 2773232812Sjmallett IPD only supports 63 reasm-nums, so bit [63] 2774232812Sjmallett should never be set. */ 2775232812Sjmallett#else 2776232812Sjmallett uint64_t sop : 64; 2777232812Sjmallett#endif 2778232812Sjmallett } s; 2779232812Sjmallett struct cvmx_ipd_port_sopx_s cn68xx; 2780232812Sjmallett struct cvmx_ipd_port_sopx_s cn68xxp1; 2781232812Sjmallett}; 2782232812Sjmalletttypedef union cvmx_ipd_port_sopx cvmx_ipd_port_sopx_t; 2783232812Sjmallett 2784232812Sjmallett/** 2785215976Sjmallett * cvmx_ipd_prc_hold_ptr_fifo_ctl 2786215976Sjmallett * 2787215976Sjmallett * IPD_PRC_HOLD_PTR_FIFO_CTL = IPD's PRC Holding Pointer FIFO Control 2788215976Sjmallett * 2789215976Sjmallett * Allows reading of the Page-Pointers stored in the IPD's PRC Holding Fifo. 2790215976Sjmallett */ 2791232812Sjmallettunion cvmx_ipd_prc_hold_ptr_fifo_ctl { 2792215976Sjmallett uint64_t u64; 2793232812Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s { 2794232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2795215976Sjmallett uint64_t reserved_39_63 : 25; 2796215976Sjmallett uint64_t max_pkt : 3; /**< Maximum number of Packet-Pointers that COULD be 2797215976Sjmallett in the FIFO. */ 2798215976Sjmallett uint64_t praddr : 3; /**< Present Packet-Pointer read address. */ 2799215976Sjmallett uint64_t ptr : 29; /**< The output of the prc-holding-fifo. */ 2800215976Sjmallett uint64_t cena : 1; /**< Active low Chip Enable that controls the 2801215976Sjmallett MUX-select that steers [RADDR] to the fifo. 2802215976Sjmallett *WARNING - Setting this field to '0' will allow 2803215976Sjmallett reading of the memories thorugh the PTR field, 2804215976Sjmallett but will cause unpredictable operation of the IPD 2805215976Sjmallett under normal operation. */ 2806215976Sjmallett uint64_t raddr : 3; /**< Sets the address to read from in the holding. 2807215976Sjmallett fifo in the PRC. This FIFO holds Packet-Pointers 2808215976Sjmallett to be used for packet data storage. */ 2809215976Sjmallett#else 2810215976Sjmallett uint64_t raddr : 3; 2811215976Sjmallett uint64_t cena : 1; 2812215976Sjmallett uint64_t ptr : 29; 2813215976Sjmallett uint64_t praddr : 3; 2814215976Sjmallett uint64_t max_pkt : 3; 2815215976Sjmallett uint64_t reserved_39_63 : 25; 2816215976Sjmallett#endif 2817215976Sjmallett } s; 2818215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx; 2819215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx; 2820215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn38xx; 2821215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn50xx; 2822215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xx; 2823215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xxp1; 2824215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xx; 2825215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1; 2826215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx; 2827215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1; 2828232812Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn61xx; 2829215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xx; 2830215976Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xxp1; 2831232812Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn66xx; 2832232812Sjmallett struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cnf71xx; 2833215976Sjmallett}; 2834215976Sjmalletttypedef union cvmx_ipd_prc_hold_ptr_fifo_ctl cvmx_ipd_prc_hold_ptr_fifo_ctl_t; 2835215976Sjmallett 2836215976Sjmallett/** 2837215976Sjmallett * cvmx_ipd_prc_port_ptr_fifo_ctl 2838215976Sjmallett * 2839215976Sjmallett * IPD_PRC_PORT_PTR_FIFO_CTL = IPD's PRC PORT Pointer FIFO Control 2840215976Sjmallett * 2841215976Sjmallett * Allows reading of the Page-Pointers stored in the IPD's PRC PORT Fifo. 2842215976Sjmallett */ 2843232812Sjmallettunion cvmx_ipd_prc_port_ptr_fifo_ctl { 2844215976Sjmallett uint64_t u64; 2845232812Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s { 2846232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2847215976Sjmallett uint64_t reserved_44_63 : 20; 2848215976Sjmallett uint64_t max_pkt : 7; /**< Maximum number of Packet-Pointers that are in 2849215976Sjmallett in the FIFO. */ 2850215976Sjmallett uint64_t ptr : 29; /**< The output of the prc-port-ptr-fifo. */ 2851215976Sjmallett uint64_t cena : 1; /**< Active low Chip Enable to the read port of the 2852215976Sjmallett pwp_fifo. This bit also controls the MUX-select 2853215976Sjmallett that steers [RADDR] to the pwp_fifo. 2854215976Sjmallett *WARNING - Setting this field to '0' will allow 2855215976Sjmallett reading of the memories thorugh the PTR field, 2856215976Sjmallett but will cause unpredictable operation of the IPD 2857215976Sjmallett under normal operation. */ 2858215976Sjmallett uint64_t raddr : 7; /**< Sets the address to read from in the port 2859215976Sjmallett fifo in the PRC. This FIFO holds Packet-Pointers 2860215976Sjmallett to be used for packet data storage. */ 2861215976Sjmallett#else 2862215976Sjmallett uint64_t raddr : 7; 2863215976Sjmallett uint64_t cena : 1; 2864215976Sjmallett uint64_t ptr : 29; 2865215976Sjmallett uint64_t max_pkt : 7; 2866215976Sjmallett uint64_t reserved_44_63 : 20; 2867215976Sjmallett#endif 2868215976Sjmallett } s; 2869215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx; 2870215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx; 2871215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn38xx; 2872215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn50xx; 2873215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xx; 2874215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xxp1; 2875215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xx; 2876215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1; 2877215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx; 2878215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1; 2879232812Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn61xx; 2880215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xx; 2881215976Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xxp1; 2882232812Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn66xx; 2883232812Sjmallett struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cnf71xx; 2884215976Sjmallett}; 2885215976Sjmalletttypedef union cvmx_ipd_prc_port_ptr_fifo_ctl cvmx_ipd_prc_port_ptr_fifo_ctl_t; 2886215976Sjmallett 2887215976Sjmallett/** 2888215976Sjmallett * cvmx_ipd_ptr_count 2889215976Sjmallett * 2890215976Sjmallett * IPD_PTR_COUNT = IPD Page Pointer Count 2891215976Sjmallett * 2892215976Sjmallett * Shows the number of WQE and Packet Page Pointers stored in the IPD. 2893215976Sjmallett */ 2894232812Sjmallettunion cvmx_ipd_ptr_count { 2895215976Sjmallett uint64_t u64; 2896232812Sjmallett struct cvmx_ipd_ptr_count_s { 2897232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2898215976Sjmallett uint64_t reserved_19_63 : 45; 2899215976Sjmallett uint64_t pktv_cnt : 1; /**< PKT Ptr Valid. */ 2900215976Sjmallett uint64_t wqev_cnt : 1; /**< WQE Ptr Valid. This value is '1' when a WQE 2901215976Sjmallett is being for use by the IPD. The value of this 2902215976Sjmallett field should be added to tha value of the 2903215976Sjmallett WQE_PCNT field, of this register, for a total 2904215976Sjmallett count of the WQE Page Pointers being held by IPD. 2905215976Sjmallett When IPD_CTL_STATUS[NO_WPTR] is set '1' this field 2906215976Sjmallett represents a Packet-Pointer NOT a WQE pointer. */ 2907215976Sjmallett uint64_t pfif_cnt : 3; /**< See PKT_PCNT. */ 2908215976Sjmallett uint64_t pkt_pcnt : 7; /**< This value plus PFIF_CNT plus 2909215976Sjmallett IPD_PRC_PORT_PTR_FIFO_CTL[MAX_PKT] is the number 2910215976Sjmallett of PKT Page Pointers in IPD. */ 2911215976Sjmallett uint64_t wqe_pcnt : 7; /**< Number of page pointers for WQE storage that are 2912215976Sjmallett buffered in the IPD. The total count is the value 2913215976Sjmallett of this buffer plus the field [WQEV_CNT]. For 2914215976Sjmallett PASS-1 (which does not have the WQEV_CNT field) 2915215976Sjmallett when the value of this register is '0' there still 2916215976Sjmallett may be 1 pointer being held by IPD. */ 2917215976Sjmallett#else 2918215976Sjmallett uint64_t wqe_pcnt : 7; 2919215976Sjmallett uint64_t pkt_pcnt : 7; 2920215976Sjmallett uint64_t pfif_cnt : 3; 2921215976Sjmallett uint64_t wqev_cnt : 1; 2922215976Sjmallett uint64_t pktv_cnt : 1; 2923215976Sjmallett uint64_t reserved_19_63 : 45; 2924215976Sjmallett#endif 2925215976Sjmallett } s; 2926215976Sjmallett struct cvmx_ipd_ptr_count_s cn30xx; 2927215976Sjmallett struct cvmx_ipd_ptr_count_s cn31xx; 2928215976Sjmallett struct cvmx_ipd_ptr_count_s cn38xx; 2929215976Sjmallett struct cvmx_ipd_ptr_count_s cn38xxp2; 2930215976Sjmallett struct cvmx_ipd_ptr_count_s cn50xx; 2931215976Sjmallett struct cvmx_ipd_ptr_count_s cn52xx; 2932215976Sjmallett struct cvmx_ipd_ptr_count_s cn52xxp1; 2933215976Sjmallett struct cvmx_ipd_ptr_count_s cn56xx; 2934215976Sjmallett struct cvmx_ipd_ptr_count_s cn56xxp1; 2935215976Sjmallett struct cvmx_ipd_ptr_count_s cn58xx; 2936215976Sjmallett struct cvmx_ipd_ptr_count_s cn58xxp1; 2937232812Sjmallett struct cvmx_ipd_ptr_count_s cn61xx; 2938215976Sjmallett struct cvmx_ipd_ptr_count_s cn63xx; 2939215976Sjmallett struct cvmx_ipd_ptr_count_s cn63xxp1; 2940232812Sjmallett struct cvmx_ipd_ptr_count_s cn66xx; 2941232812Sjmallett struct cvmx_ipd_ptr_count_s cn68xx; 2942232812Sjmallett struct cvmx_ipd_ptr_count_s cn68xxp1; 2943232812Sjmallett struct cvmx_ipd_ptr_count_s cnf71xx; 2944215976Sjmallett}; 2945215976Sjmalletttypedef union cvmx_ipd_ptr_count cvmx_ipd_ptr_count_t; 2946215976Sjmallett 2947215976Sjmallett/** 2948215976Sjmallett * cvmx_ipd_pwp_ptr_fifo_ctl 2949215976Sjmallett * 2950215976Sjmallett * IPD_PWP_PTR_FIFO_CTL = IPD's PWP Pointer FIFO Control 2951215976Sjmallett * 2952215976Sjmallett * Allows reading of the Page-Pointers stored in the IPD's PWP Fifo. 2953215976Sjmallett */ 2954232812Sjmallettunion cvmx_ipd_pwp_ptr_fifo_ctl { 2955215976Sjmallett uint64_t u64; 2956232812Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s { 2957232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2958215976Sjmallett uint64_t reserved_61_63 : 3; 2959215976Sjmallett uint64_t max_cnts : 7; /**< Maximum number of Packet-Pointers or WQE-Pointers 2960215976Sjmallett that COULD be in the FIFO. 2961215976Sjmallett When IPD_CTL_STATUS[NO_WPTR] is set '1' this field 2962215976Sjmallett only represents the Max number of Packet-Pointers, 2963215976Sjmallett WQE-Pointers are not used in this mode. */ 2964215976Sjmallett uint64_t wraddr : 8; /**< Present FIFO WQE Read address. */ 2965215976Sjmallett uint64_t praddr : 8; /**< Present FIFO Packet Read address. */ 2966215976Sjmallett uint64_t ptr : 29; /**< The output of the pwp_fifo. */ 2967215976Sjmallett uint64_t cena : 1; /**< Active low Chip Enable to the read port of the 2968215976Sjmallett pwp_fifo. This bit also controls the MUX-select 2969215976Sjmallett that steers [RADDR] to the pwp_fifo. 2970215976Sjmallett *WARNING - Setting this field to '0' will allow 2971215976Sjmallett reading of the memories thorugh the PTR field, 2972215976Sjmallett but will cause unpredictable operation of the IPD 2973215976Sjmallett under normal operation. */ 2974215976Sjmallett uint64_t raddr : 8; /**< Sets the address to read from in the pwp_fifo. 2975215976Sjmallett Addresses 0 through 63 contain Packet-Pointers and 2976215976Sjmallett addresses 64 through 127 contain WQE-Pointers. 2977215976Sjmallett When IPD_CTL_STATUS[NO_WPTR] is set '1' addresses 2978215976Sjmallett 64 through 127 are not valid. */ 2979215976Sjmallett#else 2980215976Sjmallett uint64_t raddr : 8; 2981215976Sjmallett uint64_t cena : 1; 2982215976Sjmallett uint64_t ptr : 29; 2983215976Sjmallett uint64_t praddr : 8; 2984215976Sjmallett uint64_t wraddr : 8; 2985215976Sjmallett uint64_t max_cnts : 7; 2986215976Sjmallett uint64_t reserved_61_63 : 3; 2987215976Sjmallett#endif 2988215976Sjmallett } s; 2989215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn30xx; 2990215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn31xx; 2991215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn38xx; 2992215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn50xx; 2993215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xx; 2994215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xxp1; 2995215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xx; 2996215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1; 2997215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx; 2998215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1; 2999232812Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn61xx; 3000215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xx; 3001215976Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xxp1; 3002232812Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn66xx; 3003232812Sjmallett struct cvmx_ipd_pwp_ptr_fifo_ctl_s cnf71xx; 3004215976Sjmallett}; 3005215976Sjmalletttypedef union cvmx_ipd_pwp_ptr_fifo_ctl cvmx_ipd_pwp_ptr_fifo_ctl_t; 3006215976Sjmallett 3007215976Sjmallett/** 3008215976Sjmallett * cvmx_ipd_qos#_red_marks 3009215976Sjmallett * 3010215976Sjmallett * IPD_QOS0_RED_MARKS = IPD QOS 0 Marks Red High Low 3011215976Sjmallett * 3012215976Sjmallett * Set the pass-drop marks for qos level. 3013215976Sjmallett */ 3014232812Sjmallettunion cvmx_ipd_qosx_red_marks { 3015215976Sjmallett uint64_t u64; 3016232812Sjmallett struct cvmx_ipd_qosx_red_marks_s { 3017232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3018215976Sjmallett uint64_t drop : 32; /**< Packets will be dropped when the average value of 3019215976Sjmallett IPD_QUE0_FREE_PAGE_CNT is equal to or less than 3020215976Sjmallett this value. */ 3021215976Sjmallett uint64_t pass : 32; /**< Packets will be passed when the average value of 3022215976Sjmallett IPD_QUE0_FREE_PAGE_CNT is larger than this value. */ 3023215976Sjmallett#else 3024215976Sjmallett uint64_t pass : 32; 3025215976Sjmallett uint64_t drop : 32; 3026215976Sjmallett#endif 3027215976Sjmallett } s; 3028215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn30xx; 3029215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn31xx; 3030215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn38xx; 3031215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn38xxp2; 3032215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn50xx; 3033215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn52xx; 3034215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn52xxp1; 3035215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn56xx; 3036215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn56xxp1; 3037215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn58xx; 3038215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn58xxp1; 3039232812Sjmallett struct cvmx_ipd_qosx_red_marks_s cn61xx; 3040215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn63xx; 3041215976Sjmallett struct cvmx_ipd_qosx_red_marks_s cn63xxp1; 3042232812Sjmallett struct cvmx_ipd_qosx_red_marks_s cn66xx; 3043232812Sjmallett struct cvmx_ipd_qosx_red_marks_s cn68xx; 3044232812Sjmallett struct cvmx_ipd_qosx_red_marks_s cn68xxp1; 3045232812Sjmallett struct cvmx_ipd_qosx_red_marks_s cnf71xx; 3046215976Sjmallett}; 3047215976Sjmalletttypedef union cvmx_ipd_qosx_red_marks cvmx_ipd_qosx_red_marks_t; 3048215976Sjmallett 3049215976Sjmallett/** 3050215976Sjmallett * cvmx_ipd_que0_free_page_cnt 3051215976Sjmallett * 3052215976Sjmallett * IPD_QUE0_FREE_PAGE_CNT = IPD Queue0 Free Page Count 3053215976Sjmallett * 3054215976Sjmallett * Number of Free-Page Pointer that are available for use in the FPA for Queue-0. 3055215976Sjmallett */ 3056232812Sjmallettunion cvmx_ipd_que0_free_page_cnt { 3057215976Sjmallett uint64_t u64; 3058232812Sjmallett struct cvmx_ipd_que0_free_page_cnt_s { 3059232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3060215976Sjmallett uint64_t reserved_32_63 : 32; 3061215976Sjmallett uint64_t q0_pcnt : 32; /**< Number of Queue-0 Page Pointers Available. */ 3062215976Sjmallett#else 3063215976Sjmallett uint64_t q0_pcnt : 32; 3064215976Sjmallett uint64_t reserved_32_63 : 32; 3065215976Sjmallett#endif 3066215976Sjmallett } s; 3067215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn30xx; 3068215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn31xx; 3069215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn38xx; 3070215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn38xxp2; 3071215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn50xx; 3072215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn52xx; 3073215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn52xxp1; 3074215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn56xx; 3075215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1; 3076215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn58xx; 3077215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1; 3078232812Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn61xx; 3079215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn63xx; 3080215976Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn63xxp1; 3081232812Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn66xx; 3082232812Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn68xx; 3083232812Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cn68xxp1; 3084232812Sjmallett struct cvmx_ipd_que0_free_page_cnt_s cnf71xx; 3085215976Sjmallett}; 3086215976Sjmalletttypedef union cvmx_ipd_que0_free_page_cnt cvmx_ipd_que0_free_page_cnt_t; 3087215976Sjmallett 3088215976Sjmallett/** 3089232812Sjmallett * cvmx_ipd_red_bpid_enable# 3090232812Sjmallett * 3091232812Sjmallett * IPD_RED_BPID_ENABLE = IPD RED BPID Enable 3092232812Sjmallett * 3093232812Sjmallett * Set the pass-drop marks for qos level. 3094232812Sjmallett */ 3095232812Sjmallettunion cvmx_ipd_red_bpid_enablex { 3096232812Sjmallett uint64_t u64; 3097232812Sjmallett struct cvmx_ipd_red_bpid_enablex_s { 3098232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3099232812Sjmallett uint64_t prt_enb : 64; /**< The bit position will enable the corresponding 3100232812Sjmallett BPIDs ability to have packets dropped by RED 3101232812Sjmallett probability. */ 3102232812Sjmallett#else 3103232812Sjmallett uint64_t prt_enb : 64; 3104232812Sjmallett#endif 3105232812Sjmallett } s; 3106232812Sjmallett struct cvmx_ipd_red_bpid_enablex_s cn68xx; 3107232812Sjmallett struct cvmx_ipd_red_bpid_enablex_s cn68xxp1; 3108232812Sjmallett}; 3109232812Sjmalletttypedef union cvmx_ipd_red_bpid_enablex cvmx_ipd_red_bpid_enablex_t; 3110232812Sjmallett 3111232812Sjmallett/** 3112232812Sjmallett * cvmx_ipd_red_delay 3113232812Sjmallett * 3114232812Sjmallett * IPD_RED_DELAY = IPD RED BPID Enable 3115232812Sjmallett * 3116232812Sjmallett * Set the pass-drop marks for qos level. 3117232812Sjmallett */ 3118232812Sjmallettunion cvmx_ipd_red_delay { 3119232812Sjmallett uint64_t u64; 3120232812Sjmallett struct cvmx_ipd_red_delay_s { 3121232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3122232812Sjmallett uint64_t reserved_28_63 : 36; 3123232812Sjmallett uint64_t prb_dly : 14; /**< Number (core clocks periods + 68) * 8 to wait 3124232812Sjmallett before calculating the new packet drop 3125232812Sjmallett probability for each QOS level. */ 3126232812Sjmallett uint64_t avg_dly : 14; /**< Number (core clocks periods + 10) * 8 to wait 3127232812Sjmallett before calculating the moving average for each 3128232812Sjmallett QOS level. 3129232812Sjmallett Larger AVG_DLY values cause the moving averages 3130232812Sjmallett of ALL QOS levels to track changes in the actual 3131232812Sjmallett free space more slowly. Smaller NEW_CON (and 3132232812Sjmallett larger AVG_CON) values can have a similar effect, 3133232812Sjmallett but only affect an individual QOS level, rather 3134232812Sjmallett than all. */ 3135232812Sjmallett#else 3136232812Sjmallett uint64_t avg_dly : 14; 3137232812Sjmallett uint64_t prb_dly : 14; 3138232812Sjmallett uint64_t reserved_28_63 : 36; 3139232812Sjmallett#endif 3140232812Sjmallett } s; 3141232812Sjmallett struct cvmx_ipd_red_delay_s cn68xx; 3142232812Sjmallett struct cvmx_ipd_red_delay_s cn68xxp1; 3143232812Sjmallett}; 3144232812Sjmalletttypedef union cvmx_ipd_red_delay cvmx_ipd_red_delay_t; 3145232812Sjmallett 3146232812Sjmallett/** 3147215976Sjmallett * cvmx_ipd_red_port_enable 3148215976Sjmallett * 3149215976Sjmallett * IPD_RED_PORT_ENABLE = IPD RED Port Enable 3150215976Sjmallett * 3151215976Sjmallett * Set the pass-drop marks for qos level. 3152215976Sjmallett */ 3153232812Sjmallettunion cvmx_ipd_red_port_enable { 3154215976Sjmallett uint64_t u64; 3155232812Sjmallett struct cvmx_ipd_red_port_enable_s { 3156232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3157215976Sjmallett uint64_t prb_dly : 14; /**< Number (core clocks periods + 68) * 8 to wait 3158215976Sjmallett before calculating the new packet drop 3159215976Sjmallett probability for each QOS level. */ 3160215976Sjmallett uint64_t avg_dly : 14; /**< Number (core clocks periods + 10) * 8 to wait 3161215976Sjmallett before calculating the moving average for each 3162215976Sjmallett QOS level. 3163215976Sjmallett Larger AVG_DLY values cause the moving averages 3164215976Sjmallett of ALL QOS levels to track changes in the actual 3165215976Sjmallett free space more slowly. Smaller NEW_CON (and 3166215976Sjmallett larger AVG_CON) values can have a similar effect, 3167215976Sjmallett but only affect an individual QOS level, rather 3168215976Sjmallett than all. */ 3169215976Sjmallett uint64_t prt_enb : 36; /**< The bit position will enable the corresponding 3170215976Sjmallett Ports ability to have packets dropped by RED 3171215976Sjmallett probability. */ 3172215976Sjmallett#else 3173215976Sjmallett uint64_t prt_enb : 36; 3174215976Sjmallett uint64_t avg_dly : 14; 3175215976Sjmallett uint64_t prb_dly : 14; 3176215976Sjmallett#endif 3177215976Sjmallett } s; 3178215976Sjmallett struct cvmx_ipd_red_port_enable_s cn30xx; 3179215976Sjmallett struct cvmx_ipd_red_port_enable_s cn31xx; 3180215976Sjmallett struct cvmx_ipd_red_port_enable_s cn38xx; 3181215976Sjmallett struct cvmx_ipd_red_port_enable_s cn38xxp2; 3182215976Sjmallett struct cvmx_ipd_red_port_enable_s cn50xx; 3183215976Sjmallett struct cvmx_ipd_red_port_enable_s cn52xx; 3184215976Sjmallett struct cvmx_ipd_red_port_enable_s cn52xxp1; 3185215976Sjmallett struct cvmx_ipd_red_port_enable_s cn56xx; 3186215976Sjmallett struct cvmx_ipd_red_port_enable_s cn56xxp1; 3187215976Sjmallett struct cvmx_ipd_red_port_enable_s cn58xx; 3188215976Sjmallett struct cvmx_ipd_red_port_enable_s cn58xxp1; 3189232812Sjmallett struct cvmx_ipd_red_port_enable_s cn61xx; 3190215976Sjmallett struct cvmx_ipd_red_port_enable_s cn63xx; 3191215976Sjmallett struct cvmx_ipd_red_port_enable_s cn63xxp1; 3192232812Sjmallett struct cvmx_ipd_red_port_enable_s cn66xx; 3193232812Sjmallett struct cvmx_ipd_red_port_enable_s cnf71xx; 3194215976Sjmallett}; 3195215976Sjmalletttypedef union cvmx_ipd_red_port_enable cvmx_ipd_red_port_enable_t; 3196215976Sjmallett 3197215976Sjmallett/** 3198215976Sjmallett * cvmx_ipd_red_port_enable2 3199215976Sjmallett * 3200215976Sjmallett * IPD_RED_PORT_ENABLE2 = IPD RED Port Enable2 3201215976Sjmallett * 3202215976Sjmallett * Set the pass-drop marks for qos level. 3203215976Sjmallett */ 3204232812Sjmallettunion cvmx_ipd_red_port_enable2 { 3205215976Sjmallett uint64_t u64; 3206232812Sjmallett struct cvmx_ipd_red_port_enable2_s { 3207232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3208232812Sjmallett uint64_t reserved_12_63 : 52; 3209232812Sjmallett uint64_t prt_enb : 12; /**< Bits 11-0 corresponds to ports 47-36. These bits 3210215976Sjmallett have the same meaning as the PRT_ENB field of 3211215976Sjmallett IPD_RED_PORT_ENABLE. */ 3212215976Sjmallett#else 3213232812Sjmallett uint64_t prt_enb : 12; 3214232812Sjmallett uint64_t reserved_12_63 : 52; 3215215976Sjmallett#endif 3216215976Sjmallett } s; 3217232812Sjmallett struct cvmx_ipd_red_port_enable2_cn52xx { 3218232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3219215976Sjmallett uint64_t reserved_4_63 : 60; 3220215976Sjmallett uint64_t prt_enb : 4; /**< Bits 3-0 cooresponds to ports 39-36. These bits 3221215976Sjmallett have the same meaning as the PRT_ENB field of 3222215976Sjmallett IPD_RED_PORT_ENABLE. */ 3223215976Sjmallett#else 3224215976Sjmallett uint64_t prt_enb : 4; 3225215976Sjmallett uint64_t reserved_4_63 : 60; 3226215976Sjmallett#endif 3227215976Sjmallett } cn52xx; 3228215976Sjmallett struct cvmx_ipd_red_port_enable2_cn52xx cn52xxp1; 3229215976Sjmallett struct cvmx_ipd_red_port_enable2_cn52xx cn56xx; 3230215976Sjmallett struct cvmx_ipd_red_port_enable2_cn52xx cn56xxp1; 3231232812Sjmallett struct cvmx_ipd_red_port_enable2_s cn61xx; 3232232812Sjmallett struct cvmx_ipd_red_port_enable2_cn63xx { 3233232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3234232812Sjmallett uint64_t reserved_8_63 : 56; 3235232812Sjmallett uint64_t prt_enb : 8; /**< Bits 7-0 corresponds to ports 43-36. These bits 3236232812Sjmallett have the same meaning as the PRT_ENB field of 3237232812Sjmallett IPD_RED_PORT_ENABLE. */ 3238232812Sjmallett#else 3239232812Sjmallett uint64_t prt_enb : 8; 3240232812Sjmallett uint64_t reserved_8_63 : 56; 3241232812Sjmallett#endif 3242232812Sjmallett } cn63xx; 3243232812Sjmallett struct cvmx_ipd_red_port_enable2_cn63xx cn63xxp1; 3244232812Sjmallett struct cvmx_ipd_red_port_enable2_s cn66xx; 3245232812Sjmallett struct cvmx_ipd_red_port_enable2_s cnf71xx; 3246215976Sjmallett}; 3247215976Sjmalletttypedef union cvmx_ipd_red_port_enable2 cvmx_ipd_red_port_enable2_t; 3248215976Sjmallett 3249215976Sjmallett/** 3250215976Sjmallett * cvmx_ipd_red_que#_param 3251215976Sjmallett * 3252215976Sjmallett * IPD_RED_QUE0_PARAM = IPD RED Queue-0 Parameters 3253215976Sjmallett * 3254215976Sjmallett * Value control the Passing and Dropping of packets by the red engine for QOS Level-0. 3255215976Sjmallett */ 3256232812Sjmallettunion cvmx_ipd_red_quex_param { 3257215976Sjmallett uint64_t u64; 3258232812Sjmallett struct cvmx_ipd_red_quex_param_s { 3259232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3260215976Sjmallett uint64_t reserved_49_63 : 15; 3261215976Sjmallett uint64_t use_pcnt : 1; /**< When set '1' red will use the actual Packet-Page 3262215976Sjmallett Count in place of the Average for RED calculations. */ 3263215976Sjmallett uint64_t new_con : 8; /**< This value is used control how much of the present 3264215976Sjmallett Actual Queue Size is used to calculate the new 3265215976Sjmallett Average Queue Size. The value is a number from 0 3266215976Sjmallett 256, which represents NEW_CON/256 of the Actual 3267215976Sjmallett Queue Size that will be used in the calculation. 3268215976Sjmallett The number in this field plus the value of 3269215976Sjmallett AVG_CON must be equal to 256. 3270215976Sjmallett Larger AVG_DLY values cause the moving averages 3271215976Sjmallett of ALL QOS levels to track changes in the actual 3272215976Sjmallett free space more slowly. Smaller NEW_CON (and 3273215976Sjmallett larger AVG_CON) values can have a similar effect, 3274215976Sjmallett but only affect an individual QOS level, rather 3275215976Sjmallett than all. */ 3276215976Sjmallett uint64_t avg_con : 8; /**< This value is used control how much of the present 3277215976Sjmallett Average Queue Size is used to calculate the new 3278215976Sjmallett Average Queue Size. The value is a number from 0 3279215976Sjmallett 256, which represents AVG_CON/256 of the Average 3280215976Sjmallett Queue Size that will be used in the calculation. 3281215976Sjmallett The number in this field plus the value of 3282215976Sjmallett NEW_CON must be equal to 256. 3283215976Sjmallett Larger AVG_DLY values cause the moving averages 3284215976Sjmallett of ALL QOS levels to track changes in the actual 3285215976Sjmallett free space more slowly. Smaller NEW_CON (and 3286215976Sjmallett larger AVG_CON) values can have a similar effect, 3287215976Sjmallett but only affect an individual QOS level, rather 3288215976Sjmallett than all. */ 3289215976Sjmallett uint64_t prb_con : 32; /**< Used in computing the probability of a packet being 3290215976Sjmallett passed or drop by the WRED engine. The field is 3291215976Sjmallett calculated to be (255 * 2^24)/(PASS-DROP). Where 3292215976Sjmallett PASS and DROP are the field from the 3293215976Sjmallett IPD_QOS0_RED_MARKS CSR. */ 3294215976Sjmallett#else 3295215976Sjmallett uint64_t prb_con : 32; 3296215976Sjmallett uint64_t avg_con : 8; 3297215976Sjmallett uint64_t new_con : 8; 3298215976Sjmallett uint64_t use_pcnt : 1; 3299215976Sjmallett uint64_t reserved_49_63 : 15; 3300215976Sjmallett#endif 3301215976Sjmallett } s; 3302215976Sjmallett struct cvmx_ipd_red_quex_param_s cn30xx; 3303215976Sjmallett struct cvmx_ipd_red_quex_param_s cn31xx; 3304215976Sjmallett struct cvmx_ipd_red_quex_param_s cn38xx; 3305215976Sjmallett struct cvmx_ipd_red_quex_param_s cn38xxp2; 3306215976Sjmallett struct cvmx_ipd_red_quex_param_s cn50xx; 3307215976Sjmallett struct cvmx_ipd_red_quex_param_s cn52xx; 3308215976Sjmallett struct cvmx_ipd_red_quex_param_s cn52xxp1; 3309215976Sjmallett struct cvmx_ipd_red_quex_param_s cn56xx; 3310215976Sjmallett struct cvmx_ipd_red_quex_param_s cn56xxp1; 3311215976Sjmallett struct cvmx_ipd_red_quex_param_s cn58xx; 3312215976Sjmallett struct cvmx_ipd_red_quex_param_s cn58xxp1; 3313232812Sjmallett struct cvmx_ipd_red_quex_param_s cn61xx; 3314215976Sjmallett struct cvmx_ipd_red_quex_param_s cn63xx; 3315215976Sjmallett struct cvmx_ipd_red_quex_param_s cn63xxp1; 3316232812Sjmallett struct cvmx_ipd_red_quex_param_s cn66xx; 3317232812Sjmallett struct cvmx_ipd_red_quex_param_s cn68xx; 3318232812Sjmallett struct cvmx_ipd_red_quex_param_s cn68xxp1; 3319232812Sjmallett struct cvmx_ipd_red_quex_param_s cnf71xx; 3320215976Sjmallett}; 3321215976Sjmalletttypedef union cvmx_ipd_red_quex_param cvmx_ipd_red_quex_param_t; 3322215976Sjmallett 3323215976Sjmallett/** 3324232812Sjmallett * cvmx_ipd_req_wgt 3325232812Sjmallett * 3326232812Sjmallett * IPD_REQ_WGT = IPD REQ weights 3327232812Sjmallett * 3328232812Sjmallett * There are 8 devices that can request to send packet traffic to the IPD. These weights are used for the Weighted Round Robin 3329232812Sjmallett * grant generated by the IPD to requestors. 3330232812Sjmallett */ 3331232812Sjmallettunion cvmx_ipd_req_wgt { 3332232812Sjmallett uint64_t u64; 3333232812Sjmallett struct cvmx_ipd_req_wgt_s { 3334232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3335232812Sjmallett uint64_t wgt7 : 8; /**< Weight for ILK REQ */ 3336232812Sjmallett uint64_t wgt6 : 8; /**< Weight for PKO REQ */ 3337232812Sjmallett uint64_t wgt5 : 8; /**< Weight for DPI REQ */ 3338232812Sjmallett uint64_t wgt4 : 8; /**< Weight for AGX4 REQ */ 3339232812Sjmallett uint64_t wgt3 : 8; /**< Weight for AGX3 REQ */ 3340232812Sjmallett uint64_t wgt2 : 8; /**< Weight for AGX2 REQ */ 3341232812Sjmallett uint64_t wgt1 : 8; /**< Weight for AGX1 REQ */ 3342232812Sjmallett uint64_t wgt0 : 8; /**< Weight for AGX0 REQ */ 3343232812Sjmallett#else 3344232812Sjmallett uint64_t wgt0 : 8; 3345232812Sjmallett uint64_t wgt1 : 8; 3346232812Sjmallett uint64_t wgt2 : 8; 3347232812Sjmallett uint64_t wgt3 : 8; 3348232812Sjmallett uint64_t wgt4 : 8; 3349232812Sjmallett uint64_t wgt5 : 8; 3350232812Sjmallett uint64_t wgt6 : 8; 3351232812Sjmallett uint64_t wgt7 : 8; 3352232812Sjmallett#endif 3353232812Sjmallett } s; 3354232812Sjmallett struct cvmx_ipd_req_wgt_s cn68xx; 3355232812Sjmallett}; 3356232812Sjmalletttypedef union cvmx_ipd_req_wgt cvmx_ipd_req_wgt_t; 3357232812Sjmallett 3358232812Sjmallett/** 3359215976Sjmallett * cvmx_ipd_sub_port_bp_page_cnt 3360215976Sjmallett * 3361215976Sjmallett * IPD_SUB_PORT_BP_PAGE_CNT = IPD Subtract Port Backpressure Page Count 3362215976Sjmallett * 3363215976Sjmallett * Will add the value to the indicated port count register, the number of pages supplied. The value added should 3364215976Sjmallett * be the 2's complement of the value that needs to be subtracted. Users add 2's complement values to the 3365215976Sjmallett * port-mbuf-count register to return (lower the count) mbufs to the counter in order to avoid port-level 3366215976Sjmallett * backpressure being applied to the port. Backpressure is applied when the MBUF used count of a port exceeds the 3367215976Sjmallett * value in the IPD_PORTX_BP_PAGE_CNT, IPD_PORTX_BP_PAGE_CNT2, and IPD_PORTX_BP_PAGE_CNT3. 3368215976Sjmallett * 3369215976Sjmallett * This register can't be written from the PCI via a window write. 3370215976Sjmallett */ 3371232812Sjmallettunion cvmx_ipd_sub_port_bp_page_cnt { 3372215976Sjmallett uint64_t u64; 3373232812Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s { 3374232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3375215976Sjmallett uint64_t reserved_31_63 : 33; 3376215976Sjmallett uint64_t port : 6; /**< The port to add the PAGE_CNT field to. */ 3377215976Sjmallett uint64_t page_cnt : 25; /**< The number of page pointers to add to 3378215976Sjmallett the port counter pointed to by the 3379215976Sjmallett PORT Field. */ 3380215976Sjmallett#else 3381215976Sjmallett uint64_t page_cnt : 25; 3382215976Sjmallett uint64_t port : 6; 3383215976Sjmallett uint64_t reserved_31_63 : 33; 3384215976Sjmallett#endif 3385215976Sjmallett } s; 3386215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx; 3387215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx; 3388215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xx; 3389215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xxp2; 3390215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn50xx; 3391215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xx; 3392215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xxp1; 3393215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xx; 3394215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1; 3395215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx; 3396215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1; 3397232812Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn61xx; 3398215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xx; 3399215976Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xxp1; 3400232812Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn66xx; 3401232812Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn68xx; 3402232812Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cn68xxp1; 3403232812Sjmallett struct cvmx_ipd_sub_port_bp_page_cnt_s cnf71xx; 3404215976Sjmallett}; 3405215976Sjmalletttypedef union cvmx_ipd_sub_port_bp_page_cnt cvmx_ipd_sub_port_bp_page_cnt_t; 3406215976Sjmallett 3407215976Sjmallett/** 3408215976Sjmallett * cvmx_ipd_sub_port_fcs 3409215976Sjmallett * 3410215976Sjmallett * IPD_SUB_PORT_FCS = IPD Subtract Ports FCS Register 3411215976Sjmallett * 3412215976Sjmallett * When set '1' the port corresponding to the bit set will subtract 4 bytes from the end of 3413215976Sjmallett * the packet. 3414215976Sjmallett */ 3415232812Sjmallettunion cvmx_ipd_sub_port_fcs { 3416215976Sjmallett uint64_t u64; 3417232812Sjmallett struct cvmx_ipd_sub_port_fcs_s { 3418232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3419215976Sjmallett uint64_t reserved_40_63 : 24; 3420215976Sjmallett uint64_t port_bit2 : 4; /**< When set '1', the port corresponding to the bit 3421215976Sjmallett position set, will subtract the FCS for packets 3422215976Sjmallett on that port. */ 3423215976Sjmallett uint64_t reserved_32_35 : 4; 3424215976Sjmallett uint64_t port_bit : 32; /**< When set '1', the port corresponding to the bit 3425215976Sjmallett position set, will subtract the FCS for packets 3426215976Sjmallett on that port. */ 3427215976Sjmallett#else 3428215976Sjmallett uint64_t port_bit : 32; 3429215976Sjmallett uint64_t reserved_32_35 : 4; 3430215976Sjmallett uint64_t port_bit2 : 4; 3431215976Sjmallett uint64_t reserved_40_63 : 24; 3432215976Sjmallett#endif 3433215976Sjmallett } s; 3434232812Sjmallett struct cvmx_ipd_sub_port_fcs_cn30xx { 3435232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3436215976Sjmallett uint64_t reserved_3_63 : 61; 3437215976Sjmallett uint64_t port_bit : 3; /**< When set '1', the port corresponding to the bit 3438215976Sjmallett position set, will subtract the FCS for packets 3439215976Sjmallett on that port. */ 3440215976Sjmallett#else 3441215976Sjmallett uint64_t port_bit : 3; 3442215976Sjmallett uint64_t reserved_3_63 : 61; 3443215976Sjmallett#endif 3444215976Sjmallett } cn30xx; 3445215976Sjmallett struct cvmx_ipd_sub_port_fcs_cn30xx cn31xx; 3446232812Sjmallett struct cvmx_ipd_sub_port_fcs_cn38xx { 3447232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3448215976Sjmallett uint64_t reserved_32_63 : 32; 3449215976Sjmallett uint64_t port_bit : 32; /**< When set '1', the port corresponding to the bit 3450215976Sjmallett position set, will subtract the FCS for packets 3451215976Sjmallett on that port. */ 3452215976Sjmallett#else 3453215976Sjmallett uint64_t port_bit : 32; 3454215976Sjmallett uint64_t reserved_32_63 : 32; 3455215976Sjmallett#endif 3456215976Sjmallett } cn38xx; 3457215976Sjmallett struct cvmx_ipd_sub_port_fcs_cn38xx cn38xxp2; 3458215976Sjmallett struct cvmx_ipd_sub_port_fcs_cn30xx cn50xx; 3459215976Sjmallett struct cvmx_ipd_sub_port_fcs_s cn52xx; 3460215976Sjmallett struct cvmx_ipd_sub_port_fcs_s cn52xxp1; 3461215976Sjmallett struct cvmx_ipd_sub_port_fcs_s cn56xx; 3462215976Sjmallett struct cvmx_ipd_sub_port_fcs_s cn56xxp1; 3463215976Sjmallett struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx; 3464215976Sjmallett struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1; 3465232812Sjmallett struct cvmx_ipd_sub_port_fcs_s cn61xx; 3466215976Sjmallett struct cvmx_ipd_sub_port_fcs_s cn63xx; 3467215976Sjmallett struct cvmx_ipd_sub_port_fcs_s cn63xxp1; 3468232812Sjmallett struct cvmx_ipd_sub_port_fcs_s cn66xx; 3469232812Sjmallett struct cvmx_ipd_sub_port_fcs_s cnf71xx; 3470215976Sjmallett}; 3471215976Sjmalletttypedef union cvmx_ipd_sub_port_fcs cvmx_ipd_sub_port_fcs_t; 3472215976Sjmallett 3473215976Sjmallett/** 3474215976Sjmallett * cvmx_ipd_sub_port_qos_cnt 3475215976Sjmallett * 3476215976Sjmallett * IPD_SUB_PORT_QOS_CNT = IPD Subtract Port QOS Count 3477215976Sjmallett * 3478215976Sjmallett * Will add the value (CNT) to the indicated Port-QOS register (PORT_QOS). The value added must be 3479215976Sjmallett * be the 2's complement of the value that needs to be subtracted. 3480215976Sjmallett */ 3481232812Sjmallettunion cvmx_ipd_sub_port_qos_cnt { 3482215976Sjmallett uint64_t u64; 3483232812Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s { 3484232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3485215976Sjmallett uint64_t reserved_41_63 : 23; 3486215976Sjmallett uint64_t port_qos : 9; /**< The port to add the CNT field to. */ 3487215976Sjmallett uint64_t cnt : 32; /**< The value to be added to the register selected 3488215976Sjmallett in the PORT_QOS field. */ 3489215976Sjmallett#else 3490215976Sjmallett uint64_t cnt : 32; 3491215976Sjmallett uint64_t port_qos : 9; 3492215976Sjmallett uint64_t reserved_41_63 : 23; 3493215976Sjmallett#endif 3494215976Sjmallett } s; 3495215976Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cn52xx; 3496215976Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1; 3497215976Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cn56xx; 3498215976Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1; 3499232812Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cn61xx; 3500215976Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cn63xx; 3501215976Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cn63xxp1; 3502232812Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cn66xx; 3503232812Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cn68xx; 3504232812Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cn68xxp1; 3505232812Sjmallett struct cvmx_ipd_sub_port_qos_cnt_s cnf71xx; 3506215976Sjmallett}; 3507215976Sjmalletttypedef union cvmx_ipd_sub_port_qos_cnt cvmx_ipd_sub_port_qos_cnt_t; 3508215976Sjmallett 3509215976Sjmallett/** 3510215976Sjmallett * cvmx_ipd_wqe_fpa_queue 3511215976Sjmallett * 3512215976Sjmallett * IPD_WQE_FPA_QUEUE = IPD Work-Queue-Entry FPA Page Size 3513215976Sjmallett * 3514215976Sjmallett * Which FPA Queue (0-7) to fetch page-pointers from for WQE's 3515215976Sjmallett */ 3516232812Sjmallettunion cvmx_ipd_wqe_fpa_queue { 3517215976Sjmallett uint64_t u64; 3518232812Sjmallett struct cvmx_ipd_wqe_fpa_queue_s { 3519232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3520215976Sjmallett uint64_t reserved_3_63 : 61; 3521215976Sjmallett uint64_t wqe_pool : 3; /**< Which FPA Queue to fetch page-pointers 3522215976Sjmallett from for WQE's. 3523215976Sjmallett Not used when IPD_CTL_STATUS[NO_WPTR] is set. */ 3524215976Sjmallett#else 3525215976Sjmallett uint64_t wqe_pool : 3; 3526215976Sjmallett uint64_t reserved_3_63 : 61; 3527215976Sjmallett#endif 3528215976Sjmallett } s; 3529215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn30xx; 3530215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn31xx; 3531215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn38xx; 3532215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn38xxp2; 3533215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn50xx; 3534215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn52xx; 3535215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn52xxp1; 3536215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn56xx; 3537215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1; 3538215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn58xx; 3539215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1; 3540232812Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn61xx; 3541215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn63xx; 3542215976Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn63xxp1; 3543232812Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn66xx; 3544232812Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn68xx; 3545232812Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cn68xxp1; 3546232812Sjmallett struct cvmx_ipd_wqe_fpa_queue_s cnf71xx; 3547215976Sjmallett}; 3548215976Sjmalletttypedef union cvmx_ipd_wqe_fpa_queue cvmx_ipd_wqe_fpa_queue_t; 3549215976Sjmallett 3550215976Sjmallett/** 3551215976Sjmallett * cvmx_ipd_wqe_ptr_valid 3552215976Sjmallett * 3553215976Sjmallett * IPD_WQE_PTR_VALID = IPD's WQE Pointer Valid 3554215976Sjmallett * 3555215976Sjmallett * The value of the WQE-pointer fetched and in the valid register. 3556215976Sjmallett */ 3557232812Sjmallettunion cvmx_ipd_wqe_ptr_valid { 3558215976Sjmallett uint64_t u64; 3559232812Sjmallett struct cvmx_ipd_wqe_ptr_valid_s { 3560232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3561215976Sjmallett uint64_t reserved_29_63 : 35; 3562215976Sjmallett uint64_t ptr : 29; /**< Pointer value. 3563215976Sjmallett When IPD_CTL_STATUS[NO_WPTR] is set '1' this field 3564215976Sjmallett represents a Packet-Pointer NOT a WQE pointer. */ 3565215976Sjmallett#else 3566215976Sjmallett uint64_t ptr : 29; 3567215976Sjmallett uint64_t reserved_29_63 : 35; 3568215976Sjmallett#endif 3569215976Sjmallett } s; 3570215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn30xx; 3571215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn31xx; 3572215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn38xx; 3573215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn50xx; 3574215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn52xx; 3575215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn52xxp1; 3576215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn56xx; 3577215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1; 3578215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn58xx; 3579215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1; 3580232812Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn61xx; 3581215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn63xx; 3582215976Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn63xxp1; 3583232812Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cn66xx; 3584232812Sjmallett struct cvmx_ipd_wqe_ptr_valid_s cnf71xx; 3585215976Sjmallett}; 3586215976Sjmalletttypedef union cvmx_ipd_wqe_ptr_valid cvmx_ipd_wqe_ptr_valid_t; 3587215976Sjmallett 3588215976Sjmallett#endif 3589