cvmx-higig.h revision 215990
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THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * Functions and typedefs for using Octeon in HiGig/HiGig+/HiGig2 mode over 50 * XAUI. 51 * 52 * <hr>$Revision: 49448 $<hr> 53 */ 54 55#ifndef __CVMX_HIGIG_H__ 56#define __CVMX_HIGIG_H__ 57#include "cvmx-wqe.h" 58 59#ifdef __cplusplus 60extern "C" { 61#endif 62 63typedef struct 64{ 65 union 66 { 67 uint32_t u32; 68 struct 69 { 70 uint32_t start : 8; /**< 8-bits of Preamble indicating start of frame */ 71 uint32_t dst_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of 72 DST_MODID (bits 4:0 are in Byte 7 and bit 5 is in Byte 9). ). For HGI field 73 value of b'01' this field should be b'1'. For all other values of HGI it is don't 74 care. */ 75 uint32_t src_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of 76 SRC_MODID (bits 4:0 are in Byte 4 and bit 5 is in Byte 9). For HGI field 77 value of b'01' this field should be b'0'. For all other values of HGI it is don't 78 care. */ 79 uint32_t hdr_ext_len : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension 80 to the standard 12-bytes of XGS HiGig header. Each unit represents 4 81 bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110' 82 and b'111' are reserved. For HGI field value of b'01' this field should be 83 b'01'. For all other values of HGI it is don't care. */ 84 uint32_t cng_high : 1; /**< Congestion Bit High flag */ 85 uint32_t hgi : 2; /**< HiGig interface format indicator 86 00 = Reserved 87 01 = Pure preamble - IEEE standard framing of 10GE 88 10 = XGS header - framing based on XGS family definition In this 89 format, the default length of the header is 12 bytes and additional 90 bytes are indicated by the HDR_EXT_LEN field 91 11 = Reserved */ 92 uint32_t vid_high : 8; /**< 8-bits of the VLAN tag information */ 93 uint32_t vid_low : 8; /**< 8 bits LSB of the VLAN tag information */ 94 } s; 95 } dw0; 96 union 97 { 98 uint32_t u32; 99 struct 100 { 101 uint32_t opcode : 3; /**< XGS HiGig op-code, indicating the type of packet 102 000 = Control frames used for CPU to CPU communications 103 001 = Unicast packet with destination resolved; The packet can be 104 either Layer 2 unicast packet or L3 unicast packet that was 105 routed in the ingress chip. 106 010 = Broadcast or unknown Unicast packet or unknown multicast, 107 destined to all members of the VLAN 108 011 = L2 Multicast packet, destined to all ports of the group indicated 109 in the L2MC_INDEX which is overlayed on DST_PORT/DST_MODID fields 110 100 = IP Multicast packet, destined to all ports of the group indicated 111 in the IPMC_INDEX which is overlayed on DST_PORT/DST_MODID fields 112 101 = Reserved 113 110 = Reserved 114 111 = Reserved */ 115 uint32_t src_modid_low : 5; /**< Bits 4:0 of Module ID of the source module on which the packet ingress (bit 116 5 is in Byte 9 and bit 6 Is in Byte 1) */ 117 uint32_t src_port_tgid : 6; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed 118 on, else it represents the physical port the packet ingressed on. */ 119 uint32_t pfm : 2; /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered 120 multicast (unknown L2 multicast and IPMC) packets. This field is used 121 when OPCODE is 011 or 100 Semantics of PFM bits are as follows; 122 For registered L2 multicast packets: 123 PFM= 0 � Flood to VLAN 124 PFM= 1 or 2 � Send to group members in the L2MC table 125 For unregistered L2 multicast packets: 126 PFM= 0 or 1 � Flood to VLAN 127 PFM= 2 � Drop the packet */ 128 uint32_t priority : 3; /**< This is the internal priority of the packet. This internal priority will go through 129 COS_SEL mapping registers to map to the actual MMU queues. */ 130 uint32_t dst_port : 5; /**< Port number of destination port on which the packet needs to egress. */ 131 uint32_t dst_modid_low : 5; /**< Bits [4-: 0] of Module ID of the destination port on which the packet needs to egress. */ 132 uint32_t cng_low : 1; /**< Semantics of CNG_HIGH and CNG_LOW are as follows: The following 133 encodings are to make it backward compatible: 134 {CNG_HIGH, CNG_LOW] - COLOR 135 [0, 0] � Packet is green 136 [0, 1] � Packet is red 137 [1, 1] � Packet is yellow 138 [1, 0] � Undefined */ 139 uint32_t header_type : 2; /**< Indicates the format of the next 4 bytes of the XGS HiGig header 140 00 = Overlay 1 (default) 141 01 = Overlay 2 (Classification Tag) 142 10 = Reserved 143 11 = Reserved */ 144 } s; 145 } dw1; 146 union 147 { 148 uint32_t u32; 149 struct 150 { 151 uint32_t mirror : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the 152 packet was switched and only needs to be mirrored. */ 153 uint32_t mirror_done : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and 154 may still need to be switched. */ 155 uint32_t mirror_only : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only 156 needs to be mirrored. */ 157 uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally 158 ingressed the system. */ 159 uint32_t dst_tgid : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The 160 DO_NOT_LEARN bit is overlaid on the second bit of this field. */ 161 uint32_t dst_t : 1; /**< Destination Trunk: Indicates that the destination port is a member of a trunk 162 group. */ 163 uint32_t vc_label_16_19 : 4; /**< VC Label: Bits 19:16 of VC label: HiGig+ added field */ 164 uint32_t label_present : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+ 165 added field. */ 166 uint32_t l3 : 1; /**< L3: Indicates that the packet is L3 switched */ 167 uint32_t dst_modid_5 : 1; /**< Destination Module ID: Bit 5 of Dst_ModID (bits 4:0 are in byte 7 and bit 6 168 is in byte 1) */ 169 uint32_t src_modid_5 : 1; /**< Source Module ID: Bit 5 of Src_ModID (bits 4:0 are in byte 4 and bit 6 is in 170 byte 1) */ 171 uint32_t vc_label_0_15 : 16;/**< VC Label: Bits 15:0 of VC label: HiGig+ added field */ 172 } o1; 173 struct 174 { 175 uint32_t classification : 16; /**< Classification tag information from the HiGig device FFP */ 176 uint32_t reserved_0_15 : 16; 177 178 } o2; 179 } dw2; 180} cvmx_higig_header_t; 181 182typedef struct 183{ 184 union 185 { 186 uint32_t u32; 187 struct 188 { 189 uint32_t k_sop : 8; /**< The delimiter indicating the start of a packet transmission */ 190 uint32_t reserved_21_23 : 3; 191 uint32_t mcst : 1; /**< MCST indicates whether the packet should be unicast or 192 multicast forwarded through the XGS switching fabric 193 - 0: Unicast 194 - 1: Mulitcast */ 195 uint32_t tc : 4; /**< Traffic Class [3:0] indicates the distinctive Quality of Service (QoS) 196 the switching fabric will provide when forwarding the packet 197 through the fabric */ 198 uint32_t dst_modid_mgid : 8; /**< When MCST=0, this field indicates the destination XGS module to 199 which the packet will be delivered. When MCST=1, this field indicates 200 higher order bits of the Multicast Group ID. */ 201 uint32_t dst_pid_mgid : 8; /**< When MCST=0, this field indicates a port associated with the 202 module indicated by the DST_MODID, through which the packet 203 will exit the system. When MCST=1, this field indicates lower order 204 bits of the Multicast Group ID */ 205 } s; 206 } dw0; 207 union 208 { 209 uint32_t u32; 210 struct 211 { 212 uint32_t src_modid : 8; /**< Source Module ID indicates the source XGS module from which 213 the packet is originated. (It can also be used for the fabric multicast 214 load balancing purpose.) */ 215 uint32_t src_pid : 8; /**< Source Port ID indicates a port associated with the module 216 indicated by the SRC_MODID, through which the packet has 217 entered the system */ 218 uint32_t lbid : 8; /**< Load Balancing ID indicates a packet flow hashing index 219 computed by the ingress XGS module for statistical distribution of 220 packet flows through a multipath fabric */ 221 uint32_t dp : 2; /**< Drop Precedence indicates the traffic rate violation status of the 222 packet measured by the ingress module. 223 - 00: GREEN 224 - 01: RED 225 - 10: Reserved 226 - 11: Yellow */ 227 uint32_t reserved_3_5 : 3; 228 uint32_t ppd_type : 3; /**< Packet Processing Descriptor Type 229 - 000: PPD Overlay1 230 - 001: PPD Overlay2 231 - 010~111: Reserved */ 232 } s; 233 } dw1; 234 union 235 { 236 uint32_t u32; 237 struct 238 { 239 uint32_t dst_t : 1; /**< Destination Trunk: Indicates that the destination port is a member of a trunk 240 group. */ 241 uint32_t dst_tgid : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The 242 DO_NOT_LEARN bit is overlaid on the second bit of this field. */ 243 uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally 244 ingressed the system. */ 245 uint32_t mirror_only : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only 246 needs to be mirrored. */ 247 uint32_t mirror_done : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and 248 may still need to be switched. */ 249 uint32_t mirror : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the 250 packet was switched and only needs to be mirrored. */ 251 uint32_t reserved_22_23 : 2; 252 uint32_t l3 : 1; /**< L3: Indicates that the packet is L3 switched */ 253 uint32_t label_present : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+ 254 added field. */ 255 uint32_t vc_label : 20; /**< Refer to the HiGig+ Architecture Specification */ 256 } o1; 257 struct 258 { 259 uint32_t classification : 16; /**< Classification tag information from the HiGig device FFP */ 260 uint32_t reserved_0_15 : 16; 261 } o2; 262 } dw2; 263 union 264 { 265 uint32_t u32; 266 struct 267 { 268 uint32_t vid : 16; /**< VLAN tag information */ 269 uint32_t pfm : 2; /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered 270 multicast (unknown L2 multicast and IPMC) packets. This field is used 271 when OPCODE is 011 or 100 Semantics of PFM bits are as follows; 272 For registered L2 multicast packets: 273 PFM= 0 � Flood to VLAN 274 PFM= 1 or 2 � Send to group members in the L2MC table 275 For unregistered L2 multicast packets: 276 PFM= 0 or 1 � Flood to VLAN 277 PFM= 2 � Drop the packet */ 278 uint32_t src_t : 1; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed 279 on, else it represents the physical port the packet ingressed on. */ 280 uint32_t reserved_11_12 : 2; 281 uint32_t opcode : 3; /**< XGS HiGig op-code, indicating the type of packet 282 000 = Control frames used for CPU to CPU communications 283 001 = Unicast packet with destination resolved; The packet can be 284 either Layer 2 unicast packet or L3 unicast packet that was 285 routed in the ingress chip. 286 010 = Broadcast or unknown Unicast packet or unknown multicast, 287 destined to all members of the VLAN 288 011 = L2 Multicast packet, destined to all ports of the group indicated 289 in the L2MC_INDEX which is overlayed on DST_PORT/DST_MODID fields 290 100 = IP Multicast packet, destined to all ports of the group indicated 291 in the IPMC_INDEX which is overlayed on DST_PORT/DST_MODID fields 292 101 = Reserved 293 110 = Reserved 294 111 = Reserved */ 295 uint32_t hdr_ext_len : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension 296 to the standard 12-bytes of XGS HiGig header. Each unit represents 4 297 bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110' 298 and b'111' are reserved. For HGI field value of b'01' this field should be 299 b'01'. For all other values of HGI it is don't care. */ 300 uint32_t reserved_0_4 : 5; 301 } s; 302 } dw3; 303} cvmx_higig2_header_t; 304 305 306/** 307 * Initialize the HiGig aspects of a XAUI interface. This function 308 * should be called before the cvmx-helper generic init. 309 * 310 * @param interface Interface to initialize HiGig on (0-1) 311 * @param enable_higig2 312 * Non zero to enable HiGig2 support. Zero to support HiGig 313 * and HiGig+. 314 * 315 * @return Zero on success, negative on failure 316 */ 317static inline int cvmx_higig_initialize(int interface, int enable_higig2) 318{ 319 cvmx_pip_prt_cfgx_t pip_prt_cfg; 320 cvmx_gmxx_rxx_udd_skp_t gmx_rx_udd_skp; 321 cvmx_gmxx_txx_min_pkt_t gmx_tx_min_pkt; 322 cvmx_gmxx_txx_append_t gmx_tx_append; 323 cvmx_gmxx_tx_ifg_t gmx_tx_ifg; 324 cvmx_gmxx_tx_ovr_bp_t gmx_tx_ovr_bp; 325 cvmx_gmxx_rxx_frm_ctl_t gmx_rx_frm_ctl; 326 cvmx_gmxx_tx_xaui_ctl_t gmx_tx_xaui_ctl; 327 int i; 328 int header_size = (enable_higig2) ? 16 : 12; 329 330 /* Setup PIP to handle HiGig */ 331 pip_prt_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(interface*16)); 332 pip_prt_cfg.s.dsa_en = 0; 333 pip_prt_cfg.s.higig_en = 1; 334 pip_prt_cfg.s.hg_qos = 1; 335 pip_prt_cfg.s.skip = header_size; 336 cvmx_write_csr(CVMX_PIP_PRT_CFGX(interface*16), pip_prt_cfg.u64); 337 338 /* Setup some sample QoS defaults. These can be changed later */ 339 for (i=0; i<64; i++) 340 { 341 cvmx_pip_hg_pri_qos_t pip_hg_pri_qos; 342 pip_hg_pri_qos.u64 = 0; 343 pip_hg_pri_qos.s.up_qos = 1; 344 pip_hg_pri_qos.s.pri = i; 345 pip_hg_pri_qos.s.qos = i&7; 346 cvmx_write_csr(CVMX_PIP_HG_PRI_QOS, pip_hg_pri_qos.u64); 347 } 348 349 /* Setup GMX RX to treat the HiGig header as user data to ignore */ 350 gmx_rx_udd_skp.u64 = cvmx_read_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface)); 351 gmx_rx_udd_skp.s.len = header_size; 352 gmx_rx_udd_skp.s.fcssel = 0; 353 cvmx_write_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface), gmx_rx_udd_skp.u64); 354 355 /* Disable GMX preamble checking */ 356 gmx_rx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface)); 357 gmx_rx_frm_ctl.s.pre_chk = 0; 358 cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface), gmx_rx_frm_ctl.u64); 359 360 /* Setup GMX TX to pad properly min sized packets */ 361 gmx_tx_min_pkt.u64 = cvmx_read_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface)); 362 gmx_tx_min_pkt.s.min_size = 59 + header_size; 363 cvmx_write_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface), gmx_tx_min_pkt.u64); 364 365 /* Setup GMX TX to not add a preamble */ 366 gmx_tx_append.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(0, interface)); 367 gmx_tx_append.s.preamble = 0; 368 cvmx_write_csr(CVMX_GMXX_TXX_APPEND(0, interface), gmx_tx_append.u64); 369 370 /* Reduce the inter frame gap to 8 bytes */ 371 gmx_tx_ifg.u64 = cvmx_read_csr(CVMX_GMXX_TX_IFG(interface)); 372 gmx_tx_ifg.s.ifg1 = 4; 373 gmx_tx_ifg.s.ifg2 = 4; 374 cvmx_write_csr(CVMX_GMXX_TX_IFG(interface), gmx_tx_ifg.u64); 375 376 /* Disable GMX backpressure */ 377 gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface)); 378 gmx_tx_ovr_bp.s.bp = 0; 379 gmx_tx_ovr_bp.s.en = 0xf; 380 gmx_tx_ovr_bp.s.ign_full = 0xf; 381 cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64); 382 383 if (enable_higig2) 384 { 385 /* Enable HiGig2 support and forwarding of virtual port backpressure 386 to PKO */ 387 cvmx_gmxx_hg2_control_t gmx_hg2_control; 388 gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); 389 gmx_hg2_control.s.hg2rx_en = 1; 390 gmx_hg2_control.s.hg2tx_en = 1; 391 gmx_hg2_control.s.logl_en = 0xffff; 392 gmx_hg2_control.s.phys_en = 1; 393 cvmx_write_csr(CVMX_GMXX_HG2_CONTROL(interface), gmx_hg2_control.u64); 394 } 395 396 /* Enable HiGig */ 397 gmx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); 398 gmx_tx_xaui_ctl.s.hg_en = 1; 399 cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmx_tx_xaui_ctl.u64); 400 401 return 0; 402} 403 404#ifdef __cplusplus 405} 406#endif 407 408#endif // __CVMX_HIGIG_H__ 409