cvmx-higig.h revision 210284
1189251Ssam/***********************license start*************** 2189251Ssam * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3189251Ssam * reserved. 4189251Ssam * 5252726Srpaulo * 6252726Srpaulo * Redistribution and use in source and binary forms, with or without 7189251Ssam * modification, are permitted provided that the following conditions are 8189251Ssam * met: 9189251Ssam * 10189251Ssam * * Redistributions of source code must retain the above copyright 11189251Ssam * notice, this list of conditions and the following disclaimer. 12189251Ssam * 13189251Ssam * * Redistributions in binary form must reproduce the above 14189251Ssam * copyright notice, this list of conditions and the following 15189251Ssam * disclaimer in the documentation and/or other materials provided 16189251Ssam * with the distribution. 17189251Ssam * 18189251Ssam * * Neither the name of Cavium Networks nor the names of 19189251Ssam * its contributors may be used to endorse or promote products 20189251Ssam * derived from this software without specific prior written 21189251Ssam * permission. 22189251Ssam * 23189251Ssam * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24189251Ssam * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25189251Ssam * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26189251Ssam * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27189251Ssam * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28189251Ssam * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29189251Ssam * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30189251Ssam * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31189251Ssam * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32189251Ssam * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33189251Ssam * 34189251Ssam * 35252726Srpaulo * For any questions regarding licensing please contact marketing@caviumnetworks.com 36189251Ssam * 37189251Ssam ***********************license end**************************************/ 38189251Ssam 39189251Ssam 40189251Ssam 41189251Ssam 42189251Ssam 43189251Ssam 44189251Ssam/** 45189251Ssam * @file 46189251Ssam * 47189251Ssam * Functions and typedefs for using Octeon in HiGig/HiGig+/HiGig2 mode over 48189251Ssam * XAUI. 49189251Ssam * 50189251Ssam * <hr>$Revision: 41586 $<hr> 51189251Ssam */ 52189251Ssam 53189251Ssam#ifndef __CVMX_HIGIG_H__ 54252726Srpaulo#define __CVMX_HIGIG_H__ 55252726Srpaulo#include "cvmx-wqe.h" 56252726Srpaulo 57252726Srpaulo#ifdef __cplusplus 58189251Ssamextern "C" { 59189251Ssam#endif 60189251Ssam 61189251Ssamtypedef struct 62189251Ssam{ 63189251Ssam union 64189251Ssam { 65189251Ssam uint32_t u32; 66189251Ssam struct 67189251Ssam { 68189251Ssam uint32_t start : 8; /**< 8-bits of Preamble indicating start of frame */ 69189251Ssam uint32_t dst_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of 70252726Srpaulo DST_MODID (bits 4:0 are in Byte 7 and bit 5 is in Byte 9). ). For HGI field 71252726Srpaulo value of b'01' this field should be b'1'. For all other values of HGI it is don't 72189251Ssam care. */ 73189251Ssam uint32_t src_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of 74189251Ssam SRC_MODID (bits 4:0 are in Byte 4 and bit 5 is in Byte 9). For HGI field 75189251Ssam value of b'01' this field should be b'0'. For all other values of HGI it is don't 76189251Ssam care. */ 77189251Ssam uint32_t hdr_ext_len : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension 78189251Ssam to the standard 12-bytes of XGS HiGig header. Each unit represents 4 79189251Ssam bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110' 80189251Ssam and b'111' are reserved. For HGI field value of b'01' this field should be 81189251Ssam b'01'. For all other values of HGI it is don't care. */ 82189251Ssam uint32_t cng_high : 1; /**< Congestion Bit High flag */ 83189251Ssam uint32_t hgi : 2; /**< HiGig interface format indicator 84189251Ssam 00 = Reserved 85189251Ssam 01 = Pure preamble - IEEE standard framing of 10GE 86189251Ssam 10 = XGS header - framing based on XGS family definition In this 87189251Ssam format, the default length of the header is 12 bytes and additional 88189251Ssam bytes are indicated by the HDR_EXT_LEN field 89189251Ssam 11 = Reserved */ 90189251Ssam uint32_t vid_high : 8; /**< 8-bits of the VLAN tag information */ 91252726Srpaulo uint32_t vid_low : 8; /**< 8 bits LSB of the VLAN tag information */ 92252726Srpaulo } s; 93252726Srpaulo } dw0; 94189251Ssam union 95189251Ssam { 96189251Ssam uint32_t u32; 97189251Ssam struct 98189251Ssam { 99189251Ssam uint32_t opcode : 3; /**< XGS HiGig op-code, indicating the type of packet 100189251Ssam 000 = Control frames used for CPU to CPU communications 101189251Ssam 001 = Unicast packet with destination resolved; The packet can be 102189251Ssam either Layer 2 unicast packet or L3 unicast packet that was 103189251Ssam routed in the ingress chip. 104189251Ssam 010 = Broadcast or unknown Unicast packet or unknown multicast, 105189251Ssam destined to all members of the VLAN 106189251Ssam 011 = L2 Multicast packet, destined to all ports of the group indicated 107189251Ssam in the L2MC_INDEX which is overlayed on DST_PORT/DST_MODID fields 108189251Ssam 100 = IP Multicast packet, destined to all ports of the group indicated 109189251Ssam in the IPMC_INDEX which is overlayed on DST_PORT/DST_MODID fields 110189251Ssam 101 = Reserved 111189251Ssam 110 = Reserved 112189251Ssam 111 = Reserved */ 113189251Ssam uint32_t src_modid_low : 5; /**< Bits 4:0 of Module ID of the source module on which the packet ingress (bit 114189251Ssam 5 is in Byte 9 and bit 6 Is in Byte 1) */ 115189251Ssam uint32_t src_port_tgid : 6; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed 116189251Ssam on, else it represents the physical port the packet ingressed on. */ 117189251Ssam uint32_t pfm : 2; /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered 118189251Ssam multicast (unknown L2 multicast and IPMC) packets. This field is used 119189251Ssam when OPCODE is 011 or 100 Semantics of PFM bits are as follows; 120189251Ssam For registered L2 multicast packets: 121189251Ssam PFM= 0 � Flood to VLAN 122252726Srpaulo PFM= 1 or 2 � Send to group members in the L2MC table 123189251Ssam For unregistered L2 multicast packets: 124252726Srpaulo PFM= 0 or 1 � Flood to VLAN 125252726Srpaulo PFM= 2 � Drop the packet */ 126252726Srpaulo uint32_t priority : 3; /**< This is the internal priority of the packet. This internal priority will go through 127252726Srpaulo COS_SEL mapping registers to map to the actual MMU queues. */ 128252726Srpaulo uint32_t dst_port : 5; /**< Port number of destination port on which the packet needs to egress. */ 129189251Ssam uint32_t dst_modid_low : 5; /**< Bits [4-: 0] of Module ID of the destination port on which the packet needs to egress. */ 130189251Ssam uint32_t cng_low : 1; /**< Semantics of CNG_HIGH and CNG_LOW are as follows: The following 131189251Ssam encodings are to make it backward compatible: 132189251Ssam {CNG_HIGH, CNG_LOW] - COLOR 133189251Ssam [0, 0] � Packet is green 134189251Ssam [0, 1] � Packet is red 135189251Ssam [1, 1] � Packet is yellow 136189251Ssam [1, 0] � Undefined */ 137189251Ssam uint32_t header_type : 2; /**< Indicates the format of the next 4 bytes of the XGS HiGig header 138189251Ssam 00 = Overlay 1 (default) 139189251Ssam 01 = Overlay 2 (Classification Tag) 140189251Ssam 10 = Reserved 141189251Ssam 11 = Reserved */ 142189251Ssam } s; 143189251Ssam } dw1; 144189251Ssam union 145189251Ssam { 146189251Ssam uint32_t u32; 147189251Ssam struct 148189251Ssam { 149189251Ssam uint32_t mirror : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the 150189251Ssam packet was switched and only needs to be mirrored. */ 151189251Ssam uint32_t mirror_done : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and 152189251Ssam may still need to be switched. */ 153189251Ssam uint32_t mirror_only : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only 154189251Ssam needs to be mirrored. */ 155189251Ssam uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally 156189251Ssam ingressed the system. */ 157189251Ssam uint32_t dst_tgid : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The 158189251Ssam DO_NOT_LEARN bit is overlaid on the second bit of this field. */ 159189251Ssam uint32_t dst_t : 1; /**< Destination Trunk: Indicates that the destination port is a member of a trunk 160189251Ssam group. */ 161189251Ssam uint32_t vc_label_16_19 : 4; /**< VC Label: Bits 19:16 of VC label: HiGig+ added field */ 162189251Ssam uint32_t label_present : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+ 163189251Ssam added field. */ 164189251Ssam uint32_t l3 : 1; /**< L3: Indicates that the packet is L3 switched */ 165189251Ssam uint32_t dst_modid_5 : 1; /**< Destination Module ID: Bit 5 of Dst_ModID (bits 4:0 are in byte 7 and bit 6 166189251Ssam is in byte 1) */ 167189251Ssam uint32_t src_modid_5 : 1; /**< Source Module ID: Bit 5 of Src_ModID (bits 4:0 are in byte 4 and bit 6 is in 168189251Ssam byte 1) */ 169189251Ssam uint32_t vc_label_0_15 : 16;/**< VC Label: Bits 15:0 of VC label: HiGig+ added field */ 170189251Ssam } o1; 171189251Ssam struct 172189251Ssam { 173189251Ssam uint32_t classification : 16; /**< Classification tag information from the HiGig device FFP */ 174189251Ssam uint32_t reserved_0_15 : 16; 175189251Ssam 176189251Ssam } o2; 177189251Ssam } dw2; 178189251Ssam} cvmx_higig_header_t; 179189251Ssam 180189251Ssam 181189251Ssam/** 182189251Ssam * Initialize the HiGig aspects of a XAUI interface. This function 183189251Ssam * should be called before the cvmx-helper generic init. 184189251Ssam * 185189251Ssam * @param interface Interface to initialize HiGig on (0-1) 186189251Ssam * @param enable_higig2 187189251Ssam * Non zero to enable HiGig2 support. Zero to support HiGig 188189251Ssam * and HiGig+. 189189251Ssam * 190324739Sgordon * @return Zero on success, negative on failure 191324739Sgordon */ 192324739Sgordonstatic inline int cvmx_higig_initialize(int interface, int enable_higig2) 193324739Sgordon{ 194189251Ssam cvmx_pip_prt_cfgx_t pip_prt_cfg; 195324739Sgordon cvmx_gmxx_rxx_udd_skp_t gmx_rx_udd_skp; 196324739Sgordon cvmx_gmxx_txx_min_pkt_t gmx_tx_min_pkt; 197324739Sgordon cvmx_gmxx_txx_append_t gmx_tx_append; 198324739Sgordon cvmx_gmxx_tx_ifg_t gmx_tx_ifg; 199324739Sgordon cvmx_gmxx_tx_ovr_bp_t gmx_tx_ovr_bp; 200324739Sgordon cvmx_gmxx_rxx_frm_ctl_t gmx_rx_frm_ctl; 201324739Sgordon cvmx_gmxx_tx_xaui_ctl_t gmx_tx_xaui_ctl; 202189251Ssam int i; 203189251Ssam int header_size = (enable_higig2) ? 16 : 12; 204189251Ssam 205189251Ssam /* Setup PIP to handle HiGig */ 206189251Ssam pip_prt_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(interface*16)); 207189251Ssam pip_prt_cfg.s.dsa_en = 0; 208189251Ssam pip_prt_cfg.s.higig_en = 1; 209189251Ssam pip_prt_cfg.s.hg_qos = 1; 210189251Ssam pip_prt_cfg.s.skip = header_size; 211189251Ssam cvmx_write_csr(CVMX_PIP_PRT_CFGX(interface*16), pip_prt_cfg.u64); 212189251Ssam 213189251Ssam /* Setup some sample QoS defaults. These can be changed later */ 214189251Ssam for (i=0; i<64; i++) 215189251Ssam { 216189251Ssam cvmx_pip_hg_pri_qos_t pip_hg_pri_qos; 217189251Ssam pip_hg_pri_qos.u64 = 0; 218189251Ssam pip_hg_pri_qos.s.up_qos = 1; 219189251Ssam pip_hg_pri_qos.s.pri = i; 220189251Ssam pip_hg_pri_qos.s.qos = i&7; 221189251Ssam cvmx_write_csr(CVMX_PIP_HG_PRI_QOS, pip_hg_pri_qos.u64); 222189251Ssam } 223189251Ssam 224189251Ssam /* Setup GMX RX to treat the HiGig header as user data to ignore */ 225189251Ssam gmx_rx_udd_skp.u64 = cvmx_read_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface)); 226189251Ssam gmx_rx_udd_skp.s.len = header_size; 227189251Ssam gmx_rx_udd_skp.s.fcssel = 0; 228189251Ssam cvmx_write_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface), gmx_rx_udd_skp.u64); 229189251Ssam 230189251Ssam /* Disable GMX preamble checking */ 231189251Ssam gmx_rx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface)); 232189251Ssam gmx_rx_frm_ctl.s.pre_chk = 0; 233189251Ssam cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface), gmx_rx_frm_ctl.u64); 234189251Ssam 235189251Ssam /* Setup GMX TX to pad properly min sized packets */ 236189251Ssam gmx_tx_min_pkt.u64 = cvmx_read_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface)); 237189251Ssam gmx_tx_min_pkt.s.min_size = 59 + header_size; 238189251Ssam cvmx_write_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface), gmx_tx_min_pkt.u64); 239189251Ssam 240189251Ssam /* Setup GMX TX to not add a preamble */ 241189251Ssam gmx_tx_append.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(0, interface)); 242189251Ssam gmx_tx_append.s.preamble = 0; 243189251Ssam cvmx_write_csr(CVMX_GMXX_TXX_APPEND(0, interface), gmx_tx_append.u64); 244189251Ssam 245189251Ssam /* Reduce the inter frame gap to 8 bytes */ 246189251Ssam gmx_tx_ifg.u64 = cvmx_read_csr(CVMX_GMXX_TX_IFG(interface)); 247189251Ssam gmx_tx_ifg.s.ifg1 = 4; 248189251Ssam gmx_tx_ifg.s.ifg2 = 4; 249189251Ssam cvmx_write_csr(CVMX_GMXX_TX_IFG(interface), gmx_tx_ifg.u64); 250189251Ssam 251189251Ssam /* Disable GMX backpressure */ 252189251Ssam gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface)); 253189251Ssam gmx_tx_ovr_bp.s.bp = 0; 254189251Ssam gmx_tx_ovr_bp.s.en = 0xf; 255189251Ssam gmx_tx_ovr_bp.s.ign_full = 0xf; 256189251Ssam cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64); 257189251Ssam 258189251Ssam if (enable_higig2) 259189251Ssam { 260189251Ssam /* Enable HiGig2 support and forwarding of virtual port backpressure 261189251Ssam to PKO */ 262189251Ssam cvmx_gmxx_hg2_control_t gmx_hg2_control; 263189251Ssam gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); 264189251Ssam gmx_hg2_control.s.hg2rx_en = 1; 265189251Ssam gmx_hg2_control.s.hg2tx_en = 1; 266189251Ssam gmx_hg2_control.s.logl_en = 0xffff; 267189251Ssam gmx_hg2_control.s.phys_en = 1; 268189251Ssam cvmx_write_csr(CVMX_GMXX_HG2_CONTROL(interface), gmx_hg2_control.u64); 269189251Ssam } 270189251Ssam 271189251Ssam /* Enable HiGig */ 272189251Ssam gmx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); 273189251Ssam gmx_tx_xaui_ctl.s.hg_en = 1; 274189251Ssam cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmx_tx_xaui_ctl.u64); 275189251Ssam 276189251Ssam return 0; 277189251Ssam} 278189251Ssam 279189251Ssam#ifdef __cplusplus 280189251Ssam} 281189251Ssam#endif 282189251Ssam 283189251Ssam#endif // __CVMX_HIGIG_H__ 284189251Ssam