cvmx-helper-util.c revision 210311
1/***********************license start*************** 2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 * 23 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25 * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26 * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31 * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33 * 34 * 35 * For any questions regarding licensing please contact marketing@caviumnetworks.com 36 * 37 ***********************license end**************************************/ 38 39 40 41 42 43 44/** 45 * @file 46 * 47 * Small helper utilities. 48 * 49 * <hr>$Revision: 42493 $<hr> 50 */ 51#include "cvmx.h" 52#include "cvmx-bootmem.h" 53#include "cvmx-fpa.h" 54#include "cvmx-pip.h" 55#include "cvmx-pko.h" 56#include "cvmx-ipd.h" 57#include "cvmx-asx.h" 58#include "cvmx-gmx.h" 59#include "cvmx-spi.h" 60#include "cvmx-sysinfo.h" 61#include "cvmx-helper.h" 62#include "cvmx-helper-util.h" 63#include "cvmx-version.h" 64 65#ifdef CVMX_ENABLE_HELPER_FUNCTIONS 66 67/** 68 * Get the version of the CVMX libraries. 69 * 70 * @return Version string. Note this buffer is allocated statically 71 * and will be shared by all callers. 72 */ 73const char *cvmx_helper_get_version(void) 74{ 75 return OCTEON_SDK_VERSION_STRING; 76} 77 78 79/** 80 * Convert a interface mode into a human readable string 81 * 82 * @param mode Mode to convert 83 * 84 * @return String 85 */ 86const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode) 87{ 88 switch (mode) 89 { 90 case CVMX_HELPER_INTERFACE_MODE_DISABLED: return "DISABLED"; 91 case CVMX_HELPER_INTERFACE_MODE_RGMII: return "RGMII"; 92 case CVMX_HELPER_INTERFACE_MODE_GMII: return "GMII"; 93 case CVMX_HELPER_INTERFACE_MODE_SPI: return "SPI"; 94 case CVMX_HELPER_INTERFACE_MODE_PCIE: return "PCIE"; 95 case CVMX_HELPER_INTERFACE_MODE_XAUI: return "XAUI"; 96 case CVMX_HELPER_INTERFACE_MODE_SGMII: return "SGMII"; 97 case CVMX_HELPER_INTERFACE_MODE_PICMG: return "PICMG"; 98 case CVMX_HELPER_INTERFACE_MODE_NPI: return "NPI"; 99 case CVMX_HELPER_INTERFACE_MODE_LOOP: return "LOOP"; 100 } 101 return "UNKNOWN"; 102} 103 104 105/** 106 * Debug routine to dump the packet structure to the console 107 * 108 * @param work Work queue entry containing the packet to dump 109 * @return 110 */ 111int cvmx_helper_dump_packet(cvmx_wqe_t *work) 112{ 113 uint64_t count; 114 uint64_t remaining_bytes; 115 cvmx_buf_ptr_t buffer_ptr; 116 uint64_t start_of_buffer; 117 uint8_t * data_address; 118 uint8_t * end_of_data; 119 120 cvmx_dprintf("Packet Length: %u\n", work->len); 121 cvmx_dprintf(" Input Port: %u\n", work->ipprt); 122 cvmx_dprintf(" QoS: %u\n", work->qos); 123 cvmx_dprintf(" Buffers: %u\n", work->word2.s.bufs); 124 125 if (work->word2.s.bufs == 0) 126 { 127 cvmx_ipd_wqe_fpa_queue_t wqe_pool; 128 wqe_pool.u64 = cvmx_read_csr(CVMX_IPD_WQE_FPA_QUEUE); 129 buffer_ptr.u64 = 0; 130 buffer_ptr.s.pool = wqe_pool.s.wqe_pool; 131 buffer_ptr.s.size = 128; 132 buffer_ptr.s.addr = cvmx_ptr_to_phys(work->packet_data); 133 if (cvmx_likely(!work->word2.s.not_IP)) 134 { 135 cvmx_pip_ip_offset_t pip_ip_offset; 136 pip_ip_offset.u64 = cvmx_read_csr(CVMX_PIP_IP_OFFSET); 137 buffer_ptr.s.addr += (pip_ip_offset.s.offset<<3) - work->word2.s.ip_offset; 138 buffer_ptr.s.addr += (work->word2.s.is_v6^1)<<2; 139 } 140 else 141 { 142 /* WARNING: This code assume that the packet is not RAW. If it was, 143 we would use PIP_GBL_CFG[RAW_SHF] instead of 144 PIP_GBL_CFG[NIP_SHF] */ 145 cvmx_pip_gbl_cfg_t pip_gbl_cfg; 146 pip_gbl_cfg.u64 = cvmx_read_csr(CVMX_PIP_GBL_CFG); 147 buffer_ptr.s.addr += pip_gbl_cfg.s.nip_shf; 148 } 149 } 150 else 151 buffer_ptr = work->packet_ptr; 152 remaining_bytes = work->len; 153 154 while (remaining_bytes) 155 { 156 start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; 157 cvmx_dprintf(" Buffer Start:%llx\n", (unsigned long long)start_of_buffer); 158 cvmx_dprintf(" Buffer I : %u\n", buffer_ptr.s.i); 159 cvmx_dprintf(" Buffer Back: %u\n", buffer_ptr.s.back); 160 cvmx_dprintf(" Buffer Pool: %u\n", buffer_ptr.s.pool); 161 cvmx_dprintf(" Buffer Data: %llx\n", (unsigned long long)buffer_ptr.s.addr); 162 cvmx_dprintf(" Buffer Size: %u\n", buffer_ptr.s.size); 163 164 cvmx_dprintf("\t\t"); 165 data_address = (uint8_t *)cvmx_phys_to_ptr(buffer_ptr.s.addr); 166 end_of_data = data_address + buffer_ptr.s.size; 167 count = 0; 168 while (data_address < end_of_data) 169 { 170 if (remaining_bytes == 0) 171 break; 172 else 173 remaining_bytes--; 174 cvmx_dprintf("%02x", (unsigned int)*data_address); 175 data_address++; 176 if (remaining_bytes && (count == 7)) 177 { 178 cvmx_dprintf("\n\t\t"); 179 count = 0; 180 } 181 else 182 count++; 183 } 184 cvmx_dprintf("\n"); 185 186 if (remaining_bytes) 187 buffer_ptr = *(cvmx_buf_ptr_t*)cvmx_phys_to_ptr(buffer_ptr.s.addr - 8); 188 } 189 return 0; 190} 191 192 193/** 194 * Setup Random Early Drop on a specific input queue 195 * 196 * @param queue Input queue to setup RED on (0-7) 197 * @param pass_thresh 198 * Packets will begin slowly dropping when there are less than 199 * this many packet buffers free in FPA 0. 200 * @param drop_thresh 201 * All incomming packets will be dropped when there are less 202 * than this many free packet buffers in FPA 0. 203 * @return Zero on success. Negative on failure 204 */ 205int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh) 206{ 207 cvmx_ipd_qos_red_marks_t red_marks; 208 cvmx_ipd_red_quex_param_t red_param; 209 210 /* Set RED to begin dropping packets when there are pass_thresh buffers 211 left. It will linearly drop more packets until reaching drop_thresh 212 buffers */ 213 red_marks.u64 = 0; 214 red_marks.s.drop = drop_thresh; 215 red_marks.s.pass = pass_thresh; 216 cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64); 217 218 /* Use the actual queue 0 counter, not the average */ 219 red_param.u64 = 0; 220 red_param.s.prb_con = (255ul<<24) / (red_marks.s.pass - red_marks.s.drop); 221 red_param.s.avg_con = 1; 222 red_param.s.new_con = 255; 223 red_param.s.use_pcnt = 1; 224 cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64); 225 return 0; 226} 227 228 229/** 230 * Setup Random Early Drop to automatically begin dropping packets. 231 * 232 * @param pass_thresh 233 * Packets will begin slowly dropping when there are less than 234 * this many packet buffers free in FPA 0. 235 * @param drop_thresh 236 * All incomming packets will be dropped when there are less 237 * than this many free packet buffers in FPA 0. 238 * @return Zero on success. Negative on failure 239 */ 240int cvmx_helper_setup_red(int pass_thresh, int drop_thresh) 241{ 242 cvmx_ipd_portx_bp_page_cnt_t page_cnt; 243 cvmx_ipd_bp_prt_red_end_t ipd_bp_prt_red_end; 244 cvmx_ipd_red_port_enable_t red_port_enable; 245 int queue; 246 int interface; 247 int port; 248 249 /* Disable backpressure based on queued buffers. It needs SW support */ 250 page_cnt.u64 = 0; 251 page_cnt.s.bp_enb = 0; 252 page_cnt.s.page_cnt = 100; 253 for (interface=0; interface<2; interface++) 254 { 255 for (port=cvmx_helper_get_first_ipd_port(interface); port<cvmx_helper_get_last_ipd_port(interface); port++) 256 cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port), page_cnt.u64); 257 } 258 259 for (queue=0; queue<8; queue++) 260 cvmx_helper_setup_red_queue(queue, pass_thresh, drop_thresh); 261 262 /* Shutoff the dropping based on the per port page count. SW isn't 263 decrementing it right now */ 264 ipd_bp_prt_red_end.u64 = 0; 265 ipd_bp_prt_red_end.s.prt_enb = 0; 266 cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64); 267 268 red_port_enable.u64 = 0; 269 red_port_enable.s.prt_enb = 0xfffffffffull; 270 red_port_enable.s.avg_dly = 10000; 271 red_port_enable.s.prb_dly = 10000; 272 cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64); 273 274 return 0; 275} 276 277 278/** 279 * @INTERNAL 280 * Setup the common GMX settings that determine the number of 281 * ports. These setting apply to almost all configurations of all 282 * chips. 283 * 284 * @param interface Interface to configure 285 * @param num_ports Number of ports on the interface 286 * 287 * @return Zero on success, negative on failure 288 */ 289int __cvmx_helper_setup_gmx(int interface, int num_ports) 290{ 291 cvmx_gmxx_tx_prts_t gmx_tx_prts; 292 cvmx_gmxx_rx_prts_t gmx_rx_prts; 293 cvmx_pko_reg_gmx_port_mode_t pko_mode; 294 cvmx_gmxx_txx_thresh_t gmx_tx_thresh; 295 int index; 296 297 /* Tell GMX the number of TX ports on this interface */ 298 gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface)); 299 gmx_tx_prts.s.prts = num_ports; 300 cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64); 301 302 /* Tell GMX the number of RX ports on this interface. This only 303 ** applies to *GMII and XAUI ports */ 304 if (cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_RGMII 305 || cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_SGMII 306 || cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_GMII 307 || cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_XAUI) 308 { 309 if (num_ports > 4) 310 { 311 cvmx_dprintf("__cvmx_helper_setup_gmx: Illegal num_ports\n"); 312 return(-1); 313 } 314 315 gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface)); 316 gmx_rx_prts.s.prts = num_ports; 317 cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64); 318 } 319 320 /* Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX, 31XX, and 50XX */ 321 if (!OCTEON_IS_MODEL(OCTEON_CN30XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) && !OCTEON_IS_MODEL(OCTEON_CN50XX)) 322 { 323 /* Tell PKO the number of ports on this interface */ 324 pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE); 325 if (interface == 0) 326 { 327 if (num_ports == 1) 328 pko_mode.s.mode0 = 4; 329 else if (num_ports == 2) 330 pko_mode.s.mode0 = 3; 331 else if (num_ports <= 4) 332 pko_mode.s.mode0 = 2; 333 else if (num_ports <= 8) 334 pko_mode.s.mode0 = 1; 335 else 336 pko_mode.s.mode0 = 0; 337 } 338 else 339 { 340 if (num_ports == 1) 341 pko_mode.s.mode1 = 4; 342 else if (num_ports == 2) 343 pko_mode.s.mode1 = 3; 344 else if (num_ports <= 4) 345 pko_mode.s.mode1 = 2; 346 else if (num_ports <= 8) 347 pko_mode.s.mode1 = 1; 348 else 349 pko_mode.s.mode1 = 0; 350 } 351 cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64); 352 } 353 354 /* Set GMX to buffer as much data as possible before starting transmit. 355 This reduces the chances that we have a TX under run due to memory 356 contention. Any packet that fits entirely in the GMX FIFO can never 357 have an under run regardless of memory load */ 358 gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface)); 359 if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) 360 { 361 /* These chips have a fixed max threshold of 0x40 */ 362 gmx_tx_thresh.s.cnt = 0x40; 363 } 364 else 365 { 366 /* Choose the max value for the number of ports */ 367 if (num_ports <= 1) 368 gmx_tx_thresh.s.cnt = 0x100 / 1; 369 else if (num_ports == 2) 370 gmx_tx_thresh.s.cnt = 0x100 / 2; 371 else 372 gmx_tx_thresh.s.cnt = 0x100 / 4; 373 } 374 /* SPI and XAUI can have lots of ports but the GMX hardware only ever has 375 a max of 4 */ 376 if (num_ports > 4) 377 num_ports = 4; 378 for (index=0; index<num_ports; index++) 379 cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface), gmx_tx_thresh.u64); 380 381 return 0; 382} 383 384 385/** 386 * Returns the IPD/PKO port number for a port on teh given 387 * interface. 388 * 389 * @param interface Interface to use 390 * @param port Port on the interface 391 * 392 * @return IPD/PKO port number 393 */ 394int cvmx_helper_get_ipd_port(int interface, int port) 395{ 396 switch (interface) 397 { 398 case 0: return port; 399 case 1: return port + 16; 400 case 2: return port + 32; 401 case 3: return port + 36; 402 } 403 return -1; 404} 405 406#endif /* CVMX_ENABLE_HELPER_FUNCTIONS */ 407 408 409/** 410 * Returns the interface number for an IPD/PKO port number. 411 * 412 * @param ipd_port IPD/PKO port number 413 * 414 * @return Interface number 415 */ 416int cvmx_helper_get_interface_num(int ipd_port) 417{ 418 if (ipd_port < 16) 419 return 0; 420 else if (ipd_port < 32) 421 return 1; 422 else if (ipd_port < 36) 423 return 2; 424 else if (ipd_port < 40) 425 return 3; 426 else 427 cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD port number\n"); 428 429 return -1; 430} 431 432 433/** 434 * Returns the interface index number for an IPD/PKO port 435 * number. 436 * 437 * @param ipd_port IPD/PKO port number 438 * 439 * @return Interface index number 440 */ 441int cvmx_helper_get_interface_index_num(int ipd_port) 442{ 443 if (ipd_port < 32) 444 return ipd_port & 15; 445 else if (ipd_port < 36) 446 return ipd_port & 3; 447 else if (ipd_port < 40) 448 return ipd_port & 3; 449 else 450 cvmx_dprintf("cvmx_helper_get_interface_index_num: Illegal IPD port number\n"); 451 452 return -1; 453} 454 455/** 456 * Initialize the internal QLM JTAG logic to allow programming 457 * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions. 458 * These functions should only be used at the direction of Cavium 459 * Networks. Programming incorrect values into the JTAG chain 460 * can cause chip damage. 461 */ 462void cvmx_helper_qlm_jtag_init(void) 463{ 464 cvmx_ciu_qlm_jtgc_t jtgc; 465 int clock_div = 0; 466 int divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000); 467 divisor = (divisor-1)>>2; 468 /* Convert the divisor into a power of 2 shift */ 469 CVMX_CLZ(clock_div, divisor); 470 clock_div = 32 - clock_div; 471 472 /* Clock divider for QLM JTAG operations. eclk is divided by 2^(CLK_DIV + 2) */ 473 jtgc.u64 = 0; 474 jtgc.s.clk_div = clock_div; 475 jtgc.s.mux_sel = 0; 476 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) 477 jtgc.s.bypass = 0x3; 478 else 479 jtgc.s.bypass = 0xf; 480 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64); 481 cvmx_read_csr(CVMX_CIU_QLM_JTGC); 482} 483 484 485/** 486 * Write up to 32bits into the QLM jtag chain. Bits are shifted 487 * into the MSB and out the LSB, so you should shift in the low 488 * order bits followed by the high order bits. The JTAG chain is 489 * 4 * 268 bits long, or 1072. 490 * 491 * @param qlm QLM to shift value into 492 * @param bits Number of bits to shift in (1-32). 493 * @param data Data to shift in. Bit 0 enters the chain first, followed by 494 * bit 1, etc. 495 * 496 * @return The low order bits of the JTAG chain that shifted out of the 497 * circle. 498 */ 499uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data) 500{ 501 cvmx_ciu_qlm_jtgd_t jtgd; 502 jtgd.u64 = 0; 503 jtgd.s.shift = 1; 504 jtgd.s.shft_cnt = bits-1; 505 jtgd.s.shft_reg = data; 506 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) 507 jtgd.s.select = 1 << qlm; 508 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); 509 do 510 { 511 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD); 512 } while (jtgd.s.shift); 513 return jtgd.s.shft_reg >> (32-bits); 514} 515 516 517/** 518 * Shift long sequences of zeros into the QLM JTAG chain. It is 519 * common to need to shift more than 32 bits of zeros into the 520 * chain. This function is a convience wrapper around 521 * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of 522 * zeros at a time. 523 * 524 * @param qlm QLM to shift zeros into 525 * @param bits 526 */ 527void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits) 528{ 529 while (bits > 0) 530 { 531 int n = bits; 532 if (n > 32) 533 n = 32; 534 cvmx_helper_qlm_jtag_shift(qlm, n, 0); 535 bits -= n; 536 } 537} 538 539 540/** 541 * Program the QLM JTAG chain into all lanes of the QLM. You must 542 * have already shifted in 268*4, or 1072 bits into the JTAG 543 * chain. Updating invalid values can possibly cause chip damage. 544 * 545 * @param qlm QLM to program 546 */ 547void cvmx_helper_qlm_jtag_update(int qlm) 548{ 549 cvmx_ciu_qlm_jtgd_t jtgd; 550 551 /* Update the new data */ 552 jtgd.u64 = 0; 553 jtgd.s.update = 1; 554 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) 555 jtgd.s.select = 1 << qlm; 556 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); 557 do 558 { 559 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD); 560 } while (jtgd.s.update); 561} 562 563