cvmx-helper-util.c revision 210286
1/***********************license start*************** 2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 * 23 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25 * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26 * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31 * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33 * 34 * 35 * For any questions regarding licensing please contact marketing@caviumnetworks.com 36 * 37 ***********************license end**************************************/ 38 39 40 41 42 43 44/** 45 * @file 46 * 47 * Small helper utilities. 48 * 49 * <hr>$Revision: 42493 $<hr> 50 */ 51#include "executive-config.h" 52#include "cvmx-config.h" 53#include "cvmx.h" 54#include "cvmx-bootmem.h" 55#include "cvmx-fpa.h" 56#include "cvmx-pip.h" 57#include "cvmx-pko.h" 58#include "cvmx-ipd.h" 59#include "cvmx-asx.h" 60#include "cvmx-gmx.h" 61#include "cvmx-spi.h" 62#include "cvmx-sysinfo.h" 63#include "cvmx-helper.h" 64#include "cvmx-helper-util.h" 65#include "cvmx-version.h" 66 67#ifdef CVMX_ENABLE_HELPER_FUNCTIONS 68 69/** 70 * Get the version of the CVMX libraries. 71 * 72 * @return Version string. Note this buffer is allocated statically 73 * and will be shared by all callers. 74 */ 75const char *cvmx_helper_get_version(void) 76{ 77 return OCTEON_SDK_VERSION_STRING; 78} 79 80 81/** 82 * Convert a interface mode into a human readable string 83 * 84 * @param mode Mode to convert 85 * 86 * @return String 87 */ 88const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode) 89{ 90 switch (mode) 91 { 92 case CVMX_HELPER_INTERFACE_MODE_DISABLED: return "DISABLED"; 93 case CVMX_HELPER_INTERFACE_MODE_RGMII: return "RGMII"; 94 case CVMX_HELPER_INTERFACE_MODE_GMII: return "GMII"; 95 case CVMX_HELPER_INTERFACE_MODE_SPI: return "SPI"; 96 case CVMX_HELPER_INTERFACE_MODE_PCIE: return "PCIE"; 97 case CVMX_HELPER_INTERFACE_MODE_XAUI: return "XAUI"; 98 case CVMX_HELPER_INTERFACE_MODE_SGMII: return "SGMII"; 99 case CVMX_HELPER_INTERFACE_MODE_PICMG: return "PICMG"; 100 case CVMX_HELPER_INTERFACE_MODE_NPI: return "NPI"; 101 case CVMX_HELPER_INTERFACE_MODE_LOOP: return "LOOP"; 102 } 103 return "UNKNOWN"; 104} 105 106 107/** 108 * Debug routine to dump the packet structure to the console 109 * 110 * @param work Work queue entry containing the packet to dump 111 * @return 112 */ 113int cvmx_helper_dump_packet(cvmx_wqe_t *work) 114{ 115 uint64_t count; 116 uint64_t remaining_bytes; 117 cvmx_buf_ptr_t buffer_ptr; 118 uint64_t start_of_buffer; 119 uint8_t * data_address; 120 uint8_t * end_of_data; 121 122 cvmx_dprintf("Packet Length: %u\n", work->len); 123 cvmx_dprintf(" Input Port: %u\n", work->ipprt); 124 cvmx_dprintf(" QoS: %u\n", work->qos); 125 cvmx_dprintf(" Buffers: %u\n", work->word2.s.bufs); 126 127 if (work->word2.s.bufs == 0) 128 { 129 cvmx_ipd_wqe_fpa_queue_t wqe_pool; 130 wqe_pool.u64 = cvmx_read_csr(CVMX_IPD_WQE_FPA_QUEUE); 131 buffer_ptr.u64 = 0; 132 buffer_ptr.s.pool = wqe_pool.s.wqe_pool; 133 buffer_ptr.s.size = 128; 134 buffer_ptr.s.addr = cvmx_ptr_to_phys(work->packet_data); 135 if (cvmx_likely(!work->word2.s.not_IP)) 136 { 137 cvmx_pip_ip_offset_t pip_ip_offset; 138 pip_ip_offset.u64 = cvmx_read_csr(CVMX_PIP_IP_OFFSET); 139 buffer_ptr.s.addr += (pip_ip_offset.s.offset<<3) - work->word2.s.ip_offset; 140 buffer_ptr.s.addr += (work->word2.s.is_v6^1)<<2; 141 } 142 else 143 { 144 /* WARNING: This code assume that the packet is not RAW. If it was, 145 we would use PIP_GBL_CFG[RAW_SHF] instead of 146 PIP_GBL_CFG[NIP_SHF] */ 147 cvmx_pip_gbl_cfg_t pip_gbl_cfg; 148 pip_gbl_cfg.u64 = cvmx_read_csr(CVMX_PIP_GBL_CFG); 149 buffer_ptr.s.addr += pip_gbl_cfg.s.nip_shf; 150 } 151 } 152 else 153 buffer_ptr = work->packet_ptr; 154 remaining_bytes = work->len; 155 156 while (remaining_bytes) 157 { 158 start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; 159 cvmx_dprintf(" Buffer Start:%llx\n", (unsigned long long)start_of_buffer); 160 cvmx_dprintf(" Buffer I : %u\n", buffer_ptr.s.i); 161 cvmx_dprintf(" Buffer Back: %u\n", buffer_ptr.s.back); 162 cvmx_dprintf(" Buffer Pool: %u\n", buffer_ptr.s.pool); 163 cvmx_dprintf(" Buffer Data: %llx\n", (unsigned long long)buffer_ptr.s.addr); 164 cvmx_dprintf(" Buffer Size: %u\n", buffer_ptr.s.size); 165 166 cvmx_dprintf("\t\t"); 167 data_address = (uint8_t *)cvmx_phys_to_ptr(buffer_ptr.s.addr); 168 end_of_data = data_address + buffer_ptr.s.size; 169 count = 0; 170 while (data_address < end_of_data) 171 { 172 if (remaining_bytes == 0) 173 break; 174 else 175 remaining_bytes--; 176 cvmx_dprintf("%02x", (unsigned int)*data_address); 177 data_address++; 178 if (remaining_bytes && (count == 7)) 179 { 180 cvmx_dprintf("\n\t\t"); 181 count = 0; 182 } 183 else 184 count++; 185 } 186 cvmx_dprintf("\n"); 187 188 if (remaining_bytes) 189 buffer_ptr = *(cvmx_buf_ptr_t*)cvmx_phys_to_ptr(buffer_ptr.s.addr - 8); 190 } 191 return 0; 192} 193 194 195/** 196 * Setup Random Early Drop on a specific input queue 197 * 198 * @param queue Input queue to setup RED on (0-7) 199 * @param pass_thresh 200 * Packets will begin slowly dropping when there are less than 201 * this many packet buffers free in FPA 0. 202 * @param drop_thresh 203 * All incomming packets will be dropped when there are less 204 * than this many free packet buffers in FPA 0. 205 * @return Zero on success. Negative on failure 206 */ 207int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh) 208{ 209 cvmx_ipd_qos_red_marks_t red_marks; 210 cvmx_ipd_red_quex_param_t red_param; 211 212 /* Set RED to begin dropping packets when there are pass_thresh buffers 213 left. It will linearly drop more packets until reaching drop_thresh 214 buffers */ 215 red_marks.u64 = 0; 216 red_marks.s.drop = drop_thresh; 217 red_marks.s.pass = pass_thresh; 218 cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64); 219 220 /* Use the actual queue 0 counter, not the average */ 221 red_param.u64 = 0; 222 red_param.s.prb_con = (255ul<<24) / (red_marks.s.pass - red_marks.s.drop); 223 red_param.s.avg_con = 1; 224 red_param.s.new_con = 255; 225 red_param.s.use_pcnt = 1; 226 cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64); 227 return 0; 228} 229 230 231/** 232 * Setup Random Early Drop to automatically begin dropping packets. 233 * 234 * @param pass_thresh 235 * Packets will begin slowly dropping when there are less than 236 * this many packet buffers free in FPA 0. 237 * @param drop_thresh 238 * All incomming packets will be dropped when there are less 239 * than this many free packet buffers in FPA 0. 240 * @return Zero on success. Negative on failure 241 */ 242int cvmx_helper_setup_red(int pass_thresh, int drop_thresh) 243{ 244 cvmx_ipd_portx_bp_page_cnt_t page_cnt; 245 cvmx_ipd_bp_prt_red_end_t ipd_bp_prt_red_end; 246 cvmx_ipd_red_port_enable_t red_port_enable; 247 int queue; 248 int interface; 249 int port; 250 251 /* Disable backpressure based on queued buffers. It needs SW support */ 252 page_cnt.u64 = 0; 253 page_cnt.s.bp_enb = 0; 254 page_cnt.s.page_cnt = 100; 255 for (interface=0; interface<2; interface++) 256 { 257 for (port=cvmx_helper_get_first_ipd_port(interface); port<cvmx_helper_get_last_ipd_port(interface); port++) 258 cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port), page_cnt.u64); 259 } 260 261 for (queue=0; queue<8; queue++) 262 cvmx_helper_setup_red_queue(queue, pass_thresh, drop_thresh); 263 264 /* Shutoff the dropping based on the per port page count. SW isn't 265 decrementing it right now */ 266 ipd_bp_prt_red_end.u64 = 0; 267 ipd_bp_prt_red_end.s.prt_enb = 0; 268 cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64); 269 270 red_port_enable.u64 = 0; 271 red_port_enable.s.prt_enb = 0xfffffffffull; 272 red_port_enable.s.avg_dly = 10000; 273 red_port_enable.s.prb_dly = 10000; 274 cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64); 275 276 return 0; 277} 278 279 280/** 281 * @INTERNAL 282 * Setup the common GMX settings that determine the number of 283 * ports. These setting apply to almost all configurations of all 284 * chips. 285 * 286 * @param interface Interface to configure 287 * @param num_ports Number of ports on the interface 288 * 289 * @return Zero on success, negative on failure 290 */ 291int __cvmx_helper_setup_gmx(int interface, int num_ports) 292{ 293 cvmx_gmxx_tx_prts_t gmx_tx_prts; 294 cvmx_gmxx_rx_prts_t gmx_rx_prts; 295 cvmx_pko_reg_gmx_port_mode_t pko_mode; 296 cvmx_gmxx_txx_thresh_t gmx_tx_thresh; 297 int index; 298 299 /* Tell GMX the number of TX ports on this interface */ 300 gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface)); 301 gmx_tx_prts.s.prts = num_ports; 302 cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64); 303 304 /* Tell GMX the number of RX ports on this interface. This only 305 ** applies to *GMII and XAUI ports */ 306 if (cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_RGMII 307 || cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_SGMII 308 || cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_GMII 309 || cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_XAUI) 310 { 311 if (num_ports > 4) 312 { 313 cvmx_dprintf("__cvmx_helper_setup_gmx: Illegal num_ports\n"); 314 return(-1); 315 } 316 317 gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface)); 318 gmx_rx_prts.s.prts = num_ports; 319 cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64); 320 } 321 322 /* Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX, 31XX, and 50XX */ 323 if (!OCTEON_IS_MODEL(OCTEON_CN30XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) && !OCTEON_IS_MODEL(OCTEON_CN50XX)) 324 { 325 /* Tell PKO the number of ports on this interface */ 326 pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE); 327 if (interface == 0) 328 { 329 if (num_ports == 1) 330 pko_mode.s.mode0 = 4; 331 else if (num_ports == 2) 332 pko_mode.s.mode0 = 3; 333 else if (num_ports <= 4) 334 pko_mode.s.mode0 = 2; 335 else if (num_ports <= 8) 336 pko_mode.s.mode0 = 1; 337 else 338 pko_mode.s.mode0 = 0; 339 } 340 else 341 { 342 if (num_ports == 1) 343 pko_mode.s.mode1 = 4; 344 else if (num_ports == 2) 345 pko_mode.s.mode1 = 3; 346 else if (num_ports <= 4) 347 pko_mode.s.mode1 = 2; 348 else if (num_ports <= 8) 349 pko_mode.s.mode1 = 1; 350 else 351 pko_mode.s.mode1 = 0; 352 } 353 cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64); 354 } 355 356 /* Set GMX to buffer as much data as possible before starting transmit. 357 This reduces the chances that we have a TX under run due to memory 358 contention. Any packet that fits entirely in the GMX FIFO can never 359 have an under run regardless of memory load */ 360 gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface)); 361 if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) 362 { 363 /* These chips have a fixed max threshold of 0x40 */ 364 gmx_tx_thresh.s.cnt = 0x40; 365 } 366 else 367 { 368 /* Choose the max value for the number of ports */ 369 if (num_ports <= 1) 370 gmx_tx_thresh.s.cnt = 0x100 / 1; 371 else if (num_ports == 2) 372 gmx_tx_thresh.s.cnt = 0x100 / 2; 373 else 374 gmx_tx_thresh.s.cnt = 0x100 / 4; 375 } 376 /* SPI and XAUI can have lots of ports but the GMX hardware only ever has 377 a max of 4 */ 378 if (num_ports > 4) 379 num_ports = 4; 380 for (index=0; index<num_ports; index++) 381 cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface), gmx_tx_thresh.u64); 382 383 return 0; 384} 385 386 387/** 388 * Returns the IPD/PKO port number for a port on teh given 389 * interface. 390 * 391 * @param interface Interface to use 392 * @param port Port on the interface 393 * 394 * @return IPD/PKO port number 395 */ 396int cvmx_helper_get_ipd_port(int interface, int port) 397{ 398 switch (interface) 399 { 400 case 0: return port; 401 case 1: return port + 16; 402 case 2: return port + 32; 403 case 3: return port + 36; 404 } 405 return -1; 406} 407 408#endif /* CVMX_ENABLE_HELPER_FUNCTIONS */ 409 410 411/** 412 * Returns the interface number for an IPD/PKO port number. 413 * 414 * @param ipd_port IPD/PKO port number 415 * 416 * @return Interface number 417 */ 418int cvmx_helper_get_interface_num(int ipd_port) 419{ 420 if (ipd_port < 16) 421 return 0; 422 else if (ipd_port < 32) 423 return 1; 424 else if (ipd_port < 36) 425 return 2; 426 else if (ipd_port < 40) 427 return 3; 428 else 429 cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD port number\n"); 430 431 return -1; 432} 433 434 435/** 436 * Returns the interface index number for an IPD/PKO port 437 * number. 438 * 439 * @param ipd_port IPD/PKO port number 440 * 441 * @return Interface index number 442 */ 443int cvmx_helper_get_interface_index_num(int ipd_port) 444{ 445 if (ipd_port < 32) 446 return ipd_port & 15; 447 else if (ipd_port < 36) 448 return ipd_port & 3; 449 else if (ipd_port < 40) 450 return ipd_port & 3; 451 else 452 cvmx_dprintf("cvmx_helper_get_interface_index_num: Illegal IPD port number\n"); 453 454 return -1; 455} 456 457/** 458 * Initialize the internal QLM JTAG logic to allow programming 459 * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions. 460 * These functions should only be used at the direction of Cavium 461 * Networks. Programming incorrect values into the JTAG chain 462 * can cause chip damage. 463 */ 464void cvmx_helper_qlm_jtag_init(void) 465{ 466 cvmx_ciu_qlm_jtgc_t jtgc; 467 int clock_div = 0; 468 int divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000); 469 divisor = (divisor-1)>>2; 470 /* Convert the divisor into a power of 2 shift */ 471 CVMX_CLZ(clock_div, divisor); 472 clock_div = 32 - clock_div; 473 474 /* Clock divider for QLM JTAG operations. eclk is divided by 2^(CLK_DIV + 2) */ 475 jtgc.u64 = 0; 476 jtgc.s.clk_div = clock_div; 477 jtgc.s.mux_sel = 0; 478 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) 479 jtgc.s.bypass = 0x3; 480 else 481 jtgc.s.bypass = 0xf; 482 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64); 483 cvmx_read_csr(CVMX_CIU_QLM_JTGC); 484} 485 486 487/** 488 * Write up to 32bits into the QLM jtag chain. Bits are shifted 489 * into the MSB and out the LSB, so you should shift in the low 490 * order bits followed by the high order bits. The JTAG chain is 491 * 4 * 268 bits long, or 1072. 492 * 493 * @param qlm QLM to shift value into 494 * @param bits Number of bits to shift in (1-32). 495 * @param data Data to shift in. Bit 0 enters the chain first, followed by 496 * bit 1, etc. 497 * 498 * @return The low order bits of the JTAG chain that shifted out of the 499 * circle. 500 */ 501uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data) 502{ 503 cvmx_ciu_qlm_jtgd_t jtgd; 504 jtgd.u64 = 0; 505 jtgd.s.shift = 1; 506 jtgd.s.shft_cnt = bits-1; 507 jtgd.s.shft_reg = data; 508 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) 509 jtgd.s.select = 1 << qlm; 510 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); 511 do 512 { 513 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD); 514 } while (jtgd.s.shift); 515 return jtgd.s.shft_reg >> (32-bits); 516} 517 518 519/** 520 * Shift long sequences of zeros into the QLM JTAG chain. It is 521 * common to need to shift more than 32 bits of zeros into the 522 * chain. This function is a convience wrapper around 523 * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of 524 * zeros at a time. 525 * 526 * @param qlm QLM to shift zeros into 527 * @param bits 528 */ 529void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits) 530{ 531 while (bits > 0) 532 { 533 int n = bits; 534 if (n > 32) 535 n = 32; 536 cvmx_helper_qlm_jtag_shift(qlm, n, 0); 537 bits -= n; 538 } 539} 540 541 542/** 543 * Program the QLM JTAG chain into all lanes of the QLM. You must 544 * have already shifted in 268*4, or 1072 bits into the JTAG 545 * chain. Updating invalid values can possibly cause chip damage. 546 * 547 * @param qlm QLM to program 548 */ 549void cvmx_helper_qlm_jtag_update(int qlm) 550{ 551 cvmx_ciu_qlm_jtgd_t jtgd; 552 553 /* Update the new data */ 554 jtgd.u64 = 0; 555 jtgd.s.update = 1; 556 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) 557 jtgd.s.select = 1 << qlm; 558 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); 559 do 560 { 561 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD); 562 } while (jtgd.s.update); 563} 564 565