cvmx-helper-srio.c revision 215990 
1/***********************license start***************
2 * Copyright (c) 2003-2010  Cavium Networks (support@cavium.com). All rights
3 * reserved.
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:
9 *
10 *   * Redistributions of source code must retain the above copyright
11 *     notice, this list of conditions and the following disclaimer.
12 *
13 *   * Redistributions in binary form must reproduce the above
14 *     copyright notice, this list of conditions and the following
15 *     disclaimer in the documentation and/or other materials provided
16 *     with the distribution.
17
18 *   * Neither the name of Cavium Networks nor the names of
19 *     its contributors may be used to endorse or promote products
20 *     derived from this software without specific prior written
21 *     permission.
22
23 * This Software, including technical data, may be subject to U.S. export  control
24 * laws, including the U.S. Export Administration Act and its  associated
25 * regulations, and may be subject to export or import  regulations in other
26 * countries.
27
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM  NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
39
40
41
42
43
44
45
46/**
47 * @file
48 *
49 * Functions for SRIO initialization, configuration,
50 * and monitoring.
51 *
52 * <hr>$Revision: 41586 $<hr>
53 */
54#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
55#include <asm/octeon/cvmx.h>
56#include <asm/octeon/cvmx-config.h>
57#include <asm/octeon/cvmx-clock.h>
58#include <asm/octeon/cvmx-helper.h>
59#include <asm/octeon/cvmx-srio.h>
60#include <asm/octeon/cvmx-pip-defs.h>
61#include <asm/octeon/cvmx-sriox-defs.h>
62#include <asm/octeon/cvmx-sriomaintx-defs.h>
63#include <asm/octeon/cvmx-dpi-defs.h>
64#else
65#if !defined(__FreeBSD__) || !defined(_KERNEL)
66#include "executive-config.h"
67#include "cvmx-config.h"
68#ifdef CVMX_ENABLE_PKO_FUNCTIONS
69
70#include "cvmx.h"
71#include "cvmx-helper.h"
72#include "cvmx-srio.h"
73#endif
74#else
75#include "cvmx.h"
76#include "cvmx-helper.h"
77#include "cvmx-srio.h"
78#endif
79#endif
80
81#ifdef CVMX_ENABLE_PKO_FUNCTIONS
82
83/**
84 * @INTERNAL
85 * Probe a SRIO interface and determine the number of ports
86 * connected to it. The SRIO interface should still be down
87 * after this call.
88 *
89 * @param interface Interface to probe
90 *
91 * @return Number of ports on the interface. Zero to disable.
92 */
93int __cvmx_helper_srio_probe(int interface)
94{
95    cvmx_sriox_status_reg_t srio0_status_reg;
96    cvmx_sriox_status_reg_t srio1_status_reg;
97
98    if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
99        return 0;
100
101    srio0_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
102    srio1_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
103    if (srio0_status_reg.s.srio || srio1_status_reg.s.srio)
104        return 2;
105    else
106        return 0;
107}
108
109
110/**
111 * @INTERNAL
112 * Bringup and enable SRIO interface. After this call packet
113 * I/O should be fully functional. This is called with IPD
114 * enabled but PKO disabled.
115 *
116 * @param interface Interface to bring up
117 *
118 * @return Zero on success, negative on failure
119 */
120int __cvmx_helper_srio_enable(int interface)
121{
122    int num_ports = cvmx_helper_ports_on_interface(interface);
123    int index;
124    cvmx_sriomaintx_core_enables_t sriomaintx_core_enables;
125    cvmx_sriox_imsg_ctrl_t sriox_imsg_ctrl;
126    cvmx_dpi_ctl_t dpi_ctl;
127
128    /* All SRIO ports have a cvmx_srio_rx_message_header_t header
129        on them that must be skipped by IPD */
130    for (index=0; index<num_ports; index++)
131    {
132        cvmx_pip_prt_cfgx_t port_config;
133        cvmx_sriox_omsg_portx_t sriox_omsg_portx;
134        cvmx_sriox_omsg_sp_mrx_t sriox_omsg_sp_mrx;
135        cvmx_sriox_omsg_fmp_mrx_t sriox_omsg_fmp_mrx;
136        cvmx_sriox_omsg_nmp_mrx_t sriox_omsg_nmp_mrx;
137        int ipd_port = cvmx_helper_get_ipd_port(interface, index);
138        port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
139        /* Only change the skip if the user hasn't already set it */
140        if (!port_config.s.skip)
141        {
142            port_config.s.skip = sizeof(cvmx_srio_rx_message_header_t);
143            cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64);
144        }
145
146        /* Enable TX with PKO */
147        sriox_omsg_portx.u64 = cvmx_read_csr(CVMX_SRIOX_OMSG_PORTX(index, interface - 4));
148        sriox_omsg_portx.s.port = (interface - 4) * 2 + index;
149        sriox_omsg_portx.s.enable = 1;
150        cvmx_write_csr(CVMX_SRIOX_OMSG_PORTX(index, interface - 4), sriox_omsg_portx.u64);
151
152        /* Allow OMSG controller to send regardless of the state of any other
153            controller. Allow messages to different IDs and MBOXes to go in
154            parallel */
155        sriox_omsg_sp_mrx.u64 = 0;
156        sriox_omsg_sp_mrx.s.xmbox_sp = 1;
157        sriox_omsg_sp_mrx.s.ctlr_sp = 1;
158        sriox_omsg_sp_mrx.s.ctlr_fmp = 1;
159        sriox_omsg_sp_mrx.s.ctlr_nmp = 1;
160        sriox_omsg_sp_mrx.s.id_sp = 1;
161        sriox_omsg_sp_mrx.s.id_fmp = 1;
162        sriox_omsg_sp_mrx.s.id_nmp = 1;
163        sriox_omsg_sp_mrx.s.mbox_sp = 1;
164        sriox_omsg_sp_mrx.s.mbox_fmp = 1;
165        sriox_omsg_sp_mrx.s.mbox_nmp = 1;
166        sriox_omsg_sp_mrx.s.all_psd = 1;
167        cvmx_write_csr(CVMX_SRIOX_OMSG_SP_MRX(index, interface-4), sriox_omsg_sp_mrx.u64);
168
169        /* Allow OMSG controller to send regardless of the state of any other
170            controller. Allow messages to different IDs and MBOXes to go in
171            parallel */
172        sriox_omsg_fmp_mrx.u64 = 0;
173        sriox_omsg_fmp_mrx.s.ctlr_sp = 1;
174        sriox_omsg_fmp_mrx.s.ctlr_fmp = 1;
175        sriox_omsg_fmp_mrx.s.ctlr_nmp = 1;
176        sriox_omsg_fmp_mrx.s.id_sp = 1;
177        sriox_omsg_fmp_mrx.s.id_fmp = 1;
178        sriox_omsg_fmp_mrx.s.id_nmp = 1;
179        sriox_omsg_fmp_mrx.s.mbox_sp = 1;
180        sriox_omsg_fmp_mrx.s.mbox_fmp = 1;
181        sriox_omsg_fmp_mrx.s.mbox_nmp = 1;
182        sriox_omsg_fmp_mrx.s.all_psd = 1;
183        cvmx_write_csr(CVMX_SRIOX_OMSG_FMP_MRX(index, interface-4), sriox_omsg_fmp_mrx.u64);
184
185        /* Once the first part of a message is accepted, always acept the rest
186            of the message */
187        sriox_omsg_nmp_mrx.u64 = 0;
188        sriox_omsg_nmp_mrx.s.all_sp = 1;
189        sriox_omsg_nmp_mrx.s.all_fmp = 1;
190        sriox_omsg_nmp_mrx.s.all_nmp = 1;
191        cvmx_write_csr(CVMX_SRIOX_OMSG_NMP_MRX(index, interface-4), sriox_omsg_nmp_mrx.u64);
192
193    }
194
195    /* Choose the receive controller based on the mailbox */
196    sriox_imsg_ctrl.u64 = cvmx_read_csr(CVMX_SRIOX_IMSG_CTRL(interface - 4));
197    sriox_imsg_ctrl.s.prt_sel = 0;
198    sriox_imsg_ctrl.s.mbox = 0xa;
199    cvmx_write_csr(CVMX_SRIOX_IMSG_CTRL(interface - 4), sriox_imsg_ctrl.u64);
200
201    /* DPI must be enabled for us to RX messages */
202    dpi_ctl.u64 = cvmx_read_csr(CVMX_DPI_CTL);
203    dpi_ctl.s.clk = 1;
204    dpi_ctl.s.en = 1;
205    cvmx_write_csr(CVMX_DPI_CTL, dpi_ctl.u64);
206
207    /* Enable RX */
208    if (!cvmx_srio_config_read32(interface - 4, 0, -1, 0, 0,
209        CVMX_SRIOMAINTX_CORE_ENABLES(interface-4), &sriomaintx_core_enables.u32))
210    {
211        sriomaintx_core_enables.s.imsg0 = 1;
212        sriomaintx_core_enables.s.imsg1 = 1;
213        cvmx_srio_config_write32(interface - 4, 0, -1, 0, 0,
214            CVMX_SRIOMAINTX_CORE_ENABLES(interface-4), sriomaintx_core_enables.u32);
215    }
216
217    return 0;
218}
219
220/**
221 * @INTERNAL
222 * Return the link state of an IPD/PKO port as returned by SRIO link status.
223 *
224 * @param ipd_port IPD/PKO port to query
225 *
226 * @return Link state
227 */
228cvmx_helper_link_info_t __cvmx_helper_srio_link_get(int ipd_port)
229{
230    int interface = cvmx_helper_get_interface_num(ipd_port);
231    int srio_port = interface - 4;
232    cvmx_helper_link_info_t result;
233    cvmx_sriox_status_reg_t srio_status_reg;
234    cvmx_sriomaintx_port_0_err_stat_t sriomaintx_port_0_err_stat;
235    cvmx_sriomaintx_port_0_ctl_t sriomaintx_port_0_ctl;
236    cvmx_sriomaintx_port_0_ctl2_t sriomaintx_port_0_ctl2;
237
238    result.u64 = 0;
239
240    /* Make sure register access is allowed */
241    srio_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(srio_port));
242    if (!srio_status_reg.s.access)
243        return result;
244
245    /* Read the port link status */
246    if (cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
247        CVMX_SRIOMAINTX_PORT_0_ERR_STAT(srio_port),
248        &sriomaintx_port_0_err_stat.u32))
249        return result;
250
251    /* Return if link is down */
252    if (!sriomaintx_port_0_err_stat.s.pt_ok)
253        return result;
254
255    /* Read the port link width and speed */
256    if (cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
257        CVMX_SRIOMAINTX_PORT_0_CTL(srio_port),
258        &sriomaintx_port_0_ctl.u32))
259        return result;
260    if (cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
261        CVMX_SRIOMAINTX_PORT_0_CTL2(srio_port),
262        &sriomaintx_port_0_ctl2.u32))
263        return result;
264
265    /* Link is up */
266    result.s.full_duplex = 1;
267    result.s.link_up = 1;
268    switch (sriomaintx_port_0_ctl2.s.sel_baud)
269    {
270        case 1:
271            result.s.speed = 1250;
272            break;
273        case 2:
274            result.s.speed = 2500;
275            break;
276        case 3:
277            result.s.speed = 3125;
278            break;
279        case 4:
280            result.s.speed = 5000;
281            break;
282        case 5:
283            result.s.speed = 6250;
284            break;
285        default:
286            result.s.speed = 0;
287            break;
288    }
289    switch (sriomaintx_port_0_ctl.s.it_width)
290    {
291        case 2: /* Four lanes */
292            result.s.speed += 40000;
293            break;
294        case 3: /* Two lanes */
295            result.s.speed += 20000;
296            break;
297        default: /* One lane */
298            result.s.speed += 10000;
299            break;
300    }
301    return result;
302}
303
304/**
305 * @INTERNAL
306 * Configure an IPD/PKO port for the specified link state. This
307 * function does not influence auto negotiation at the PHY level.
308 * The passed link state must always match the link state returned
309 * by cvmx_helper_link_get(). It is normally best to use
310 * cvmx_helper_link_autoconf() instead.
311 *
312 * @param ipd_port  IPD/PKO port to configure
313 * @param link_info The new link state
314 *
315 * @return Zero on success, negative on failure
316 */
317int __cvmx_helper_srio_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
318{
319    return 0;
320}
321
322#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
323
324