cvmx-helper-errata.h revision 210284 
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38
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42
43
44/**
45 * @file
46 *
47 * Fixes and workaround for Octeon chip errata. This file
48 * contains functions called by cvmx-helper to workaround known
49 * chip errata. For the most part, code doesn't need to call
50 * these functions directly.
51 *
52 * <hr>$Revision: 41586 $<hr>
53 */
54#ifndef __CVMX_HELPER_ERRATA_H__
55#define __CVMX_HELPER_ERRATA_H__
56
57/**
58 * @INTERNAL
59 * Function to adjust internal IPD pointer alignments
60 *
61 * @return 0 on success
62 *         !0 on failure
63 */
64extern int __cvmx_helper_errata_fix_ipd_ptr_alignment(void);
65
66/**
67 * @INTERNAL
68 * Workaround ASX setup errata with CN38XX pass1
69 *
70 * @param interface Interface to setup
71 * @param port      Port to setup (0..3)
72 * @param cpu_clock_hz
73 *                  Chip frequency in Hertz
74 *
75 * @return Zero on success, negative on failure
76 */
77extern int __cvmx_helper_errata_asx_pass1(int interface, int port, int cpu_clock_hz);
78
79/**
80 * This function needs to be called on all Octeon chips with
81 * errata PKI-100.
82 *
83 * The Size field is 8 too large in WQE and next pointers
84 *
85 *  The Size field generated by IPD is 8 larger than it should
86 *  be. The Size field is <55:40> of both:
87 *      - WORD3 in the work queue entry, and
88 *      - the next buffer pointer (which precedes the packet data
89 *        in each buffer).
90 *
91 * @param work   Work queue entry to fix
92 * @return Zero on success. Negative on failure
93 */
94extern int cvmx_helper_fix_ipd_packet_chain(cvmx_wqe_t *work);
95
96/**
97 * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
98 * 1 doesn't work properly. The following code disables 2nd order
99 * CDR for the specified QLM.
100 *
101 * @param qlm    QLM to disable 2nd order CDR for.
102 */
103extern void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm);
104
105#endif
106