cvmx-helper-errata.c revision 215990 
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45
46/**
47 * @file
48 *
49 * Fixes and workaround for Octeon chip errata. This file
50 * contains functions called by cvmx-helper to workaround known
51 * chip errata. For the most part, code doesn't need to call
52 * these functions directly.
53 *
54 * <hr>$Revision: 52004 $<hr>
55 */
56#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
57#include <asm/octeon/cvmx.h>
58#include <asm/octeon/cvmx-helper.h>
59#include <asm/octeon/cvmx-helper-jtag.h>
60#include <asm/octeon/cvmx-pko.h>
61#include <asm/octeon/cvmx-asxx-defs.h>
62#include <asm/octeon/cvmx-gmxx-defs.h>
63#else
64#if !defined(__FreeBSD__) || !defined(_KERNEL)
65#include "executive-config.h"
66#include "cvmx-config.h"
67#endif
68
69#include "cvmx.h"
70
71#include "cvmx-fpa.h"
72#include "cvmx-pip.h"
73#include "cvmx-pko.h"
74#include "cvmx-ipd.h"
75#include "cvmx-gmx.h"
76#include "cvmx-spi.h"
77#include "cvmx-pow.h"
78#include "cvmx-sysinfo.h"
79#include "cvmx-helper.h"
80#include "cvmx-helper-jtag.h"
81#endif
82
83
84#ifdef CVMX_ENABLE_PKO_FUNCTIONS
85
86
87/**
88 * @INTERNAL
89 * Function to adjust internal IPD pointer alignments
90 *
91 * @return 0 on success
92 *         !0 on failure
93 */
94int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
95{
96#define FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES     (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_FIRST_MBUFF_SKIP)
97#define FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_NOT_FIRST_MBUFF_SKIP)
98#define FIX_IPD_OUTPORT 0
99#define INTERFACE(port) (port >> 4) /* Ports 0-15 are interface 0, 16-31 are interface 1 */
100#define INDEX(port) (port & 0xf)
101    uint64_t *p64;
102    cvmx_pko_command_word0_t    pko_command;
103    cvmx_buf_ptr_t              g_buffer, pkt_buffer;
104    cvmx_wqe_t *work;
105    int size, num_segs = 0, wqe_pcnt, pkt_pcnt;
106    cvmx_gmxx_prtx_cfg_t gmx_cfg;
107    int retry_cnt;
108    int retry_loop_cnt;
109    int mtu;
110    int i;
111    cvmx_helper_link_info_t link_info;
112
113    /* Save values for restore at end */
114    uint64_t prtx_cfg = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
115    uint64_t tx_ptr_en = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
116    uint64_t rx_ptr_en = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
117    uint64_t rxx_jabber = cvmx_read_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
118    uint64_t frame_max = cvmx_read_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
119
120    /* Configure port to gig FDX as required for loopback mode */
121    cvmx_helper_rgmii_internal_loopback(FIX_IPD_OUTPORT);
122
123    /* Disable reception on all ports so if traffic is present it will not interfere. */
124    cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0);
125
126    cvmx_wait(100000000ull);
127
128    for (retry_loop_cnt = 0;retry_loop_cnt < 10;retry_loop_cnt++)
129    {
130        retry_cnt = 100000;
131        wqe_pcnt = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
132        pkt_pcnt = (wqe_pcnt >> 7) & 0x7f;
133        wqe_pcnt &= 0x7f;
134
135        num_segs = (2 + pkt_pcnt - wqe_pcnt) & 3;
136
137        if (num_segs == 0)
138            goto fix_ipd_exit;
139
140        num_segs += 1;
141
142        size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES + ((num_segs-1)*FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES) -
143            (FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES / 2);
144
145        cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT));
146        CVMX_SYNC;
147
148        g_buffer.u64 = 0;
149        g_buffer.s.addr = cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_WQE_POOL));
150        if (g_buffer.s.addr == 0) {
151            cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT buffer allocation failure.\n");
152            goto fix_ipd_exit;
153        }
154
155        g_buffer.s.pool = CVMX_FPA_WQE_POOL;
156        g_buffer.s.size = num_segs;
157
158        pkt_buffer.u64 = 0;
159        pkt_buffer.s.addr = cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL));
160        if (pkt_buffer.s.addr == 0) {
161            cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT buffer allocation failure.\n");
162            goto fix_ipd_exit;
163        }
164        pkt_buffer.s.i = 1;
165        pkt_buffer.s.pool = CVMX_FPA_PACKET_POOL;
166        pkt_buffer.s.size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES;
167
168        p64 = (uint64_t*) cvmx_phys_to_ptr(pkt_buffer.s.addr);
169        p64[0] = 0xffffffffffff0000ull;
170        p64[1] = 0x08004510ull;
171        p64[2] = ((uint64_t)(size-14) << 48) | 0x5ae740004000ull;
172        p64[3] = 0x3a5fc0a81073c0a8ull;
173
174        for (i=0;i<num_segs;i++)
175        {
176            if (i>0)
177                pkt_buffer.s.size = FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES;
178
179            if (i==(num_segs-1))
180                pkt_buffer.s.i = 0;
181
182            *(uint64_t*)cvmx_phys_to_ptr(g_buffer.s.addr + 8*i) = pkt_buffer.u64;
183        }
184
185        /* Build the PKO command */
186        pko_command.u64 = 0;
187        pko_command.s.segs = num_segs;
188        pko_command.s.total_bytes = size;
189        pko_command.s.dontfree = 0;
190        pko_command.s.gather = 1;
191
192        gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
193        gmx_cfg.s.en = 1;
194        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), gmx_cfg.u64);
195        cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT));
196        cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT));
197
198        mtu = cvmx_read_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
199        cvmx_write_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392-14-4);
200        cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392-14-4);
201
202        cvmx_pko_send_packet_prepare(FIX_IPD_OUTPORT, cvmx_pko_get_base_queue(FIX_IPD_OUTPORT), CVMX_PKO_LOCK_CMD_QUEUE);
203        cvmx_pko_send_packet_finish(FIX_IPD_OUTPORT, cvmx_pko_get_base_queue(FIX_IPD_OUTPORT), pko_command, g_buffer, CVMX_PKO_LOCK_CMD_QUEUE);
204
205        CVMX_SYNC;
206
207        do {
208            work = cvmx_pow_work_request_sync(CVMX_POW_WAIT);
209            retry_cnt--;
210        } while ((work == NULL) && (retry_cnt > 0));
211
212        if (!retry_cnt)
213            cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT get_work() timeout occurred.\n");
214
215
216        /* Free packet */
217        if (work)
218            cvmx_helper_free_packet_data(work);
219    }
220
221fix_ipd_exit:
222
223    /* Return CSR configs to saved values */
224    cvmx_write_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), prtx_cfg);
225    cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), tx_ptr_en);
226    cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), rx_ptr_en);
227    cvmx_write_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), rxx_jabber);
228    cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), frame_max);
229    cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 0);
230    link_info.u64 = 0;  /* Set link to down so autonegotiation will set it up again */
231    cvmx_helper_link_set(FIX_IPD_OUTPORT, link_info);
232
233    /* Bring the link back up as autonegotiation is not done in user applications. */
234    cvmx_helper_link_autoconf(FIX_IPD_OUTPORT);
235
236    CVMX_SYNC;
237    if (num_segs)
238        cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT failed.\n");
239
240    return(!!num_segs);
241
242}
243
244
245/**
246 * This function needs to be called on all Octeon chips with
247 * errata PKI-100.
248 *
249 * The Size field is 8 too large in WQE and next pointers
250 *
251 *  The Size field generated by IPD is 8 larger than it should
252 *  be. The Size field is <55:40> of both:
253 *      - WORD3 in the work queue entry, and
254 *      - the next buffer pointer (which precedes the packet data
255 *        in each buffer).
256 *
257 * @param work   Work queue entry to fix
258 * @return Zero on success. Negative on failure
259 */
260int cvmx_helper_fix_ipd_packet_chain(cvmx_wqe_t *work)
261{
262    uint64_t number_buffers = work->word2.s.bufs;
263
264    /* We only need to do this if the work has buffers */
265    if (number_buffers)
266    {
267        cvmx_buf_ptr_t buffer_ptr = work->packet_ptr;
268        /* Check for errata PKI-100 */
269        if ( (buffer_ptr.s.pool == 0) && (((uint64_t)buffer_ptr.s.size +
270                 ((uint64_t)buffer_ptr.s.back << 7) + ((uint64_t)buffer_ptr.s.addr & 0x7F))
271                 != (CVMX_FPA_PACKET_POOL_SIZE+8))) {
272            /* fix is not needed */
273            return 0;
274        }
275        /* Decrement the work packet pointer */
276        buffer_ptr.s.size -= 8;
277        work->packet_ptr = buffer_ptr;
278
279        /* Now loop through decrementing the size for each additional buffer */
280        while (--number_buffers)
281        {
282            /* Chain pointers are 8 bytes before the data */
283            cvmx_buf_ptr_t *ptr = (cvmx_buf_ptr_t*)cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
284            buffer_ptr = *ptr;
285            buffer_ptr.s.size -= 8;
286            *ptr = buffer_ptr;
287        }
288    }
289    /* Make sure that these write go out before other operations such as FPA frees */
290    CVMX_SYNCWS;
291    return 0;
292}
293
294#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
295
296
297/**
298 * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
299 * 1 doesn't work properly. The following code disables 2nd order
300 * CDR for the specified QLM.
301 *
302 * @param qlm    QLM to disable 2nd order CDR for.
303 */
304void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
305{
306    int lane;
307    cvmx_helper_qlm_jtag_init();
308    /* We need to load all four lanes of the QLM, a total of 1072 bits */
309    for (lane=0; lane<4; lane++)
310    {
311        /* Each lane has 268 bits. We need to set cfg_cdr_incx<67:64>=3 and
312            cfg_cdr_secord<77>=1. All other bits are zero. Bits go in LSB
313            first, so start off with the zeros for bits <63:0> */
314        cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1);
315        /* cfg_cdr_incx<67:64>=3 */
316        cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3);
317        /* Zeros for bits <76:68> */
318        cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1);
319        /* cfg_cdr_secord<77>=1 */
320        cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1);
321        /* Zeros for bits <267:78> */
322        cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1);
323    }
324    cvmx_helper_qlm_jtag_update(qlm);
325}
326