cvmx-helper-board.c revision 243265
1/***********************license start*************** 2 * Copyright (c) 2003-2011 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * Helper functions to abstract board specific data about 50 * network ports from the rest of the cvmx-helper files. 51 * 52 * <hr>$Revision: 70030 $<hr> 53 */ 54#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 55#include <linux/module.h> 56#include <asm/octeon/cvmx.h> 57#include <asm/octeon/cvmx-bootinfo.h> 58#include <asm/octeon/cvmx-smix-defs.h> 59#include <asm/octeon/cvmx-gmxx-defs.h> 60#include <asm/octeon/cvmx-asxx-defs.h> 61#include <asm/octeon/cvmx-mdio.h> 62#include <asm/octeon/cvmx-helper.h> 63#include <asm/octeon/cvmx-helper-util.h> 64#include <asm/octeon/cvmx-helper-board.h> 65#include <asm/octeon/cvmx-twsi.h> 66#else 67#include "cvmx.h" 68#include "cvmx-app-init.h" 69#include "cvmx-sysinfo.h" 70#include "cvmx-twsi.h" 71#include "cvmx-mdio.h" 72#include "cvmx-helper.h" 73#include "cvmx-helper-util.h" 74#include "cvmx-helper-board.h" 75#include "cvmx-gpio.h" 76#if !defined(__FreeBSD__) || !defined(_KERNEL) 77#ifdef __U_BOOT__ 78# include <libfdt.h> 79#else 80# include "libfdt/libfdt.h" 81#endif 82#endif 83#include "cvmx-swap.h" 84#endif 85 86/** 87 * cvmx_override_board_link_get(int ipd_port) is a function 88 * pointer. It is meant to allow customization of the process of 89 * talking to a PHY to determine link speed. It is called every 90 * time a PHY must be polled for link status. Users should set 91 * this pointer to a function before calling any cvmx-helper 92 * operations. 93 */ 94CVMX_SHARED cvmx_helper_link_info_t (*cvmx_override_board_link_get)(int ipd_port) = NULL; 95 96#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL)) 97 98static void cvmx_retry_i2c_write(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t data) 99{ 100 int tries = 3; 101 int r; 102 do { 103 r = cvmx_twsix_write_ia(twsi_id, dev_addr, internal_addr, num_bytes, ia_width_bytes, data); 104 } while (tries-- > 0 && r < 0); 105} 106 107static int __pip_eth_node(const void *fdt_addr, int aliases, int ipd_port) 108{ 109 char name_buffer[20]; 110 const char*pip_path; 111 int pip, iface, eth; 112 int interface_num = cvmx_helper_get_interface_num(ipd_port); 113 int interface_index = cvmx_helper_get_interface_index_num(ipd_port); 114 115 pip_path = fdt_getprop(fdt_addr, aliases, "pip", NULL); 116 if (!pip_path) 117 { 118 cvmx_dprintf("ERROR: pip path not found in device tree\n"); 119 return -1; 120 } 121 pip = fdt_path_offset(fdt_addr, pip_path); 122 if (pip < 0) 123 { 124 cvmx_dprintf("ERROR: pip not found in device tree\n"); 125 return -1; 126 } 127#ifdef __U_BOOT__ 128 sprintf(name_buffer, "interface@%d", interface_num); 129#else 130 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", interface_num); 131#endif 132 iface = fdt_subnode_offset(fdt_addr, pip, name_buffer); 133 if (iface < 0) 134 { 135 cvmx_dprintf("ERROR : pip intf %d not found in device tree \n", 136 interface_num); 137 return -1; 138 } 139#ifdef __U_BOOT__ 140 sprintf(name_buffer, "ethernet@%x", interface_index); 141#else 142 snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", interface_index); 143#endif 144 eth = fdt_subnode_offset(fdt_addr, iface, name_buffer); 145 if (eth < 0) 146 { 147 cvmx_dprintf("ERROR : pip interface@%d ethernet@%d not found in device " 148 "tree\n", interface_num, interface_index); 149 return -1; 150 } 151 return eth; 152} 153 154static int __mix_eth_node(const void *fdt_addr, int aliases, int interface_index) 155{ 156 char name_buffer[20]; 157 const char*mix_path; 158 int mix; 159 160#ifdef __U_BOOT__ 161 sprintf(name_buffer, "mix%d", interface_index); 162#else 163 snprintf(name_buffer, sizeof(name_buffer), "mix%d", interface_index); 164#endif 165 mix_path = fdt_getprop(fdt_addr, aliases, name_buffer, NULL); 166 if (!mix_path) 167 { 168 cvmx_dprintf("ERROR: mix%d path not found in device tree\n",interface_index); 169 } 170 mix = fdt_path_offset(fdt_addr, mix_path); 171 if (mix < 0) 172 { 173 cvmx_dprintf("ERROR: %s not found in device tree\n", mix_path); 174 return -1; 175 } 176 return mix; 177} 178 179typedef struct cvmx_phy_info 180{ 181 int phy_addr; 182 int direct_connect; 183 cvmx_phy_type_t phy_type; 184}cvmx_phy_info_t; 185 186 187static int __mdiobus_addr_to_unit(uint32_t addr) 188{ 189 int unit = (addr >> 7) & 3; 190 if (!OCTEON_IS_MODEL(OCTEON_CN68XX)) 191 unit >>= 1; 192 return unit; 193} 194/** 195 * Return the MII PHY address associated with the given IPD 196 * port. The phy address is obtained from the device tree. 197 * 198 * @param ipd_port Octeon IPD port to get the MII address for. 199 * 200 * @return MII PHY address and bus number or -1. 201 */ 202 203static cvmx_phy_info_t __get_phy_info_from_dt(int ipd_port) 204{ 205 const void *fdt_addr = CASTPTR(const void *, cvmx_sysinfo_get()->fdt_addr); 206 uint32_t *phy_handle; 207 int aliases, eth, phy, phy_parent, phandle, ret; 208 cvmx_phy_info_t phy_info; 209 int mdio_unit=-1; 210 const char *phy_comaptible_str; 211 uint32_t *phy_addr_ptr; 212 213 phy_info.phy_addr = -1; 214 phy_info.direct_connect = -1; 215 phy_info.phy_type = (cvmx_phy_type_t) -1; 216 217 if (!fdt_addr) 218 { 219 cvmx_dprintf("No device tree found.\n"); 220 return phy_info; 221 } 222 aliases = fdt_path_offset(fdt_addr, "/aliases"); 223 if (aliases < 0) { 224 cvmx_dprintf("Error: No /aliases node in device tree.\n"); 225 return phy_info; 226 } 227 if (ipd_port < 0) 228 { 229 int interface_index = ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT; 230 eth = __mix_eth_node(fdt_addr, aliases, interface_index) ; 231 } 232 else 233 { 234 eth = __pip_eth_node(fdt_addr, aliases, ipd_port); 235 } 236 if (eth < 0 ) 237 { 238 cvmx_dprintf("ERROR : cannot find interface for ipd_port=%d\n", ipd_port); 239 return phy_info; 240 } 241 /* Get handle to phy */ 242 phy_handle = (uint32_t *) fdt_getprop(fdt_addr, eth, "phy-handle", NULL); 243 if (!phy_handle) 244 { 245 cvmx_dprintf("ERROR : phy handle not found in device tree ipd_port=%d" 246 "\n", ipd_port); 247 return phy_info; 248 } 249 phandle = cvmx_be32_to_cpu(*phy_handle); 250 phy = fdt_node_offset_by_phandle(fdt_addr, phandle); 251 if (phy < 0) 252 { 253 cvmx_dprintf("ERROR : cannot find phy for ipd_port=%d ret=%d\n", 254 ipd_port, phy); 255 return phy_info; 256 } 257 phy_comaptible_str = (const char *) fdt_getprop(fdt_addr, phy, 258 "compatible", NULL); 259 if (!phy_comaptible_str) 260 { 261 cvmx_dprintf("ERROR : no compatible prop in phy\n"); 262 return phy_info; 263 } 264 if (memcmp("marvell", phy_comaptible_str, strlen("marvell")) == 0) 265 { 266 phy_info.phy_type = MARVELL_GENERIC_PHY; 267 } 268 else if (memcmp("broadcom", phy_comaptible_str, strlen("broadcom")) == 0) 269 { 270 phy_info.phy_type = BROADCOM_GENERIC_PHY; 271 } 272 else 273 { 274 phy_info.phy_type = -1; 275 } 276 277 /* Check if PHY parent is the octeon MDIO bus. Some boards are connected 278 though a MUX and for them direct_connect_to_phy will be 0 */ 279 phy_parent = fdt_parent_offset(fdt_addr, phy); 280 if (phy_parent < 0) 281 { 282 cvmx_dprintf("ERROR : cannot find phy parent for ipd_port=%d ret=%d\n", 283 ipd_port, phy_parent); 284 return phy_info; 285 } 286 ret = fdt_node_check_compatible(fdt_addr, phy_parent, 287 "cavium,octeon-3860-mdio"); 288 if (ret == 0) 289 { 290 phy_info.direct_connect = 1 ; 291 uint32_t *mdio_reg_base = (uint32_t *) fdt_getprop(fdt_addr, phy_parent,"reg",0); 292 if (mdio_reg_base == 0) 293 { 294 cvmx_dprintf("ERROR : unable to get reg property in phy mdio\n"); 295 return phy_info; 296 } 297 mdio_unit = __mdiobus_addr_to_unit(mdio_reg_base[1]); 298 //cvmx_dprintf("phy parent=%s reg_base=%08x unit=%d \n", 299 // fdt_get_name(fdt_addr,phy_parent, NULL), mdio_reg_base[1], mdio_unit); 300 } 301 else 302 { 303 phy_info.direct_connect = 0; 304 /* The PHY is not directly connected to the Octeon MDIO bus. 305 SE doesn't have abstractions for MDIO MUX or MDIO MUX drivers and 306 hence for the non direct cases code will be needed which is 307 board specific. 308 For now the the MDIO Unit is defaulted to 1. 309 */ 310 mdio_unit = 1; 311 } 312 313 phy_addr_ptr = (uint32_t *) fdt_getprop(fdt_addr, phy, "reg", NULL); 314 phy_info.phy_addr = cvmx_be32_to_cpu(*phy_addr_ptr) | mdio_unit << 8; 315 return phy_info; 316 317} 318 319/** 320 * Return the MII PHY address associated with the given IPD 321 * port. The phy address is obtained from the device tree. 322 * 323 * @param ipd_port Octeon IPD port to get the MII address for. 324 * 325 * @return MII PHY address and bus number or -1. 326 */ 327 328int cvmx_helper_board_get_mii_address_from_dt(int ipd_port) 329{ 330 cvmx_phy_info_t phy_info = __get_phy_info_from_dt(ipd_port); 331 return phy_info.phy_addr; 332} 333#endif 334 335/** 336 * Return the MII PHY address associated with the given IPD 337 * port. A result of -1 means there isn't a MII capable PHY 338 * connected to this port. On chips supporting multiple MII 339 * busses the bus number is encoded in bits <15:8>. 340 * 341 * This function must be modified for every new Octeon board. 342 * Internally it uses switch statements based on the cvmx_sysinfo 343 * data to determine board types and revisions. It replies on the 344 * fact that every Octeon board receives a unique board type 345 * enumeration from the bootloader. 346 * 347 * @param ipd_port Octeon IPD port to get the MII address for. 348 * 349 * @return MII PHY address and bus number or -1. 350 */ 351int cvmx_helper_board_get_mii_address(int ipd_port) 352{ 353 /* 354 * Board types we have to know at compile-time. 355 */ 356#ifdef OCTEON_BOARD_CAPK_0100ND 357 switch (ipd_port) { 358 case 0: 359 return 2; 360 case 1: 361 return 3; 362 case 2: 363 /* XXX Switch PHY? */ 364 return -1; 365 default: 366 return -1; 367 } 368#endif 369 370 /* 371 * For board types we can determine at runtime. 372 */ 373 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) 374 return -1; 375#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL)) 376 if (cvmx_sysinfo_get()->fdt_addr) 377 { 378 cvmx_phy_info_t phy_info = __get_phy_info_from_dt(ipd_port); 379 //cvmx_dprintf("ipd_port=%d phy_addr=%d\n", ipd_port, phy_info.phy_addr); 380 if (phy_info.phy_addr >= 0) return phy_info.phy_addr; 381 } 382#endif 383 switch (cvmx_sysinfo_get()->board_type) 384 { 385 case CVMX_BOARD_TYPE_SIM: 386 /* Simulator doesn't have MII */ 387 return -1; 388 case CVMX_BOARD_TYPE_EBT3000: 389 case CVMX_BOARD_TYPE_EBT5800: 390 case CVMX_BOARD_TYPE_THUNDER: 391 case CVMX_BOARD_TYPE_NICPRO2: 392 /* Interface 0 is SPI4, interface 1 is RGMII */ 393 if ((ipd_port >= 16) && (ipd_port < 20)) 394 return ipd_port - 16; 395 else 396 return -1; 397 case CVMX_BOARD_TYPE_LANAI2_A: 398 if (ipd_port == 0) 399 return 0; 400 else 401 return -1; 402 case CVMX_BOARD_TYPE_LANAI2_U: 403 case CVMX_BOARD_TYPE_LANAI2_G: 404 if (ipd_port == 0) 405 return 0x1c; 406 else 407 return -1; 408 case CVMX_BOARD_TYPE_KODAMA: 409 case CVMX_BOARD_TYPE_EBH3100: 410 case CVMX_BOARD_TYPE_HIKARI: 411 case CVMX_BOARD_TYPE_CN3010_EVB_HS5: 412 case CVMX_BOARD_TYPE_CN3005_EVB_HS5: 413 case CVMX_BOARD_TYPE_CN3020_EVB_HS5: 414 /* Port 0 is WAN connected to a PHY, Port 1 is GMII connected to a 415 switch */ 416 if (ipd_port == 0) 417 return 4; 418 else if (ipd_port == 1) 419 return 9; 420 else 421 return -1; 422 case CVMX_BOARD_TYPE_EBH3000: 423 /* Board has dual SPI4 and no PHYs */ 424 return -1; 425 case CVMX_BOARD_TYPE_EBT5810: 426 /* Board has 10g PHYs hooked up to the MII controller on the 427 ** IXF18201 MAC. The 10G PHYS use clause 45 MDIO which the CN58XX 428 ** does not support. All MII accesses go through the IXF part. */ 429 return -1; 430 case CVMX_BOARD_TYPE_EBH5200: 431 case CVMX_BOARD_TYPE_EBH5201: 432 case CVMX_BOARD_TYPE_EBT5200: 433 /* Board has 2 management ports */ 434 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))) 435 return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT; 436 /* Board has 4 SGMII ports. The PHYs start right after the MII 437 ports MII0 = 0, MII1 = 1, SGMII = 2-5 */ 438 if ((ipd_port >= 0) && (ipd_port < 4)) 439 return ipd_port+2; 440 else 441 return -1; 442 case CVMX_BOARD_TYPE_EBH5600: 443 case CVMX_BOARD_TYPE_EBH5601: 444 case CVMX_BOARD_TYPE_EBH5610: 445 /* Board has 1 management port */ 446 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) 447 return 0; 448 /* Board has 8 SGMII ports. 4 connect out, two connect to a switch, 449 and 2 loop to each other */ 450 if ((ipd_port >= 0) && (ipd_port < 4)) 451 return ipd_port+1; 452 else 453 return -1; 454 case CVMX_BOARD_TYPE_EBT5600: 455 /* Board has 1 management port */ 456 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) 457 return 0; 458 /* Board has 1 XAUI port connected to a switch. */ 459 return -1; 460 case CVMX_BOARD_TYPE_EBB5600: 461 { 462 static unsigned char qlm_switch_addr = 0; 463 464 /* Board has 1 management port */ 465 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) 466 return 0; 467 468 /* Board has 8 SGMII ports. 4 connected QLM1, 4 connected QLM3 */ 469 if ((ipd_port >= 0) && (ipd_port < 4)) 470 { 471 if (qlm_switch_addr != 0x3) 472 { 473 qlm_switch_addr = 0x3; /* QLM1 */ 474 cvmx_twsix_write_ia(0, 0x71, 0, 1, 1, qlm_switch_addr); 475 cvmx_wait_usec(11000); /* Let the write complete */ 476 } 477 return ipd_port+1 + (1<<8); 478 } 479 else if ((ipd_port >= 16) && (ipd_port < 20)) 480 { 481 if (qlm_switch_addr != 0xC) 482 { 483 qlm_switch_addr = 0xC; /* QLM3 */ 484 cvmx_twsix_write_ia(0, 0x71, 0, 1, 1, qlm_switch_addr); 485 cvmx_wait_usec(11000); /* Let the write complete */ 486 } 487 return ipd_port-16+1 + (1<<8); 488 } 489 else 490 return -1; 491 } 492 case CVMX_BOARD_TYPE_EBB6300: 493 /* Board has 2 management ports */ 494 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))) 495 return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT + 4; 496 if ((ipd_port >= 0) && (ipd_port < 4)) 497 return ipd_port + 1 + (1<<8); 498 else 499 return -1; 500 case CVMX_BOARD_TYPE_EBB6800: 501 /* Board has 1 management ports */ 502 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) 503 return 6; 504 if (ipd_port >= 0x800 && ipd_port < 0x900) /* QLM 0*/ 505 return 0x101 + ((ipd_port >> 4) & 3); /* SMI 1*/ 506 if (ipd_port >= 0xa00 && ipd_port < 0xb00) /* QLM 2*/ 507 return 0x201 + ((ipd_port >> 4) & 3); /* SMI 2*/ 508 if (ipd_port >= 0xb00 && ipd_port < 0xc00) /* QLM 3*/ 509 return 0x301 + ((ipd_port >> 4) & 3); /* SMI 3*/ 510 if (ipd_port >= 0xc00 && ipd_port < 0xd00) /* QLM 4*/ 511 return 0x001 + ((ipd_port >> 4) & 3); /* SMI 0*/ 512 return -1; 513 case CVMX_BOARD_TYPE_EP6300C: 514 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) 515 return 0x01; 516 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT+1) 517 return 0x02; 518#ifdef CVMX_ENABLE_PKO_FUNCTIONS 519 { 520 int interface = cvmx_helper_get_interface_num(ipd_port); 521 int mode = cvmx_helper_interface_get_mode(interface); 522 if (mode == CVMX_HELPER_INTERFACE_MODE_XAUI) 523 return ipd_port; 524 else if ((ipd_port >= 0) && (ipd_port < 4)) 525 return ipd_port + 3; 526 else 527 return -1; 528 } 529#endif 530 break; 531 case CVMX_BOARD_TYPE_CUST_NB5: 532 if (ipd_port == 2) 533 return 4; 534 else 535 return -1; 536 case CVMX_BOARD_TYPE_NIC_XLE_4G: 537 /* Board has 4 SGMII ports. connected QLM3(interface 1) */ 538 if ((ipd_port >= 16) && (ipd_port < 20)) 539 return ipd_port - 16 + 1; 540 else 541 return -1; 542 case CVMX_BOARD_TYPE_NIC_XLE_10G: 543 case CVMX_BOARD_TYPE_NIC10E: 544 return -1; /* We don't use clause 45 MDIO for anything */ 545 case CVMX_BOARD_TYPE_NIC4E: 546 if (ipd_port >= 0 && ipd_port <= 3) 547 return (ipd_port + 0x1f) & 0x1f; 548 else 549 return -1; 550 case CVMX_BOARD_TYPE_NIC2E: 551 if (ipd_port >= 0 && ipd_port <= 1) 552 return (ipd_port + 1); 553 else 554 return -1; 555 case CVMX_BOARD_TYPE_REDWING: 556 return -1; /* No PHYs connected to Octeon */ 557 case CVMX_BOARD_TYPE_BBGW_REF: 558 return -1; /* No PHYs are connected to Octeon, everything is through switch */ 559 case CVMX_BOARD_TYPE_CUST_WSX16: 560 if (ipd_port >= 0 && ipd_port <= 3) 561 return ipd_port; 562 else if (ipd_port >= 16 && ipd_port <= 19) 563 return ipd_port - 16 + 4; 564 else 565 return -1; 566 567 /* Private vendor-defined boards. */ 568#if defined(OCTEON_VENDOR_LANNER) 569 case CVMX_BOARD_TYPE_CUST_LANNER_MR955: 570 /* Interface 1 is 12 BCM5482S PHYs. */ 571 if ((ipd_port >= 16) && (ipd_port < 28)) 572 return ipd_port - 16; 573 return -1; 574 case CVMX_BOARD_TYPE_CUST_LANNER_MR730: 575 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))) 576 return (ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT) + 0x81; 577 if ((ipd_port >= 0) && (ipd_port < 4)) 578 return ipd_port; 579 return -1; 580 case CVMX_BOARD_TYPE_CUST_LANNER_MR320: 581 case CVMX_BOARD_TYPE_CUST_LANNER_MR321X: 582 /* Port 0 is a Marvell 88E6161 switch, ports 1 and 2 are Marvell 583 88E1111 interfaces. */ 584 switch (ipd_port) { 585 case 0: 586 return 16; 587 case 1: 588 return 1; 589 case 2: 590 return 2; 591 default: 592 return -1; 593 } 594#endif 595#if defined(OCTEON_VENDOR_RADISYS) 596 case CVMX_BOARD_TYPE_CUST_RADISYS_RSYS4GBE: 597 /* No MII. */ 598 return -1; 599#endif 600 } 601 602 /* Some unknown board. Somebody forgot to update this function... */ 603 cvmx_dprintf("%s: Unknown board type %d\n", 604 __FUNCTION__, cvmx_sysinfo_get()->board_type); 605 return -1; 606} 607#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 608EXPORT_SYMBOL(cvmx_helper_board_get_mii_address); 609#endif 610 611/** 612 * @INTERNAL 613 * Get link state of marvell PHY 614 */ 615static cvmx_helper_link_info_t __get_marvell_phy_link_state(int phy_addr) 616{ 617 cvmx_helper_link_info_t result; 618 int phy_status; 619 620 result.u64 = 0; 621 /*All the speed information can be read from register 17 in one go.*/ 622 phy_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17); 623 624 /* If the resolve bit 11 isn't set, see if autoneg is turned off 625 (bit 12, reg 0). The resolve bit doesn't get set properly when 626 autoneg is off, so force it */ 627 if ((phy_status & (1<<11)) == 0) 628 { 629 int auto_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0); 630 if ((auto_status & (1<<12)) == 0) 631 phy_status |= 1<<11; 632 } 633 634 /* Only return a link if the PHY has finished auto negotiation 635 and set the resolved bit (bit 11) */ 636 if (phy_status & (1<<11)) 637 { 638 result.s.link_up = 1; 639 result.s.full_duplex = ((phy_status>>13)&1); 640 switch ((phy_status>>14)&3) 641 { 642 case 0: /* 10 Mbps */ 643 result.s.speed = 10; 644 break; 645 case 1: /* 100 Mbps */ 646 result.s.speed = 100; 647 break; 648 case 2: /* 1 Gbps */ 649 result.s.speed = 1000; 650 break; 651 case 3: /* Illegal */ 652 result.u64 = 0; 653 break; 654 } 655 } 656 return result; 657} 658 659/** 660 * @INTERNAL 661 * Get link state of broadcom PHY 662 */ 663static cvmx_helper_link_info_t __get_broadcom_phy_link_state(int phy_addr) 664{ 665 cvmx_helper_link_info_t result; 666 int phy_status; 667 668 result.u64 = 0; 669 /* Below we are going to read SMI/MDIO register 0x19 which works 670 on Broadcom parts */ 671 phy_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0x19); 672 switch ((phy_status>>8) & 0x7) 673 { 674 case 0: 675 result.u64 = 0; 676 break; 677 case 1: 678 result.s.link_up = 1; 679 result.s.full_duplex = 0; 680 result.s.speed = 10; 681 break; 682 case 2: 683 result.s.link_up = 1; 684 result.s.full_duplex = 1; 685 result.s.speed = 10; 686 break; 687 case 3: 688 result.s.link_up = 1; 689 result.s.full_duplex = 0; 690 result.s.speed = 100; 691 break; 692 case 4: 693 result.s.link_up = 1; 694 result.s.full_duplex = 1; 695 result.s.speed = 100; 696 break; 697 case 5: 698 result.s.link_up = 1; 699 result.s.full_duplex = 1; 700 result.s.speed = 100; 701 break; 702 case 6: 703 result.s.link_up = 1; 704 result.s.full_duplex = 0; 705 result.s.speed = 1000; 706 break; 707 case 7: 708 result.s.link_up = 1; 709 result.s.full_duplex = 1; 710 result.s.speed = 1000; 711 break; 712 } 713 return result; 714} 715 716 717/** 718 * @INTERNAL 719 * Get link state using inband status 720 */ 721static cvmx_helper_link_info_t __get_inband_link_state(int ipd_port) 722{ 723 cvmx_helper_link_info_t result; 724 cvmx_gmxx_rxx_rx_inbnd_t inband_status; 725 int interface = cvmx_helper_get_interface_num(ipd_port); 726 int index = cvmx_helper_get_interface_index_num(ipd_port); 727 728 result.u64 = 0; 729 inband_status.u64 = cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface)); 730 result.s.link_up = inband_status.s.status; 731 result.s.full_duplex = inband_status.s.duplex; 732 switch (inband_status.s.speed) 733 { 734 case 0: /* 10 Mbps */ 735 result.s.speed = 10; 736 break; 737 case 1: /* 100 Mbps */ 738 result.s.speed = 100; 739 break; 740 case 2: /* 1 Gbps */ 741 result.s.speed = 1000; 742 break; 743 case 3: /* Illegal */ 744 result.u64 = 0; 745 break; 746 } 747 return result; 748} 749 750#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL)) 751/** 752 * @INTERNAL 753 * Switch MDIO mux to the specified port. 754 */ 755static int __switch_mdio_mux(int ipd_port) 756{ 757 /* This method is board specific and doesn't use the device tree 758 information as SE doesn't implement MDIO MUX abstration */ 759 switch (cvmx_sysinfo_get()->board_type) 760 { 761 case CVMX_BOARD_TYPE_EBB5600: 762 { 763 static unsigned char qlm_switch_addr = 0; 764 /* Board has 1 management port */ 765 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) 766 return 0; 767 /* Board has 8 SGMII ports. 4 connected QLM1, 4 connected QLM3 */ 768 if ((ipd_port >= 0) && (ipd_port < 4)) 769 { 770 if (qlm_switch_addr != 0x3) 771 { 772 qlm_switch_addr = 0x3; /* QLM1 */ 773 cvmx_twsix_write_ia(0, 0x71, 0, 1, 1, qlm_switch_addr); 774 cvmx_wait_usec(11000); /* Let the write complete */ 775 } 776 return ipd_port+1 + (1<<8); 777 } 778 else if ((ipd_port >= 16) && (ipd_port < 20)) 779 { 780 if (qlm_switch_addr != 0xC) 781 { 782 qlm_switch_addr = 0xC; /* QLM3 */ 783 cvmx_twsix_write_ia(0, 0x71, 0, 1, 1, qlm_switch_addr); 784 cvmx_wait_usec(11000); /* Let the write complete */ 785 } 786 return ipd_port-16+1 + (1<<8); 787 } 788 else 789 return -1; 790 } 791 case CVMX_BOARD_TYPE_EBB6600: 792 { 793 static unsigned char qlm_switch_addr = 0; 794 int old_twsi_switch_reg; 795 /* Board has 2 management ports */ 796 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && 797 (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))) 798 return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT + 4; 799 if ((ipd_port >= 0) && (ipd_port < 4)) /* QLM 2 */ 800 { 801 if (qlm_switch_addr != 2) 802 { 803 int tries; 804 qlm_switch_addr = 2; 805 tries = 3; 806 do { 807 old_twsi_switch_reg = cvmx_twsix_read8(0, 0x70, 0); 808 } while (tries-- > 0 && old_twsi_switch_reg < 0); 809 /* Set I2C MUX to enable port expander */ 810 cvmx_retry_i2c_write(0, 0x70, 0, 1, 0, 8); 811 /* Set selecter to QLM 1 */ 812 cvmx_retry_i2c_write(0, 0x38, 0, 1, 0, 0xff); 813 /* disable port expander */ 814 cvmx_retry_i2c_write(0, 0x70, 0, 1, 0, old_twsi_switch_reg); 815 } 816 return 0x101 + ipd_port; 817 } 818 else if ((ipd_port >= 16) && (ipd_port < 20)) /* QLM 1 */ 819 { 820 if (qlm_switch_addr != 1) 821 { 822 int tries; 823 qlm_switch_addr = 1; 824 tries = 3; 825 do { 826 old_twsi_switch_reg = cvmx_twsix_read8(0, 0x70, 0); 827 } while (tries-- > 0 && old_twsi_switch_reg < 0); 828 /* Set I2C MUX to enable port expander */ 829 cvmx_retry_i2c_write(0, 0x70, 0, 1, 0, 8); 830 /* Set selecter to QLM 2 */ 831 cvmx_retry_i2c_write(0, 0x38, 0, 1, 0, 0xf7); 832 /* disable port expander */ 833 cvmx_retry_i2c_write(0, 0x70, 0, 1, 0, old_twsi_switch_reg); 834 } 835 return 0x101 + (ipd_port - 16); 836 } else 837 return -1; 838 } 839 case CVMX_BOARD_TYPE_EBB6100: 840 { 841 static char gpio_configured = 0; 842 843 if (!gpio_configured) 844 { 845 cvmx_gpio_cfg(3, 1); 846 gpio_configured = 1; 847 } 848 /* Board has 2 management ports */ 849 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && 850 (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))) 851 return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT + 4; 852 if ((ipd_port >= 0) && (ipd_port < 4)) /* QLM 2 */ 853 { 854 cvmx_gpio_set(1ull << 3); 855 return 0x101 + ipd_port; 856 } 857 else if ((ipd_port >= 16) && (ipd_port < 20)) /* QLM 0 */ 858 { 859 cvmx_gpio_clear(1ull << 3); 860 return 0x101 + (ipd_port - 16); 861 } 862 else 863 { 864 printf("%s: Unknown ipd port 0x%x\n", __func__, ipd_port); 865 return -1; 866 } 867 } 868 default: 869 { 870 cvmx_dprintf("ERROR : unexpected mdio switch for board=%08x\n", 871 cvmx_sysinfo_get()->board_type); 872 return -1; 873 } 874 } 875 /* should never get here */ 876 return -1; 877} 878 879/** 880 * @INTERNAL 881 * This function is used ethernet ports link speed. This functions uses the 882 * device tree information to determine the phy address and type of PHY. 883 * The only supproted PHYs are Marvell and Broadcom. 884 * 885 * @param ipd_port IPD input port associated with the port we want to get link 886 * status for. 887 * 888 * @return The ports link status. If the link isn't fully resolved, this must 889 * return zero. 890 */ 891 892cvmx_helper_link_info_t __cvmx_helper_board_link_get_from_dt(int ipd_port) 893{ 894 cvmx_helper_link_info_t result; 895 cvmx_phy_info_t phy_info; 896 897 result.u64 = 0; 898 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) 899 { 900 /* The simulator gives you a simulated 1Gbps full duplex link */ 901 result.s.link_up = 1; 902 result.s.full_duplex = 1; 903 result.s.speed = 1000; 904 return result; 905 } 906 phy_info = __get_phy_info_from_dt(ipd_port); 907 //cvmx_dprintf("ipd_port=%d phy_addr=%d dc=%d type=%d \n", ipd_port, 908 // phy_info.phy_addr, phy_info.direct_connect, phy_info.phy_type); 909 if (phy_info.phy_addr < 0) return result; 910 911 if (phy_info.direct_connect == 0) 912 __switch_mdio_mux(ipd_port); 913 switch(phy_info.phy_type) 914 { 915 case BROADCOM_GENERIC_PHY: 916 result = __get_broadcom_phy_link_state(phy_info.phy_addr); 917 break; 918 case MARVELL_GENERIC_PHY: 919 result = __get_marvell_phy_link_state(phy_info.phy_addr); 920 break; 921 default: 922 result = __get_inband_link_state(ipd_port); 923 } 924 return result; 925 926} 927#endif 928 929/** 930 * @INTERNAL 931 * This function invokes __cvmx_helper_board_link_get_from_dt when device tree 932 * info is available. When the device tree information is not available then 933 * this function is the board specific method of determining an 934 * ethernet ports link speed. Most Octeon boards have Marvell PHYs 935 * and are handled by the fall through case. This function must be 936 * updated for boards that don't have the normal Marvell PHYs. 937 * 938 * This function must be modified for every new Octeon board. 939 * Internally it uses switch statements based on the cvmx_sysinfo 940 * data to determine board types and revisions. It relies on the 941 * fact that every Octeon board receives a unique board type 942 * enumeration from the bootloader. 943 * 944 * @param ipd_port IPD input port associated with the port we want to get link 945 * status for. 946 * 947 * @return The ports link status. If the link isn't fully resolved, this must 948 * return zero. 949 */ 950cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port) 951{ 952 cvmx_helper_link_info_t result; 953 int phy_addr; 954 int is_broadcom_phy = 0; 955 956#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL)) 957 if (cvmx_sysinfo_get()->fdt_addr) 958 { 959 return __cvmx_helper_board_link_get_from_dt(ipd_port); 960 } 961#endif 962 963 /* Give the user a chance to override the processing of this function */ 964 if (cvmx_override_board_link_get) 965 return cvmx_override_board_link_get(ipd_port); 966 967 /* Unless we fix it later, all links are defaulted to down */ 968 result.u64 = 0; 969 970#if !defined(OCTEON_BOARD_CAPK_0100ND) 971 /* This switch statement should handle all ports that either don't use 972 Marvell PHYS, or don't support in-band status */ 973 switch (cvmx_sysinfo_get()->board_type) 974 { 975 case CVMX_BOARD_TYPE_SIM: 976 /* The simulator gives you a simulated 1Gbps full duplex link */ 977 result.s.link_up = 1; 978 result.s.full_duplex = 1; 979 result.s.speed = 1000; 980 return result; 981 case CVMX_BOARD_TYPE_LANAI2_A: 982 case CVMX_BOARD_TYPE_LANAI2_U: 983 case CVMX_BOARD_TYPE_LANAI2_G: 984 break; 985 case CVMX_BOARD_TYPE_EBH3100: 986 case CVMX_BOARD_TYPE_CN3010_EVB_HS5: 987 case CVMX_BOARD_TYPE_CN3005_EVB_HS5: 988 case CVMX_BOARD_TYPE_CN3020_EVB_HS5: 989 /* Port 1 on these boards is always Gigabit */ 990 if (ipd_port == 1) 991 { 992 result.s.link_up = 1; 993 result.s.full_duplex = 1; 994 result.s.speed = 1000; 995 return result; 996 } 997 /* Fall through to the generic code below */ 998 break; 999 case CVMX_BOARD_TYPE_EBT5600: 1000 case CVMX_BOARD_TYPE_EBH5600: 1001 case CVMX_BOARD_TYPE_EBH5601: 1002 case CVMX_BOARD_TYPE_EBH5610: 1003 /* Board has 1 management ports */ 1004 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) 1005 is_broadcom_phy = 1; 1006 break; 1007 case CVMX_BOARD_TYPE_EBH5200: 1008 case CVMX_BOARD_TYPE_EBH5201: 1009 case CVMX_BOARD_TYPE_EBT5200: 1010 /* Board has 2 management ports */ 1011 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))) 1012 is_broadcom_phy = 1; 1013 break; 1014 case CVMX_BOARD_TYPE_EBB6100: 1015 case CVMX_BOARD_TYPE_EBB6300: /* Only for MII mode, with PHY addresses 0/1. Default is RGMII*/ 1016 case CVMX_BOARD_TYPE_EBB6600: /* Only for MII mode, with PHY addresses 0/1. Default is RGMII*/ 1017 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)) 1018 && cvmx_helper_board_get_mii_address(ipd_port) >= 0 && cvmx_helper_board_get_mii_address(ipd_port) <= 1) 1019 is_broadcom_phy = 1; 1020 break; 1021 case CVMX_BOARD_TYPE_EP6300C: 1022 is_broadcom_phy = 1; 1023 break; 1024 case CVMX_BOARD_TYPE_CUST_NB5: 1025 /* Port 1 on these boards is always Gigabit */ 1026 if (ipd_port == 1) 1027 { 1028 result.s.link_up = 1; 1029 result.s.full_duplex = 1; 1030 result.s.speed = 1000; 1031 return result; 1032 } 1033 else /* The other port uses a broadcom PHY */ 1034 is_broadcom_phy = 1; 1035 break; 1036 case CVMX_BOARD_TYPE_BBGW_REF: 1037 /* Port 1 on these boards is always Gigabit */ 1038 if (ipd_port == 2) 1039 { 1040 /* Port 2 is not hooked up */ 1041 result.u64 = 0; 1042 return result; 1043 } 1044 else 1045 { 1046 /* Ports 0 and 1 connect to the switch */ 1047 result.s.link_up = 1; 1048 result.s.full_duplex = 1; 1049 result.s.speed = 1000; 1050 return result; 1051 } 1052 case CVMX_BOARD_TYPE_NIC4E: 1053 case CVMX_BOARD_TYPE_NIC2E: 1054 is_broadcom_phy = 1; 1055 break; 1056 /* Private vendor-defined boards. */ 1057#if defined(OCTEON_VENDOR_LANNER) 1058 case CVMX_BOARD_TYPE_CUST_LANNER_MR730: 1059 /* Ports are BCM5482S */ 1060 is_broadcom_phy = 1; 1061 break; 1062 case CVMX_BOARD_TYPE_CUST_LANNER_MR320: 1063 case CVMX_BOARD_TYPE_CUST_LANNER_MR321X: 1064 /* Port 0 connects to the switch */ 1065 if (ipd_port == 0) 1066 { 1067 result.s.link_up = 1; 1068 result.s.full_duplex = 1; 1069 result.s.speed = 1000; 1070 return result; 1071 } 1072 break; 1073#endif 1074 } 1075#endif 1076 1077 phy_addr = cvmx_helper_board_get_mii_address(ipd_port); 1078 //cvmx_dprintf("ipd_port=%d phy_addr=%d broadcom=%d\n", 1079 // ipd_port, phy_addr, is_broadcom_phy); 1080 if (phy_addr != -1) 1081 { 1082 if (is_broadcom_phy) 1083 { 1084 result = __get_broadcom_phy_link_state(phy_addr); 1085 } 1086 else 1087 { 1088 /* This code assumes we are using a Marvell Gigabit PHY. */ 1089 result = __get_marvell_phy_link_state(phy_addr); 1090 } 1091 } 1092 else if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN58XX) 1093 || OCTEON_IS_MODEL(OCTEON_CN50XX)) 1094 { 1095 /* We don't have a PHY address, so attempt to use in-band status. It is 1096 really important that boards not supporting in-band status never get 1097 here. Reading broken in-band status tends to do bad things */ 1098 result = __get_inband_link_state(ipd_port); 1099 } 1100 else 1101 { 1102 /* We don't have a PHY address and we don't have in-band status. There 1103 is no way to determine the link speed. Return down assuming this 1104 port isn't wired */ 1105 result.u64 = 0; 1106 } 1107 1108 /* If link is down, return all fields as zero. */ 1109 if (!result.s.link_up) 1110 result.u64 = 0; 1111 1112 return result; 1113} 1114 1115 1116/** 1117 * This function as a board specific method of changing the PHY 1118 * speed, duplex, and autonegotiation. This programs the PHY and 1119 * not Octeon. This can be used to force Octeon's links to 1120 * specific settings. 1121 * 1122 * @param phy_addr The address of the PHY to program 1123 * @param link_flags 1124 * Flags to control autonegotiation. Bit 0 is autonegotiation 1125 * enable/disable to maintain backward compatibility. 1126 * @param link_info Link speed to program. If the speed is zero and autonegotiation 1127 * is enabled, all possible negotiation speeds are advertised. 1128 * 1129 * @return Zero on success, negative on failure 1130 */ 1131int cvmx_helper_board_link_set_phy(int phy_addr, cvmx_helper_board_set_phy_link_flags_types_t link_flags, 1132 cvmx_helper_link_info_t link_info) 1133{ 1134 1135 /* Set the flow control settings based on link_flags */ 1136 if ((link_flags & set_phy_link_flags_flow_control_mask) != set_phy_link_flags_flow_control_dont_touch) 1137 { 1138 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; 1139 reg_autoneg_adver.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER); 1140 reg_autoneg_adver.s.asymmetric_pause = (link_flags & set_phy_link_flags_flow_control_mask) == set_phy_link_flags_flow_control_enable; 1141 reg_autoneg_adver.s.pause = (link_flags & set_phy_link_flags_flow_control_mask) == set_phy_link_flags_flow_control_enable; 1142 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER, reg_autoneg_adver.u16); 1143 } 1144 1145 /* If speed isn't set and autoneg is on advertise all supported modes */ 1146 if ((link_flags & set_phy_link_flags_autoneg) && (link_info.s.speed == 0)) 1147 { 1148 cvmx_mdio_phy_reg_control_t reg_control; 1149 cvmx_mdio_phy_reg_status_t reg_status; 1150 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; 1151 cvmx_mdio_phy_reg_extended_status_t reg_extended_status; 1152 cvmx_mdio_phy_reg_control_1000_t reg_control_1000; 1153 1154 reg_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_STATUS); 1155 reg_autoneg_adver.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER); 1156 reg_autoneg_adver.s.advert_100base_t4 = reg_status.s.capable_100base_t4; 1157 reg_autoneg_adver.s.advert_10base_tx_full = reg_status.s.capable_10_full; 1158 reg_autoneg_adver.s.advert_10base_tx_half = reg_status.s.capable_10_half; 1159 reg_autoneg_adver.s.advert_100base_tx_full = reg_status.s.capable_100base_x_full; 1160 reg_autoneg_adver.s.advert_100base_tx_half = reg_status.s.capable_100base_x_half; 1161 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER, reg_autoneg_adver.u16); 1162 if (reg_status.s.capable_extended_status) 1163 { 1164 reg_extended_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_EXTENDED_STATUS); 1165 reg_control_1000.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000); 1166 reg_control_1000.s.advert_1000base_t_full = reg_extended_status.s.capable_1000base_t_full; 1167 reg_control_1000.s.advert_1000base_t_half = reg_extended_status.s.capable_1000base_t_half; 1168 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000, reg_control_1000.u16); 1169 } 1170 reg_control.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL); 1171 reg_control.s.autoneg_enable = 1; 1172 reg_control.s.restart_autoneg = 1; 1173 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); 1174 } 1175 else if ((link_flags & set_phy_link_flags_autoneg)) 1176 { 1177 cvmx_mdio_phy_reg_control_t reg_control; 1178 cvmx_mdio_phy_reg_status_t reg_status; 1179 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; 1180 cvmx_mdio_phy_reg_control_1000_t reg_control_1000; 1181 1182 reg_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_STATUS); 1183 reg_autoneg_adver.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER); 1184 reg_autoneg_adver.s.advert_100base_t4 = 0; 1185 reg_autoneg_adver.s.advert_10base_tx_full = 0; 1186 reg_autoneg_adver.s.advert_10base_tx_half = 0; 1187 reg_autoneg_adver.s.advert_100base_tx_full = 0; 1188 reg_autoneg_adver.s.advert_100base_tx_half = 0; 1189 if (reg_status.s.capable_extended_status) 1190 { 1191 reg_control_1000.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000); 1192 reg_control_1000.s.advert_1000base_t_full = 0; 1193 reg_control_1000.s.advert_1000base_t_half = 0; 1194 } 1195 switch (link_info.s.speed) 1196 { 1197 case 10: 1198 reg_autoneg_adver.s.advert_10base_tx_full = link_info.s.full_duplex; 1199 reg_autoneg_adver.s.advert_10base_tx_half = !link_info.s.full_duplex; 1200 break; 1201 case 100: 1202 reg_autoneg_adver.s.advert_100base_tx_full = link_info.s.full_duplex; 1203 reg_autoneg_adver.s.advert_100base_tx_half = !link_info.s.full_duplex; 1204 break; 1205 case 1000: 1206 reg_control_1000.s.advert_1000base_t_full = link_info.s.full_duplex; 1207 reg_control_1000.s.advert_1000base_t_half = !link_info.s.full_duplex; 1208 break; 1209 } 1210 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER, reg_autoneg_adver.u16); 1211 if (reg_status.s.capable_extended_status) 1212 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000, reg_control_1000.u16); 1213 reg_control.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL); 1214 reg_control.s.autoneg_enable = 1; 1215 reg_control.s.restart_autoneg = 1; 1216 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); 1217 } 1218 else 1219 { 1220 cvmx_mdio_phy_reg_control_t reg_control; 1221 reg_control.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL); 1222 reg_control.s.autoneg_enable = 0; 1223 reg_control.s.restart_autoneg = 1; 1224 reg_control.s.duplex = link_info.s.full_duplex; 1225 if (link_info.s.speed == 1000) 1226 { 1227 reg_control.s.speed_msb = 1; 1228 reg_control.s.speed_lsb = 0; 1229 } 1230 else if (link_info.s.speed == 100) 1231 { 1232 reg_control.s.speed_msb = 0; 1233 reg_control.s.speed_lsb = 1; 1234 } 1235 else if (link_info.s.speed == 10) 1236 { 1237 reg_control.s.speed_msb = 0; 1238 reg_control.s.speed_lsb = 0; 1239 } 1240 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); 1241 } 1242 return 0; 1243} 1244 1245 1246/** 1247 * @INTERNAL 1248 * This function is called by cvmx_helper_interface_probe() after it 1249 * determines the number of ports Octeon can support on a specific 1250 * interface. This function is the per board location to override 1251 * this value. It is called with the number of ports Octeon might 1252 * support and should return the number of actual ports on the 1253 * board. 1254 * 1255 * This function must be modified for every new Octeon board. 1256 * Internally it uses switch statements based on the cvmx_sysinfo 1257 * data to determine board types and revisions. It relies on the 1258 * fact that every Octeon board receives a unique board type 1259 * enumeration from the bootloader. 1260 * 1261 * @param interface Interface to probe 1262 * @param supported_ports 1263 * Number of ports Octeon supports. 1264 * 1265 * @return Number of ports the actual board supports. Many times this will 1266 * simple be "support_ports". 1267 */ 1268int __cvmx_helper_board_interface_probe(int interface, int supported_ports) 1269{ 1270 switch (cvmx_sysinfo_get()->board_type) 1271 { 1272 case CVMX_BOARD_TYPE_CN3005_EVB_HS5: 1273 case CVMX_BOARD_TYPE_LANAI2_A: 1274 case CVMX_BOARD_TYPE_LANAI2_U: 1275 case CVMX_BOARD_TYPE_LANAI2_G: 1276 if (interface == 0) 1277 return 2; 1278 break; 1279 case CVMX_BOARD_TYPE_BBGW_REF: 1280 if (interface == 0) 1281 return 2; 1282 break; 1283 case CVMX_BOARD_TYPE_NIC_XLE_4G: 1284 if (interface == 0) 1285 return 0; 1286 break; 1287 /* The 2nd interface on the EBH5600 is connected to the Marvel switch, 1288 which we don't support. Disable ports connected to it */ 1289 case CVMX_BOARD_TYPE_EBH5600: 1290 if (interface == 1) 1291 return 0; 1292 break; 1293 case CVMX_BOARD_TYPE_EBB5600: 1294#ifdef CVMX_ENABLE_PKO_FUNCTIONS 1295 if (cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_PICMG) 1296 return 0; 1297#endif 1298 break; 1299 case CVMX_BOARD_TYPE_EBT5600: 1300 /* Disable loopback. */ 1301 if (interface == 3) 1302 return 0; 1303 break; 1304 case CVMX_BOARD_TYPE_EBT5810: 1305 return 1; /* Two ports on each SPI: 1 hooked to MAC, 1 loopback 1306 ** Loopback disabled by default. */ 1307 case CVMX_BOARD_TYPE_NIC2E: 1308 if (interface == 0) 1309 return 2; 1310#if defined(OCTEON_VENDOR_LANNER) 1311 case CVMX_BOARD_TYPE_CUST_LANNER_MR955: 1312 if (interface == 1) 1313 return 12; 1314 break; 1315#endif 1316 } 1317#ifdef CVMX_BUILD_FOR_UBOOT 1318 if (CVMX_HELPER_INTERFACE_MODE_SPI == cvmx_helper_interface_get_mode(interface) && getenv("disable_spi")) 1319 return 0; 1320#endif 1321 return supported_ports; 1322} 1323 1324 1325/** 1326 * @INTERNAL 1327 * Enable packet input/output from the hardware. This function is 1328 * called after by cvmx_helper_packet_hardware_enable() to 1329 * perform board specific initialization. For most boards 1330 * nothing is needed. 1331 * 1332 * @param interface Interface to enable 1333 * 1334 * @return Zero on success, negative on failure 1335 */ 1336int __cvmx_helper_board_hardware_enable(int interface) 1337{ 1338 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5) 1339 { 1340 if (interface == 0) 1341 { 1342 /* Different config for switch port */ 1343 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0); 1344 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); 1345 /* Boards with gigabit WAN ports need a different setting that is 1346 compatible with 100 Mbit settings */ 1347 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 0xc); 1348 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0xc); 1349 } 1350 } 1351 else if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_LANAI2_U) 1352 { 1353 if (interface == 0) 1354 { 1355 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 16); 1356 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 16); 1357 } 1358 } 1359 else if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3010_EVB_HS5) 1360 { 1361 /* Broadcom PHYs require different ASX clocks. Unfortunately 1362 many customer don't define a new board Id and simply 1363 mangle the CN3010_EVB_HS5 */ 1364 if (interface == 0) 1365 { 1366 /* Some customers boards use a hacked up bootloader that identifies them as 1367 ** CN3010_EVB_HS5 evaluation boards. This leads to all kinds of configuration 1368 ** problems. Detect one case, and print warning, while trying to do the right thing. 1369 */ 1370 int phy_addr = cvmx_helper_board_get_mii_address(0); 1371 if (phy_addr != -1) 1372 { 1373 int phy_identifier = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0x2); 1374 /* Is it a Broadcom PHY? */ 1375 if (phy_identifier == 0x0143) 1376 { 1377 cvmx_dprintf("\n"); 1378 cvmx_dprintf("ERROR:\n"); 1379 cvmx_dprintf("ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found.\n"); 1380 cvmx_dprintf("ERROR: The board type is mis-configured, and software malfunctions are likely.\n"); 1381 cvmx_dprintf("ERROR: All boards require a unique board type to identify them.\n"); 1382 cvmx_dprintf("ERROR:\n"); 1383 cvmx_dprintf("\n"); 1384 cvmx_wait(1000000000); 1385 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 5); 1386 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 5); 1387 } 1388 } 1389 } 1390 } 1391 return 0; 1392} 1393 1394 1395/** 1396 * @INTERNAL 1397 * Gets the clock type used for the USB block based on board type. 1398 * Used by the USB code for auto configuration of clock type. 1399 * 1400 * @return USB clock type enumeration 1401 */ 1402cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void) 1403{ 1404#if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL)) 1405 const void *fdt_addr = CASTPTR(const void *, cvmx_sysinfo_get()->fdt_addr); 1406 int nodeoffset; 1407 const void *nodep; 1408 int len; 1409 uint32_t speed = 0; 1410 const char *type = NULL; 1411 1412 if (fdt_addr) 1413 { 1414 nodeoffset = fdt_path_offset(fdt_addr, "/soc/uctl"); 1415 if (nodeoffset < 0) 1416 nodeoffset = fdt_path_offset(fdt_addr, "/soc/usbn"); 1417 1418 if (nodeoffset >= 0) 1419 { 1420 nodep = fdt_getprop(fdt_addr, nodeoffset, "refclk-type", &len); 1421 if (nodep != NULL && len > 0) 1422 type = (const char *)nodep; 1423 else 1424 type = "unknown"; 1425 nodep = fdt_getprop(fdt_addr, nodeoffset, "refclk-frequency", &len); 1426 if (nodep != NULL && len == sizeof(uint32_t)) 1427 speed = fdt32_to_cpu(*(int *)nodep); 1428 else 1429 speed = 0; 1430 if (!strcmp(type, "crystal")) 1431 { 1432 if (speed == 0 || speed == 12000000) 1433 return USB_CLOCK_TYPE_CRYSTAL_12; 1434 else 1435 printf("Warning: invalid crystal speed for USB clock type in FDT\n"); 1436 } 1437 else if (!strcmp(type, "external")) 1438 { 1439 switch (speed) { 1440 case 12000000: 1441 return USB_CLOCK_TYPE_REF_12; 1442 case 24000000: 1443 return USB_CLOCK_TYPE_REF_24; 1444 case 0: 1445 case 48000000: 1446 return USB_CLOCK_TYPE_REF_48; 1447 default: 1448 printf("Warning: invalid USB clock speed of %u hz in FDT\n", speed); 1449 } 1450 } 1451 else 1452 printf("Warning: invalid USB reference clock type \"%s\" in FDT\n", type ? type : "NULL"); 1453 } 1454 } 1455#endif 1456 switch (cvmx_sysinfo_get()->board_type) 1457 { 1458 case CVMX_BOARD_TYPE_BBGW_REF: 1459 case CVMX_BOARD_TYPE_LANAI2_A: 1460 case CVMX_BOARD_TYPE_LANAI2_U: 1461 case CVMX_BOARD_TYPE_LANAI2_G: 1462#if defined(OCTEON_VENDOR_LANNER) 1463 case CVMX_BOARD_TYPE_CUST_LANNER_MR320: 1464 case CVMX_BOARD_TYPE_CUST_LANNER_MR321X: 1465#endif 1466#if defined(OCTEON_BOARD_CAPK_0100ND) 1467 case CVMX_BOARD_TYPE_CN3010_EVB_HS5: 1468#endif 1469 case CVMX_BOARD_TYPE_NIC10E_66: 1470 return USB_CLOCK_TYPE_CRYSTAL_12; 1471 case CVMX_BOARD_TYPE_NIC10E: 1472 return USB_CLOCK_TYPE_REF_12; 1473 default: 1474 break; 1475 } 1476 if (OCTEON_IS_MODEL(OCTEON_CN6XXX) /* Most boards except NIC10e use a 12MHz crystal */ 1477 || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) 1478 return USB_CLOCK_TYPE_CRYSTAL_12; 1479 return USB_CLOCK_TYPE_REF_48; 1480} 1481 1482 1483/** 1484 * @INTERNAL 1485 * Adjusts the number of available USB ports on Octeon based on board 1486 * specifics. 1487 * 1488 * @param supported_ports expected number of ports based on chip type; 1489 * 1490 * 1491 * @return number of available usb ports, based on board specifics. 1492 * Return value is supported_ports if function does not 1493 * override. 1494 */ 1495int __cvmx_helper_board_usb_get_num_ports(int supported_ports) 1496{ 1497 switch (cvmx_sysinfo_get()->board_type) 1498 { 1499 case CVMX_BOARD_TYPE_NIC_XLE_4G: 1500 case CVMX_BOARD_TYPE_NIC2E: 1501 return 0; 1502 } 1503 1504 return supported_ports; 1505} 1506 1507 1508