cvmx-helper-board.c revision 215990
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * Helper functions to abstract board specific data about 50 * network ports from the rest of the cvmx-helper files. 51 * 52 * <hr>$Revision: 49627 $<hr> 53 */ 54#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 55#include <linux/module.h> 56#include <asm/octeon/cvmx.h> 57#include <asm/octeon/cvmx-bootinfo.h> 58#include <asm/octeon/cvmx-smix-defs.h> 59#include <asm/octeon/cvmx-gmxx-defs.h> 60#include <asm/octeon/cvmx-asxx-defs.h> 61#include <asm/octeon/cvmx-mdio.h> 62#include <asm/octeon/cvmx-helper.h> 63#include <asm/octeon/cvmx-helper-util.h> 64#include <asm/octeon/cvmx-helper-board.h> 65#include <asm/octeon/cvmx-twsi.h> 66#else 67#include "cvmx.h" 68#include "cvmx-app-init.h" 69#include "cvmx-sysinfo.h" 70#include "cvmx-twsi.h" 71#include "cvmx-mdio.h" 72#include "cvmx-helper.h" 73#include "cvmx-helper-util.h" 74#include "cvmx-helper-board.h" 75#endif 76 77/** 78 * cvmx_override_board_link_get(int ipd_port) is a function 79 * pointer. It is meant to allow customization of the process of 80 * talking to a PHY to determine link speed. It is called every 81 * time a PHY must be polled for link status. Users should set 82 * this pointer to a function before calling any cvmx-helper 83 * operations. 84 */ 85CVMX_SHARED cvmx_helper_link_info_t (*cvmx_override_board_link_get)(int ipd_port) = NULL; 86 87/** 88 * Return the MII PHY address associated with the given IPD 89 * port. A result of -1 means there isn't a MII capable PHY 90 * connected to this port. On chips supporting multiple MII 91 * busses the bus number is encoded in bits <15:8>. 92 * 93 * This function must be modified for every new Octeon board. 94 * Internally it uses switch statements based on the cvmx_sysinfo 95 * data to determine board types and revisions. It replies on the 96 * fact that every Octeon board receives a unique board type 97 * enumeration from the bootloader. 98 * 99 * @param ipd_port Octeon IPD port to get the MII address for. 100 * 101 * @return MII PHY address and bus number or -1. 102 */ 103int cvmx_helper_board_get_mii_address(int ipd_port) 104{ 105 /* 106 * Board types we have to know at compile-time. 107 */ 108#ifdef OCTEON_BOARD_CAPK_0100ND 109 switch (ipd_port) { 110 case 0: 111 return 2; 112 case 1: 113 return 3; 114 case 2: 115 /* XXX Switch PHY? */ 116 return -1; 117 default: 118 return -1; 119 } 120#endif 121 122 /* 123 * For board types we can determine at runtime. 124 */ 125 switch (cvmx_sysinfo_get()->board_type) 126 { 127 case CVMX_BOARD_TYPE_SIM: 128 /* Simulator doesn't have MII */ 129 return -1; 130 case CVMX_BOARD_TYPE_EBT3000: 131 case CVMX_BOARD_TYPE_EBT5800: 132 case CVMX_BOARD_TYPE_THUNDER: 133 case CVMX_BOARD_TYPE_NICPRO2: 134 /* Interface 0 is SPI4, interface 1 is RGMII */ 135 if ((ipd_port >= 16) && (ipd_port < 20)) 136 return ipd_port - 16; 137 else 138 return -1; 139 case CVMX_BOARD_TYPE_LANAI2_A: 140 if (ipd_port == 0) 141 return 0; 142 else 143 return -1; 144 case CVMX_BOARD_TYPE_LANAI2_U: 145 case CVMX_BOARD_TYPE_LANAI2_G: 146 if (ipd_port == 0) 147 return 0x1c; 148 else 149 return -1; 150 case CVMX_BOARD_TYPE_KODAMA: 151 case CVMX_BOARD_TYPE_EBH3100: 152 case CVMX_BOARD_TYPE_HIKARI: 153 case CVMX_BOARD_TYPE_CN3010_EVB_HS5: 154 case CVMX_BOARD_TYPE_CN3005_EVB_HS5: 155 case CVMX_BOARD_TYPE_CN3020_EVB_HS5: 156 /* Port 0 is WAN connected to a PHY, Port 1 is GMII connected to a 157 switch */ 158 if (ipd_port == 0) 159 return 4; 160 else if (ipd_port == 1) 161 return 9; 162 else 163 return -1; 164 case CVMX_BOARD_TYPE_NAC38: 165 /* Board has 8 RGMII ports PHYs are 0-7 */ 166 if ((ipd_port >= 0) && (ipd_port < 4)) 167 return ipd_port; 168 else if ((ipd_port >= 16) && (ipd_port < 20)) 169 return ipd_port - 16 + 4; 170 else 171 return -1; 172 case CVMX_BOARD_TYPE_EBH3000: 173 /* Board has dual SPI4 and no PHYs */ 174 return -1; 175 case CVMX_BOARD_TYPE_EBT5810: 176 /* Board has 10g PHYs hooked up to the MII controller on the 177 ** IXF18201 MAC. The 10G PHYS use clause 45 MDIO which the CN58XX 178 ** does not support. All MII accesses go through the IXF part. */ 179 return -1; 180 case CVMX_BOARD_TYPE_EBH5200: 181 case CVMX_BOARD_TYPE_EBH5201: 182 case CVMX_BOARD_TYPE_EBT5200: 183 /* Board has 2 management ports */ 184 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))) 185 return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT; 186 /* Board has 4 SGMII ports. The PHYs start right after the MII 187 ports MII0 = 0, MII1 = 1, SGMII = 2-5 */ 188 if ((ipd_port >= 0) && (ipd_port < 4)) 189 return ipd_port+2; 190 else 191 return -1; 192 case CVMX_BOARD_TYPE_EBH5600: 193 case CVMX_BOARD_TYPE_EBH5601: 194 case CVMX_BOARD_TYPE_EBH5610: 195 /* Board has 1 management port */ 196 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) 197 return 0; 198 /* Board has 8 SGMII ports. 4 connect out, two connect to a switch, 199 and 2 loop to each other */ 200 if ((ipd_port >= 0) && (ipd_port < 4)) 201 return ipd_port+1; 202 else 203 return -1; 204 case CVMX_BOARD_TYPE_EBB5600: 205 { 206 static unsigned char qlm_switch_addr = 0; 207 208 /* Board has 1 management port */ 209 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) 210 return 0; 211 212 /* Board has 8 SGMII ports. 4 connected QLM1, 4 connected QLM3 */ 213 if ((ipd_port >= 0) && (ipd_port < 4)) 214 { 215 if (qlm_switch_addr != 0x3) 216 { 217 qlm_switch_addr = 0x3; /* QLM1 */ 218 cvmx_twsix_write_ia(0, 0x71, 0, 1, 1, qlm_switch_addr); 219 cvmx_wait_usec(11000); /* Let the write complete */ 220 } 221 return ipd_port+1 + (1<<8); 222 } 223 else if ((ipd_port >= 16) && (ipd_port < 20)) 224 { 225 if (qlm_switch_addr != 0xC) 226 { 227 qlm_switch_addr = 0xC; /* QLM3 */ 228 cvmx_twsix_write_ia(0, 0x71, 0, 1, 1, qlm_switch_addr); 229 cvmx_wait_usec(11000); /* Let the write complete */ 230 } 231 return ipd_port-16+1 + (1<<8); 232 } 233 else 234 return -1; 235 } 236 case CVMX_BOARD_TYPE_EBB6300: 237 /* Board has 2 management ports */ 238 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))) 239 return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT + 4; 240 if ((ipd_port >= 0) && (ipd_port < 4)) 241 return ipd_port + 1 + (1<<8); 242 else 243 return -1; 244 case CVMX_BOARD_TYPE_CUST_NB5: 245 if (ipd_port == 2) 246 return 4; 247 else 248 return -1; 249 case CVMX_BOARD_TYPE_NIC_XLE_4G: 250 /* Board has 4 SGMII ports. connected QLM3(interface 1) */ 251 if ((ipd_port >= 16) && (ipd_port < 20)) 252 return ipd_port - 16 + 1; 253 else 254 return -1; 255 case CVMX_BOARD_TYPE_NIC_XLE_10G: 256 return -1; /* We don't use clause 45 MDIO for anything */ 257 case CVMX_BOARD_TYPE_BBGW_REF: 258 return -1; /* No PHYs are connected to Octeon, everything is through switch */ 259 case CVMX_BOARD_TYPE_CUST_WSX16: 260 if (ipd_port >= 0 && ipd_port <= 3) 261 return ipd_port; 262 else if (ipd_port >= 16 && ipd_port <= 19) 263 return ipd_port - 16 + 4; 264 else 265 return -1; 266 267 /* Private vendor-defined boards. */ 268#if defined(OCTEON_VENDOR_LANNER) 269 case CVMX_BOARD_TYPE_CUST_LANNER_MR955: 270 /* Interface 1 is 12 BCM5482S PHYs. */ 271 if ((ipd_port >= 16) && (ipd_port < 28)) 272 return ipd_port - 16; 273 return -1; 274 case CVMX_BOARD_TYPE_CUST_LANNER_MR730: 275 if ((ipd_port >= 0) && (ipd_port < 4)) 276 return ipd_port; 277 return -1; 278 case CVMX_BOARD_TYPE_CUST_LANNER_MR320: 279 /* Port 0 is a Marvell 88E6161 switch, ports 1 and 2 are Marvell 280 88E1111 interfaces. */ 281 switch (ipd_port) { 282 case 0: 283 return 16; 284 case 1: 285 return 1; 286 case 2: 287 return 2; 288 default: 289 return -1; 290 } 291#endif 292 } 293 294 /* Some unknown board. Somebody forgot to update this function... */ 295 cvmx_dprintf("%s: Unknown board type %d\n", 296 __FUNCTION__, cvmx_sysinfo_get()->board_type); 297 return -1; 298} 299#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 300EXPORT_SYMBOL(cvmx_helper_board_get_mii_address); 301#endif 302 303 304/** 305 * @INTERNAL 306 * This function is the board specific method of determining an 307 * ethernet ports link speed. Most Octeon boards have Marvell PHYs 308 * and are handled by the fall through case. This function must be 309 * updated for boards that don't have the normal Marvell PHYs. 310 * 311 * This function must be modified for every new Octeon board. 312 * Internally it uses switch statements based on the cvmx_sysinfo 313 * data to determine board types and revisions. It relies on the 314 * fact that every Octeon board receives a unique board type 315 * enumeration from the bootloader. 316 * 317 * @param ipd_port IPD input port associated with the port we want to get link 318 * status for. 319 * 320 * @return The ports link status. If the link isn't fully resolved, this must 321 * return zero. 322 */ 323cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port) 324{ 325 cvmx_helper_link_info_t result; 326 int phy_addr; 327 int is_broadcom_phy = 0; 328 329 /* Give the user a chance to override the processing of this function */ 330 if (cvmx_override_board_link_get) 331 return cvmx_override_board_link_get(ipd_port); 332 333 /* Unless we fix it later, all links are defaulted to down */ 334 result.u64 = 0; 335 336#if !defined(OCTEON_BOARD_CAPK_0100ND) 337 /* This switch statement should handle all ports that either don't use 338 Marvell PHYS, or don't support in-band status */ 339 switch (cvmx_sysinfo_get()->board_type) 340 { 341 case CVMX_BOARD_TYPE_SIM: 342 /* The simulator gives you a simulated 1Gbps full duplex link */ 343 result.s.link_up = 1; 344 result.s.full_duplex = 1; 345 result.s.speed = 1000; 346 return result; 347 case CVMX_BOARD_TYPE_LANAI2_A: 348 case CVMX_BOARD_TYPE_LANAI2_U: 349 case CVMX_BOARD_TYPE_LANAI2_G: 350 break; 351 case CVMX_BOARD_TYPE_EBH3100: 352 case CVMX_BOARD_TYPE_CN3010_EVB_HS5: 353 case CVMX_BOARD_TYPE_CN3005_EVB_HS5: 354 case CVMX_BOARD_TYPE_CN3020_EVB_HS5: 355 /* Port 1 on these boards is always Gigabit */ 356 if (ipd_port == 1) 357 { 358 result.s.link_up = 1; 359 result.s.full_duplex = 1; 360 result.s.speed = 1000; 361 return result; 362 } 363 /* Fall through to the generic code below */ 364 break; 365 case CVMX_BOARD_TYPE_EBH5600: 366 case CVMX_BOARD_TYPE_EBH5601: 367 case CVMX_BOARD_TYPE_EBH5610: 368 /* Board has 1 management ports */ 369 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) 370 is_broadcom_phy = 1; 371 break; 372 case CVMX_BOARD_TYPE_EBH5200: 373 case CVMX_BOARD_TYPE_EBH5201: 374 case CVMX_BOARD_TYPE_EBT5200: 375 /* Board has 2 management ports */ 376 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))) 377 is_broadcom_phy = 1; 378 break; 379 case CVMX_BOARD_TYPE_EBB6300: /* Only for MII mode, with PHY addresses 0/1. Default is RGMII*/ 380 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)) 381 && cvmx_helper_board_get_mii_address(ipd_port) >= 0 && cvmx_helper_board_get_mii_address(ipd_port) <= 1) 382 is_broadcom_phy = 1; 383 break; 384 case CVMX_BOARD_TYPE_CUST_NB5: 385 /* Port 1 on these boards is always Gigabit */ 386 if (ipd_port == 1) 387 { 388 result.s.link_up = 1; 389 result.s.full_duplex = 1; 390 result.s.speed = 1000; 391 return result; 392 } 393 else /* The other port uses a broadcom PHY */ 394 is_broadcom_phy = 1; 395 break; 396 case CVMX_BOARD_TYPE_BBGW_REF: 397 /* Port 1 on these boards is always Gigabit */ 398 if (ipd_port == 2) 399 { 400 /* Port 2 is not hooked up */ 401 result.u64 = 0; 402 return result; 403 } 404 else 405 { 406 /* Ports 0 and 1 connect to the switch */ 407 result.s.link_up = 1; 408 result.s.full_duplex = 1; 409 result.s.speed = 1000; 410 return result; 411 } 412 break; 413 /* Private vendor-defined boards. */ 414#if defined(OCTEON_VENDOR_LANNER) 415 case CVMX_BOARD_TYPE_CUST_LANNER_MR730: 416 /* Ports are BCM5482S */ 417 is_broadcom_phy = 1; 418 break; 419 case CVMX_BOARD_TYPE_CUST_LANNER_MR320: 420 /* Port 0 connects to the switch */ 421 if (ipd_port == 0) 422 { 423 result.s.link_up = 1; 424 result.s.full_duplex = 1; 425 result.s.speed = 1000; 426 return result; 427 } 428 break; 429#endif 430 } 431#endif 432 433 phy_addr = cvmx_helper_board_get_mii_address(ipd_port); 434 if (phy_addr != -1) 435 { 436 if (is_broadcom_phy) 437 { 438 /* Below we are going to read SMI/MDIO register 0x19 which works 439 on Broadcom parts */ 440 int phy_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0x19); 441 switch ((phy_status>>8) & 0x7) 442 { 443 case 0: 444 result.u64 = 0; 445 break; 446 case 1: 447 result.s.link_up = 1; 448 result.s.full_duplex = 0; 449 result.s.speed = 10; 450 break; 451 case 2: 452 result.s.link_up = 1; 453 result.s.full_duplex = 1; 454 result.s.speed = 10; 455 break; 456 case 3: 457 result.s.link_up = 1; 458 result.s.full_duplex = 0; 459 result.s.speed = 100; 460 break; 461 case 4: 462 result.s.link_up = 1; 463 result.s.full_duplex = 1; 464 result.s.speed = 100; 465 break; 466 case 5: 467 result.s.link_up = 1; 468 result.s.full_duplex = 1; 469 result.s.speed = 100; 470 break; 471 case 6: 472 result.s.link_up = 1; 473 result.s.full_duplex = 0; 474 result.s.speed = 1000; 475 break; 476 case 7: 477 result.s.link_up = 1; 478 result.s.full_duplex = 1; 479 result.s.speed = 1000; 480 break; 481 } 482 } 483 else 484 { 485 /* This code assumes we are using a Marvell Gigabit PHY. All the 486 speed information can be read from register 17 in one go. Somebody 487 using a different PHY will need to handle it above in the board 488 specific area */ 489 int phy_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17); 490 491 /* If the resolve bit 11 isn't set, see if autoneg is turned off 492 (bit 12, reg 0). The resolve bit doesn't get set properly when 493 autoneg is off, so force it */ 494 if ((phy_status & (1<<11)) == 0) 495 { 496 int auto_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0); 497 if ((auto_status & (1<<12)) == 0) 498 phy_status |= 1<<11; 499 } 500 501 /* Only return a link if the PHY has finished auto negotiation 502 and set the resolved bit (bit 11) */ 503 if (phy_status & (1<<11)) 504 { 505#if defined(OCTEON_BOARD_CAPK_0100ND) 506 result.s.link_up = (phy_status>>10)&1; 507#else 508 result.s.link_up = 1; 509#endif 510 result.s.full_duplex = ((phy_status>>13)&1); 511 switch ((phy_status>>14)&3) 512 { 513 case 0: /* 10 Mbps */ 514 result.s.speed = 10; 515 break; 516 case 1: /* 100 Mbps */ 517 result.s.speed = 100; 518 break; 519 case 2: /* 1 Gbps */ 520 result.s.speed = 1000; 521 break; 522 case 3: /* Illegal */ 523 result.u64 = 0; 524 break; 525 } 526 } 527 } 528 } 529 else if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) 530 { 531 /* We don't have a PHY address, so attempt to use in-band status. It is 532 really important that boards not supporting in-band status never get 533 here. Reading broken in-band status tends to do bad things */ 534 cvmx_gmxx_rxx_rx_inbnd_t inband_status; 535 int interface = cvmx_helper_get_interface_num(ipd_port); 536 int index = cvmx_helper_get_interface_index_num(ipd_port); 537 inband_status.u64 = cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface)); 538 539 result.s.link_up = inband_status.s.status; 540 result.s.full_duplex = inband_status.s.duplex; 541 switch (inband_status.s.speed) 542 { 543 case 0: /* 10 Mbps */ 544 result.s.speed = 10; 545 break; 546 case 1: /* 100 Mbps */ 547 result.s.speed = 100; 548 break; 549 case 2: /* 1 Gbps */ 550 result.s.speed = 1000; 551 break; 552 case 3: /* Illegal */ 553 result.u64 = 0; 554 break; 555 } 556 } 557 else 558 { 559 /* We don't have a PHY address and we don't have in-band status. There 560 is no way to determine the link speed. Return down assuming this 561 port isn't wired */ 562 result.u64 = 0; 563 } 564 565 /* If link is down, return all fields as zero. */ 566 if (!result.s.link_up) 567 result.u64 = 0; 568 569 return result; 570} 571 572 573/** 574 * This function as a board specific method of changing the PHY 575 * speed, duplex, and autonegotiation. This programs the PHY and 576 * not Octeon. This can be used to force Octeon's links to 577 * specific settings. 578 * 579 * @param phy_addr The address of the PHY to program 580 * @param link_flags 581 * Flags to control autonegotiation. Bit 0 is autonegotiation 582 * enable/disable to maintain backward compatibility. 583 * @param link_info Link speed to program. If the speed is zero and autonegotiation 584 * is enabled, all possible negotiation speeds are advertised. 585 * 586 * @return Zero on success, negative on failure 587 */ 588int cvmx_helper_board_link_set_phy(int phy_addr, cvmx_helper_board_set_phy_link_flags_types_t link_flags, 589 cvmx_helper_link_info_t link_info) 590{ 591 592 /* Set the flow control settings based on link_flags */ 593 if ((link_flags & set_phy_link_flags_flow_control_mask) != set_phy_link_flags_flow_control_dont_touch) 594 { 595 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; 596 reg_autoneg_adver.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER); 597 reg_autoneg_adver.s.asymmetric_pause = (link_flags & set_phy_link_flags_flow_control_mask) == set_phy_link_flags_flow_control_enable; 598 reg_autoneg_adver.s.pause = (link_flags & set_phy_link_flags_flow_control_mask) == set_phy_link_flags_flow_control_enable; 599 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER, reg_autoneg_adver.u16); 600 } 601 602 /* If speed isn't set and autoneg is on advertise all supported modes */ 603 if ((link_flags & set_phy_link_flags_autoneg) && (link_info.s.speed == 0)) 604 { 605 cvmx_mdio_phy_reg_control_t reg_control; 606 cvmx_mdio_phy_reg_status_t reg_status; 607 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; 608 cvmx_mdio_phy_reg_extended_status_t reg_extended_status; 609 cvmx_mdio_phy_reg_control_1000_t reg_control_1000; 610 611 reg_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_STATUS); 612 reg_autoneg_adver.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER); 613 reg_autoneg_adver.s.advert_100base_t4 = reg_status.s.capable_100base_t4; 614 reg_autoneg_adver.s.advert_10base_tx_full = reg_status.s.capable_10_full; 615 reg_autoneg_adver.s.advert_10base_tx_half = reg_status.s.capable_10_half; 616 reg_autoneg_adver.s.advert_100base_tx_full = reg_status.s.capable_100base_x_full; 617 reg_autoneg_adver.s.advert_100base_tx_half = reg_status.s.capable_100base_x_half; 618 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER, reg_autoneg_adver.u16); 619 if (reg_status.s.capable_extended_status) 620 { 621 reg_extended_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_EXTENDED_STATUS); 622 reg_control_1000.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000); 623 reg_control_1000.s.advert_1000base_t_full = reg_extended_status.s.capable_1000base_t_full; 624 reg_control_1000.s.advert_1000base_t_half = reg_extended_status.s.capable_1000base_t_half; 625 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000, reg_control_1000.u16); 626 } 627 reg_control.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL); 628 reg_control.s.autoneg_enable = 1; 629 reg_control.s.restart_autoneg = 1; 630 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); 631 } 632 else if ((link_flags & set_phy_link_flags_autoneg)) 633 { 634 cvmx_mdio_phy_reg_control_t reg_control; 635 cvmx_mdio_phy_reg_status_t reg_status; 636 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; 637 cvmx_mdio_phy_reg_extended_status_t reg_extended_status; 638 cvmx_mdio_phy_reg_control_1000_t reg_control_1000; 639 640 reg_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_STATUS); 641 reg_autoneg_adver.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER); 642 reg_autoneg_adver.s.advert_100base_t4 = 0; 643 reg_autoneg_adver.s.advert_10base_tx_full = 0; 644 reg_autoneg_adver.s.advert_10base_tx_half = 0; 645 reg_autoneg_adver.s.advert_100base_tx_full = 0; 646 reg_autoneg_adver.s.advert_100base_tx_half = 0; 647 if (reg_status.s.capable_extended_status) 648 { 649 reg_extended_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_EXTENDED_STATUS); 650 reg_control_1000.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000); 651 reg_control_1000.s.advert_1000base_t_full = 0; 652 reg_control_1000.s.advert_1000base_t_half = 0; 653 } 654 switch (link_info.s.speed) 655 { 656 case 10: 657 reg_autoneg_adver.s.advert_10base_tx_full = link_info.s.full_duplex; 658 reg_autoneg_adver.s.advert_10base_tx_half = !link_info.s.full_duplex; 659 break; 660 case 100: 661 reg_autoneg_adver.s.advert_100base_tx_full = link_info.s.full_duplex; 662 reg_autoneg_adver.s.advert_100base_tx_half = !link_info.s.full_duplex; 663 break; 664 case 1000: 665 reg_control_1000.s.advert_1000base_t_full = link_info.s.full_duplex; 666 reg_control_1000.s.advert_1000base_t_half = !link_info.s.full_duplex; 667 break; 668 } 669 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER, reg_autoneg_adver.u16); 670 if (reg_status.s.capable_extended_status) 671 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000, reg_control_1000.u16); 672 reg_control.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL); 673 reg_control.s.autoneg_enable = 1; 674 reg_control.s.restart_autoneg = 1; 675 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); 676 } 677 else 678 { 679 cvmx_mdio_phy_reg_control_t reg_control; 680 reg_control.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL); 681 reg_control.s.autoneg_enable = 0; 682 reg_control.s.restart_autoneg = 1; 683 reg_control.s.duplex = link_info.s.full_duplex; 684 if (link_info.s.speed == 1000) 685 { 686 reg_control.s.speed_msb = 1; 687 reg_control.s.speed_lsb = 0; 688 } 689 else if (link_info.s.speed == 100) 690 { 691 reg_control.s.speed_msb = 0; 692 reg_control.s.speed_lsb = 1; 693 } 694 else if (link_info.s.speed == 10) 695 { 696 reg_control.s.speed_msb = 0; 697 reg_control.s.speed_lsb = 0; 698 } 699 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); 700 } 701 return 0; 702} 703 704 705/** 706 * @INTERNAL 707 * This function is called by cvmx_helper_interface_probe() after it 708 * determines the number of ports Octeon can support on a specific 709 * interface. This function is the per board location to override 710 * this value. It is called with the number of ports Octeon might 711 * support and should return the number of actual ports on the 712 * board. 713 * 714 * This function must be modified for every new Octeon board. 715 * Internally it uses switch statements based on the cvmx_sysinfo 716 * data to determine board types and revisions. It relies on the 717 * fact that every Octeon board receives a unique board type 718 * enumeration from the bootloader. 719 * 720 * @param interface Interface to probe 721 * @param supported_ports 722 * Number of ports Octeon supports. 723 * 724 * @return Number of ports the actual board supports. Many times this will 725 * simple be "support_ports". 726 */ 727int __cvmx_helper_board_interface_probe(int interface, int supported_ports) 728{ 729 switch (cvmx_sysinfo_get()->board_type) 730 { 731 case CVMX_BOARD_TYPE_CN3005_EVB_HS5: 732 case CVMX_BOARD_TYPE_LANAI2_A: 733 case CVMX_BOARD_TYPE_LANAI2_U: 734 case CVMX_BOARD_TYPE_LANAI2_G: 735 if (interface == 0) 736 return 2; 737 break; 738 case CVMX_BOARD_TYPE_BBGW_REF: 739 if (interface == 0) 740 return 2; 741 break; 742 case CVMX_BOARD_TYPE_NIC_XLE_4G: 743 if (interface == 0) 744 return 0; 745 break; 746 /* The 2nd interface on the EBH5600 is connected to the Marvel switch, 747 which we don't support. Disable ports connected to it */ 748 case CVMX_BOARD_TYPE_EBH5600: 749 if (interface == 1) 750 return 0; 751 break; 752 case CVMX_BOARD_TYPE_EBB5600: 753#ifdef CVMX_ENABLE_PKO_FUNCTIONS 754 if (cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_PICMG) 755 return 0; 756#endif 757 break; 758 case CVMX_BOARD_TYPE_EBT5810: 759 return 1; /* Two ports on each SPI: 1 hooked to MAC, 1 loopback 760 ** Loopback disabled by default. */ 761#if defined(OCTEON_VENDOR_LANNER) 762 case CVMX_BOARD_TYPE_CUST_LANNER_MR955: 763 if (interface == 1) 764 return 12; 765 break; 766#endif 767 } 768#ifdef CVMX_BUILD_FOR_UBOOT 769 if (CVMX_HELPER_INTERFACE_MODE_SPI == cvmx_helper_interface_get_mode(interface) && getenv("disable_spi")) 770 return 0; 771#endif 772 return supported_ports; 773} 774 775 776/** 777 * @INTERNAL 778 * Enable packet input/output from the hardware. This function is 779 * called after by cvmx_helper_packet_hardware_enable() to 780 * perform board specific initialization. For most boards 781 * nothing is needed. 782 * 783 * @param interface Interface to enable 784 * 785 * @return Zero on success, negative on failure 786 */ 787int __cvmx_helper_board_hardware_enable(int interface) 788{ 789 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5) 790 { 791 if (interface == 0) 792 { 793 /* Different config for switch port */ 794 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0); 795 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); 796 /* Boards with gigabit WAN ports need a different setting that is 797 compatible with 100 Mbit settings */ 798 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 0xc); 799 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0xc); 800 } 801 } 802 else if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_LANAI2_U) 803 { 804 if (interface == 0) 805 { 806 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 16); 807 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 16); 808 } 809 } 810 else if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3010_EVB_HS5) 811 { 812 /* Broadcom PHYs require different ASX clocks. Unfortunately 813 many customer don't define a new board Id and simply 814 mangle the CN3010_EVB_HS5 */ 815 if (interface == 0) 816 { 817 /* Some customers boards use a hacked up bootloader that identifies them as 818 ** CN3010_EVB_HS5 evaluation boards. This leads to all kinds of configuration 819 ** problems. Detect one case, and print warning, while trying to do the right thing. 820 */ 821 int phy_addr = cvmx_helper_board_get_mii_address(0); 822 if (phy_addr != -1) 823 { 824 int phy_identifier = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0x2); 825 /* Is it a Broadcom PHY? */ 826 if (phy_identifier == 0x0143) 827 { 828 cvmx_dprintf("\n"); 829 cvmx_dprintf("ERROR:\n"); 830 cvmx_dprintf("ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found.\n"); 831 cvmx_dprintf("ERROR: The board type is mis-configured, and software malfunctions are likely.\n"); 832 cvmx_dprintf("ERROR: All boards require a unique board type to identify them.\n"); 833 cvmx_dprintf("ERROR:\n"); 834 cvmx_dprintf("\n"); 835 cvmx_wait(1000000000); 836 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 5); 837 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 5); 838 } 839 } 840 } 841 } 842 return 0; 843} 844 845 846/** 847 * @INTERNAL 848 * Gets the clock type used for the USB block based on board type. 849 * Used by the USB code for auto configuration of clock type. 850 * 851 * @return USB clock type enumeration 852 */ 853cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void) 854{ 855 switch (cvmx_sysinfo_get()->board_type) 856 { 857 case CVMX_BOARD_TYPE_BBGW_REF: 858 case CVMX_BOARD_TYPE_LANAI2_A: 859 case CVMX_BOARD_TYPE_LANAI2_U: 860 case CVMX_BOARD_TYPE_LANAI2_G: 861#if defined(OCTEON_VENDOR_LANNER) 862 case CVMX_BOARD_TYPE_CUST_LANNER_MR320: 863#endif 864 return USB_CLOCK_TYPE_CRYSTAL_12; 865 } 866 return USB_CLOCK_TYPE_REF_48; 867} 868 869 870/** 871 * @INTERNAL 872 * Adjusts the number of available USB ports on Octeon based on board 873 * specifics. 874 * 875 * @param supported_ports expected number of ports based on chip type; 876 * 877 * 878 * @return number of available usb ports, based on board specifics. 879 * Return value is supported_ports if function does not 880 * override. 881 */ 882int __cvmx_helper_board_usb_get_num_ports(int supported_ports) 883{ 884 switch (cvmx_sysinfo_get()->board_type) 885 { 886 case CVMX_BOARD_TYPE_NIC_XLE_4G: 887 return 0; 888 } 889 890 return supported_ports; 891} 892 893 894