cvmx-gpio.h revision 215990 
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39
40
41
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43
44
45
46/**
47 * @file
48 *
49 * General Purpose IO interface.
50 *
51 * <hr>$Revision: 49448 $<hr>
52 */
53
54#ifndef __CVMX_GPIO_H__
55#define __CVMX_GPIO_H__
56
57#ifdef	__cplusplus
58extern "C" {
59#endif
60
61/* CSR typedefs have been moved to cvmx-gpio-defs.h */
62
63/**
64 * Clear the interrupt rising edge detector for the supplied
65 * pins in the mask. Chips which have more than 16 GPIO pins
66 * can't use them for interrupts.
67 *
68 * @param clear_mask Mask of pins to clear
69 */
70static inline void cvmx_gpio_interrupt_clear(uint16_t clear_mask)
71{
72    cvmx_gpio_int_clr_t gpio_int_clr;
73    gpio_int_clr.u64 = 0;
74    gpio_int_clr.s.type = clear_mask;
75    cvmx_write_csr(CVMX_GPIO_INT_CLR, gpio_int_clr.u64);
76}
77
78
79/**
80 * GPIO Read Data
81 *
82 * @return Status of the GPIO pins
83 */
84static inline uint32_t cvmx_gpio_read(void)
85{
86    cvmx_gpio_rx_dat_t gpio_rx_dat;
87    gpio_rx_dat.u64 = cvmx_read_csr(CVMX_GPIO_RX_DAT);
88    return gpio_rx_dat.s.dat;
89}
90
91
92/**
93 * GPIO Clear pin
94 *
95 * @param clear_mask Bit mask to indicate which bits to drive to '0'.
96 */
97static inline void cvmx_gpio_clear(uint32_t clear_mask)
98{
99    cvmx_gpio_tx_clr_t gpio_tx_clr;
100    gpio_tx_clr.u64 = 0;
101    gpio_tx_clr.s.clr = clear_mask;
102    cvmx_write_csr(CVMX_GPIO_TX_CLR, gpio_tx_clr.u64);
103}
104
105
106/**
107 * GPIO Set pin
108 *
109 * @param set_mask Bit mask to indicate which bits to drive to '1'.
110 */
111static inline void cvmx_gpio_set(uint32_t set_mask)
112{
113    cvmx_gpio_tx_set_t gpio_tx_set;
114    gpio_tx_set.u64 = 0;
115    gpio_tx_set.s.set = set_mask;
116    cvmx_write_csr(CVMX_GPIO_TX_SET, gpio_tx_set.u64);
117}
118
119#ifdef	__cplusplus
120}
121#endif
122
123#endif
124
125