cvmx-fpa-defs.h revision 256281
1321964Ssjg/***********************license start*************** 2236769Sobrien * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3236769Sobrien * reserved. 4236769Sobrien * 5236769Sobrien * 6236769Sobrien * Redistribution and use in source and binary forms, with or without 7236769Sobrien * modification, are permitted provided that the following conditions are 8236769Sobrien * met: 9236769Sobrien * 10236769Sobrien * * Redistributions of source code must retain the above copyright 11236769Sobrien * notice, this list of conditions and the following disclaimer. 12236769Sobrien * 13236769Sobrien * * Redistributions in binary form must reproduce the above 14236769Sobrien * copyright notice, this list of conditions and the following 15236769Sobrien * disclaimer in the documentation and/or other materials provided 16236769Sobrien * with the distribution. 17236769Sobrien 18236769Sobrien * * Neither the name of Cavium Inc. nor the names of 19236769Sobrien * its contributors may be used to endorse or promote products 20236769Sobrien * derived from this software without specific prior written 21236769Sobrien * permission. 22236769Sobrien 23236769Sobrien * This Software, including technical data, may be subject to U.S. export control 24236769Sobrien * laws, including the U.S. Export Administration Act and its associated 25236769Sobrien * regulations, and may be subject to export or import regulations in other 26236769Sobrien * countries. 27236769Sobrien 28236769Sobrien * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29236769Sobrien * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30236769Sobrien * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31236769Sobrien * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32236769Sobrien * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33236769Sobrien * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34236769Sobrien * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35236769Sobrien * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36236769Sobrien * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37236769Sobrien * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38236769Sobrien ***********************license end**************************************/ 39236769Sobrien 40236769Sobrien 41236769Sobrien/** 42236769Sobrien * cvmx-fpa-defs.h 43236769Sobrien * 44236769Sobrien * Configuration and status register (CSR) type definitions for 45236769Sobrien * Octeon fpa. 46236769Sobrien * 47236769Sobrien * This file is auto generated. Do not edit. 48236769Sobrien * 49236769Sobrien * <hr>$Revision$<hr> 50236769Sobrien * 51236769Sobrien */ 52236769Sobrien#ifndef __CVMX_FPA_DEFS_H__ 53236769Sobrien#define __CVMX_FPA_DEFS_H__ 54236769Sobrien 55236769Sobrien#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56236769Sobrien#define CVMX_FPA_ADDR_RANGE_ERROR CVMX_FPA_ADDR_RANGE_ERROR_FUNC() 57236769Sobrienstatic inline uint64_t CVMX_FPA_ADDR_RANGE_ERROR_FUNC(void) 58236769Sobrien{ 59236769Sobrien if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 60236769Sobrien cvmx_warn("CVMX_FPA_ADDR_RANGE_ERROR not supported on this chip\n"); 61236769Sobrien return CVMX_ADD_IO_SEG(0x0001180028000458ull); 62236769Sobrien} 63236769Sobrien#else 64236769Sobrien#define CVMX_FPA_ADDR_RANGE_ERROR (CVMX_ADD_IO_SEG(0x0001180028000458ull)) 65236769Sobrien#endif 66236769Sobrien#define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull)) 67236769Sobrien#define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull)) 68236769Sobrien#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69236769Sobrien#define CVMX_FPA_FPF0_MARKS CVMX_FPA_FPF0_MARKS_FUNC() 70236769Sobrienstatic inline uint64_t CVMX_FPA_FPF0_MARKS_FUNC(void) 71236769Sobrien{ 72321964Ssjg if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 73236769Sobrien cvmx_warn("CVMX_FPA_FPF0_MARKS not supported on this chip\n"); 74236769Sobrien return CVMX_ADD_IO_SEG(0x0001180028000000ull); 75236769Sobrien} 76236769Sobrien#else 77236769Sobrien#define CVMX_FPA_FPF0_MARKS (CVMX_ADD_IO_SEG(0x0001180028000000ull)) 78236769Sobrien#endif 79321964Ssjg#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80236769Sobrien#define CVMX_FPA_FPF0_SIZE CVMX_FPA_FPF0_SIZE_FUNC() 81236769Sobrienstatic inline uint64_t CVMX_FPA_FPF0_SIZE_FUNC(void) 82236769Sobrien{ 83236769Sobrien if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 84236769Sobrien cvmx_warn("CVMX_FPA_FPF0_SIZE not supported on this chip\n"); 85236769Sobrien return CVMX_ADD_IO_SEG(0x0001180028000058ull); 86236769Sobrien} 87236769Sobrien#else 88236769Sobrien#define CVMX_FPA_FPF0_SIZE (CVMX_ADD_IO_SEG(0x0001180028000058ull)) 89236769Sobrien#endif 90236769Sobrien#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1) 91236769Sobrien#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2) 92236769Sobrien#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3) 93236769Sobrien#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4) 94236769Sobrien#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5) 95236769Sobrien#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6) 96236769Sobrien#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7) 97236769Sobrien#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 98236769Sobrien#define CVMX_FPA_FPF8_MARKS CVMX_FPA_FPF8_MARKS_FUNC() 99236769Sobrienstatic inline uint64_t CVMX_FPA_FPF8_MARKS_FUNC(void) 100236769Sobrien{ 101236769Sobrien if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 102236769Sobrien cvmx_warn("CVMX_FPA_FPF8_MARKS not supported on this chip\n"); 103236769Sobrien return CVMX_ADD_IO_SEG(0x0001180028000240ull); 104236769Sobrien} 105236769Sobrien#else 106236769Sobrien#define CVMX_FPA_FPF8_MARKS (CVMX_ADD_IO_SEG(0x0001180028000240ull)) 107236769Sobrien#endif 108236769Sobrien#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 109236769Sobrien#define CVMX_FPA_FPF8_SIZE CVMX_FPA_FPF8_SIZE_FUNC() 110236769Sobrienstatic inline uint64_t CVMX_FPA_FPF8_SIZE_FUNC(void) 111236769Sobrien{ 112236769Sobrien if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 113236769Sobrien cvmx_warn("CVMX_FPA_FPF8_SIZE not supported on this chip\n"); 114236769Sobrien return CVMX_ADD_IO_SEG(0x0001180028000248ull); 115236769Sobrien} 116236769Sobrien#else 117236769Sobrien#define CVMX_FPA_FPF8_SIZE (CVMX_ADD_IO_SEG(0x0001180028000248ull)) 118236769Sobrien#endif 119236769Sobrien#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 120236769Sobrienstatic inline uint64_t CVMX_FPA_FPFX_MARKS(unsigned long offset) 121236769Sobrien{ 122236769Sobrien if (!( 123236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) || 124236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) || 125236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7)))) || 126236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 1) && (offset <= 7)))) || 127236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 1) && (offset <= 7)))) || 128236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 1) && (offset <= 7)))) || 129236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 1) && (offset <= 7)))) || 130236769Sobrien (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 1) && (offset <= 7)))))) 131236769Sobrien cvmx_warn("CVMX_FPA_FPFX_MARKS(%lu) is invalid on this chip\n", offset); 132236769Sobrien return CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1; 133236769Sobrien} 134236769Sobrien#else 135236769Sobrien#define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1) 136236769Sobrien#endif 137236769Sobrien#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 138236769Sobrienstatic inline uint64_t CVMX_FPA_FPFX_SIZE(unsigned long offset) 139236769Sobrien{ 140292068Ssjg if (!( 141236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) || 142253883Ssjg (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) || 143236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7)))) || 144236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 1) && (offset <= 7)))) || 145236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 1) && (offset <= 7)))) || 146236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 1) && (offset <= 7)))) || 147236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 1) && (offset <= 7)))) || 148236769Sobrien (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 1) && (offset <= 7)))))) 149236769Sobrien cvmx_warn("CVMX_FPA_FPFX_SIZE(%lu) is invalid on this chip\n", offset); 150236769Sobrien return CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1; 151236769Sobrien} 152236769Sobrien#else 153236769Sobrien#define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1) 154236769Sobrien#endif 155236769Sobrien#define CVMX_FPA_INT_ENB (CVMX_ADD_IO_SEG(0x0001180028000048ull)) 156236769Sobrien#define CVMX_FPA_INT_SUM (CVMX_ADD_IO_SEG(0x0001180028000040ull)) 157321964Ssjg#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 158321964Ssjg#define CVMX_FPA_PACKET_THRESHOLD CVMX_FPA_PACKET_THRESHOLD_FUNC() 159321964Ssjgstatic inline uint64_t CVMX_FPA_PACKET_THRESHOLD_FUNC(void) 160236769Sobrien{ 161236769Sobrien if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 162236769Sobrien cvmx_warn("CVMX_FPA_PACKET_THRESHOLD not supported on this chip\n"); 163236769Sobrien return CVMX_ADD_IO_SEG(0x0001180028000460ull); 164321964Ssjg} 165321964Ssjg#else 166321964Ssjg#define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull)) 167321964Ssjg#endif 168321964Ssjg#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 169321964Ssjgstatic inline uint64_t CVMX_FPA_POOLX_END_ADDR(unsigned long offset) 170321964Ssjg{ 171321964Ssjg if (!( 172321964Ssjg (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 173321964Ssjg (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 174236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) || 175236769Sobrien (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 176236769Sobrien cvmx_warn("CVMX_FPA_POOLX_END_ADDR(%lu) is invalid on this chip\n", offset); 177236769Sobrien return CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8; 178236769Sobrien} 179236769Sobrien#else 180236769Sobrien#define CVMX_FPA_POOLX_END_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000358ull) + ((offset) & 15) * 8) 181236769Sobrien#endif 182236769Sobrien#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 183236769Sobrienstatic inline uint64_t CVMX_FPA_POOLX_START_ADDR(unsigned long offset) 184236769Sobrien{ 185236769Sobrien if (!( 186236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 187236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 188236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) || 189255253Ssjg (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 190236769Sobrien cvmx_warn("CVMX_FPA_POOLX_START_ADDR(%lu) is invalid on this chip\n", offset); 191236769Sobrien return CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8; 192236769Sobrien} 193236769Sobrien#else 194236769Sobrien#define CVMX_FPA_POOLX_START_ADDR(offset) (CVMX_ADD_IO_SEG(0x0001180028000258ull) + ((offset) & 15) * 8) 195236769Sobrien#endif 196236769Sobrien#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 197236769Sobrienstatic inline uint64_t CVMX_FPA_POOLX_THRESHOLD(unsigned long offset) 198236769Sobrien{ 199236769Sobrien if (!( 200236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 201236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 202236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 203236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) || 204236769Sobrien (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 205236769Sobrien cvmx_warn("CVMX_FPA_POOLX_THRESHOLD(%lu) is invalid on this chip\n", offset); 206236769Sobrien return CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8; 207236769Sobrien} 208236769Sobrien#else 209236769Sobrien#define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 15) * 8) 210236769Sobrien#endif 211236769Sobrien#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0) 212236769Sobrien#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1) 213236769Sobrien#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2) 214236769Sobrien#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3) 215236769Sobrien#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4) 216236769Sobrien#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5) 217236769Sobrien#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6) 218236769Sobrien#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7) 219236769Sobrien#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 220236769Sobrien#define CVMX_FPA_QUE8_PAGE_INDEX CVMX_FPA_QUE8_PAGE_INDEX_FUNC() 221236769Sobrienstatic inline uint64_t CVMX_FPA_QUE8_PAGE_INDEX_FUNC(void) 222236769Sobrien{ 223236769Sobrien if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 224236769Sobrien cvmx_warn("CVMX_FPA_QUE8_PAGE_INDEX not supported on this chip\n"); 225236769Sobrien return CVMX_ADD_IO_SEG(0x0001180028000250ull); 226236769Sobrien} 227236769Sobrien#else 228236769Sobrien#define CVMX_FPA_QUE8_PAGE_INDEX (CVMX_ADD_IO_SEG(0x0001180028000250ull)) 229321964Ssjg#endif 230321964Ssjg#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 231321964Ssjgstatic inline uint64_t CVMX_FPA_QUEX_AVAILABLE(unsigned long offset) 232321964Ssjg{ 233321964Ssjg if (!( 234236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 235236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 236236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 237236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 238236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 239236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 240236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 241236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 242236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 243236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 244236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 8))) || 245236769Sobrien (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 246236769Sobrien cvmx_warn("CVMX_FPA_QUEX_AVAILABLE(%lu) is invalid on this chip\n", offset); 247236769Sobrien return CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8; 248236769Sobrien} 249236769Sobrien#else 250236769Sobrien#define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 15) * 8) 251236769Sobrien#endif 252236769Sobrien#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 253236769Sobrienstatic inline uint64_t CVMX_FPA_QUEX_PAGE_INDEX(unsigned long offset) 254236769Sobrien{ 255236769Sobrien if (!( 256236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 257236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 258236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 259236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 260236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 261236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 262236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 263236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 264236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 265236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 266236769Sobrien (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 267236769Sobrien (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 268236769Sobrien cvmx_warn("CVMX_FPA_QUEX_PAGE_INDEX(%lu) is invalid on this chip\n", offset); 269236769Sobrien return CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8; 270236769Sobrien} 271236769Sobrien#else 272236769Sobrien#define CVMX_FPA_QUEX_PAGE_INDEX(offset) (CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8) 273236769Sobrien#endif 274236769Sobrien#define CVMX_FPA_QUE_ACT (CVMX_ADD_IO_SEG(0x0001180028000138ull)) 275236769Sobrien#define CVMX_FPA_QUE_EXP (CVMX_ADD_IO_SEG(0x0001180028000130ull)) 276236769Sobrien#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 277236769Sobrien#define CVMX_FPA_WART_CTL CVMX_FPA_WART_CTL_FUNC() 278236769Sobrienstatic inline uint64_t CVMX_FPA_WART_CTL_FUNC(void) 279236769Sobrien{ 280236769Sobrien if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 281236769Sobrien cvmx_warn("CVMX_FPA_WART_CTL not supported on this chip\n"); 282236769Sobrien return CVMX_ADD_IO_SEG(0x00011800280000D8ull); 283236769Sobrien} 284236769Sobrien#else 285236769Sobrien#define CVMX_FPA_WART_CTL (CVMX_ADD_IO_SEG(0x00011800280000D8ull)) 286236769Sobrien#endif 287236769Sobrien#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 288236769Sobrien#define CVMX_FPA_WART_STATUS CVMX_FPA_WART_STATUS_FUNC() 289236769Sobrienstatic inline uint64_t CVMX_FPA_WART_STATUS_FUNC(void) 290236769Sobrien{ 291236769Sobrien if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 292236769Sobrien cvmx_warn("CVMX_FPA_WART_STATUS not supported on this chip\n"); 293236769Sobrien return CVMX_ADD_IO_SEG(0x00011800280000E0ull); 294236769Sobrien} 295236769Sobrien#else 296236769Sobrien#define CVMX_FPA_WART_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E0ull)) 297236769Sobrien#endif 298236769Sobrien#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 299236769Sobrien#define CVMX_FPA_WQE_THRESHOLD CVMX_FPA_WQE_THRESHOLD_FUNC() 300236769Sobrienstatic inline uint64_t CVMX_FPA_WQE_THRESHOLD_FUNC(void) 301236769Sobrien{ 302236769Sobrien if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 303236769Sobrien cvmx_warn("CVMX_FPA_WQE_THRESHOLD not supported on this chip\n"); 304236769Sobrien return CVMX_ADD_IO_SEG(0x0001180028000468ull); 305236769Sobrien} 306236769Sobrien#else 307236769Sobrien#define CVMX_FPA_WQE_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000468ull)) 308236769Sobrien#endif 309236769Sobrien 310236769Sobrien/** 311236769Sobrien * cvmx_fpa_addr_range_error 312236769Sobrien * 313236769Sobrien * Space here reserved 314236769Sobrien * 315236769Sobrien * FPA_ADDR_RANGE_ERROR = FPA's Pool Address Range Error Information 316236769Sobrien * 317236769Sobrien * When an address is sent to a pool that does not fall in the start and end address spcified by 318236769Sobrien * FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR the information related to the failure is captured here. 319236769Sobrien * In addition FPA_INT_SUM[PADDR_E] will be set and this register will not be updated again till 320236769Sobrien * FPA_INT_SUM[PADDR_E] is cleared. 321236769Sobrien */ 322236769Sobrienunion cvmx_fpa_addr_range_error { 323236769Sobrien uint64_t u64; 324236769Sobrien struct cvmx_fpa_addr_range_error_s { 325236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 326236769Sobrien uint64_t reserved_38_63 : 26; 327236769Sobrien uint64_t pool : 5; /**< Pool address sent to. */ 328236769Sobrien uint64_t addr : 33; /**< Failing address. */ 329236769Sobrien#else 330236769Sobrien uint64_t addr : 33; 331236769Sobrien uint64_t pool : 5; 332236769Sobrien uint64_t reserved_38_63 : 26; 333236769Sobrien#endif 334236769Sobrien } s; 335236769Sobrien struct cvmx_fpa_addr_range_error_s cn61xx; 336236769Sobrien struct cvmx_fpa_addr_range_error_s cn66xx; 337236769Sobrien struct cvmx_fpa_addr_range_error_s cn68xx; 338236769Sobrien struct cvmx_fpa_addr_range_error_s cn68xxp1; 339236769Sobrien struct cvmx_fpa_addr_range_error_s cnf71xx; 340236769Sobrien}; 341236769Sobrientypedef union cvmx_fpa_addr_range_error cvmx_fpa_addr_range_error_t; 342236769Sobrien 343236769Sobrien/** 344236769Sobrien * cvmx_fpa_bist_status 345236769Sobrien * 346236769Sobrien * FPA_BIST_STATUS = BIST Status of FPA Memories 347236769Sobrien * 348236769Sobrien * The result of the BIST run on the FPA memories. 349236769Sobrien */ 350236769Sobrienunion cvmx_fpa_bist_status { 351236769Sobrien uint64_t u64; 352236769Sobrien struct cvmx_fpa_bist_status_s { 353236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 354236769Sobrien uint64_t reserved_5_63 : 59; 355236769Sobrien uint64_t frd : 1; /**< fpa_frd memory bist status. */ 356236769Sobrien uint64_t fpf0 : 1; /**< fpa_fpf0 memory bist status. */ 357236769Sobrien uint64_t fpf1 : 1; /**< fpa_fpf1 memory bist status. */ 358236769Sobrien uint64_t ffr : 1; /**< fpa_ffr memory bist status. */ 359236769Sobrien uint64_t fdr : 1; /**< fpa_fdr memory bist status. */ 360236769Sobrien#else 361236769Sobrien uint64_t fdr : 1; 362236769Sobrien uint64_t ffr : 1; 363236769Sobrien uint64_t fpf1 : 1; 364236769Sobrien uint64_t fpf0 : 1; 365236769Sobrien uint64_t frd : 1; 366236769Sobrien uint64_t reserved_5_63 : 59; 367236769Sobrien#endif 368236769Sobrien } s; 369236769Sobrien struct cvmx_fpa_bist_status_s cn30xx; 370236769Sobrien struct cvmx_fpa_bist_status_s cn31xx; 371236769Sobrien struct cvmx_fpa_bist_status_s cn38xx; 372236769Sobrien struct cvmx_fpa_bist_status_s cn38xxp2; 373236769Sobrien struct cvmx_fpa_bist_status_s cn50xx; 374236769Sobrien struct cvmx_fpa_bist_status_s cn52xx; 375236769Sobrien struct cvmx_fpa_bist_status_s cn52xxp1; 376236769Sobrien struct cvmx_fpa_bist_status_s cn56xx; 377236769Sobrien struct cvmx_fpa_bist_status_s cn56xxp1; 378236769Sobrien struct cvmx_fpa_bist_status_s cn58xx; 379236769Sobrien struct cvmx_fpa_bist_status_s cn58xxp1; 380236769Sobrien struct cvmx_fpa_bist_status_s cn61xx; 381236769Sobrien struct cvmx_fpa_bist_status_s cn63xx; 382236769Sobrien struct cvmx_fpa_bist_status_s cn63xxp1; 383236769Sobrien struct cvmx_fpa_bist_status_s cn66xx; 384236769Sobrien struct cvmx_fpa_bist_status_s cn68xx; 385236769Sobrien struct cvmx_fpa_bist_status_s cn68xxp1; 386236769Sobrien struct cvmx_fpa_bist_status_s cnf71xx; 387236769Sobrien}; 388236769Sobrientypedef union cvmx_fpa_bist_status cvmx_fpa_bist_status_t; 389236769Sobrien 390236769Sobrien/** 391236769Sobrien * cvmx_fpa_ctl_status 392236769Sobrien * 393236769Sobrien * FPA_CTL_STATUS = FPA's Control/Status Register 394236769Sobrien * 395236769Sobrien * The FPA's interrupt enable register. 396236769Sobrien */ 397236769Sobrienunion cvmx_fpa_ctl_status { 398236769Sobrien uint64_t u64; 399236769Sobrien struct cvmx_fpa_ctl_status_s { 400236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 401236769Sobrien uint64_t reserved_21_63 : 43; 402236769Sobrien uint64_t free_en : 1; /**< Enables the setting of the INT_SUM_[FREE*] bits. */ 403236769Sobrien uint64_t ret_off : 1; /**< When set NCB devices returning pointer will be 404236769Sobrien stalled. */ 405236769Sobrien uint64_t req_off : 1; /**< When set NCB devices requesting pointers will be 406236769Sobrien stalled. */ 407236769Sobrien uint64_t reset : 1; /**< When set causes a reset of the FPA with the */ 408236769Sobrien uint64_t use_ldt : 1; /**< When clear '0' the FPA will use LDT to load 409236769Sobrien pointers from the L2C. This is a PASS-2 field. */ 410236769Sobrien uint64_t use_stt : 1; /**< When clear '0' the FPA will use STT to store 411236769Sobrien pointers to the L2C. This is a PASS-2 field. */ 412236769Sobrien uint64_t enb : 1; /**< Must be set to 1 AFTER writing all config registers 413236769Sobrien and 10 cycles have past. If any of the config 414236769Sobrien register are written after writing this bit the 415236769Sobrien FPA may begin to operate incorrectly. */ 416236769Sobrien uint64_t mem1_err : 7; /**< Causes a flip of the ECC bit associated 38:32 417236769Sobrien respective to bit 6:0 of this field, for FPF 418236769Sobrien FIFO 1. */ 419236769Sobrien uint64_t mem0_err : 7; /**< Causes a flip of the ECC bit associated 38:32 420236769Sobrien respective to bit 6:0 of this field, for FPF 421236769Sobrien FIFO 0. */ 422236769Sobrien#else 423236769Sobrien uint64_t mem0_err : 7; 424236769Sobrien uint64_t mem1_err : 7; 425236769Sobrien uint64_t enb : 1; 426255253Ssjg uint64_t use_stt : 1; 427255253Ssjg uint64_t use_ldt : 1; 428255253Ssjg uint64_t reset : 1; 429255253Ssjg uint64_t req_off : 1; 430236769Sobrien uint64_t ret_off : 1; 431236769Sobrien uint64_t free_en : 1; 432236769Sobrien uint64_t reserved_21_63 : 43; 433236769Sobrien#endif 434236769Sobrien } s; 435236769Sobrien struct cvmx_fpa_ctl_status_cn30xx { 436236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 437236769Sobrien uint64_t reserved_18_63 : 46; 438236769Sobrien uint64_t reset : 1; /**< When set causes a reset of the FPA with the 439236769Sobrien exception of the RSL. */ 440236769Sobrien uint64_t use_ldt : 1; /**< When clear '0' the FPA will use LDT to load 441236769Sobrien pointers from the L2C. */ 442236769Sobrien uint64_t use_stt : 1; /**< When clear '0' the FPA will use STT to store 443236769Sobrien pointers to the L2C. */ 444236769Sobrien uint64_t enb : 1; /**< Must be set to 1 AFTER writing all config registers 445236769Sobrien and 10 cycles have past. If any of the config 446236769Sobrien register are written after writing this bit the 447236769Sobrien FPA may begin to operate incorrectly. */ 448236769Sobrien uint64_t mem1_err : 7; /**< Causes a flip of the ECC bit associated 38:32 449236769Sobrien respective to bit 6:0 of this field, for FPF 450236769Sobrien FIFO 1. */ 451255253Ssjg uint64_t mem0_err : 7; /**< Causes a flip of the ECC bit associated 38:32 452255253Ssjg respective to bit 6:0 of this field, for FPF 453255253Ssjg FIFO 0. */ 454236769Sobrien#else 455236769Sobrien uint64_t mem0_err : 7; 456236769Sobrien uint64_t mem1_err : 7; 457236769Sobrien uint64_t enb : 1; 458236769Sobrien uint64_t use_stt : 1; 459236769Sobrien uint64_t use_ldt : 1; 460236769Sobrien uint64_t reset : 1; 461236769Sobrien uint64_t reserved_18_63 : 46; 462236769Sobrien#endif 463236769Sobrien } cn30xx; 464236769Sobrien struct cvmx_fpa_ctl_status_cn30xx cn31xx; 465236769Sobrien struct cvmx_fpa_ctl_status_cn30xx cn38xx; 466236769Sobrien struct cvmx_fpa_ctl_status_cn30xx cn38xxp2; 467236769Sobrien struct cvmx_fpa_ctl_status_cn30xx cn50xx; 468236769Sobrien struct cvmx_fpa_ctl_status_cn30xx cn52xx; 469236769Sobrien struct cvmx_fpa_ctl_status_cn30xx cn52xxp1; 470236769Sobrien struct cvmx_fpa_ctl_status_cn30xx cn56xx; 471236769Sobrien struct cvmx_fpa_ctl_status_cn30xx cn56xxp1; 472236769Sobrien struct cvmx_fpa_ctl_status_cn30xx cn58xx; 473236769Sobrien struct cvmx_fpa_ctl_status_cn30xx cn58xxp1; 474236769Sobrien struct cvmx_fpa_ctl_status_s cn61xx; 475236769Sobrien struct cvmx_fpa_ctl_status_s cn63xx; 476236769Sobrien struct cvmx_fpa_ctl_status_cn30xx cn63xxp1; 477236769Sobrien struct cvmx_fpa_ctl_status_s cn66xx; 478236769Sobrien struct cvmx_fpa_ctl_status_s cn68xx; 479236769Sobrien struct cvmx_fpa_ctl_status_s cn68xxp1; 480236769Sobrien struct cvmx_fpa_ctl_status_s cnf71xx; 481236769Sobrien}; 482236769Sobrientypedef union cvmx_fpa_ctl_status cvmx_fpa_ctl_status_t; 483236769Sobrien 484236769Sobrien/** 485236769Sobrien * cvmx_fpa_fpf#_marks 486236769Sobrien * 487236769Sobrien * FPA_FPF1_MARKS = FPA's Queue 1 Free Page FIFO Read Write Marks 488236769Sobrien * 489236769Sobrien * The high and low watermark register that determines when we write and read free pages from L2C 490236769Sobrien * for Queue 1. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value 491236769Sobrien * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75) 492236769Sobrien */ 493236769Sobrienunion cvmx_fpa_fpfx_marks { 494236769Sobrien uint64_t u64; 495236769Sobrien struct cvmx_fpa_fpfx_marks_s { 496236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 497236769Sobrien uint64_t reserved_22_63 : 42; 498236769Sobrien uint64_t fpf_wr : 11; /**< When the number of free-page-pointers in a 499236769Sobrien queue exceeds this value the FPA will write 500236769Sobrien 32-page-pointers of that queue to DRAM. 501236769Sobrien The MAX value for this field should be 502236769Sobrien FPA_FPF1_SIZE[FPF_SIZ]-2. */ 503236769Sobrien uint64_t fpf_rd : 11; /**< When the number of free-page-pointers in a 504236769Sobrien queue drops below this value and there are 505236769Sobrien free-page-pointers in DRAM, the FPA will 506236769Sobrien read one page (32 pointers) from DRAM. 507236769Sobrien This maximum value for this field should be 508236769Sobrien FPA_FPF1_SIZE[FPF_SIZ]-34. The min number 509236769Sobrien for this would be 16. */ 510236769Sobrien#else 511236769Sobrien uint64_t fpf_rd : 11; 512236769Sobrien uint64_t fpf_wr : 11; 513236769Sobrien uint64_t reserved_22_63 : 42; 514236769Sobrien#endif 515236769Sobrien } s; 516236769Sobrien struct cvmx_fpa_fpfx_marks_s cn38xx; 517236769Sobrien struct cvmx_fpa_fpfx_marks_s cn38xxp2; 518236769Sobrien struct cvmx_fpa_fpfx_marks_s cn56xx; 519236769Sobrien struct cvmx_fpa_fpfx_marks_s cn56xxp1; 520236769Sobrien struct cvmx_fpa_fpfx_marks_s cn58xx; 521236769Sobrien struct cvmx_fpa_fpfx_marks_s cn58xxp1; 522236769Sobrien struct cvmx_fpa_fpfx_marks_s cn61xx; 523236769Sobrien struct cvmx_fpa_fpfx_marks_s cn63xx; 524236769Sobrien struct cvmx_fpa_fpfx_marks_s cn63xxp1; 525236769Sobrien struct cvmx_fpa_fpfx_marks_s cn66xx; 526236769Sobrien struct cvmx_fpa_fpfx_marks_s cn68xx; 527236769Sobrien struct cvmx_fpa_fpfx_marks_s cn68xxp1; 528236769Sobrien struct cvmx_fpa_fpfx_marks_s cnf71xx; 529236769Sobrien}; 530236769Sobrientypedef union cvmx_fpa_fpfx_marks cvmx_fpa_fpfx_marks_t; 531236769Sobrien 532236769Sobrien/** 533321964Ssjg * cvmx_fpa_fpf#_size 534236769Sobrien * 535236769Sobrien * FPA_FPFX_SIZE = FPA's Queue 1-7 Free Page FIFO Size 536236769Sobrien * 537236769Sobrien * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are 538236769Sobrien * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used. 539236769Sobrien * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048. 540236769Sobrien */ 541236769Sobrienunion cvmx_fpa_fpfx_size { 542236769Sobrien uint64_t u64; 543236769Sobrien struct cvmx_fpa_fpfx_size_s { 544236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 545236769Sobrien uint64_t reserved_11_63 : 53; 546236769Sobrien uint64_t fpf_siz : 11; /**< The number of entries assigned in the FPA FIFO 547236769Sobrien (used to hold page-pointers) for this Queue. 548236769Sobrien The value of this register must divisable by 2, 549236769Sobrien and the FPA will ignore bit [0] of this register. 550236769Sobrien The total of the FPF_SIZ field of the 8 (0-7) 551236769Sobrien FPA_FPF#_SIZE registers must not exceed 2048. 552236769Sobrien After writing this field the FPA will need 10 553236769Sobrien core clock cycles to be ready for operation. The 554236769Sobrien assignment of location in the FPA FIFO must 555250770Ssjg start with Queue 0, then 1, 2, etc. 556250770Ssjg The number of useable entries will be FPF_SIZ-2. */ 557250770Ssjg#else 558321964Ssjg uint64_t fpf_siz : 11; 559250770Ssjg uint64_t reserved_11_63 : 53; 560250771Ssjg#endif 561250770Ssjg } s; 562250770Ssjg struct cvmx_fpa_fpfx_size_s cn38xx; 563236769Sobrien struct cvmx_fpa_fpfx_size_s cn38xxp2; 564236769Sobrien struct cvmx_fpa_fpfx_size_s cn56xx; 565250770Ssjg struct cvmx_fpa_fpfx_size_s cn56xxp1; 566236769Sobrien struct cvmx_fpa_fpfx_size_s cn58xx; 567250770Ssjg struct cvmx_fpa_fpfx_size_s cn58xxp1; 568250770Ssjg struct cvmx_fpa_fpfx_size_s cn61xx; 569250770Ssjg struct cvmx_fpa_fpfx_size_s cn63xx; 570236769Sobrien struct cvmx_fpa_fpfx_size_s cn63xxp1; 571236769Sobrien struct cvmx_fpa_fpfx_size_s cn66xx; 572236769Sobrien struct cvmx_fpa_fpfx_size_s cn68xx; 573236769Sobrien struct cvmx_fpa_fpfx_size_s cn68xxp1; 574236769Sobrien struct cvmx_fpa_fpfx_size_s cnf71xx; 575236769Sobrien}; 576236769Sobrientypedef union cvmx_fpa_fpfx_size cvmx_fpa_fpfx_size_t; 577236769Sobrien 578236769Sobrien/** 579236769Sobrien * cvmx_fpa_fpf0_marks 580236769Sobrien * 581236769Sobrien * FPA_FPF0_MARKS = FPA's Queue 0 Free Page FIFO Read Write Marks 582236769Sobrien * 583236769Sobrien * The high and low watermark register that determines when we write and read free pages from L2C 584236769Sobrien * for Queue 0. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value 585236769Sobrien * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75) 586236769Sobrien */ 587236769Sobrienunion cvmx_fpa_fpf0_marks { 588236769Sobrien uint64_t u64; 589236769Sobrien struct cvmx_fpa_fpf0_marks_s { 590236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 591236769Sobrien uint64_t reserved_24_63 : 40; 592236769Sobrien uint64_t fpf_wr : 12; /**< When the number of free-page-pointers in a 593236769Sobrien queue exceeds this value the FPA will write 594236769Sobrien 32-page-pointers of that queue to DRAM. 595236769Sobrien The MAX value for this field should be 596236769Sobrien FPA_FPF0_SIZE[FPF_SIZ]-2. */ 597321964Ssjg uint64_t fpf_rd : 12; /**< When the number of free-page-pointers in a 598236769Sobrien queue drops below this value and there are 599236769Sobrien free-page-pointers in DRAM, the FPA will 600236769Sobrien read one page (32 pointers) from DRAM. 601236769Sobrien This maximum value for this field should be 602236769Sobrien FPA_FPF0_SIZE[FPF_SIZ]-34. The min number 603321964Ssjg for this would be 16. */ 604236769Sobrien#else 605236769Sobrien uint64_t fpf_rd : 12; 606236769Sobrien uint64_t fpf_wr : 12; 607236769Sobrien uint64_t reserved_24_63 : 40; 608236769Sobrien#endif 609236769Sobrien } s; 610236769Sobrien struct cvmx_fpa_fpf0_marks_s cn38xx; 611236769Sobrien struct cvmx_fpa_fpf0_marks_s cn38xxp2; 612236769Sobrien struct cvmx_fpa_fpf0_marks_s cn56xx; 613236769Sobrien struct cvmx_fpa_fpf0_marks_s cn56xxp1; 614236769Sobrien struct cvmx_fpa_fpf0_marks_s cn58xx; 615236769Sobrien struct cvmx_fpa_fpf0_marks_s cn58xxp1; 616236769Sobrien struct cvmx_fpa_fpf0_marks_s cn61xx; 617236769Sobrien struct cvmx_fpa_fpf0_marks_s cn63xx; 618236769Sobrien struct cvmx_fpa_fpf0_marks_s cn63xxp1; 619236769Sobrien struct cvmx_fpa_fpf0_marks_s cn66xx; 620236769Sobrien struct cvmx_fpa_fpf0_marks_s cn68xx; 621236769Sobrien struct cvmx_fpa_fpf0_marks_s cn68xxp1; 622236769Sobrien struct cvmx_fpa_fpf0_marks_s cnf71xx; 623236769Sobrien}; 624236769Sobrientypedef union cvmx_fpa_fpf0_marks cvmx_fpa_fpf0_marks_t; 625236769Sobrien 626236769Sobrien/** 627236769Sobrien * cvmx_fpa_fpf0_size 628236769Sobrien * 629236769Sobrien * FPA_FPF0_SIZE = FPA's Queue 0 Free Page FIFO Size 630236769Sobrien * 631321964Ssjg * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are 632236769Sobrien * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used. 633236769Sobrien * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048. 634236769Sobrien */ 635236769Sobrienunion cvmx_fpa_fpf0_size { 636236769Sobrien uint64_t u64; 637236769Sobrien struct cvmx_fpa_fpf0_size_s { 638236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 639236769Sobrien uint64_t reserved_12_63 : 52; 640236769Sobrien uint64_t fpf_siz : 12; /**< The number of entries assigned in the FPA FIFO 641236769Sobrien (used to hold page-pointers) for this Queue. 642236769Sobrien The value of this register must divisable by 2, 643236769Sobrien and the FPA will ignore bit [0] of this register. 644236769Sobrien The total of the FPF_SIZ field of the 8 (0-7) 645236769Sobrien FPA_FPF#_SIZE registers must not exceed 2048. 646236769Sobrien After writing this field the FPA will need 10 647236769Sobrien core clock cycles to be ready for operation. The 648236769Sobrien assignment of location in the FPA FIFO must 649236769Sobrien start with Queue 0, then 1, 2, etc. 650321964Ssjg The number of useable entries will be FPF_SIZ-2. */ 651236769Sobrien#else 652236769Sobrien uint64_t fpf_siz : 12; 653236769Sobrien uint64_t reserved_12_63 : 52; 654236769Sobrien#endif 655236769Sobrien } s; 656236769Sobrien struct cvmx_fpa_fpf0_size_s cn38xx; 657236769Sobrien struct cvmx_fpa_fpf0_size_s cn38xxp2; 658236769Sobrien struct cvmx_fpa_fpf0_size_s cn56xx; 659236769Sobrien struct cvmx_fpa_fpf0_size_s cn56xxp1; 660236769Sobrien struct cvmx_fpa_fpf0_size_s cn58xx; 661236769Sobrien struct cvmx_fpa_fpf0_size_s cn58xxp1; 662236769Sobrien struct cvmx_fpa_fpf0_size_s cn61xx; 663236769Sobrien struct cvmx_fpa_fpf0_size_s cn63xx; 664236769Sobrien struct cvmx_fpa_fpf0_size_s cn63xxp1; 665236769Sobrien struct cvmx_fpa_fpf0_size_s cn66xx; 666236769Sobrien struct cvmx_fpa_fpf0_size_s cn68xx; 667236769Sobrien struct cvmx_fpa_fpf0_size_s cn68xxp1; 668236769Sobrien struct cvmx_fpa_fpf0_size_s cnf71xx; 669236769Sobrien}; 670236769Sobrientypedef union cvmx_fpa_fpf0_size cvmx_fpa_fpf0_size_t; 671236769Sobrien 672236769Sobrien/** 673236769Sobrien * cvmx_fpa_fpf8_marks 674236769Sobrien * 675236769Sobrien * Reserved through 0x238 for additional thresholds 676236769Sobrien * 677236769Sobrien * FPA_FPF8_MARKS = FPA's Queue 8 Free Page FIFO Read Write Marks 678236769Sobrien * 679236769Sobrien * The high and low watermark register that determines when we write and read free pages from L2C 680236769Sobrien * for Queue 8. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value 681236769Sobrien * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75) 682236769Sobrien */ 683236769Sobrienunion cvmx_fpa_fpf8_marks { 684253883Ssjg uint64_t u64; 685253883Ssjg struct cvmx_fpa_fpf8_marks_s { 686253883Ssjg#ifdef __BIG_ENDIAN_BITFIELD 687253883Ssjg uint64_t reserved_22_63 : 42; 688253883Ssjg uint64_t fpf_wr : 11; /**< When the number of free-page-pointers in a 689253883Ssjg queue exceeds this value the FPA will write 690253883Ssjg 32-page-pointers of that queue to DRAM. 691253883Ssjg The MAX value for this field should be 692253883Ssjg FPA_FPF0_SIZE[FPF_SIZ]-2. */ 693236769Sobrien uint64_t fpf_rd : 11; /**< When the number of free-page-pointers in a 694236769Sobrien queue drops below this value and there are 695236769Sobrien free-page-pointers in DRAM, the FPA will 696236769Sobrien read one page (32 pointers) from DRAM. 697236769Sobrien This maximum value for this field should be 698236769Sobrien FPA_FPF0_SIZE[FPF_SIZ]-34. The min number 699236769Sobrien for this would be 16. */ 700236769Sobrien#else 701236769Sobrien uint64_t fpf_rd : 11; 702236769Sobrien uint64_t fpf_wr : 11; 703236769Sobrien uint64_t reserved_22_63 : 42; 704236769Sobrien#endif 705236769Sobrien } s; 706236769Sobrien struct cvmx_fpa_fpf8_marks_s cn68xx; 707236769Sobrien struct cvmx_fpa_fpf8_marks_s cn68xxp1; 708236769Sobrien}; 709236769Sobrientypedef union cvmx_fpa_fpf8_marks cvmx_fpa_fpf8_marks_t; 710236769Sobrien 711236769Sobrien/** 712236769Sobrien * cvmx_fpa_fpf8_size 713236769Sobrien * 714236769Sobrien * FPA_FPF8_SIZE = FPA's Queue 8 Free Page FIFO Size 715236769Sobrien * 716236769Sobrien * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are 717236769Sobrien * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used. 718321964Ssjg * The sum of the 9 (0-8) FPA_FPF#_SIZE registers must be limited to 2048. 719292068Ssjg */ 720292068Ssjgunion cvmx_fpa_fpf8_size { 721292068Ssjg uint64_t u64; 722292068Ssjg struct cvmx_fpa_fpf8_size_s { 723292068Ssjg#ifdef __BIG_ENDIAN_BITFIELD 724292068Ssjg uint64_t reserved_12_63 : 52; 725292068Ssjg uint64_t fpf_siz : 12; /**< The number of entries assigned in the FPA FIFO 726236769Sobrien (used to hold page-pointers) for this Queue. 727236769Sobrien The value of this register must divisable by 2, 728236769Sobrien and the FPA will ignore bit [0] of this register. 729236769Sobrien The total of the FPF_SIZ field of the 8 (0-7) 730236769Sobrien FPA_FPF#_SIZE registers must not exceed 2048. 731236769Sobrien After writing this field the FPA will need 10 732236769Sobrien core clock cycles to be ready for operation. The 733236769Sobrien assignment of location in the FPA FIFO must 734236769Sobrien start with Queue 0, then 1, 2, etc. 735236769Sobrien The number of useable entries will be FPF_SIZ-2. */ 736236769Sobrien#else 737236769Sobrien uint64_t fpf_siz : 12; 738236769Sobrien uint64_t reserved_12_63 : 52; 739236769Sobrien#endif 740236769Sobrien } s; 741236769Sobrien struct cvmx_fpa_fpf8_size_s cn68xx; 742236769Sobrien struct cvmx_fpa_fpf8_size_s cn68xxp1; 743321964Ssjg}; 744236769Sobrientypedef union cvmx_fpa_fpf8_size cvmx_fpa_fpf8_size_t; 745236769Sobrien 746236769Sobrien/** 747236769Sobrien * cvmx_fpa_int_enb 748236769Sobrien * 749236769Sobrien * FPA_INT_ENB = FPA's Interrupt Enable 750236769Sobrien * 751236769Sobrien * The FPA's interrupt enable register. 752321964Ssjg */ 753236769Sobrienunion cvmx_fpa_int_enb { 754236769Sobrien uint64_t u64; 755321964Ssjg struct cvmx_fpa_int_enb_s { 756321964Ssjg#ifdef __BIG_ENDIAN_BITFIELD 757321964Ssjg uint64_t reserved_50_63 : 14; 758236769Sobrien uint64_t paddr_e : 1; /**< When set (1) and bit 49 of the FPA_INT_SUM 759321964Ssjg register is asserted the FPA will assert an 760236769Sobrien interrupt. */ 761321964Ssjg uint64_t reserved_44_48 : 5; 762292068Ssjg uint64_t free7 : 1; /**< When set (1) and bit 43 of the FPA_INT_SUM 763292068Ssjg register is asserted the FPA will assert an 764292068Ssjg interrupt. */ 765292068Ssjg uint64_t free6 : 1; /**< When set (1) and bit 42 of the FPA_INT_SUM 766292068Ssjg register is asserted the FPA will assert an 767292068Ssjg interrupt. */ 768292068Ssjg uint64_t free5 : 1; /**< When set (1) and bit 41 of the FPA_INT_SUM 769292068Ssjg register is asserted the FPA will assert an 770292068Ssjg interrupt. */ 771292068Ssjg uint64_t free4 : 1; /**< When set (1) and bit 40 of the FPA_INT_SUM 772292068Ssjg register is asserted the FPA will assert an 773292068Ssjg interrupt. */ 774292068Ssjg uint64_t free3 : 1; /**< When set (1) and bit 39 of the FPA_INT_SUM 775292068Ssjg register is asserted the FPA will assert an 776292068Ssjg interrupt. */ 777292068Ssjg uint64_t free2 : 1; /**< When set (1) and bit 38 of the FPA_INT_SUM 778292068Ssjg register is asserted the FPA will assert an 779292068Ssjg interrupt. */ 780236769Sobrien uint64_t free1 : 1; /**< When set (1) and bit 37 of the FPA_INT_SUM 781321964Ssjg register is asserted the FPA will assert an 782292068Ssjg interrupt. */ 783292068Ssjg uint64_t free0 : 1; /**< When set (1) and bit 36 of the FPA_INT_SUM 784321964Ssjg register is asserted the FPA will assert an 785292068Ssjg interrupt. */ 786292068Ssjg uint64_t pool7th : 1; /**< When set (1) and bit 35 of the FPA_INT_SUM 787236769Sobrien register is asserted the FPA will assert an 788236769Sobrien interrupt. */ 789292068Ssjg uint64_t pool6th : 1; /**< When set (1) and bit 34 of the FPA_INT_SUM 790292068Ssjg register is asserted the FPA will assert an 791236769Sobrien interrupt. */ 792236769Sobrien uint64_t pool5th : 1; /**< When set (1) and bit 33 of the FPA_INT_SUM 793236769Sobrien register is asserted the FPA will assert an 794236769Sobrien interrupt. */ 795236769Sobrien uint64_t pool4th : 1; /**< When set (1) and bit 32 of the FPA_INT_SUM 796236769Sobrien register is asserted the FPA will assert an 797236769Sobrien interrupt. */ 798236769Sobrien uint64_t pool3th : 1; /**< When set (1) and bit 31 of the FPA_INT_SUM 799236769Sobrien register is asserted the FPA will assert an 800236769Sobrien interrupt. */ 801236769Sobrien uint64_t pool2th : 1; /**< When set (1) and bit 30 of the FPA_INT_SUM 802236769Sobrien register is asserted the FPA will assert an 803236769Sobrien interrupt. */ 804236769Sobrien uint64_t pool1th : 1; /**< When set (1) and bit 29 of the FPA_INT_SUM 805236769Sobrien register is asserted the FPA will assert an 806236769Sobrien interrupt. */ 807236769Sobrien uint64_t pool0th : 1; /**< When set (1) and bit 28 of the FPA_INT_SUM 808236769Sobrien register is asserted the FPA will assert an 809236769Sobrien interrupt. */ 810236769Sobrien uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 811236769Sobrien register is asserted the FPA will assert an 812236769Sobrien interrupt. */ 813236769Sobrien uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 814236769Sobrien register is asserted the FPA will assert an 815236769Sobrien interrupt. */ 816236769Sobrien uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 817236769Sobrien register is asserted the FPA will assert an 818236769Sobrien interrupt. */ 819236769Sobrien uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 820236769Sobrien register is asserted the FPA will assert an 821253883Ssjg interrupt. */ 822236769Sobrien uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 823236769Sobrien register is asserted the FPA will assert an 824236769Sobrien interrupt. */ 825236769Sobrien uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 826236769Sobrien register is asserted the FPA will assert an 827236769Sobrien interrupt. */ 828236769Sobrien uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 829236769Sobrien register is asserted the FPA will assert an 830236769Sobrien interrupt. */ 831236769Sobrien uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 832236769Sobrien register is asserted the FPA will assert an 833236769Sobrien interrupt. */ 834236769Sobrien uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 835236769Sobrien register is asserted the FPA will assert an 836236769Sobrien interrupt. */ 837236769Sobrien uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 838253883Ssjg register is asserted the FPA will assert an 839236769Sobrien interrupt. */ 840236769Sobrien uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 841236769Sobrien register is asserted the FPA will assert an 842236769Sobrien interrupt. */ 843236769Sobrien uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 844236769Sobrien register is asserted the FPA will assert an 845236769Sobrien interrupt. */ 846236769Sobrien uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 847236769Sobrien register is asserted the FPA will assert an 848236769Sobrien interrupt. */ 849236769Sobrien uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 850236769Sobrien register is asserted the FPA will assert an 851321964Ssjg interrupt. */ 852236769Sobrien uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 853236769Sobrien register is asserted the FPA will assert an 854236769Sobrien interrupt. */ 855236769Sobrien uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 856236769Sobrien register is asserted the FPA will assert an 857236769Sobrien interrupt. */ 858236769Sobrien uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 859236769Sobrien register is asserted the FPA will assert an 860236769Sobrien interrupt. */ 861236769Sobrien uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 862236769Sobrien register is asserted the FPA will assert an 863236769Sobrien interrupt. */ 864236769Sobrien uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 865236769Sobrien register is asserted the FPA will assert an 866236769Sobrien interrupt. */ 867236769Sobrien uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 868236769Sobrien register is asserted the FPA will assert an 869236769Sobrien interrupt. */ 870236769Sobrien uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 871236769Sobrien register is asserted the FPA will assert an 872236769Sobrien interrupt. */ 873236769Sobrien uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 874236769Sobrien register is asserted the FPA will assert an 875236769Sobrien interrupt. */ 876236769Sobrien uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 877236769Sobrien register is asserted the FPA will assert an 878236769Sobrien interrupt. */ 879236769Sobrien uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 880236769Sobrien register is asserted the FPA will assert an 881321964Ssjg interrupt. */ 882236769Sobrien uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 883236769Sobrien register is asserted the FPA will assert an 884236769Sobrien interrupt. */ 885236769Sobrien uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 886236769Sobrien register is asserted the FPA will assert an 887236769Sobrien interrupt. */ 888236769Sobrien uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 889236769Sobrien register is asserted the FPA will assert an 890236769Sobrien interrupt. */ 891236769Sobrien uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 892236769Sobrien register is asserted the FPA will assert an 893236769Sobrien interrupt. */ 894236769Sobrien#else 895236769Sobrien uint64_t fed0_sbe : 1; 896236769Sobrien uint64_t fed0_dbe : 1; 897236769Sobrien uint64_t fed1_sbe : 1; 898236769Sobrien uint64_t fed1_dbe : 1; 899236769Sobrien uint64_t q0_und : 1; 900236769Sobrien uint64_t q0_coff : 1; 901236769Sobrien uint64_t q0_perr : 1; 902236769Sobrien uint64_t q1_und : 1; 903236769Sobrien uint64_t q1_coff : 1; 904236769Sobrien uint64_t q1_perr : 1; 905236769Sobrien uint64_t q2_und : 1; 906236769Sobrien uint64_t q2_coff : 1; 907236769Sobrien uint64_t q2_perr : 1; 908236769Sobrien uint64_t q3_und : 1; 909236769Sobrien uint64_t q3_coff : 1; 910236769Sobrien uint64_t q3_perr : 1; 911236769Sobrien uint64_t q4_und : 1; 912236769Sobrien uint64_t q4_coff : 1; 913236769Sobrien uint64_t q4_perr : 1; 914236769Sobrien uint64_t q5_und : 1; 915236769Sobrien uint64_t q5_coff : 1; 916236769Sobrien uint64_t q5_perr : 1; 917236769Sobrien uint64_t q6_und : 1; 918236769Sobrien uint64_t q6_coff : 1; 919236769Sobrien uint64_t q6_perr : 1; 920236769Sobrien uint64_t q7_und : 1; 921236769Sobrien uint64_t q7_coff : 1; 922236769Sobrien uint64_t q7_perr : 1; 923236769Sobrien uint64_t pool0th : 1; 924236769Sobrien uint64_t pool1th : 1; 925236769Sobrien uint64_t pool2th : 1; 926236769Sobrien uint64_t pool3th : 1; 927236769Sobrien uint64_t pool4th : 1; 928236769Sobrien uint64_t pool5th : 1; 929236769Sobrien uint64_t pool6th : 1; 930236769Sobrien uint64_t pool7th : 1; 931236769Sobrien uint64_t free0 : 1; 932236769Sobrien uint64_t free1 : 1; 933236769Sobrien uint64_t free2 : 1; 934236769Sobrien uint64_t free3 : 1; 935236769Sobrien uint64_t free4 : 1; 936321964Ssjg uint64_t free5 : 1; 937236769Sobrien uint64_t free6 : 1; 938236769Sobrien uint64_t free7 : 1; 939236769Sobrien uint64_t reserved_44_48 : 5; 940236769Sobrien uint64_t paddr_e : 1; 941236769Sobrien uint64_t reserved_50_63 : 14; 942236769Sobrien#endif 943236769Sobrien } s; 944236769Sobrien struct cvmx_fpa_int_enb_cn30xx { 945236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 946236769Sobrien uint64_t reserved_28_63 : 36; 947236769Sobrien uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 948236769Sobrien register is asserted the FPA will assert an 949236769Sobrien interrupt. */ 950236769Sobrien uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 951236769Sobrien register is asserted the FPA will assert an 952236769Sobrien interrupt. */ 953236769Sobrien uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 954236769Sobrien register is asserted the FPA will assert an 955236769Sobrien interrupt. */ 956236769Sobrien uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 957236769Sobrien register is asserted the FPA will assert an 958236769Sobrien interrupt. */ 959236769Sobrien uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 960236769Sobrien register is asserted the FPA will assert an 961236769Sobrien interrupt. */ 962253883Ssjg uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 963253883Ssjg register is asserted the FPA will assert an 964253883Ssjg interrupt. */ 965253883Ssjg uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 966253883Ssjg register is asserted the FPA will assert an 967253883Ssjg interrupt. */ 968253883Ssjg uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 969253883Ssjg register is asserted the FPA will assert an 970236769Sobrien interrupt. */ 971236769Sobrien uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 972236769Sobrien register is asserted the FPA will assert an 973236769Sobrien interrupt. */ 974236769Sobrien uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 975236769Sobrien register is asserted the FPA will assert an 976236769Sobrien interrupt. */ 977236769Sobrien uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 978236769Sobrien register is asserted the FPA will assert an 979236769Sobrien interrupt. */ 980236769Sobrien uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 981236769Sobrien register is asserted the FPA will assert an 982236769Sobrien interrupt. */ 983236769Sobrien uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 984236769Sobrien register is asserted the FPA will assert an 985236769Sobrien interrupt. */ 986236769Sobrien uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 987236769Sobrien register is asserted the FPA will assert an 988236769Sobrien interrupt. */ 989236769Sobrien uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 990236769Sobrien register is asserted the FPA will assert an 991236769Sobrien interrupt. */ 992236769Sobrien uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 993236769Sobrien register is asserted the FPA will assert an 994236769Sobrien interrupt. */ 995236769Sobrien uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 996236769Sobrien register is asserted the FPA will assert an 997236769Sobrien interrupt. */ 998236769Sobrien uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 999236769Sobrien register is asserted the FPA will assert an 1000236769Sobrien interrupt. */ 1001236769Sobrien uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 1002236769Sobrien register is asserted the FPA will assert an 1003236769Sobrien interrupt. */ 1004321964Ssjg uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 1005321964Ssjg register is asserted the FPA will assert an 1006321964Ssjg interrupt. */ 1007321964Ssjg uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 1008253883Ssjg register is asserted the FPA will assert an 1009236769Sobrien interrupt. */ 1010292068Ssjg uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 1011236769Sobrien register is asserted the FPA will assert an 1012236769Sobrien interrupt. */ 1013236769Sobrien uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 1014236769Sobrien register is asserted the FPA will assert an 1015236769Sobrien interrupt. */ 1016236769Sobrien uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 1017236769Sobrien register is asserted the FPA will assert an 1018236769Sobrien interrupt. */ 1019236769Sobrien uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 1020236769Sobrien register is asserted the FPA will assert an 1021236769Sobrien interrupt. */ 1022236769Sobrien uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 1023236769Sobrien register is asserted the FPA will assert an 1024236769Sobrien interrupt. */ 1025236769Sobrien uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 1026236769Sobrien register is asserted the FPA will assert an 1027236769Sobrien interrupt. */ 1028236769Sobrien uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 1029236769Sobrien register is asserted the FPA will assert an 1030236769Sobrien interrupt. */ 1031236769Sobrien#else 1032236769Sobrien uint64_t fed0_sbe : 1; 1033236769Sobrien uint64_t fed0_dbe : 1; 1034236769Sobrien uint64_t fed1_sbe : 1; 1035236769Sobrien uint64_t fed1_dbe : 1; 1036236769Sobrien uint64_t q0_und : 1; 1037236769Sobrien uint64_t q0_coff : 1; 1038236769Sobrien uint64_t q0_perr : 1; 1039236769Sobrien uint64_t q1_und : 1; 1040236769Sobrien uint64_t q1_coff : 1; 1041236769Sobrien uint64_t q1_perr : 1; 1042236769Sobrien uint64_t q2_und : 1; 1043236769Sobrien uint64_t q2_coff : 1; 1044236769Sobrien uint64_t q2_perr : 1; 1045236769Sobrien uint64_t q3_und : 1; 1046236769Sobrien uint64_t q3_coff : 1; 1047236769Sobrien uint64_t q3_perr : 1; 1048236769Sobrien uint64_t q4_und : 1; 1049236769Sobrien uint64_t q4_coff : 1; 1050321964Ssjg uint64_t q4_perr : 1; 1051236769Sobrien uint64_t q5_und : 1; 1052236769Sobrien uint64_t q5_coff : 1; 1053236769Sobrien uint64_t q5_perr : 1; 1054236769Sobrien uint64_t q6_und : 1; 1055236769Sobrien uint64_t q6_coff : 1; 1056236769Sobrien uint64_t q6_perr : 1; 1057236769Sobrien uint64_t q7_und : 1; 1058236769Sobrien uint64_t q7_coff : 1; 1059236769Sobrien uint64_t q7_perr : 1; 1060236769Sobrien uint64_t reserved_28_63 : 36; 1061236769Sobrien#endif 1062236769Sobrien } cn30xx; 1063236769Sobrien struct cvmx_fpa_int_enb_cn30xx cn31xx; 1064236769Sobrien struct cvmx_fpa_int_enb_cn30xx cn38xx; 1065236769Sobrien struct cvmx_fpa_int_enb_cn30xx cn38xxp2; 1066236769Sobrien struct cvmx_fpa_int_enb_cn30xx cn50xx; 1067236769Sobrien struct cvmx_fpa_int_enb_cn30xx cn52xx; 1068236769Sobrien struct cvmx_fpa_int_enb_cn30xx cn52xxp1; 1069236769Sobrien struct cvmx_fpa_int_enb_cn30xx cn56xx; 1070236769Sobrien struct cvmx_fpa_int_enb_cn30xx cn56xxp1; 1071236769Sobrien struct cvmx_fpa_int_enb_cn30xx cn58xx; 1072236769Sobrien struct cvmx_fpa_int_enb_cn30xx cn58xxp1; 1073236769Sobrien struct cvmx_fpa_int_enb_cn61xx { 1074236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 1075236769Sobrien uint64_t reserved_50_63 : 14; 1076236769Sobrien uint64_t paddr_e : 1; /**< When set (1) and bit 49 of the FPA_INT_SUM 1077236769Sobrien register is asserted the FPA will assert an 1078236769Sobrien interrupt. */ 1079236769Sobrien uint64_t res_44 : 5; /**< Reserved */ 1080236769Sobrien uint64_t free7 : 1; /**< When set (1) and bit 43 of the FPA_INT_SUM 1081236769Sobrien register is asserted the FPA will assert an 1082236769Sobrien interrupt. */ 1083236769Sobrien uint64_t free6 : 1; /**< When set (1) and bit 42 of the FPA_INT_SUM 1084236769Sobrien register is asserted the FPA will assert an 1085236769Sobrien interrupt. */ 1086236769Sobrien uint64_t free5 : 1; /**< When set (1) and bit 41 of the FPA_INT_SUM 1087236769Sobrien register is asserted the FPA will assert an 1088292068Ssjg interrupt. */ 1089236769Sobrien uint64_t free4 : 1; /**< When set (1) and bit 40 of the FPA_INT_SUM 1090236769Sobrien register is asserted the FPA will assert an 1091236769Sobrien interrupt. */ 1092236769Sobrien uint64_t free3 : 1; /**< When set (1) and bit 39 of the FPA_INT_SUM 1093236769Sobrien register is asserted the FPA will assert an 1094236769Sobrien interrupt. */ 1095236769Sobrien uint64_t free2 : 1; /**< When set (1) and bit 38 of the FPA_INT_SUM 1096236769Sobrien register is asserted the FPA will assert an 1097236769Sobrien interrupt. */ 1098236769Sobrien uint64_t free1 : 1; /**< When set (1) and bit 37 of the FPA_INT_SUM 1099236769Sobrien register is asserted the FPA will assert an 1100236769Sobrien interrupt. */ 1101236769Sobrien uint64_t free0 : 1; /**< When set (1) and bit 36 of the FPA_INT_SUM 1102236769Sobrien register is asserted the FPA will assert an 1103236769Sobrien interrupt. */ 1104236769Sobrien uint64_t pool7th : 1; /**< When set (1) and bit 35 of the FPA_INT_SUM 1105236769Sobrien register is asserted the FPA will assert an 1106236769Sobrien interrupt. */ 1107236769Sobrien uint64_t pool6th : 1; /**< When set (1) and bit 34 of the FPA_INT_SUM 1108236769Sobrien register is asserted the FPA will assert an 1109236769Sobrien interrupt. */ 1110236769Sobrien uint64_t pool5th : 1; /**< When set (1) and bit 33 of the FPA_INT_SUM 1111236769Sobrien register is asserted the FPA will assert an 1112236769Sobrien interrupt. */ 1113236769Sobrien uint64_t pool4th : 1; /**< When set (1) and bit 32 of the FPA_INT_SUM 1114236769Sobrien register is asserted the FPA will assert an 1115321964Ssjg interrupt. */ 1116236769Sobrien uint64_t pool3th : 1; /**< When set (1) and bit 31 of the FPA_INT_SUM 1117236769Sobrien register is asserted the FPA will assert an 1118292068Ssjg interrupt. */ 1119236769Sobrien uint64_t pool2th : 1; /**< When set (1) and bit 30 of the FPA_INT_SUM 1120236769Sobrien register is asserted the FPA will assert an 1121236769Sobrien interrupt. */ 1122236769Sobrien uint64_t pool1th : 1; /**< When set (1) and bit 29 of the FPA_INT_SUM 1123236769Sobrien register is asserted the FPA will assert an 1124236769Sobrien interrupt. */ 1125236769Sobrien uint64_t pool0th : 1; /**< When set (1) and bit 28 of the FPA_INT_SUM 1126236769Sobrien register is asserted the FPA will assert an 1127236769Sobrien interrupt. */ 1128236769Sobrien uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 1129236769Sobrien register is asserted the FPA will assert an 1130236769Sobrien interrupt. */ 1131236769Sobrien uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 1132236769Sobrien register is asserted the FPA will assert an 1133236769Sobrien interrupt. */ 1134236769Sobrien uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 1135236769Sobrien register is asserted the FPA will assert an 1136236769Sobrien interrupt. */ 1137236769Sobrien uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 1138236769Sobrien register is asserted the FPA will assert an 1139236769Sobrien interrupt. */ 1140236769Sobrien uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 1141236769Sobrien register is asserted the FPA will assert an 1142236769Sobrien interrupt. */ 1143236769Sobrien uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 1144236769Sobrien register is asserted the FPA will assert an 1145236769Sobrien interrupt. */ 1146236769Sobrien uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 1147236769Sobrien register is asserted the FPA will assert an 1148236769Sobrien interrupt. */ 1149236769Sobrien uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 1150236769Sobrien register is asserted the FPA will assert an 1151236769Sobrien interrupt. */ 1152236769Sobrien uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 1153236769Sobrien register is asserted the FPA will assert an 1154236769Sobrien interrupt. */ 1155236769Sobrien uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 1156236769Sobrien register is asserted the FPA will assert an 1157236769Sobrien interrupt. */ 1158236769Sobrien uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 1159236769Sobrien register is asserted the FPA will assert an 1160236769Sobrien interrupt. */ 1161236769Sobrien uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 1162236769Sobrien register is asserted the FPA will assert an 1163236769Sobrien interrupt. */ 1164236769Sobrien uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 1165236769Sobrien register is asserted the FPA will assert an 1166236769Sobrien interrupt. */ 1167236769Sobrien uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 1168236769Sobrien register is asserted the FPA will assert an 1169236769Sobrien interrupt. */ 1170236769Sobrien uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 1171236769Sobrien register is asserted the FPA will assert an 1172236769Sobrien interrupt. */ 1173236769Sobrien uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 1174236769Sobrien register is asserted the FPA will assert an 1175236769Sobrien interrupt. */ 1176236769Sobrien uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 1177236769Sobrien register is asserted the FPA will assert an 1178236769Sobrien interrupt. */ 1179236769Sobrien uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 1180236769Sobrien register is asserted the FPA will assert an 1181236769Sobrien interrupt. */ 1182237578Sobrien uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 1183236769Sobrien register is asserted the FPA will assert an 1184321964Ssjg interrupt. */ 1185236769Sobrien uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 1186236769Sobrien register is asserted the FPA will assert an 1187236769Sobrien interrupt. */ 1188236769Sobrien uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 1189236769Sobrien register is asserted the FPA will assert an 1190236769Sobrien interrupt. */ 1191236769Sobrien uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 1192236769Sobrien register is asserted the FPA will assert an 1193236769Sobrien interrupt. */ 1194236769Sobrien uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 1195236769Sobrien register is asserted the FPA will assert an 1196236769Sobrien interrupt. */ 1197236769Sobrien uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 1198236769Sobrien register is asserted the FPA will assert an 1199236769Sobrien interrupt. */ 1200236769Sobrien uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 1201236769Sobrien register is asserted the FPA will assert an 1202236769Sobrien interrupt. */ 1203236769Sobrien uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 1204236769Sobrien register is asserted the FPA will assert an 1205321964Ssjg interrupt. */ 1206236769Sobrien uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 1207236769Sobrien register is asserted the FPA will assert an 1208236769Sobrien interrupt. */ 1209236769Sobrien uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 1210236769Sobrien register is asserted the FPA will assert an 1211236769Sobrien interrupt. */ 1212236769Sobrien#else 1213236769Sobrien uint64_t fed0_sbe : 1; 1214236769Sobrien uint64_t fed0_dbe : 1; 1215236769Sobrien uint64_t fed1_sbe : 1; 1216236769Sobrien uint64_t fed1_dbe : 1; 1217236769Sobrien uint64_t q0_und : 1; 1218236769Sobrien uint64_t q0_coff : 1; 1219236769Sobrien uint64_t q0_perr : 1; 1220236769Sobrien uint64_t q1_und : 1; 1221236769Sobrien uint64_t q1_coff : 1; 1222236769Sobrien uint64_t q1_perr : 1; 1223236769Sobrien uint64_t q2_und : 1; 1224236769Sobrien uint64_t q2_coff : 1; 1225236769Sobrien uint64_t q2_perr : 1; 1226236769Sobrien uint64_t q3_und : 1; 1227236769Sobrien uint64_t q3_coff : 1; 1228236769Sobrien uint64_t q3_perr : 1; 1229236769Sobrien uint64_t q4_und : 1; 1230237578Sobrien uint64_t q4_coff : 1; 1231236769Sobrien uint64_t q4_perr : 1; 1232321964Ssjg uint64_t q5_und : 1; 1233236769Sobrien uint64_t q5_coff : 1; 1234236769Sobrien uint64_t q5_perr : 1; 1235236769Sobrien uint64_t q6_und : 1; 1236236769Sobrien uint64_t q6_coff : 1; 1237236769Sobrien uint64_t q6_perr : 1; 1238236769Sobrien uint64_t q7_und : 1; 1239236769Sobrien uint64_t q7_coff : 1; 1240236769Sobrien uint64_t q7_perr : 1; 1241236769Sobrien uint64_t pool0th : 1; 1242236769Sobrien uint64_t pool1th : 1; 1243236769Sobrien uint64_t pool2th : 1; 1244236769Sobrien uint64_t pool3th : 1; 1245236769Sobrien uint64_t pool4th : 1; 1246236769Sobrien uint64_t pool5th : 1; 1247236769Sobrien uint64_t pool6th : 1; 1248321964Ssjg uint64_t pool7th : 1; 1249236769Sobrien uint64_t free0 : 1; 1250236769Sobrien uint64_t free1 : 1; 1251236769Sobrien uint64_t free2 : 1; 1252236769Sobrien uint64_t free3 : 1; 1253236769Sobrien uint64_t free4 : 1; 1254236769Sobrien uint64_t free5 : 1; 1255236769Sobrien uint64_t free6 : 1; 1256236769Sobrien uint64_t free7 : 1; 1257236769Sobrien uint64_t res_44 : 5; 1258236769Sobrien uint64_t paddr_e : 1; 1259236769Sobrien uint64_t reserved_50_63 : 14; 1260236769Sobrien#endif 1261236769Sobrien } cn61xx; 1262236769Sobrien struct cvmx_fpa_int_enb_cn63xx { 1263236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 1264236769Sobrien uint64_t reserved_44_63 : 20; 1265236769Sobrien uint64_t free7 : 1; /**< When set (1) and bit 43 of the FPA_INT_SUM 1266236769Sobrien register is asserted the FPA will assert an 1267236769Sobrien interrupt. */ 1268236769Sobrien uint64_t free6 : 1; /**< When set (1) and bit 42 of the FPA_INT_SUM 1269236769Sobrien register is asserted the FPA will assert an 1270236769Sobrien interrupt. */ 1271236769Sobrien uint64_t free5 : 1; /**< When set (1) and bit 41 of the FPA_INT_SUM 1272237578Sobrien register is asserted the FPA will assert an 1273236769Sobrien interrupt. */ 1274321964Ssjg uint64_t free4 : 1; /**< When set (1) and bit 40 of the FPA_INT_SUM 1275236769Sobrien register is asserted the FPA will assert an 1276236769Sobrien interrupt. */ 1277236769Sobrien uint64_t free3 : 1; /**< When set (1) and bit 39 of the FPA_INT_SUM 1278236769Sobrien register is asserted the FPA will assert an 1279236769Sobrien interrupt. */ 1280236769Sobrien uint64_t free2 : 1; /**< When set (1) and bit 38 of the FPA_INT_SUM 1281236769Sobrien register is asserted the FPA will assert an 1282236769Sobrien interrupt. */ 1283236769Sobrien uint64_t free1 : 1; /**< When set (1) and bit 37 of the FPA_INT_SUM 1284236769Sobrien register is asserted the FPA will assert an 1285236769Sobrien interrupt. */ 1286236769Sobrien uint64_t free0 : 1; /**< When set (1) and bit 36 of the FPA_INT_SUM 1287236769Sobrien register is asserted the FPA will assert an 1288321964Ssjg interrupt. */ 1289236769Sobrien uint64_t pool7th : 1; /**< When set (1) and bit 35 of the FPA_INT_SUM 1290236769Sobrien register is asserted the FPA will assert an 1291236769Sobrien interrupt. */ 1292236769Sobrien uint64_t pool6th : 1; /**< When set (1) and bit 34 of the FPA_INT_SUM 1293236769Sobrien register is asserted the FPA will assert an 1294236769Sobrien interrupt. */ 1295236769Sobrien uint64_t pool5th : 1; /**< When set (1) and bit 33 of the FPA_INT_SUM 1296236769Sobrien register is asserted the FPA will assert an 1297236769Sobrien interrupt. */ 1298236769Sobrien uint64_t pool4th : 1; /**< When set (1) and bit 32 of the FPA_INT_SUM 1299236769Sobrien register is asserted the FPA will assert an 1300236769Sobrien interrupt. */ 1301236769Sobrien uint64_t pool3th : 1; /**< When set (1) and bit 31 of the FPA_INT_SUM 1302236769Sobrien register is asserted the FPA will assert an 1303236769Sobrien interrupt. */ 1304236769Sobrien uint64_t pool2th : 1; /**< When set (1) and bit 30 of the FPA_INT_SUM 1305236769Sobrien register is asserted the FPA will assert an 1306236769Sobrien interrupt. */ 1307236769Sobrien uint64_t pool1th : 1; /**< When set (1) and bit 29 of the FPA_INT_SUM 1308236769Sobrien register is asserted the FPA will assert an 1309236769Sobrien interrupt. */ 1310236769Sobrien uint64_t pool0th : 1; /**< When set (1) and bit 28 of the FPA_INT_SUM 1311236769Sobrien register is asserted the FPA will assert an 1312236769Sobrien interrupt. */ 1313237578Sobrien uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 1314236769Sobrien register is asserted the FPA will assert an 1315321964Ssjg interrupt. */ 1316236769Sobrien uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 1317236769Sobrien register is asserted the FPA will assert an 1318236769Sobrien interrupt. */ 1319236769Sobrien uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 1320236769Sobrien register is asserted the FPA will assert an 1321236769Sobrien interrupt. */ 1322236769Sobrien uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 1323236769Sobrien register is asserted the FPA will assert an 1324236769Sobrien interrupt. */ 1325236769Sobrien uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 1326236769Sobrien register is asserted the FPA will assert an 1327236769Sobrien interrupt. */ 1328236769Sobrien uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 1329236769Sobrien register is asserted the FPA will assert an 1330236769Sobrien interrupt. */ 1331321964Ssjg uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 1332236769Sobrien register is asserted the FPA will assert an 1333236769Sobrien interrupt. */ 1334236769Sobrien uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 1335236769Sobrien register is asserted the FPA will assert an 1336236769Sobrien interrupt. */ 1337236769Sobrien uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 1338236769Sobrien register is asserted the FPA will assert an 1339236769Sobrien interrupt. */ 1340236769Sobrien uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 1341236769Sobrien register is asserted the FPA will assert an 1342236769Sobrien interrupt. */ 1343236769Sobrien uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 1344236769Sobrien register is asserted the FPA will assert an 1345236769Sobrien interrupt. */ 1346236769Sobrien uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 1347236769Sobrien register is asserted the FPA will assert an 1348236769Sobrien interrupt. */ 1349236769Sobrien uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 1350236769Sobrien register is asserted the FPA will assert an 1351236769Sobrien interrupt. */ 1352236769Sobrien uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 1353236769Sobrien register is asserted the FPA will assert an 1354236769Sobrien interrupt. */ 1355236769Sobrien uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 1356236769Sobrien register is asserted the FPA will assert an 1357237578Sobrien interrupt. */ 1358236769Sobrien uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 1359236769Sobrien register is asserted the FPA will assert an 1360236769Sobrien interrupt. */ 1361236769Sobrien uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 1362236769Sobrien register is asserted the FPA will assert an 1363236769Sobrien interrupt. */ 1364236769Sobrien uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 1365236769Sobrien register is asserted the FPA will assert an 1366236769Sobrien interrupt. */ 1367236769Sobrien uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 1368236769Sobrien register is asserted the FPA will assert an 1369236769Sobrien interrupt. */ 1370236769Sobrien uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 1371236769Sobrien register is asserted the FPA will assert an 1372236769Sobrien interrupt. */ 1373236769Sobrien uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 1374236769Sobrien register is asserted the FPA will assert an 1375236769Sobrien interrupt. */ 1376236769Sobrien uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 1377236769Sobrien register is asserted the FPA will assert an 1378236769Sobrien interrupt. */ 1379236769Sobrien uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 1380236769Sobrien register is asserted the FPA will assert an 1381236769Sobrien interrupt. */ 1382236769Sobrien uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 1383236769Sobrien register is asserted the FPA will assert an 1384236769Sobrien interrupt. */ 1385236769Sobrien uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 1386236769Sobrien register is asserted the FPA will assert an 1387236769Sobrien interrupt. */ 1388236769Sobrien uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 1389236769Sobrien register is asserted the FPA will assert an 1390236769Sobrien interrupt. */ 1391236769Sobrien uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 1392236769Sobrien register is asserted the FPA will assert an 1393236769Sobrien interrupt. */ 1394236769Sobrien uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 1395236769Sobrien register is asserted the FPA will assert an 1396236769Sobrien interrupt. */ 1397236769Sobrien#else 1398236769Sobrien uint64_t fed0_sbe : 1; 1399236769Sobrien uint64_t fed0_dbe : 1; 1400236769Sobrien uint64_t fed1_sbe : 1; 1401236769Sobrien uint64_t fed1_dbe : 1; 1402236769Sobrien uint64_t q0_und : 1; 1403236769Sobrien uint64_t q0_coff : 1; 1404236769Sobrien uint64_t q0_perr : 1; 1405236769Sobrien uint64_t q1_und : 1; 1406236769Sobrien uint64_t q1_coff : 1; 1407236769Sobrien uint64_t q1_perr : 1; 1408236769Sobrien uint64_t q2_und : 1; 1409236769Sobrien uint64_t q2_coff : 1; 1410236769Sobrien uint64_t q2_perr : 1; 1411236769Sobrien uint64_t q3_und : 1; 1412236769Sobrien uint64_t q3_coff : 1; 1413321964Ssjg uint64_t q3_perr : 1; 1414236769Sobrien uint64_t q4_und : 1; 1415236769Sobrien uint64_t q4_coff : 1; 1416236769Sobrien uint64_t q4_perr : 1; 1417236769Sobrien uint64_t q5_und : 1; 1418236769Sobrien uint64_t q5_coff : 1; 1419236769Sobrien uint64_t q5_perr : 1; 1420236769Sobrien uint64_t q6_und : 1; 1421236769Sobrien uint64_t q6_coff : 1; 1422236769Sobrien uint64_t q6_perr : 1; 1423236769Sobrien uint64_t q7_und : 1; 1424236769Sobrien uint64_t q7_coff : 1; 1425236769Sobrien uint64_t q7_perr : 1; 1426236769Sobrien uint64_t pool0th : 1; 1427236769Sobrien uint64_t pool1th : 1; 1428236769Sobrien uint64_t pool2th : 1; 1429236769Sobrien uint64_t pool3th : 1; 1430236769Sobrien uint64_t pool4th : 1; 1431236769Sobrien uint64_t pool5th : 1; 1432236769Sobrien uint64_t pool6th : 1; 1433236769Sobrien uint64_t pool7th : 1; 1434236769Sobrien uint64_t free0 : 1; 1435236769Sobrien uint64_t free1 : 1; 1436236769Sobrien uint64_t free2 : 1; 1437236769Sobrien uint64_t free3 : 1; 1438236769Sobrien uint64_t free4 : 1; 1439236769Sobrien uint64_t free5 : 1; 1440236769Sobrien uint64_t free6 : 1; 1441236769Sobrien uint64_t free7 : 1; 1442236769Sobrien uint64_t reserved_44_63 : 20; 1443236769Sobrien#endif 1444236769Sobrien } cn63xx; 1445236769Sobrien struct cvmx_fpa_int_enb_cn30xx cn63xxp1; 1446236769Sobrien struct cvmx_fpa_int_enb_cn61xx cn66xx; 1447236769Sobrien struct cvmx_fpa_int_enb_cn68xx { 1448237578Sobrien#ifdef __BIG_ENDIAN_BITFIELD 1449236769Sobrien uint64_t reserved_50_63 : 14; 1450236769Sobrien uint64_t paddr_e : 1; /**< When set (1) and bit 49 of the FPA_INT_SUM 1451236769Sobrien register is asserted the FPA will assert an 1452236769Sobrien interrupt. */ 1453236769Sobrien uint64_t pool8th : 1; /**< When set (1) and bit 48 of the FPA_INT_SUM 1454236769Sobrien register is asserted the FPA will assert an 1455236769Sobrien interrupt. */ 1456236769Sobrien uint64_t q8_perr : 1; /**< When set (1) and bit 47 of the FPA_INT_SUM 1457236769Sobrien register is asserted the FPA will assert an 1458236769Sobrien interrupt. */ 1459236769Sobrien uint64_t q8_coff : 1; /**< When set (1) and bit 46 of the FPA_INT_SUM 1460236769Sobrien register is asserted the FPA will assert an 1461236769Sobrien interrupt. */ 1462236769Sobrien uint64_t q8_und : 1; /**< When set (1) and bit 45 of the FPA_INT_SUM 1463236769Sobrien register is asserted the FPA will assert an 1464236769Sobrien interrupt. */ 1465236769Sobrien uint64_t free8 : 1; /**< When set (1) and bit 44 of the FPA_INT_SUM 1466236769Sobrien register is asserted the FPA will assert an 1467236769Sobrien interrupt. */ 1468236769Sobrien uint64_t free7 : 1; /**< When set (1) and bit 43 of the FPA_INT_SUM 1469236769Sobrien register is asserted the FPA will assert an 1470236769Sobrien interrupt. */ 1471236769Sobrien uint64_t free6 : 1; /**< When set (1) and bit 42 of the FPA_INT_SUM 1472236769Sobrien register is asserted the FPA will assert an 1473236769Sobrien interrupt. */ 1474236769Sobrien uint64_t free5 : 1; /**< When set (1) and bit 41 of the FPA_INT_SUM 1475236769Sobrien register is asserted the FPA will assert an 1476236769Sobrien interrupt. */ 1477236769Sobrien uint64_t free4 : 1; /**< When set (1) and bit 40 of the FPA_INT_SUM 1478236769Sobrien register is asserted the FPA will assert an 1479236769Sobrien interrupt. */ 1480236769Sobrien uint64_t free3 : 1; /**< When set (1) and bit 39 of the FPA_INT_SUM 1481236769Sobrien register is asserted the FPA will assert an 1482236769Sobrien interrupt. */ 1483236769Sobrien uint64_t free2 : 1; /**< When set (1) and bit 38 of the FPA_INT_SUM 1484236769Sobrien register is asserted the FPA will assert an 1485237578Sobrien interrupt. */ 1486236769Sobrien uint64_t free1 : 1; /**< When set (1) and bit 37 of the FPA_INT_SUM 1487236769Sobrien register is asserted the FPA will assert an 1488236769Sobrien interrupt. */ 1489236769Sobrien uint64_t free0 : 1; /**< When set (1) and bit 36 of the FPA_INT_SUM 1490236769Sobrien register is asserted the FPA will assert an 1491236769Sobrien interrupt. */ 1492236769Sobrien uint64_t pool7th : 1; /**< When set (1) and bit 35 of the FPA_INT_SUM 1493236769Sobrien register is asserted the FPA will assert an 1494236769Sobrien interrupt. */ 1495236769Sobrien uint64_t pool6th : 1; /**< When set (1) and bit 34 of the FPA_INT_SUM 1496236769Sobrien register is asserted the FPA will assert an 1497236769Sobrien interrupt. */ 1498236769Sobrien uint64_t pool5th : 1; /**< When set (1) and bit 33 of the FPA_INT_SUM 1499236769Sobrien register is asserted the FPA will assert an 1500236769Sobrien interrupt. */ 1501236769Sobrien uint64_t pool4th : 1; /**< When set (1) and bit 32 of the FPA_INT_SUM 1502236769Sobrien register is asserted the FPA will assert an 1503236769Sobrien interrupt. */ 1504236769Sobrien uint64_t pool3th : 1; /**< When set (1) and bit 31 of the FPA_INT_SUM 1505236769Sobrien register is asserted the FPA will assert an 1506236769Sobrien interrupt. */ 1507236769Sobrien uint64_t pool2th : 1; /**< When set (1) and bit 30 of the FPA_INT_SUM 1508236769Sobrien register is asserted the FPA will assert an 1509236769Sobrien interrupt. */ 1510236769Sobrien uint64_t pool1th : 1; /**< When set (1) and bit 29 of the FPA_INT_SUM 1511236769Sobrien register is asserted the FPA will assert an 1512236769Sobrien interrupt. */ 1513236769Sobrien uint64_t pool0th : 1; /**< When set (1) and bit 28 of the FPA_INT_SUM 1514236769Sobrien register is asserted the FPA will assert an 1515236769Sobrien interrupt. */ 1516236769Sobrien uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 1517236769Sobrien register is asserted the FPA will assert an 1518236769Sobrien interrupt. */ 1519236769Sobrien uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 1520236769Sobrien register is asserted the FPA will assert an 1521236769Sobrien interrupt. */ 1522236769Sobrien uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 1523236769Sobrien register is asserted the FPA will assert an 1524236769Sobrien interrupt. */ 1525236769Sobrien uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 1526236769Sobrien register is asserted the FPA will assert an 1527236769Sobrien interrupt. */ 1528236769Sobrien uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 1529236769Sobrien register is asserted the FPA will assert an 1530236769Sobrien interrupt. */ 1531236769Sobrien uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 1532236769Sobrien register is asserted the FPA will assert an 1533236769Sobrien interrupt. */ 1534236769Sobrien uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 1535236769Sobrien register is asserted the FPA will assert an 1536236769Sobrien interrupt. */ 1537236769Sobrien uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 1538236769Sobrien register is asserted the FPA will assert an 1539236769Sobrien interrupt. */ 1540236769Sobrien uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 1541236769Sobrien register is asserted the FPA will assert an 1542236769Sobrien interrupt. */ 1543236769Sobrien uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 1544236769Sobrien register is asserted the FPA will assert an 1545236769Sobrien interrupt. */ 1546236769Sobrien uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 1547236769Sobrien register is asserted the FPA will assert an 1548236769Sobrien interrupt. */ 1549236769Sobrien uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 1550236769Sobrien register is asserted the FPA will assert an 1551236769Sobrien interrupt. */ 1552236769Sobrien uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 1553236769Sobrien register is asserted the FPA will assert an 1554236769Sobrien interrupt. */ 1555236769Sobrien uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 1556236769Sobrien register is asserted the FPA will assert an 1557236769Sobrien interrupt. */ 1558236769Sobrien uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 1559236769Sobrien register is asserted the FPA will assert an 1560236769Sobrien interrupt. */ 1561236769Sobrien uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 1562236769Sobrien register is asserted the FPA will assert an 1563236769Sobrien interrupt. */ 1564236769Sobrien uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 1565236769Sobrien register is asserted the FPA will assert an 1566236769Sobrien interrupt. */ 1567236769Sobrien uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 1568236769Sobrien register is asserted the FPA will assert an 1569236769Sobrien interrupt. */ 1570236769Sobrien uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 1571236769Sobrien register is asserted the FPA will assert an 1572236769Sobrien interrupt. */ 1573236769Sobrien uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 1574236769Sobrien register is asserted the FPA will assert an 1575236769Sobrien interrupt. */ 1576236769Sobrien uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 1577236769Sobrien register is asserted the FPA will assert an 1578236769Sobrien interrupt. */ 1579236769Sobrien uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 1580236769Sobrien register is asserted the FPA will assert an 1581236769Sobrien interrupt. */ 1582236769Sobrien uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 1583236769Sobrien register is asserted the FPA will assert an 1584236769Sobrien interrupt. */ 1585236769Sobrien uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 1586236769Sobrien register is asserted the FPA will assert an 1587236769Sobrien interrupt. */ 1588236769Sobrien uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 1589236769Sobrien register is asserted the FPA will assert an 1590236769Sobrien interrupt. */ 1591236769Sobrien uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 1592236769Sobrien register is asserted the FPA will assert an 1593236769Sobrien interrupt. */ 1594236769Sobrien uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 1595236769Sobrien register is asserted the FPA will assert an 1596236769Sobrien interrupt. */ 1597236769Sobrien uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 1598236769Sobrien register is asserted the FPA will assert an 1599236769Sobrien interrupt. */ 1600236769Sobrien#else 1601236769Sobrien uint64_t fed0_sbe : 1; 1602236769Sobrien uint64_t fed0_dbe : 1; 1603236769Sobrien uint64_t fed1_sbe : 1; 1604236769Sobrien uint64_t fed1_dbe : 1; 1605236769Sobrien uint64_t q0_und : 1; 1606236769Sobrien uint64_t q0_coff : 1; 1607236769Sobrien uint64_t q0_perr : 1; 1608236769Sobrien uint64_t q1_und : 1; 1609236769Sobrien uint64_t q1_coff : 1; 1610236769Sobrien uint64_t q1_perr : 1; 1611236769Sobrien uint64_t q2_und : 1; 1612236769Sobrien uint64_t q2_coff : 1; 1613236769Sobrien uint64_t q2_perr : 1; 1614236769Sobrien uint64_t q3_und : 1; 1615236769Sobrien uint64_t q3_coff : 1; 1616236769Sobrien uint64_t q3_perr : 1; 1617236769Sobrien uint64_t q4_und : 1; 1618236769Sobrien uint64_t q4_coff : 1; 1619236769Sobrien uint64_t q4_perr : 1; 1620236769Sobrien uint64_t q5_und : 1; 1621236769Sobrien uint64_t q5_coff : 1; 1622236769Sobrien uint64_t q5_perr : 1; 1623236769Sobrien uint64_t q6_und : 1; 1624236769Sobrien uint64_t q6_coff : 1; 1625236769Sobrien uint64_t q6_perr : 1; 1626236769Sobrien uint64_t q7_und : 1; 1627236769Sobrien uint64_t q7_coff : 1; 1628236769Sobrien uint64_t q7_perr : 1; 1629236769Sobrien uint64_t pool0th : 1; 1630236769Sobrien uint64_t pool1th : 1; 1631236769Sobrien uint64_t pool2th : 1; 1632236769Sobrien uint64_t pool3th : 1; 1633236769Sobrien uint64_t pool4th : 1; 1634236769Sobrien uint64_t pool5th : 1; 1635236769Sobrien uint64_t pool6th : 1; 1636236769Sobrien uint64_t pool7th : 1; 1637236769Sobrien uint64_t free0 : 1; 1638236769Sobrien uint64_t free1 : 1; 1639236769Sobrien uint64_t free2 : 1; 1640236769Sobrien uint64_t free3 : 1; 1641236769Sobrien uint64_t free4 : 1; 1642236769Sobrien uint64_t free5 : 1; 1643236769Sobrien uint64_t free6 : 1; 1644236769Sobrien uint64_t free7 : 1; 1645236769Sobrien uint64_t free8 : 1; 1646236769Sobrien uint64_t q8_und : 1; 1647236769Sobrien uint64_t q8_coff : 1; 1648236769Sobrien uint64_t q8_perr : 1; 1649236769Sobrien uint64_t pool8th : 1; 1650236769Sobrien uint64_t paddr_e : 1; 1651236769Sobrien uint64_t reserved_50_63 : 14; 1652236769Sobrien#endif 1653321964Ssjg } cn68xx; 1654236769Sobrien struct cvmx_fpa_int_enb_cn68xx cn68xxp1; 1655236769Sobrien struct cvmx_fpa_int_enb_cn61xx cnf71xx; 1656236769Sobrien}; 1657236769Sobrientypedef union cvmx_fpa_int_enb cvmx_fpa_int_enb_t; 1658321964Ssjg 1659236769Sobrien/** 1660321964Ssjg * cvmx_fpa_int_sum 1661236769Sobrien * 1662236769Sobrien * FPA_INT_SUM = FPA's Interrupt Summary Register 1663236769Sobrien * 1664236769Sobrien * Contains the different interrupt summary bits of the FPA. 1665236769Sobrien */ 1666236769Sobrienunion cvmx_fpa_int_sum { 1667236769Sobrien uint64_t u64; 1668236769Sobrien struct cvmx_fpa_int_sum_s { 1669236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 1670236769Sobrien uint64_t reserved_50_63 : 14; 1671236769Sobrien uint64_t paddr_e : 1; /**< Set when a pointer address does not fall in the 1672236769Sobrien address range for a pool specified by 1673236769Sobrien FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR. */ 1674236769Sobrien uint64_t pool8th : 1; /**< Set when FPA_QUE8_AVAILABLE is equal to 1675236769Sobrien FPA_POOL8_THRESHOLD[THRESH] and a pointer is 1676236769Sobrien allocated or de-allocated. */ 1677236769Sobrien uint64_t q8_perr : 1; /**< Set when a Queue8 pointer read from the stack in 1678236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1679236769Sobrien uint64_t q8_coff : 1; /**< Set when a Queue8 stack end tag is present and 1680236769Sobrien the count available is greater than than pointers 1681237578Sobrien present in the FPA. */ 1682237578Sobrien uint64_t q8_und : 1; /**< Set when a Queue8 page count available goes 1683236769Sobrien negative. */ 1684236769Sobrien uint64_t free8 : 1; /**< When a pointer for POOL8 is freed bit is set. */ 1685236769Sobrien uint64_t free7 : 1; /**< When a pointer for POOL7 is freed bit is set. */ 1686236769Sobrien uint64_t free6 : 1; /**< When a pointer for POOL6 is freed bit is set. */ 1687236769Sobrien uint64_t free5 : 1; /**< When a pointer for POOL5 is freed bit is set. */ 1688236769Sobrien uint64_t free4 : 1; /**< When a pointer for POOL4 is freed bit is set. */ 1689236769Sobrien uint64_t free3 : 1; /**< When a pointer for POOL3 is freed bit is set. */ 1690236769Sobrien uint64_t free2 : 1; /**< When a pointer for POOL2 is freed bit is set. */ 1691236769Sobrien uint64_t free1 : 1; /**< When a pointer for POOL1 is freed bit is set. */ 1692236769Sobrien uint64_t free0 : 1; /**< When a pointer for POOL0 is freed bit is set. */ 1693236769Sobrien uint64_t pool7th : 1; /**< Set when FPA_QUE7_AVAILABLE is equal to 1694236769Sobrien FPA_POOL7_THRESHOLD[THRESH] and a pointer is 1695236769Sobrien allocated or de-allocated. */ 1696236769Sobrien uint64_t pool6th : 1; /**< Set when FPA_QUE6_AVAILABLE is equal to 1697236769Sobrien FPA_POOL6_THRESHOLD[THRESH] and a pointer is 1698236769Sobrien allocated or de-allocated. */ 1699236769Sobrien uint64_t pool5th : 1; /**< Set when FPA_QUE5_AVAILABLE is equal to 1700236769Sobrien FPA_POOL5_THRESHOLD[THRESH] and a pointer is 1701236769Sobrien allocated or de-allocated. */ 1702236769Sobrien uint64_t pool4th : 1; /**< Set when FPA_QUE4_AVAILABLE is equal to 1703236769Sobrien FPA_POOL4_THRESHOLD[THRESH] and a pointer is 1704236769Sobrien allocated or de-allocated. */ 1705236769Sobrien uint64_t pool3th : 1; /**< Set when FPA_QUE3_AVAILABLE is equal to 1706236769Sobrien FPA_POOL3_THRESHOLD[THRESH] and a pointer is 1707236769Sobrien allocated or de-allocated. */ 1708236769Sobrien uint64_t pool2th : 1; /**< Set when FPA_QUE2_AVAILABLE is equal to 1709236769Sobrien FPA_POOL2_THRESHOLD[THRESH] and a pointer is 1710236769Sobrien allocated or de-allocated. */ 1711236769Sobrien uint64_t pool1th : 1; /**< Set when FPA_QUE1_AVAILABLE is equal to 1712236769Sobrien FPA_POOL1_THRESHOLD[THRESH] and a pointer is 1713236769Sobrien allocated or de-allocated. */ 1714236769Sobrien uint64_t pool0th : 1; /**< Set when FPA_QUE0_AVAILABLE is equal to 1715236769Sobrien FPA_POOL`_THRESHOLD[THRESH] and a pointer is 1716236769Sobrien allocated or de-allocated. */ 1717236769Sobrien uint64_t q7_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1718236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1719236769Sobrien uint64_t q7_coff : 1; /**< Set when a Queue0 stack end tag is present and 1720236769Sobrien the count available is greater than than pointers 1721236769Sobrien present in the FPA. */ 1722236769Sobrien uint64_t q7_und : 1; /**< Set when a Queue0 page count available goes 1723236769Sobrien negative. */ 1724236769Sobrien uint64_t q6_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1725236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1726236769Sobrien uint64_t q6_coff : 1; /**< Set when a Queue0 stack end tag is present and 1727236769Sobrien the count available is greater than than pointers 1728236769Sobrien present in the FPA. */ 1729236769Sobrien uint64_t q6_und : 1; /**< Set when a Queue0 page count available goes 1730236769Sobrien negative. */ 1731236769Sobrien uint64_t q5_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1732236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1733236769Sobrien uint64_t q5_coff : 1; /**< Set when a Queue0 stack end tag is present and 1734236769Sobrien the count available is greater than than pointers 1735236769Sobrien present in the FPA. */ 1736236769Sobrien uint64_t q5_und : 1; /**< Set when a Queue0 page count available goes 1737236769Sobrien negative. */ 1738236769Sobrien uint64_t q4_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1739236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1740236769Sobrien uint64_t q4_coff : 1; /**< Set when a Queue0 stack end tag is present and 1741236769Sobrien the count available is greater than than pointers 1742236769Sobrien present in the FPA. */ 1743236769Sobrien uint64_t q4_und : 1; /**< Set when a Queue0 page count available goes 1744236769Sobrien negative. */ 1745236769Sobrien uint64_t q3_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1746236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1747236769Sobrien uint64_t q3_coff : 1; /**< Set when a Queue0 stack end tag is present and 1748236769Sobrien the count available is greater than than pointers 1749236769Sobrien present in the FPA. */ 1750236769Sobrien uint64_t q3_und : 1; /**< Set when a Queue0 page count available goes 1751236769Sobrien negative. */ 1752236769Sobrien uint64_t q2_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1753236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1754236769Sobrien uint64_t q2_coff : 1; /**< Set when a Queue0 stack end tag is present and 1755236769Sobrien the count available is greater than than pointers 1756236769Sobrien present in the FPA. */ 1757236769Sobrien uint64_t q2_und : 1; /**< Set when a Queue0 page count available goes 1758236769Sobrien negative. */ 1759236769Sobrien uint64_t q1_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1760236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1761236769Sobrien uint64_t q1_coff : 1; /**< Set when a Queue0 stack end tag is present and 1762236769Sobrien the count available is greater than pointers 1763236769Sobrien present in the FPA. */ 1764236769Sobrien uint64_t q1_und : 1; /**< Set when a Queue0 page count available goes 1765236769Sobrien negative. */ 1766236769Sobrien uint64_t q0_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1767236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1768236769Sobrien uint64_t q0_coff : 1; /**< Set when a Queue0 stack end tag is present and 1769236769Sobrien the count available is greater than pointers 1770236769Sobrien present in the FPA. */ 1771236769Sobrien uint64_t q0_und : 1; /**< Set when a Queue0 page count available goes 1772236769Sobrien negative. */ 1773236769Sobrien uint64_t fed1_dbe : 1; /**< Set when a Double Bit Error is detected in FPF1. */ 1774236769Sobrien uint64_t fed1_sbe : 1; /**< Set when a Single Bit Error is detected in FPF1. */ 1775236769Sobrien uint64_t fed0_dbe : 1; /**< Set when a Double Bit Error is detected in FPF0. */ 1776236769Sobrien uint64_t fed0_sbe : 1; /**< Set when a Single Bit Error is detected in FPF0. */ 1777236769Sobrien#else 1778236769Sobrien uint64_t fed0_sbe : 1; 1779236769Sobrien uint64_t fed0_dbe : 1; 1780236769Sobrien uint64_t fed1_sbe : 1; 1781236769Sobrien uint64_t fed1_dbe : 1; 1782236769Sobrien uint64_t q0_und : 1; 1783236769Sobrien uint64_t q0_coff : 1; 1784236769Sobrien uint64_t q0_perr : 1; 1785236769Sobrien uint64_t q1_und : 1; 1786236769Sobrien uint64_t q1_coff : 1; 1787236769Sobrien uint64_t q1_perr : 1; 1788236769Sobrien uint64_t q2_und : 1; 1789236769Sobrien uint64_t q2_coff : 1; 1790236769Sobrien uint64_t q2_perr : 1; 1791236769Sobrien uint64_t q3_und : 1; 1792236769Sobrien uint64_t q3_coff : 1; 1793236769Sobrien uint64_t q3_perr : 1; 1794236769Sobrien uint64_t q4_und : 1; 1795236769Sobrien uint64_t q4_coff : 1; 1796236769Sobrien uint64_t q4_perr : 1; 1797236769Sobrien uint64_t q5_und : 1; 1798236769Sobrien uint64_t q5_coff : 1; 1799236769Sobrien uint64_t q5_perr : 1; 1800236769Sobrien uint64_t q6_und : 1; 1801236769Sobrien uint64_t q6_coff : 1; 1802236769Sobrien uint64_t q6_perr : 1; 1803236769Sobrien uint64_t q7_und : 1; 1804236769Sobrien uint64_t q7_coff : 1; 1805236769Sobrien uint64_t q7_perr : 1; 1806236769Sobrien uint64_t pool0th : 1; 1807236769Sobrien uint64_t pool1th : 1; 1808236769Sobrien uint64_t pool2th : 1; 1809236769Sobrien uint64_t pool3th : 1; 1810236769Sobrien uint64_t pool4th : 1; 1811236769Sobrien uint64_t pool5th : 1; 1812236769Sobrien uint64_t pool6th : 1; 1813236769Sobrien uint64_t pool7th : 1; 1814236769Sobrien uint64_t free0 : 1; 1815236769Sobrien uint64_t free1 : 1; 1816236769Sobrien uint64_t free2 : 1; 1817236769Sobrien uint64_t free3 : 1; 1818236769Sobrien uint64_t free4 : 1; 1819236769Sobrien uint64_t free5 : 1; 1820236769Sobrien uint64_t free6 : 1; 1821236769Sobrien uint64_t free7 : 1; 1822237578Sobrien uint64_t free8 : 1; 1823237578Sobrien uint64_t q8_und : 1; 1824236769Sobrien uint64_t q8_coff : 1; 1825236769Sobrien uint64_t q8_perr : 1; 1826236769Sobrien uint64_t pool8th : 1; 1827236769Sobrien uint64_t paddr_e : 1; 1828236769Sobrien uint64_t reserved_50_63 : 14; 1829236769Sobrien#endif 1830236769Sobrien } s; 1831236769Sobrien struct cvmx_fpa_int_sum_cn30xx { 1832236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 1833321964Ssjg uint64_t reserved_28_63 : 36; 1834236769Sobrien uint64_t q7_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1835236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1836236769Sobrien uint64_t q7_coff : 1; /**< Set when a Queue0 stack end tag is present and 1837236769Sobrien the count available is greater than than pointers 1838236769Sobrien present in the FPA. */ 1839236769Sobrien uint64_t q7_und : 1; /**< Set when a Queue0 page count available goes 1840321964Ssjg negative. */ 1841236769Sobrien uint64_t q6_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1842236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1843236769Sobrien uint64_t q6_coff : 1; /**< Set when a Queue0 stack end tag is present and 1844236769Sobrien the count available is greater than than pointers 1845236769Sobrien present in the FPA. */ 1846236769Sobrien uint64_t q6_und : 1; /**< Set when a Queue0 page count available goes 1847236769Sobrien negative. */ 1848236769Sobrien uint64_t q5_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1849236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1850236769Sobrien uint64_t q5_coff : 1; /**< Set when a Queue0 stack end tag is present and 1851236769Sobrien the count available is greater than than pointers 1852236769Sobrien present in the FPA. */ 1853236769Sobrien uint64_t q5_und : 1; /**< Set when a Queue0 page count available goes 1854236769Sobrien negative. */ 1855236769Sobrien uint64_t q4_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1856236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1857236769Sobrien uint64_t q4_coff : 1; /**< Set when a Queue0 stack end tag is present and 1858236769Sobrien the count available is greater than than pointers 1859236769Sobrien present in the FPA. */ 1860236769Sobrien uint64_t q4_und : 1; /**< Set when a Queue0 page count available goes 1861236769Sobrien negative. */ 1862236769Sobrien uint64_t q3_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1863236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1864236769Sobrien uint64_t q3_coff : 1; /**< Set when a Queue0 stack end tag is present and 1865236769Sobrien the count available is greater than than pointers 1866237578Sobrien present in the FPA. */ 1867236769Sobrien uint64_t q3_und : 1; /**< Set when a Queue0 page count available goes 1868236769Sobrien negative. */ 1869236769Sobrien uint64_t q2_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1870236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1871236769Sobrien uint64_t q2_coff : 1; /**< Set when a Queue0 stack end tag is present and 1872236769Sobrien the count available is greater than than pointers 1873236769Sobrien present in the FPA. */ 1874236769Sobrien uint64_t q2_und : 1; /**< Set when a Queue0 page count available goes 1875236769Sobrien negative. */ 1876236769Sobrien uint64_t q1_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1877236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1878236769Sobrien uint64_t q1_coff : 1; /**< Set when a Queue0 stack end tag is present and 1879236769Sobrien the count available is greater than pointers 1880236769Sobrien present in the FPA. */ 1881236769Sobrien uint64_t q1_und : 1; /**< Set when a Queue0 page count available goes 1882236769Sobrien negative. */ 1883236769Sobrien uint64_t q0_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1884236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1885236769Sobrien uint64_t q0_coff : 1; /**< Set when a Queue0 stack end tag is present and 1886236769Sobrien the count available is greater than pointers 1887236769Sobrien present in the FPA. */ 1888236769Sobrien uint64_t q0_und : 1; /**< Set when a Queue0 page count available goes 1889236769Sobrien negative. */ 1890236769Sobrien uint64_t fed1_dbe : 1; /**< Set when a Double Bit Error is detected in FPF1. */ 1891236769Sobrien uint64_t fed1_sbe : 1; /**< Set when a Single Bit Error is detected in FPF1. */ 1892236769Sobrien uint64_t fed0_dbe : 1; /**< Set when a Double Bit Error is detected in FPF0. */ 1893236769Sobrien uint64_t fed0_sbe : 1; /**< Set when a Single Bit Error is detected in FPF0. */ 1894236769Sobrien#else 1895236769Sobrien uint64_t fed0_sbe : 1; 1896236769Sobrien uint64_t fed0_dbe : 1; 1897236769Sobrien uint64_t fed1_sbe : 1; 1898236769Sobrien uint64_t fed1_dbe : 1; 1899236769Sobrien uint64_t q0_und : 1; 1900236769Sobrien uint64_t q0_coff : 1; 1901236769Sobrien uint64_t q0_perr : 1; 1902236769Sobrien uint64_t q1_und : 1; 1903236769Sobrien uint64_t q1_coff : 1; 1904236769Sobrien uint64_t q1_perr : 1; 1905236769Sobrien uint64_t q2_und : 1; 1906236769Sobrien uint64_t q2_coff : 1; 1907236769Sobrien uint64_t q2_perr : 1; 1908236769Sobrien uint64_t q3_und : 1; 1909236769Sobrien uint64_t q3_coff : 1; 1910236769Sobrien uint64_t q3_perr : 1; 1911236769Sobrien uint64_t q4_und : 1; 1912236769Sobrien uint64_t q4_coff : 1; 1913236769Sobrien uint64_t q4_perr : 1; 1914236769Sobrien uint64_t q5_und : 1; 1915236769Sobrien uint64_t q5_coff : 1; 1916236769Sobrien uint64_t q5_perr : 1; 1917236769Sobrien uint64_t q6_und : 1; 1918236769Sobrien uint64_t q6_coff : 1; 1919236769Sobrien uint64_t q6_perr : 1; 1920236769Sobrien uint64_t q7_und : 1; 1921236769Sobrien uint64_t q7_coff : 1; 1922236769Sobrien uint64_t q7_perr : 1; 1923236769Sobrien uint64_t reserved_28_63 : 36; 1924236769Sobrien#endif 1925236769Sobrien } cn30xx; 1926236769Sobrien struct cvmx_fpa_int_sum_cn30xx cn31xx; 1927236769Sobrien struct cvmx_fpa_int_sum_cn30xx cn38xx; 1928236769Sobrien struct cvmx_fpa_int_sum_cn30xx cn38xxp2; 1929236769Sobrien struct cvmx_fpa_int_sum_cn30xx cn50xx; 1930236769Sobrien struct cvmx_fpa_int_sum_cn30xx cn52xx; 1931236769Sobrien struct cvmx_fpa_int_sum_cn30xx cn52xxp1; 1932236769Sobrien struct cvmx_fpa_int_sum_cn30xx cn56xx; 1933236769Sobrien struct cvmx_fpa_int_sum_cn30xx cn56xxp1; 1934236769Sobrien struct cvmx_fpa_int_sum_cn30xx cn58xx; 1935236769Sobrien struct cvmx_fpa_int_sum_cn30xx cn58xxp1; 1936236769Sobrien struct cvmx_fpa_int_sum_cn61xx { 1937236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 1938236769Sobrien uint64_t reserved_50_63 : 14; 1939236769Sobrien uint64_t paddr_e : 1; /**< Set when a pointer address does not fall in the 1940236769Sobrien address range for a pool specified by 1941237578Sobrien FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR. */ 1942236769Sobrien uint64_t reserved_44_48 : 5; 1943237578Sobrien uint64_t free7 : 1; /**< When a pointer for POOL7 is freed bit is set. */ 1944236769Sobrien uint64_t free6 : 1; /**< When a pointer for POOL6 is freed bit is set. */ 1945236769Sobrien uint64_t free5 : 1; /**< When a pointer for POOL5 is freed bit is set. */ 1946236769Sobrien uint64_t free4 : 1; /**< When a pointer for POOL4 is freed bit is set. */ 1947236769Sobrien uint64_t free3 : 1; /**< When a pointer for POOL3 is freed bit is set. */ 1948236769Sobrien uint64_t free2 : 1; /**< When a pointer for POOL2 is freed bit is set. */ 1949236769Sobrien uint64_t free1 : 1; /**< When a pointer for POOL1 is freed bit is set. */ 1950236769Sobrien uint64_t free0 : 1; /**< When a pointer for POOL0 is freed bit is set. */ 1951236769Sobrien uint64_t pool7th : 1; /**< Set when FPA_QUE7_AVAILABLE is equal to 1952236769Sobrien FPA_POOL7_THRESHOLD[THRESH] and a pointer is 1953321964Ssjg allocated or de-allocated. */ 1954236769Sobrien uint64_t pool6th : 1; /**< Set when FPA_QUE6_AVAILABLE is equal to 1955236769Sobrien FPA_POOL6_THRESHOLD[THRESH] and a pointer is 1956236769Sobrien allocated or de-allocated. */ 1957236769Sobrien uint64_t pool5th : 1; /**< Set when FPA_QUE5_AVAILABLE is equal to 1958236769Sobrien FPA_POOL5_THRESHOLD[THRESH] and a pointer is 1959236769Sobrien allocated or de-allocated. */ 1960236769Sobrien uint64_t pool4th : 1; /**< Set when FPA_QUE4_AVAILABLE is equal to 1961236769Sobrien FPA_POOL4_THRESHOLD[THRESH] and a pointer is 1962236769Sobrien allocated or de-allocated. */ 1963236769Sobrien uint64_t pool3th : 1; /**< Set when FPA_QUE3_AVAILABLE is equal to 1964236769Sobrien FPA_POOL3_THRESHOLD[THRESH] and a pointer is 1965236769Sobrien allocated or de-allocated. */ 1966236769Sobrien uint64_t pool2th : 1; /**< Set when FPA_QUE2_AVAILABLE is equal to 1967236769Sobrien FPA_POOL2_THRESHOLD[THRESH] and a pointer is 1968236769Sobrien allocated or de-allocated. */ 1969236769Sobrien uint64_t pool1th : 1; /**< Set when FPA_QUE1_AVAILABLE is equal to 1970236769Sobrien FPA_POOL1_THRESHOLD[THRESH] and a pointer is 1971236769Sobrien allocated or de-allocated. */ 1972236769Sobrien uint64_t pool0th : 1; /**< Set when FPA_QUE0_AVAILABLE is equal to 1973236769Sobrien FPA_POOL`_THRESHOLD[THRESH] and a pointer is 1974236769Sobrien allocated or de-allocated. */ 1975236769Sobrien uint64_t q7_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1976236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1977236769Sobrien uint64_t q7_coff : 1; /**< Set when a Queue0 stack end tag is present and 1978236769Sobrien the count available is greater than than pointers 1979236769Sobrien present in the FPA. */ 1980236769Sobrien uint64_t q7_und : 1; /**< Set when a Queue0 page count available goes 1981236769Sobrien negative. */ 1982236769Sobrien uint64_t q6_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1983236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1984236769Sobrien uint64_t q6_coff : 1; /**< Set when a Queue0 stack end tag is present and 1985236769Sobrien the count available is greater than than pointers 1986236769Sobrien present in the FPA. */ 1987236769Sobrien uint64_t q6_und : 1; /**< Set when a Queue0 page count available goes 1988236769Sobrien negative. */ 1989236769Sobrien uint64_t q5_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1990236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1991236769Sobrien uint64_t q5_coff : 1; /**< Set when a Queue0 stack end tag is present and 1992236769Sobrien the count available is greater than than pointers 1993236769Sobrien present in the FPA. */ 1994236769Sobrien uint64_t q5_und : 1; /**< Set when a Queue0 page count available goes 1995236769Sobrien negative. */ 1996236769Sobrien uint64_t q4_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1997236769Sobrien the L2C does not have the FPA owner ship bit set. */ 1998236769Sobrien uint64_t q4_coff : 1; /**< Set when a Queue0 stack end tag is present and 1999236769Sobrien the count available is greater than than pointers 2000236769Sobrien present in the FPA. */ 2001236769Sobrien uint64_t q4_und : 1; /**< Set when a Queue0 page count available goes 2002236769Sobrien negative. */ 2003236769Sobrien uint64_t q3_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2004236769Sobrien the L2C does not have the FPA owner ship bit set. */ 2005236769Sobrien uint64_t q3_coff : 1; /**< Set when a Queue0 stack end tag is present and 2006236769Sobrien the count available is greater than than pointers 2007236769Sobrien present in the FPA. */ 2008236769Sobrien uint64_t q3_und : 1; /**< Set when a Queue0 page count available goes 2009236769Sobrien negative. */ 2010236769Sobrien uint64_t q2_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2011236769Sobrien the L2C does not have the FPA owner ship bit set. */ 2012236769Sobrien uint64_t q2_coff : 1; /**< Set when a Queue0 stack end tag is present and 2013236769Sobrien the count available is greater than than pointers 2014236769Sobrien present in the FPA. */ 2015236769Sobrien uint64_t q2_und : 1; /**< Set when a Queue0 page count available goes 2016236769Sobrien negative. */ 2017236769Sobrien uint64_t q1_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2018236769Sobrien the L2C does not have the FPA owner ship bit set. */ 2019236769Sobrien uint64_t q1_coff : 1; /**< Set when a Queue0 stack end tag is present and 2020236769Sobrien the count available is greater than pointers 2021236769Sobrien present in the FPA. */ 2022236769Sobrien uint64_t q1_und : 1; /**< Set when a Queue0 page count available goes 2023236769Sobrien negative. */ 2024236769Sobrien uint64_t q0_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2025236769Sobrien the L2C does not have the FPA owner ship bit set. */ 2026236769Sobrien uint64_t q0_coff : 1; /**< Set when a Queue0 stack end tag is present and 2027236769Sobrien the count available is greater than pointers 2028236769Sobrien present in the FPA. */ 2029236769Sobrien uint64_t q0_und : 1; /**< Set when a Queue0 page count available goes 2030236769Sobrien negative. */ 2031236769Sobrien uint64_t fed1_dbe : 1; /**< Set when a Double Bit Error is detected in FPF1. */ 2032236769Sobrien uint64_t fed1_sbe : 1; /**< Set when a Single Bit Error is detected in FPF1. */ 2033236769Sobrien uint64_t fed0_dbe : 1; /**< Set when a Double Bit Error is detected in FPF0. */ 2034236769Sobrien uint64_t fed0_sbe : 1; /**< Set when a Single Bit Error is detected in FPF0. */ 2035236769Sobrien#else 2036236769Sobrien uint64_t fed0_sbe : 1; 2037236769Sobrien uint64_t fed0_dbe : 1; 2038236769Sobrien uint64_t fed1_sbe : 1; 2039236769Sobrien uint64_t fed1_dbe : 1; 2040236769Sobrien uint64_t q0_und : 1; 2041236769Sobrien uint64_t q0_coff : 1; 2042236769Sobrien uint64_t q0_perr : 1; 2043236769Sobrien uint64_t q1_und : 1; 2044236769Sobrien uint64_t q1_coff : 1; 2045236769Sobrien uint64_t q1_perr : 1; 2046236769Sobrien uint64_t q2_und : 1; 2047236769Sobrien uint64_t q2_coff : 1; 2048236769Sobrien uint64_t q2_perr : 1; 2049236769Sobrien uint64_t q3_und : 1; 2050236769Sobrien uint64_t q3_coff : 1; 2051236769Sobrien uint64_t q3_perr : 1; 2052236769Sobrien uint64_t q4_und : 1; 2053236769Sobrien uint64_t q4_coff : 1; 2054236769Sobrien uint64_t q4_perr : 1; 2055236769Sobrien uint64_t q5_und : 1; 2056236769Sobrien uint64_t q5_coff : 1; 2057236769Sobrien uint64_t q5_perr : 1; 2058236769Sobrien uint64_t q6_und : 1; 2059236769Sobrien uint64_t q6_coff : 1; 2060236769Sobrien uint64_t q6_perr : 1; 2061236769Sobrien uint64_t q7_und : 1; 2062236769Sobrien uint64_t q7_coff : 1; 2063236769Sobrien uint64_t q7_perr : 1; 2064236769Sobrien uint64_t pool0th : 1; 2065236769Sobrien uint64_t pool1th : 1; 2066236769Sobrien uint64_t pool2th : 1; 2067236769Sobrien uint64_t pool3th : 1; 2068236769Sobrien uint64_t pool4th : 1; 2069236769Sobrien uint64_t pool5th : 1; 2070236769Sobrien uint64_t pool6th : 1; 2071236769Sobrien uint64_t pool7th : 1; 2072236769Sobrien uint64_t free0 : 1; 2073236769Sobrien uint64_t free1 : 1; 2074236769Sobrien uint64_t free2 : 1; 2075236769Sobrien uint64_t free3 : 1; 2076236769Sobrien uint64_t free4 : 1; 2077236769Sobrien uint64_t free5 : 1; 2078236769Sobrien uint64_t free6 : 1; 2079236769Sobrien uint64_t free7 : 1; 2080236769Sobrien uint64_t reserved_44_48 : 5; 2081236769Sobrien uint64_t paddr_e : 1; 2082236769Sobrien uint64_t reserved_50_63 : 14; 2083236769Sobrien#endif 2084236769Sobrien } cn61xx; 2085236769Sobrien struct cvmx_fpa_int_sum_cn63xx { 2086236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 2087236769Sobrien uint64_t reserved_44_63 : 20; 2088236769Sobrien uint64_t free7 : 1; /**< When a pointer for POOL7 is freed bit is set. */ 2089236769Sobrien uint64_t free6 : 1; /**< When a pointer for POOL6 is freed bit is set. */ 2090236769Sobrien uint64_t free5 : 1; /**< When a pointer for POOL5 is freed bit is set. */ 2091236769Sobrien uint64_t free4 : 1; /**< When a pointer for POOL4 is freed bit is set. */ 2092236769Sobrien uint64_t free3 : 1; /**< When a pointer for POOL3 is freed bit is set. */ 2093236769Sobrien uint64_t free2 : 1; /**< When a pointer for POOL2 is freed bit is set. */ 2094236769Sobrien uint64_t free1 : 1; /**< When a pointer for POOL1 is freed bit is set. */ 2095236769Sobrien uint64_t free0 : 1; /**< When a pointer for POOL0 is freed bit is set. */ 2096236769Sobrien uint64_t pool7th : 1; /**< Set when FPA_QUE7_AVAILABLE is equal to 2097236769Sobrien FPA_POOL7_THRESHOLD[THRESH] and a pointer is 2098236769Sobrien allocated or de-allocated. */ 2099236769Sobrien uint64_t pool6th : 1; /**< Set when FPA_QUE6_AVAILABLE is equal to 2100236769Sobrien FPA_POOL6_THRESHOLD[THRESH] and a pointer is 2101236769Sobrien allocated or de-allocated. */ 2102236769Sobrien uint64_t pool5th : 1; /**< Set when FPA_QUE5_AVAILABLE is equal to 2103236769Sobrien FPA_POOL5_THRESHOLD[THRESH] and a pointer is 2104236769Sobrien allocated or de-allocated. */ 2105236769Sobrien uint64_t pool4th : 1; /**< Set when FPA_QUE4_AVAILABLE is equal to 2106236769Sobrien FPA_POOL4_THRESHOLD[THRESH] and a pointer is 2107236769Sobrien allocated or de-allocated. */ 2108236769Sobrien uint64_t pool3th : 1; /**< Set when FPA_QUE3_AVAILABLE is equal to 2109236769Sobrien FPA_POOL3_THRESHOLD[THRESH] and a pointer is 2110236769Sobrien allocated or de-allocated. */ 2111236769Sobrien uint64_t pool2th : 1; /**< Set when FPA_QUE2_AVAILABLE is equal to 2112236769Sobrien FPA_POOL2_THRESHOLD[THRESH] and a pointer is 2113236769Sobrien allocated or de-allocated. */ 2114236769Sobrien uint64_t pool1th : 1; /**< Set when FPA_QUE1_AVAILABLE is equal to 2115236769Sobrien FPA_POOL1_THRESHOLD[THRESH] and a pointer is 2116236769Sobrien allocated or de-allocated. */ 2117236769Sobrien uint64_t pool0th : 1; /**< Set when FPA_QUE0_AVAILABLE is equal to 2118236769Sobrien FPA_POOL`_THRESHOLD[THRESH] and a pointer is 2119236769Sobrien allocated or de-allocated. */ 2120236769Sobrien uint64_t q7_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2121236769Sobrien the L2C does not have the FPA owner ship bit set. */ 2122236769Sobrien uint64_t q7_coff : 1; /**< Set when a Queue0 stack end tag is present and 2123236769Sobrien the count available is greater than than pointers 2124236769Sobrien present in the FPA. */ 2125236769Sobrien uint64_t q7_und : 1; /**< Set when a Queue0 page count available goes 2126236769Sobrien negative. */ 2127236769Sobrien uint64_t q6_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2128236769Sobrien the L2C does not have the FPA owner ship bit set. */ 2129236769Sobrien uint64_t q6_coff : 1; /**< Set when a Queue0 stack end tag is present and 2130236769Sobrien the count available is greater than than pointers 2131236769Sobrien present in the FPA. */ 2132236769Sobrien uint64_t q6_und : 1; /**< Set when a Queue0 page count available goes 2133236769Sobrien negative. */ 2134236769Sobrien uint64_t q5_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2135236769Sobrien the L2C does not have the FPA owner ship bit set. */ 2136236769Sobrien uint64_t q5_coff : 1; /**< Set when a Queue0 stack end tag is present and 2137236769Sobrien the count available is greater than than pointers 2138236769Sobrien present in the FPA. */ 2139236769Sobrien uint64_t q5_und : 1; /**< Set when a Queue0 page count available goes 2140236769Sobrien negative. */ 2141236769Sobrien uint64_t q4_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2142321964Ssjg the L2C does not have the FPA owner ship bit set. */ 2143321964Ssjg uint64_t q4_coff : 1; /**< Set when a Queue0 stack end tag is present and 2144321964Ssjg the count available is greater than than pointers 2145321964Ssjg present in the FPA. */ 2146321964Ssjg uint64_t q4_und : 1; /**< Set when a Queue0 page count available goes 2147321964Ssjg negative. */ 2148321964Ssjg uint64_t q3_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2149321964Ssjg the L2C does not have the FPA owner ship bit set. */ 2150321964Ssjg uint64_t q3_coff : 1; /**< Set when a Queue0 stack end tag is present and 2151321964Ssjg the count available is greater than than pointers 2152321964Ssjg present in the FPA. */ 2153321964Ssjg uint64_t q3_und : 1; /**< Set when a Queue0 page count available goes 2154321964Ssjg negative. */ 2155321964Ssjg uint64_t q2_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2156321964Ssjg the L2C does not have the FPA owner ship bit set. */ 2157321964Ssjg uint64_t q2_coff : 1; /**< Set when a Queue0 stack end tag is present and 2158321964Ssjg the count available is greater than than pointers 2159321964Ssjg present in the FPA. */ 2160321964Ssjg uint64_t q2_und : 1; /**< Set when a Queue0 page count available goes 2161321964Ssjg negative. */ 2162321964Ssjg uint64_t q1_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2163321964Ssjg the L2C does not have the FPA owner ship bit set. */ 2164236769Sobrien uint64_t q1_coff : 1; /**< Set when a Queue0 stack end tag is present and 2165321964Ssjg the count available is greater than pointers 2166321964Ssjg present in the FPA. */ 2167321964Ssjg uint64_t q1_und : 1; /**< Set when a Queue0 page count available goes 2168321964Ssjg negative. */ 2169321964Ssjg uint64_t q0_perr : 1; /**< Set when a Queue0 pointer read from the stack in 2170321964Ssjg the L2C does not have the FPA owner ship bit set. */ 2171321964Ssjg uint64_t q0_coff : 1; /**< Set when a Queue0 stack end tag is present and 2172321964Ssjg the count available is greater than pointers 2173321964Ssjg present in the FPA. */ 2174321964Ssjg uint64_t q0_und : 1; /**< Set when a Queue0 page count available goes 2175321964Ssjg negative. */ 2176321964Ssjg uint64_t fed1_dbe : 1; /**< Set when a Double Bit Error is detected in FPF1. */ 2177321964Ssjg uint64_t fed1_sbe : 1; /**< Set when a Single Bit Error is detected in FPF1. */ 2178321964Ssjg uint64_t fed0_dbe : 1; /**< Set when a Double Bit Error is detected in FPF0. */ 2179321964Ssjg uint64_t fed0_sbe : 1; /**< Set when a Single Bit Error is detected in FPF0. */ 2180321964Ssjg#else 2181321964Ssjg uint64_t fed0_sbe : 1; 2182321964Ssjg uint64_t fed0_dbe : 1; 2183321964Ssjg uint64_t fed1_sbe : 1; 2184321964Ssjg uint64_t fed1_dbe : 1; 2185321964Ssjg uint64_t q0_und : 1; 2186321964Ssjg uint64_t q0_coff : 1; 2187321964Ssjg uint64_t q0_perr : 1; 2188236769Sobrien uint64_t q1_und : 1; 2189236769Sobrien uint64_t q1_coff : 1; 2190236769Sobrien uint64_t q1_perr : 1; 2191236769Sobrien uint64_t q2_und : 1; 2192236769Sobrien uint64_t q2_coff : 1; 2193236769Sobrien uint64_t q2_perr : 1; 2194236769Sobrien uint64_t q3_und : 1; 2195236769Sobrien uint64_t q3_coff : 1; 2196236769Sobrien uint64_t q3_perr : 1; 2197236769Sobrien uint64_t q4_und : 1; 2198236769Sobrien uint64_t q4_coff : 1; 2199236769Sobrien uint64_t q4_perr : 1; 2200236769Sobrien uint64_t q5_und : 1; 2201236769Sobrien uint64_t q5_coff : 1; 2202236769Sobrien uint64_t q5_perr : 1; 2203236769Sobrien uint64_t q6_und : 1; 2204236769Sobrien uint64_t q6_coff : 1; 2205236769Sobrien uint64_t q6_perr : 1; 2206236769Sobrien uint64_t q7_und : 1; 2207236769Sobrien uint64_t q7_coff : 1; 2208236769Sobrien uint64_t q7_perr : 1; 2209236769Sobrien uint64_t pool0th : 1; 2210236769Sobrien uint64_t pool1th : 1; 2211237578Sobrien uint64_t pool2th : 1; 2212321964Ssjg uint64_t pool3th : 1; 2213236769Sobrien uint64_t pool4th : 1; 2214236769Sobrien uint64_t pool5th : 1; 2215236769Sobrien uint64_t pool6th : 1; 2216236769Sobrien uint64_t pool7th : 1; 2217236769Sobrien uint64_t free0 : 1; 2218236769Sobrien uint64_t free1 : 1; 2219321964Ssjg uint64_t free2 : 1; 2220236769Sobrien uint64_t free3 : 1; 2221236769Sobrien uint64_t free4 : 1; 2222236769Sobrien uint64_t free5 : 1; 2223236769Sobrien uint64_t free6 : 1; 2224236769Sobrien uint64_t free7 : 1; 2225236769Sobrien uint64_t reserved_44_63 : 20; 2226236769Sobrien#endif 2227236769Sobrien } cn63xx; 2228236769Sobrien struct cvmx_fpa_int_sum_cn30xx cn63xxp1; 2229236769Sobrien struct cvmx_fpa_int_sum_cn61xx cn66xx; 2230236769Sobrien struct cvmx_fpa_int_sum_s cn68xx; 2231236769Sobrien struct cvmx_fpa_int_sum_s cn68xxp1; 2232236769Sobrien struct cvmx_fpa_int_sum_cn61xx cnf71xx; 2233236769Sobrien}; 2234236769Sobrientypedef union cvmx_fpa_int_sum cvmx_fpa_int_sum_t; 2235236769Sobrien 2236236769Sobrien/** 2237236769Sobrien * cvmx_fpa_packet_threshold 2238236769Sobrien * 2239236769Sobrien * FPA_PACKET_THRESHOLD = FPA's Packet Threshold 2240236769Sobrien * 2241321964Ssjg * When the value of FPA_QUE0_AVAILABLE[QUE_SIZ] is Less than the value of this register a low pool count signal is sent to the 2242236769Sobrien * PCIe packet instruction engine (to make it stop reading instructions) and to the Packet-Arbiter informing it to not give grants 2243236769Sobrien * to packets MAC with the exception of the PCIe MAC. 2244236769Sobrien */ 2245236769Sobrienunion cvmx_fpa_packet_threshold { 2246236769Sobrien uint64_t u64; 2247236769Sobrien struct cvmx_fpa_packet_threshold_s { 2248321964Ssjg#ifdef __BIG_ENDIAN_BITFIELD 2249236769Sobrien uint64_t reserved_32_63 : 32; 2250321964Ssjg uint64_t thresh : 32; /**< Packet Threshold. */ 2251236769Sobrien#else 2252236769Sobrien uint64_t thresh : 32; 2253236769Sobrien uint64_t reserved_32_63 : 32; 2254236769Sobrien#endif 2255236769Sobrien } s; 2256236769Sobrien struct cvmx_fpa_packet_threshold_s cn61xx; 2257236769Sobrien struct cvmx_fpa_packet_threshold_s cn63xx; 2258236769Sobrien struct cvmx_fpa_packet_threshold_s cn66xx; 2259236769Sobrien struct cvmx_fpa_packet_threshold_s cn68xx; 2260321964Ssjg struct cvmx_fpa_packet_threshold_s cn68xxp1; 2261321964Ssjg struct cvmx_fpa_packet_threshold_s cnf71xx; 2262236769Sobrien}; 2263292068Ssjgtypedef union cvmx_fpa_packet_threshold cvmx_fpa_packet_threshold_t; 2264236769Sobrien 2265236769Sobrien/** 2266236769Sobrien * cvmx_fpa_pool#_end_addr 2267236769Sobrien * 2268236769Sobrien * Space here reserved 2269236769Sobrien * 2270236769Sobrien * FPA_POOLX_END_ADDR = FPA's Pool-X Ending Addres 2271236769Sobrien * 2272236769Sobrien * Pointers sent to this pool must be equal to or less than this address. 2273236769Sobrien */ 2274236769Sobrienunion cvmx_fpa_poolx_end_addr { 2275236769Sobrien uint64_t u64; 2276236769Sobrien struct cvmx_fpa_poolx_end_addr_s { 2277236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 2278236769Sobrien uint64_t reserved_33_63 : 31; 2279236769Sobrien uint64_t addr : 33; /**< Address. */ 2280236769Sobrien#else 2281236769Sobrien uint64_t addr : 33; 2282236769Sobrien uint64_t reserved_33_63 : 31; 2283236769Sobrien#endif 2284236769Sobrien } s; 2285236769Sobrien struct cvmx_fpa_poolx_end_addr_s cn61xx; 2286236769Sobrien struct cvmx_fpa_poolx_end_addr_s cn66xx; 2287236769Sobrien struct cvmx_fpa_poolx_end_addr_s cn68xx; 2288236769Sobrien struct cvmx_fpa_poolx_end_addr_s cn68xxp1; 2289236769Sobrien struct cvmx_fpa_poolx_end_addr_s cnf71xx; 2290236769Sobrien}; 2291236769Sobrientypedef union cvmx_fpa_poolx_end_addr cvmx_fpa_poolx_end_addr_t; 2292236769Sobrien 2293236769Sobrien/** 2294236769Sobrien * cvmx_fpa_pool#_start_addr 2295236769Sobrien * 2296236769Sobrien * FPA_POOLX_START_ADDR = FPA's Pool-X Starting Addres 2297236769Sobrien * 2298236769Sobrien * Pointers sent to this pool must be equal to or greater than this address. 2299236769Sobrien */ 2300236769Sobrienunion cvmx_fpa_poolx_start_addr { 2301236769Sobrien uint64_t u64; 2302236769Sobrien struct cvmx_fpa_poolx_start_addr_s { 2303236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 2304236769Sobrien uint64_t reserved_33_63 : 31; 2305236769Sobrien uint64_t addr : 33; /**< Address. */ 2306236769Sobrien#else 2307236769Sobrien uint64_t addr : 33; 2308236769Sobrien uint64_t reserved_33_63 : 31; 2309236769Sobrien#endif 2310236769Sobrien } s; 2311236769Sobrien struct cvmx_fpa_poolx_start_addr_s cn61xx; 2312236769Sobrien struct cvmx_fpa_poolx_start_addr_s cn66xx; 2313236769Sobrien struct cvmx_fpa_poolx_start_addr_s cn68xx; 2314236769Sobrien struct cvmx_fpa_poolx_start_addr_s cn68xxp1; 2315236769Sobrien struct cvmx_fpa_poolx_start_addr_s cnf71xx; 2316292068Ssjg}; 2317236769Sobrientypedef union cvmx_fpa_poolx_start_addr cvmx_fpa_poolx_start_addr_t; 2318236769Sobrien 2319236769Sobrien/** 2320236769Sobrien * cvmx_fpa_pool#_threshold 2321236769Sobrien * 2322236769Sobrien * FPA_POOLX_THRESHOLD = FPA's Pool 0-7 Threshold 2323236769Sobrien * 2324236769Sobrien * When the value of FPA_QUEX_AVAILABLE is equal to FPA_POOLX_THRESHOLD[THRESH] when a pointer is allocated 2325236769Sobrien * or deallocated, set interrupt FPA_INT_SUM[POOLXTH]. 2326236769Sobrien */ 2327236769Sobrienunion cvmx_fpa_poolx_threshold { 2328236769Sobrien uint64_t u64; 2329236769Sobrien struct cvmx_fpa_poolx_threshold_s { 2330236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 2331236769Sobrien uint64_t reserved_32_63 : 32; 2332292068Ssjg uint64_t thresh : 32; /**< The Threshold. */ 2333236769Sobrien#else 2334236769Sobrien uint64_t thresh : 32; 2335236769Sobrien uint64_t reserved_32_63 : 32; 2336236769Sobrien#endif 2337236769Sobrien } s; 2338236769Sobrien struct cvmx_fpa_poolx_threshold_cn61xx { 2339292068Ssjg#ifdef __BIG_ENDIAN_BITFIELD 2340292068Ssjg uint64_t reserved_29_63 : 35; 2341292068Ssjg uint64_t thresh : 29; /**< The Threshold. */ 2342236769Sobrien#else 2343292068Ssjg uint64_t thresh : 29; 2344292068Ssjg uint64_t reserved_29_63 : 35; 2345292068Ssjg#endif 2346236769Sobrien } cn61xx; 2347292068Ssjg struct cvmx_fpa_poolx_threshold_cn61xx cn63xx; 2348236769Sobrien struct cvmx_fpa_poolx_threshold_cn61xx cn66xx; 2349292068Ssjg struct cvmx_fpa_poolx_threshold_s cn68xx; 2350236769Sobrien struct cvmx_fpa_poolx_threshold_s cn68xxp1; 2351236769Sobrien struct cvmx_fpa_poolx_threshold_cn61xx cnf71xx; 2352236769Sobrien}; 2353236769Sobrientypedef union cvmx_fpa_poolx_threshold cvmx_fpa_poolx_threshold_t; 2354236769Sobrien 2355236769Sobrien/** 2356236769Sobrien * cvmx_fpa_que#_available 2357236769Sobrien * 2358236769Sobrien * FPA_QUEX_PAGES_AVAILABLE = FPA's Queue 0-7 Free Page Available Register 2359236769Sobrien * 2360236769Sobrien * The number of page pointers that are available in the FPA and local DRAM. 2361236769Sobrien */ 2362236769Sobrienunion cvmx_fpa_quex_available { 2363236769Sobrien uint64_t u64; 2364236769Sobrien struct cvmx_fpa_quex_available_s { 2365236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 2366236769Sobrien uint64_t reserved_32_63 : 32; 2367236769Sobrien uint64_t que_siz : 32; /**< The number of free pages available in this Queue. 2368236769Sobrien In PASS-1 this field was [25:0]. */ 2369236769Sobrien#else 2370236769Sobrien uint64_t que_siz : 32; 2371236769Sobrien uint64_t reserved_32_63 : 32; 2372236769Sobrien#endif 2373236769Sobrien } s; 2374236769Sobrien struct cvmx_fpa_quex_available_cn30xx { 2375236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 2376236769Sobrien uint64_t reserved_29_63 : 35; 2377236769Sobrien uint64_t que_siz : 29; /**< The number of free pages available in this Queue. */ 2378236769Sobrien#else 2379236769Sobrien uint64_t que_siz : 29; 2380292068Ssjg uint64_t reserved_29_63 : 35; 2381236769Sobrien#endif 2382236769Sobrien } cn30xx; 2383236769Sobrien struct cvmx_fpa_quex_available_cn30xx cn31xx; 2384236769Sobrien struct cvmx_fpa_quex_available_cn30xx cn38xx; 2385236769Sobrien struct cvmx_fpa_quex_available_cn30xx cn38xxp2; 2386236769Sobrien struct cvmx_fpa_quex_available_cn30xx cn50xx; 2387236769Sobrien struct cvmx_fpa_quex_available_cn30xx cn52xx; 2388236769Sobrien struct cvmx_fpa_quex_available_cn30xx cn52xxp1; 2389236769Sobrien struct cvmx_fpa_quex_available_cn30xx cn56xx; 2390236769Sobrien struct cvmx_fpa_quex_available_cn30xx cn56xxp1; 2391236769Sobrien struct cvmx_fpa_quex_available_cn30xx cn58xx; 2392236769Sobrien struct cvmx_fpa_quex_available_cn30xx cn58xxp1; 2393236769Sobrien struct cvmx_fpa_quex_available_cn30xx cn61xx; 2394236769Sobrien struct cvmx_fpa_quex_available_cn30xx cn63xx; 2395236769Sobrien struct cvmx_fpa_quex_available_cn30xx cn63xxp1; 2396236769Sobrien struct cvmx_fpa_quex_available_cn30xx cn66xx; 2397236769Sobrien struct cvmx_fpa_quex_available_s cn68xx; 2398236769Sobrien struct cvmx_fpa_quex_available_s cn68xxp1; 2399236769Sobrien struct cvmx_fpa_quex_available_cn30xx cnf71xx; 2400236769Sobrien}; 2401236769Sobrientypedef union cvmx_fpa_quex_available cvmx_fpa_quex_available_t; 2402236769Sobrien 2403236769Sobrien/** 2404236769Sobrien * cvmx_fpa_que#_page_index 2405236769Sobrien * 2406236769Sobrien * FPA_QUE0_PAGE_INDEX = FPA's Queue0 Page Index 2407236769Sobrien * 2408236769Sobrien * The present index page for queue 0 of the FPA, this is a PASS-2 register. 2409236769Sobrien * This number reflects the number of pages of pointers that have been written to memory 2410236769Sobrien * for this queue. 2411251422Ssjg */ 2412236769Sobrienunion cvmx_fpa_quex_page_index { 2413236769Sobrien uint64_t u64; 2414236769Sobrien struct cvmx_fpa_quex_page_index_s { 2415236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 2416236769Sobrien uint64_t reserved_25_63 : 39; 2417236769Sobrien uint64_t pg_num : 25; /**< Page number. */ 2418236769Sobrien#else 2419236769Sobrien uint64_t pg_num : 25; 2420236769Sobrien uint64_t reserved_25_63 : 39; 2421236769Sobrien#endif 2422236769Sobrien } s; 2423236769Sobrien struct cvmx_fpa_quex_page_index_s cn30xx; 2424236769Sobrien struct cvmx_fpa_quex_page_index_s cn31xx; 2425236769Sobrien struct cvmx_fpa_quex_page_index_s cn38xx; 2426236769Sobrien struct cvmx_fpa_quex_page_index_s cn38xxp2; 2427236769Sobrien struct cvmx_fpa_quex_page_index_s cn50xx; 2428321964Ssjg struct cvmx_fpa_quex_page_index_s cn52xx; 2429236769Sobrien struct cvmx_fpa_quex_page_index_s cn52xxp1; 2430236769Sobrien struct cvmx_fpa_quex_page_index_s cn56xx; 2431236769Sobrien struct cvmx_fpa_quex_page_index_s cn56xxp1; 2432321964Ssjg struct cvmx_fpa_quex_page_index_s cn58xx; 2433321964Ssjg struct cvmx_fpa_quex_page_index_s cn58xxp1; 2434236769Sobrien struct cvmx_fpa_quex_page_index_s cn61xx; 2435236769Sobrien struct cvmx_fpa_quex_page_index_s cn63xx; 2436236769Sobrien struct cvmx_fpa_quex_page_index_s cn63xxp1; 2437236769Sobrien struct cvmx_fpa_quex_page_index_s cn66xx; 2438236769Sobrien struct cvmx_fpa_quex_page_index_s cn68xx; 2439236769Sobrien struct cvmx_fpa_quex_page_index_s cn68xxp1; 2440236769Sobrien struct cvmx_fpa_quex_page_index_s cnf71xx; 2441236769Sobrien}; 2442236769Sobrientypedef union cvmx_fpa_quex_page_index cvmx_fpa_quex_page_index_t; 2443236769Sobrien 2444236769Sobrien/** 2445236769Sobrien * cvmx_fpa_que8_page_index 2446236769Sobrien * 2447236769Sobrien * FPA_QUE8_PAGE_INDEX = FPA's Queue7 Page Index 2448236769Sobrien * 2449236769Sobrien * The present index page for queue 7 of the FPA. 2450236769Sobrien * This number reflects the number of pages of pointers that have been written to memory 2451236769Sobrien * for this queue. 2452236769Sobrien * Because the address space is 38-bits the number of 128 byte pages could cause this register value to wrap. 2453236769Sobrien */ 2454236769Sobrienunion cvmx_fpa_que8_page_index { 2455236769Sobrien uint64_t u64; 2456236769Sobrien struct cvmx_fpa_que8_page_index_s { 2457236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 2458236769Sobrien uint64_t reserved_25_63 : 39; 2459236769Sobrien uint64_t pg_num : 25; /**< Page number. */ 2460236769Sobrien#else 2461236769Sobrien uint64_t pg_num : 25; 2462236769Sobrien uint64_t reserved_25_63 : 39; 2463236769Sobrien#endif 2464236769Sobrien } s; 2465236769Sobrien struct cvmx_fpa_que8_page_index_s cn68xx; 2466236769Sobrien struct cvmx_fpa_que8_page_index_s cn68xxp1; 2467236769Sobrien}; 2468236769Sobrientypedef union cvmx_fpa_que8_page_index cvmx_fpa_que8_page_index_t; 2469236769Sobrien 2470236769Sobrien/** 2471236769Sobrien * cvmx_fpa_que_act 2472236769Sobrien * 2473236769Sobrien * FPA_QUE_ACT = FPA's Queue# Actual Page Index 2474236769Sobrien * 2475236769Sobrien * When a INT_SUM[PERR#] occurs this will be latched with the value read from L2C. PASS-2 register. 2476236769Sobrien * This is latched on the first error and will not latch again unitl all errors are cleared. 2477236769Sobrien */ 2478236769Sobrienunion cvmx_fpa_que_act { 2479236769Sobrien uint64_t u64; 2480236769Sobrien struct cvmx_fpa_que_act_s { 2481236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 2482236769Sobrien uint64_t reserved_29_63 : 35; 2483236769Sobrien uint64_t act_que : 3; /**< FPA-queue-number read from memory. */ 2484236769Sobrien uint64_t act_indx : 26; /**< Page number read from memory. */ 2485236769Sobrien#else 2486236769Sobrien uint64_t act_indx : 26; 2487236769Sobrien uint64_t act_que : 3; 2488236769Sobrien uint64_t reserved_29_63 : 35; 2489236769Sobrien#endif 2490236769Sobrien } s; 2491236769Sobrien struct cvmx_fpa_que_act_s cn30xx; 2492236769Sobrien struct cvmx_fpa_que_act_s cn31xx; 2493236769Sobrien struct cvmx_fpa_que_act_s cn38xx; 2494236769Sobrien struct cvmx_fpa_que_act_s cn38xxp2; 2495236769Sobrien struct cvmx_fpa_que_act_s cn50xx; 2496236769Sobrien struct cvmx_fpa_que_act_s cn52xx; 2497236769Sobrien struct cvmx_fpa_que_act_s cn52xxp1; 2498236769Sobrien struct cvmx_fpa_que_act_s cn56xx; 2499236769Sobrien struct cvmx_fpa_que_act_s cn56xxp1; 2500236769Sobrien struct cvmx_fpa_que_act_s cn58xx; 2501236769Sobrien struct cvmx_fpa_que_act_s cn58xxp1; 2502236769Sobrien struct cvmx_fpa_que_act_s cn61xx; 2503236769Sobrien struct cvmx_fpa_que_act_s cn63xx; 2504236769Sobrien struct cvmx_fpa_que_act_s cn63xxp1; 2505236769Sobrien struct cvmx_fpa_que_act_s cn66xx; 2506236769Sobrien struct cvmx_fpa_que_act_s cn68xx; 2507236769Sobrien struct cvmx_fpa_que_act_s cn68xxp1; 2508236769Sobrien struct cvmx_fpa_que_act_s cnf71xx; 2509236769Sobrien}; 2510236769Sobrientypedef union cvmx_fpa_que_act cvmx_fpa_que_act_t; 2511236769Sobrien 2512236769Sobrien/** 2513236769Sobrien * cvmx_fpa_que_exp 2514236769Sobrien * 2515236769Sobrien * FPA_QUE_EXP = FPA's Queue# Expected Page Index 2516236769Sobrien * 2517236769Sobrien * When a INT_SUM[PERR#] occurs this will be latched with the expected value. PASS-2 register. 2518236769Sobrien * This is latched on the first error and will not latch again unitl all errors are cleared. 2519236769Sobrien */ 2520236769Sobrienunion cvmx_fpa_que_exp { 2521236769Sobrien uint64_t u64; 2522236769Sobrien struct cvmx_fpa_que_exp_s { 2523236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 2524236769Sobrien uint64_t reserved_29_63 : 35; 2525236769Sobrien uint64_t exp_que : 3; /**< Expected fpa-queue-number read from memory. */ 2526236769Sobrien uint64_t exp_indx : 26; /**< Expected page number read from memory. */ 2527236769Sobrien#else 2528236769Sobrien uint64_t exp_indx : 26; 2529236769Sobrien uint64_t exp_que : 3; 2530321964Ssjg uint64_t reserved_29_63 : 35; 2531321964Ssjg#endif 2532321964Ssjg } s; 2533236769Sobrien struct cvmx_fpa_que_exp_s cn30xx; 2534236769Sobrien struct cvmx_fpa_que_exp_s cn31xx; 2535236769Sobrien struct cvmx_fpa_que_exp_s cn38xx; 2536236769Sobrien struct cvmx_fpa_que_exp_s cn38xxp2; 2537321964Ssjg struct cvmx_fpa_que_exp_s cn50xx; 2538236769Sobrien struct cvmx_fpa_que_exp_s cn52xx; 2539236769Sobrien struct cvmx_fpa_que_exp_s cn52xxp1; 2540236769Sobrien struct cvmx_fpa_que_exp_s cn56xx; 2541236769Sobrien struct cvmx_fpa_que_exp_s cn56xxp1; 2542236769Sobrien struct cvmx_fpa_que_exp_s cn58xx; 2543236769Sobrien struct cvmx_fpa_que_exp_s cn58xxp1; 2544321964Ssjg struct cvmx_fpa_que_exp_s cn61xx; 2545236769Sobrien struct cvmx_fpa_que_exp_s cn63xx; 2546236769Sobrien struct cvmx_fpa_que_exp_s cn63xxp1; 2547236769Sobrien struct cvmx_fpa_que_exp_s cn66xx; 2548236769Sobrien struct cvmx_fpa_que_exp_s cn68xx; 2549236769Sobrien struct cvmx_fpa_que_exp_s cn68xxp1; 2550236769Sobrien struct cvmx_fpa_que_exp_s cnf71xx; 2551321964Ssjg}; 2552236769Sobrientypedef union cvmx_fpa_que_exp cvmx_fpa_que_exp_t; 2553236769Sobrien 2554236769Sobrien/** 2555236769Sobrien * cvmx_fpa_wart_ctl 2556236769Sobrien * 2557236769Sobrien * FPA_WART_CTL = FPA's WART Control 2558236769Sobrien * 2559236769Sobrien * Control and status for the WART block. 2560236769Sobrien */ 2561236769Sobrienunion cvmx_fpa_wart_ctl { 2562236769Sobrien uint64_t u64; 2563236769Sobrien struct cvmx_fpa_wart_ctl_s { 2564236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 2565236769Sobrien uint64_t reserved_16_63 : 48; 2566236769Sobrien uint64_t ctl : 16; /**< Control information. */ 2567236769Sobrien#else 2568236769Sobrien uint64_t ctl : 16; 2569236769Sobrien uint64_t reserved_16_63 : 48; 2570321964Ssjg#endif 2571236769Sobrien } s; 2572236769Sobrien struct cvmx_fpa_wart_ctl_s cn30xx; 2573236769Sobrien struct cvmx_fpa_wart_ctl_s cn31xx; 2574236769Sobrien struct cvmx_fpa_wart_ctl_s cn38xx; 2575236769Sobrien struct cvmx_fpa_wart_ctl_s cn38xxp2; 2576236769Sobrien struct cvmx_fpa_wart_ctl_s cn50xx; 2577236769Sobrien struct cvmx_fpa_wart_ctl_s cn52xx; 2578236769Sobrien struct cvmx_fpa_wart_ctl_s cn52xxp1; 2579236769Sobrien struct cvmx_fpa_wart_ctl_s cn56xx; 2580292068Ssjg struct cvmx_fpa_wart_ctl_s cn56xxp1; 2581236769Sobrien struct cvmx_fpa_wart_ctl_s cn58xx; 2582236769Sobrien struct cvmx_fpa_wart_ctl_s cn58xxp1; 2583236769Sobrien}; 2584236769Sobrientypedef union cvmx_fpa_wart_ctl cvmx_fpa_wart_ctl_t; 2585236769Sobrien 2586236769Sobrien/** 2587236769Sobrien * cvmx_fpa_wart_status 2588236769Sobrien * 2589236769Sobrien * FPA_WART_STATUS = FPA's WART Status 2590236769Sobrien * 2591236769Sobrien * Control and status for the WART block. 2592236769Sobrien */ 2593236769Sobrienunion cvmx_fpa_wart_status { 2594236769Sobrien uint64_t u64; 2595321964Ssjg struct cvmx_fpa_wart_status_s { 2596236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 2597321964Ssjg uint64_t reserved_32_63 : 32; 2598236769Sobrien uint64_t status : 32; /**< Status information. */ 2599292068Ssjg#else 2600236769Sobrien uint64_t status : 32; 2601236769Sobrien uint64_t reserved_32_63 : 32; 2602236769Sobrien#endif 2603292068Ssjg } s; 2604236769Sobrien struct cvmx_fpa_wart_status_s cn30xx; 2605236769Sobrien struct cvmx_fpa_wart_status_s cn31xx; 2606236769Sobrien struct cvmx_fpa_wart_status_s cn38xx; 2607236769Sobrien struct cvmx_fpa_wart_status_s cn38xxp2; 2608236769Sobrien struct cvmx_fpa_wart_status_s cn50xx; 2609236769Sobrien struct cvmx_fpa_wart_status_s cn52xx; 2610236769Sobrien struct cvmx_fpa_wart_status_s cn52xxp1; 2611236769Sobrien struct cvmx_fpa_wart_status_s cn56xx; 2612236769Sobrien struct cvmx_fpa_wart_status_s cn56xxp1; 2613236769Sobrien struct cvmx_fpa_wart_status_s cn58xx; 2614246223Ssjg struct cvmx_fpa_wart_status_s cn58xxp1; 2615246223Ssjg}; 2616236769Sobrientypedef union cvmx_fpa_wart_status cvmx_fpa_wart_status_t; 2617236769Sobrien 2618236769Sobrien/** 2619236769Sobrien * cvmx_fpa_wqe_threshold 2620236769Sobrien * 2621236769Sobrien * FPA_WQE_THRESHOLD = FPA's WQE Threshold 2622236769Sobrien * 2623236769Sobrien * When the value of FPA_QUE#_AVAILABLE[QUE_SIZ] (\# is determined by the value of IPD_WQE_FPA_QUEUE) is Less than the value of this 2624236769Sobrien * register a low pool count signal is sent to the PCIe packet instruction engine (to make it stop reading instructions) and to the 2625236769Sobrien * Packet-Arbiter informing it to not give grants to packets MAC with the exception of the PCIe MAC. 2626236769Sobrien */ 2627236769Sobrienunion cvmx_fpa_wqe_threshold { 2628236769Sobrien uint64_t u64; 2629236769Sobrien struct cvmx_fpa_wqe_threshold_s { 2630236769Sobrien#ifdef __BIG_ENDIAN_BITFIELD 2631236769Sobrien uint64_t reserved_32_63 : 32; 2632321964Ssjg uint64_t thresh : 32; /**< WQE Threshold. */ 2633236769Sobrien#else 2634236769Sobrien uint64_t thresh : 32; 2635236769Sobrien uint64_t reserved_32_63 : 32; 2636236769Sobrien#endif 2637236769Sobrien } s; 2638236769Sobrien struct cvmx_fpa_wqe_threshold_s cn61xx; 2639236769Sobrien struct cvmx_fpa_wqe_threshold_s cn63xx; 2640236769Sobrien struct cvmx_fpa_wqe_threshold_s cn66xx; 2641236769Sobrien struct cvmx_fpa_wqe_threshold_s cn68xx; 2642236769Sobrien struct cvmx_fpa_wqe_threshold_s cn68xxp1; 2643236769Sobrien struct cvmx_fpa_wqe_threshold_s cnf71xx; 2644236769Sobrien}; 2645236769Sobrientypedef union cvmx_fpa_wqe_threshold cvmx_fpa_wqe_threshold_t; 2646236769Sobrien 2647236769Sobrien#endif 2648236769Sobrien