cvmx-fpa-defs.h revision 215976
177807Sru/***********************license start*************** 277807Sru * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 377807Sru * reserved. 41590Srgrimes * 577807Sru * 677807Sru * Redistribution and use in source and binary forms, with or without 777807Sru * modification, are permitted provided that the following conditions are 877807Sru * met: 977807Sru * 1077807Sru * * Redistributions of source code must retain the above copyright 1177807Sru * notice, this list of conditions and the following disclaimer. 1277807Sru * 1377807Sru * * Redistributions in binary form must reproduce the above 1477807Sru * copyright notice, this list of conditions and the following 1577807Sru * disclaimer in the documentation and/or other materials provided 1677807Sru * with the distribution. 1777807Sru 1877807Sru * * Neither the name of Cavium Networks nor the names of 1977807Sru * its contributors may be used to endorse or promote products 2077807Sru * derived from this software without specific prior written 2177807Sru * permission. 2277807Sru 2377807Sru * This Software, including technical data, may be subject to U.S. export control 2477807Sru * laws, including the U.S. Export Administration Act and its associated 2577807Sru * regulations, and may be subject to export or import regulations in other 2677807Sru * countries. 2777807Sru 2877807Sru * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 2977807Sru * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 3077807Sru * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 3177807Sru * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 3277807Sru * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 3377807Sru * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 3477807Sru * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 3577807Sru * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 3677807Sru * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 3777807Sru * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 3877807Sru ***********************license end**************************************/ 3977807Sru 4077807Sru 4177807Sru/** 4277807Sru * cvmx-fpa-defs.h 4377807Sru * 4477807Sru * Configuration and status register (CSR) type definitions for 4577807Sru * Octeon fpa. 4677807Sru * 4777807Sru * This file is auto generated. Do not edit. 4877807Sru * 4977807Sru * <hr>$Revision$<hr> 5077807Sru * 5177807Sru */ 5277807Sru#ifndef __CVMX_FPA_TYPEDEFS_H__ 5377807Sru#define __CVMX_FPA_TYPEDEFS_H__ 5477807Sru 5577807Sru#define CVMX_FPA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E8ull)) 5677807Sru#define CVMX_FPA_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180028000050ull)) 5777807Sru#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 5877807Sru#define CVMX_FPA_FPF0_MARKS CVMX_FPA_FPF0_MARKS_FUNC() 5977807Srustatic inline uint64_t CVMX_FPA_FPF0_MARKS_FUNC(void) 6077807Sru{ 6177807Sru if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 6277807Sru cvmx_warn("CVMX_FPA_FPF0_MARKS not supported on this chip\n"); 6377807Sru return CVMX_ADD_IO_SEG(0x0001180028000000ull); 6477807Sru} 6577807Sru#else 6677807Sru#define CVMX_FPA_FPF0_MARKS (CVMX_ADD_IO_SEG(0x0001180028000000ull)) 6777807Sru#endif 6877807Sru#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 6977807Sru#define CVMX_FPA_FPF0_SIZE CVMX_FPA_FPF0_SIZE_FUNC() 7077807Srustatic inline uint64_t CVMX_FPA_FPF0_SIZE_FUNC(void) 7177807Sru{ 7277807Sru if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 7377807Sru cvmx_warn("CVMX_FPA_FPF0_SIZE not supported on this chip\n"); 7477807Sru return CVMX_ADD_IO_SEG(0x0001180028000058ull); 7577807Sru} 7677807Sru#else 7777807Sru#define CVMX_FPA_FPF0_SIZE (CVMX_ADD_IO_SEG(0x0001180028000058ull)) 7877807Sru#endif 7977807Sru#define CVMX_FPA_FPF1_MARKS CVMX_FPA_FPFX_MARKS(1) 8077807Sru#define CVMX_FPA_FPF2_MARKS CVMX_FPA_FPFX_MARKS(2) 8177807Sru#define CVMX_FPA_FPF3_MARKS CVMX_FPA_FPFX_MARKS(3) 8277807Sru#define CVMX_FPA_FPF4_MARKS CVMX_FPA_FPFX_MARKS(4) 8377807Sru#define CVMX_FPA_FPF5_MARKS CVMX_FPA_FPFX_MARKS(5) 8477807Sru#define CVMX_FPA_FPF6_MARKS CVMX_FPA_FPFX_MARKS(6) 8577807Sru#define CVMX_FPA_FPF7_MARKS CVMX_FPA_FPFX_MARKS(7) 8677807Sru#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 8777807Srustatic inline uint64_t CVMX_FPA_FPFX_MARKS(unsigned long offset) 8877807Sru{ 8977807Sru if (!( 9077807Sru (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) || 9177807Sru (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) || 9277807Sru (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7)))) || 9377807Sru (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 1) && (offset <= 7)))))) 9477807Sru cvmx_warn("CVMX_FPA_FPFX_MARKS(%lu) is invalid on this chip\n", offset); 9577807Sru return CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1; 9677807Sru} 9777807Sru#else 9877807Sru#define CVMX_FPA_FPFX_MARKS(offset) (CVMX_ADD_IO_SEG(0x0001180028000008ull) + ((offset) & 7) * 8 - 8*1) 9977807Sru#endif 10077807Sru#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 10177807Srustatic inline uint64_t CVMX_FPA_FPFX_SIZE(unsigned long offset) 10277807Sru{ 10377807Sru if (!( 10477807Sru (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 1) && (offset <= 7)))) || 10577807Sru (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 1) && (offset <= 7)))) || 10677807Sru (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 1) && (offset <= 7)))) || 10777807Sru (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 1) && (offset <= 7)))))) 10877807Sru cvmx_warn("CVMX_FPA_FPFX_SIZE(%lu) is invalid on this chip\n", offset); 10977807Sru return CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1; 11077807Sru} 11177807Sru#else 11277807Sru#define CVMX_FPA_FPFX_SIZE(offset) (CVMX_ADD_IO_SEG(0x0001180028000060ull) + ((offset) & 7) * 8 - 8*1) 11377807Sru#endif 11477807Sru#define CVMX_FPA_INT_ENB (CVMX_ADD_IO_SEG(0x0001180028000048ull)) 11577807Sru#define CVMX_FPA_INT_SUM (CVMX_ADD_IO_SEG(0x0001180028000040ull)) 11677807Sru#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 11777807Sru#define CVMX_FPA_PACKET_THRESHOLD CVMX_FPA_PACKET_THRESHOLD_FUNC() 11877807Srustatic inline uint64_t CVMX_FPA_PACKET_THRESHOLD_FUNC(void) 11977807Sru{ 12077807Sru if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 12177807Sru cvmx_warn("CVMX_FPA_PACKET_THRESHOLD not supported on this chip\n"); 12277807Sru return CVMX_ADD_IO_SEG(0x0001180028000460ull); 12377807Sru} 12477807Sru#else 12577807Sru#define CVMX_FPA_PACKET_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000460ull)) 12677807Sru#endif 12777807Sru#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 12877807Srustatic inline uint64_t CVMX_FPA_POOLX_THRESHOLD(unsigned long offset) 12977807Sru{ 13077807Sru if (!( 1311590Srgrimes (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 1321590Srgrimes cvmx_warn("CVMX_FPA_POOLX_THRESHOLD(%lu) is invalid on this chip\n", offset); 13377807Sru return CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 7) * 8; 13477807Sru} 13577807Sru#else 13677807Sru#define CVMX_FPA_POOLX_THRESHOLD(offset) (CVMX_ADD_IO_SEG(0x0001180028000140ull) + ((offset) & 7) * 8) 13777807Sru#endif 13877807Sru#define CVMX_FPA_QUE0_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(0) 13977807Sru#define CVMX_FPA_QUE1_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(1) 14077807Sru#define CVMX_FPA_QUE2_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(2) 14177807Sru#define CVMX_FPA_QUE3_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(3) 14277807Sru#define CVMX_FPA_QUE4_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(4) 14377807Sru#define CVMX_FPA_QUE5_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(5) 1441590Srgrimes#define CVMX_FPA_QUE6_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(6) 1451590Srgrimes#define CVMX_FPA_QUE7_PAGE_INDEX CVMX_FPA_QUEX_PAGE_INDEX(7) 14677807Sru#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 14777807Srustatic inline uint64_t CVMX_FPA_QUEX_AVAILABLE(unsigned long offset) 14877807Sru{ 14977807Sru if (!( 15077807Sru (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 15177807Sru (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 15277807Sru (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 15377807Sru (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 15477807Sru (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 15577807Sru (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 15677807Sru (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 15777807Sru (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 15877807Sru cvmx_warn("CVMX_FPA_QUEX_AVAILABLE(%lu) is invalid on this chip\n", offset); 15977807Sru return CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 7) * 8; 16077807Sru} 16177807Sru#else 16277807Sru#define CVMX_FPA_QUEX_AVAILABLE(offset) (CVMX_ADD_IO_SEG(0x0001180028000098ull) + ((offset) & 7) * 8) 16377807Sru#endif 16477807Sru#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 16577807Srustatic inline uint64_t CVMX_FPA_QUEX_PAGE_INDEX(unsigned long offset) 16677807Sru{ 16777807Sru if (!( 1681590Srgrimes (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 1691590Srgrimes (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 17027185Scharnier (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 17150477Speter (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 17277807Sru (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 17377807Sru (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 1741590Srgrimes (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 1751590Srgrimes (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 1761590Srgrimes cvmx_warn("CVMX_FPA_QUEX_PAGE_INDEX(%lu) is invalid on this chip\n", offset); 17727185Scharnier return CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8; 17811765Sache} 17927185Scharnier#else 18012317Sjoerg#define CVMX_FPA_QUEX_PAGE_INDEX(offset) (CVMX_ADD_IO_SEG(0x00011800280000F0ull) + ((offset) & 7) * 8) 18127185Scharnier#endif 18277807Sru#define CVMX_FPA_QUE_ACT (CVMX_ADD_IO_SEG(0x0001180028000138ull)) 18377807Sru#define CVMX_FPA_QUE_EXP (CVMX_ADD_IO_SEG(0x0001180028000130ull)) 1841590Srgrimes#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 18577807Sru#define CVMX_FPA_WART_CTL CVMX_FPA_WART_CTL_FUNC() 18677807Srustatic inline uint64_t CVMX_FPA_WART_CTL_FUNC(void) 1871590Srgrimes{ 18877807Sru if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 1891590Srgrimes cvmx_warn("CVMX_FPA_WART_CTL not supported on this chip\n"); 19077807Sru return CVMX_ADD_IO_SEG(0x00011800280000D8ull); 19177807Sru} 19277807Sru#else 19377807Sru#define CVMX_FPA_WART_CTL (CVMX_ADD_IO_SEG(0x00011800280000D8ull)) 19477807Sru#endif 1951590Srgrimes#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 19677807Sru#define CVMX_FPA_WART_STATUS CVMX_FPA_WART_STATUS_FUNC() 19777807Srustatic inline uint64_t CVMX_FPA_WART_STATUS_FUNC(void) 19877807Sru{ 19977807Sru if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))) 20077807Sru cvmx_warn("CVMX_FPA_WART_STATUS not supported on this chip\n"); 20181510Skris return CVMX_ADD_IO_SEG(0x00011800280000E0ull); 20277807Sru} 20377807Sru#else 2041590Srgrimes#define CVMX_FPA_WART_STATUS (CVMX_ADD_IO_SEG(0x00011800280000E0ull)) 20581701Sru#endif 20681701Sru#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 20781701Sru#define CVMX_FPA_WQE_THRESHOLD CVMX_FPA_WQE_THRESHOLD_FUNC() 20881701Srustatic inline uint64_t CVMX_FPA_WQE_THRESHOLD_FUNC(void) 20981701Sru{ 21081701Sru if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 21181701Sru cvmx_warn("CVMX_FPA_WQE_THRESHOLD not supported on this chip\n"); 21281701Sru return CVMX_ADD_IO_SEG(0x0001180028000468ull); 21381701Sru} 21477807Sru#else 2151590Srgrimes#define CVMX_FPA_WQE_THRESHOLD (CVMX_ADD_IO_SEG(0x0001180028000468ull)) 21677807Sru#endif 21777807Sru 21877807Sru/** 21977807Sru * cvmx_fpa_bist_status 22077807Sru * 22177807Sru * FPA_BIST_STATUS = BIST Status of FPA Memories 22281701Sru * 22377807Sru * The result of the BIST run on the FPA memories. 22477807Sru */ 2251590Srgrimesunion cvmx_fpa_bist_status 22677807Sru{ 22777807Sru uint64_t u64; 22877807Sru struct cvmx_fpa_bist_status_s 22977807Sru { 23077807Sru#if __BYTE_ORDER == __BIG_ENDIAN 23177807Sru uint64_t reserved_5_63 : 59; 23227185Scharnier uint64_t frd : 1; /**< fpa_frd memory bist status. */ 23377807Sru uint64_t fpf0 : 1; /**< fpa_fpf0 memory bist status. */ 23477807Sru uint64_t fpf1 : 1; /**< fpa_fpf1 memory bist status. */ 23577807Sru uint64_t ffr : 1; /**< fpa_ffr memory bist status. */ 23677807Sru uint64_t fdr : 1; /**< fpa_fdr memory bist status. */ 23777807Sru#else 23877807Sru uint64_t fdr : 1; 23977807Sru uint64_t ffr : 1; 24077807Sru uint64_t fpf1 : 1; 24177807Sru uint64_t fpf0 : 1; 24277807Sru uint64_t frd : 1; 24377807Sru uint64_t reserved_5_63 : 59; 24477807Sru#endif 24577807Sru } s; 24677807Sru struct cvmx_fpa_bist_status_s cn30xx; 24777807Sru struct cvmx_fpa_bist_status_s cn31xx; 24877807Sru struct cvmx_fpa_bist_status_s cn38xx; 24977807Sru struct cvmx_fpa_bist_status_s cn38xxp2; 2501590Srgrimes struct cvmx_fpa_bist_status_s cn50xx; 25127185Scharnier struct cvmx_fpa_bist_status_s cn52xx; 25277807Sru struct cvmx_fpa_bist_status_s cn52xxp1; 25377807Sru struct cvmx_fpa_bist_status_s cn56xx; 2541590Srgrimes struct cvmx_fpa_bist_status_s cn56xxp1; 25511765Sache struct cvmx_fpa_bist_status_s cn58xx; 25677807Sru struct cvmx_fpa_bist_status_s cn58xxp1; 2571590Srgrimes struct cvmx_fpa_bist_status_s cn63xx; 25877807Sru struct cvmx_fpa_bist_status_s cn63xxp1; 2591590Srgrimes}; 26077807Srutypedef union cvmx_fpa_bist_status cvmx_fpa_bist_status_t; 26177807Sru 26277807Sru/** 26377807Sru * cvmx_fpa_ctl_status 26477807Sru * 26577807Sru * FPA_CTL_STATUS = FPA's Control/Status Register 26677807Sru * 26777807Sru * The FPA's interrupt enable register. 26877807Sru */ 26977807Sruunion cvmx_fpa_ctl_status 27081701Sru{ 27177807Sru uint64_t u64; 27277807Sru struct cvmx_fpa_ctl_status_s 27377807Sru { 27477807Sru#if __BYTE_ORDER == __BIG_ENDIAN 27577807Sru uint64_t reserved_21_63 : 43; 27677807Sru uint64_t free_en : 1; /**< Enables the setting of the INT_SUM_[FREE*] bits. */ 27777807Sru uint64_t ret_off : 1; /**< When set NCB devices returning pointer will be 27877807Sru stalled. */ 27977807Sru uint64_t req_off : 1; /**< When set NCB devices requesting pointers will be 28077807Sru stalled. */ 28177807Sru uint64_t reset : 1; /**< When set causes a reset of the FPA with the 28277807Sru exception of the RSL. This is a PASS-2 field. */ 28377807Sru uint64_t use_ldt : 1; /**< When clear '0' the FPA will use LDT to load 28477807Sru pointers from the L2C. This is a PASS-2 field. */ 28577807Sru uint64_t use_stt : 1; /**< When clear '0' the FPA will use STT to store 28677807Sru pointers to the L2C. This is a PASS-2 field. */ 28777807Sru uint64_t enb : 1; /**< Must be set to 1 AFTER writing all config registers 28877807Sru and 10 cycles have past. If any of the config 28977807Sru register are written after writing this bit the 29077807Sru FPA may begin to operate incorrectly. */ 29177807Sru uint64_t mem1_err : 7; /**< Causes a flip of the ECC bit associated 38:32 29277807Sru respective to bit 6:0 of this field, for FPF 29377807Sru FIFO 1. */ 29477807Sru uint64_t mem0_err : 7; /**< Causes a flip of the ECC bit associated 38:32 29577807Sru respective to bit 6:0 of this field, for FPF 29677807Sru FIFO 0. */ 29777807Sru#else 29877807Sru uint64_t mem0_err : 7; 29977807Sru uint64_t mem1_err : 7; 30077807Sru uint64_t enb : 1; 30177807Sru uint64_t use_stt : 1; 30277807Sru uint64_t use_ldt : 1; 30377807Sru uint64_t reset : 1; 30477807Sru uint64_t req_off : 1; 30577807Sru uint64_t ret_off : 1; 30677807Sru uint64_t free_en : 1; 30777807Sru uint64_t reserved_21_63 : 43; 30877807Sru#endif 30977807Sru } s; 31077807Sru struct cvmx_fpa_ctl_status_cn30xx 31177807Sru { 31277807Sru#if __BYTE_ORDER == __BIG_ENDIAN 31377807Sru uint64_t reserved_18_63 : 46; 31477807Sru uint64_t reset : 1; /**< When set causes a reset of the FPA with the 31577807Sru exception of the RSL. */ 31677807Sru uint64_t use_ldt : 1; /**< When clear '0' the FPA will use LDT to load 31777807Sru pointers from the L2C. */ 31828478Sjlemon uint64_t use_stt : 1; /**< When clear '0' the FPA will use STT to store 31977807Sru pointers to the L2C. */ 3201590Srgrimes uint64_t enb : 1; /**< Must be set to 1 AFTER writing all config registers 32177807Sru and 10 cycles have past. If any of the config 32277807Sru register are written after writing this bit the 32377807Sru FPA may begin to operate incorrectly. */ 32477807Sru uint64_t mem1_err : 7; /**< Causes a flip of the ECC bit associated 38:32 32577807Sru respective to bit 6:0 of this field, for FPF 32677807Sru FIFO 1. */ 32777807Sru uint64_t mem0_err : 7; /**< Causes a flip of the ECC bit associated 38:32 32877807Sru respective to bit 6:0 of this field, for FPF 32977807Sru FIFO 0. */ 33077807Sru#else 33177807Sru uint64_t mem0_err : 7; 33277807Sru uint64_t mem1_err : 7; 33377807Sru uint64_t enb : 1; 33477807Sru uint64_t use_stt : 1; 33577807Sru uint64_t use_ldt : 1; 3368874Srgrimes uint64_t reset : 1; 33777807Sru uint64_t reserved_18_63 : 46; 33815344Ssmpatel#endif 33977807Sru } cn30xx; 34077807Sru struct cvmx_fpa_ctl_status_cn30xx cn31xx; 34177807Sru struct cvmx_fpa_ctl_status_cn30xx cn38xx; 34277807Sru struct cvmx_fpa_ctl_status_cn30xx cn38xxp2; 34377807Sru struct cvmx_fpa_ctl_status_cn30xx cn50xx; 34477807Sru struct cvmx_fpa_ctl_status_cn30xx cn52xx; 3451590Srgrimes struct cvmx_fpa_ctl_status_cn30xx cn52xxp1; 34677807Sru struct cvmx_fpa_ctl_status_cn30xx cn56xx; 34777807Sru struct cvmx_fpa_ctl_status_cn30xx cn56xxp1; 34877807Sru struct cvmx_fpa_ctl_status_cn30xx cn58xx; 34977807Sru struct cvmx_fpa_ctl_status_cn30xx cn58xxp1; 3501590Srgrimes struct cvmx_fpa_ctl_status_s cn63xx; 3511590Srgrimes struct cvmx_fpa_ctl_status_cn30xx cn63xxp1; 35277807Sru}; 3531590Srgrimestypedef union cvmx_fpa_ctl_status cvmx_fpa_ctl_status_t; 35477807Sru 35577807Sru/** 35677807Sru * cvmx_fpa_fpf#_marks 35777807Sru * 35877807Sru * FPA_FPF1_MARKS = FPA's Queue 1 Free Page FIFO Read Write Marks 35977807Sru * 36077807Sru * The high and low watermark register that determines when we write and read free pages from L2C 36177807Sru * for Queue 1. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value 3621590Srgrimes * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75) 3631590Srgrimes */ 36477807Sruunion cvmx_fpa_fpfx_marks 3651590Srgrimes{ 36677807Sru uint64_t u64; 36777807Sru struct cvmx_fpa_fpfx_marks_s 36877807Sru { 36977807Sru#if __BYTE_ORDER == __BIG_ENDIAN 37077807Sru uint64_t reserved_22_63 : 42; 37177807Sru uint64_t fpf_wr : 11; /**< When the number of free-page-pointers in a 3721590Srgrimes queue exceeds this value the FPA will write 37377807Sru 32-page-pointers of that queue to DRAM. 37477807Sru The MAX value for this field should be 37577807Sru FPA_FPF1_SIZE[FPF_SIZ]-2. */ 37677807Sru uint64_t fpf_rd : 11; /**< When the number of free-page-pointers in a 37777807Sru queue drops below this value and there are 37877807Sru free-page-pointers in DRAM, the FPA will 37977807Sru read one page (32 pointers) from DRAM. 38077807Sru This maximum value for this field should be 38177807Sru FPA_FPF1_SIZE[FPF_SIZ]-34. The min number 38277807Sru for this would be 16. */ 38377807Sru#else 38477807Sru uint64_t fpf_rd : 11; 38530009Sjoerg uint64_t fpf_wr : 11; 38677807Sru uint64_t reserved_22_63 : 42; 38777807Sru#endif 38877807Sru } s; 38977807Sru struct cvmx_fpa_fpfx_marks_s cn38xx; 39077807Sru struct cvmx_fpa_fpfx_marks_s cn38xxp2; 39177807Sru struct cvmx_fpa_fpfx_marks_s cn56xx; 39277807Sru struct cvmx_fpa_fpfx_marks_s cn56xxp1; 39377807Sru struct cvmx_fpa_fpfx_marks_s cn58xx; 39477807Sru struct cvmx_fpa_fpfx_marks_s cn58xxp1; 39577807Sru struct cvmx_fpa_fpfx_marks_s cn63xx; 39677807Sru struct cvmx_fpa_fpfx_marks_s cn63xxp1; 39777807Sru}; 39877807Srutypedef union cvmx_fpa_fpfx_marks cvmx_fpa_fpfx_marks_t; 39977807Sru 40077807Sru/** 40177807Sru * cvmx_fpa_fpf#_size 40277807Sru * 40377807Sru * FPA_FPFX_SIZE = FPA's Queue 1-7 Free Page FIFO Size 40477807Sru * 40577807Sru * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are 40677807Sru * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used. 40777807Sru * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048. 40877807Sru */ 40977807Sruunion cvmx_fpa_fpfx_size 41077807Sru{ 41177807Sru uint64_t u64; 41277807Sru struct cvmx_fpa_fpfx_size_s 41377807Sru { 41477807Sru#if __BYTE_ORDER == __BIG_ENDIAN 41577807Sru uint64_t reserved_11_63 : 53; 41677807Sru uint64_t fpf_siz : 11; /**< The number of entries assigned in the FPA FIFO 41777807Sru (used to hold page-pointers) for this Queue. 41877807Sru The value of this register must divisable by 2, 41977807Sru and the FPA will ignore bit [0] of this register. 42077807Sru The total of the FPF_SIZ field of the 8 (0-7) 42177807Sru FPA_FPF#_SIZE registers must not exceed 2048. 42277807Sru After writing this field the FPA will need 10 42377807Sru core clock cycles to be ready for operation. The 42477807Sru assignment of location in the FPA FIFO must 42577807Sru start with Queue 0, then 1, 2, etc. 42677807Sru The number of useable entries will be FPF_SIZ-2. */ 42777807Sru#else 42877807Sru uint64_t fpf_siz : 11; 42977807Sru uint64_t reserved_11_63 : 53; 4301590Srgrimes#endif 43177807Sru } s; 43277807Sru struct cvmx_fpa_fpfx_size_s cn38xx; 43377807Sru struct cvmx_fpa_fpfx_size_s cn38xxp2; 43477807Sru struct cvmx_fpa_fpfx_size_s cn56xx; 43577807Sru struct cvmx_fpa_fpfx_size_s cn56xxp1; 43677807Sru struct cvmx_fpa_fpfx_size_s cn58xx; 43777807Sru struct cvmx_fpa_fpfx_size_s cn58xxp1; 43877807Sru struct cvmx_fpa_fpfx_size_s cn63xx; 43977807Sru struct cvmx_fpa_fpfx_size_s cn63xxp1; 44077807Sru}; 44177807Srutypedef union cvmx_fpa_fpfx_size cvmx_fpa_fpfx_size_t; 44277807Sru 44377807Sru/** 44477807Sru * cvmx_fpa_fpf0_marks 44577807Sru * 44677807Sru * FPA_FPF0_MARKS = FPA's Queue 0 Free Page FIFO Read Write Marks 44777807Sru * 44877807Sru * The high and low watermark register that determines when we write and read free pages from L2C 44977807Sru * for Queue 0. The value of FPF_RD and FPF_WR should have at least a 33 difference. Recommend value 4501590Srgrimes * is FPF_RD == (FPA_FPF#_SIZE[FPF_SIZ] * .25) and FPF_WR == (FPA_FPF#_SIZE[FPF_SIZ] * .75) 4511590Srgrimes */ 45277807Sruunion cvmx_fpa_fpf0_marks 4531590Srgrimes{ 45477807Sru uint64_t u64; 45577807Sru struct cvmx_fpa_fpf0_marks_s 45677807Sru { 45777807Sru#if __BYTE_ORDER == __BIG_ENDIAN 45877807Sru uint64_t reserved_24_63 : 40; 45977807Sru uint64_t fpf_wr : 12; /**< When the number of free-page-pointers in a 4601590Srgrimes queue exceeds this value the FPA will write 46177807Sru 32-page-pointers of that queue to DRAM. 46277807Sru The MAX value for this field should be 46377807Sru FPA_FPF0_SIZE[FPF_SIZ]-2. */ 46477807Sru uint64_t fpf_rd : 12; /**< When the number of free-page-pointers in a 46577807Sru queue drops below this value and there are 4661590Srgrimes free-page-pointers in DRAM, the FPA will 46777807Sru read one page (32 pointers) from DRAM. 46877807Sru This maximum value for this field should be 46977807Sru FPA_FPF0_SIZE[FPF_SIZ]-34. The min number 47077807Sru for this would be 16. */ 47177807Sru#else 4721590Srgrimes uint64_t fpf_rd : 12; 4731590Srgrimes uint64_t fpf_wr : 12; 47477807Sru uint64_t reserved_24_63 : 40; 4751590Srgrimes#endif 47677807Sru } s; 47777807Sru struct cvmx_fpa_fpf0_marks_s cn38xx; 47877807Sru struct cvmx_fpa_fpf0_marks_s cn38xxp2; 47977807Sru struct cvmx_fpa_fpf0_marks_s cn56xx; 48077807Sru struct cvmx_fpa_fpf0_marks_s cn56xxp1; 48177807Sru struct cvmx_fpa_fpf0_marks_s cn58xx; 48277807Sru struct cvmx_fpa_fpf0_marks_s cn58xxp1; 48377807Sru struct cvmx_fpa_fpf0_marks_s cn63xx; 48477807Sru struct cvmx_fpa_fpf0_marks_s cn63xxp1; 4851590Srgrimes}; 4861590Srgrimestypedef union cvmx_fpa_fpf0_marks cvmx_fpa_fpf0_marks_t; 48777807Sru 4881590Srgrimes/** 48977807Sru * cvmx_fpa_fpf0_size 49077807Sru * 49177807Sru * FPA_FPF0_SIZE = FPA's Queue 0 Free Page FIFO Size 49277807Sru * 49377807Sru * The number of page pointers that will be kept local to the FPA for this Queue. FPA Queues are 49477807Sru * assigned in order from Queue 0 to Queue 7, though only Queue 0 through Queue x can be used. 49577807Sru * The sum of the 8 (0-7) FPA_FPF#_SIZE registers must be limited to 2048. 49677807Sru */ 49777807Sruunion cvmx_fpa_fpf0_size 4981590Srgrimes{ 4991590Srgrimes uint64_t u64; 50077807Sru struct cvmx_fpa_fpf0_size_s 50177807Sru { 50277807Sru#if __BYTE_ORDER == __BIG_ENDIAN 5031590Srgrimes uint64_t reserved_12_63 : 52; 50477807Sru uint64_t fpf_siz : 12; /**< The number of entries assigned in the FPA FIFO 50577807Sru (used to hold page-pointers) for this Queue. 50677807Sru The value of this register must divisable by 2, 50777807Sru and the FPA will ignore bit [0] of this register. 5081590Srgrimes The total of the FPF_SIZ field of the 8 (0-7) 50977807Sru FPA_FPF#_SIZE registers must not exceed 2048. 51077807Sru After writing this field the FPA will need 10 51177807Sru core clock cycles to be ready for operation. The 51277807Sru assignment of location in the FPA FIFO must 51377807Sru start with Queue 0, then 1, 2, etc. 51477807Sru The number of useable entries will be FPF_SIZ-2. */ 51577807Sru#else 5168874Srgrimes uint64_t fpf_siz : 12; 51777807Sru uint64_t reserved_12_63 : 52; 51877807Sru#endif 51977807Sru } s; 52077807Sru struct cvmx_fpa_fpf0_size_s cn38xx; 52177807Sru struct cvmx_fpa_fpf0_size_s cn38xxp2; 52277807Sru struct cvmx_fpa_fpf0_size_s cn56xx; 52377807Sru struct cvmx_fpa_fpf0_size_s cn56xxp1; 52477807Sru struct cvmx_fpa_fpf0_size_s cn58xx; 52577807Sru struct cvmx_fpa_fpf0_size_s cn58xxp1; 52677807Sru struct cvmx_fpa_fpf0_size_s cn63xx; 52777807Sru struct cvmx_fpa_fpf0_size_s cn63xxp1; 52877807Sru}; 52977807Srutypedef union cvmx_fpa_fpf0_size cvmx_fpa_fpf0_size_t; 53077807Sru 53177807Sru/** 53277807Sru * cvmx_fpa_int_enb 53377807Sru * 53477807Sru * FPA_INT_ENB = FPA's Interrupt Enable 53577807Sru * 53677807Sru * The FPA's interrupt enable register. 53778334Sjlemon */ 53877807Sruunion cvmx_fpa_int_enb 53977807Sru{ 54077807Sru uint64_t u64; 54177807Sru struct cvmx_fpa_int_enb_s 54277807Sru { 54377807Sru#if __BYTE_ORDER == __BIG_ENDIAN 54477807Sru uint64_t reserved_44_63 : 20; 54577807Sru uint64_t free7 : 1; /**< When set (1) and bit 43 of the FPA_INT_SUM 54677807Sru register is asserted the FPA will assert an 54777807Sru interrupt. */ 54877807Sru uint64_t free6 : 1; /**< When set (1) and bit 42 of the FPA_INT_SUM 54977807Sru register is asserted the FPA will assert an 55077807Sru interrupt. */ 55177807Sru uint64_t free5 : 1; /**< When set (1) and bit 41 of the FPA_INT_SUM 55277807Sru register is asserted the FPA will assert an 55377807Sru interrupt. */ 55477807Sru uint64_t free4 : 1; /**< When set (1) and bit 40 of the FPA_INT_SUM 55577807Sru register is asserted the FPA will assert an 55677807Sru interrupt. */ 55777807Sru uint64_t free3 : 1; /**< When set (1) and bit 39 of the FPA_INT_SUM 55877807Sru register is asserted the FPA will assert an 5591590Srgrimes interrupt. */ 5601590Srgrimes uint64_t free2 : 1; /**< When set (1) and bit 38 of the FPA_INT_SUM 56177807Sru register is asserted the FPA will assert an 56277807Sru interrupt. */ 5631590Srgrimes uint64_t free1 : 1; /**< When set (1) and bit 37 of the FPA_INT_SUM 56477807Sru register is asserted the FPA will assert an 56577807Sru interrupt. */ 56677807Sru uint64_t free0 : 1; /**< When set (1) and bit 36 of the FPA_INT_SUM 56777807Sru register is asserted the FPA will assert an 56877807Sru interrupt. */ 56977807Sru uint64_t pool7th : 1; /**< When set (1) and bit 35 of the FPA_INT_SUM 57077807Sru register is asserted the FPA will assert an 57177807Sru interrupt. */ 57277807Sru uint64_t pool6th : 1; /**< When set (1) and bit 34 of the FPA_INT_SUM 57377807Sru register is asserted the FPA will assert an 57477807Sru interrupt. */ 57577807Sru uint64_t pool5th : 1; /**< When set (1) and bit 33 of the FPA_INT_SUM 57677807Sru register is asserted the FPA will assert an 5771590Srgrimes interrupt. */ 5781590Srgrimes uint64_t pool4th : 1; /**< When set (1) and bit 32 of the FPA_INT_SUM 57977807Sru register is asserted the FPA will assert an 58077807Sru interrupt. */ 58177807Sru uint64_t pool3th : 1; /**< When set (1) and bit 31 of the FPA_INT_SUM 58277807Sru register is asserted the FPA will assert an 58377807Sru interrupt. */ 58477807Sru uint64_t pool2th : 1; /**< When set (1) and bit 30 of the FPA_INT_SUM 58577807Sru register is asserted the FPA will assert an 58677807Sru interrupt. */ 58777807Sru uint64_t pool1th : 1; /**< When set (1) and bit 29 of the FPA_INT_SUM 58877807Sru register is asserted the FPA will assert an 5891590Srgrimes interrupt. */ 59077807Sru uint64_t pool0th : 1; /**< When set (1) and bit 28 of the FPA_INT_SUM 59177807Sru register is asserted the FPA will assert an 59277807Sru interrupt. */ 59377807Sru uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 59477807Sru register is asserted the FPA will assert an 59577807Sru interrupt. */ 59677807Sru uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 5971590Srgrimes register is asserted the FPA will assert an 59877807Sru interrupt. */ 59977807Sru uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 60077807Sru register is asserted the FPA will assert an 60177807Sru interrupt. */ 60277807Sru uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 60377807Sru register is asserted the FPA will assert an 60477807Sru interrupt. */ 60577807Sru uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 60677807Sru register is asserted the FPA will assert an 60777807Sru interrupt. */ 60877807Sru uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 60977807Sru register is asserted the FPA will assert an 61077807Sru interrupt. */ 61177807Sru uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 61277807Sru register is asserted the FPA will assert an 61377807Sru interrupt. */ 6141590Srgrimes uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 6151590Srgrimes register is asserted the FPA will assert an 61677807Sru interrupt. */ 6171590Srgrimes uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 61877807Sru register is asserted the FPA will assert an 61977807Sru interrupt. */ 62077807Sru uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 62177807Sru register is asserted the FPA will assert an 62277807Sru interrupt. */ 6231590Srgrimes uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 624 register is asserted the FPA will assert an 625 interrupt. */ 626 uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 627 register is asserted the FPA will assert an 628 interrupt. */ 629 uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 630 register is asserted the FPA will assert an 631 interrupt. */ 632 uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 633 register is asserted the FPA will assert an 634 interrupt. */ 635 uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 636 register is asserted the FPA will assert an 637 interrupt. */ 638 uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 639 register is asserted the FPA will assert an 640 interrupt. */ 641 uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 642 register is asserted the FPA will assert an 643 interrupt. */ 644 uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 645 register is asserted the FPA will assert an 646 interrupt. */ 647 uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 648 register is asserted the FPA will assert an 649 interrupt. */ 650 uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 651 register is asserted the FPA will assert an 652 interrupt. */ 653 uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 654 register is asserted the FPA will assert an 655 interrupt. */ 656 uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 657 register is asserted the FPA will assert an 658 interrupt. */ 659 uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 660 register is asserted the FPA will assert an 661 interrupt. */ 662 uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 663 register is asserted the FPA will assert an 664 interrupt. */ 665 uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 666 register is asserted the FPA will assert an 667 interrupt. */ 668 uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 669 register is asserted the FPA will assert an 670 interrupt. */ 671 uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 672 register is asserted the FPA will assert an 673 interrupt. */ 674 uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 675 register is asserted the FPA will assert an 676 interrupt. */ 677#else 678 uint64_t fed0_sbe : 1; 679 uint64_t fed0_dbe : 1; 680 uint64_t fed1_sbe : 1; 681 uint64_t fed1_dbe : 1; 682 uint64_t q0_und : 1; 683 uint64_t q0_coff : 1; 684 uint64_t q0_perr : 1; 685 uint64_t q1_und : 1; 686 uint64_t q1_coff : 1; 687 uint64_t q1_perr : 1; 688 uint64_t q2_und : 1; 689 uint64_t q2_coff : 1; 690 uint64_t q2_perr : 1; 691 uint64_t q3_und : 1; 692 uint64_t q3_coff : 1; 693 uint64_t q3_perr : 1; 694 uint64_t q4_und : 1; 695 uint64_t q4_coff : 1; 696 uint64_t q4_perr : 1; 697 uint64_t q5_und : 1; 698 uint64_t q5_coff : 1; 699 uint64_t q5_perr : 1; 700 uint64_t q6_und : 1; 701 uint64_t q6_coff : 1; 702 uint64_t q6_perr : 1; 703 uint64_t q7_und : 1; 704 uint64_t q7_coff : 1; 705 uint64_t q7_perr : 1; 706 uint64_t pool0th : 1; 707 uint64_t pool1th : 1; 708 uint64_t pool2th : 1; 709 uint64_t pool3th : 1; 710 uint64_t pool4th : 1; 711 uint64_t pool5th : 1; 712 uint64_t pool6th : 1; 713 uint64_t pool7th : 1; 714 uint64_t free0 : 1; 715 uint64_t free1 : 1; 716 uint64_t free2 : 1; 717 uint64_t free3 : 1; 718 uint64_t free4 : 1; 719 uint64_t free5 : 1; 720 uint64_t free6 : 1; 721 uint64_t free7 : 1; 722 uint64_t reserved_44_63 : 20; 723#endif 724 } s; 725 struct cvmx_fpa_int_enb_cn30xx 726 { 727#if __BYTE_ORDER == __BIG_ENDIAN 728 uint64_t reserved_28_63 : 36; 729 uint64_t q7_perr : 1; /**< When set (1) and bit 27 of the FPA_INT_SUM 730 register is asserted the FPA will assert an 731 interrupt. */ 732 uint64_t q7_coff : 1; /**< When set (1) and bit 26 of the FPA_INT_SUM 733 register is asserted the FPA will assert an 734 interrupt. */ 735 uint64_t q7_und : 1; /**< When set (1) and bit 25 of the FPA_INT_SUM 736 register is asserted the FPA will assert an 737 interrupt. */ 738 uint64_t q6_perr : 1; /**< When set (1) and bit 24 of the FPA_INT_SUM 739 register is asserted the FPA will assert an 740 interrupt. */ 741 uint64_t q6_coff : 1; /**< When set (1) and bit 23 of the FPA_INT_SUM 742 register is asserted the FPA will assert an 743 interrupt. */ 744 uint64_t q6_und : 1; /**< When set (1) and bit 22 of the FPA_INT_SUM 745 register is asserted the FPA will assert an 746 interrupt. */ 747 uint64_t q5_perr : 1; /**< When set (1) and bit 21 of the FPA_INT_SUM 748 register is asserted the FPA will assert an 749 interrupt. */ 750 uint64_t q5_coff : 1; /**< When set (1) and bit 20 of the FPA_INT_SUM 751 register is asserted the FPA will assert an 752 interrupt. */ 753 uint64_t q5_und : 1; /**< When set (1) and bit 19 of the FPA_INT_SUM 754 register is asserted the FPA will assert an 755 interrupt. */ 756 uint64_t q4_perr : 1; /**< When set (1) and bit 18 of the FPA_INT_SUM 757 register is asserted the FPA will assert an 758 interrupt. */ 759 uint64_t q4_coff : 1; /**< When set (1) and bit 17 of the FPA_INT_SUM 760 register is asserted the FPA will assert an 761 interrupt. */ 762 uint64_t q4_und : 1; /**< When set (1) and bit 16 of the FPA_INT_SUM 763 register is asserted the FPA will assert an 764 interrupt. */ 765 uint64_t q3_perr : 1; /**< When set (1) and bit 15 of the FPA_INT_SUM 766 register is asserted the FPA will assert an 767 interrupt. */ 768 uint64_t q3_coff : 1; /**< When set (1) and bit 14 of the FPA_INT_SUM 769 register is asserted the FPA will assert an 770 interrupt. */ 771 uint64_t q3_und : 1; /**< When set (1) and bit 13 of the FPA_INT_SUM 772 register is asserted the FPA will assert an 773 interrupt. */ 774 uint64_t q2_perr : 1; /**< When set (1) and bit 12 of the FPA_INT_SUM 775 register is asserted the FPA will assert an 776 interrupt. */ 777 uint64_t q2_coff : 1; /**< When set (1) and bit 11 of the FPA_INT_SUM 778 register is asserted the FPA will assert an 779 interrupt. */ 780 uint64_t q2_und : 1; /**< When set (1) and bit 10 of the FPA_INT_SUM 781 register is asserted the FPA will assert an 782 interrupt. */ 783 uint64_t q1_perr : 1; /**< When set (1) and bit 9 of the FPA_INT_SUM 784 register is asserted the FPA will assert an 785 interrupt. */ 786 uint64_t q1_coff : 1; /**< When set (1) and bit 8 of the FPA_INT_SUM 787 register is asserted the FPA will assert an 788 interrupt. */ 789 uint64_t q1_und : 1; /**< When set (1) and bit 7 of the FPA_INT_SUM 790 register is asserted the FPA will assert an 791 interrupt. */ 792 uint64_t q0_perr : 1; /**< When set (1) and bit 6 of the FPA_INT_SUM 793 register is asserted the FPA will assert an 794 interrupt. */ 795 uint64_t q0_coff : 1; /**< When set (1) and bit 5 of the FPA_INT_SUM 796 register is asserted the FPA will assert an 797 interrupt. */ 798 uint64_t q0_und : 1; /**< When set (1) and bit 4 of the FPA_INT_SUM 799 register is asserted the FPA will assert an 800 interrupt. */ 801 uint64_t fed1_dbe : 1; /**< When set (1) and bit 3 of the FPA_INT_SUM 802 register is asserted the FPA will assert an 803 interrupt. */ 804 uint64_t fed1_sbe : 1; /**< When set (1) and bit 2 of the FPA_INT_SUM 805 register is asserted the FPA will assert an 806 interrupt. */ 807 uint64_t fed0_dbe : 1; /**< When set (1) and bit 1 of the FPA_INT_SUM 808 register is asserted the FPA will assert an 809 interrupt. */ 810 uint64_t fed0_sbe : 1; /**< When set (1) and bit 0 of the FPA_INT_SUM 811 register is asserted the FPA will assert an 812 interrupt. */ 813#else 814 uint64_t fed0_sbe : 1; 815 uint64_t fed0_dbe : 1; 816 uint64_t fed1_sbe : 1; 817 uint64_t fed1_dbe : 1; 818 uint64_t q0_und : 1; 819 uint64_t q0_coff : 1; 820 uint64_t q0_perr : 1; 821 uint64_t q1_und : 1; 822 uint64_t q1_coff : 1; 823 uint64_t q1_perr : 1; 824 uint64_t q2_und : 1; 825 uint64_t q2_coff : 1; 826 uint64_t q2_perr : 1; 827 uint64_t q3_und : 1; 828 uint64_t q3_coff : 1; 829 uint64_t q3_perr : 1; 830 uint64_t q4_und : 1; 831 uint64_t q4_coff : 1; 832 uint64_t q4_perr : 1; 833 uint64_t q5_und : 1; 834 uint64_t q5_coff : 1; 835 uint64_t q5_perr : 1; 836 uint64_t q6_und : 1; 837 uint64_t q6_coff : 1; 838 uint64_t q6_perr : 1; 839 uint64_t q7_und : 1; 840 uint64_t q7_coff : 1; 841 uint64_t q7_perr : 1; 842 uint64_t reserved_28_63 : 36; 843#endif 844 } cn30xx; 845 struct cvmx_fpa_int_enb_cn30xx cn31xx; 846 struct cvmx_fpa_int_enb_cn30xx cn38xx; 847 struct cvmx_fpa_int_enb_cn30xx cn38xxp2; 848 struct cvmx_fpa_int_enb_cn30xx cn50xx; 849 struct cvmx_fpa_int_enb_cn30xx cn52xx; 850 struct cvmx_fpa_int_enb_cn30xx cn52xxp1; 851 struct cvmx_fpa_int_enb_cn30xx cn56xx; 852 struct cvmx_fpa_int_enb_cn30xx cn56xxp1; 853 struct cvmx_fpa_int_enb_cn30xx cn58xx; 854 struct cvmx_fpa_int_enb_cn30xx cn58xxp1; 855 struct cvmx_fpa_int_enb_s cn63xx; 856 struct cvmx_fpa_int_enb_cn30xx cn63xxp1; 857}; 858typedef union cvmx_fpa_int_enb cvmx_fpa_int_enb_t; 859 860/** 861 * cvmx_fpa_int_sum 862 * 863 * FPA_INT_SUM = FPA's Interrupt Summary Register 864 * 865 * Contains the different interrupt summary bits of the FPA. 866 */ 867union cvmx_fpa_int_sum 868{ 869 uint64_t u64; 870 struct cvmx_fpa_int_sum_s 871 { 872#if __BYTE_ORDER == __BIG_ENDIAN 873 uint64_t reserved_44_63 : 20; 874 uint64_t free7 : 1; /**< When a pointer for POOL7 is freed bit is set. */ 875 uint64_t free6 : 1; /**< When a pointer for POOL6 is freed bit is set. */ 876 uint64_t free5 : 1; /**< When a pointer for POOL5 is freed bit is set. */ 877 uint64_t free4 : 1; /**< When a pointer for POOL4 is freed bit is set. */ 878 uint64_t free3 : 1; /**< When a pointer for POOL3 is freed bit is set. */ 879 uint64_t free2 : 1; /**< When a pointer for POOL2 is freed bit is set. */ 880 uint64_t free1 : 1; /**< When a pointer for POOL1 is freed bit is set. */ 881 uint64_t free0 : 1; /**< When a pointer for POOL0 is freed bit is set. */ 882 uint64_t pool7th : 1; /**< Set when FPA_QUE7_AVAILABLE is equal to 883 FPA_POOL7_THRESHOLD[THRESH] and a pointer is 884 allocated or de-allocated. */ 885 uint64_t pool6th : 1; /**< Set when FPA_QUE6_AVAILABLE is equal to 886 FPA_POOL6_THRESHOLD[THRESH] and a pointer is 887 allocated or de-allocated. */ 888 uint64_t pool5th : 1; /**< Set when FPA_QUE5_AVAILABLE is equal to 889 FPA_POOL5_THRESHOLD[THRESH] and a pointer is 890 allocated or de-allocated. */ 891 uint64_t pool4th : 1; /**< Set when FPA_QUE4_AVAILABLE is equal to 892 FPA_POOL4_THRESHOLD[THRESH] and a pointer is 893 allocated or de-allocated. */ 894 uint64_t pool3th : 1; /**< Set when FPA_QUE3_AVAILABLE is equal to 895 FPA_POOL3_THRESHOLD[THRESH] and a pointer is 896 allocated or de-allocated. */ 897 uint64_t pool2th : 1; /**< Set when FPA_QUE2_AVAILABLE is equal to 898 FPA_POOL2_THRESHOLD[THRESH] and a pointer is 899 allocated or de-allocated. */ 900 uint64_t pool1th : 1; /**< Set when FPA_QUE1_AVAILABLE is equal to 901 FPA_POOL1_THRESHOLD[THRESH] and a pointer is 902 allocated or de-allocated. */ 903 uint64_t pool0th : 1; /**< Set when FPA_QUE0_AVAILABLE is equal to 904 FPA_POOL`_THRESHOLD[THRESH] and a pointer is 905 allocated or de-allocated. */ 906 uint64_t q7_perr : 1; /**< Set when a Queue0 pointer read from the stack in 907 the L2C does not have the FPA owner ship bit set. */ 908 uint64_t q7_coff : 1; /**< Set when a Queue0 stack end tag is present and 909 the count available is greater than than pointers 910 present in the FPA. */ 911 uint64_t q7_und : 1; /**< Set when a Queue0 page count available goes 912 negative. */ 913 uint64_t q6_perr : 1; /**< Set when a Queue0 pointer read from the stack in 914 the L2C does not have the FPA owner ship bit set. */ 915 uint64_t q6_coff : 1; /**< Set when a Queue0 stack end tag is present and 916 the count available is greater than than pointers 917 present in the FPA. */ 918 uint64_t q6_und : 1; /**< Set when a Queue0 page count available goes 919 negative. */ 920 uint64_t q5_perr : 1; /**< Set when a Queue0 pointer read from the stack in 921 the L2C does not have the FPA owner ship bit set. */ 922 uint64_t q5_coff : 1; /**< Set when a Queue0 stack end tag is present and 923 the count available is greater than than pointers 924 present in the FPA. */ 925 uint64_t q5_und : 1; /**< Set when a Queue0 page count available goes 926 negative. */ 927 uint64_t q4_perr : 1; /**< Set when a Queue0 pointer read from the stack in 928 the L2C does not have the FPA owner ship bit set. */ 929 uint64_t q4_coff : 1; /**< Set when a Queue0 stack end tag is present and 930 the count available is greater than than pointers 931 present in the FPA. */ 932 uint64_t q4_und : 1; /**< Set when a Queue0 page count available goes 933 negative. */ 934 uint64_t q3_perr : 1; /**< Set when a Queue0 pointer read from the stack in 935 the L2C does not have the FPA owner ship bit set. */ 936 uint64_t q3_coff : 1; /**< Set when a Queue0 stack end tag is present and 937 the count available is greater than than pointers 938 present in the FPA. */ 939 uint64_t q3_und : 1; /**< Set when a Queue0 page count available goes 940 negative. */ 941 uint64_t q2_perr : 1; /**< Set when a Queue0 pointer read from the stack in 942 the L2C does not have the FPA owner ship bit set. */ 943 uint64_t q2_coff : 1; /**< Set when a Queue0 stack end tag is present and 944 the count available is greater than than pointers 945 present in the FPA. */ 946 uint64_t q2_und : 1; /**< Set when a Queue0 page count available goes 947 negative. */ 948 uint64_t q1_perr : 1; /**< Set when a Queue0 pointer read from the stack in 949 the L2C does not have the FPA owner ship bit set. */ 950 uint64_t q1_coff : 1; /**< Set when a Queue0 stack end tag is present and 951 the count available is greater than pointers 952 present in the FPA. */ 953 uint64_t q1_und : 1; /**< Set when a Queue0 page count available goes 954 negative. */ 955 uint64_t q0_perr : 1; /**< Set when a Queue0 pointer read from the stack in 956 the L2C does not have the FPA owner ship bit set. */ 957 uint64_t q0_coff : 1; /**< Set when a Queue0 stack end tag is present and 958 the count available is greater than pointers 959 present in the FPA. */ 960 uint64_t q0_und : 1; /**< Set when a Queue0 page count available goes 961 negative. */ 962 uint64_t fed1_dbe : 1; /**< Set when a Double Bit Error is detected in FPF1. */ 963 uint64_t fed1_sbe : 1; /**< Set when a Single Bit Error is detected in FPF1. */ 964 uint64_t fed0_dbe : 1; /**< Set when a Double Bit Error is detected in FPF0. */ 965 uint64_t fed0_sbe : 1; /**< Set when a Single Bit Error is detected in FPF0. */ 966#else 967 uint64_t fed0_sbe : 1; 968 uint64_t fed0_dbe : 1; 969 uint64_t fed1_sbe : 1; 970 uint64_t fed1_dbe : 1; 971 uint64_t q0_und : 1; 972 uint64_t q0_coff : 1; 973 uint64_t q0_perr : 1; 974 uint64_t q1_und : 1; 975 uint64_t q1_coff : 1; 976 uint64_t q1_perr : 1; 977 uint64_t q2_und : 1; 978 uint64_t q2_coff : 1; 979 uint64_t q2_perr : 1; 980 uint64_t q3_und : 1; 981 uint64_t q3_coff : 1; 982 uint64_t q3_perr : 1; 983 uint64_t q4_und : 1; 984 uint64_t q4_coff : 1; 985 uint64_t q4_perr : 1; 986 uint64_t q5_und : 1; 987 uint64_t q5_coff : 1; 988 uint64_t q5_perr : 1; 989 uint64_t q6_und : 1; 990 uint64_t q6_coff : 1; 991 uint64_t q6_perr : 1; 992 uint64_t q7_und : 1; 993 uint64_t q7_coff : 1; 994 uint64_t q7_perr : 1; 995 uint64_t pool0th : 1; 996 uint64_t pool1th : 1; 997 uint64_t pool2th : 1; 998 uint64_t pool3th : 1; 999 uint64_t pool4th : 1; 1000 uint64_t pool5th : 1; 1001 uint64_t pool6th : 1; 1002 uint64_t pool7th : 1; 1003 uint64_t free0 : 1; 1004 uint64_t free1 : 1; 1005 uint64_t free2 : 1; 1006 uint64_t free3 : 1; 1007 uint64_t free4 : 1; 1008 uint64_t free5 : 1; 1009 uint64_t free6 : 1; 1010 uint64_t free7 : 1; 1011 uint64_t reserved_44_63 : 20; 1012#endif 1013 } s; 1014 struct cvmx_fpa_int_sum_cn30xx 1015 { 1016#if __BYTE_ORDER == __BIG_ENDIAN 1017 uint64_t reserved_28_63 : 36; 1018 uint64_t q7_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1019 the L2C does not have the FPA owner ship bit set. */ 1020 uint64_t q7_coff : 1; /**< Set when a Queue0 stack end tag is present and 1021 the count available is greater than than pointers 1022 present in the FPA. */ 1023 uint64_t q7_und : 1; /**< Set when a Queue0 page count available goes 1024 negative. */ 1025 uint64_t q6_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1026 the L2C does not have the FPA owner ship bit set. */ 1027 uint64_t q6_coff : 1; /**< Set when a Queue0 stack end tag is present and 1028 the count available is greater than than pointers 1029 present in the FPA. */ 1030 uint64_t q6_und : 1; /**< Set when a Queue0 page count available goes 1031 negative. */ 1032 uint64_t q5_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1033 the L2C does not have the FPA owner ship bit set. */ 1034 uint64_t q5_coff : 1; /**< Set when a Queue0 stack end tag is present and 1035 the count available is greater than than pointers 1036 present in the FPA. */ 1037 uint64_t q5_und : 1; /**< Set when a Queue0 page count available goes 1038 negative. */ 1039 uint64_t q4_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1040 the L2C does not have the FPA owner ship bit set. */ 1041 uint64_t q4_coff : 1; /**< Set when a Queue0 stack end tag is present and 1042 the count available is greater than than pointers 1043 present in the FPA. */ 1044 uint64_t q4_und : 1; /**< Set when a Queue0 page count available goes 1045 negative. */ 1046 uint64_t q3_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1047 the L2C does not have the FPA owner ship bit set. */ 1048 uint64_t q3_coff : 1; /**< Set when a Queue0 stack end tag is present and 1049 the count available is greater than than pointers 1050 present in the FPA. */ 1051 uint64_t q3_und : 1; /**< Set when a Queue0 page count available goes 1052 negative. */ 1053 uint64_t q2_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1054 the L2C does not have the FPA owner ship bit set. */ 1055 uint64_t q2_coff : 1; /**< Set when a Queue0 stack end tag is present and 1056 the count available is greater than than pointers 1057 present in the FPA. */ 1058 uint64_t q2_und : 1; /**< Set when a Queue0 page count available goes 1059 negative. */ 1060 uint64_t q1_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1061 the L2C does not have the FPA owner ship bit set. */ 1062 uint64_t q1_coff : 1; /**< Set when a Queue0 stack end tag is present and 1063 the count available is greater than pointers 1064 present in the FPA. */ 1065 uint64_t q1_und : 1; /**< Set when a Queue0 page count available goes 1066 negative. */ 1067 uint64_t q0_perr : 1; /**< Set when a Queue0 pointer read from the stack in 1068 the L2C does not have the FPA owner ship bit set. */ 1069 uint64_t q0_coff : 1; /**< Set when a Queue0 stack end tag is present and 1070 the count available is greater than pointers 1071 present in the FPA. */ 1072 uint64_t q0_und : 1; /**< Set when a Queue0 page count available goes 1073 negative. */ 1074 uint64_t fed1_dbe : 1; /**< Set when a Double Bit Error is detected in FPF1. */ 1075 uint64_t fed1_sbe : 1; /**< Set when a Single Bit Error is detected in FPF1. */ 1076 uint64_t fed0_dbe : 1; /**< Set when a Double Bit Error is detected in FPF0. */ 1077 uint64_t fed0_sbe : 1; /**< Set when a Single Bit Error is detected in FPF0. */ 1078#else 1079 uint64_t fed0_sbe : 1; 1080 uint64_t fed0_dbe : 1; 1081 uint64_t fed1_sbe : 1; 1082 uint64_t fed1_dbe : 1; 1083 uint64_t q0_und : 1; 1084 uint64_t q0_coff : 1; 1085 uint64_t q0_perr : 1; 1086 uint64_t q1_und : 1; 1087 uint64_t q1_coff : 1; 1088 uint64_t q1_perr : 1; 1089 uint64_t q2_und : 1; 1090 uint64_t q2_coff : 1; 1091 uint64_t q2_perr : 1; 1092 uint64_t q3_und : 1; 1093 uint64_t q3_coff : 1; 1094 uint64_t q3_perr : 1; 1095 uint64_t q4_und : 1; 1096 uint64_t q4_coff : 1; 1097 uint64_t q4_perr : 1; 1098 uint64_t q5_und : 1; 1099 uint64_t q5_coff : 1; 1100 uint64_t q5_perr : 1; 1101 uint64_t q6_und : 1; 1102 uint64_t q6_coff : 1; 1103 uint64_t q6_perr : 1; 1104 uint64_t q7_und : 1; 1105 uint64_t q7_coff : 1; 1106 uint64_t q7_perr : 1; 1107 uint64_t reserved_28_63 : 36; 1108#endif 1109 } cn30xx; 1110 struct cvmx_fpa_int_sum_cn30xx cn31xx; 1111 struct cvmx_fpa_int_sum_cn30xx cn38xx; 1112 struct cvmx_fpa_int_sum_cn30xx cn38xxp2; 1113 struct cvmx_fpa_int_sum_cn30xx cn50xx; 1114 struct cvmx_fpa_int_sum_cn30xx cn52xx; 1115 struct cvmx_fpa_int_sum_cn30xx cn52xxp1; 1116 struct cvmx_fpa_int_sum_cn30xx cn56xx; 1117 struct cvmx_fpa_int_sum_cn30xx cn56xxp1; 1118 struct cvmx_fpa_int_sum_cn30xx cn58xx; 1119 struct cvmx_fpa_int_sum_cn30xx cn58xxp1; 1120 struct cvmx_fpa_int_sum_s cn63xx; 1121 struct cvmx_fpa_int_sum_cn30xx cn63xxp1; 1122}; 1123typedef union cvmx_fpa_int_sum cvmx_fpa_int_sum_t; 1124 1125/** 1126 * cvmx_fpa_packet_threshold 1127 * 1128 * FPA_PACKET_THRESHOLD = FPA's Packet Threshold 1129 * 1130 * When the value of FPA_QUE0_AVAILABLE[QUE_SIZ] is Less than the value of this register a low pool count signal is sent to the 1131 * PCIe packet instruction engine (to make it stop reading instructions) and to the Packet-Arbiter informing it to not give grants 1132 * to packets MAC with the exception of the PCIe MAC. 1133 */ 1134union cvmx_fpa_packet_threshold 1135{ 1136 uint64_t u64; 1137 struct cvmx_fpa_packet_threshold_s 1138 { 1139#if __BYTE_ORDER == __BIG_ENDIAN 1140 uint64_t reserved_32_63 : 32; 1141 uint64_t thresh : 32; /**< Packet Threshold. */ 1142#else 1143 uint64_t thresh : 32; 1144 uint64_t reserved_32_63 : 32; 1145#endif 1146 } s; 1147 struct cvmx_fpa_packet_threshold_s cn63xx; 1148}; 1149typedef union cvmx_fpa_packet_threshold cvmx_fpa_packet_threshold_t; 1150 1151/** 1152 * cvmx_fpa_pool#_threshold 1153 * 1154 * FPA_POOLX_THRESHOLD = FPA's Pool 0-7 Threshold 1155 * 1156 * When the value of FPA_QUEX_AVAILABLE is equal to FPA_POOLX_THRESHOLD[THRESH] when a pointer is allocated 1157 * or deallocated, set interrupt FPA_INT_SUM[POOLXTH]. 1158 */ 1159union cvmx_fpa_poolx_threshold 1160{ 1161 uint64_t u64; 1162 struct cvmx_fpa_poolx_threshold_s 1163 { 1164#if __BYTE_ORDER == __BIG_ENDIAN 1165 uint64_t reserved_29_63 : 35; 1166 uint64_t thresh : 29; /**< The Threshold. */ 1167#else 1168 uint64_t thresh : 29; 1169 uint64_t reserved_29_63 : 35; 1170#endif 1171 } s; 1172 struct cvmx_fpa_poolx_threshold_s cn63xx; 1173}; 1174typedef union cvmx_fpa_poolx_threshold cvmx_fpa_poolx_threshold_t; 1175 1176/** 1177 * cvmx_fpa_que#_available 1178 * 1179 * FPA_QUEX_PAGES_AVAILABLE = FPA's Queue 0-7 Free Page Available Register 1180 * 1181 * The number of page pointers that are available in the FPA and local DRAM. 1182 */ 1183union cvmx_fpa_quex_available 1184{ 1185 uint64_t u64; 1186 struct cvmx_fpa_quex_available_s 1187 { 1188#if __BYTE_ORDER == __BIG_ENDIAN 1189 uint64_t reserved_29_63 : 35; 1190 uint64_t que_siz : 29; /**< The number of free pages available in this Queue. 1191 In PASS-1 this field was [25:0]. */ 1192#else 1193 uint64_t que_siz : 29; 1194 uint64_t reserved_29_63 : 35; 1195#endif 1196 } s; 1197 struct cvmx_fpa_quex_available_s cn30xx; 1198 struct cvmx_fpa_quex_available_s cn31xx; 1199 struct cvmx_fpa_quex_available_s cn38xx; 1200 struct cvmx_fpa_quex_available_s cn38xxp2; 1201 struct cvmx_fpa_quex_available_s cn50xx; 1202 struct cvmx_fpa_quex_available_s cn52xx; 1203 struct cvmx_fpa_quex_available_s cn52xxp1; 1204 struct cvmx_fpa_quex_available_s cn56xx; 1205 struct cvmx_fpa_quex_available_s cn56xxp1; 1206 struct cvmx_fpa_quex_available_s cn58xx; 1207 struct cvmx_fpa_quex_available_s cn58xxp1; 1208 struct cvmx_fpa_quex_available_s cn63xx; 1209 struct cvmx_fpa_quex_available_s cn63xxp1; 1210}; 1211typedef union cvmx_fpa_quex_available cvmx_fpa_quex_available_t; 1212 1213/** 1214 * cvmx_fpa_que#_page_index 1215 * 1216 * FPA_QUE0_PAGE_INDEX = FPA's Queue0 Page Index 1217 * 1218 * The present index page for queue 0 of the FPA, this is a PASS-2 register. 1219 * This number reflects the number of pages of pointers that have been written to memory 1220 * for this queue. 1221 */ 1222union cvmx_fpa_quex_page_index 1223{ 1224 uint64_t u64; 1225 struct cvmx_fpa_quex_page_index_s 1226 { 1227#if __BYTE_ORDER == __BIG_ENDIAN 1228 uint64_t reserved_25_63 : 39; 1229 uint64_t pg_num : 25; /**< Page number. */ 1230#else 1231 uint64_t pg_num : 25; 1232 uint64_t reserved_25_63 : 39; 1233#endif 1234 } s; 1235 struct cvmx_fpa_quex_page_index_s cn30xx; 1236 struct cvmx_fpa_quex_page_index_s cn31xx; 1237 struct cvmx_fpa_quex_page_index_s cn38xx; 1238 struct cvmx_fpa_quex_page_index_s cn38xxp2; 1239 struct cvmx_fpa_quex_page_index_s cn50xx; 1240 struct cvmx_fpa_quex_page_index_s cn52xx; 1241 struct cvmx_fpa_quex_page_index_s cn52xxp1; 1242 struct cvmx_fpa_quex_page_index_s cn56xx; 1243 struct cvmx_fpa_quex_page_index_s cn56xxp1; 1244 struct cvmx_fpa_quex_page_index_s cn58xx; 1245 struct cvmx_fpa_quex_page_index_s cn58xxp1; 1246 struct cvmx_fpa_quex_page_index_s cn63xx; 1247 struct cvmx_fpa_quex_page_index_s cn63xxp1; 1248}; 1249typedef union cvmx_fpa_quex_page_index cvmx_fpa_quex_page_index_t; 1250 1251/** 1252 * cvmx_fpa_que_act 1253 * 1254 * FPA_QUE_ACT = FPA's Queue# Actual Page Index 1255 * 1256 * When a INT_SUM[PERR#] occurs this will be latched with the value read from L2C. PASS-2 register. 1257 * This is latched on the first error and will not latch again unitl all errors are cleared. 1258 */ 1259union cvmx_fpa_que_act 1260{ 1261 uint64_t u64; 1262 struct cvmx_fpa_que_act_s 1263 { 1264#if __BYTE_ORDER == __BIG_ENDIAN 1265 uint64_t reserved_29_63 : 35; 1266 uint64_t act_que : 3; /**< FPA-queue-number read from memory. */ 1267 uint64_t act_indx : 26; /**< Page number read from memory. */ 1268#else 1269 uint64_t act_indx : 26; 1270 uint64_t act_que : 3; 1271 uint64_t reserved_29_63 : 35; 1272#endif 1273 } s; 1274 struct cvmx_fpa_que_act_s cn30xx; 1275 struct cvmx_fpa_que_act_s cn31xx; 1276 struct cvmx_fpa_que_act_s cn38xx; 1277 struct cvmx_fpa_que_act_s cn38xxp2; 1278 struct cvmx_fpa_que_act_s cn50xx; 1279 struct cvmx_fpa_que_act_s cn52xx; 1280 struct cvmx_fpa_que_act_s cn52xxp1; 1281 struct cvmx_fpa_que_act_s cn56xx; 1282 struct cvmx_fpa_que_act_s cn56xxp1; 1283 struct cvmx_fpa_que_act_s cn58xx; 1284 struct cvmx_fpa_que_act_s cn58xxp1; 1285 struct cvmx_fpa_que_act_s cn63xx; 1286 struct cvmx_fpa_que_act_s cn63xxp1; 1287}; 1288typedef union cvmx_fpa_que_act cvmx_fpa_que_act_t; 1289 1290/** 1291 * cvmx_fpa_que_exp 1292 * 1293 * FPA_QUE_EXP = FPA's Queue# Expected Page Index 1294 * 1295 * When a INT_SUM[PERR#] occurs this will be latched with the expected value. PASS-2 register. 1296 * This is latched on the first error and will not latch again unitl all errors are cleared. 1297 */ 1298union cvmx_fpa_que_exp 1299{ 1300 uint64_t u64; 1301 struct cvmx_fpa_que_exp_s 1302 { 1303#if __BYTE_ORDER == __BIG_ENDIAN 1304 uint64_t reserved_29_63 : 35; 1305 uint64_t exp_que : 3; /**< Expected fpa-queue-number read from memory. */ 1306 uint64_t exp_indx : 26; /**< Expected page number read from memory. */ 1307#else 1308 uint64_t exp_indx : 26; 1309 uint64_t exp_que : 3; 1310 uint64_t reserved_29_63 : 35; 1311#endif 1312 } s; 1313 struct cvmx_fpa_que_exp_s cn30xx; 1314 struct cvmx_fpa_que_exp_s cn31xx; 1315 struct cvmx_fpa_que_exp_s cn38xx; 1316 struct cvmx_fpa_que_exp_s cn38xxp2; 1317 struct cvmx_fpa_que_exp_s cn50xx; 1318 struct cvmx_fpa_que_exp_s cn52xx; 1319 struct cvmx_fpa_que_exp_s cn52xxp1; 1320 struct cvmx_fpa_que_exp_s cn56xx; 1321 struct cvmx_fpa_que_exp_s cn56xxp1; 1322 struct cvmx_fpa_que_exp_s cn58xx; 1323 struct cvmx_fpa_que_exp_s cn58xxp1; 1324 struct cvmx_fpa_que_exp_s cn63xx; 1325 struct cvmx_fpa_que_exp_s cn63xxp1; 1326}; 1327typedef union cvmx_fpa_que_exp cvmx_fpa_que_exp_t; 1328 1329/** 1330 * cvmx_fpa_wart_ctl 1331 * 1332 * FPA_WART_CTL = FPA's WART Control 1333 * 1334 * Control and status for the WART block. 1335 */ 1336union cvmx_fpa_wart_ctl 1337{ 1338 uint64_t u64; 1339 struct cvmx_fpa_wart_ctl_s 1340 { 1341#if __BYTE_ORDER == __BIG_ENDIAN 1342 uint64_t reserved_16_63 : 48; 1343 uint64_t ctl : 16; /**< Control information. */ 1344#else 1345 uint64_t ctl : 16; 1346 uint64_t reserved_16_63 : 48; 1347#endif 1348 } s; 1349 struct cvmx_fpa_wart_ctl_s cn30xx; 1350 struct cvmx_fpa_wart_ctl_s cn31xx; 1351 struct cvmx_fpa_wart_ctl_s cn38xx; 1352 struct cvmx_fpa_wart_ctl_s cn38xxp2; 1353 struct cvmx_fpa_wart_ctl_s cn50xx; 1354 struct cvmx_fpa_wart_ctl_s cn52xx; 1355 struct cvmx_fpa_wart_ctl_s cn52xxp1; 1356 struct cvmx_fpa_wart_ctl_s cn56xx; 1357 struct cvmx_fpa_wart_ctl_s cn56xxp1; 1358 struct cvmx_fpa_wart_ctl_s cn58xx; 1359 struct cvmx_fpa_wart_ctl_s cn58xxp1; 1360}; 1361typedef union cvmx_fpa_wart_ctl cvmx_fpa_wart_ctl_t; 1362 1363/** 1364 * cvmx_fpa_wart_status 1365 * 1366 * FPA_WART_STATUS = FPA's WART Status 1367 * 1368 * Control and status for the WART block. 1369 */ 1370union cvmx_fpa_wart_status 1371{ 1372 uint64_t u64; 1373 struct cvmx_fpa_wart_status_s 1374 { 1375#if __BYTE_ORDER == __BIG_ENDIAN 1376 uint64_t reserved_32_63 : 32; 1377 uint64_t status : 32; /**< Status information. */ 1378#else 1379 uint64_t status : 32; 1380 uint64_t reserved_32_63 : 32; 1381#endif 1382 } s; 1383 struct cvmx_fpa_wart_status_s cn30xx; 1384 struct cvmx_fpa_wart_status_s cn31xx; 1385 struct cvmx_fpa_wart_status_s cn38xx; 1386 struct cvmx_fpa_wart_status_s cn38xxp2; 1387 struct cvmx_fpa_wart_status_s cn50xx; 1388 struct cvmx_fpa_wart_status_s cn52xx; 1389 struct cvmx_fpa_wart_status_s cn52xxp1; 1390 struct cvmx_fpa_wart_status_s cn56xx; 1391 struct cvmx_fpa_wart_status_s cn56xxp1; 1392 struct cvmx_fpa_wart_status_s cn58xx; 1393 struct cvmx_fpa_wart_status_s cn58xxp1; 1394}; 1395typedef union cvmx_fpa_wart_status cvmx_fpa_wart_status_t; 1396 1397/** 1398 * cvmx_fpa_wqe_threshold 1399 * 1400 * FPA_WQE_THRESHOLD = FPA's WQE Threshold 1401 * 1402 * When the value of FPA_QUE#_AVAILABLE[QUE_SIZ] (\# is determined by the value of IPD_WQE_FPA_QUEUE) is Less than the value of this 1403 * register a low pool count signal is sent to the PCIe packet instruction engine (to make it stop reading instructions) and to the 1404 * Packet-Arbiter informing it to not give grants to packets MAC with the exception of the PCIe MAC. 1405 */ 1406union cvmx_fpa_wqe_threshold 1407{ 1408 uint64_t u64; 1409 struct cvmx_fpa_wqe_threshold_s 1410 { 1411#if __BYTE_ORDER == __BIG_ENDIAN 1412 uint64_t reserved_32_63 : 32; 1413 uint64_t thresh : 32; /**< WQE Threshold. */ 1414#else 1415 uint64_t thresh : 32; 1416 uint64_t reserved_32_63 : 32; 1417#endif 1418 } s; 1419 struct cvmx_fpa_wqe_threshold_s cn63xx; 1420}; 1421typedef union cvmx_fpa_wqe_threshold cvmx_fpa_wqe_threshold_t; 1422 1423#endif 1424