cvmx-dma-engine.h revision 210284
1210284Sjmallett/***********************license start*************** 2210284Sjmallett * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3210284Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6210284Sjmallett * Redistribution and use in source and binary forms, with or without 7210284Sjmallett * modification, are permitted provided that the following conditions are 8210284Sjmallett * met: 9210284Sjmallett * 10210284Sjmallett * * Redistributions of source code must retain the above copyright 11210284Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13210284Sjmallett * * Redistributions in binary form must reproduce the above 14210284Sjmallett * copyright notice, this list of conditions and the following 15210284Sjmallett * disclaimer in the documentation and/or other materials provided 16210284Sjmallett * with the distribution. 17210284Sjmallett * 18210284Sjmallett * * Neither the name of Cavium Networks nor the names of 19210284Sjmallett * its contributors may be used to endorse or promote products 20210284Sjmallett * derived from this software without specific prior written 21210284Sjmallett * permission. 22210284Sjmallett * 23210284Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24210284Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25210284Sjmallett * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26210284Sjmallett * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27210284Sjmallett * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28210284Sjmallett * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29210284Sjmallett * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30210284Sjmallett * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31210284Sjmallett * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32210284Sjmallett * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33210284Sjmallett * 34210284Sjmallett * 35210284Sjmallett * For any questions regarding licensing please contact marketing@caviumnetworks.com 36210284Sjmallett * 37210284Sjmallett ***********************license end**************************************/ 38210284Sjmallett 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett/** 45210284Sjmallett * @file 46210284Sjmallett * 47210284Sjmallett * Interface to the PCI / PCIe DMA engines. These are only avialable 48210284Sjmallett * on chips with PCI / PCIe. 49210284Sjmallett * 50210284Sjmallett * <hr>$Revision: 41586 $<hr> 51210284Sjmallett */ 52210284Sjmallett 53210284Sjmallett#ifndef __CVMX_DMA_ENGINES_H__ 54210284Sjmallett#define __CVMX_DMA_ENGINES_H__ 55210284Sjmallett 56210284Sjmallett#ifdef __cplusplus 57210284Sjmallettextern "C" { 58210284Sjmallett#endif 59210284Sjmallett 60210284Sjmalletttypedef enum 61210284Sjmallett{ 62210284Sjmallett CVMX_DMA_ENGINE_TRANSFER_OUTBOUND = 0, /**< OUTBOUND (read from L2/DRAM, write into PCI / PCIe memory space) */ 63210284Sjmallett CVMX_DMA_ENGINE_TRANSFER_INBOUND = 1, /**< INBOUND (read from PCI / PCIe memory space, write into L2/DRAM) */ 64210284Sjmallett CVMX_DMA_ENGINE_TRANSFER_INTERNAL = 2, /**< INTERNAL-ONLY (read from L2/DRAM, write into L2/DRAM). Only available on chips with PCIe */ 65210284Sjmallett CVMX_DMA_ENGINE_TRANSFER_EXTERNAL = 3, /**< EXTERNAL-ONLY (read from PCIe memory space, write into PCIe memory space). Only available on chips with PCIe */ 66210284Sjmallett} cvmx_dma_engine_transfer_t; 67210284Sjmallett 68210284Sjmalletttypedef union 69210284Sjmallett{ 70210284Sjmallett uint64_t u64; 71210284Sjmallett struct 72210284Sjmallett { 73210284Sjmallett uint64_t reserved_60_63 : 4; /**< Must be zero */ 74210284Sjmallett uint64_t fport : 2; /**< First port. FPort indicates the physical PCIe port used for the 75210284Sjmallett PCIe memory space pointers in the FIRST POINTERS block in the 76210284Sjmallett EXTERNAL-ONLY case. Must be zero in the OUTBOUND, INBOUND and 77210284Sjmallett INTERNAL-ONLY cases. Must be zero on chips with PCI */ 78210284Sjmallett uint64_t lport : 2; /**< Last port. LPort indicates the physical PCIe port used for the 79210284Sjmallett PCIe memory space pointers in the LAST POINTERS block in the 80210284Sjmallett OUTBOUND, INBOUND, and EXTERNAL-ONLY cases. Must be zero in the 81210284Sjmallett INTERNAL-ONLY case. Must be zero on chips with PCI */ 82210284Sjmallett cvmx_dma_engine_transfer_t type : 2; /**< Type � A given PCI DMA transfer is either OUTBOUND (read from L2/DRAM, 83210284Sjmallett write into PCI / PCIe memory space), INBOUND (read from PCI / PCIe memory space, write 84210284Sjmallett into L2/DRAM), INTERNAL-ONLY (read from L2/DRAM, write into L2/DRAM), or 85210284Sjmallett EXTERNAL-ONLY (read from PCIe memory space, write into PCIe memory space). */ 86210284Sjmallett uint64_t wqp : 1; /**< Work-queue pointer. When WQP = 1, PTR (if non-zero) is a pointer to a 87210284Sjmallett work-queue entry that is submitted by the hardware after completing the DMA; 88210284Sjmallett when WQP = 0, PTR (if non-zero) is a pointer to a byte in local memory that 89210284Sjmallett is written to 0 by the hardware after completing the DMA. */ 90210284Sjmallett uint64_t c : 1; /**< C � Counter. 1 = use counter 1, 0 = use counter 0. 91210284Sjmallett The C bit selects between the two counters (NPEI_DMA_CNTS[DMA0,DMA1]) 92210284Sjmallett that can optionally be updated after an OUTBOUND or EXTERNAL-ONLY 93210284Sjmallett transfer, and also selects between the two forced-interrupt bits 94210284Sjmallett (NPEI_INT_SUMn[DMA0_FI, DMA1_FI]) that can optionally be set after an 95210284Sjmallett OUTBOUND or EXTERNAL-ONLY transfer. C must be zero for INBOUND or 96210284Sjmallett INTERNAL-ONLY transfers. */ 97210284Sjmallett uint64_t ca : 1; /**< CA � Counter add. 98210284Sjmallett When CA = 1, the hardware updates the selected counter after it completes the 99210284Sjmallett PCI DMA OUTBOUND or EXTERNAL-ONLY Instruction. 100210284Sjmallett - If C = 0, PCIE_DMA_CNT0 is updated 101210284Sjmallett - If C = 1, PCIE_DMA_CNT1 is updated. 102210284Sjmallett Note that this update may indirectly cause 103210284Sjmallett NPEI_INT_SUM[DCNT0,DCNT1,DTIME0,DTIME1] to become set (depending 104210284Sjmallett on the NPEI_DMA*_INT_LEVEL settings), so may cause interrupts to occur on a 105210284Sjmallett remote PCI host. 106210284Sjmallett - If NPEI_DMA_CONTROL[O_ADD1] = 1, the counter is updated by 1. 107210284Sjmallett - If NPEI_DMA_CONTROL[O_ADD1] = 0, the counter is updated by the total 108210284Sjmallett bytes in the transfer. 109210284Sjmallett When CA = 0, the hardware does not update any counters. 110210284Sjmallett For an INBOUND or INTERNAL-ONLY PCI DMA transfer, CA must never be 111210284Sjmallett set, and the hardware never adds to the counters. */ 112210284Sjmallett uint64_t fi : 1; /**< FI � Force interrupt. 113210284Sjmallett When FI is set for an OUTBOUND or EXTERNAL-ONLY transfer, the hardware 114210284Sjmallett sets a forced interrupt bit after it completes the PCI DMA Instruction. If C = 0, 115210284Sjmallett NPEI_INT_SUMn[DMA0_FI] is set, else NPEI_INT_SUMn[DMA1_FI] is set. For 116210284Sjmallett an INBOUND or INTERNAL-ONLY PCI DMA operation, FI must never be set, 117210284Sjmallett and the hardware never generates interrupts. */ 118210284Sjmallett uint64_t ii : 1; /**< II� Ignore the I bit (i.e. the I bit of the PCI DMA instruction local pointer). 119210284Sjmallett For OUTBOUND transfers when II = 1, ignore the I bit and the FL bit in the 120210284Sjmallett DMA HDR alone determines whether the hardware frees any/all of the local 121210284Sjmallett buffers in the FIRST POINTERS area: 122210284Sjmallett - when FL = 1, the hardware frees the local buffer when II=1. 123210284Sjmallett - when FL = 0, the hardware does not free the local buffer when II=1. 124210284Sjmallett For OUTBOUND transfers when II = 0, the I bit in the local pointer selects 125210284Sjmallett whether local buffers are freed on a pointer-by-pointer basis: 126210284Sjmallett - when (FL I) is true, the hardware frees the local buffer when II=0. 127210284Sjmallett For INBOUND, INTERNAL-ONLY, and EXTERNAL-ONLY PCI DMA transfers, 128210284Sjmallett II must never be set, and local buffers are never freed. */ 129210284Sjmallett uint64_t fl : 1; /**< FL � Free local buffer. 130210284Sjmallett When FL = 1, for an OUTBOUND operation, it indicates that the local buffers in 131210284Sjmallett the FIRST BUFFERS area should be freed. 132210284Sjmallett If II = 1, the FL bit alone indicates whether the local buffer should be freed: 133210284Sjmallett - when FL = 1, the hardware frees the local buffer when II=1. 134210284Sjmallett - when FL = 0, the hardware does not free the local buffer when II=1. 135210284Sjmallett If II = 0, the I bit in the local pointer (refer to Section 9.5.2) determines whether 136210284Sjmallett the local buffer is freed: 137210284Sjmallett - when (FL I) is true, the hardware frees the local buffer when II=0. 138210284Sjmallett For an INBOUND, INTERNAL-ONLY, or EXTERNAL-ONLY PCI DMA transfer, 139210284Sjmallett FL must never be set, and local buffers are never freed. */ 140210284Sjmallett uint64_t nlst : 4; /**< NLST � Number Last pointers. 141210284Sjmallett The number of pointers in the LAST POINTERS area. 142210284Sjmallett In the INBOUND, OUTBOUND, and EXTERNAL-ONLY cases, the LAST 143210284Sjmallett POINTERS area contains PCI components, and the number of 64-bit words 144210284Sjmallett required in the LAST POINTERS area is: 145210284Sjmallett - HDR.NLST + ((HDR.NLST + 3)/4) where the division removes the fraction. 146210284Sjmallett In the INTERNAL-ONLY case, the LAST POINTERS area contains local 147210284Sjmallett pointers, and the number of 64-bit words required in the LAST POINTERS area is: 148210284Sjmallett - HDR.NLST 149210284Sjmallett Note that the sum of the number of 64-bit words in the LAST POINTERS and 150210284Sjmallett FIRST POINTERS area must never exceed 31. */ 151210284Sjmallett uint64_t nfst : 4; /**< NFST � Number First pointers. 152210284Sjmallett The number of pointers in the FIRST POINTERS area. 153210284Sjmallett In the INBOUND, OUTBOUND, and INTERNAL-ONLY cases, the FIRST 154210284Sjmallett POINTERS area contains local pointers, and the number of 64-bit words required 155210284Sjmallett in the FIRST POINTERS area is: 156210284Sjmallett - HDR.NFST 157210284Sjmallett In the EXTERNAL-ONLY case, the FIRST POINTERS area contains PCI 158210284Sjmallett components, and the number of 64-bit words required in the FIRST POINTERS 159210284Sjmallett area is: 160210284Sjmallett - HDR.NFST + ((HDR.NFST + 3)/4) where the division removes the fraction. */ 161210284Sjmallett uint64_t addr : 40; /**< PTR � Pointer, either a work-queue-entry pointer (when WQP = 1) or a local 162210284Sjmallett memory pointer (WQP = 0). 163210284Sjmallett When WQP = 1 and PTR 0x0, the hardware inserts the work-queue entry 164210284Sjmallett indicated by PTR into a POW input queue after the PCI DMA operation is 165210284Sjmallett complete. (Section 5.4 describes the work queue entry requirements in this 166210284Sjmallett case.) When WQP = 1, PTR<2:0> must be 0x0. 167210284Sjmallett When WQP = 0 and PTR 0x0, the hardware writes the single byte in local 168210284Sjmallett memory indicated by PTR to 0x0 after the PCI DMA operation is complete. 169210284Sjmallett NPEI_DMA_CONTROL[B0_LEND] selects the endian-ness of PTR in this 170210284Sjmallett case. 171210284Sjmallett When PTR = 0x0, the hardware performs no operation after the PCI DMA 172210284Sjmallett operation is complete. */ 173210284Sjmallett } s; 174210284Sjmallett} cvmx_dma_engine_header_t; 175210284Sjmallett 176210284Sjmalletttypedef union 177210284Sjmallett{ 178210284Sjmallett uint64_t u64; 179210284Sjmallett struct 180210284Sjmallett { 181210284Sjmallett uint64_t i : 1; /**< I � Invert free. 182210284Sjmallett This bit gives the software the ability to free buffers independently for an 183210284Sjmallett OUTBOUND PCI DMA transfer. I is not used by the hardware when II is set. I 184210284Sjmallett must not be set, and buffers are never freed, for INBOUND, INTERNAL-ONLY, 185210284Sjmallett and EXTERNAL-ONLY PCI DMA transfers. */ 186210284Sjmallett uint64_t back : 4; /**< Back � Backup amount. 187210284Sjmallett Allows the start of a buffer that is to be freed during an OUTBOUND transfer to 188210284Sjmallett be different from the ptr value. Back specifies the amount to subtract from the 189210284Sjmallett pointer to reach the start when freeing a buffer. 190210284Sjmallett The address that is the start of the buffer being freed is: 191210284Sjmallett - Buffer start address = ((ptr >> 7) - Back) << 7. 192210284Sjmallett Back is only used by the hardware when the buffer corresponding to ptr is freed. 193210284Sjmallett Back must be 0x0, and buffers are never freed, for INBOUND, INTERNAL-ONLY, 194210284Sjmallett and EXTERNAL-ONLY PCI DMA transfers. */ 195210284Sjmallett uint64_t pool : 3; /**< Pool � Free pool. 196210284Sjmallett Specifies which pool (of the eight hardware-managed FPA free pools) receives the 197210284Sjmallett buffer associated with ptr when freed during an OUTBOUND transfer. 198210284Sjmallett Pool is only used when the buffer corresponding to ptr is freed. Pool must be 0x0, 199210284Sjmallett and buffers are never freed, for INBOUND, INTERNAL-ONLY, and EXTERNAL-ONLY 200210284Sjmallett PCI DMA transfers. */ 201210284Sjmallett uint64_t f : 1; /**< F � Full-block writes are allowed. 202210284Sjmallett When set, the hardware is permitted to write all the bytes in the cache blocks 203210284Sjmallett covered by ptr, ptr + Size - 1. This can improve memory system performance 204210284Sjmallett when the write misses in the L2 cache. 205210284Sjmallett F can only be set for local pointers that can be written to: 206210284Sjmallett - The local pointers in the FIRST POINTERS area that are write pointers for 207210284Sjmallett INBOUND transfers. 208210284Sjmallett - The local pointers in the LAST POINTERS area that are always write 209210284Sjmallett pointers (when present for INTERNAL-ONLY transfers). 210210284Sjmallett F must not be set for local pointers that are not written to: 211210284Sjmallett - The local pointers in the FIRST POINTERS area for OUTBOUND and 212210284Sjmallett INTERNAL-ONLY transfers. */ 213210284Sjmallett uint64_t a : 1; /**< A � Allocate L2. 214210284Sjmallett This is a hint to the hardware that the cache blocks should be allocated in the L2 215210284Sjmallett cache (if they were not already). */ 216210284Sjmallett uint64_t l : 1; /**< L � Little-endian. 217210284Sjmallett When L is set, the data at ptr is in little-endian format rather than big-endian. */ 218210284Sjmallett uint64_t size : 13; /**< Size � Size in bytes of the contiguous space specified by ptr. A Size value of 0 is 219210284Sjmallett illegal. Note that the sum of the sizes in the FIRST POINTERS area must always 220210284Sjmallett exactly equal the sum of the sizes/lengths in the LAST POINTERS area: 221210284Sjmallett - In the OUTBOUND and INBOUND cases, the HDR.NFST size fields in the 222210284Sjmallett local pointers in the FIRST POINTERS area must exactly equal the lengths 223210284Sjmallett of the HDR.NLST fragments in the PCI components in the LAST POINTERS 224210284Sjmallett area. 225210284Sjmallett - In the INTERNAL-ONLY case, the HDR.NFST size fields in the local 226210284Sjmallett pointers in the FIRST POINTERS area must equal the HDR.NLST size 227210284Sjmallett fields in the local pointers in the LAST POINTERS area. */ 228210284Sjmallett uint64_t reserved_36_39 : 4; /**< Must be zero */ 229210284Sjmallett uint64_t addr : 36; /**< L2/DRAM byte pointer. Points to where the packet data starts. 230210284Sjmallett Ptr can be any byte alignment. Note that ptr is interpreted as a big-endian byte 231210284Sjmallett pointer when L is clear, a little-endian byte pointer when L is set. */ 232210284Sjmallett } internal; 233210284Sjmallett struct 234210284Sjmallett { 235210284Sjmallett uint64_t len0 : 16; /**< Length of PCI / PCIe memory for address 0 */ 236210284Sjmallett uint64_t len1 : 16; /**< Length of PCI / PCIe memory for address 1 */ 237210284Sjmallett uint64_t len2 : 16; /**< Length of PCI / PCIe memory for address 2 */ 238210284Sjmallett uint64_t len3 : 16; /**< Length of PCI / PCIe memory for address 3 */ 239210284Sjmallett } pcie_length; 240210284Sjmallett} cvmx_dma_engine_buffer_t; 241210284Sjmallett 242210284Sjmallett/** 243210284Sjmallett * Initialize the DMA engines for use 244210284Sjmallett * 245210284Sjmallett * @return Zero on success, negative on failure 246210284Sjmallett */ 247210284Sjmallettint cvmx_dma_engine_initialize(void); 248210284Sjmallett 249210284Sjmallett/** 250210284Sjmallett * Shutdown all DMA engines. The engeines must be idle when this 251210284Sjmallett * function is called. 252210284Sjmallett * 253210284Sjmallett * @return Zero on success, negative on failure 254210284Sjmallett */ 255210284Sjmallettint cvmx_dma_engine_shutdown(void); 256210284Sjmallett 257210284Sjmallett/** 258210284Sjmallett * Return the number of DMA engimes supported by this chip 259210284Sjmallett * 260210284Sjmallett * @return Number of DMA engines 261210284Sjmallett */ 262210284Sjmallettint cvmx_dma_engine_get_num(void); 263210284Sjmallett 264210284Sjmallett/** 265210284Sjmallett * Submit a series of DMA comamnd to the DMA engines. 266210284Sjmallett * 267210284Sjmallett * @param engine Engine to submit to (0-4) 268210284Sjmallett * @param header Command header 269210284Sjmallett * @param num_buffers 270210284Sjmallett * The number of data pointers 271210284Sjmallett * @param buffers Comamnd data pointers 272210284Sjmallett * 273210284Sjmallett * @return Zero on success, negative on failure 274210284Sjmallett */ 275210284Sjmallettint cvmx_dma_engine_submit(int engine, cvmx_dma_engine_header_t header, int num_buffers, cvmx_dma_engine_buffer_t buffers[]); 276210284Sjmallett 277210284Sjmallett/** 278210284Sjmallett * Build the first and last pointers based on a DMA engine header 279210284Sjmallett * and submit them to the engine. The purpose of this function is 280210284Sjmallett * to simplify the building of DMA engine commands by automatically 281210284Sjmallett * converting a simple address and size into the apropriate internal 282210284Sjmallett * or PCI / PCIe address list. This function does not support gather lists, 283210284Sjmallett * so you will need to build your own lists in that case. 284210284Sjmallett * 285210284Sjmallett * @param engine Engine to submit to (0-4) 286210284Sjmallett * @param header DMA Command header. Note that the nfst and nlst fields do not 287210284Sjmallett * need to be filled in. All other fields must be set properly. 288210284Sjmallett * @param first_address 289210284Sjmallett * Address to use for the first pointers. In the case of INTERNAL, 290210284Sjmallett * INBOUND, and OUTBOUND this is an Octeon memory address. In the 291210284Sjmallett * case of EXTERNAL, this is the source PCI / PCIe address. 292210284Sjmallett * @param last_address 293210284Sjmallett * Address to use for the last pointers. In the case of EXTERNAL, 294210284Sjmallett * INBOUND, and OUTBOUND this is a PCI / PCIe address. In the 295210284Sjmallett * case of INTERNAL, this is the Octeon memory destination address. 296210284Sjmallett * @param size Size of the transfer to perform. 297210284Sjmallett * 298210284Sjmallett * @return Zero on success, negative on failure 299210284Sjmallett */ 300210284Sjmallettint cvmx_dma_engine_transfer(int engine, cvmx_dma_engine_header_t header, 301210284Sjmallett uint64_t first_address, uint64_t last_address, 302210284Sjmallett int size); 303210284Sjmallett 304210284Sjmallett/** 305210284Sjmallett * Simplified interface to the DMA engines to emulate memcpy() 306210284Sjmallett * 307210284Sjmallett * @param engine Engine to submit to (0-4) 308210284Sjmallett * @param dest Pointer to the destination memory. cvmx_ptr_to_phys() will be 309210284Sjmallett * used to turn this into a physical address. It cannot be a local 310210284Sjmallett * or CVMX_SHARED block. 311210284Sjmallett * @param source Pointer to the source memory. 312210284Sjmallett * cvmx_ptr_to_phys() will be used to turn this 313210284Sjmallett * into a physical address. It cannot be a local 314210284Sjmallett * or CVMX_SHARED block. 315210284Sjmallett * @param length Number of bytes to copy 316210284Sjmallett * 317210284Sjmallett * @return Zero on success, negative on failure 318210284Sjmallett */ 319210284Sjmallettstatic inline int cvmx_dma_engine_memcpy(int engine, void *dest, void *source, int length) 320210284Sjmallett{ 321210284Sjmallett cvmx_dma_engine_header_t header; 322210284Sjmallett header.u64 = 0; 323210284Sjmallett header.s.type = CVMX_DMA_ENGINE_TRANSFER_INTERNAL; 324210284Sjmallett return cvmx_dma_engine_transfer(engine, header, cvmx_ptr_to_phys(source), 325210284Sjmallett cvmx_ptr_to_phys(dest), length); 326210284Sjmallett} 327210284Sjmallett 328210284Sjmallett#ifdef __cplusplus 329210284Sjmallett} 330210284Sjmallett#endif 331210284Sjmallett 332210284Sjmallett#endif // __CVMX_CMD_QUEUE_H__ 333