cvmx-core.h revision 210284
1/***********************license start*************** 2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 * 23 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25 * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26 * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31 * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33 * 34 * 35 * For any questions regarding licensing please contact marketing@caviumnetworks.com 36 * 37 ***********************license end**************************************/ 38 39 40 41 42 43 44/** 45 * @file 46 * 47 * Module to support operations on core such as TLB config, etc. 48 * 49 * <hr>$Revision: 41586 $<hr> 50 * 51 */ 52 53 54#ifndef __CVMX_CORE_H__ 55#define __CVMX_CORE_H__ 56 57#ifdef __cplusplus 58extern "C" { 59#endif 60 61/** 62 * The types of performance counters supported per cpu 63 */ 64typedef enum 65{ 66 CVMX_CORE_PERF_NONE = 0, /**< Turn off the performance counter */ 67 CVMX_CORE_PERF_CLK = 1, /**< Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks) */ 68 CVMX_CORE_PERF_ISSUE = 2, /**< Instructions issued but not retired */ 69 CVMX_CORE_PERF_RET = 3, /**< Instructions retired */ 70 CVMX_CORE_PERF_NISSUE = 4, /**< Cycles no issue */ 71 CVMX_CORE_PERF_SISSUE = 5, /**< Cycles single issue */ 72 CVMX_CORE_PERF_DISSUE = 6, /**< Cycles dual issue */ 73 CVMX_CORE_PERF_IFI = 7, /**< Cycle ifetch issued (but not necessarily commit to pp_mem) */ 74 CVMX_CORE_PERF_BR = 8, /**< Branches retired */ 75 CVMX_CORE_PERF_BRMIS = 9, /**< Branch mispredicts */ 76 CVMX_CORE_PERF_J = 10, /**< Jumps retired */ 77 CVMX_CORE_PERF_JMIS = 11, /**< Jumps mispredicted */ 78 CVMX_CORE_PERF_REPLAY = 12, /**< Mem Replays */ 79 CVMX_CORE_PERF_IUNA = 13, /**< Cycles idle due to unaligned_replays */ 80 CVMX_CORE_PERF_TRAP = 14, /**< trap_6a signal */ 81 CVMX_CORE_PERF_UULOAD = 16, /**< Unexpected unaligned loads (REPUN=1) */ 82 CVMX_CORE_PERF_UUSTORE = 17, /**< Unexpected unaligned store (REPUN=1) */ 83 CVMX_CORE_PERF_ULOAD = 18, /**< Unaligned loads (REPUN=1 or USEUN=1) */ 84 CVMX_CORE_PERF_USTORE = 19, /**< Unaligned store (REPUN=1 or USEUN=1) */ 85 CVMX_CORE_PERF_EC = 20, /**< Exec clocks(must set CvmCtl[DISCE] for accurate timing) */ 86 CVMX_CORE_PERF_MC = 21, /**< Mul clocks(must set CvmCtl[DISCE] for accurate timing) */ 87 CVMX_CORE_PERF_CC = 22, /**< Crypto clocks(must set CvmCtl[DISCE] for accurate timing) */ 88 CVMX_CORE_PERF_CSRC = 23, /**< Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing) */ 89 CVMX_CORE_PERF_CFETCH = 24, /**< Icache committed fetches (demand+prefetch) */ 90 CVMX_CORE_PERF_CPREF = 25, /**< Icache committed prefetches */ 91 CVMX_CORE_PERF_ICA = 26, /**< Icache aliases */ 92 CVMX_CORE_PERF_II = 27, /**< Icache invalidates */ 93 CVMX_CORE_PERF_IP = 28, /**< Icache parity error */ 94 CVMX_CORE_PERF_CIMISS = 29, /**< Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing) */ 95 CVMX_CORE_PERF_WBUF = 32, /**< Number of write buffer entries created */ 96 CVMX_CORE_PERF_WDAT = 33, /**< Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts) */ 97 CVMX_CORE_PERF_WBUFLD = 34, /**< Number of write buffer entries forced out by loads */ 98 CVMX_CORE_PERF_WBUFFL = 35, /**< Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */ 99 CVMX_CORE_PERF_WBUFTR = 36, /**< Number of stores that found no available write buffer entries */ 100 CVMX_CORE_PERF_BADD = 37, /**< Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */ 101 CVMX_CORE_PERF_BADDL2 = 38, /**< Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts) */ 102 CVMX_CORE_PERF_BFILL = 39, /**< Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */ 103 CVMX_CORE_PERF_DDIDS = 40, /**< Number of Dstream DIDs created */ 104 CVMX_CORE_PERF_IDIDS = 41, /**< Number of Istream DIDs created */ 105 CVMX_CORE_PERF_DIDNA = 42, /**< Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */ 106 CVMX_CORE_PERF_LDS = 43, /**< Number of load issues */ 107 CVMX_CORE_PERF_LMLDS = 44, /**< Number of local memory load */ 108 CVMX_CORE_PERF_IOLDS = 45, /**< Number of I/O load issues */ 109 CVMX_CORE_PERF_DMLDS = 46, /**< Number of loads that were not prefetches and missed in the cache */ 110 CVMX_CORE_PERF_STS = 48, /**< Number of store issues */ 111 CVMX_CORE_PERF_LMSTS = 49, /**< Number of local memory store issues */ 112 CVMX_CORE_PERF_IOSTS = 50, /**< Number of I/O store issues */ 113 CVMX_CORE_PERF_IOBDMA = 51, /**< Number of IOBDMAs */ 114 CVMX_CORE_PERF_DTLB = 53, /**< Number of dstream TLB refill, invalid, or modified exceptions */ 115 CVMX_CORE_PERF_DTLBAD = 54, /**< Number of dstream TLB address errors */ 116 CVMX_CORE_PERF_ITLB = 55, /**< Number of istream TLB refill, invalid, or address error exceptions */ 117 CVMX_CORE_PERF_SYNC = 56, /**< Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */ 118 CVMX_CORE_PERF_SYNCIOB = 57, /**< Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */ 119 CVMX_CORE_PERF_SYNCW = 58, /**< Number of SYNCWs */ 120 CVMX_CORE_PERF_MAX /**< This not a counter, just a marker for the highest number */ 121} cvmx_core_perf_t; 122 123/** 124 * Bit description of the COP0 counter control register 125 */ 126typedef union 127{ 128 uint32_t u32; 129 struct 130 { 131 uint32_t m : 1; /**< Set to 1 for sel 0 and 0 for sel 2, indicating there are two performance counters */ 132 uint32_t w : 1; /**< Set to 1 indicating coutners are 64 bit */ 133 uint32_t reserved_11_29 :19; 134 cvmx_core_perf_t event : 6; /**< Selects the event to be counted by the corresponding Counter Register */ 135 uint32_t ie : 1; /**< Count in interrupt context */ 136 uint32_t u : 1; /**< Count in user mode */ 137 uint32_t s : 1; /**< Count in supervisor mode */ 138 uint32_t k : 1; /**< Count in kernel mode */ 139 uint32_t ex : 1; /**< Count in exception context */ 140 } s; 141} cvmx_core_perf_control_t; 142 143typedef enum { 144 CVMX_TLB_PAGEMASK_4K = 0x3 << 11, 145 CVMX_TLB_PAGEMASK_16K = 0xF << 11, 146 CVMX_TLB_PAGEMASK_64K = 0x3F << 11, 147 CVMX_TLB_PAGEMASK_256K = 0xFF << 11, 148 CVMX_TLB_PAGEMASK_1M = 0x3FF << 11, 149 CVMX_TLB_PAGEMASK_4M = 0xFFF << 11, 150 CVMX_TLB_PAGEMASK_16M = 0x3FFF << 11, 151 CVMX_TLB_PAGEMASK_64M = 0xFFFF << 11, 152 CVMX_TLB_PAGEMASK_256M = 0x3FFFF << 11, 153} cvmx_tlb_pagemask_t; 154 155 156int cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask); 157 158 159int cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask); 160int cvmx_core_add_fixed_tlb_mapping_bits(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask); 161 162#ifdef __cplusplus 163} 164#endif 165 166#endif /* __CVMX_CORE_H__ */ 167