cvmx-clock.c revision 215990 
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44
45
46/**
47 * @file
48 *
49 * Interface to Core, IO and DDR Clock.
50 *
51 * <hr>$Revision: 45089 $<hr>
52*/
53
54#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
55#include <linux/module.h>
56#include <asm/octeon/octeon.h>
57#include <asm/octeon/cvmx-clock.h>
58#include <asm/octeon/cvmx-npei-defs.h>
59#include <asm/octeon/cvmx-pexp-defs.h>
60#include <asm/octeon/cvmx-dbg-defs.h>
61#else
62#if !defined(__FreeBSD__) || !defined(_KERNEL)
63#include "executive-config.h"
64#endif
65#include "cvmx.h"
66#endif
67
68#ifndef CVMX_BUILD_FOR_UBOOT
69static uint64_t rate_eclk = 0;
70static uint64_t rate_sclk = 0;
71static uint64_t rate_dclk = 0;
72#endif
73
74/**
75 * Get clock rate based on the clock type.
76 *
77 * @param clock - Enumeration of the clock type.
78 * @return      - return the clock rate.
79 */
80uint64_t cvmx_clock_get_rate(cvmx_clock_t clock)
81{
82    const uint64_t REF_CLOCK = 50000000;
83
84#ifdef CVMX_BUILD_FOR_UBOOT
85    uint64_t rate_eclk = 0;
86    uint64_t rate_sclk = 0;
87    uint64_t rate_dclk = 0;
88#endif
89
90    if (cvmx_unlikely(!rate_eclk))
91    {
92        if (octeon_has_feature(OCTEON_FEATURE_NPEI))
93        {
94            cvmx_npei_dbg_data_t npei_dbg_data;
95            npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
96            rate_eclk =  REF_CLOCK * npei_dbg_data.s.c_mul;
97            rate_sclk = rate_eclk;
98        }
99        else if (octeon_has_feature(OCTEON_FEATURE_PCIE))
100        {
101            cvmx_mio_rst_boot_t mio_rst_boot;
102            mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
103            rate_eclk =  REF_CLOCK * mio_rst_boot.s.c_mul;
104            rate_sclk = REF_CLOCK * mio_rst_boot.s.pnr_mul;
105        }
106        else
107        {
108            cvmx_dbg_data_t dbg_data;
109            dbg_data.u64 = cvmx_read_csr(CVMX_DBG_DATA);
110            rate_eclk =  REF_CLOCK * dbg_data.s.c_mul;
111            rate_sclk = rate_eclk;
112        }
113    }
114
115    switch (clock)
116    {
117        case CVMX_CLOCK_SCLK:
118        case CVMX_CLOCK_TIM:
119        case CVMX_CLOCK_IPD:
120            return rate_sclk;
121
122        case CVMX_CLOCK_RCLK:
123        case CVMX_CLOCK_CORE:
124            return rate_eclk;
125
126        case CVMX_CLOCK_DDR:
127#if !defined(CVMX_BUILD_FOR_LINUX_HOST) && !defined(__OCTEON_NEWLIB__)
128            if (cvmx_unlikely(!rate_dclk))
129                rate_dclk = cvmx_sysinfo_get()->dram_data_rate_hz;
130#endif
131            return rate_dclk;
132    }
133
134    cvmx_dprintf("cvmx_clock_get_rate: Unknown clock type\n");
135    return 0;
136}
137#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
138EXPORT_SYMBOL(cvmx_clock_get_rate);
139#endif
140